The minimum detectable input pulse Width is 3uSec.
The 3us minimum pulse width comes from 2us input filter delay, and 1us sampling delay due to 1MHz sampling rate.
The internal sampling and comparator are working continuously no matter LATCH\\ or CS\\ is high or low. The analog front end always looks at the input and updates the internal DI data value. The LATCH\\ and CS\\ going low freezes the data register value so it is ready to be read by SPI master. If you keep LATCH\\ or CS\\ always low, then you will be reading the last value before LATCH\\ or CS\\ going high. You need to issue a falling edge on LATCH\\ or CS\\ before reading the up-to-date DI value.