If this situation occurs, normal operation can be resumed by performing a Power on reset (POR), cold reset or warm reset of the HPS, which causes the HPS to relinquish control of the CSS and gives control back to the FPGA.    If you are not using secure boot, you can avoid this issue by ensuring that software executing after the boot ROM stage relinquishes HPS control of the CSS after a reset to let the FPGA proceed to take ownership of the CSS block.  It is important that the HPS is not held in cold or warm reset indefinitely, otherwise the CSS will not be accessible to FPGA configuration sources.
This information is scheduled to be included in a future release of the Arria 10 Technical Referenece Manual.