The most beneficial method is to reduce the number of test points by creating a “net” test or testing only the unique nodes on the circuit.
This eliminates any redundant re-testing of component pins. Generally, CAD data or schematics are necessary to create a net test.
Other things that can be done to reduce test time is to decrease the number of test ranges used (though we recommend using at least two), disabling the “Z
Home between Components” in the Sequence settings and grouping small discrete components into one component test. Increasing the test range frequency to 200Hz or
higher will also result in shorter test times.
More suggestions such as probe position optimization are available in the Technical Support Quick Tips