This is totally dependent upon the complexity of the design that is to be commenced. Adding RF, micros and memory all adds to the engineering time needed to complete the project. The more complex the design may also mean that a higher speed process may be required. Generally, the lower geometry process that is used for the ASIC usually means that the tooling costs are increased. Therefore a simple design on a 0.6µm CMOS will cost less than a design on a 0.18µm BiCMOS SiGe process. Swindon guides our customers through this process and advises on the optimal process to choose to ensure that the result is an ASIC that provides the customer with the best performance versus price versus size, that is achievable.