The market always pushes towards building fast chips that can perform multiple operations at once; therefore, industry leaders are required to construct complex chip designs operating at very high frequencies. However, extracting these parasitic effects of the chip results in a gigantic circuit that contains a large number of parasitic instances, and it becomes hard and sometimes impossible to simulate this huge circuit to study delay, noise, power consumption, and other important analyses.
Reducing this gigantic circuit to a small one while preserving all of its properties and characteristics is the function of “Model Order Reduction (MOR).” MOReal is a MOR tool that can reduce large circuits full of parasitic instances to a smaller circuit ready for post-layout simulations and analyses. As an example, please, refer to the next figure.