Historically, when you see advancements in semiconductor performance, it was frequently done through the miniaturization of die through front end manufacturing improvements and shrinking process nodes. But semiconductors are starting to reach the limit of improvements in front end manufacturing. Cost is the primary limitation today, but the physics of fitting more transistors in the space available is starting to show diminishing returns.
Beginning with single-chip package architecture, increased semiconductor die sizes were the first evolution with monolithic silicon chips. The aim was do more on one chip in less space. However, larger silicon and more delicate active layers led to reduced product reliability. It also led to increased difficulty characterizing the product using existing packaging methods. Silicon turns are also very costly, making this progression unappealing for die sizes approaching 20mm.
The second architecture iteration was the beginning of what the industry is calling “disaggregation” or splitting out of various functions into multiple die. The concept of multi-chip modules is not new but is being revisited in support of CSWaP objectives. This package style is common in industry today and facilitates more effective product optimization during development and flexibility down the line. We have several multi-chip module (MCM) style products from external customers in active production today.
The third iteration, titled 2.5D heterogeneous integration, leverages semiconductor technology and disaggregation to do more in less space by adding another interposer—silicon, glass, silicon carbide—between the substrate and high density silicon devices or “chiplets.” 2.5D is becoming very important in the industry, and is something that I could talk about in-length, but maybe that’s better saved for its own interview.