The Timing generation is meant to compute the delay to apply, within a data rate model, to each block requiring an external resource.
The resources can be DPRAM access, using the ram_controller or peripheral access, using the Sequencer.
This delay is counted in Flu clock cycles and is relative to the start of the algorithm, triggered by the StartPulse signal.
Those delays have no impact on the simulation as they use pipelines (clock rate delays, invisible during data rate simulation).