The ChgStatI interrupt caused by rising edge of CHGIN is delayed by 3x32us (roughly 100us). So for the fail case, the ChgStatI interrupt occurred while their firmware was clocking out IntA =0x08. At the end of the read, /INT was cleared, clearing also the new value IntA = 0x48. As to why this was only observed while VBAT > VBAT_RECHG, we suspect it’s because ChgStat only changes once for this case (red route below). For VBAT < VBAT_RECHG, the ChgStat can change multiple times (green route).