The data acquisition card is usually timed by a crystal-controlled clock on the card, so the time between each sample is not affected by the speed of the computer. However, the speed of the computer does affect how many samples can be taken within a given amount of time. When the analog to digital converter (A/D) is triggered by the hardware clock, each sample is usually added to a first in, first out buffer (FIFO). It is up to the operating system and the drivers for the board to ensure the FIFO gets emptied in time; otherwise, it will overflow and signal the data acquisition application that it has lost data.