Q
We have an audio device built around the ADAU1445-DSP and the AD1937 CODEC. The ADAU1445-DSP is the clock master. Both of them are controlled on the same I2C bus by a processor, with a software, (‘bit bang’), I2C. 7 bit address of the AD1937 is 0x04 and the ADAU1445 is 0x38. When our processor gets busy, the I2C is a low priority and gets interrupted. We can see on the oscilloscope that sometimes midway through an I2C transaction, both the SCL and the SDA ports stay low for about 40ms. This within the I2C specs as there’s no limit on clock or data speed, the I2C protocol analyzer, ( http://www.totalphase.com/products/beagle_ism/ ), shown no errors, took us a while to notice the 40ms delay in the transaction. When this 40ms both signal low happens, the AD1937’s AD clocks lock up: - Both clock pins, (ALRCLK and ALRCLK), turn from normally configured input to output, (and as our system is normally configured as CODEC slave, we have very loud noise sent on all AD channels with two out of phase clock sources). - I2C communication is working OK, can write and read all registers. - Verified, that all written commands into registers are correctly executed, except the AD clock pin directions, we can even change the ABCLK rate. Only Hardware reset will release the AD1937 from this locked state. We are wondering if this problem is known to AD, or you can see something we are missing, (and possibly on the wrong track).
A
We have done a comprehensive analysis of Stand Alone mode in the AD193x family of parts. Given the fact that the customer is using the AD1937, I will refer to the I2C pins, with respect to the corresponding stand alone mode pins. There are 4 pins total that are used for Stand Alone mode: ADDR0, ADDR1, SCL, and SDA, see the table 12 n the datasheet. Usually, it would be assumed that an IC would look at the Stand Alone mode port once at startup and stay fixed, in or out, of Stand Alone mode until the next reset. However, it appears from bench testing that the AD1937 will go into Stand Alone mode if ADDR0, ADDR1 and SCL are all held Low for more than 4 mS, with the state of SDA setting the ADC Clock ports to Master or Slave. At the same time, the Stand Alone mode will revert to *default* state if the pin conditions above are removed. If the customer is using ADDR 00, two of the three pins are already low. If the SDA and SCL pins are held low for 40 mS, this would certainly put the part in Stand Alone Slave mode, and when the SDA and SCL pins come back high, the part will be left in default. The easiest solution would be to change the I2C address by pulling either or both ADDR0/1 pins high; the AD1937 will never go into Stand Alone mode. P.S. After some lengthy testing, it turns out that the part does not lose its register settings when it goes into and comes out of Stand Alone mode.