There are 2 methods that can be used to modify the example design project : Method 1 : ALERT# placement in DQS group 0 1) Using the Arria 10 GX FPGA Development Kit with DDR4 HiLo preset, in the DDR4 IP Memory tab, change the DQS group of ALERT# parameter to be DQS group 0 and set the DQ width to the required value.
2) In the DDR4 IP Example Designs tab, set the Target Development Kit Select Board parameter to be the Arria 10 FPGA Development Kit with DDR4 HiLo. 3) Generate the example design project. 4) Modify these pin locations either in the qsf file or in the Quartus Prime assignments editor after opening the DDR4 example design project : - Change the pin locations of DQS group 8 to be DQS group 0. Place the DQS group 0 signals at these pin locations : emif_0_mem_mem_dqs[0]      D33 emif_0_mem_mem_dqs_n[0]  C34 emif_0_mem_mem_dbi_n[0]   A32 emif_0_mem_mem_dq[7:0]    A33,B32,D32,C33,B33,D34,C35,E34  (order is not important)   - Disable or delete the DQS group pin location assignments which are not required. 5) In the top level project file (ed_synth_top.sv) modify the inout wire statement bus widths of the signals emif_0_mem_mem_dbi_n ,emif_0_mem_mem_dq,  emif_0_mem_mem_dqs and emif_0_mem_mem_dqs_n. For example,  for a 32 bit wide interface  project these are set to :    inout wire [3:0] emif_0_mem_mem_dbi_n,    inout wire [31:0] emif_0_mem_mem_dq,    inout wire [3:0] emif_0_mem_mem_dqs,    inout wire [3:0] emif_0_mem_mem_dqs_n, 6) Compile the project. Method 2 : ALERT# placement in the address/command I/O bank 1) Using the Arria 10 GX FPGA Development Kit with DDR4 HiLo preset, in the DDR4 IP Memory tab, set the DQ width to the required value and change the ALERT# pin placement settings to be : ALERT# pin placement = I/O Lane with Address/Command Pins Address/Command I/O Lane of ALERT# = 3 Pin index of ALERT# = 0 2) In the DDR4 IP  Example Designs tab, set the Target Development Kit Select Board parameter to be the Arria 10 FPGA Development Kit with DDR4 HiLo. 3) Generate the example design project. 4) Disable or delete the DQS group pin location assignments which are not required either in the qsf file or in the Quartus Prime Assignments Editor after opening the DDR4 example design project. 5) In the top level project file (ed_synth_top.sv) modify the inout wire statement bus widths of the signals emif_0_mem_mem_dbi_n, emif_0_mem_mem_dq, emif_0_mem_mem_dqs and emif_0_mem_mem_dqs_n. For example,  for a 16 bit wide interface project these are set to :    inout wire [1:0] emif_0_mem_mem_dbi_n,    inout wire [15:0] emif_0_mem_mem_dq,    inout wire [1:0] emif_0_mem_mem_dqs,    inout wire [1:0] emif_0_mem_mem_dqs_n, 6) Compile the project.