I'm writing a SystemVerilog modules.

I have the following AXI Stream interface definition.
```
interface xorif_prach_bid_if;

    logic [3:0]  cc;
    logic [7:0]  ss;
    logic [11:0] section_id;
    logic [3:0]  return_port;
    logic [3:0]  filter_index;
    logic [3:0]  sf;
    logic [5:0]  sl;
    logic [5:0]  sy;
    logic [15:0] time_offset;
    logic [7:0]  frame_structure;
    logic [15:0] cp_length;
    logic [7:0]  udcomphdr;
    logic        rb;
    logic        syminc;
    logic [9:0]  start_prbc;
    logic [7:0]  num_prbc;
    logic [11:0] remask;
    logic [3:0]  num_symbol;
    logic [14:0] beamid;
    logic [23:0] freqoffset;
    logic        tvalid;
    logic        tready;

    modport master (
        input  tready,
        output cc, ss, section_id, return_port, filter_index, sf, sl, sy,
               time_offset, frame_structure, cp_length, udcomphdr, rb, syminc, start_prbc,
               num_prbc, remask, num_symbol, beamid, freqoffset, tvalid
    );

    modport slave (
        input  cc, ss, section_id, return_port, filter_index, sf, sl, sy,
               time_offset, frame_structure, cp_length, udcomphdr, rb, syminc, start_prbc,
               num_prbc, remask, num_symbol, beamid, freqoffset, tvalid,
        output tready
    );

endinterface
```

I have the following adapter modules to convert between regular wires and interfaces.
```
module xorif_prach_bid_if_slave_adapter(
    xorif_prach_bid_if.slave s_prach_bid_if,

    input  logic [3:0]       i_cc,
    input  logic [7:0]       i_ss,
    input  logic [11:0]      i_section_id,
    input  logic [3:0]       i_return_port,
    input  logic [3:0]       i_filter_index,
    input  logic [3:0]       i_sf,
    input  logic [5:0]       i_sl,
    input  logic [5:0]       i_sy,
    input  logic [15:0]      i_time_offset,
    input  logic [7:0]       i_frame_structure,
    input  logic [15:0]      i_cp_length,
    input  logic [7:0]       i_udcomphdr,
    input  logic             i_rb,
    input  logic             i_syminc,
    input  logic [9:0]       i_start_prbc,
    input  logic [7:0]       i_num_prbc,
    input  logic [11:0]      i_remask,
    input  logic [3:0]       i_num_symbol,
    input  logic [14:0]      i_beamid,
    input  logic [23:0]      i_freqoffset,
    input  logic             i_tvalid,

    output logic             o_tready
);

    assign s_prach_bid_if.cc              = i_cc;              
    assign s_prach_bid_if.ss              = i_ss;              
    assign s_prach_bid_if.section_id      = i_section_id;      
    assign s_prach_bid_if.return_port     = i_return_port;     
    assign s_prach_bid_if.filter_index    = i_filter_index;    
    assign s_prach_bid_if.sf              = i_sf;        
    assign s_prach_bid_if.sl              = i_sl;        
    assign s_prach_bid_if.sy              = i_sy;        
    assign s_prach_bid_if.time_offset     = i_time_offset;     
    assign s_prach_bid_if.frame_structure = i_frame_structure; 
    assign s_prach_bid_if.cp_length       = i_cp_length;       
    assign s_prach_bid_if.udcomphdr       = i_udcomphdr;       
    assign s_prach_bid_if.rb              = i_rb;              
    assign s_prach_bid_if.syminc          = i_syminc;          
    assign s_prach_bid_if.start_prbc      = i_start_prbc;      
    assign s_prach_bid_if.num_prbc        = i_num_prbc;        
    assign s_prach_bid_if.remask          = i_remask;          
    assign s_prach_bid_if.num_symbol      = i_num_symbol;      
    assign s_prach_bid_if.beamid          = i_beamid;          
    assign s_prach_bid_if.freqoffset      = i_freqoffset;      
    assign s_prach_bid_if.tvalid          = i_tvalid;          

    assign o_tready = s_prach_bid_if.tready;

endmodule
```

For the module below instantiate xorif_prach_bid_if and a corresponding adapter module for input ports:
```
module top(
    // oran_prach_s0_bid
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid beamid"          *) input  [14:0] oran_prach_s0_bid_beamid,
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid cc"              *) input  [3:0]  oran_prach_s0_bid_cc,
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid cp_length"       *) input  [15:0] oran_prach_s0_bid_cp_length,
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid filter_index"    *) input  [3:0]  oran_prach_s0_bid_filter_index,
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid frame_structure" *) input  [7:0]  oran_prach_s0_bid_frame_structure,
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid freqoffset"      *) input  [23:0] oran_prach_s0_bid_freqoffset,
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid num_prbc"        *) input  [7:0]  oran_prach_s0_bid_num_prbc,
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid num_symbol"      *) input  [3:0]  oran_prach_s0_bid_num_symbol,
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid rb"              *) input         oran_prach_s0_bid_rb,
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid remask"          *) input  [11:0] oran_prach_s0_bid_remask,
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid return_port"     *) input  [3:0]  oran_prach_s0_bid_return_port,
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid section_id"      *) input  [11:0] oran_prach_s0_bid_section_id,
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid sf"              *) input  [3:0]  oran_prach_s0_bid_sf,
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid sl"              *) input  [5:0]  oran_prach_s0_bid_sl,
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid ss"              *) input  [7:0]  oran_prach_s0_bid_ss,
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid start_prbc"      *) input  [9:0]  oran_prach_s0_bid_start_prbc,
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid sy"              *) input  [5:0]  oran_prach_s0_bid_sy,
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid syminc"          *) input         oran_prach_s0_bid_syminc,
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid time_offset"     *) input  [15:0] oran_prach_s0_bid_time_offset,
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid tready"          *) output        oran_prach_s0_bid_tready,
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid tvalid"          *) input         oran_prach_s0_bid_tvalid,
    (* X_INTERFACE_INFO = "xilinx.com:xroe_display:xorif_prach_if:1.0 oran_prach_s0_bid udcomphdr"       *) input  [7:0]  oran_prach_s0_bid_udcomphdr
);
endmodule
```