# Hybsync: Nanosecond Wireless Position and Clock Synchronization Based on UWB Communication with Multisensors

Authors: Pengyu Lei; Zhitian Li; Bo Xue; Haifeng Zhang; Xudong Zou
Journal: Journal of Sensors
 (2021)

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## Abstract

PNT (positioning, navigation, and timing) is the core functional part of kinds of wireless sensor network, which can provide high-precision timing and positioning services for cooperative work systems. Unfortunately, the mature wireless PNT schemes are generally based on GNSS and other auxiliary sources to complete the high accuracy synchronization process, which cannot be applied to GNSS degraded and denied environments such as mines, underground application. In order to solve the application problem of high-precision wireless PNT, Hybsync—a novel non-GNSS-aided wireless PNT architecture, is proposed in this paper, which integrates the information from the UWB communication, inertial sensor, and camera to achieve great PNT performance. Hybsync improves the accuracy of time deviation measurement by collecting and recording timestamps in hardware layer, and with the coarse/fine synchronization two-phase calibration, Hybsync greatly improves the accuracy of time deviation adjustment, thus providing accurate time information for the whole system. Besides, Hybsync uses the VINS framework to further integrate the real-time information of IMU and camera to complete the multinode positioning service. Under the premise that the cost is much lower than existing solutions, Hybsync can provide nanosecond-level clock synchronization and centimeter-level positioning. Experiments prove that Hybsync supports high-precision clock synchronization and positioning of more than 10 nodes; the maximum clock synchronization error is 3 ns, and the positioning error is 7 cm. It can provide accurate time and position services for cooperative work systems under complex and GNSS-denied conditions.


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## Body

## 1. Introduction

PNT systems play a very important role in our technological society. Especially in applications that require high precision, there is a lack of solutions to meet the needs of suitable applications [1, 2].The existing PNT system basically relies on a global satellite navigation system and related enhancement systems, navigation systems, and timing systems [3]. Global Navigation Satellite System (GNSS) is a satellite-based positioning, navigation, and timing (PNT) system, which is the most common and widely used type of PNT service [4, 5]. GNSS has wide coverage, high accuracy, and relatively low cost, so it is widely used in power electronics, positioning, and node cooperative work. However, GNSS is easily affected by radio interference, thus posing a serious threat to the signals [6]. From the perspective of robustness and security, PNT services should not only rely on GNSS [7, 8]. In actual applications, GNSS will inevitably be interrupted or denied. Other PNT solutions that do not rely on GNSS are mostly point-to-point solutions, such as longwave/shortwave timing systems. These schemes can only achieve μs-level clock synchronization accuracy [9]. Methods such as Ethernet timing and optical fibre timing have high precision, which can reach the picosecond level, but they are not suitable for mobile nodes [10]. The existing clock synchronization schemes, shown in Table 1, are not suitable for our application scenarios. In the relative positioning of some UAV (unmanned aerial vehicle) groups, a synchronization accuracy of less than 10 ns is usually required to achieve centimeter-level positioning accuracy. However, existing wireless synchronization schemes with GNSS denied are difficult to meet the requirements and are prone to large positioning errors [11–13].Table 1
Clock synchronization scheme.
Clock synchronizationAccuracyInfluencing factorsCostNetwork based10μs-100 msUncertainty delayMediumTV based100 ns-100μsTransmission rangeLowShortwave based200μs-500 μsAffected by the ionosphereMediumLongwave based1μsAffected by the seasonHighMobile-station based1 msCommunication equipmentLowSatellite based<50 nsAffected by viewing angle, relying on GNSSMediumOptical fibre based<100 psDispersion and attenuation lossHighMultisource fusion is the development direction of PNT, and the positioning field has been widely used. However, there are few mature solutions for multisource integration in the field of wireless multinode PNT. Existing systems with both positioning and clock synchronization are mainly based on GNSS or GNSS-compatible pseudolite systems [14, 15]. Considering the needs of multinode cooperative working systems in complex and extreme environments, the existing solutions cannot simultaneously satisfy GNSS denied, high precision, multinodes, clock synchronization, and positioning [16].In order to solve the problem of low synchronization accuracy and high positioning error under GNSS-denied conditions, Hybsync, a clock synchronization and positioning system for GNSS-denied conditions, is proposed in this paper, which has the advantages of low cost and high accuracy. Unlike other synchronization solutions, Hybsync makes full use of the high-precision features of UWB to realize wireless clock synchronization and positioning under multiple nodes. By optimizing the hardware architecture and reducing the impact of uncertain delays, the system can provide nanosecond clock synchronization messages. In the case of GNSS denied and no predeployed anchor points, Hybsync can use the visual sensors and IMUs installed on the nodes to obtain positioning information and complete positioning. Hybsync also can provide a wealth of signal interfaces and can be easily integrated into the cooperative detection network node. Through testing, Hybsync can achieve a clock synchronization accuracy of less than 5 ns and a position synchronization accuracy of less than 10 cm. This is of great significance for tasks such as cooperative detection, positioning, and mapping.The main contributions of this article are as follows:(1)
A set of high-precision positioning and clock synchronization system architecture solutions based on low-cost shelf products is designed, which can integrate various sensor information. Compared with existing mature technical solutions, this solution has lower cost and better synchronization accuracy and supports a larger number of nodes(2)
An adaptive multinode network strategy is designed that can satisfy the Hybsync system for efficient positioning and synchronizationThe remainder of this paper is structured as follows: Section2 introduces the comprehensive hardware architecture that supports nanosecond clock synchronization and centimeter-level positioning services. It also describes the Hybsync workflow that supports multiple nodes. Section 3 describes the experimental design and results of the Hybsync synchronization system, which verify the clock and position synchronization function of Hybsync under a single pair of nodes and multiple nodes. This paper is concluded in Section 4.


## 2. The General Architecture of Hybsync

Our Hybsync system can provide high-precision time reference, clock synchronization, and real-time position information for the multinode cooperative network under complex, dynamic, and GNSS-denied environments and ensure the accuracy of cooperative work. Based on actual engineering needs and design requirements, the Hybsync system can be divided into two parts:(1)
The Core Hardware Architecture. Hybsync’s hardware architecture takes full advantage of UWB and multisensor fusion. It takes advantage of the large bandwidth and high time resolution of the ultrawideband signal, reduces the uncertain delay in the signal transmission process by recording the timestamps at the hardware layer, uses the improved two-way clock synchronization protocol and reasonably sets the clock tame circuit to achieve nanosecond-level synchronization between nodes, and uses camera and IMU fusion positioning to achieve high-precision position synchronization between nodes.(2)
The Adaptive Multinode Synchronization Network. Hybsync combines a self-organizing network and local area network to communicate between nodes and complete the time and position synchronization function to satisfy the actual application requirements.The Hybsync block diagram is shown in Figure1. Hybsync can exchange time messages and calibrate the clock through wireless communication between nodes and then adjust the clock frequency output at the nodes to achieve clock synchronization. In addition, it can complete position synchronization through a local area network composed of system nodes. In the architecture, each node consists of a processor, a system board, a binocular camera, a built-in IMU, and other sensors. This system can be easily integrated into the nodes of the cooperative detection network.Figure 1
General hardware and function module architecture of Hybsync.Hybsync adopts a modular design to synchronize clock and positioning. By selecting appropriate hardware components, designing working modules, and adding corresponding indicator lights, Hybsync is a low-cost, high-precision, and easy-to-test system. The following introduces the various working modules of the Hybsync system.


### 2.1. Clock Synchronization

The clock synchronization part of Hybsync includes three modules: wireless transceiver module, a control module, and a time tame module. We select an appropriate UWB channel communication chip and control chip and design a suitable clock taming circuit. We also add suitable working status indicators and design interface signals to give the hardware system platform more functionality and make it easier to operate. The hardware system architecture of the clock synchronization system is shown in Figure2.Figure 2
Clock synchronization system architecture.Clock synchronization mainly includes two aspects: accurate measurement and accurate compensation of clock deviation. The former mainly requires that the timestamp accurately reflects the time when the message leaves the antenna, and the timestamp should be accurate itself. Traditional schemes obtain timestamps in the MAC (Media Access Control), and multiple time delays occur in the process of transmitting the message to the antenna, such as sending delay, access delay, transmission delay, and receiving processing delay. The transmission delay, access delay, and receiving processing delay are uncertain delays, which usually bring microsecond or millisecond errors and greatly impact the clock synchronization accuracy [17]. Therefore, traditional clock synchronization schemes always have low accuracy due to inaccurate timestamp data, as shown in Figure 3. In this design, in order to reduce the impact on accuracy caused by uncertainty delays and improve the performance of the clock synchronization system, the UWB channel is selected as the wireless communication channel, and the timestamps are recorded at the hardware layer to truly reflect the timing when the message arrives at the antenna. This way, uncertain delays in the transmission process can be ignored. The system also uses timestamps generated by the 64 GHz counter in the UWB communication chip [18]. The resolution of the timestamps is about 15.65 picoseconds, which ensures that the synchronization results achieve sufficient accuracy [19, 20].Figure 3
Schematic diagram of delay error in the process of information dissemination.Accurate compensation of time deviation is also important to ensure high-precision clock synchronization. By accurately calculating the difference between the local clock phase and the reference phase and adjusting the clock taming module composed of a high-precision DAC and a voltage-controlled temperature-compensated crystal oscillator, the output clock of the oscillator can be controlled. However, in practical situations, the phase of the clock is uncertain, bringing uncertain adjustment time. Meanwhile, the frequency traction of the voltage-controlled oscillator is also limited. If the phase of the time deviation is too large and is directly output to the clock taming module, it will take a long time (hours) to achieve clock synchronization, which is unacceptable in actual applications. We use a combination of coarse synchronization, and fine synchronization is used; the former is to reduce the synchronization time when the phase deviation is too large, and the latter is to ensure that the system can achieve sufficient accuracy. This ensures that the synchronization time of the system is within a reasonable range, and the synchronization accuracy can satisfy actual requirements.


#### 2.1.1. Time Synchronization Protocol

In order to improve the accuracy of time synchronization, an optimized protocol based on PTP [21] (Precise Time Protocol) is proposed and introduced into the Hybsync. By optimizing the model, using three-time messages and replacing the uncertain processing delay with a fixed delay improve the accuracy clock synchronization. By calculating the frequency scale factor to guide the local clock adjusts the frequency. The established two-way clock synchronization model is shown in Figure 4. Figure 4 identifies the timestamp recorded during the message exchange.Figure 4
Optimized time synchronization protocol.According to the model, the propagation delayTprop can be expressed as Equation (1). The time deviation Δθ can be expressed as Equation (2) by using the characteristics of two two-way measurements. The phase difference information obtained makes full use of the phase information contained in the timestamp and reduces the influence of random environmental noise on the measurement.(1)Tprop=T4−T1−T3−T22=T6−T3−T5−T42,(2)Δθ=2T3−T4+T2+T6−T1−T54.There is an assumption in this model: the frequency of the node’s oscillator is the nominal frequency. Therefore, in practical applications, it is necessary to consider the influence of the frequency difference between the master and slave nodes and the asymmetry of propagation delay. The frequency factor between the master and slave clocks is calculated, expressed as Equations (3)–(5), and adjusted the frequency to make the frequency of the master and slave clocks close to the same. In order to eliminate the uncertain delay, replace it with a fixed delay, while leaving enough margins for system operation to complete the operation.(3)T5−T1=T6−T2=∆t,(4)T5−T1=kM∆t,(5)T6−T2=kS∆t.kM and kS are the clock frequencies of the master and slave nodes, and ∆t is a constant. The frequency scale factor a can be calculated as Equation (6).(6)a=kMkS=T5−T1T6−T2.Adjust the clock of the slave node according to the frequency scaling factora. When the scale factor a tends to 1, the frequency of the master and slave nodes converges. In this module, one synchronization process can achieve two-phase measurements, which not only improves the accuracy of the measurement, but also reflects the frequency difference between nodes. This can help the node predict the change of error and improve the system’s resistance to environmental noise and the stability of synchronization.


#### 2.1.2. Coarse Synchronization Module

The time required for synchronization can be greatly reduced through coarse synchronization, which is in line with actual engineering applications. We design a coarse synchronizer, as shown in Figure5. It generates a synchronization signal in advance to reduce the time deviation to a certain range. Specifically, it obtains the time deviation value measured by the time interval measurement module and transmits the value to the FPGA through serial communication. This FPGA is equipped with a synchronous signal generator and a timer. In the normal state, the synchronization signal generator generates a synchronization signal every second. As soon as the UART receives data, the timer in the FPGA counts the corresponding time and generates a synchronization signal to make the system synchronize in advance, thus reducing the clock phase difference between the synchronization node and the reference node.Figure 5
Coarse synchronization module frame.


#### 2.1.3. Fine Synchronization Module

After the time deviation passes through the coarse synchronization module, the phase difference between the two nodes falls below the set threshold, and the time deviation can be adjusted accurately and efficiently through fine synchronization. In order to improve the control accuracy and effectively suppress the effect of phase measurement noise on the results, PID control modules are applied. The structure is shown in Figure6. PID control is a technology widely used in industrial process control. It is a feedback controller, which maintains the output at the required level through feedback based on the input signal. The designed PID controller maintains zero error between the output and the expected output using closed-loop negative feedback.Figure 6
Fine synchronization scheme based on PID.The input of the PID controller is the phase difference between the local phase and the received reference phase, and the output is the control signal. The clock taming circuit controls the frequency of the voltage-controlled oscillator based on the received control signal. The system adjusts the output frequency of the oscillator through the PID controller to reduce the time deviation. Eventually, the phase difference will converge to a lower level ensuring that the clocks of the oscillator and the reference oscillator are consistent and achieving clock synchronization.


#### 2.1.4. Clock Taming Module

The clock taming module consists of a DAC and a voltage-controlled temperature-compensated crystal oscillator. The module tames the oscillator output frequency according to the output of the PID controller in the fine synchronization module, so that the local crystal oscillator phase of the node is kept consistent with the clock phase of the received reference node. In order to improve the accuracy of the oscillator output frequency adjustment, the DAC is configured according to the selected oscillator parameters, so that the resolution of the corresponding timestamps will be improved.The formula for calculating the number of DAC bits is expressed as Equation (7).(7)12nVDAC=A∗fK,where VDAC is the control voltage of the DAC (2 V), A is the short-term stability of the oscillator (1.5e-10), f is the nominal frequency of the selected crystal oscillator (38.4 MHz), K is the voltage-controlled frequency coefficient, and n is the number of bits of the selected DAC. The theoretical number of DAC bits that can be calculated is about 16, so a 16-bit DAC is selected. To ensure the accuracy of the voltage output by the DAC, a suitable reference voltage chip is selected to provide accurate voltages for the DAC and crystal oscillator.


### 2.2. Positioning

In an unfamiliar environment, real-time positioning is very important. Hybsync can use the sensors of the synchronization node to obtain information and perform positioning without prior knowledge. The position synchronization function of Hybsync is realized through the networking of multiple nodes, which is made up of unmanned vehicles, servers, and gateways. Each node is equipped with binocular cameras, IMUs, and processors. The multisource sensing system minimizes the reprojection error and IMU residual error to obtain a reliable estimation of the node pose. By running the sensor fusion algorithm of binocular camera and IMU on the processor, the reliable pose information can be solved. The accuracy and reliability of the system position synchronization are improved, and a centimeter-level positioning accuracy is achieved. The hardware architecture of this function is shown in Figure7.Figure 7
Position synchronization of the Hybsync.In the Hybsync system, in order to improve the accuracy of positioning, it is necessary to achieve clock synchronization between the camera, IMU, and UWB. The details are shown in Figure8. First, the IMU and camera on the node use a tightly coupled optimization algorithm based on a sliding window to achieve time synchronization [22]. The cost function is constructed by using the invariance of feature points in adjacent frames. Hybsync uses UWB to obtain the accurate time of the system and outputs time sync information and positioning information.Figure 8
Clock synchronization between UWB, CAM, and IMU.In order to achieve the positioning function, Hybsync needs to obtain the pose information of each node. In this system, we use the state variables to express the pose information, which is expressed asX=pvq. In order to optimize the state variables, a tightly coupled fusion method is used to process visual information and inertial information, and the inverse depth of the feature points, expressed as λ, is also added to the state variables [22]. In order to fuse the information output by the camera and the IMU sensor, the spatial transformation relationship between them, expressed as Xcb, is also added to the state variable. Since the IMU will be affected by the zero offset and lead to accumulated errors in the positioning information, the gyroscope zero offset, expressed as bg, and the accelerometer zero offset, expressed as ba, are also taken into account. Then, the related cost function is constructed based on the sliding window algorithm, and nonlinear optimization is adopted to solve the state variables in real time [23]. Finally, the state variable to be estimated for each node in the system is shown in Equations (8)–(10).(8)Xi=x0,x1,⋯xn,xcb,λ0,λ1,⋯λm,(9)xk=pbkw,vbkw,qbkw,ba,bg,(10)xcb=pcb,qcb.xk represents the variable that the node needs to be optimized at time k, respectively, which represents the node’s position, velocity, rotation, and IMU bias. n represents the size of the sliding window, and λ represents the inverse depth of the image feature point. xcb represents camera-IMU transformation simultaneously.The state estimation problem of nodes can be modelled as a nonlinear optimization problem. The final optimized cost function is expressed as Equation (11).(11)minXirp−HpXi2+∑k∈BrBz^bk+1bk,XiPbk+1bk2+∑l,j∈CρrCz^lcj,XiPlcj2.rp represents the prior residuals. rB represents the IMU residuals, and rC represents the visual residuals. ρ represents a robust kernel function, which reduces the influence of outliers on the system. The above cost function is solved by using the Ceres optimization library. Finally, the optimal output of the positioning information of each node in the system is obtained.


### 2.3. Multinode Network Strategy

In a multinode cooperative detection system, more nodes usually mean a longer cooperative detection range, richer position information, and greater application value. Therefore, in practical applications, the Hybsync synchronization system must utilize multiple nodes. In order to reduce the complexity and improve the synchronization accuracy, the clock synchronization module is connected in the form of an ad hoc network, while the position synchronization module is connected through a local area network. Hybsync architecture under multinode working conditions is shown in Figure9. The Hybsync workflow is shown in Figure 10.Figure 9
Hybsync’s multinode network strategy.Figure 10
Hybsync synchronization workflow.The core clock synchronization algorithm of Hybsync draws on the IEEE 1588v2 protocol and makes certain improvements. By sharing the time message with a two-way time message exchange mechanism, we achieve low complexity, strong scalability, and fast synchronization speed, which makes our system suitable for wireless multinode high-precision mutual clock calibration within the cluster. We mainly use a two-way time message exchange between the master reference node and the synchronization node in the UWB channel to perform mutual calibration and obtain the timestamp [24]. Then, the timestamp is processed to perform clock taming, and nanosecond-level calibration of clock signals between nodes can be performed in a short time. When it is necessary to expand the scale of the node network, newly added nodes must satisfy the communication protocol we design.After being powered on, Hybsync’s clock synchronization system begins to work, and the nodes communicate with each other to record and transmit the accurate timestamp from the hardware layer. The control module calculates the time deviation, which is compared with the set threshold, and decides whether to perform coarse synchronization. Coarse synchronization is then implemented to reduce the time deviation between the two nodes. The output frequency of the oscillator is adjusted by the fine synchronization module which is mainly composed of the PID controller and the clock taming module. This provides the clock for the nodes in the wireless sensor network.After Hybsync is powered on, the position synchronization module also begins to work. The nodes communicate with the server and rely on ROS (Robot Operating System) to combine a network remotely. The server issues synchronous positioning commands to all nodes and receives positioning information from them at the same time, including pose, speed, and acceleration. The server can obtain access control to a single node, restart it, and output the original sensor information.In the described working state, Hybsync can realize high-precision PT synchronization of multiple nodes and output accurate time and position messages. In our test, the system supports the normal operation of 10 nodes, which demonstrates the correctness and rationality of the system design. In future large-scale networks, a corresponding number of nodes can be deployed as needed. Hybsync can easily be expanded to incorporate additional nodes.


## 2.1. Clock Synchronization

The clock synchronization part of Hybsync includes three modules: wireless transceiver module, a control module, and a time tame module. We select an appropriate UWB channel communication chip and control chip and design a suitable clock taming circuit. We also add suitable working status indicators and design interface signals to give the hardware system platform more functionality and make it easier to operate. The hardware system architecture of the clock synchronization system is shown in Figure2.Figure 2
Clock synchronization system architecture.Clock synchronization mainly includes two aspects: accurate measurement and accurate compensation of clock deviation. The former mainly requires that the timestamp accurately reflects the time when the message leaves the antenna, and the timestamp should be accurate itself. Traditional schemes obtain timestamps in the MAC (Media Access Control), and multiple time delays occur in the process of transmitting the message to the antenna, such as sending delay, access delay, transmission delay, and receiving processing delay. The transmission delay, access delay, and receiving processing delay are uncertain delays, which usually bring microsecond or millisecond errors and greatly impact the clock synchronization accuracy [17]. Therefore, traditional clock synchronization schemes always have low accuracy due to inaccurate timestamp data, as shown in Figure 3. In this design, in order to reduce the impact on accuracy caused by uncertainty delays and improve the performance of the clock synchronization system, the UWB channel is selected as the wireless communication channel, and the timestamps are recorded at the hardware layer to truly reflect the timing when the message arrives at the antenna. This way, uncertain delays in the transmission process can be ignored. The system also uses timestamps generated by the 64 GHz counter in the UWB communication chip [18]. The resolution of the timestamps is about 15.65 picoseconds, which ensures that the synchronization results achieve sufficient accuracy [19, 20].Figure 3
Schematic diagram of delay error in the process of information dissemination.Accurate compensation of time deviation is also important to ensure high-precision clock synchronization. By accurately calculating the difference between the local clock phase and the reference phase and adjusting the clock taming module composed of a high-precision DAC and a voltage-controlled temperature-compensated crystal oscillator, the output clock of the oscillator can be controlled. However, in practical situations, the phase of the clock is uncertain, bringing uncertain adjustment time. Meanwhile, the frequency traction of the voltage-controlled oscillator is also limited. If the phase of the time deviation is too large and is directly output to the clock taming module, it will take a long time (hours) to achieve clock synchronization, which is unacceptable in actual applications. We use a combination of coarse synchronization, and fine synchronization is used; the former is to reduce the synchronization time when the phase deviation is too large, and the latter is to ensure that the system can achieve sufficient accuracy. This ensures that the synchronization time of the system is within a reasonable range, and the synchronization accuracy can satisfy actual requirements.


### 2.1.1. Time Synchronization Protocol

In order to improve the accuracy of time synchronization, an optimized protocol based on PTP [21] (Precise Time Protocol) is proposed and introduced into the Hybsync. By optimizing the model, using three-time messages and replacing the uncertain processing delay with a fixed delay improve the accuracy clock synchronization. By calculating the frequency scale factor to guide the local clock adjusts the frequency. The established two-way clock synchronization model is shown in Figure 4. Figure 4 identifies the timestamp recorded during the message exchange.Figure 4
Optimized time synchronization protocol.According to the model, the propagation delayTprop can be expressed as Equation (1). The time deviation Δθ can be expressed as Equation (2) by using the characteristics of two two-way measurements. The phase difference information obtained makes full use of the phase information contained in the timestamp and reduces the influence of random environmental noise on the measurement.(1)Tprop=T4−T1−T3−T22=T6−T3−T5−T42,(2)Δθ=2T3−T4+T2+T6−T1−T54.There is an assumption in this model: the frequency of the node’s oscillator is the nominal frequency. Therefore, in practical applications, it is necessary to consider the influence of the frequency difference between the master and slave nodes and the asymmetry of propagation delay. The frequency factor between the master and slave clocks is calculated, expressed as Equations (3)–(5), and adjusted the frequency to make the frequency of the master and slave clocks close to the same. In order to eliminate the uncertain delay, replace it with a fixed delay, while leaving enough margins for system operation to complete the operation.(3)T5−T1=T6−T2=∆t,(4)T5−T1=kM∆t,(5)T6−T2=kS∆t.kM and kS are the clock frequencies of the master and slave nodes, and ∆t is a constant. The frequency scale factor a can be calculated as Equation (6).(6)a=kMkS=T5−T1T6−T2.Adjust the clock of the slave node according to the frequency scaling factora. When the scale factor a tends to 1, the frequency of the master and slave nodes converges. In this module, one synchronization process can achieve two-phase measurements, which not only improves the accuracy of the measurement, but also reflects the frequency difference between nodes. This can help the node predict the change of error and improve the system’s resistance to environmental noise and the stability of synchronization.


### 2.1.2. Coarse Synchronization Module

The time required for synchronization can be greatly reduced through coarse synchronization, which is in line with actual engineering applications. We design a coarse synchronizer, as shown in Figure5. It generates a synchronization signal in advance to reduce the time deviation to a certain range. Specifically, it obtains the time deviation value measured by the time interval measurement module and transmits the value to the FPGA through serial communication. This FPGA is equipped with a synchronous signal generator and a timer. In the normal state, the synchronization signal generator generates a synchronization signal every second. As soon as the UART receives data, the timer in the FPGA counts the corresponding time and generates a synchronization signal to make the system synchronize in advance, thus reducing the clock phase difference between the synchronization node and the reference node.Figure 5
Coarse synchronization module frame.


### 2.1.3. Fine Synchronization Module

After the time deviation passes through the coarse synchronization module, the phase difference between the two nodes falls below the set threshold, and the time deviation can be adjusted accurately and efficiently through fine synchronization. In order to improve the control accuracy and effectively suppress the effect of phase measurement noise on the results, PID control modules are applied. The structure is shown in Figure6. PID control is a technology widely used in industrial process control. It is a feedback controller, which maintains the output at the required level through feedback based on the input signal. The designed PID controller maintains zero error between the output and the expected output using closed-loop negative feedback.Figure 6
Fine synchronization scheme based on PID.The input of the PID controller is the phase difference between the local phase and the received reference phase, and the output is the control signal. The clock taming circuit controls the frequency of the voltage-controlled oscillator based on the received control signal. The system adjusts the output frequency of the oscillator through the PID controller to reduce the time deviation. Eventually, the phase difference will converge to a lower level ensuring that the clocks of the oscillator and the reference oscillator are consistent and achieving clock synchronization.


### 2.1.4. Clock Taming Module

The clock taming module consists of a DAC and a voltage-controlled temperature-compensated crystal oscillator. The module tames the oscillator output frequency according to the output of the PID controller in the fine synchronization module, so that the local crystal oscillator phase of the node is kept consistent with the clock phase of the received reference node. In order to improve the accuracy of the oscillator output frequency adjustment, the DAC is configured according to the selected oscillator parameters, so that the resolution of the corresponding timestamps will be improved.The formula for calculating the number of DAC bits is expressed as Equation (7).(7)12nVDAC=A∗fK,where VDAC is the control voltage of the DAC (2 V), A is the short-term stability of the oscillator (1.5e-10), f is the nominal frequency of the selected crystal oscillator (38.4 MHz), K is the voltage-controlled frequency coefficient, and n is the number of bits of the selected DAC. The theoretical number of DAC bits that can be calculated is about 16, so a 16-bit DAC is selected. To ensure the accuracy of the voltage output by the DAC, a suitable reference voltage chip is selected to provide accurate voltages for the DAC and crystal oscillator.


## 2.1.1. Time Synchronization Protocol

In order to improve the accuracy of time synchronization, an optimized protocol based on PTP [21] (Precise Time Protocol) is proposed and introduced into the Hybsync. By optimizing the model, using three-time messages and replacing the uncertain processing delay with a fixed delay improve the accuracy clock synchronization. By calculating the frequency scale factor to guide the local clock adjusts the frequency. The established two-way clock synchronization model is shown in Figure 4. Figure 4 identifies the timestamp recorded during the message exchange.Figure 4
Optimized time synchronization protocol.According to the model, the propagation delayTprop can be expressed as Equation (1). The time deviation Δθ can be expressed as Equation (2) by using the characteristics of two two-way measurements. The phase difference information obtained makes full use of the phase information contained in the timestamp and reduces the influence of random environmental noise on the measurement.(1)Tprop=T4−T1−T3−T22=T6−T3−T5−T42,(2)Δθ=2T3−T4+T2+T6−T1−T54.There is an assumption in this model: the frequency of the node’s oscillator is the nominal frequency. Therefore, in practical applications, it is necessary to consider the influence of the frequency difference between the master and slave nodes and the asymmetry of propagation delay. The frequency factor between the master and slave clocks is calculated, expressed as Equations (3)–(5), and adjusted the frequency to make the frequency of the master and slave clocks close to the same. In order to eliminate the uncertain delay, replace it with a fixed delay, while leaving enough margins for system operation to complete the operation.(3)T5−T1=T6−T2=∆t,(4)T5−T1=kM∆t,(5)T6−T2=kS∆t.kM and kS are the clock frequencies of the master and slave nodes, and ∆t is a constant. The frequency scale factor a can be calculated as Equation (6).(6)a=kMkS=T5−T1T6−T2.Adjust the clock of the slave node according to the frequency scaling factora. When the scale factor a tends to 1, the frequency of the master and slave nodes converges. In this module, one synchronization process can achieve two-phase measurements, which not only improves the accuracy of the measurement, but also reflects the frequency difference between nodes. This can help the node predict the change of error and improve the system’s resistance to environmental noise and the stability of synchronization.


## 2.1.2. Coarse Synchronization Module

The time required for synchronization can be greatly reduced through coarse synchronization, which is in line with actual engineering applications. We design a coarse synchronizer, as shown in Figure5. It generates a synchronization signal in advance to reduce the time deviation to a certain range. Specifically, it obtains the time deviation value measured by the time interval measurement module and transmits the value to the FPGA through serial communication. This FPGA is equipped with a synchronous signal generator and a timer. In the normal state, the synchronization signal generator generates a synchronization signal every second. As soon as the UART receives data, the timer in the FPGA counts the corresponding time and generates a synchronization signal to make the system synchronize in advance, thus reducing the clock phase difference between the synchronization node and the reference node.Figure 5
Coarse synchronization module frame.


## 2.1.3. Fine Synchronization Module

After the time deviation passes through the coarse synchronization module, the phase difference between the two nodes falls below the set threshold, and the time deviation can be adjusted accurately and efficiently through fine synchronization. In order to improve the control accuracy and effectively suppress the effect of phase measurement noise on the results, PID control modules are applied. The structure is shown in Figure6. PID control is a technology widely used in industrial process control. It is a feedback controller, which maintains the output at the required level through feedback based on the input signal. The designed PID controller maintains zero error between the output and the expected output using closed-loop negative feedback.Figure 6
Fine synchronization scheme based on PID.The input of the PID controller is the phase difference between the local phase and the received reference phase, and the output is the control signal. The clock taming circuit controls the frequency of the voltage-controlled oscillator based on the received control signal. The system adjusts the output frequency of the oscillator through the PID controller to reduce the time deviation. Eventually, the phase difference will converge to a lower level ensuring that the clocks of the oscillator and the reference oscillator are consistent and achieving clock synchronization.


## 2.1.4. Clock Taming Module

The clock taming module consists of a DAC and a voltage-controlled temperature-compensated crystal oscillator. The module tames the oscillator output frequency according to the output of the PID controller in the fine synchronization module, so that the local crystal oscillator phase of the node is kept consistent with the clock phase of the received reference node. In order to improve the accuracy of the oscillator output frequency adjustment, the DAC is configured according to the selected oscillator parameters, so that the resolution of the corresponding timestamps will be improved.The formula for calculating the number of DAC bits is expressed as Equation (7).(7)12nVDAC=A∗fK,where VDAC is the control voltage of the DAC (2 V), A is the short-term stability of the oscillator (1.5e-10), f is the nominal frequency of the selected crystal oscillator (38.4 MHz), K is the voltage-controlled frequency coefficient, and n is the number of bits of the selected DAC. The theoretical number of DAC bits that can be calculated is about 16, so a 16-bit DAC is selected. To ensure the accuracy of the voltage output by the DAC, a suitable reference voltage chip is selected to provide accurate voltages for the DAC and crystal oscillator.


## 2.2. Positioning

In an unfamiliar environment, real-time positioning is very important. Hybsync can use the sensors of the synchronization node to obtain information and perform positioning without prior knowledge. The position synchronization function of Hybsync is realized through the networking of multiple nodes, which is made up of unmanned vehicles, servers, and gateways. Each node is equipped with binocular cameras, IMUs, and processors. The multisource sensing system minimizes the reprojection error and IMU residual error to obtain a reliable estimation of the node pose. By running the sensor fusion algorithm of binocular camera and IMU on the processor, the reliable pose information can be solved. The accuracy and reliability of the system position synchronization are improved, and a centimeter-level positioning accuracy is achieved. The hardware architecture of this function is shown in Figure7.Figure 7
Position synchronization of the Hybsync.In the Hybsync system, in order to improve the accuracy of positioning, it is necessary to achieve clock synchronization between the camera, IMU, and UWB. The details are shown in Figure8. First, the IMU and camera on the node use a tightly coupled optimization algorithm based on a sliding window to achieve time synchronization [22]. The cost function is constructed by using the invariance of feature points in adjacent frames. Hybsync uses UWB to obtain the accurate time of the system and outputs time sync information and positioning information.Figure 8
Clock synchronization between UWB, CAM, and IMU.In order to achieve the positioning function, Hybsync needs to obtain the pose information of each node. In this system, we use the state variables to express the pose information, which is expressed asX=pvq. In order to optimize the state variables, a tightly coupled fusion method is used to process visual information and inertial information, and the inverse depth of the feature points, expressed as λ, is also added to the state variables [22]. In order to fuse the information output by the camera and the IMU sensor, the spatial transformation relationship between them, expressed as Xcb, is also added to the state variable. Since the IMU will be affected by the zero offset and lead to accumulated errors in the positioning information, the gyroscope zero offset, expressed as bg, and the accelerometer zero offset, expressed as ba, are also taken into account. Then, the related cost function is constructed based on the sliding window algorithm, and nonlinear optimization is adopted to solve the state variables in real time [23]. Finally, the state variable to be estimated for each node in the system is shown in Equations (8)–(10).(8)Xi=x0,x1,⋯xn,xcb,λ0,λ1,⋯λm,(9)xk=pbkw,vbkw,qbkw,ba,bg,(10)xcb=pcb,qcb.xk represents the variable that the node needs to be optimized at time k, respectively, which represents the node’s position, velocity, rotation, and IMU bias. n represents the size of the sliding window, and λ represents the inverse depth of the image feature point. xcb represents camera-IMU transformation simultaneously.The state estimation problem of nodes can be modelled as a nonlinear optimization problem. The final optimized cost function is expressed as Equation (11).(11)minXirp−HpXi2+∑k∈BrBz^bk+1bk,XiPbk+1bk2+∑l,j∈CρrCz^lcj,XiPlcj2.rp represents the prior residuals. rB represents the IMU residuals, and rC represents the visual residuals. ρ represents a robust kernel function, which reduces the influence of outliers on the system. The above cost function is solved by using the Ceres optimization library. Finally, the optimal output of the positioning information of each node in the system is obtained.


## 2.3. Multinode Network Strategy

In a multinode cooperative detection system, more nodes usually mean a longer cooperative detection range, richer position information, and greater application value. Therefore, in practical applications, the Hybsync synchronization system must utilize multiple nodes. In order to reduce the complexity and improve the synchronization accuracy, the clock synchronization module is connected in the form of an ad hoc network, while the position synchronization module is connected through a local area network. Hybsync architecture under multinode working conditions is shown in Figure9. The Hybsync workflow is shown in Figure 10.Figure 9
Hybsync’s multinode network strategy.Figure 10
Hybsync synchronization workflow.The core clock synchronization algorithm of Hybsync draws on the IEEE 1588v2 protocol and makes certain improvements. By sharing the time message with a two-way time message exchange mechanism, we achieve low complexity, strong scalability, and fast synchronization speed, which makes our system suitable for wireless multinode high-precision mutual clock calibration within the cluster. We mainly use a two-way time message exchange between the master reference node and the synchronization node in the UWB channel to perform mutual calibration and obtain the timestamp [24]. Then, the timestamp is processed to perform clock taming, and nanosecond-level calibration of clock signals between nodes can be performed in a short time. When it is necessary to expand the scale of the node network, newly added nodes must satisfy the communication protocol we design.After being powered on, Hybsync’s clock synchronization system begins to work, and the nodes communicate with each other to record and transmit the accurate timestamp from the hardware layer. The control module calculates the time deviation, which is compared with the set threshold, and decides whether to perform coarse synchronization. Coarse synchronization is then implemented to reduce the time deviation between the two nodes. The output frequency of the oscillator is adjusted by the fine synchronization module which is mainly composed of the PID controller and the clock taming module. This provides the clock for the nodes in the wireless sensor network.After Hybsync is powered on, the position synchronization module also begins to work. The nodes communicate with the server and rely on ROS (Robot Operating System) to combine a network remotely. The server issues synchronous positioning commands to all nodes and receives positioning information from them at the same time, including pose, speed, and acceleration. The server can obtain access control to a single node, restart it, and output the original sensor information.In the described working state, Hybsync can realize high-precision PT synchronization of multiple nodes and output accurate time and position messages. In our test, the system supports the normal operation of 10 nodes, which demonstrates the correctness and rationality of the system design. In future large-scale networks, a corresponding number of nodes can be deployed as needed. Hybsync can easily be expanded to incorporate additional nodes.


## 3. Experiment

According to the framework described above, we design a Hybsync prototype integrated with a high-precision clock synchronization system and a high-precision position synchronization system. Our tests demonstrate nanosecond-level time alignment accuracy and centimeter-level positioning accuracy for each node in a multinode network in a dynamic and GNSS-denied environment through wireless two-way time comparison and mutual calibration technology and all-source fusion autonomous positioning technology. The Hybsync board has shell dimensions24cm×10cm×2cm, power consumption of 1.5 A at 5 V, and a weight of 661.0 g. The Hybsync prototype is shown in Figure 11.Figure 11
Hybsync prototype.The radio frequency band of Hybsync is 4 GHz, and the working voltage is 5 V which is provided by the mini_USB interface, while 28 V is provided by the DC power port.The test experiment of Hybsync system is designed according to different application scenarios. The performance of the Hybsync board is tested for representativeness, comprehensiveness, accuracy, and reproducibility.


### 3.1. Clock Synchronization Performance Test

In order to test the Hybsync performance, a multinode, long-distance clock synchronization performance test experiment is designed. The test system includes synchronization node A, reference node T, a host computer, an oscilloscope, and a time/frequency synchronization measuring instrument. During the test, the oscilloscope is used to detect the PPS signal output by the synchronization node and the reference node, and then, the real-time synchronization accuracy of the synchronization system can be measured by observing the time interval between the rising edges of the PPS. The time/frequency synchronization measuring instrument can display the results of synchronization in the form of real-time data. The host computer monitors the timestamp of the two-way time message exchange between the two nodes through serial communication and finally monitors the internal operation of the system. The test environment setup in the laboratory is shown in Figure12.Figure 12
Single node test environment with (i) master node T, (ii) oscilloscope, (iii) slave node A, (iv) mobile power bank, and (v) host computer.In order to verify the working conditions at long distances, a test environment is set up outdoors. To account for the synchronization convergence time of the clock system and the network complexity, the node network adopts the “one master and nine slaves” topology. The test scheme is displayed in Figure13.Figure 13
Multinode, long-distance test plan diagram.A time/frequency synchronization measuring instrument is used to test the time deviation between two nodes at a distance of 80 m to 100 m, and a four-channel oscilloscope is used to detect the real-time time deviation of multiple synchronization nodes. The test environment is shown in Figure14.Figure 14
Multinode test environment.At the beginning, we power on each node. When the synchronization node detects the time message sent by the reference node, it decodes the message and records the corresponding timestamp to complete the synchronization process. Then, the time-frequency measuring instrument is directly used to compare the time deviation between the reference node and the synchronization node to evaluate the performance of network clock synchronization. Meanwhile, we randomly choose a synchronization node and measure the time deviation between the node and the PPS signal output by the reference node, and the result is shown in Figure15.Figure 15
Synchronization result of 630 s continuous measurement: (i) power off during 50~95 s and (ii) power off during 260~265 s.The test lasts for 630 seconds. First, a coaxial cable of approximately 30 meters is used to test the time deviation between the reference node and the synchronization node after the synchronization system works stably. The test shows that the time deviation is within 10 ns. Then, the synchronization node is restarted at 50 s, and the control system does not adjust the clock tame module at the same time. It can be seen that the time deviation between nodes is maintained at a fixed value during 50 s-95 s. Afterwards, the fine synchronization module begins to work at 95 s, and the system converges to a synchronized state within 3 s. The time deviation at this time is within 10 ns stably and maintained around ±3 ns. At 260 s, the synchronization node is restarted again, and the synchronization starts immediately after the node is powered on. The synchronization completes within 3 s, and the clock synchronization system works stably for about 630 s. The time interval error between 265 s and 630 s is shown in Figure16 and is stable at about ±3 ns. The sliding window average time error (at 1 s window) during this period is within ±2 ns, as shown in Figure 17.Figure 16
Results after the clock synchronization system works stably.Figure 17
Average clock synchronization error.Four nodes in the “one master and nine slaves” topology are randomly selected, and the PPS signals are input to four channels of the oscilloscope through coaxial cables. We select the rising edge of one of the signals as a trigger and observe the time intervals output by the four nodes. The TIME/DIV of the oscilloscope is set to 5 ns. The result is shown in Figure18, where the real-time synchronization accuracy of the four signals is within 5 ns and high-precision synchronization is achieved.Figure 18
Multinode synchronization result.


### 3.2. Positioning Performance Test

In order to increase the diversity of nodes and facilitate debugging, the nodes of the position synchronization system are divided into two types: mobile nodes and fixed nodes. Mobile nodes are located on a remote-control car, as shown in Figure19, speed and direction of which are controlled by the experimenter. Its speed reaches up to 1.5 m/s. The car is equipped with sensors for positioning, consisting of a binocular camera (Intel Real-sense D435i) and its built-in IMU. We use a Jetson Nano for the processor, and we use GNSS-RTK to collect the true trajectory value of the mobile node to evaluate the accuracy of our position synchronization. The position of the fixed node is fixed, but the coordinates are known, and there is no need for a vehicle and a true value measuring device.Figure 19
Distributed node-position synchronization physical map with (i) RTK, (ii) vision sensor and IMU, and (iii) Hybsync.This experiment is carried out in an outdoor environment. The experimental environment is shown in Figure20. A relatively open outdoor environment with certain texture characteristics is chosen. The experimenter drives along a predetermined trajectory. However, there exist uncertain factors such as dynamic objects and instability of environmental textures, so the reliability and robustness of the sensor fusion positioning algorithm can be investigated to the maximum extent. Standard positioning devices using GNSS-RTK are installed on the node vehicle to obtain accurate reference position data. In order to evaluate the positioning performance, the actual trajectory is compared with the result of a standard positioning device.Figure 20
Positioning performance test environment with (i) mobile nodes locate on remote-control car.In the multinode positioning test, 10 nodes are deployed in the test site, where three nodes equipped with GNSS-RTK are regarded as mobile nodes, and the other seven nodes are used as fixed nodes. The schematic diagram of the test scenario is shown in Figure21. Three nodes on the remote-control car move in a circle around the flower bed. RTK calibrates the position for the fixed nodes before the test, and the mobile nodes are remotely controlled to move along a certain trajectory during the test. Each mobile node aligns its pose reference GNSS-RTK to the geodetic coordinate system and posts the pose information to the server via the LAN. The server then displays its results in a unified coordinate system. Finally, the server compares the positioning results of each mobile node with the true value of the GNSS-RTK position to judge the overall positioning performance of the position synchronization system and the stability of multinode coordination.Figure 21
Schematic diagram of positioning experiment scene.Figure22 shows the circular movement of three nodes around a circular flower bed. Node 1, node 2, and node 3 are the original trajectories of the three mobile nodes, and the other three are the trajectories of RTK, representing the ground truth. Through the partial enlarged view in Figure 22, it can be seen that the trajectory maintains a high degree of anastomosis. The experiment verifies the feasibility of the time position synchronization system and the effectiveness of the location algorithm. In the case of installation error, the node trajectory can still be well aligned with the RTK trajectory. The overall trajectory error is less than 7 cm. Table 2 lists the average positioning error of all of the nodes when the position synchronization system is running normally.Figure 22
Mobile node trajectory graph.Table 2
Positioning accuracy of position synchronization system.
Node labelRPE (relative pose error) (m)Node 10.0680836606Node 20.0450717215Node 30.0555678569In order to test the stability of the position synchronization system during operation, the real-time accuracy of mobile nodes is calculated as shown in Figure23, where the abscissa is the system running time and the ordinate is the real-time accuracy of the node.Figure 23
Dynamic node localization accuracy.In order to verify the positioning performance of a single node, another experiment was conducted to observe the positioning performance for a longer time on the same platform, which the sampling rate of the positioning system is 8.6 Hz. As shown in Figure24, the average positioning accuracy of single node positioning is within 0.08 m, which proves the robustness of the Hybsync’s positioning.Figure 24
Single node positioning accuracy.The series of experiments above show that the positioning synchronization system can support at least 10 nodes, and the number of nodes can be further expanded. The high-precision time and position synchronization system achieves a positioning accuracy of 7 cm when the driving distance is within 100 meters. In addition, the stability of the positioning algorithm can be seen by observing the real-time trajectory comparison.In summary, Hybsync can achieve nanosecond-level clock synchronization and centimeter-level positioning and can be used in scenarios such as collaborative detection. Compared with other existing wireless clock synchronization and positioning systems as shown in Table3 [25–28], Hybsync can still achieve or even surpass the existing wireless PNT systems in terms of clock synchronization accuracy and positioning accuracy without GNSS support. It fills up the gaps in the function’s realization of clock synchronization and positioning in GNSS-denied environments. At the same time, Hybsync uses shelf products, which gives it a cost advantage.Table 3
Comparison of Hybsync with other wireless solutions.
SchemeClock synchronization accuracyPositioning accuracyCostHybsync3 ns3~7 cmLowBasic GNSS (BeiDou satellite system)10~20 ns5~10 mHighTWSTFT1~5 ns--HighLocataNets [27]1~5 ns5~10 cmMediumPseudolite [28]5~10 ns1~10 cmMedium


## 3.1. Clock Synchronization Performance Test

In order to test the Hybsync performance, a multinode, long-distance clock synchronization performance test experiment is designed. The test system includes synchronization node A, reference node T, a host computer, an oscilloscope, and a time/frequency synchronization measuring instrument. During the test, the oscilloscope is used to detect the PPS signal output by the synchronization node and the reference node, and then, the real-time synchronization accuracy of the synchronization system can be measured by observing the time interval between the rising edges of the PPS. The time/frequency synchronization measuring instrument can display the results of synchronization in the form of real-time data. The host computer monitors the timestamp of the two-way time message exchange between the two nodes through serial communication and finally monitors the internal operation of the system. The test environment setup in the laboratory is shown in Figure12.Figure 12
Single node test environment with (i) master node T, (ii) oscilloscope, (iii) slave node A, (iv) mobile power bank, and (v) host computer.In order to verify the working conditions at long distances, a test environment is set up outdoors. To account for the synchronization convergence time of the clock system and the network complexity, the node network adopts the “one master and nine slaves” topology. The test scheme is displayed in Figure13.Figure 13
Multinode, long-distance test plan diagram.A time/frequency synchronization measuring instrument is used to test the time deviation between two nodes at a distance of 80 m to 100 m, and a four-channel oscilloscope is used to detect the real-time time deviation of multiple synchronization nodes. The test environment is shown in Figure14.Figure 14
Multinode test environment.At the beginning, we power on each node. When the synchronization node detects the time message sent by the reference node, it decodes the message and records the corresponding timestamp to complete the synchronization process. Then, the time-frequency measuring instrument is directly used to compare the time deviation between the reference node and the synchronization node to evaluate the performance of network clock synchronization. Meanwhile, we randomly choose a synchronization node and measure the time deviation between the node and the PPS signal output by the reference node, and the result is shown in Figure15.Figure 15
Synchronization result of 630 s continuous measurement: (i) power off during 50~95 s and (ii) power off during 260~265 s.The test lasts for 630 seconds. First, a coaxial cable of approximately 30 meters is used to test the time deviation between the reference node and the synchronization node after the synchronization system works stably. The test shows that the time deviation is within 10 ns. Then, the synchronization node is restarted at 50 s, and the control system does not adjust the clock tame module at the same time. It can be seen that the time deviation between nodes is maintained at a fixed value during 50 s-95 s. Afterwards, the fine synchronization module begins to work at 95 s, and the system converges to a synchronized state within 3 s. The time deviation at this time is within 10 ns stably and maintained around ±3 ns. At 260 s, the synchronization node is restarted again, and the synchronization starts immediately after the node is powered on. The synchronization completes within 3 s, and the clock synchronization system works stably for about 630 s. The time interval error between 265 s and 630 s is shown in Figure16 and is stable at about ±3 ns. The sliding window average time error (at 1 s window) during this period is within ±2 ns, as shown in Figure 17.Figure 16
Results after the clock synchronization system works stably.Figure 17
Average clock synchronization error.Four nodes in the “one master and nine slaves” topology are randomly selected, and the PPS signals are input to four channels of the oscilloscope through coaxial cables. We select the rising edge of one of the signals as a trigger and observe the time intervals output by the four nodes. The TIME/DIV of the oscilloscope is set to 5 ns. The result is shown in Figure18, where the real-time synchronization accuracy of the four signals is within 5 ns and high-precision synchronization is achieved.Figure 18
Multinode synchronization result.


## 3.2. Positioning Performance Test

In order to increase the diversity of nodes and facilitate debugging, the nodes of the position synchronization system are divided into two types: mobile nodes and fixed nodes. Mobile nodes are located on a remote-control car, as shown in Figure19, speed and direction of which are controlled by the experimenter. Its speed reaches up to 1.5 m/s. The car is equipped with sensors for positioning, consisting of a binocular camera (Intel Real-sense D435i) and its built-in IMU. We use a Jetson Nano for the processor, and we use GNSS-RTK to collect the true trajectory value of the mobile node to evaluate the accuracy of our position synchronization. The position of the fixed node is fixed, but the coordinates are known, and there is no need for a vehicle and a true value measuring device.Figure 19
Distributed node-position synchronization physical map with (i) RTK, (ii) vision sensor and IMU, and (iii) Hybsync.This experiment is carried out in an outdoor environment. The experimental environment is shown in Figure20. A relatively open outdoor environment with certain texture characteristics is chosen. The experimenter drives along a predetermined trajectory. However, there exist uncertain factors such as dynamic objects and instability of environmental textures, so the reliability and robustness of the sensor fusion positioning algorithm can be investigated to the maximum extent. Standard positioning devices using GNSS-RTK are installed on the node vehicle to obtain accurate reference position data. In order to evaluate the positioning performance, the actual trajectory is compared with the result of a standard positioning device.Figure 20
Positioning performance test environment with (i) mobile nodes locate on remote-control car.In the multinode positioning test, 10 nodes are deployed in the test site, where three nodes equipped with GNSS-RTK are regarded as mobile nodes, and the other seven nodes are used as fixed nodes. The schematic diagram of the test scenario is shown in Figure21. Three nodes on the remote-control car move in a circle around the flower bed. RTK calibrates the position for the fixed nodes before the test, and the mobile nodes are remotely controlled to move along a certain trajectory during the test. Each mobile node aligns its pose reference GNSS-RTK to the geodetic coordinate system and posts the pose information to the server via the LAN. The server then displays its results in a unified coordinate system. Finally, the server compares the positioning results of each mobile node with the true value of the GNSS-RTK position to judge the overall positioning performance of the position synchronization system and the stability of multinode coordination.Figure 21
Schematic diagram of positioning experiment scene.Figure22 shows the circular movement of three nodes around a circular flower bed. Node 1, node 2, and node 3 are the original trajectories of the three mobile nodes, and the other three are the trajectories of RTK, representing the ground truth. Through the partial enlarged view in Figure 22, it can be seen that the trajectory maintains a high degree of anastomosis. The experiment verifies the feasibility of the time position synchronization system and the effectiveness of the location algorithm. In the case of installation error, the node trajectory can still be well aligned with the RTK trajectory. The overall trajectory error is less than 7 cm. Table 2 lists the average positioning error of all of the nodes when the position synchronization system is running normally.Figure 22
Mobile node trajectory graph.Table 2
Positioning accuracy of position synchronization system.
Node labelRPE (relative pose error) (m)Node 10.0680836606Node 20.0450717215Node 30.0555678569In order to test the stability of the position synchronization system during operation, the real-time accuracy of mobile nodes is calculated as shown in Figure23, where the abscissa is the system running time and the ordinate is the real-time accuracy of the node.Figure 23
Dynamic node localization accuracy.In order to verify the positioning performance of a single node, another experiment was conducted to observe the positioning performance for a longer time on the same platform, which the sampling rate of the positioning system is 8.6 Hz. As shown in Figure24, the average positioning accuracy of single node positioning is within 0.08 m, which proves the robustness of the Hybsync’s positioning.Figure 24
Single node positioning accuracy.The series of experiments above show that the positioning synchronization system can support at least 10 nodes, and the number of nodes can be further expanded. The high-precision time and position synchronization system achieves a positioning accuracy of 7 cm when the driving distance is within 100 meters. In addition, the stability of the positioning algorithm can be seen by observing the real-time trajectory comparison.In summary, Hybsync can achieve nanosecond-level clock synchronization and centimeter-level positioning and can be used in scenarios such as collaborative detection. Compared with other existing wireless clock synchronization and positioning systems as shown in Table3 [25–28], Hybsync can still achieve or even surpass the existing wireless PNT systems in terms of clock synchronization accuracy and positioning accuracy without GNSS support. It fills up the gaps in the function’s realization of clock synchronization and positioning in GNSS-denied environments. At the same time, Hybsync uses shelf products, which gives it a cost advantage.Table 3
Comparison of Hybsync with other wireless solutions.
SchemeClock synchronization accuracyPositioning accuracyCostHybsync3 ns3~7 cmLowBasic GNSS (BeiDou satellite system)10~20 ns5~10 mHighTWSTFT1~5 ns--HighLocataNets [27]1~5 ns5~10 cmMediumPseudolite [28]5~10 ns1~10 cmMedium


## 4. Conclusions

In this paper, we proposed a Hybsync system that is based on UWB communication and multisensor fusion to achieve high-precision wireless clock synchronization and positioning. This system can use low-cost shelf products to achieve nanosecond clock synchronization accuracy. Hybsync is also equipped with multisensor fusion to achieve high-precision positioning. Experiments prove that the maximum clock synchronization error of Hybsync is 3 ns, and the positioning error is 7 cm. Although wired communication can achieve subnanosecond synchronization, with the development of highly flexible wireless sensor networks, synchronization schemes under wireless communication are very important. Compared with existing wireless clock synchronization solutions, Hybsync does not rely on GNSS and can achieve nanosecond synchronization accuracy with lower cost and more stable signals when GNSS is denied. At the same time, unlike other network positioning solutions, Hybsync is based on a high-precision clock synchronization system, which can greatly reduce positioning errors. In addition, it also supports multinode application scenarios. It is very convenient to increase the number of nodes and expand the network, which improves portability in practical applications. In a collaborative work scenario, Hybsync can be easily integrated into other devices and provides high-precision clock signals and positioning information for the devices.



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*Source: 9920567-2021-09-25.xml*