# An Effective Solution to Eliminate DC-Offset for Extracting the Phase and Frequency of Grid Voltage

Authors: Fehmi Sevilmiş; Hulusi Karaca
Journal: Mathematical Problems in Engineering
 (2021)

---

## Abstract

Recently, several approaches with the ability to reject the DC-offset in phase locked loop (PLL) methods have been developed. These approaches include different filtering structures which can be classified into two categories: prefiltering before the PLL input and in-loop filtering in the PLL control loop. As highlighted in the literature, the DC-offset rejection methods based on in-loop filtering have received less attention due to their slow dynamic performance. Therefore, this paper proposes an alternative DC-offset rejection technique as in-loop filtering of the PLL. The effectiveness of the proposed PLL is confirmed by simulation and experimental results.


---

## Body

## 1. Introduction

Rapid and precise extraction of grid voltage frequency and phase angle is a critical process for grid interactive converters and microgrids [1, 2]. According to grid codes, to ensure frequency and voltage support to the grid when faults emerge, interconnected renewable energy sources (RES) need fault ride through (FRT) ability. In practice, fast and smoothly tracking of the grid phase angle is specially wanted under frequency and phase variations, various short-term disturbances, voltage sags, DC-offset, and so on. So, research studies on how to develop the performance of PLLs connected to faulty grids without violating the grid code limits are a topic of maximum interest [3–6].Synchronous reference frame-phase locked loop (SRF-PLL) is broadly used thanks to advantages of its fast dynamic performance and simple structure [7, 8]. However, the performance of SRF-PLL is dramatically deteriorated in case of existence of DC-offset on grid voltages. The DC-offset component may occur due to measurement devices, DC injection from generation systems, A/D conversion processes, grid faults, and so on [9]. This component causes fundamental frequency fluctuations in phase angle and frequency measurement. To overcome this problem, several techniques have been suggested in the literature.In [10], a band-pass filter (BPF) is introduced in the prefiltering stage of the PLL to eliminate the DC-offset component. Although the BPF can completely remove the DC-offset, it significantly reduces the dynamic performance of the PLL. In [11], an adaptive first-order low-pass filter (LPF) is proposed at the PLL input. In this DC-offset removal method based on the study of [12], the grid voltages passed through LPF are subtracted from their original input voltages. This method is a simple approach to destroy the DC-offset; however, it may deteriorate the harmonic filtering capability of the system. In [13], five DC-offset removal techniques based on prefiltering and in-loop filtering are analyzed in detail. Among these methods, the cross-feedback network, complex-coefficient filter, and αβ-frame delayed signal cancellation (DSC) operator are used in prefilter stage of PLL while the notch filter (NF) and dq-frame DSC (dqDSC) operator are used in its in-loop filter stage. It is reported in [13] that the PLLs based on in-loop filtering effectively eliminate the DC-offset; however, they cause longer transient response time compared with the PLLs based on prefiltering. Some other PLLs designed to block the DC-offset can be accessed in [14–16].The objective of presented work is to develop the performance of the PLL caused by in-loop filtering in the presence of DC-offset. To minimize the transient response time, all-pass filter (APF)-based DSC operator (dqADSC-PLL) is proposed. In addition to poor dynamic performance of the standard dqDSC-PLL, another drawback of the dqDSC-PLL is that it has a discretization error in case of grid frequency variation even if the DSC operator is adaptive [17]. Thanks to the APF-based DSC operator, the discretization error that occurs in the standard dqDSC-PLL is eliminated in the proposed dqADSC-PLL.In brief, the main contributions of the proposed PLL can be listed as follows:(1)
The suggesteddqADSC-PLL has a simple structure and is easy to implement(2)
Its parameter design process is straightforward because only one parameter has to be set in its structure(3)
It considerably reduces the convergence time(4)
In addition to effectively blocking the DC-offset component, it minimizes the discretization errorsThe effectiveness and feasibility of the suggested method are validated by simulation and experimental studies and comparison with standarddqDSC-PLL and NF-PLL, which have the different filters in the loop of the PLL to cancel out the DC-offset disturbance component.


## 2. Description ofdqDSC-PLL and NF-PLL

### 2.1.dqDSC-PLL

Figure1 presents the topology of classical dqDSC-PLL. In the dqDSC-PLL, firstly, three-phase grid signals (Va, Vb, and Vc) are measured. Then, these signals are converted into synchronous reference frame components (Vd and Vq). The dqDSC-PLL has the DSC operator in PLL control loop. It also has a magnitude normalization processing after the DSC operator. Thus, the PLL control loop becomes independent against the grid voltage amplitude changes.Figure 1
Structure of the standarddqDSC-PLL.The DSC operator is a kind of finite impulse response (FIR) filter. The transfer function of thedqDSC operator is defined as follows [17]:(1)dqDSCns=1+e−T/ns2,where n is a delay factor and T is the fundamental cycle of grid voltages.n is chosen as 2 to block the DC-offset component. Substituting n = 2 and s = jω into (1), the frequency response of dqDSC2 can be obtained as(2)dqDSC2jω=cosωT4∠−ωT4.


### 2.2. NF-PLL

Figure2 demonstrates the block structure of the standard NF-PLL. Here, the measured grid signals are converted to dq-frame variables. The NF-PLL has a second-order notch filter as in-loop filtering of the PLL. As in dqDSC-PLL, the NF-PLL also has an amplitude normalization processing. Actually, the design of the NF-PLL is based on the replacement of the DSC operator in the dqDSC-PLL structure with a notch filter as illustrated in Figure 2.Figure 2
NF-PLL’s block structure.The NF which acts as a band rejection filter eliminates frequencies within a restricted band. It also passes other frequencies without change. The transfer function of second-order NF is expressed as(3)NFs=s2+ωnf2s2+ωnf/Qs+ωnf2,where Q and ωnf indicate the quality factor and notch frequency of NF, respectively.It is recommended in [13] to set the ωnf as 2π50 rad/s (notice that the NF is nonadaptive) for the 50 Hz system because DC-offset component converts to fundamental frequency disturbance component after Park transformation. The Q value directly affects the bandwidth of the filter. In case of large changes in the grid frequency, selecting wide bandwidth allows the DC-offset to be effectively destroyed. Therefore, it should be chosen as 0.707 [13]. However, the wide bandwidth causes dynamic performance of PLL to slow down.


## 2.1.dqDSC-PLL

Figure1 presents the topology of classical dqDSC-PLL. In the dqDSC-PLL, firstly, three-phase grid signals (Va, Vb, and Vc) are measured. Then, these signals are converted into synchronous reference frame components (Vd and Vq). The dqDSC-PLL has the DSC operator in PLL control loop. It also has a magnitude normalization processing after the DSC operator. Thus, the PLL control loop becomes independent against the grid voltage amplitude changes.Figure 1
Structure of the standarddqDSC-PLL.The DSC operator is a kind of finite impulse response (FIR) filter. The transfer function of thedqDSC operator is defined as follows [17]:(1)dqDSCns=1+e−T/ns2,where n is a delay factor and T is the fundamental cycle of grid voltages.n is chosen as 2 to block the DC-offset component. Substituting n = 2 and s = jω into (1), the frequency response of dqDSC2 can be obtained as(2)dqDSC2jω=cosωT4∠−ωT4.


## 2.2. NF-PLL

Figure2 demonstrates the block structure of the standard NF-PLL. Here, the measured grid signals are converted to dq-frame variables. The NF-PLL has a second-order notch filter as in-loop filtering of the PLL. As in dqDSC-PLL, the NF-PLL also has an amplitude normalization processing. Actually, the design of the NF-PLL is based on the replacement of the DSC operator in the dqDSC-PLL structure with a notch filter as illustrated in Figure 2.Figure 2
NF-PLL’s block structure.The NF which acts as a band rejection filter eliminates frequencies within a restricted band. It also passes other frequencies without change. The transfer function of second-order NF is expressed as(3)NFs=s2+ωnf2s2+ωnf/Qs+ωnf2,where Q and ωnf indicate the quality factor and notch frequency of NF, respectively.It is recommended in [13] to set the ωnf as 2π50 rad/s (notice that the NF is nonadaptive) for the 50 Hz system because DC-offset component converts to fundamental frequency disturbance component after Park transformation. The Q value directly affects the bandwidth of the filter. In case of large changes in the grid frequency, selecting wide bandwidth allows the DC-offset to be effectively destroyed. Therefore, it should be chosen as 0.707 [13]. However, the wide bandwidth causes dynamic performance of PLL to slow down.


## 3. ProposeddqADSC-PLL

### 3.1. Description

Figure3 illustrates the topology of suggested dqADSC-PLL, in which the standard DSC operator is replaced by the APF-based DSC operator in dq-frame. In this study, APF is preferred as a loop filter because it has many advantages such as low computational load, simple digital implementation, and fast transient response [18, 19].Figure 3
Structure of suggesteddqADSC-PLL.The APF has a low-pass filter feature. Transfer function of a first-order APF can be expressed as(4)APFs=ωn−sωn+s,where ωn is the nominal grid frequency.Substitutings = jω into (4), the gain and phase responses of the APF are determined as(5)APFjω=1∠−2arctanωωn.In Figure4, the Bode graph of the APF is shown. From the figure, the APF for all frequencies ensures unity gain (e.g., the APF does not change the amplitude of frequencies) and solely varies the input signal phase. When the obtained grid frequency equals the nominal frequency (where ωn = 2π50 rad/s), a 90° phase shift happens at the nominal frequency [19]. The structure of APF can be simply designed as in Figure 5. Here, qv is a 90° lagging-phase of input signal v.Figure 4
Bode plot of APF.Figure 5
Structure of APF.In the proposed APF-baseddqDSC2 operator, two APF modules are cascaded to eliminate the DC-offset (see Figure 6). In this way, a 180° phase shift is acquired by means of the cascaded two APFs. The transfer function of the cascaded APF (CAPF) module is obtained as(6)CAPFs=s2−2ωns+ωn2s2+2ωns+ωn2.Figure 6
Structure of APF-baseddqDSC2.As observed from Figure6, the transfer function of the APF-based dqDSC2 operator is easily expressed as follows:(7)dqADSC2s=s2+ωn2s2+2ωns+ωn2.Figure7 shows the Bode plot of the proposed dqADSC2 operator in dq-frame. While the fundamental frequency positive sequence (FFPS) transforms into DC component, DC-offset turns to fundamental frequency disturbance component after Park transformation. It can be seen from Figure 7 that the suggested operator ensures unity gain at the nominal grid frequency (0 Hz) and zero gain at −50 Hz in dq-frame. That is, the proposed dqADSC2 operator rejects the DC-offset and passes the FFPS component completely.Figure 7
Bode plot of the proposed APF-baseddqDSC2.In the proposed method, the controller design is different from that of the standarddqDSC-PLL and NF-PLL. As can be seen from the standard dqDSC-PLL and NF-PLL structures given in Figures 1 and 2, respectively, the conventional PI controllers are used in the control loop of these PLLs. However, as seen in Figure 3, PI is not used in the controlling stage of the proposed dqADSC-PLL method. Instead of the PI controller, the controller pattern in [20] is preferred. In this controller structure, there is only a simple gain (kp). Besides, this structure has a path to phase output. Thus, it has two poles at the origin, as given in (10). Although this controller pattern seems as a type-1 system, it is actually type-2 system. And it has two major advantages: (1) it increases dynamic performance significantly and (2) it provides a simpler controller parameter design procedure, which is discussed in the later section in detail.


### 3.2. Discretization of the Filters

Filters must be expressed in a discrete time domain in order to be used in practical applications. To discrete the APF given in continuous time domain as illustrated in Figure5, the third-order Adams–Bashforth method [21] is preferred in this paper. The reason for using this method is that it provides high accuracy in discretization process. The integrator in the APF is approximated by(8)1s⟺Ts1223z−1−16z−2+5z−31−z−1,where Ts denotes the sampling time. In other words, it is sufficient to replace the integrator in Figure 5 with the discrete form in (8) to discrete the APF.Similar to APF discretization, the approximate equation in (8) is considered for integrators in NF structure to discrete the NF.In order to discrete the standarddqDSC2 given in (1), the block structure in Figure 8 is used. In Figure 8, N is defined as T/(nTs). N is also an integer value. Here, Ts is the sampling time, n is a delay factor, and T is the grid period. If grid frequency is equal to 50 Hz, n is chosen as 2 to reject the DC-offset, and sampling frequency is set to be 10 kHz; N equals 100. When frequency variation occurs besides the DC-offset and the DSC operator is adaptive, N is calculated as a noninteger value. Therefore, N is rounded to the integer value. This situation causes the discretization error. Figure 9 shows the phase errors of the standard dqDSC-PLL and proposed dqADSC-PLL in presence of DC-offset with a +2 Hz frequency jump. Notice that the DSC operator in the standard dqDSC-PLL and the CAPF module in the proposed dqADSC-PLL are adaptive. It is observed from Figure 9 that the discretization error occurs on estimated phase angle in the standard dqDSC-PLL. This error is caused by rounding the N value to the nearest integer value. Since the proposed PLL uses APF instead of the DSC operator, there is no such a problem in the proposed PLL. This is another contribution of this paper to the literature.Figure 8
Discrete time implementation ofdqDSC2.Figure 9
Discretization error in presence of DC-offset with a +2 Hz frequency step change.


### 3.3. Parameter Design Guideline of ProposeddqADSC-PLL

In the proposeddqADSC-PLL, kp is the only one parameter to be designed. In order to design kp, as shown in Figure 10, the small-signal model of the dqADSC-PLL should be derived. As shown in (7), the second-order terms of the proposed dqADSC2 operator in the low frequency range can be neglected as follows:(9)dqADSC2s=s2+ωn2s2+2ωns+ωn2≈ωn22ωns+ωn2=ωn/2s+ωn/2.Figure 10
Small-signal model of thedqADSC-PLL.As understood from (9), the approximate transfer function of dqADSC2 is equivalent to a first-order low-pass filter, in which its cut-off frequency is ωn/2.The open-loop transfer function of thedqADSC-PLL by using the small-signal model is expressed as(10)Gols=Δθ+sθe=dqADSC2s1−dqADSC2s1+kps=ωn/2s+kps2.As can be understood from (10), the open-loop transfer function of the suggested method has two poles at the origin, which means it turns into a type-2 system.Using (10), the transfer function of phase error can be obtained as(11)Ges=θeΔθis=11+Gols.Using (11), the variation of the 2% settling time of the dqADSC-PLL under phase and frequency jump conditions, as shown in Figure 11, can be attained as a function of kp. It is shown that kp of the dqADSC-PLL is chosen as 61, which is the best value under both conditions.Figure 11
2% settling time ofdqADSC-PLL as a function of kp under phase and frequency jump.Finally, the performance of the proposeddqADSC-PLL and its model is compared to judge the accuracy of small-signal model under frequency and phase jump conditions. Figure 12 shows that its model predicts the dynamic behaviour of dqADSC-PLL with high accuracy.Figure 12
Accuracy of thedqADSC-PLL’s model.


### 3.4. Stability Analysis

To analyze the stability of the method, its model can be used. Based on the model given in Figure10, the closed-loop transfer function of the proposed dqADSC-PLL is determined as follows:(12)Gcls=Δθ+sΔθis=ωn/2s+kps2+ωn/2s+ωn/2kp.Considering the characteristic equation (12), the Routh–Hurwitz criterion is used for stability analysis of the system. According to this criterion, the suggested dqADSC-PLL is stable for ωn > 0 and kp > 0.


## 3.1. Description

Figure3 illustrates the topology of suggested dqADSC-PLL, in which the standard DSC operator is replaced by the APF-based DSC operator in dq-frame. In this study, APF is preferred as a loop filter because it has many advantages such as low computational load, simple digital implementation, and fast transient response [18, 19].Figure 3
Structure of suggesteddqADSC-PLL.The APF has a low-pass filter feature. Transfer function of a first-order APF can be expressed as(4)APFs=ωn−sωn+s,where ωn is the nominal grid frequency.Substitutings = jω into (4), the gain and phase responses of the APF are determined as(5)APFjω=1∠−2arctanωωn.In Figure4, the Bode graph of the APF is shown. From the figure, the APF for all frequencies ensures unity gain (e.g., the APF does not change the amplitude of frequencies) and solely varies the input signal phase. When the obtained grid frequency equals the nominal frequency (where ωn = 2π50 rad/s), a 90° phase shift happens at the nominal frequency [19]. The structure of APF can be simply designed as in Figure 5. Here, qv is a 90° lagging-phase of input signal v.Figure 4
Bode plot of APF.Figure 5
Structure of APF.In the proposed APF-baseddqDSC2 operator, two APF modules are cascaded to eliminate the DC-offset (see Figure 6). In this way, a 180° phase shift is acquired by means of the cascaded two APFs. The transfer function of the cascaded APF (CAPF) module is obtained as(6)CAPFs=s2−2ωns+ωn2s2+2ωns+ωn2.Figure 6
Structure of APF-baseddqDSC2.As observed from Figure6, the transfer function of the APF-based dqDSC2 operator is easily expressed as follows:(7)dqADSC2s=s2+ωn2s2+2ωns+ωn2.Figure7 shows the Bode plot of the proposed dqADSC2 operator in dq-frame. While the fundamental frequency positive sequence (FFPS) transforms into DC component, DC-offset turns to fundamental frequency disturbance component after Park transformation. It can be seen from Figure 7 that the suggested operator ensures unity gain at the nominal grid frequency (0 Hz) and zero gain at −50 Hz in dq-frame. That is, the proposed dqADSC2 operator rejects the DC-offset and passes the FFPS component completely.Figure 7
Bode plot of the proposed APF-baseddqDSC2.In the proposed method, the controller design is different from that of the standarddqDSC-PLL and NF-PLL. As can be seen from the standard dqDSC-PLL and NF-PLL structures given in Figures 1 and 2, respectively, the conventional PI controllers are used in the control loop of these PLLs. However, as seen in Figure 3, PI is not used in the controlling stage of the proposed dqADSC-PLL method. Instead of the PI controller, the controller pattern in [20] is preferred. In this controller structure, there is only a simple gain (kp). Besides, this structure has a path to phase output. Thus, it has two poles at the origin, as given in (10). Although this controller pattern seems as a type-1 system, it is actually type-2 system. And it has two major advantages: (1) it increases dynamic performance significantly and (2) it provides a simpler controller parameter design procedure, which is discussed in the later section in detail.


## 3.2. Discretization of the Filters

Filters must be expressed in a discrete time domain in order to be used in practical applications. To discrete the APF given in continuous time domain as illustrated in Figure5, the third-order Adams–Bashforth method [21] is preferred in this paper. The reason for using this method is that it provides high accuracy in discretization process. The integrator in the APF is approximated by(8)1s⟺Ts1223z−1−16z−2+5z−31−z−1,where Ts denotes the sampling time. In other words, it is sufficient to replace the integrator in Figure 5 with the discrete form in (8) to discrete the APF.Similar to APF discretization, the approximate equation in (8) is considered for integrators in NF structure to discrete the NF.In order to discrete the standarddqDSC2 given in (1), the block structure in Figure 8 is used. In Figure 8, N is defined as T/(nTs). N is also an integer value. Here, Ts is the sampling time, n is a delay factor, and T is the grid period. If grid frequency is equal to 50 Hz, n is chosen as 2 to reject the DC-offset, and sampling frequency is set to be 10 kHz; N equals 100. When frequency variation occurs besides the DC-offset and the DSC operator is adaptive, N is calculated as a noninteger value. Therefore, N is rounded to the integer value. This situation causes the discretization error. Figure 9 shows the phase errors of the standard dqDSC-PLL and proposed dqADSC-PLL in presence of DC-offset with a +2 Hz frequency jump. Notice that the DSC operator in the standard dqDSC-PLL and the CAPF module in the proposed dqADSC-PLL are adaptive. It is observed from Figure 9 that the discretization error occurs on estimated phase angle in the standard dqDSC-PLL. This error is caused by rounding the N value to the nearest integer value. Since the proposed PLL uses APF instead of the DSC operator, there is no such a problem in the proposed PLL. This is another contribution of this paper to the literature.Figure 8
Discrete time implementation ofdqDSC2.Figure 9
Discretization error in presence of DC-offset with a +2 Hz frequency step change.


## 3.3. Parameter Design Guideline of ProposeddqADSC-PLL

In the proposeddqADSC-PLL, kp is the only one parameter to be designed. In order to design kp, as shown in Figure 10, the small-signal model of the dqADSC-PLL should be derived. As shown in (7), the second-order terms of the proposed dqADSC2 operator in the low frequency range can be neglected as follows:(9)dqADSC2s=s2+ωn2s2+2ωns+ωn2≈ωn22ωns+ωn2=ωn/2s+ωn/2.Figure 10
Small-signal model of thedqADSC-PLL.As understood from (9), the approximate transfer function of dqADSC2 is equivalent to a first-order low-pass filter, in which its cut-off frequency is ωn/2.The open-loop transfer function of thedqADSC-PLL by using the small-signal model is expressed as(10)Gols=Δθ+sθe=dqADSC2s1−dqADSC2s1+kps=ωn/2s+kps2.As can be understood from (10), the open-loop transfer function of the suggested method has two poles at the origin, which means it turns into a type-2 system.Using (10), the transfer function of phase error can be obtained as(11)Ges=θeΔθis=11+Gols.Using (11), the variation of the 2% settling time of the dqADSC-PLL under phase and frequency jump conditions, as shown in Figure 11, can be attained as a function of kp. It is shown that kp of the dqADSC-PLL is chosen as 61, which is the best value under both conditions.Figure 11
2% settling time ofdqADSC-PLL as a function of kp under phase and frequency jump.Finally, the performance of the proposeddqADSC-PLL and its model is compared to judge the accuracy of small-signal model under frequency and phase jump conditions. Figure 12 shows that its model predicts the dynamic behaviour of dqADSC-PLL with high accuracy.Figure 12
Accuracy of thedqADSC-PLL’s model.


## 3.4. Stability Analysis

To analyze the stability of the method, its model can be used. Based on the model given in Figure10, the closed-loop transfer function of the proposed dqADSC-PLL is determined as follows:(12)Gcls=Δθ+sΔθis=ωn/2s+kps2+ωn/2s+ωn/2kp.Considering the characteristic equation (12), the Routh–Hurwitz criterion is used for stability analysis of the system. According to this criterion, the suggested dqADSC-PLL is stable for ωn > 0 and kp > 0.


## 4. Simulation and Experimental Results

The effectiveness of suggesteddqADSC-PLL is validated by simulation and experimental studies. The simulation studies are realized in Matlab/Simulink software. The experimental studies are performed by a TMS320F28335 DSP. Sampling frequency, magnitude of the grid voltages, and nominal grid frequency (ωn) are tuned to 10 kHz, 1 p.u., and 2π50 rad/s, respectively. Moreover, the standard dqDSC-PLL and NF-PLL [13] are carried out to compare their performance with the proposed dqADSC-PLL. In the experiments, the grid voltages are created internally in the DSP. All PLLs are employed in the DSP. To demonstrate the grid voltages, phase error, and estimated frequency on the oscilloscope, these signals are passed through external low-pass filter. Figure 13 shows the experimental setup.Figure 13
Experimental setup.The control parameter (kp) of the proposed PLL is obtained as 61 in the previous section. The parameters of the standard dqDSC-PLL and NF-PLL are chosen as in [13] (e.g., kp = 82.84 and ki = 2842.7 for dqDSC-PLL; kp = 92, and ki = 3507.1 for NF-PLL).To compare the DC-offset rejection methods under different grid scenarios, four test conditions are considered as follows:(i)
Test 1. The frequency jumps from 50 Hz to 52 Hz suddenly.(ii)
Test 2. The grid signals subject a phase jump of +40°. The frequency is set at 50 Hz.(iii)
Test 3. The DC-offset components are added to all phases. The values of these components are 0.2, 0.1, and −0.2 p.u. for phases A, B, and C, respectively. The grid frequency is tuned as 50 Hz.(iv)
Test 4. The same DC-offsets are added to each phase as in the test 3. However, the frequency is tuned as 52 Hz simultaneously. Notice that all PLLs are adaptive during this test.Figure14 demonstrates the estimated frequency results for the first test. As shown, the suggested dqADSC-PLL presents the fast dynamic response. Its settling time is about 1.85 periods. The settling times of the standard dqDSC-PLL and NF-PLL are about 2.9 periods and 2.6 periods, respectively.Figure 14
Frequency jump of +2 Hz (Test 1): (a) simulation results; (b) experimental results.
(a)(b)Figure15 demonstrates the phase error results for the second test. It is shown that the suggested dqADSC-PLL ensures a fast dynamic performance again. The settling time of the proposed PLL (around 2.5 periods) is lower than that of the standard dqDSC-PLL (around 3.6 periods) and NF-PLL (around 3.2 periods). The phase-angle phase overshoot is around 8.7%, 13.8%, and 14.3% for the proposed dqADSC-PLL, standard dqDSC-PLL, and NF-PLL, respectively. This test demonstrates that the proposed DC-offset rejection method has the best performance from the point of both settling time and phase overshoot.Figure 15
Phase jump of+40° (Test 2): (a) simulation results; (b) experimental results.
(a)(b)Figure16 shows the experimental results of phase error for the third test. It is illustrated that all PLLs in the steady-state have no phase-angle error. However, the suggested PLL offers a better dynamic performance than that of the dqDSC-PLL and NF-PLL. On the other hand, if frequency change occurs besides the DC-offset, phase error occurs in all PLL methods. To overcome such a situation, the DSC operator in the standard dqDSC-PLL, the NF in the standard NF-PLL, and the CAPF module in the proposed dqADSC-PLL can be adapted against the frequency changes. Figure 17 illustrates the phase errors of adaptive PLL methods for the fourth test condition. As shown, the proposed dqADSC-PLL presents a quite fast dynamic performance. Furthermore, the proposed DC-offset rejection method provides a lower phase error overshoot compared with two other PLLs.Figure 16
DC-offset at 50 Hz (Test 3): (a) simulation results; (b) experimental results.
(a)(b)Figure 17
DC-offset at 52 Hz (Test 4): (a) simulation results; (b) experimental results.
(a)(b)


## 5. Conclusions

In this paper, a highly effective and simple structured DC-offset elimination technique as in-loop filtering of the PLL is proposed. The proposed method calleddqADSC-PLL offers a lower settling time than that of the standard dqDSC-PLL and NF-PLL under all test conditions. Furthermore, it eliminates the discretization errors in the standard dqDSC-PLL thanks to the APF. Several numerical results verify the effectiveness of the suggested dqADSC-PLL.



---

*Source: 9742683-2021-09-23.xml*