# Single-Resistance-Controlled Sinusoidal Oscillator Using Single VD-DIBA

Authors: K. L. Pushkar; D. R. Bhaskar; Dinesh Prasad
Journal: Active and Passive Electronic Components
 (2013)

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## Abstract

This paper presents a new single-resistance-controlled sinusoidal oscillator (SRCO).  The proposed oscillator employs only one voltage differencing differential input buffered amplifier (VD-DIBA), two resistors, and two grounded capacitors. The proposed configuration offers the following advantageous features: (i) independent control of condition of oscillation and frequency of oscillation, (ii) low active and passive sensitivities, and (iii)  a very good frequency stability. The validity of the proposed SRCO has been established by SPICE simulations using 0.35μm MIETEC technology.


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## Body

## 1. Introduction

Realisation of oscillators and active filters has become important research area in analog circuit design. Recently, various modern active building blocks have been introduced in [1], and VD-DIBA is one of them which is emerging as a very flexible and versatile building block for analog signal processing and has been used earlier for realizing a number of functions. Single-resistance-controlled sinusoidal oscillators (SRCOs) play an important role in control systems, signal processing, communication, and instrumentation and measurement systems [2–4]. SRCOs employing different active building blocks have attracted considerable attention of the researchers due to their several advantages over traditional op-amp-based SRCOs; see [5–15] and the references cited therein. The applications, advantages, and usefulness of VD-DIBA have now been recognised in the realisation of first-order all-pass filter, in simulation of inductors and in the realisation of sinusoidal oscillator [16–18]. However, to the best of the knowledge and belief of the authors, none of the SRCOs using single VD-DIBA has yet been presented in the literature so far. Therefore, the purpose of this paper is to present a new SRCO using a single VD-DIBA along with a bare minimum number of four passive components. The proposed configuration offers (i) independent control of condition of oscillation and frequency of oscillation, (ii) low active and passive sensitivities, and (iii) a very good frequency stability. The workability of the proposed SRCO has been established by SPICE simulations using 0.35 μm MIETEC technology.


## 2. New Oscillator Configuration

The schematic symbol and behavioral model of the VD-DIBA are shown in Figures1(a) and 1(b), respectively. The model includes two controlled sources: the current source controlled by differential voltage (V+-V-), with the transconductance gm, and the voltage source controlled by differential voltage (Vz-Vv), with the unity voltage gain. The VD-DIBA can be described by the following set of equations:
(1)(I+I-IzIvVw)=(0000000000gm-gm00000000001-10)(V+V-VzVvIw).
A routine circuit analysis of Figure 2 yields the following characteristic equation:
(2)s2C1C2R1R2+sR1{2C1-C2gmR2}+1=0.
Thus, the condition of oscillation (CO) and frequency of oscillation (FO) are given by
(3)CO:{2C1-C2gmR2}≤0,(4)FO:f0=12π1C1C2R1R2.
Therefore, it is seen that FO is independently controllable by resistor R1 and CO is controlled by gm.(a) Schematic symbol and (b) behavioural model of VD-DIBA.
(a)
(b)Figure 2
The proposed configuration.


## 3. Frequency Stability Analysis

Frequency stability may be considered to be an important figure of merit of an oscillator. The frequency stability factor is defined asSF=dϕ(u)/du, where u=ω/ω0 is the normalized frequency, and ϕ(u) represents the phase function of the open loop transfer function of the oscillator circuit, with C1=C2=C,  R2=2R,  R=1/gm, and R1=R/n;  SF for the proposed SRCO is found to be
(5)SF=2n{-2n2n+1}≈-2nforn≫1.
Thus, for larger values of n, the oscillator enjoys a very good frequency stability.


## 4. Nonideal Analysis and Sensitivity Performance

LetRZ and CZ denote the parasitic resistance and parasitic capacitance of the Z-terminal of the VD-DIBA. Taking the nonidealities into account, namely, the voltage of  W-terminal VW=(β+VZ-β-VV), where β+=1-εp  (εp≪1) and β-=1-εn  (εn≪1) denote the voltage tracking errors of Z-terminal and V-terminal of the VD-DIBA, respectively, then the expressions for CO and FO become
(6)CO:{(β-+1)(C1+Cz)R2R1-C2{(β+-1)R2R1+β+gmR2+R2Rz}}≤0,(7)FO:ω0={β+-(β-+1)(β+-1)}+(β-+1)(R1/RZ)(C1+CZ)C2R1R2.
The left-hand side of (3) with the component values shown in Section 4 turns out to be −0.812 which is in accordance with (3) (<0). On the other hand, when left-hand side of (6) is calculated using the components and parasitic values in Section 4, it turns out to be −0.7992. It is therefore seen that both values are quite close from these numerical examples; it can be inferred that by considering C1≫CZ, and   R1, R2≪RZ,  (6) becomes {2C1-C2R2(gm+1/Rz)}≤0 which shows that (6) is almost the same as (3).Its active and passive sensitivities can be found as(8)SC1ω0=-12C1C1+CZ,SC2ω0=-12,SCZω0=-12CZC1+CZ,SR1ω0=-12{1+((β-+1)(R1/RZ))/(β+-(β-+1)(β+-1))},(9)SR2ω0=-12,SRZω0=-12RZ(β-+1)R1{β+-(β-+1)(β+-1)+(β-+1)R1},Sβ+ω0=12β+{(β-+1)(R1/RZ)-β-}{1+(β+-1)(R1/RZ-β-)},Sβ-ω0=12β-{R1/RZ-(β+-1)}{1+(β+-1)(R1/RZ-β-)}.
In the ideal case, the various sensitivities of FO with respect to R1,  R2,  C1, and C2 are found to be
(10)SR1ω0=SR2ω0=SC1ω0=SC2ω0=-12.
Considering the typical values of various parasitic, for example, Cz=0.81 pF, Rz=53 kΩ, and β+=β-=1 along with C1=C2=0.01 nF,  R1=1 kΩ, and R2=9.5 kΩ, the various sensitivities are found to be  SC1ω0=-0.4625,  SC2ω0=-0.5,  SCZω0=-0.03747,  SR1ω0=-0.3681,  SR2ω0=-0.5, SRZω0=-0.132,  Sβ+ω0=-0.17925, and  Sβ-ω0=0.0896  which are all low.


## 5. Simulation Results

To confirm theoretical analysis, the proposed SRCO was simulated using CMOS VD-DIBA (as shown in Figure3). The passive elements were selected as C1=C2=0.01 nF, R1=1 KΩ, and R2=9.5 KΩ. The transconductance of VD-DIBA was controlled by bias voltage VB1. PSPICE-generated output waveforms indicating transient and steady state responses are shown in Figures 4(a) and 4(b), respectively. These results, thus, confirm the validity of the proposed configuration. Figure 5 shows the output spectrum, where the total harmonic distortion (THD) is found to be 2.77%. Figure 6 shows the variation of frequency with resistance R1. A comparison with other previously known SRCOs using different active building blocks has been given in Table 2.Figure 3
Proposed CMOS implementation of VD-DIBA;VDD=-VSS=2 V,  VB1=-0.44 V, VB2=VB3=-0.22V, and VB4=-0.9V.(a) Transient output waveform. (b) Steady state response of the output.
(a)
(b)Figure 5
Simulation result of the output spectrum.Figure 6
Variation of frequency with resistanceR1.The CMOS VD-DIBA is implemented using 0.35μm MIETEC real transistor model which is listed in  Box 1.Box 1
.MODEL N NMOS (LEVEL = 3TOX = 7.9E-9NSUB = 1E17GAMMA = 0.5827871PHI = 0.7VTO = 0.5445549
DELTA = 0UO = 436.256147ETA = 0THETA = 0.1749684KP = 2.055786E-4VMAX = 8.309444E4KAPPA = 0.2574081
RSH = 0.0559398NFS = 1E12TPG = 1XJ = 3E-7LD = 3.162278E-11WD = 7.046724E-8 CGDO = 2.82E-10
CGSO =2.82E-10CGBO = 1E-10CJ = 1E-3PB = 0.9758533MJ = 0.3448504CJSW = 3.777852E-10
MJSW = 0.3508721)
.MODEL P PMOS (LEVEL = 3TOX = 7.9E-9NSUB = 1E17GAMMA = 0.4083894PHI = 0.7VTO = −0.7140674
DELTA = 0UO = 212.2319801ETA = 9.999762E-4THETA = 0.2020774KP = 6.733755E-5VMAX = 1.181551E5
KAPPA = 1.5RSH = 30.0712458NFS = 1E12TPG = -1XJ = 2E-7LD = 5.000001E-13WD = 1.249872E-7
CGDO =3.09E-10CGSO = 3.09E-10CGBO = 1E-10CJ = 1.419508E-3PB = 0.8152753MJ = 0.5
CJSW =4.813504E-10MJSW = 0.5)Aspect ratios of transistors used in Figure3 are given in Table 1.Table 1
Transistor
W/L (µm)
M1–M6
14/1
M7–M9
14/0.35
M10–M18
4/1
M19–M22
7/0.35Table 2
Reference
Active component(s)
Groundedcapacitors
Floating capacitors
Resistors
CO and FO independently controllable
[5]
1
1
1
3
Yes
[6]
1
1
1
3
Yes
[7]
2
2
0
3
Yes
[8]
1
1
1
3
Yes
[9]
1
2
0
4
No
[10]
1
2
0
3
Yes
[11]
1
2
0
3/2
Yes
[12]
1
1 (virtually grounded)
1
3
Yes (only in second topology of Table1)
[13]
1
1 (virtually grounded)
1
3
No
[14]
1
1
1
2
Yes
[18]
2
2
0
1
Yes
[15]
1
2
0
2
Yes
Proposed
1
2
0
2
Yes


## 6. Conclusions

A new application of a recently introduced VD-DIBA in the realisation of SRCO has been proposed. The proposed configuration employs a minimum possible number of passive elements (namely, two resistors and two grounded capacitors) and yet offers independent control of FO through the resistorR1 and CO through the transconductance gm (hence, the circuit enjoys the electronic control of CO), low active and passive sensitivities, and a very good frequency stability. This paper thus added a new application circuit to the existing repertoire of VD-DIBA-based application circuits.



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*Source: 971936-2013-04-16.xml*