# Current Controlled Differential Difference Current Conveyor Transconductance Amplifier and Its Application as Wave Active Filter

Authors: Neeta Pandey; Praveen Kumar; Jaya Choudhary
Journal: ISRN Electronics
 (2013)

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## Abstract

This paper proposes current controlled differential difference current conveyor transconductance amplifier (CCDDCCTA), a new active building block for analog signal processing. The functionality of the proposed block is verified via SPICE simulations using 0.25μm TSMC CMOS technology parameters. The usefulness of the proposed element is demonstrated through an application, namely, wave filter. The CCDDCCTA-based wave equivalents are developed which use grounded capacitors and do not employ any resistors. The flexibility of terminal characteristics is utilized to suggest an alternate wave equivalents realization scheme which results in compact realization of wave filter. The feasibility of CCDDCCTA-based wave active filter is confirmed through simulation of a third-order Butterworth filter. The filter cutoff frequency can be tuned electronically via bias current.


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## Body

## 1. Introduction

The current mode approach for analog signal processing circuits and systems has received considerable attention and emerged as an alternate method besides the traditional voltage mode circuits [1] due to its potential performance features like wide bandwidth, less circuit complexity, wide dynamic range, low power consumption, and high operating speed. The current mode active elements are appropriate to operate with signals in current, voltage, or mixed mode and are gaining acceptance as building blocks in high performance circuit designs which is clear from the availability of wide variety of current mode active elements [2–10]. Recently some analog building blocks [11–16] based on current conveyor variants and transconductance amplifier (TA) cascades in monolithic chip are proposed in open literature which gives compact implementation of signal processing circuits and systems. The examples of such blocks are current conveyor transconductance amplifier (CCTA) [11, 12], current controlled current conveyor transconductance amplifier (CCCCTA) [13], differential voltage current conveyor transconductance amplifier (DVCCTA) [14], differential voltage current controlled conveyor transconductance amplifier DVCCCTA [15], and differential difference current conveyor transconductance amplifier (DDCCTA) [16].A new active building block, namely, current controlled differential difference current conveyor transconductance amplifier (CCDDCCTA) which has current controlled differential difference current conveyor (CCDDCC) [10] as input block followed by a TA. The CCDDCCTA possesses all the good properties of CCCCTA and DVCCCTA including the possibility of inbuilt tuning of the parameters of the signal processing circuits to be implemented and also all the versatile and special properties of DDCC such as easy implementation of differential and floating input circuits [9, 17, 18]. The CCDDCCTA can be implemented using separate CCDDCC and OTA analog building blocks, but it will be more convenient and useful if CCDDCCTA is implemented in monolithic chip which will result in compact implementation of signal processing circuits and systems. The analytical formulations for port relationship of the proposed CCDDCCTA circuit are presented in Section 2. Section 3 elaborates the concept of wave filter followed by derivation of CCDDCCTA-based wave equivalent of series inductor. The methodology for obtaining wave equivalent of other passive elements is outlined. An alternate scheme for wave equivalents of shunt capacitor and inductor is also presented. A third order Butterworth filter has been designed using the outlined approach and is presented in Section 4 followed by conclusion. The functionality has been verified through SPICE simulation using 0.25 μm TSMC CMOS technology parameters.


## 2. Proposed CCDDCCTA

The CCDDCCCTA is an extension of CCDDCC [10] and consists of differential amplifier, translinear loop, and transconductance amplifier. The port relationships of the CCDDCCTA as shown in Figure 1 can be characterized by the following matrix:
(1)[IY1IY2IY3VXIZIO]=[0000000000000000001-11Rx000001000000-gm0][VY1VY2VY3IXVZVO],
where Rx is the intrinsic resistance at X terminal, and gm is the transconductance from Z terminal to O terminal of the CCDDCCTA.Figure 1
Schematic symbol of CCDDCCTA.The CMOS-based internal circuit of CCDDCCTA in CMOS is depicted in Figure2. The transistors M1 to M10 present differential difference voltage (VY1-VY2+VY3) at gate terminal of M6, and transistors M11 to M23 form translinear loop and transistors M24 to M31 are connected as transconductance amplifier. The analytical expressions for port relationships are obtained in the following sub sections.Figure 2
CMOS implementation of CCDDCCTA.


### 2.1. Relationship between Voltages of X Port and Y1, Y2, and Y3 Ports

The analysis of the differential difference part and translinear loop (comprising of transistors fromM1 to M21) of the circuit of Figure 2 gives the voltage at X port as
(2)VX=β1VY1-β2VY2+β3VY3+εV+IXRX,
where RX=1/(gm16+gm18)(3)β1=1P1(gm5gm8+gm5(gm6gm7-gm5gm8)gm5+gm6),β2=1P1(gm2gm7+gm2(gm2gm7-gm3gm8)gm2+gm3),β3=1P1(gm3gm8+gm3(gm2gm7-gm3gm8)gm2+gm3),εV=IBP1(gm2gm7-gm3gm8gm2+gm3+gm6gm7-gm5gm8gm5+gm6)+IB1gm16+gm18(gm20gm12gm18gm11gm17gm19-gm13gm16gm11gm15),P1=gm6gm7-gm6(gm6gm7-gm5gm8)gm5+gm6,
where IB represents the current flowing through transistor M1, M4, and M9. With matched transconductances gm2=gm3=gm5=gm6 and gm7=gm8, VX is obtained as
(4)VX=VY1-VY2+VY3+IXRX.


### 2.2. Relationship between Currents atZ and X Ports

The analysis of the portion of the circuit comprising of transistors fromM11 to M23 of the circuit of Figure 2 gives
(5)IZ=αIX+ε1,
where
(6)α=1gm16+gm18(gm18gm22gm21+gm23gm16gm14),ε1=(gm12gm20gm18gm22gm11gm17gm19gm21-gm13gm16gm23gm11gm14gm15)+1gm16+gm18(gm18gm22gm21+gm23gm16gm14)×(-gm12gm18gm20gm11gm17gm19+gm13gm16gm11gm15)IB1.
For matched transistors, (6) reduced to
(7)IZ=IX.


### 2.3. Relation for Currents at O Port

The transistor comprising fromM24 to M31 forms transconductance amplifier (TA). Assuming gate voltages of transistors M24 and M25 as VT1 and VT2, respectively, the output currents IO may be found as
(8)IO=γ1VT1-γ2VT2+ε2,
where
(9)γ1=-1gm24+gm25(gm24gm25gm29gm28+gm24gm25gm27gm31gm26gm30),γ2=-1gm24+gm25(gm24gm25gm29gm28+gm24gm25gm27gm31gm26gm30),ε2=IB2gm24+gm25(-gm24gm29gm28+gm25gm27gm31gm26gm30).
With gm24=gm25=gm, gm26=gm27, gm28=gm29, and gm30=gm31, (8) reduced to
(10)IO=gmVT1-gmVT2,
as VT1=0 and VT2=VZ(11)IO=-gmVZ,
where
(12)gm=2μCOX(WL)24,25IB2.


### 2.4. Simulation

To verify the port relationship of proposed CCDDCCTA, PSPICE simulations have been carried out using TSMC 0.25μm CMOS process model parameters. The aspect ratio of various transistors for CCDDCCTA is given in Table 1. The supply voltages of VDD=-VSS=1.25 V and VBB=-0.8 V are used. The DC transfer characteristics of the proposed CCDDCCTA from Y1, Y2, and Y3 terminals to X terminal are shown in Figure 3. The variation of current at Z terminal with X terminal current is shown in Figure 4. Figures 3 and 4 verify the port relationships. The variation of resistance, RX with respect to bias current IB1, is shown in Figure 5. The transconductance of CCDDCCTA is bias current controllable which is depicted in Figure 6 by varying IB2 from 0 to 800 μA. There is decrease in transconductance for bias currents larger than 400 μA. This is due to transistors M24,M25 entering in linear region of operation from saturation region.Table 1
Aspect ratio of various transistors.
Transistors
W (μm)/L (μm) ratio
M1, M4, M9, M11–M14, M23, and M30-M31
3.0/0.25
M2-M3, M5-M6
1.0/0.25
M7-M8
5.0/0.25
M10
12.5/0.25
M15
8.0/0.25
M16
9.0/0.25
M18
4.5/0.25
M27
4.35/0.25
M17, M19–M22, M24-M25, M26, and M28-M29
5.0/0.25DC transfer characteristic for voltage transfer from (a)Y1 port to X port, (b) Y2 port to X port, and (c) Y3 port to X port.
(a)
(b)
(c)Figure 4
DC transfer characteristic for current transfer fromX port to Z port.Figure 5
Variation of resistance with bias currentIB1.Figure 6
Variation of transconductance with bias currentIB2.


## 2.1. Relationship between Voltages of X Port and Y1, Y2, and Y3 Ports

The analysis of the differential difference part and translinear loop (comprising of transistors fromM1 to M21) of the circuit of Figure 2 gives the voltage at X port as
(2)VX=β1VY1-β2VY2+β3VY3+εV+IXRX,
where RX=1/(gm16+gm18)(3)β1=1P1(gm5gm8+gm5(gm6gm7-gm5gm8)gm5+gm6),β2=1P1(gm2gm7+gm2(gm2gm7-gm3gm8)gm2+gm3),β3=1P1(gm3gm8+gm3(gm2gm7-gm3gm8)gm2+gm3),εV=IBP1(gm2gm7-gm3gm8gm2+gm3+gm6gm7-gm5gm8gm5+gm6)+IB1gm16+gm18(gm20gm12gm18gm11gm17gm19-gm13gm16gm11gm15),P1=gm6gm7-gm6(gm6gm7-gm5gm8)gm5+gm6,
where IB represents the current flowing through transistor M1, M4, and M9. With matched transconductances gm2=gm3=gm5=gm6 and gm7=gm8, VX is obtained as
(4)VX=VY1-VY2+VY3+IXRX.


## 2.2. Relationship between Currents atZ and X Ports

The analysis of the portion of the circuit comprising of transistors fromM11 to M23 of the circuit of Figure 2 gives
(5)IZ=αIX+ε1,
where
(6)α=1gm16+gm18(gm18gm22gm21+gm23gm16gm14),ε1=(gm12gm20gm18gm22gm11gm17gm19gm21-gm13gm16gm23gm11gm14gm15)+1gm16+gm18(gm18gm22gm21+gm23gm16gm14)×(-gm12gm18gm20gm11gm17gm19+gm13gm16gm11gm15)IB1.
For matched transistors, (6) reduced to
(7)IZ=IX.


## 2.3. Relation for Currents at O Port

The transistor comprising fromM24 to M31 forms transconductance amplifier (TA). Assuming gate voltages of transistors M24 and M25 as VT1 and VT2, respectively, the output currents IO may be found as
(8)IO=γ1VT1-γ2VT2+ε2,
where
(9)γ1=-1gm24+gm25(gm24gm25gm29gm28+gm24gm25gm27gm31gm26gm30),γ2=-1gm24+gm25(gm24gm25gm29gm28+gm24gm25gm27gm31gm26gm30),ε2=IB2gm24+gm25(-gm24gm29gm28+gm25gm27gm31gm26gm30).
With gm24=gm25=gm, gm26=gm27, gm28=gm29, and gm30=gm31, (8) reduced to
(10)IO=gmVT1-gmVT2,
as VT1=0 and VT2=VZ(11)IO=-gmVZ,
where
(12)gm=2μCOX(WL)24,25IB2.


## 2.4. Simulation

To verify the port relationship of proposed CCDDCCTA, PSPICE simulations have been carried out using TSMC 0.25μm CMOS process model parameters. The aspect ratio of various transistors for CCDDCCTA is given in Table 1. The supply voltages of VDD=-VSS=1.25 V and VBB=-0.8 V are used. The DC transfer characteristics of the proposed CCDDCCTA from Y1, Y2, and Y3 terminals to X terminal are shown in Figure 3. The variation of current at Z terminal with X terminal current is shown in Figure 4. Figures 3 and 4 verify the port relationships. The variation of resistance, RX with respect to bias current IB1, is shown in Figure 5. The transconductance of CCDDCCTA is bias current controllable which is depicted in Figure 6 by varying IB2 from 0 to 800 μA. There is decrease in transconductance for bias currents larger than 400 μA. This is due to transistors M24,M25 entering in linear region of operation from saturation region.Table 1
Aspect ratio of various transistors.
Transistors
W (μm)/L (μm) ratio
M1, M4, M9, M11–M14, M23, and M30-M31
3.0/0.25
M2-M3, M5-M6
1.0/0.25
M7-M8
5.0/0.25
M10
12.5/0.25
M15
8.0/0.25
M16
9.0/0.25
M18
4.5/0.25
M27
4.35/0.25
M17, M19–M22, M24-M25, M26, and M28-M29
5.0/0.25DC transfer characteristic for voltage transfer from (a)Y1 port to X port, (b) Y2 port to X port, and (c) Y3 port to X port.
(a)
(b)
(c)Figure 4
DC transfer characteristic for current transfer fromX port to Z port.Figure 5
Variation of resistance with bias currentIB1.Figure 6
Variation of transconductance with bias currentIB2.


## 3. CCDDCCTA’s Application as Wave Active Filter

In this section the proposed CCDDCCTA has been used to develop higher-order filter. There are many schemes for simulating higher order filters using doubly terminated lossless ladders available in the literature. The element replacement, operational simulation, and impedance scaling schemes employ mostly lossless integrator which is not easy to implement in integrated circuits due to active and passive element imperfections. Recently, wave approach based ladder filter realization has received attention which relies on modelling incident and reflected voltage waves. It utilizes only lossy integrators for passive component representation and results in a very modular structure. Considering this, some wave active filters have been reported in the literature [19–22]. The wave active filter realization using proposed CCDDCCTA is presented in this section which has the following advantageous features.(i)
It does not use any resistor in contrast to those proposed in [19–21].(ii)
It uses only active elements and capacitors similar to [22].(iii)
It possesses an attractive feature of electronic tunability via bias currents of CCDDCCTA similar to the reported in [22].(iv)
The availability of an additional voltage input terminal in CCDDCCTA as compared to DVCCCTA, the active elements required for wave equivalent can be reduced. Thus, the proposed element gives a compact resistorless realization of wave filter than the one reported in [22].


### 3.1. Derived Basic Wave Equivalent

According to wave method, the corresponding LC ladder filter is split into two-port subnetworks which are fully described using the wave variables, defined as incident and reflected waves. By choosing an inductor in a series branch as the elementary building block, its wave equivalent includes an appropriately configured lossy integrator. The wave equivalents of the other passive elements are derived by interchanging the terminals of the appropriate wave signals and signal inversion. Then each element of the passive prototype filter is substituted by its wave equivalent.The development of the filter using wave method is based on modeling incident and reflected voltage waves. For a two-port network of Figure7, the voltage wave is defined as
(13)Aj=Vj+IjRj,Bj=Vj-IjRj,
where Aj, Bj, and Rj(j=1,2) represent incident and reflected voltage waves and port normalization resistance of port j, respectively.Figure 7
Two-port network with wave variables.Equation (13) can be expressed in terms of scattering matrix S as
(14)[B1B2]=S[A1A2].The ladder network may be viewed in terms of its constituent series-arm impedance elements and shunt-arm admittance elements [19, 20], and the scattering matrices (SZ and SY) [20] for series-arm impedance (Z) and shunt-arm admittance (Y) are represented as
(15)SZ=[Z2R+Z2R2R+Z2R2R+ZZ2R+Z],(16)SY=[-Y2G+Y2G2G+Y2G2G+Z-Y2G+Y],
where R is port normalization resistance, and G is its reciprocal.The series inductorL is considered as a basic element for the wave active filter realization. Its scattering matrix (SZ_L) may be obtained from
(17)SZ_L=11+sτ[sτ11sτ],
where τ=L/2R represents time constant.Using (14) and (17), the reflected wave (Bj, j=1,2) for a series inductor can be expressed in terms of its incident wave (Aj, j=1,2) as
(18)B1=A1-11+sτ(A1-A2),(19)B2=A2+11+sτ(A1-A2).The circuit implementation of (18) is derived by cascading lossy integration subtraction with subtraction, whereas (19) requires a lossy integration subtraction followed by an adder. The complete realization is depicted in Figure 8. The CCDDCCTA marked as “1” in Figure 8(a) performs lossy integration subtraction and provides output voltages V1 as
(20)V1=(A1-A2)11+sτ,
where τ=RXCd is time constant and gmRX=1. Using (18), (19), and (20), the value of Cd may be computed as
(21)RXCd=L2R.
With R=RX, the value of capacitor Cd may be expressed as
(22)Cd=L2R2.(a) Complete schematic of CCDDCCTA-based wave equivalent of series inductor and (b) its symbolic representation.
(a)
(b)The CCDDCCTAs marked as “2” and “3” in Figure8(a) perform subtraction and addition operations and provide the output voltages as
(23)B1=A1-V1=A1-11+sτ(A1-A2)withgmRX=1,B2=A2+V1=A2+11+sτ(A1-A2)withgmRX=1.
The symbolic representation of the wave element is shown in Figure 8(b) [19–22].The wave equivalent of other reactive elements can be obtained using the basic wave equivalent of Figure8. The wave equivalent for inductor and capacitor in series and shunt branches is given in Table 2 which can be obtained by swapping outputs and signal inversion.Table 2
Wave equivalent of elementary two-port network consisting of single element in series and shunt branch.
Elementary two-port network
Port connection
Realized time constant; capacitor value for CCDDCCTA-based wave equivalent
τ
=
L
/
2
R Cd=L/2R2
τ
=
2
R
C Cd=2C
τ
=
2
L
/
R Cd=2L/R2
τ
=
R
C
/
2 Cd=C/2


### 3.2. Alternate Scheme for Shunt Impedance Realization

An alternate scheme for wave equivalent realization of shunt impedances is suggested in this section. This scheme is based on direct realization of port relation of shunt capacitor wave equivalent. It may be noted from Table2 that shunt capacitor requires two inverters with a basic wave equivalent of Figure 8 amounting to a total of five CCDDCCTAs. Using (16), the incident (Aj,j=1,2) and the reflected wave (Bj,j=1,2) for a shunt capacitor are related through the following scattering matrix:
(24)SY_C=11+sτC[-sτC11-sτC],
where τC=RC/2 is time constant. The expressions for reflected waves B1 and B2 become
(25)B1=-A1+11+sτC(A1+A2),B2=-A2+11+sτC(A1+A2).The implementation of (25) and (33) requires two operations-lossy integration addition and subtraction. The high impedance input terminal Y3 of CCDDCCTA can be used for lossy integration addition, and proper outputs are obtained by feeding A1 and A2 to Y2 terminals of second and third CCDDCCTAs as shown in Figure 9(a). This realization may be represented by a symbol of Figure 9(b) for clarity. This slight modification in implementation method results in the saving of two CCDDCCTAs. Similar reduction of active element may be achieved for a shunt inductor as shown in Figure 10. The complete set of wave equivalents is summarized in Table 3. It may be noted that all the wave equivalents in Table 3 use only three active blocks. Thus, this method leads to a compact realization of wave active filter as compared to the one proposed in [22].Table 3
Elementary two-port network consisting of single element in series and shunt branch using alternate scheme.
Elementary two-port network
Port connection
Realized time constant; capacitor value for CCDDCCTA-based wave equivalent
τ
=
L
/
2
R Cd=L/2R2
τ
=
2
R
C Cd=2C
τ
=
2
L
/
R Cd=2L/R2
τ
=
R
C
/
2 Cd=C/2(a) Complete schematic of CCDDCCTA-based wave equivalent of shunt capacitor and (b) its symbolic representation.
(a)
(b)(a) Complete schematic of CCDDCCTA-based wave equivalent of shunt inductor and (b) its symbolic representation.
(a)
(b)The design of wave active filter [19–22] starts with the selection of prototype filter based on specifications. The individual inductors or capacitors are replaced by their wave equivalents resulting in a modular realization. The complete filter schematic is then implemented by cascading the wave equivalents of the passive elements of prototype ladder.


### 3.3. Simulation of Third-Order Butterworth Filter

The theoretical proposition is verified using SPICE simulations using 0.25μm TSMC CMOS technology parameters and power supply of ±1.25 V. The usefulness of the proposed CCDDCCTA is shown by implementing wave active filter based on the method outlined in Sections 3.1 and 3.2. A third-order low-pass filter of Figure 11 has been taken as prototype. The normalized component values are  RS=1, L1=1, L2=1, C1=2, and RL=1 for maximally flat response.Figure 11
Third order low-pass Butterworth Filter.The wave equivalent topology of Figure11 may be constructed by replacing series inductor and shunt capacitor by wave equivalent of Table 3 and is shown in Figure 12. For cutoff frequency fo=10 MHz, the bias currents IB1 and IB2 are taken as 25 μA and 200 μA, respectively. The capacitor values for wave equivalent of series inductors (L1, L2) and shunt capacitors (C1) are  5.4 pF, 5.4 pF, and 10.8 pF, respectively. The topology of Figure 12 has been simulated using CCDDCCTA-based wave equivalent discussed in Section 3. Figures 13 and 14 show the simulated low pass responses (Vout) and its complementary high-pass response (Vout,c), respectively. The tunability of the filter response by varying bias current IB1 from 10 μA to 50 μA and IB2 from 50 μA to 400 μA (IB2=8IB1 for gmRx=1) is also studied through simulations, and the results are shown in Figure 15. The power dissipation of the CCDDCCTA-based filter is simulated to be 13.7 mW, whereas TA-based wave filter power dissipation is found to be 25.6 mW.Figure 12
Wave equivalent of prototype filter.Figure 13
Frequency response of third order low-pass filter.Figure 14
Frequency response of complementary high-pass filter.Figure 15
Demonstration of electronic tunability.To study the time domain behavior, input signal comprised of two frequencies of 5 MHz and 20 MHz is applied. Signal amplitude was 50 mV each. The transient response with its spectrum for input and output is shown in Figure16, which clearly shows that the 20 MHz signal is significantly attenuated. The proposed circuit is also tested to judge the level of harmonic distortion at the output of the signal. The %THD result is shown in Figure 17 which shows that the output distortion is low and within acceptable limit of 6% up to about 300 mV.Transient response with (a) input and output signals and (b) spectrum of input and output signals.
(a)
(b)Figure 17
Variation of %THD with input signal amplitude.


## 3.1. Derived Basic Wave Equivalent

According to wave method, the corresponding LC ladder filter is split into two-port subnetworks which are fully described using the wave variables, defined as incident and reflected waves. By choosing an inductor in a series branch as the elementary building block, its wave equivalent includes an appropriately configured lossy integrator. The wave equivalents of the other passive elements are derived by interchanging the terminals of the appropriate wave signals and signal inversion. Then each element of the passive prototype filter is substituted by its wave equivalent.The development of the filter using wave method is based on modeling incident and reflected voltage waves. For a two-port network of Figure7, the voltage wave is defined as
(13)Aj=Vj+IjRj,Bj=Vj-IjRj,
where Aj, Bj, and Rj(j=1,2) represent incident and reflected voltage waves and port normalization resistance of port j, respectively.Figure 7
Two-port network with wave variables.Equation (13) can be expressed in terms of scattering matrix S as
(14)[B1B2]=S[A1A2].The ladder network may be viewed in terms of its constituent series-arm impedance elements and shunt-arm admittance elements [19, 20], and the scattering matrices (SZ and SY) [20] for series-arm impedance (Z) and shunt-arm admittance (Y) are represented as
(15)SZ=[Z2R+Z2R2R+Z2R2R+ZZ2R+Z],(16)SY=[-Y2G+Y2G2G+Y2G2G+Z-Y2G+Y],
where R is port normalization resistance, and G is its reciprocal.The series inductorL is considered as a basic element for the wave active filter realization. Its scattering matrix (SZ_L) may be obtained from
(17)SZ_L=11+sτ[sτ11sτ],
where τ=L/2R represents time constant.Using (14) and (17), the reflected wave (Bj, j=1,2) for a series inductor can be expressed in terms of its incident wave (Aj, j=1,2) as
(18)B1=A1-11+sτ(A1-A2),(19)B2=A2+11+sτ(A1-A2).The circuit implementation of (18) is derived by cascading lossy integration subtraction with subtraction, whereas (19) requires a lossy integration subtraction followed by an adder. The complete realization is depicted in Figure 8. The CCDDCCTA marked as “1” in Figure 8(a) performs lossy integration subtraction and provides output voltages V1 as
(20)V1=(A1-A2)11+sτ,
where τ=RXCd is time constant and gmRX=1. Using (18), (19), and (20), the value of Cd may be computed as
(21)RXCd=L2R.
With R=RX, the value of capacitor Cd may be expressed as
(22)Cd=L2R2.(a) Complete schematic of CCDDCCTA-based wave equivalent of series inductor and (b) its symbolic representation.
(a)
(b)The CCDDCCTAs marked as “2” and “3” in Figure8(a) perform subtraction and addition operations and provide the output voltages as
(23)B1=A1-V1=A1-11+sτ(A1-A2)withgmRX=1,B2=A2+V1=A2+11+sτ(A1-A2)withgmRX=1.
The symbolic representation of the wave element is shown in Figure 8(b) [19–22].The wave equivalent of other reactive elements can be obtained using the basic wave equivalent of Figure8. The wave equivalent for inductor and capacitor in series and shunt branches is given in Table 2 which can be obtained by swapping outputs and signal inversion.Table 2
Wave equivalent of elementary two-port network consisting of single element in series and shunt branch.
Elementary two-port network
Port connection
Realized time constant; capacitor value for CCDDCCTA-based wave equivalent
τ
=
L
/
2
R Cd=L/2R2
τ
=
2
R
C Cd=2C
τ
=
2
L
/
R Cd=2L/R2
τ
=
R
C
/
2 Cd=C/2


## 3.2. Alternate Scheme for Shunt Impedance Realization

An alternate scheme for wave equivalent realization of shunt impedances is suggested in this section. This scheme is based on direct realization of port relation of shunt capacitor wave equivalent. It may be noted from Table2 that shunt capacitor requires two inverters with a basic wave equivalent of Figure 8 amounting to a total of five CCDDCCTAs. Using (16), the incident (Aj,j=1,2) and the reflected wave (Bj,j=1,2) for a shunt capacitor are related through the following scattering matrix:
(24)SY_C=11+sτC[-sτC11-sτC],
where τC=RC/2 is time constant. The expressions for reflected waves B1 and B2 become
(25)B1=-A1+11+sτC(A1+A2),B2=-A2+11+sτC(A1+A2).The implementation of (25) and (33) requires two operations-lossy integration addition and subtraction. The high impedance input terminal Y3 of CCDDCCTA can be used for lossy integration addition, and proper outputs are obtained by feeding A1 and A2 to Y2 terminals of second and third CCDDCCTAs as shown in Figure 9(a). This realization may be represented by a symbol of Figure 9(b) for clarity. This slight modification in implementation method results in the saving of two CCDDCCTAs. Similar reduction of active element may be achieved for a shunt inductor as shown in Figure 10. The complete set of wave equivalents is summarized in Table 3. It may be noted that all the wave equivalents in Table 3 use only three active blocks. Thus, this method leads to a compact realization of wave active filter as compared to the one proposed in [22].Table 3
Elementary two-port network consisting of single element in series and shunt branch using alternate scheme.
Elementary two-port network
Port connection
Realized time constant; capacitor value for CCDDCCTA-based wave equivalent
τ
=
L
/
2
R Cd=L/2R2
τ
=
2
R
C Cd=2C
τ
=
2
L
/
R Cd=2L/R2
τ
=
R
C
/
2 Cd=C/2(a) Complete schematic of CCDDCCTA-based wave equivalent of shunt capacitor and (b) its symbolic representation.
(a)
(b)(a) Complete schematic of CCDDCCTA-based wave equivalent of shunt inductor and (b) its symbolic representation.
(a)
(b)The design of wave active filter [19–22] starts with the selection of prototype filter based on specifications. The individual inductors or capacitors are replaced by their wave equivalents resulting in a modular realization. The complete filter schematic is then implemented by cascading the wave equivalents of the passive elements of prototype ladder.


## 3.3. Simulation of Third-Order Butterworth Filter

The theoretical proposition is verified using SPICE simulations using 0.25μm TSMC CMOS technology parameters and power supply of ±1.25 V. The usefulness of the proposed CCDDCCTA is shown by implementing wave active filter based on the method outlined in Sections 3.1 and 3.2. A third-order low-pass filter of Figure 11 has been taken as prototype. The normalized component values are  RS=1, L1=1, L2=1, C1=2, and RL=1 for maximally flat response.Figure 11
Third order low-pass Butterworth Filter.The wave equivalent topology of Figure11 may be constructed by replacing series inductor and shunt capacitor by wave equivalent of Table 3 and is shown in Figure 12. For cutoff frequency fo=10 MHz, the bias currents IB1 and IB2 are taken as 25 μA and 200 μA, respectively. The capacitor values for wave equivalent of series inductors (L1, L2) and shunt capacitors (C1) are  5.4 pF, 5.4 pF, and 10.8 pF, respectively. The topology of Figure 12 has been simulated using CCDDCCTA-based wave equivalent discussed in Section 3. Figures 13 and 14 show the simulated low pass responses (Vout) and its complementary high-pass response (Vout,c), respectively. The tunability of the filter response by varying bias current IB1 from 10 μA to 50 μA and IB2 from 50 μA to 400 μA (IB2=8IB1 for gmRx=1) is also studied through simulations, and the results are shown in Figure 15. The power dissipation of the CCDDCCTA-based filter is simulated to be 13.7 mW, whereas TA-based wave filter power dissipation is found to be 25.6 mW.Figure 12
Wave equivalent of prototype filter.Figure 13
Frequency response of third order low-pass filter.Figure 14
Frequency response of complementary high-pass filter.Figure 15
Demonstration of electronic tunability.To study the time domain behavior, input signal comprised of two frequencies of 5 MHz and 20 MHz is applied. Signal amplitude was 50 mV each. The transient response with its spectrum for input and output is shown in Figure16, which clearly shows that the 20 MHz signal is significantly attenuated. The proposed circuit is also tested to judge the level of harmonic distortion at the output of the signal. The %THD result is shown in Figure 17 which shows that the output distortion is low and within acceptable limit of 6% up to about 300 mV.Transient response with (a) input and output signals and (b) spectrum of input and output signals.
(a)
(b)Figure 17
Variation of %THD with input signal amplitude.


## 4. Conclusion

In this paper current controlled differential difference current conveyor transconductance amplifier (CCDDCCTA), a new active building block for analog signal processing, is presented. The expressions for port characteristics are derived and verified through SPICE. The wave filter based on CCDDCCTA is included to show the usefulness of the element. The CCDDCCTA-based wave equivalent of series inductor is introduced which is applied for other passive element realization by making suitable connections. The availability of additional input terminals in CCDDCCTA is gainfully used for obtaining a compact realization of shunt impedance wave equivalents. The structure is resistorless, employs grounded capacitors, possesses electronic tunability of cutoff frequency, and is modular.



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*Source: 968749-2013-02-28.xml*