# High Throughput Pseudorandom Number Generator Based on Variable Argument Unified Hyperchaos

Authors: Kaiyu Wang; Qingxin Yan; Shihua Yu; Xianwei Qi; Yudi Zhou; Zhenan Tang
Journal: VLSI Design
 (2014)

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## Abstract

This paper presents a new multioutput and high throughput pseudorandom number generator. The scheme is to make the homogenized Logistic chaotic sequence as unified hyperchaotic system parameter. So the unified hyperchaos can transfer in different chaotic systems and the output can be more complex with the changing of homogenized Logistic chaotic output. Through processing the unified hyperchaotic 4-way outputs, the output will be extended to 26 channels. In addition, the generated pseudorandom sequences have all passed NIST SP800-22 standard test and DIEHARD test. The system is designed in Verilog HDL and experimentally verified on a Xilinx Spartan 6 FPGA for a maximum throughput of 16.91 Gbits/s for the native chaotic output and 13.49 Gbits/s for the resulting pseudorandom number generators.


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## Body

## 1. Introduction

Pseudorandom number (PN) is the 01 sequence which has the randomness similar to noise. It has been widely used in digital communication, cryptography, computer games, and numerical computation [1–3]. Chaos is the phenomenon which shows very complex nonlinear dynamic characteristics in a deterministic system. And it has excellent properties such as nonperiodicity, broad bandwidth, and sensitivity to initial value [4, 5]. So Chaos and PN have a natural link. And compared to other PN sequences like m sequences, and so forth, the PN sequence generated by chaotic system has advantages like larger key space, longer cycle, and so forth.Currently, researches of chaotic pseudorandom number generator (PRNG) are more focused on the digital implementation of low dimensional chaos such as Logistic chaos, Tent chaos, and Lorenz chaos. While these algorithms have significant advantages in some respects, like simpler construction, fewer resources consuming, and faster computing speed, they also have the fatal weakness that cannot be ignored to PRNG like smaller secret key space, periodic problem, and relatively lower throughput. Therefore, implementing a PRNG based on higher-order chaos equations seems more advantage because the hyperchaos has multiple positive Lyapunov exponent and more controllable parameters and the output of system will have more complex randomness. The hyperchaotic encryption signal is harder to decode than low dimensional encryption signal [6]. And hyperchaos can provide multiple outputs, improve the throughput, and process multiple target signal [7, 8].In 2002, Lu et al. proposed the unified chaos that can make Lorenz chaos, Lu chaos, and Chen chaos into a unified chaotic system and realize continued transition from one to another [9]. In 2011, Ma and Wang proposed the unified hyperchaos [10]. This algorithm makes the system continued transition from Lorenz hyperchaos through Lu hyperchaos to Chen hyperchaos with one system parameter changing from 0 to 1.In this paper, we propose a novel variable parameters hyperchaotic PRNG structure which is composed by homogenized Logistic chaos and unified hyperchaos cascade. As [10] proposed the structure that needs to vary the system parameter from 0 to 1 to change chaotic class, and Logistic chaotic output is exactly between 0 and 1, so that they have a natural link. This paper uses the homogenization algorithm proposed in [11] to deal with Logistic output to provide variable parameters to the unified hyperchaos in [10]. With this method we can extend cycle of pseudorandom sequence and increase the complexity of system. And through the simple XOR processing to the output of hyperchaos, the system can generate multiple new pseudorandom sequences, greatly improving throughput. The system is designed in Verilog HDL and experimentally verified on a Xilinx Spartan 6 FPGA for a maximum throughput of 16.91 Gbits/s for the native chaotic output and 13.49 Gbits/s for the resulting PRNG output. And the output channel is increased to 26 roads. The output sequence is shown to pass the NIST SP. 800-22 test suite [12] and DIEHARD test suite to indicate statistical randomness.This paper is organized as follows: Section2 discusses the algorithms composed of the variable argument hyperchaos and demonstrates chaotic nature; Section 3 describes the details of its implementation in hardware; Section 4 introduces the test results of the output sequence and the resource consuming after FPGA implementation; Section 5 is conclusion.


## 2. Proposed Variable Argument Unified Hyperchaotic PRNG

As shown in Figure1, the proposed variable argument unified hyperchaotic PRNG is mainly composed of five modules. They are the Logistic map module which provides the parameter, homogenization module which homogenizes the output of Logistic map, unified hyperchaotic module, throughput rate choosing module which controls the number of output channel, and initial control module which controls the system. The core algorithms are the Logistic chaos, homogenization algorithm, and unified hyperchaos. Now we will discuss these three algorithms.Figure 1
Flowchart of chaotic system.


### 2.1. Logistic Chaos

Logistic chaos is one of the most studied chaos systems. It is applied in many chaos systems because of its simple description. The Logistic chaos is described as follows:(1)xn+1=rxn(1-xn)0≤xn≤1,0≤r≤4,n=0,1,2,…Iteration of Logistic chaos is affected by parametersr and initial value x0. Small changes of the two values will lead to significantly different output. When r is in the range 3.569945672≤r≤4, the numbers generated in successive iterations of the mapping become chaotic, and output is always between [0,1], just as bifurcation diagram Figure 2. We take r=4 to realize in hardware easily.Figure 2
Logistic map bifurcation diagram.


### 2.2. Homogenization Algorithm

The Logistic chaotic output in this research is homogenized to make it become a uniform pseudorandom sequence, so that the parameters input into the unified hyperchaos can be more complex and more randomness. Now, we will introduce the transform method.The IEEE double format consists of three fields: a 52-bit fraction,f; an 11-bit biased exponent, e; and a 1-bit sign, s; then, any real number can be expressed as the following equation:
(2)x=((-1)s×2e-1023×1.f)10=({s,e,f})2.Definition 1.
Left-shiftb-operation of f, f←b, is a new fraction obtained by discarding the left-most b bits of f and then padding the result with b-1 bits 0 and 1 bit 1 on the right, if the 51st-bit, 50th-bit, …, (51-b+1)th-bit in f equals zeroes, while the (51-b)th-bit in f equals one.Definition 2.
The bit-transformation off, BT{f}: in (1), the fraction f can be rewritten in the binary-coded form f=f51f50⋯f1f0. Parse f into higher 26-bit block fH and lower 26-bit block fL is as follows:
(3)fH=f51f50⋯f27,fL=f26f25⋯f0.
Then, reverse fL into fL′; that is,
(4)fL′=f0f1⋯f26.
Then
(5)BT{f}={fH⊕fL′,fL}.Now, one defines (5) as bit-transformation of f, BT{f}.Definition 3.
Bit-transformation of real numbers: supposex={s,e,f}∈G, G represent all real numbers. The bit-transformation of {s,e,f} is defined by
(6)RBT{x}={0,1023-b,BT{f}←b}.
Note that a bit-transformation of real numbers is composed of a bit-transformation and a left-shiftb-operation, so RBT{x} is a multiple-to-one map function.After the conversion like (6), the pseudorandom sequence can be made ​​uniform. One realizes the homogenization algorithm on FPGA to deal with Logistic chaos. Import the output of Logistic chaos with preprocessing and postprocessing into MATLAB. The result is shown in Figure 3. It has obtained the good effect of homogenization and achieves the goal of the interference transformation, homogenization.Figure 3
Homogenization effect.


### 2.3. Unified Hyperchaos

The unified hyperchaotic system is shown as the following equations:(7a)x˙=(26a+10)(y-x)(7b)y˙=(28-44a)x-xz+(29a-1)y-v(7c)z˙=xy-(8+a)z3(7d)v˙=0.1(1-a)yz+ax+0.2.Obviously, when the parameter a increases from 0 to 1, the systems (7a), (7b), (7c), and (7d) evolve from hyperchaotic Lorenz system to hyperchaotic Chen system. The maximum Lyapunov exponent (MLE) and the Lyapunov dimension (DL) are often used to measure a chaotic system in a state of chaos case or period orbit case. It is well known that the MLE and DL satisfy at least one MLE greater than zero and 2<DL<3 for chaos case, two MLE greater than zero, and 3<DL<4 for hyperchaos case. For systems (7a), (7b), (7c), and (7d), when a∈[0,1], the Lyapunov exponent spectrum and the Lyapunov dimension are shown as Figures 4 and 5. As it is shown in Figure 4, all points from 0 to 1 except a=0.14, there are two MLE greater than zero. And as it is shown in Figure 5, all points from 0 to 1 except a=0.14, 3<DL<4. It means the system is hyperchaotic system only except individual parameter points. And the individual bad parameter point can be removed by the means of hardware implementation.Figure 4
Max Lyapunov exponent spectrum.Figure 5
Lyapunov dimension.In order to see clearly that, when the parameter a increases from 0 to 1, the systems (7a), (7b), (7c), and (7d) evolve from hyperchaotic Lorenz system to hyperchaotic Chen system, we plot the phase diagram with different parameter as shown in Figures 6 and 7.Figure 6
Phase diagram whena=0.03.Figure 7
Phase diagram whena=0.73.


### 2.4. Variable Argument Unified Hyperchaotic Algorithm

The variable argument unified hyperchaotic PRNG we proposed is based on the above three algorithms. Logistic chaos generates sequence between 0 and 1. Then, the sequence is processed by homogenization algorithm to be made ​​uniform. After that, the uniform pseudorandom sequence is introduced as changing parameter to be imported into unified hyperchaotic system to control the output. So that the system varies in different state of hyperchaotic system and increases the output sequence cycle and has more complex dynamic characteristics and optimizes the statistical properties.


## 2.1. Logistic Chaos

Logistic chaos is one of the most studied chaos systems. It is applied in many chaos systems because of its simple description. The Logistic chaos is described as follows:(1)xn+1=rxn(1-xn)0≤xn≤1,0≤r≤4,n=0,1,2,…Iteration of Logistic chaos is affected by parametersr and initial value x0. Small changes of the two values will lead to significantly different output. When r is in the range 3.569945672≤r≤4, the numbers generated in successive iterations of the mapping become chaotic, and output is always between [0,1], just as bifurcation diagram Figure 2. We take r=4 to realize in hardware easily.Figure 2
Logistic map bifurcation diagram.


## 2.2. Homogenization Algorithm

The Logistic chaotic output in this research is homogenized to make it become a uniform pseudorandom sequence, so that the parameters input into the unified hyperchaos can be more complex and more randomness. Now, we will introduce the transform method.The IEEE double format consists of three fields: a 52-bit fraction,f; an 11-bit biased exponent, e; and a 1-bit sign, s; then, any real number can be expressed as the following equation:
(2)x=((-1)s×2e-1023×1.f)10=({s,e,f})2.Definition 1.
Left-shiftb-operation of f, f←b, is a new fraction obtained by discarding the left-most b bits of f and then padding the result with b-1 bits 0 and 1 bit 1 on the right, if the 51st-bit, 50th-bit, …, (51-b+1)th-bit in f equals zeroes, while the (51-b)th-bit in f equals one.Definition 2.
The bit-transformation off, BT{f}: in (1), the fraction f can be rewritten in the binary-coded form f=f51f50⋯f1f0. Parse f into higher 26-bit block fH and lower 26-bit block fL is as follows:
(3)fH=f51f50⋯f27,fL=f26f25⋯f0.
Then, reverse fL into fL′; that is,
(4)fL′=f0f1⋯f26.
Then
(5)BT{f}={fH⊕fL′,fL}.Now, one defines (5) as bit-transformation of f, BT{f}.Definition 3.
Bit-transformation of real numbers: supposex={s,e,f}∈G, G represent all real numbers. The bit-transformation of {s,e,f} is defined by
(6)RBT{x}={0,1023-b,BT{f}←b}.
Note that a bit-transformation of real numbers is composed of a bit-transformation and a left-shiftb-operation, so RBT{x} is a multiple-to-one map function.After the conversion like (6), the pseudorandom sequence can be made ​​uniform. One realizes the homogenization algorithm on FPGA to deal with Logistic chaos. Import the output of Logistic chaos with preprocessing and postprocessing into MATLAB. The result is shown in Figure 3. It has obtained the good effect of homogenization and achieves the goal of the interference transformation, homogenization.Figure 3
Homogenization effect.


## 2.3. Unified Hyperchaos

The unified hyperchaotic system is shown as the following equations:(7a)x˙=(26a+10)(y-x)(7b)y˙=(28-44a)x-xz+(29a-1)y-v(7c)z˙=xy-(8+a)z3(7d)v˙=0.1(1-a)yz+ax+0.2.Obviously, when the parameter a increases from 0 to 1, the systems (7a), (7b), (7c), and (7d) evolve from hyperchaotic Lorenz system to hyperchaotic Chen system. The maximum Lyapunov exponent (MLE) and the Lyapunov dimension (DL) are often used to measure a chaotic system in a state of chaos case or period orbit case. It is well known that the MLE and DL satisfy at least one MLE greater than zero and 2<DL<3 for chaos case, two MLE greater than zero, and 3<DL<4 for hyperchaos case. For systems (7a), (7b), (7c), and (7d), when a∈[0,1], the Lyapunov exponent spectrum and the Lyapunov dimension are shown as Figures 4 and 5. As it is shown in Figure 4, all points from 0 to 1 except a=0.14, there are two MLE greater than zero. And as it is shown in Figure 5, all points from 0 to 1 except a=0.14, 3<DL<4. It means the system is hyperchaotic system only except individual parameter points. And the individual bad parameter point can be removed by the means of hardware implementation.Figure 4
Max Lyapunov exponent spectrum.Figure 5
Lyapunov dimension.In order to see clearly that, when the parameter a increases from 0 to 1, the systems (7a), (7b), (7c), and (7d) evolve from hyperchaotic Lorenz system to hyperchaotic Chen system, we plot the phase diagram with different parameter as shown in Figures 6 and 7.Figure 6
Phase diagram whena=0.03.Figure 7
Phase diagram whena=0.73.


## 2.4. Variable Argument Unified Hyperchaotic Algorithm

The variable argument unified hyperchaotic PRNG we proposed is based on the above three algorithms. Logistic chaos generates sequence between 0 and 1. Then, the sequence is processed by homogenization algorithm to be made ​​uniform. After that, the uniform pseudorandom sequence is introduced as changing parameter to be imported into unified hyperchaotic system to control the output. So that the system varies in different state of hyperchaotic system and increases the output sequence cycle and has more complex dynamic characteristics and optimizes the statistical properties.


## 3. Hardware Implementation

To implement easily in the hardware, the differential equations (7a), (7b), (7c), and (7d) are discretized. Euler approximation has been shown to provide the best chaotic response, occupy the lowest area, and provide the highest speed compared with Runge-Kutta method and other methods [13]. Therefore, the Euler approximation is applied to discretize the continuous-time systems (7a), (7b), (7c), and (7d) for the digital domain: (8a)xn+1=h((26a+10)(yn-xn))+xn(8b)yn+1=h((28-44a)xn-xnzn(29a-1)yn-vn)+yn(8c)zn+1=h(xnyn-(8+a)zn3)+zn(8d)vn+1=h(0.1(1-a)ynzn+axn+0.2)+vn.While the chaotic systems are running in finite precision, the fixed-point arithmetic is preferable over floating point mathematics because it requires less hardware resources and computation time. And under the same word length fixed-point format has a higher accuracy [14, 15]. So we select fixed-point format to represent data. Also due to the limited precision, the digital realization of chaotic systems has degradation dynamics and tends to period orbit case, namely, finite precision. Based on the theory [16] proposed that the cycle of chaotic sequence will grow exponentially with growth of format word length, we use 32-bit fixed-point number format to realize the chaotic system to prevent the finite precision effect. In unified hyperchaotic system, the fixed-point two’s complement format is used with the 7 most significant bits for sign and integer part and the remaining for the fractional part. But Logistic chaotic system is used with the 1 most significant bit for integer part and the remaining for the fractional part as its output is always positive number.As shown in Figure1, the PRNG we proposed has three core algorithms: Logistic, homogenized, and unified hyperchaotic. And they are cascade structure. Therefore, this work employs a pipelined architecture between the three modules, so that the register between these three modules can be updated in each clock and increase hardware utilization efficiency.Logistic Module is controlled by control module so that the Logistic Module outputs the same value inm clock cycles. As a result of the pipeline structure, unified hyperchaotic module will read an input as a unified hyperchaotic parameter at each rising edge of the clock, so unified hyperchaotic modules will calculate the output with the same parameter in every m clock cycles. So, if Logistic period is n, then the entire system’s period is m*n.As unified hyperchaotic module has four dimensional outputs, it could provide operation space for subsequent processing. We add throughput rate choosing module after unified hyperchaotic module to make bitwise operation among the initial four outputs (x,y,z,v). Based on the conclusion proposed in [7] about the fact that doing bitwise XOR operation on chaotic system output can get better PN sequence, in throughput rate choosing module, we do bitwise XOR operation on two different output sequences A⊕B (like x⊕y, x⊕z, etc.) or three different output sequences A⊕B⊕C (like x⊕y⊕z, x⊕z⊕v, etc.) or do bitwise XOR operation on A’s higher 16 bits and B’s lower 16 bits and then merge these 16 bits with A’s lower 16 bits {Ahigh⊕Blow,Alow} (like {x[31:16]⊕y[15:0],x[15:0]}, etc.) to improve the throughput. After these XOR operations, this system can provide up to 26 channels output. And this module can be configured to decide which channel or which several channels can be output.


## 4. Result

The proposed variable argument unified hyperchaotic PRNGis designed in Xilinx ISE 12.2 environment using Verilog HDL and experimentally verified on a Xilinx Spartan 6 XC6SLX100 FPGA. In order to fully test the output, through controlling the throughput rate choosing module, make all XOR modules work to output all 26 channels and analyze these output data with below tests.


### 4.1. Phase Diagram

We import the PRNG’s output{x,y,z,v} into MATLAB as shown in Figure 8. From Figure 8 we can get the system is switching in different chaotic system with the number of iterations increase and parameter change; it effectively improves the complexity of output.Figure 8
System output phase diagram.


### 4.2. Correlation

Among the 26 channels output, there are 22 channels which are produced by XOR operation through 4 original outputs (x,y,z,v). To analyze the cross-correlation among these outputs, we import them into MATLAB. Figure 9 shows cross-correlation result between x related outputs (x⊕y,x⊕z,x⊕v,x⊕x⊕z) and original x output. The results show that the XOR operation outputs are still correlated to their original channels, as indicated by a peak at zero-lag. However, most peaks are below 0.5, and at other delays, cross-correlation coefficients are below 0.3. About other cross-correlation results, they are similar to the above one.Figure 9
X related cross-correlation diagram.


### 4.3. Pseudorandom Number Test

If the chaotic system is regarded as a PRNG, not all output bits can meet the requirements of randomness. As in the digital context, it creates an uneven distribution of pseudorandomness across the output bits. The MSBs are not only biased but also highly correlated, while the LSBs show desirable statistical randomness [17]. For this kind of situation, we first test all 32 bits. If the sequence cannot pass the tests, we will discard the highest one. Then, we will test the remaining bits. Repeat these actions until the sequence can pass tests. After tested by NIST SP800-22 test suit and DIEHARD test suit, test results show that in the 26 channels of FPGA output, 12 channels {Ahigh⊕Blow,Alow} can pass tests with all 32 bits and other 14 channels can pass with lower 20 bits. So, as a PRNG, we make the system output 32 bits in 12 channels {Ahigh⊕Blow,Alow} and output lower 20 bits in other 14 channels. And from the test result of DIEHARD, we can get the conclusion that the quality from higher to lower is {Ahigh⊕Blow,Alow}, A⊕B⊕C,A⊕B and original 4 outputs.We take the lower 20 bitsx,y,z⊕v,x⊕y⊕z NIST test results and DIEHARD test results as the representative list in this paper, in Tables 1 and 2. The remaining 22 roads also pass the tests but not list in this paper. In conclusion, the PRNG we proposed can provide as high as 26 channels output and 13.49 Gbits/s throughput.Table 1
Result of NIST SP800-22 test.
X  P value
Y  P value
Z XOR V  P value
X XOR Y XOR Z  P value
Frequency
0.791780
0.041550
0.979257
0.961716
Block frequency
0.366274
0.648388
0.367493
0.117584
Cumulative sums
0.744906
0.078225
0.664299
0.985758
Runs
0.383170
0.481335
0.872882
0.017885
Longest run of ones
0.753431
0.746675
0.173653
0.222029
Rank
0.123860
0.050112
0.202915
0.849442
FFT
0.168669
0.868803
0.868803
0.934178
Nonperiodic template matchings
0.988648
0.677613
0.896375
0.857033
Overlapping template matchings
0.545254
0.239949
0.392905
0.672648
Universal statistical
0.303032
0.748731
0.096754
0.951902
Approximate entropy
0.977511
0.223329
0.790074
0.634836
Random excursions
0.379538
0.707823
0.490369
0.981034
Random excursions variant
0.509760
0.958761
0.613635
0.937700
Serial
0.380005
0.582563
0.953135
0.876081
linear complexity
0.418562
0.193589
0.352896
0.198838
TEST status
SUCCESS
SUCCESS
SUCCESS
SUCCESS
Length of bit = 1000000, number of bit streams = 100, and confidence level = 99%.Table 2
Result of DIEHARD test.
X  P value
Y  P value
Z XOR V  P value
X XOR Y XOR Z  P value
BIRTHDAY SPACINGS
0.352976
0.728427
0.767687
0.293804
OVERLAPPING 5-PERMUTATION
1.000000
1.000000
1.000000
0.999995
RANK TEST for 31 × 31 matrices
0.364438
0.610135
0.417598
0.741397
RANK TEST for 32 × 32 matrices
0.594228
0.321434
0.431023
0.514951
RANK TEST for 6 × 8 matrices
0.335467
0.156574
0.227157
0.688417
OVERLAPPING 20-tuples BITSTREAM
0.6421225
0.413186
0.5047115
0.453427
OPSO
0.4453782
0.545113
0.552886
0.470565
OQSO
0.8444143
0.830028
0.720432
0.473571
DNA
0.8535612
0.902319
0.650219
0.597742
COUNT-THE-1’s TEST on a stream of bytes
0.3500190
0.210574
0.306527
0.183018
COUNT-THE-1’s TEST for specific bytes
0.7102660
0.641749
0.623289
0.490400
PARKING LOT
0.643434
0.068029
0.787648
0.837780
MINIMUM DISTANCE
0.689712
0.467954
0.970672
0.960276
3DSPHERES
0.130624
0.701084
0.231284
0.013265
SQEEZE
0.952062
0.781055
0.454853
0.518254
OVERLAPPING SUMS
0.862138
0.132331
0.913215
0.724329
RUNS
0.578362
0.298342
0.834721
0.302906
CRAPS
1.000000
1.000000
0.679313
0.841946


### 4.4. Hardware Resource Utilization

After the FPGA synthesis, Slice Registers resources utilization rate is 1%, Slice LUTs is 5%, and DSP block is 55%. The designed system can provide 26-way output with 32 bits. Taking into account the pipeline structure influence, the throughput of system is as high as 16.91 Gbits/s at maximum clock frequency. And its random number throughput rate is as high as 13.49 Gbits/s. Specific numbers of resource consumption and throughput are shown in Table3. To make the quantitative analysis on the resource consumption and throughput, we adopt the following definition. Gate count is estimated as Gc=8×(LUTs+FFs) and the area efficiency is assessed through a figure of merit determined as FOM=(NPRNG×fCLK)/Gc. The PRNG proposed in this paper is compared with several low dimensional chaotic PRNG in Table 4. From Table 4 we can get that although this work spent higher hardware resource than low dimensional chaotic PRNG, we get much higher throughput and higher FOM.Table 3
Experimental results on Xilinx Spartan 6 FPGA.
Experimental results on the Xilinx Spartan 6 FPGA
Registers
1780
LUTs
3068
Fully used LUT-FF pairs
854
DSP48A1s
100
Frequency (MHz)
20.811
Single output bits
32
Number of output channel
26
System throughput (Mb/s)
17314.752
PRNG throughput (Mb/s)
13818.504Table 4
Comparison with previously reported chaos-based PRNGS.
System
Area (Gc)
T.put
FOM
NIST
Chen et al.  [18]
LOG.Map
9622
200
0.02
Pass
Li et al. [19]
LOG.Map
9136
200
0.02
Fail
Chen et al. [20]
LOG.Map
31655
3200
0.10
Pass
This one
Hyp.Chaos
31376
13819
0.44
Pass


## 4.1. Phase Diagram

We import the PRNG’s output{x,y,z,v} into MATLAB as shown in Figure 8. From Figure 8 we can get the system is switching in different chaotic system with the number of iterations increase and parameter change; it effectively improves the complexity of output.Figure 8
System output phase diagram.


## 4.2. Correlation

Among the 26 channels output, there are 22 channels which are produced by XOR operation through 4 original outputs (x,y,z,v). To analyze the cross-correlation among these outputs, we import them into MATLAB. Figure 9 shows cross-correlation result between x related outputs (x⊕y,x⊕z,x⊕v,x⊕x⊕z) and original x output. The results show that the XOR operation outputs are still correlated to their original channels, as indicated by a peak at zero-lag. However, most peaks are below 0.5, and at other delays, cross-correlation coefficients are below 0.3. About other cross-correlation results, they are similar to the above one.Figure 9
X related cross-correlation diagram.


## 4.3. Pseudorandom Number Test

If the chaotic system is regarded as a PRNG, not all output bits can meet the requirements of randomness. As in the digital context, it creates an uneven distribution of pseudorandomness across the output bits. The MSBs are not only biased but also highly correlated, while the LSBs show desirable statistical randomness [17]. For this kind of situation, we first test all 32 bits. If the sequence cannot pass the tests, we will discard the highest one. Then, we will test the remaining bits. Repeat these actions until the sequence can pass tests. After tested by NIST SP800-22 test suit and DIEHARD test suit, test results show that in the 26 channels of FPGA output, 12 channels {Ahigh⊕Blow,Alow} can pass tests with all 32 bits and other 14 channels can pass with lower 20 bits. So, as a PRNG, we make the system output 32 bits in 12 channels {Ahigh⊕Blow,Alow} and output lower 20 bits in other 14 channels. And from the test result of DIEHARD, we can get the conclusion that the quality from higher to lower is {Ahigh⊕Blow,Alow}, A⊕B⊕C,A⊕B and original 4 outputs.We take the lower 20 bitsx,y,z⊕v,x⊕y⊕z NIST test results and DIEHARD test results as the representative list in this paper, in Tables 1 and 2. The remaining 22 roads also pass the tests but not list in this paper. In conclusion, the PRNG we proposed can provide as high as 26 channels output and 13.49 Gbits/s throughput.Table 1
Result of NIST SP800-22 test.
X  P value
Y  P value
Z XOR V  P value
X XOR Y XOR Z  P value
Frequency
0.791780
0.041550
0.979257
0.961716
Block frequency
0.366274
0.648388
0.367493
0.117584
Cumulative sums
0.744906
0.078225
0.664299
0.985758
Runs
0.383170
0.481335
0.872882
0.017885
Longest run of ones
0.753431
0.746675
0.173653
0.222029
Rank
0.123860
0.050112
0.202915
0.849442
FFT
0.168669
0.868803
0.868803
0.934178
Nonperiodic template matchings
0.988648
0.677613
0.896375
0.857033
Overlapping template matchings
0.545254
0.239949
0.392905
0.672648
Universal statistical
0.303032
0.748731
0.096754
0.951902
Approximate entropy
0.977511
0.223329
0.790074
0.634836
Random excursions
0.379538
0.707823
0.490369
0.981034
Random excursions variant
0.509760
0.958761
0.613635
0.937700
Serial
0.380005
0.582563
0.953135
0.876081
linear complexity
0.418562
0.193589
0.352896
0.198838
TEST status
SUCCESS
SUCCESS
SUCCESS
SUCCESS
Length of bit = 1000000, number of bit streams = 100, and confidence level = 99%.Table 2
Result of DIEHARD test.
X  P value
Y  P value
Z XOR V  P value
X XOR Y XOR Z  P value
BIRTHDAY SPACINGS
0.352976
0.728427
0.767687
0.293804
OVERLAPPING 5-PERMUTATION
1.000000
1.000000
1.000000
0.999995
RANK TEST for 31 × 31 matrices
0.364438
0.610135
0.417598
0.741397
RANK TEST for 32 × 32 matrices
0.594228
0.321434
0.431023
0.514951
RANK TEST for 6 × 8 matrices
0.335467
0.156574
0.227157
0.688417
OVERLAPPING 20-tuples BITSTREAM
0.6421225
0.413186
0.5047115
0.453427
OPSO
0.4453782
0.545113
0.552886
0.470565
OQSO
0.8444143
0.830028
0.720432
0.473571
DNA
0.8535612
0.902319
0.650219
0.597742
COUNT-THE-1’s TEST on a stream of bytes
0.3500190
0.210574
0.306527
0.183018
COUNT-THE-1’s TEST for specific bytes
0.7102660
0.641749
0.623289
0.490400
PARKING LOT
0.643434
0.068029
0.787648
0.837780
MINIMUM DISTANCE
0.689712
0.467954
0.970672
0.960276
3DSPHERES
0.130624
0.701084
0.231284
0.013265
SQEEZE
0.952062
0.781055
0.454853
0.518254
OVERLAPPING SUMS
0.862138
0.132331
0.913215
0.724329
RUNS
0.578362
0.298342
0.834721
0.302906
CRAPS
1.000000
1.000000
0.679313
0.841946


## 4.4. Hardware Resource Utilization

After the FPGA synthesis, Slice Registers resources utilization rate is 1%, Slice LUTs is 5%, and DSP block is 55%. The designed system can provide 26-way output with 32 bits. Taking into account the pipeline structure influence, the throughput of system is as high as 16.91 Gbits/s at maximum clock frequency. And its random number throughput rate is as high as 13.49 Gbits/s. Specific numbers of resource consumption and throughput are shown in Table3. To make the quantitative analysis on the resource consumption and throughput, we adopt the following definition. Gate count is estimated as Gc=8×(LUTs+FFs) and the area efficiency is assessed through a figure of merit determined as FOM=(NPRNG×fCLK)/Gc. The PRNG proposed in this paper is compared with several low dimensional chaotic PRNG in Table 4. From Table 4 we can get that although this work spent higher hardware resource than low dimensional chaotic PRNG, we get much higher throughput and higher FOM.Table 3
Experimental results on Xilinx Spartan 6 FPGA.
Experimental results on the Xilinx Spartan 6 FPGA
Registers
1780
LUTs
3068
Fully used LUT-FF pairs
854
DSP48A1s
100
Frequency (MHz)
20.811
Single output bits
32
Number of output channel
26
System throughput (Mb/s)
17314.752
PRNG throughput (Mb/s)
13818.504Table 4
Comparison with previously reported chaos-based PRNGS.
System
Area (Gc)
T.put
FOM
NIST
Chen et al.  [18]
LOG.Map
9622
200
0.02
Pass
Li et al. [19]
LOG.Map
9136
200
0.02
Fail
Chen et al. [20]
LOG.Map
31655
3200
0.10
Pass
This one
Hyp.Chaos
31376
13819
0.44
Pass


## 5. Conclusion

In this paper, we propose a novel variable parameters hyperchaotic PRNG structure which is composed of homogenized Logistic chaos and unified hyperchaos cascade. Take the homogenized Logistic chaotic output as the unified hyperchaotic parameter to make the output sequence in different chaotic system. In this way, system will be more complex and have longer period. At the same time, add a throughput rate control module after the output of the unified hyperchaotic module, through simple XOR processing; the output of the 4 road hyperchaos can be extended to 26 road and greatly improve the throughput of the system. The PRNGis designed in Xilinx ISE 12.2 environment using Verilog HDL and experimentallyverified on a Xilinx Spartan 6 FPGA. The throughput is up to 16.91 Gbits/s for the chaotic system. As a PRNG, it can provide 26 channels output as pseudorandom sequence which all pass NIST SP800-22 test and DIEHARD test. And its random number throughput rate is as high as 13.49 Gbits/s.Therefore, due to the variable argument unified hyperchaotic PRNG has advantages like high output complexity, multidimensional output, and high throughput rate; it is very suitable for being applied to multiobjective signal processing field like multiobjective control and secure communications, and so forth.



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*Source: 923618-2014-07-07.xml*