# A High Gain DC-DC Converter Based on Coupled Inductor and Switched-Capacitor Cell with Low-Voltage Stress

Authors: Hamed Javaheri Fard; Seyed Mohammad Sadeghzadeh
Journal: Journal of Electrical and Computer Engineering
 (2022)

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## Abstract

This paper presents a nonisolated ultrahigh step-up DC-DC converter with an interleaved structure that is suitable for high power and voltage applications. In order to increase the voltage gain, the proposed structure uses coupled inductors and switched-capacitor cells. Achieving this goal is accompanied by avoiding the imposition of any extreme duty cycle or high turns ratio to the converter. The current ripple is reduced due to the use of the interleaved structure. Since the voltage stress of the switches is lower than the output voltage, by selecting the low-voltage rated switches and small RDS(on), the conduction losses are reduced. In addition, alleviating the phenomenon of reverse recovery of diodes and creating soft-switching conditions in MOSFETs, which leads to a reduction of switching losses, are other advantages of the proposed converter. Therefore, there is no need to use clamp circuits in the mentioned structure. The experimental results, using a prototype of 350 W-18 V/400 V, verify the effective performance of the proposed converter.


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## Body

## 1. Introduction

In recent years, attention to power electronic equipment has increased due to the ability to work at high voltage and high power. Also, environmental problems caused by fossil fuels and exposure to global warming have increased the need to pay attention to renewable sources. Since these power sources do not have the ability to generate high voltage DC voltage, the need to use the power electronic converters as one of the types of power electronic equipment to increase the output voltage levels has increased more than before. Therefore, along with the increasing development of renewable energy, the power electronic converters, which are one of their vital elements, have also undergone changes, including design in the structure in order to increase efficiency and performance. The conventional DC-DC boost converters have been widely used in photovoltaic (PV) systems in the past. Although they have a simple structure, their high voltage stress, low power density, output voltage sensitivity to the duty cycle, reverse recovery problem, and high current ripple limit their use. By storing energy at the input of the step-up DC-DC converter and releasing it towards the output, the DC voltage increases [1]. Basically, such topologies are divided into isolated and nonisolated structures [2]. The isolated converters, although they have a high voltage conversion ratio [3], are large in size due to the use of transformers and inductors. Their production cost and electromagnetic interference (EMI) are high. The flyback [4, 5] and the forward [6, 7] are examples of this category. Therefore, understanding the above conditions in relation to the first category, the desire to use nonisolated converters is quite evident. The nonisolated step-up DC-DC converters are based on conventional boost converters that are designed and created by applying and adding voltage boosting techniques to their circuit structure and creating novel topologies. These techniques are mainly created with the help of circuit elements, including diodes, capacitors, and inductors. The switched capacitors [8, 9], the switched inductors [8, 10], and the voltage multipliers [11] are among the most important voltage boosting techniques. The use of coupled inductors [12] and multiphase converter topology, the so-called interleaved [13], are some of the most effective voltage gain boosting techniques that researchers today use frequently in their designs. The number of magnetic cores will definitely decrease with the help of coupled inductors. Also, the current ripple is reduced using the interleaved technique, and as a result, the power density will be increased. At present, the problem of increasing the voltage gain by using voltage boosting techniques, either individually or in combination with these techniques in newer topologies, is still of interest to researchers. In such complex structures, in addition to the voltage gain in high power applications, other important characteristics such as reducing the voltage stress of semiconductors, reducing current ripple, and creating soft-switching conditions to reduce loss and increase efficiency should also be considered. In [14], a high step-up DC-DC converter used the Cockcroft–Walton (CW) multiplier. Although the converter has a low input current ripple, the voltage gain is entirely dependent on the number of stages of the converter. The switched-capacitor/the switched-inductor technique is used in [15]. The voltage and current stress are less than the output voltage in this converter, but the pulsating input current and the developed modules from the switched capacitor/the switched inductor are among the disadvantages of this converter. A high step-up DC-DC converter topology consisting of coupled inductors and switched capacitors has been introduced by researchers in [16]. The zero-voltage switching (ZVS) conditions have increased the efficiency of the converter. The dependence of the voltage gain on the duty cycle is the most important defect of this converter. The same technique is used in [17]. This integration has increased the output voltage for use in the renewable energy conversion systems, but the leakage energy of the inductors has caused voltage spikes on the power switches, necessitating a passive or active clamp circuit. In [18], a novel topology is introduced based on the coupled inductor and SEPIC DC-DC converter, which have been evaluated from different aspects. This structure has low efficiency along with the desired characteristics. An ultrastep-up DC-DC converter was proposed in [19], which increases the output voltage by using a lift circuit. Due to the multiplicity of circuit components, the converter control becomes complicated. In [20], a nonisolated high step-up DC-DC converter is provided, which is based on quasi-Z-source (QZS) and the coupled inductor. In this topology, the input current is completely continuous. Also, by applying high turns ratios, there is no interference in boosting the output voltage level. In [21], a high step-up DC-DC converter is introduced. Researchers at [21] were able to increase the output voltage level by integrating and embedding voltage multiplier cell (VMC) and three-winding coupled inductor techniques in the design. Also, leakage energy absorption, low-voltage stress, reduction of reverse recovery loss, and desired efficiency are the advantages of this converter. Of course, it is noted that the complexity of the circuit increases with the three-winding coupled inductor. It was shown by researchers in [22] that the voltage boosting capability is carried out by the interleaved structure, coupled inductors, and voltage lift capacitors. In addition to the features provided in [21], the input current ripple is also drastically reduced. In this converter, soft-switching conditions can also be seen on MOSFETs. Table 1 shows the shortcomings of the above techniques.Table 1
Shortcomings of voltage boosting techniques.
TopologiesFlybackForwardSwitched capacitorsSwitched inductorsInterleavedCoupled inductorCockcroft–WaltonQuasi-Z-sourceShortcoming(i) Require additional snubber circuit(i) Minimum load requirements(i) Diode reverse recovery(i) Low efficiency(i) Phase asymmetry in case of improper design(i) Leakage inductance losses(i) Limited switching frequency(i) Electromagnetic interference issue(ii) High RMS current rating of output capacitor(ii) Higher voltage demand for MOSFET(ii) Electromagnetic interference issue(ii) Large number of diodes and capacitors(ii) Problem of core and copper losses(ii) Low power density(ii) Need to output LC filter(iii) Leakage inductance losses(iii) Low efficiency(iii) High switching frequencyThis paper suggests a novel nonisolated ultrahigh step-up DC-DC converter with interleaved structure and a design that includes a combination of coupled inductors and switched-capacitor cells. The main contributions of this study are as follows:(i)
The voltage conversion ratio increases with the help of the switched-capacitor technique and the series connection of the secondary windings of the coupled inductors. Such an achievement is achieved without imposing any high extreme duty cycles on the system and high turns ratios. Therefore, the proposed converter is suitable for high voltage and high power applications.(ii)
The proposed converter has a very low switch voltage stress; thus, low-voltage-rating MOSFETs with a small on-resistance can be used to reduce conduction loss and as a result high efficiency.(iii)
The ZCS turn-on of the switches is realized in the proposed converter, and the reverse recovery problem of the diodes is alleviated, which helps reduce the switching losses.(iv)
The input current ripple is significantly reduced with the help of the interleaved technique.(v)
The leakage energy is absorbed, and there is no need to use active or passive clamp circuits.(vi)
The proposed converter has a desired dynamic response so that by changing the load current, the output voltage changes quickly and with the appropriate magnitude.This paper consists of the following sections. The structure and operation principles of the converter are described in Section2. The steady-state converter analysis is described in Section 3. The design of the converter circuit components is given in Section 4. The converter losses analysis is described in Section 5. The dynamic performance of the proposed converter is described in Section 6. A comparison of the performance of the proposed converter with other similar converters is presented in Section 7. The experimental results and conclusions are described in Sections 8 and 9, respectively.


## 2. Proposed Converter Structure

Figure1 shows the structure and power circuit of the proposed converter. The converter is based on a boost converter and has a two-phase interleaved form [23]. It consists of circuit components as follows: the input stage has two coupled inductors and two power switches (S1; S2). In the middle stage, it has six diodes (D1–D6) and five capacitors (C1–C5) as energy transfer. Finally, the output capacitor (Co) and the load (R) are located in the output stage. As can be seen from Figure 1, the converter has two coupled inductors with primary and secondary windings that are parallel and series, respectively, neutralizing the current ripple and increasing the voltage. Also, the two cells of the switched capacitors were placed back to back in order to achieve ultrahigh voltage gain. The turns ratios are similar for both coupled inductors. Coupling references are shown in Figure 1 with symbols ∎ and Ο. The equivalent circuit of the proposed structure is illustrated in Figure 2. The coupled inductors are modeled by an ideal transformer, the leakage inductances (Lk), and the magnetizing inductances (Lm). Due to the relevant topology, analysis is performed in the continuous conduction mode (CCM), this analysis is in the steady state, and then the duty cycle should be selected larger than 0.5 in design. The converter has eight operation modes, the details of which are described in the following. The key waveforms for the proposed converter are shown in Figure 3. The equivalent circuits of all eight operation modes are also illustrated in detail in Figure 4.Figure 1
Power circuit of the proposed converter.Figure 2
Equivalent circuit of the proposed converter.Figure 3
Key waveforms in CCM operation.Figure 4
Circuits corresponding to the operation modes: (a) mode 1 [t0-t1]; (b) mode 2 [t1-t2]; (c) mode 3 [t2-t3]; (d) mode 4 [t3-t4]; (e) mode 5 [t4-t5]; (f) mode 6 [t5-t6]; (g) mode 7 [t6-t7]; (h) mode 8 [t7-t0].
(a)(b)(c)(d)(e)(f)(g)(h)


### 2.1. Operation Principles

To simplify the analysis of the proposed structure, the following assumptions are taken into account:(1)
All the circuit components are ideal in the proposed structure.(2)
The capacitors are large enough so that the voltages across them are constant.


#### 2.1.1. Mode 1 [t0-t1]

S1 and S2 are ON in this mode as shown in Figure 4(a). D1, D2, D3, and D5 are OFF. iD4 and iD6 start to decrease from the beginning of this mode. The leakage inductances dominate the falling rate of both diodes and will alleviate the reverse recovery problem. The falling rates of D4 and D6 are as follows:(1)diD4tdt=−VC2+VC4−VC1−VC3n2Lk1+Lk2,diD6tdt=−Vo−VC1−VC3−VC5n2Lk1+Lk2,where n=Na1/Na0=Nb1/Nb0.


#### 2.1.2. Mode 2 [t1-t2]

It is clear from Figure4(b) that all diodes are OFF in this mode. The magnetizing inductances and the leakage inductances are supplied by the input voltage source. By ignoring the leakage inductance relative to the magnetizing inductance in terms of quantity, the following equations are obtained:(2)vm1=Vi,vm2=Vi.


#### 2.1.3. Mode 3 [t2-t3]

S1 is turned off at t2 as shown in Figure 4(c). D1 and D5 conduct. Lk2 and Lm2 are charged through the input, and Lk1 and Lm1 are releasing energy. The leakage current, ik1, charges C1, and the other capacitors are exchanging energy. The resulting equations are as follows:(3)vm1=Vi−VC1,(4)vm2=Vi.


#### 2.1.4. Mode 4 [t3-t4]

In the previous mode,iD1 decreases linearly. This current becomes zero at t3, and D1 turns off naturally according to Figure 4(d), which will alleviate the reverse recovery problem. In this mode, D3 starts to conduct. The equations are as follows:(5)Vi=VC1−VC2+VC3−nvm2−vm1+vm1,vm2=Vi.


#### 2.1.5. Mode 5 [t4-t5]

S1 is turned on at t4 as shown in Figure 4(e). Because the leakage inductance prevents the changes in the current rate, zero-current switching (ZCS) is achieved for this switch. iD3 and iD5 decrease. The leakage inductances dominate the falling rate of D3 and D5 and will alleviate the reverse recovery problem. The falling rates of D3 and D5 are as follows:(6)diD3tdt=−VC1+VC3−VC2n2Lk1+Lk2,diD5tdt=−VC1+VC3+VC5−VC2−VC4n2Lk1+Lk2.


#### 2.1.6. Mode 6 [t5-t6]

In this mode, iD3 and iD5 become zero at t5, and both diodes are turned off. In this way, all the diodes turn off. This mode is actually similar to mode 2. The circuit corresponding to mode 6 is given in Figure4(f).


#### 2.1.7. Mode 7 [t6-t7]

S2 is turned off at t6 as shown in Figure4(g). D2 and D4 conduct. Lk1 and Lm1 are charged through the input source, and Lk2 and Lm2 are releasing energy. C1 and C3 are discharged, and the load current is supplied instead. The series windings and C3 play the role of a voltage source, which further expands the voltage gain. iD2 is decreased, and subsequently, C2 is charged. The resulting equations are as follows:(7)vm1=Vi,(8)vm2=Vi+VC1−VC2.


#### 2.1.8. Mode 8 [t7-t0]

iD2 was decreasing linearly in the previous mode so that it becomes zero at t7. D2 is turned off naturally according to Figure 4(h), which will alleviate the reverse recovery problem. In this mode, D6 starts to conduct. C1 and C3 are discharged, and the load current is supplied. S2 is turned on at the end of mode 8 at t0. The ZCS is achieved for this switch because the leakage inductance prevents the changes in the current rate. The equations are as follows:(9)Vi=Vo+vm2−VC1−VC3−VC5−nvm1−vm2.


## 2.1. Operation Principles

To simplify the analysis of the proposed structure, the following assumptions are taken into account:(1)
All the circuit components are ideal in the proposed structure.(2)
The capacitors are large enough so that the voltages across them are constant.


### 2.1.1. Mode 1 [t0-t1]

S1 and S2 are ON in this mode as shown in Figure 4(a). D1, D2, D3, and D5 are OFF. iD4 and iD6 start to decrease from the beginning of this mode. The leakage inductances dominate the falling rate of both diodes and will alleviate the reverse recovery problem. The falling rates of D4 and D6 are as follows:(1)diD4tdt=−VC2+VC4−VC1−VC3n2Lk1+Lk2,diD6tdt=−Vo−VC1−VC3−VC5n2Lk1+Lk2,where n=Na1/Na0=Nb1/Nb0.


### 2.1.2. Mode 2 [t1-t2]

It is clear from Figure4(b) that all diodes are OFF in this mode. The magnetizing inductances and the leakage inductances are supplied by the input voltage source. By ignoring the leakage inductance relative to the magnetizing inductance in terms of quantity, the following equations are obtained:(2)vm1=Vi,vm2=Vi.


### 2.1.3. Mode 3 [t2-t3]

S1 is turned off at t2 as shown in Figure 4(c). D1 and D5 conduct. Lk2 and Lm2 are charged through the input, and Lk1 and Lm1 are releasing energy. The leakage current, ik1, charges C1, and the other capacitors are exchanging energy. The resulting equations are as follows:(3)vm1=Vi−VC1,(4)vm2=Vi.


### 2.1.4. Mode 4 [t3-t4]

In the previous mode,iD1 decreases linearly. This current becomes zero at t3, and D1 turns off naturally according to Figure 4(d), which will alleviate the reverse recovery problem. In this mode, D3 starts to conduct. The equations are as follows:(5)Vi=VC1−VC2+VC3−nvm2−vm1+vm1,vm2=Vi.


### 2.1.5. Mode 5 [t4-t5]

S1 is turned on at t4 as shown in Figure 4(e). Because the leakage inductance prevents the changes in the current rate, zero-current switching (ZCS) is achieved for this switch. iD3 and iD5 decrease. The leakage inductances dominate the falling rate of D3 and D5 and will alleviate the reverse recovery problem. The falling rates of D3 and D5 are as follows:(6)diD3tdt=−VC1+VC3−VC2n2Lk1+Lk2,diD5tdt=−VC1+VC3+VC5−VC2−VC4n2Lk1+Lk2.


### 2.1.6. Mode 6 [t5-t6]

In this mode, iD3 and iD5 become zero at t5, and both diodes are turned off. In this way, all the diodes turn off. This mode is actually similar to mode 2. The circuit corresponding to mode 6 is given in Figure4(f).


### 2.1.7. Mode 7 [t6-t7]

S2 is turned off at t6 as shown in Figure4(g). D2 and D4 conduct. Lk1 and Lm1 are charged through the input source, and Lk2 and Lm2 are releasing energy. C1 and C3 are discharged, and the load current is supplied instead. The series windings and C3 play the role of a voltage source, which further expands the voltage gain. iD2 is decreased, and subsequently, C2 is charged. The resulting equations are as follows:(7)vm1=Vi,(8)vm2=Vi+VC1−VC2.


### 2.1.8. Mode 8 [t7-t0]

iD2 was decreasing linearly in the previous mode so that it becomes zero at t7. D2 is turned off naturally according to Figure 4(h), which will alleviate the reverse recovery problem. In this mode, D6 starts to conduct. C1 and C3 are discharged, and the load current is supplied. S2 is turned on at the end of mode 8 at t0. The ZCS is achieved for this switch because the leakage inductance prevents the changes in the current rate. The equations are as follows:(9)Vi=Vo+vm2−VC1−VC3−VC5−nvm1−vm2.


## 2.1.1. Mode 1 [t0-t1]

S1 and S2 are ON in this mode as shown in Figure 4(a). D1, D2, D3, and D5 are OFF. iD4 and iD6 start to decrease from the beginning of this mode. The leakage inductances dominate the falling rate of both diodes and will alleviate the reverse recovery problem. The falling rates of D4 and D6 are as follows:(1)diD4tdt=−VC2+VC4−VC1−VC3n2Lk1+Lk2,diD6tdt=−Vo−VC1−VC3−VC5n2Lk1+Lk2,where n=Na1/Na0=Nb1/Nb0.


## 2.1.2. Mode 2 [t1-t2]

It is clear from Figure4(b) that all diodes are OFF in this mode. The magnetizing inductances and the leakage inductances are supplied by the input voltage source. By ignoring the leakage inductance relative to the magnetizing inductance in terms of quantity, the following equations are obtained:(2)vm1=Vi,vm2=Vi.


## 2.1.3. Mode 3 [t2-t3]

S1 is turned off at t2 as shown in Figure 4(c). D1 and D5 conduct. Lk2 and Lm2 are charged through the input, and Lk1 and Lm1 are releasing energy. The leakage current, ik1, charges C1, and the other capacitors are exchanging energy. The resulting equations are as follows:(3)vm1=Vi−VC1,(4)vm2=Vi.


## 2.1.4. Mode 4 [t3-t4]

In the previous mode,iD1 decreases linearly. This current becomes zero at t3, and D1 turns off naturally according to Figure 4(d), which will alleviate the reverse recovery problem. In this mode, D3 starts to conduct. The equations are as follows:(5)Vi=VC1−VC2+VC3−nvm2−vm1+vm1,vm2=Vi.


## 2.1.5. Mode 5 [t4-t5]

S1 is turned on at t4 as shown in Figure 4(e). Because the leakage inductance prevents the changes in the current rate, zero-current switching (ZCS) is achieved for this switch. iD3 and iD5 decrease. The leakage inductances dominate the falling rate of D3 and D5 and will alleviate the reverse recovery problem. The falling rates of D3 and D5 are as follows:(6)diD3tdt=−VC1+VC3−VC2n2Lk1+Lk2,diD5tdt=−VC1+VC3+VC5−VC2−VC4n2Lk1+Lk2.


## 2.1.6. Mode 6 [t5-t6]

In this mode, iD3 and iD5 become zero at t5, and both diodes are turned off. In this way, all the diodes turn off. This mode is actually similar to mode 2. The circuit corresponding to mode 6 is given in Figure4(f).


## 2.1.7. Mode 7 [t6-t7]

S2 is turned off at t6 as shown in Figure4(g). D2 and D4 conduct. Lk1 and Lm1 are charged through the input source, and Lk2 and Lm2 are releasing energy. C1 and C3 are discharged, and the load current is supplied instead. The series windings and C3 play the role of a voltage source, which further expands the voltage gain. iD2 is decreased, and subsequently, C2 is charged. The resulting equations are as follows:(7)vm1=Vi,(8)vm2=Vi+VC1−VC2.


## 2.1.8. Mode 8 [t7-t0]

iD2 was decreasing linearly in the previous mode so that it becomes zero at t7. D2 is turned off naturally according to Figure 4(h), which will alleviate the reverse recovery problem. In this mode, D6 starts to conduct. C1 and C3 are discharged, and the load current is supplied. S2 is turned on at the end of mode 8 at t0. The ZCS is achieved for this switch because the leakage inductance prevents the changes in the current rate. The equations are as follows:(9)Vi=Vo+vm2−VC1−VC3−VC5−nvm1−vm2.


## 3. Steady-State Analysis

### 3.1. Voltage Gain

With the help of the volt-second balance principle and its use for magnetizing inductance, the following expressions are expressed:(10)vm1OnDT+vm1Off1−DT=0⇒ViDT+Vi−VC11−DT=0,where D and T are the duty cycle and the switching period, respectively.By solving (18), the voltage of C1 is obtained as follows:(11)VC1=11−DVi.Using (19) and placing (20) in it, the following equation can be reached:(12)VC2=21−DVi.Using equations (3)–(5) and (7) and also (20) and (21), the voltage of C3 is obtained as follows:(13)VC3=n+21−DVi.Using equations (9)–(11) and (16) to (17), the voltage of C4 is obtained as follows:(14)VC4=2n+21−DVi.Thus, using (10),(15)VC5=2n+21−DVi.Using (14) and (16) and also (20) to (22) and (24), the voltage gain of the proposed converter is found as follows:(16)M=VoVi=4n+61−D.Figure5 shows the relationship between the voltage gain of the proposed converter and the duty cycle based on the different turns ratios. It is clear that the proposed converter has an ultrahigh step-up voltage gain without any extreme duty cycle imposition or a high turns ratio.Figure 5
Voltage gain against the duty cycle by considering different turns ratios.


### 3.2. Voltage Stress

The voltage stresses of the circuit capacitors are found using the capacitor voltage equations described in the previous section. Thus, by applying equations (20) to (24) and placing (25) in them, the voltage stresses equations associated with the capacitors are obtained as follows:(17)VC1=14n+6Vo;VC2=24n+6Vo,VC3=n+24n+6Vo;VC4=VC5=2n+24n+6Vo.The voltage stress of the second switch is clamped byC1 and C2 in mode 7. Therefore, considering VC2-VC1,(18)VS1=VS2=11−DVi=14n+6Vo.It is clear from (27) that, by considering n = 1, the voltage stresses of the switches are one-tenth of the output voltage. As a result, the conduction losses are reduced with a small RDS(on).According to the operation principles of the proposed converter and operation modes, as well as using Kirchhoff’s voltage law, the voltage stresses of the diodes can be found from the voltage equations of the capacitors as follows:(19)VD1=VD2=−VC2=24n+6Vo,VD3=VD4=−VC4=2n+24n+6Vo,VD5=−VC5=2n+24n+6Vo,VD6=VC1+VC3+VC5−Vo=n+14n+6Vo.Figure6 depicts the normalized voltage stresses of semiconductors and the circuit capacitors based on equations (26) to (28). It is clear from Figure 6 that the voltage stresses on S1, S2, C1, C2, C3, D1, and D2 decrease by increasing the turns ratio of the coupled inductors. Voltage stresses increase very little for the other circuit components by increasing the turns ratio. However, their voltage stresses are still lower than the output voltage.Figure 6
Normalized voltage stresses (NVS) of the circuit components.


### 3.3. Input Current Ripple and Magnetizing Inductance

By the voltage gain equation and as well asPi = Po, the ratio of the output current to the input current of the proposed converter can be expressed as follows:(20)IoIiAvg=1−D4n+6.Due to the use of a two-phase interleaved structure and considering that the average magnetizing currents are calledIm1_Avg and Im2_Avg as well as Im1_Avg = Im2_Avg = Im_Avg, they are described by the following equation with the help of (29):(21)Im1_Avg=Im2_Avg=Im_Avg=Ii_Avg2=2n+31−DIo_Avg,where Ii_Avg and Io_Avg are the average input and output currents, respectively. It is clear from (30) that these currents are balanced. In association with the secondary windings of the coupled inductors, which are in series, it is pointed out that they share the same secondary current. Given this point and the fact that the input current is the sum of the primary currents in the coupled inductors, therefore the input current is expressed as follows:(22)ii=im1+niSec+im2−niSec=im1+im2.According to the operation principles of the proposed converter and according to the interleaved structure, the input current ripple frequency is twice the switching frequency,fs, which means that the input current is continuous and its ripple is remarkably reduced. The power switches are turned on in DT, and the voltage of the input inductors is equal to Vi. Therefore, using Faraday’s law, the ripple of the magnetizing and input currents is expressed by (32) and (33),(23)Δim=DLmfsVi,(24)Δii=2D−1LmfsVi.Figure7 shows the current ripple curve normalized for the input current and the magnetizing current. The current ripple is also lower in smaller duty cycles. This means that the size of the coupled inductors can also be designed less. Consequently, the current stress is reduced in the input capacitor, which increases the power density.Figure 7
Normalized current ripple (NCR) by considering (33)/(32).


## 3.1. Voltage Gain

With the help of the volt-second balance principle and its use for magnetizing inductance, the following expressions are expressed:(10)vm1OnDT+vm1Off1−DT=0⇒ViDT+Vi−VC11−DT=0,where D and T are the duty cycle and the switching period, respectively.By solving (18), the voltage of C1 is obtained as follows:(11)VC1=11−DVi.Using (19) and placing (20) in it, the following equation can be reached:(12)VC2=21−DVi.Using equations (3)–(5) and (7) and also (20) and (21), the voltage of C3 is obtained as follows:(13)VC3=n+21−DVi.Using equations (9)–(11) and (16) to (17), the voltage of C4 is obtained as follows:(14)VC4=2n+21−DVi.Thus, using (10),(15)VC5=2n+21−DVi.Using (14) and (16) and also (20) to (22) and (24), the voltage gain of the proposed converter is found as follows:(16)M=VoVi=4n+61−D.Figure5 shows the relationship between the voltage gain of the proposed converter and the duty cycle based on the different turns ratios. It is clear that the proposed converter has an ultrahigh step-up voltage gain without any extreme duty cycle imposition or a high turns ratio.Figure 5
Voltage gain against the duty cycle by considering different turns ratios.


## 3.2. Voltage Stress

The voltage stresses of the circuit capacitors are found using the capacitor voltage equations described in the previous section. Thus, by applying equations (20) to (24) and placing (25) in them, the voltage stresses equations associated with the capacitors are obtained as follows:(17)VC1=14n+6Vo;VC2=24n+6Vo,VC3=n+24n+6Vo;VC4=VC5=2n+24n+6Vo.The voltage stress of the second switch is clamped byC1 and C2 in mode 7. Therefore, considering VC2-VC1,(18)VS1=VS2=11−DVi=14n+6Vo.It is clear from (27) that, by considering n = 1, the voltage stresses of the switches are one-tenth of the output voltage. As a result, the conduction losses are reduced with a small RDS(on).According to the operation principles of the proposed converter and operation modes, as well as using Kirchhoff’s voltage law, the voltage stresses of the diodes can be found from the voltage equations of the capacitors as follows:(19)VD1=VD2=−VC2=24n+6Vo,VD3=VD4=−VC4=2n+24n+6Vo,VD5=−VC5=2n+24n+6Vo,VD6=VC1+VC3+VC5−Vo=n+14n+6Vo.Figure6 depicts the normalized voltage stresses of semiconductors and the circuit capacitors based on equations (26) to (28). It is clear from Figure 6 that the voltage stresses on S1, S2, C1, C2, C3, D1, and D2 decrease by increasing the turns ratio of the coupled inductors. Voltage stresses increase very little for the other circuit components by increasing the turns ratio. However, their voltage stresses are still lower than the output voltage.Figure 6
Normalized voltage stresses (NVS) of the circuit components.


## 3.3. Input Current Ripple and Magnetizing Inductance

By the voltage gain equation and as well asPi = Po, the ratio of the output current to the input current of the proposed converter can be expressed as follows:(20)IoIiAvg=1−D4n+6.Due to the use of a two-phase interleaved structure and considering that the average magnetizing currents are calledIm1_Avg and Im2_Avg as well as Im1_Avg = Im2_Avg = Im_Avg, they are described by the following equation with the help of (29):(21)Im1_Avg=Im2_Avg=Im_Avg=Ii_Avg2=2n+31−DIo_Avg,where Ii_Avg and Io_Avg are the average input and output currents, respectively. It is clear from (30) that these currents are balanced. In association with the secondary windings of the coupled inductors, which are in series, it is pointed out that they share the same secondary current. Given this point and the fact that the input current is the sum of the primary currents in the coupled inductors, therefore the input current is expressed as follows:(22)ii=im1+niSec+im2−niSec=im1+im2.According to the operation principles of the proposed converter and according to the interleaved structure, the input current ripple frequency is twice the switching frequency,fs, which means that the input current is continuous and its ripple is remarkably reduced. The power switches are turned on in DT, and the voltage of the input inductors is equal to Vi. Therefore, using Faraday’s law, the ripple of the magnetizing and input currents is expressed by (32) and (33),(23)Δim=DLmfsVi,(24)Δii=2D−1LmfsVi.Figure7 shows the current ripple curve normalized for the input current and the magnetizing current. The current ripple is also lower in smaller duty cycles. This means that the size of the coupled inductors can also be designed less. Consequently, the current stress is reduced in the input capacitor, which increases the power density.Figure 7
Normalized current ripple (NCR) by considering (33)/(32).


## 4. Design Considerations

### 4.1. Coupled Inductors

It is necessary to select a duty cycle that is larger than 0.5 to determine the turns ratio of the coupled inductors. By selecting the required output voltage, the turns ratio of the coupled inductors can be found with consideration of (25) and according to the following equation:(25)n=M1−D−64.The magnetizing inductances are obtained by consideringLm = Lm1 = Lm2 and considering (32) and based on the magnetizing current ripple according to (35),(26)Lm1=Lm2=Lm=DΔimfsVi.It should beIm_Avg > (½) ∙∆im to ensure that the converter operates on CCM. Therefore, the minimum magnetizing inductance is in accordance with (36):(27)Lm≻121−DD2n+3Io_AvgfsVi.Since the leakage inductances play an important role in alleviating the reverse recovery problem of diodes, therefore, the falling rate of diodes can be used to calculate the leakage inductances. Thus, by applying the absolute of (11) as well as considering equations (20) to (22) and (25), (37) is obtained:(28)Lk1=Lk2=Lk=n+142n+3n2xVo,diD3tdt=x.The peak magnetizing currents are obtained by considering (30) and (32) according to the following equation:(29)Im1_Pk=Im2_Pk=Im_Pk=2n+31−DIo_Avg+12DLmfsVi.


### 4.2. Semiconductors

All diodes and power switches are designed based on their voltage stresses. Furthermore, the average current of all diodes is equal to the average output current because the converter operates in CCM, and also the average current of the capacitors is zero in one switching period. Then,(30)ID1_Avg…ID6_Avg=Io_Avg.Also, the relationship between the average output current and the peak current of the diodes can be expressed according to equations (40). The peak current of the diodes will then be obtained by arranging equation (40) according to equation (41):(31)Io_Avg=12ID1_Pk…ID6_Pk1−D,(32)ID1_Pk…ID6_Pk=21−DIo_Avg.Using the principles of operation of the proposed converter and the fourth and seventh operation modes, the peak current of the power switches is expressed as follows:(33)IS1_Pk≃Ii_Avg2+ID2_Pk+nID4_Pk=4n+51−DIo_Avg,IS2_Pk≃Ii_Avg2+nID3_Pk+nID5_Pk=6n+31−DIo_Avg.Also, the RMS current of the switches using the operation principles and (30) is as follows:(34)IS1_RMS=2n+31−DIo_Avg−1−2D−41−Dn3+3n2+3n+1n3+4n2+5n+2,(35)IS2_RMS=2n+31−DIo_Avg3−2D.


### 4.3. Capacitors

The circuit capacitors are calculated and designed based on their voltage stresses, output power, and considering the voltage ripple according to the following equations:(36)C1=4n+6ΔvCVo2fsPo;C2=2n+3ΔvCVo2fsPo,C3=4n+6n+2ΔvCVo2fsPo;C4=C5=2n+3n+1ΔvCVo2fsPo,where Po and ∆VC are the output power and the voltage ripple of capacitors, respectively. It is worth noting that the use of capacitors with a low equivalent series resistance (ESR) such as metalized polyester film (MKT) can reduce power losses and improve efficiency.


## 4.1. Coupled Inductors

It is necessary to select a duty cycle that is larger than 0.5 to determine the turns ratio of the coupled inductors. By selecting the required output voltage, the turns ratio of the coupled inductors can be found with consideration of (25) and according to the following equation:(25)n=M1−D−64.The magnetizing inductances are obtained by consideringLm = Lm1 = Lm2 and considering (32) and based on the magnetizing current ripple according to (35),(26)Lm1=Lm2=Lm=DΔimfsVi.It should beIm_Avg > (½) ∙∆im to ensure that the converter operates on CCM. Therefore, the minimum magnetizing inductance is in accordance with (36):(27)Lm≻121−DD2n+3Io_AvgfsVi.Since the leakage inductances play an important role in alleviating the reverse recovery problem of diodes, therefore, the falling rate of diodes can be used to calculate the leakage inductances. Thus, by applying the absolute of (11) as well as considering equations (20) to (22) and (25), (37) is obtained:(28)Lk1=Lk2=Lk=n+142n+3n2xVo,diD3tdt=x.The peak magnetizing currents are obtained by considering (30) and (32) according to the following equation:(29)Im1_Pk=Im2_Pk=Im_Pk=2n+31−DIo_Avg+12DLmfsVi.


## 4.2. Semiconductors

All diodes and power switches are designed based on their voltage stresses. Furthermore, the average current of all diodes is equal to the average output current because the converter operates in CCM, and also the average current of the capacitors is zero in one switching period. Then,(30)ID1_Avg…ID6_Avg=Io_Avg.Also, the relationship between the average output current and the peak current of the diodes can be expressed according to equations (40). The peak current of the diodes will then be obtained by arranging equation (40) according to equation (41):(31)Io_Avg=12ID1_Pk…ID6_Pk1−D,(32)ID1_Pk…ID6_Pk=21−DIo_Avg.Using the principles of operation of the proposed converter and the fourth and seventh operation modes, the peak current of the power switches is expressed as follows:(33)IS1_Pk≃Ii_Avg2+ID2_Pk+nID4_Pk=4n+51−DIo_Avg,IS2_Pk≃Ii_Avg2+nID3_Pk+nID5_Pk=6n+31−DIo_Avg.Also, the RMS current of the switches using the operation principles and (30) is as follows:(34)IS1_RMS=2n+31−DIo_Avg−1−2D−41−Dn3+3n2+3n+1n3+4n2+5n+2,(35)IS2_RMS=2n+31−DIo_Avg3−2D.


## 4.3. Capacitors

The circuit capacitors are calculated and designed based on their voltage stresses, output power, and considering the voltage ripple according to the following equations:(36)C1=4n+6ΔvCVo2fsPo;C2=2n+3ΔvCVo2fsPo,C3=4n+6n+2ΔvCVo2fsPo;C4=C5=2n+3n+1ΔvCVo2fsPo,where Po and ∆VC are the output power and the voltage ripple of capacitors, respectively. It is worth noting that the use of capacitors with a low equivalent series resistance (ESR) such as metalized polyester film (MKT) can reduce power losses and improve efficiency.


## 5. Loss Breakdown

The proposed converter losses mainly consist of three important parts, including losses related to the power switches, the diodes, and the coupled inductors. Here, the losses of circuit capacitors are neglected due to the use of a low ESR type. Therefore, using the steady-state analysis as well as the circuit components datasheet used here, the loss breakdown of the proposed converter is as follows.


### 5.1. Diodes

The diode losses consist of the conduction loss and the reverse recovery loss as follows:(37)PD_Loss=PD_Con+PD_Rev,where PD_Con and PD_Rev are the conduction loss and the reverse recovery loss, respectively. The first term is related to when the diode is conducted. It is found by relying on the diode datasheet and the average diode current as follows:(38)PD_Con=VF⋅ID_Avg,where VF is the forward voltage. Due to the performance of the proposed converter, which alleviates the reverse recovery of the diodes, PD_Rev can be neglected. Therefore, the total losses of the diodes are extracted as follows:(39)PD_Loss=6⋅VF⋅ID_Avg=3⋅0.86⋅0.87+3⋅0.9⋅0.87=4.5W.


### 5.2. Switches

The switch losses consist of the conduction loss and the switching loss as follows:(40)PS_Loss=PS_Con+PS_Sw,where PS_Con and PS_Sw are the conduction loss and the switching loss, respectively. PS_Con is found by relying on the switch datasheet and equations (44) and (45) as follows:(41)PS_Con=RdsOn⋅IS_RMS2=7.2︸mΩ9.32+14.52=2.1W.The switching loss is also obtained by referring to the power switch datasheet and using the maximum voltage stress of the switches based on (27) as follows:(42)PS_Sw=0.5⋅IS⋅VStOn+tOfffs=20.5⋅12⋅4052+21︸nsec47︸kHz=1.6W,where tOn and tOff are rise and fall times, respectively. IS is the switch current in the turn-off period because the power switches are turned on with ZCS.


### 5.3. Coupled Inductors

The losses of the coupled inductors consist of their core and the copper used in the windings. These losses include both the primary and secondary sides. Thus,(43)PCi_Loss=PCi_Cor+PCi_Cop.The core loss, a large part of which is related to hysteresis loss, according to the Steinmetz equation, can be expressed as follows:(44)PCi_Cor=K⋅fα⋅BMaxβ⋅Ac⋅lc=2⋅0.56=1.12W.In equation (51), the coefficients of K = 0.000214, α = 1.26, and β = 2.21 can be found from the core datasheet. BMAX, Ac, and lc are the maximum core flux density, a cross-sectional area of the core, and the mean path length of the core, respectively.The copper loss is calculated for both primary and secondary withINa0_RMS = 12.8 A, INa1_RMS = ISec_RMS =  4.9 A, and RDC = 7.32 m Ω as follows:(45)PCi_Cop=2RDCINa0_RMS2+INa1_RMS2=2.75W.Figure8 illustrates the distribution of loss in the proposed converter. As can be seen, the largest share of the proposed converter losses is for the diode loss. As mentioned earlier, in this part, the major share of loss generation is related to the conduction loss of the diodes. After that, although the loss of the coupled inductors was calculated and expressed separately, as can be seen from Figure 8, their aggregation into two forms of the core and the copper loss also include a major share of the proposed converter losses. The lowest losses belong to the power switches, which is the sum of the switching and the conduction loss.Figure 8
Distribution of losses in the circuit components.


## 5.1. Diodes

The diode losses consist of the conduction loss and the reverse recovery loss as follows:(37)PD_Loss=PD_Con+PD_Rev,where PD_Con and PD_Rev are the conduction loss and the reverse recovery loss, respectively. The first term is related to when the diode is conducted. It is found by relying on the diode datasheet and the average diode current as follows:(38)PD_Con=VF⋅ID_Avg,where VF is the forward voltage. Due to the performance of the proposed converter, which alleviates the reverse recovery of the diodes, PD_Rev can be neglected. Therefore, the total losses of the diodes are extracted as follows:(39)PD_Loss=6⋅VF⋅ID_Avg=3⋅0.86⋅0.87+3⋅0.9⋅0.87=4.5W.


## 5.2. Switches

The switch losses consist of the conduction loss and the switching loss as follows:(40)PS_Loss=PS_Con+PS_Sw,where PS_Con and PS_Sw are the conduction loss and the switching loss, respectively. PS_Con is found by relying on the switch datasheet and equations (44) and (45) as follows:(41)PS_Con=RdsOn⋅IS_RMS2=7.2︸mΩ9.32+14.52=2.1W.The switching loss is also obtained by referring to the power switch datasheet and using the maximum voltage stress of the switches based on (27) as follows:(42)PS_Sw=0.5⋅IS⋅VStOn+tOfffs=20.5⋅12⋅4052+21︸nsec47︸kHz=1.6W,where tOn and tOff are rise and fall times, respectively. IS is the switch current in the turn-off period because the power switches are turned on with ZCS.


## 5.3. Coupled Inductors

The losses of the coupled inductors consist of their core and the copper used in the windings. These losses include both the primary and secondary sides. Thus,(43)PCi_Loss=PCi_Cor+PCi_Cop.The core loss, a large part of which is related to hysteresis loss, according to the Steinmetz equation, can be expressed as follows:(44)PCi_Cor=K⋅fα⋅BMaxβ⋅Ac⋅lc=2⋅0.56=1.12W.In equation (51), the coefficients of K = 0.000214, α = 1.26, and β = 2.21 can be found from the core datasheet. BMAX, Ac, and lc are the maximum core flux density, a cross-sectional area of the core, and the mean path length of the core, respectively.The copper loss is calculated for both primary and secondary withINa0_RMS = 12.8 A, INa1_RMS = ISec_RMS =  4.9 A, and RDC = 7.32 m Ω as follows:(45)PCi_Cop=2RDCINa0_RMS2+INa1_RMS2=2.75W.Figure8 illustrates the distribution of loss in the proposed converter. As can be seen, the largest share of the proposed converter losses is for the diode loss. As mentioned earlier, in this part, the major share of loss generation is related to the conduction loss of the diodes. After that, although the loss of the coupled inductors was calculated and expressed separately, as can be seen from Figure 8, their aggregation into two forms of the core and the copper loss also include a major share of the proposed converter losses. The lowest losses belong to the power switches, which is the sum of the switching and the conduction loss.Figure 8
Distribution of losses in the circuit components.


## 6. Dynamic Performance

The dynamic performance of the proposed converter can be analyzed using the small-signal model and the state-space averaged technique and applying Kirchhoff’s laws. Consider the following. All semiconductors are ideal. Leakage inductances are ignored. The converter is in a steady state. The ESR of inductors is ignored. The ESR of all circuit capacitors except the output capacitor is equal torc. Also, state-space equations are achieved in one switching period, regardless of the small intervals, and in the modes where S1 and S2 are in the form of [ON ON, ON OFF, OFF ON]. According to equation (51), the state variables are the current of inductors and voltage of capacitors. The arrays of matrices A, B, and C in equation (50) are given in equations (51). The vector of input and output variables is also given in equation (51). The weight coefficients for three switching states in the state matrix are as follows: (1 − d), (2d − 1), and (1 − d).(46)x˙∧it=Ax∧it+Bu∧it,y∧it=Cx∧it,(47)x∧it=i∧L1,i∧L2,v∧c1,v∧c2,v∧c3,v∧c4,v∧c5,v∧coT,(48)u∧it=v∧i,y∧it=v∧o,(49)A=00−n2d−1n+1Lm1n2d−1n+1Lm1−n2d−1n+1Lm100000n1−dn+1Lm2−n1−dn+1Lm2n1−dn+1Lm2−n1−dn+1Lm200−n2d−1rcC11−drcC10000002d−1rcC2d−1rcC2000000−n2d−1rcC31−drcC30000000d−1rcC4000000000000000000000−1RCo,⇒AROM=−n2d−1n+1Lm1+−n1−dn+1Lm200−1RCo:reduced_order_model,(50)B=1Lm11Lm2000000T,(51)C=0000000−1.The phase margin in the Bode diagram shown in Figure9 is 67.4°. Therefore, the stability of the system is guaranteed. Figure 10 shows the proposed converter control block diagram. In this system, a Type-2 PI controller is used to control the voltage. The K-factor method can be used to find the coefficients of the PI controller. This is achieved by determining the main parameters, namely, the phase margin (PM) and the crossover frequency (fc).Figure 9
Bode diagram of closed-loop control for the proposed converter.Figure 10
Control scheme for the proposed converter.The design steps of theK-factor approach are as follows:Step 1: Plot the frequency response, Bode, and plot of the open-loop transfer function. Choose the desired crossover frequency (fc), depending on the transient response requirements, and determine the phase shift and gain of the open-loop converter.Step 2: Choose the desired phase margin (PM) depending on the maximum allowable overshoot requirement.Step 3: Calculate the required phase boost and hence determine theK-value. Here, this K-value will be useful for selecting the appropriate compensator PI or PID type and so on.Step 4: Using pole-zero locations, determine the compensator parameter values.By using the above steps, the compensator design can do with the help of popular MATLAB software. If the closed-loop performance specifications are not matching with the requirements, then repeat the above steps until fulfilling the requirements by changing the crossover frequency. By using any power electronic simulator (PSIM), verify the time domain responses through simulations.In this work, the Type-2 PI controller has been used to keep overall closed-loop stability and good dynamic response of the proposed converter. The “Type-2” controller is one kind of lead-type controller with a pole at the origin. Hence, this controller provides a maximum 90° phase boost with zero steady-state errors. Even though the boost converter has a nonminimum phase problem, it exhibits a better closed-loop performance with a Type-2 controller. With proper tuning of this controller, the converter performs a faster response, with minimal overshoots and zero steady-state errors. Therefore, by considering PM = 67.4° andfc = 1000 Hz, the following coefficients are obtained: k = 1000, k1 = 1221.2, and k2 = 32323.


## 7. Comparison

Table2 compares the proposed converter with other converters that are similar in structure and topology. The characteristics that are compared include voltage gain, maximum voltage stress of power switches, maximum voltage stress of diodes, and number of circuit components in the structure, including switches, diodes, capacitors, and coupled inductors, as well as features such as soft-switching conditions and amount current ripple. Therefore, by reviewing Table 2, the advantages of the proposed structure over similar structures are revealed. In the column related to the voltage gain, it is observed that the converters proposed in previous papers, namely, [22, 24–30], have a lower voltage gain than the proposed converter. This is also true for the second column of Table 2. The proposed converter, as mentioned in the previous sections, has voltage stress of one-tenth of the output considering a unique turns ratio. Therefore, the proposed converter is superior to other converters in this characteristic. With the same numbering for the maximum voltage stress equations of the diodes in the third column, only converters [24, 31] are slightly smaller than the proposed converter. However, as mentioned in the previous sections, the voltage stress of the diodes and even the power switches in the proposed converter is still less than the output voltage. In terms of the number of circuit components, the converters of [22, 29–31] have more diodes and capacitors than the proposed converter. Also, the number of power switches of the converters [25, 26] is more than two. The converter of [26] also has 9 capacitors. In this regard, the coupled inductors are wound on three cores in the topologies of [22, 25, 27, 29], while the proposed converter has two cores. Obviously, more circuit components mean more losses. Finally, the converters of [28, 30] do not have soft-switching conditions, and of course, all converters have low current ripples. Figure 11 shows the comparison curve of the proposed converter voltage gain with other similar converters of the same class. Obviously, the proposed converter has an ultrahigh voltage gain than other converters without any extreme duty cycle or high turns ratio applied to the system, and it is quite suitable for high power and high output voltage applications. The efficiency of the topologies mentioned above is also listed in Table 2.Table 2
Comparison of the proposed converter with other similar converters.
TopologiesVoltage gain (M)Max. voltage stress (switches)Max. voltage stress (diodes)S∗D∗C∗M∗η∗ (%)Soft switching/input current ripple[22]3n21+n1+2/1−DVo/3n21+n1+22n21+n1+1Vo/3n21+n1+2287395.2Yes/low[24]2n+4/1−DVo/2n+4nVo/n+2266297.2Yes/low[25]2n+4/1−DVo/2n+4n+1Vo/n+2364396.2Yes/low[26]2n+2/1−DVo/2n+2Vo/2469297.2Yes/low[27]n+2/1−DVo/n+2Vo242397.3Yes/low[28]4n+4/1−DVo/4n+4Vo/2244294.5No/low[29]3n+1/1−DVo/3n+12nVo/3n+1287397Yes/low[30]2nk+N+1/1−DVo/2nk+N+12Vo/2nk+N+121010294No/low[31]6n+1/1−DVo/6n+12nVo/6n+1287296.1Yes/lowProposed4n+6/1−DVo/4n+62n+2Vo/4n+6266296.6Yes/lowS∗: number of power switches; D∗: number of diodes; C∗: number of capacitors; M∗: number of magnetic cores; η∗: efficiency.Figure 11
Comparison of the proposed converter in terms of voltage gain with other similar converters in Table2.


## 8. Experimental Results

To verify the desired performance of the proposed converter, a prototype of 350 W-18 V/400 V was made from which laboratory results were extracted. The main specifications of the prototype and its image are given in Table3 and Figure 12, respectively. MOSFETs with excellent switching performance and fast Schottky diodes have been used in the implementation of the prototype. The sampling time at 47 kHz is 21 microseconds. The winding turns ratio of the coupled inductors is 1 with the number of turns 35. According to the previously mentioned statement, the duty cycle is concluded for the proposed converter greater than 0.5. Thus, the duty cycle associated with the power switch gates is about 0.55. This means that step-up voltage conversion rates are achieved without imposing a high duty cycle on the proposed converter, and as a result, power losses are naturally reduced, and the efficiency increases reciprocally. Film capacitors were selected for the proposed structure circuit capacitors to offer the significant advantage of low ESR in order to eliminate the losses of these devices. The output capacitors are also electrolytic. It should be noted that, by considering a certain percentage of the voltage ripple, the capacitors have been selected to be larger than their design value due to their lower ESR. Note that since in the proposed interleaved converter both phases have the same operation, one phase can be analyzed. However, in this study, the performance of both phases has been investigated. In the following, the waveforms extracted from the tests performed on the prototype in the laboratory are analyzed, and the experimental results are examined. They are depicted in Figure 13 together. Figure 13(a) shows the driving signals. It indicates that the converter operates in CCM and the issue of reverse recovery has been reduced. Figure 13(b) shows the voltage stress of switches. They are less than the output voltage, about 40 V. This result is theoretically consistent with the mathematical operations related to the voltage stress of the power switches. This low amount of voltage stress no longer leads to the destruction of the power semiconductor and thus does not change the circuit MOSFET parameters. In addition, this stress significantly reduces the conduction losses and therefore allows the use of MOSFETs with low-voltage rates. It is also worth noting that there are small voltage spikes in the MOSFET voltage stress, which are caused by the leakage inductance of the coupled inductors, but since their magnitude is in the safety range, no damage is done to the power switches. The input voltage of 18 V and the output voltage of 400 V are shown in Figure 13(c). The high voltage gain is obtained by considering the turns ratio of 1. Therefore, using the proposed converter is possible and suitable for high power and high output voltage applications.Table 3
Main specifications of the prototype.
ParametersValue/descriptionInput voltage:Vi18 VOutput voltage:Vo400 VOutput power:Po350 WSwitching frequency:fs≅ 47 kHzCapacitors:C1, C2 … C5, Co20, 10, 2 ∗ 56μFMagnetizing and leakage inductances:Lm and Lk100μH, 2.5 μHTurns ratio:n1 : 1Diodes:D3, D4, and D5MBR40250Diodes:D1, D2, and D6MBR20150Power switches: S1 and S2IPB072N15N3GFigure 12
Image of the prototype and laboratory tests.Figure 13
Experimental results: (a) driving signals of the power switches, S1 and S2; (b) voltage stress of the power switches, S1 and S2; (c) input voltage and the output voltage, Vi and Vo; (d) voltages of diodes, D1 and D2; (e) voltages of diodes, D3 and D4; (f) voltages of diodes, D5 and D6; (g) voltages of capacitors, C1 to C3; (h) voltages of capacitors, C4 and C5. (i) currents of diodes, D1 and D2; (j) currents of diodes, D3 and D4; (k) The currents of diodes, D5 and D6; (l) primary winding currents of the coupled inductors; (m) voltage and current of power switches in ZCS conditions; (n) dynamic response for load increase; (o) dynamic response for load decrease.
(a)(b)(c)(d)(e)(f)(g)(h)(i)(j)(k)(l)(m)(n)(o)The voltage of diodes is illustrated in Figure13(d) to Figure 13(f). According to (28) and considering the turns ratio of 1, the voltage of the first, second, and sixth diodes is about 80 V with an output of 400 V. It is about 160 V for the third to fifth diodes. The resulting values are proportional to the theoretical and mathematical relationship. Figures 13(g) and 13(h) show the voltage stress of the capacitors. The obtained results are consistent with the mathematical equations of the capacitors. Assuming the unit turns ratio in equation (22) and the output voltage of 400 V, the voltage of the first to fifth capacitors is about 40 V, 80 V, 120 V, 160 V, and 160 V, respectively. With the presence of the leakage inductance associated with the coupled inductors, the alleviation of the reverse recovery problem of the diodes is achieved. This case is illustrated in Figure 13(i) to Figure 13(k). These figures show the current of the converter diodes. Figure 13(l) shows the primary winding currents of the coupled inductors, which indicate the proper sharing of current between the legs of the converter. Figure 13(m) shows the voltage and current of power switches. One of the main features of the proposed converter is the turn-on of the main switches under ZCS conditions. The dynamic response of the proposed converter with respect to the load variation and in the range of half to full load (50% to 100%) in the two modes of load increase and load decrease is shown in Figures 13(n) and 13(o), respectively. Considering both of the mentioned figures, it is clear that the dynamic response of the converter is fast, and the load regulation is performed efficiently. This means that the system is completely robust by the control model. The measured efficiency of the proposed converter based on the prototype is illustrated in Figure 14. The efficiency is measured in terms of different loads. The maximum efficiency is 96.6% at full load.Figure 14
Measured efficiency in terms of output power.


## 9. Conclusion

An ultrahigh step-up DC-DC converter with interleaved structure is presented in this paper. The proposed converter is made of a combination of coupled inductors along with the switched-capacitor cells. The advantages of the proposed converter include the low current ripple due to the interleaved structure, low conduction loss due to the lower voltage stress in the power switches, the soft-switching conditions, low converter losses and consequently high efficiency of 96.6%, alleviation of the reverse recovery problem for the diodes, desired stability and dynamic performance due to the precision closed-loop control design, the leakage energy absorption, and achieving high voltage conversion ratio without any extreme duty cycle and high turns ratio. Experimental results based on a prototype were extracted and analyzed. The results showed the effectiveness and desired performance of the proposed converter.



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*Source: 9323182-2022-05-25.xml*