# An Improved Control Strategy for a Four-Leg Grid-Forming Power Converter under Unbalanced Load Conditions

Authors: Mohammad Reza Miveh; Mohd Fadli Rahmat; Mohd Wazir Mustafa; Ali Asghar Ghadimi; Alireza Rezvani
Journal: Advances in Power Electronics
 (2016)

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## Abstract

This paper proposes an improved multiloop control strategy for a three-phase four-leg voltage source inverter (VSI) operating with highly unbalanced loads in an autonomous distribution network. The main objective is to balance the output voltages of the four-leg inverter under unbalanced load conditions. The proposed control strategy consists of a proportional-integral (PI) voltage controller and a proportional current loop in each phase. The voltage controller and the current control loop are, respectively, used to regulate the instantaneous output voltage and generate the pulse width modulation (PWM) voltage command with zero steady-state tracking error and fast transient response. A voltage decoupling feedforward path is also used to enhance the system robustness. Since the outer voltage loop operates in the synchronous reference frame, tuning and stability analysis of the PI controller is far from being straightforward. In order to cope with this challenge, the stationary reference frame equivalent of the voltage controller in the rotating frame is derived. Subsequently, a systematic design based on a frequency response approach is provided. Simulation results are also carried out using the DIgSILENT PowerFactory software to verify the effectiveness of the suggested control strategy.


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## Body

## 1. Introduction

Poor operational efficiency, gradual depletion of fossil-fuel resources, and environmental pollution are the main problems associated with traditional power systems [1–3]. These serious issues have led to a considerable attempt to generate power using renewable energy sources (RES) at the low voltage level [4, 5]. For applications in renewable energy and distributed generation (DG), there is a need to use power electronic inverters to convert DC power into a controlled AC power [6]. Conventionally, the inverters used in distribution networks behave like voltage sources when they operate independently [7]. On the other hand, they behave as current sources, when they are directly connected to the utility grid [8]. The change of operational mode from autonomous mode to grid-connected mode or vice versa may cause the change of their controllers’ scheme. The most important distinguishing feature of a voltage source inverter (VSI) is that there is no need to change its controller, when the operation mode is changed [7]. Therefore, it is commonly used in distribution networks, due to its proper capability to operate in both grid-connected and islanded modes [8]. Here, the autonomous operation of VSIs is considered. However, to achieve a stable and secure operation, a number of technical and regulatory issues have to be resolved before VSIs can become commonplace in distribution networks.Since most traditional six-switch inverters are designed for three-phase three-wire systems, their controllers are quite suitable for balanced three-phase loads. In many low voltage distribution systems, the loads can be a mixture of single-phase and three-phase ones, resulting in unbalanced voltage problems [9]. Unbalance voltage conditions can lead to adverse effects on equipment and the electric distribution system [10]. Malfunction of protection devices, power electronic converters, and adjustable speed drives are the main challenges caused by unbalanced loads in distribution networks [9, 10]. To cope with this challenge, a neutral line is needed to provide a current path for unbalanced loads in a three-phase four-wire system. Hence, it is important to use a proper inverter topology to balance the output voltages of critical loads.So far, various VSI topologies are introduced for proper operation in a three-phase four-wire distribution network. The use of a three-leg inverter topology in three-phase four-wire systems with a costly and bulky Δ-Y transformer is popular due to trapping zero sequence currents in the Δ winding. In this topology, the control of the inverter is only responsible for compensating the voltage drops caused by positive and negative sequence currents on the output filter of the inverter in the Δ side of the transformer. Nonetheless, the zero sequence currents may cause voltage drops in the Y-side of the transformer that the three-leg inverter cannot handle this challenge [11]. The three-leg inverter with a split DC-link capacitor has also been extensively used in the literature because of its simple structure [12, 13]. However, it needs an expensive and a large capacitor to achieve equal voltage sharing between the split capacitors. Moreover, capacitor voltage balancing is another challenge with this topology [14]. The three-phase four-leg VSI plays an important role in the proper operation of three-phase four-wire distribution networks because of its superior performance characteristics in handling unbalanced conditions. The provision of the fourth leg in four-leg VSIs can result in controlling the phase voltages independently. Indeed, the independently controlled phase voltages allow four-leg inverters to provide balanced output voltages even under unbalance load conditions.To date, various control methods have been proposed in the literature to balance the output voltage of a three-phase four-leg VSI in autonomous mode. The proportional-resonant (PR) controller in the stationary reference frame has been commonly used for balancing the output voltage of the four-leg inverter due to its superior performance in eliminating the steady-state error, while regulating sinusoidal signals [17]. However, it is sensitive to frequency variations and the phase shift of current sensors. The proportional-integral (PI) controller in the dq frame is also widely used and works well with pure DC signals [15, 16, 18, 19]. This approach operates based on the extraction of the symmetrical components of the unbalanced signals in the dq frame. Nonetheless, the use of filters to obtain the symmetrical components of the unbalanced signals leads to low crossover frequency, which may cause a slow dynamic response. In another approach, a combination of the dq frame and the stationary reference frame is utilized to compensate distorting effects of nonlinear and unbalanced loads in a stand-alone distribution system [20]. The integral controllers in the dq frame are responsible for compensating the positive and negative sequence distortions, while a zero-damping bandpass filter is employed in the stationary reference frame to compensate the zero sequence distortion. However, the effectiveness of the proposed scheme is only presented for the steady-state condition, and the zero steady-state error for the zero sequence component is not truly achieved.In this paper, an improved per-phase control scheme for a three-phase four-leg VSI operating with highly unbalanced loads in an autonomous distribution network is presented. The main objective is to effectively balance the output voltages of the four-leg inverter under extremely unbalanced load conditions. The proposed control strategy consists of an outer voltage loop and an inner current loop in each phase. The outer voltage controller and the inner capacitor loop are, respectively, utilized to regulate the instantaneous output voltage and currents. A voltage decoupling feedforward is also used to improve the system robustness. The main advantages of the method are the simplicity, low steady-state voltage tracking error, and fast transient response.The rest of this paper is organized as follows. Section2 describes the model of the four-leg inverter. Section 3 presents the proposed per-phase multiloop control of the four-leg inverter in the dq frame. The stationary reference frame equivalent model of the PI controller in the dq synchronous reference frame is derived in Section 4. The design of the current loop and the voltage control are presented in Sections 5 and 6, respectively. The carrier-based pulse width modulation (PWM) method for the generation of the inverter output voltages is also explained in Section 7. Simulation results are provided in Section 8. Finally, the conclusion gives a brief summary and critique of the findings.


## 2. System Modeling

Figure1 shows the power stage of a four-leg grid-forming inverter and its LC output filter connected to unbalanced loads in an autonomous three-phase four-wire distribution network [21]. Since the LC filter yields better performance than the L filter and is less complicated than the LCL filter, the LC filter represents a suitable compromise for the system intended for use in this paper. The LC filter parameters are chosen such that the unwanted components in the four-leg inverter output voltage are attenuated effectively and the inverter current ripple is reduced admissibly using the method presented in [17]. The loads can be placed either in line-to-line or line-to-neutral connection. It is worth noting that the neutral line of the autonomous four-wire system is provided by connecting the fourth legs of the four-leg inverter to the neutral point of loads. The additional leg regulates the load zero sequence voltage [22]. To minimize the switching frequency ripple imposed on the neutral current inverter (In), a neutral inductor (Ln) is also used.Figure 1
Power stage of a three-phase four-leg VSI.The carrier-based pulse width modulation (PWM) technique is selected to produce three output voltages independently because of its simplicity and ease of implementation [23]. Since the four-leg inverter is assumed to be powered by an ideal constant DC voltage source, no controller is needed to regulate the DC-link voltage, and it is possible to consider that the DC-link voltage is constant throughout this study [5]. Table 1 presents the parameters of the four-leg VSI.Table 1
System parameters.
Parameter Description Value f s Switching frequency 5 kHz w f Fundamental frequency 2 π 60 rad/s L f and Ln Filter inductance 0.1 mH C f Filter capacitance 300μF R f and Rn Resistor of the filter inductance 10 mΩ V d c DC-link voltage 300 VTo describe the behavior of the circuit depicted in Figure1, the following quantities for voltages and currents can be defined:(1)Vpwm=VAfVBfVCfT,where Vpwm is the vector of three-phase inverter output line-to-neutral PWM voltages.(2)Iinv=IlAIlBIlCT,Iload=Iload-AIload-BIload-CT,Vload=VAVBVCT.By applying Kirchhoff voltage and current laws to the power stage of the three-phase four-leg VSI, the following equations can be obtained [21]. (3)Vload=RfIinv+LfdIinvdt+Vpwm-RnIn-LndIndt.Iinv=Iload+CfdVloaddt.The control system tuning and stability analysis of the four-leg inverter can be performed on a per-phase basis [7]. Hence, the power stage of the four-leg inverter is modeled according to the principles of the per-phase basis so that only a single-phase representation of the inverter is used for the analysis and design [9]. Figure 2 illustrates the per-phase representation of the four-leg inverter for one phase to neutral connection [2, 9]. As can be seen, the fundamental component of the switched voltage of each phase and the connected load to that phase are modeled as an ideal controlled voltage source (uVdc, which u is the control variable) and a current source (Io), respectively. In this figure, IL and Vc are also the respective phase inductor current and capacitor voltage, respectively.Figure 2
Basic per-phase representation of the four-leg inverter in each phase.For implementation of a single-phase system in the synchronous reference frame, it is necessary to generate a pseudo-two-phase system [2]. In this two-phase system, one component is obtained from the original single-phase system (α) and an orthogonal signal (β) must be created from the original single-phase signal. Based on Figure 2, the differential equations representing the model of the single-phase system in the αβ frame can be written as(4)Ldil,αβdt=uVdc,αβ-vc,αβ-Ril,αβ,Cdvc,αβdt=il,αβ-io,αβ.The average switching model of the four-leg VSI in each phase is depicted in Figure 3. This is obtained by assuming that the switching frequency is much higher than the fundamental frequency. As can be seen from Figure 3, m~ (the function of modulating signal) is used instead of the control variable, which represents the average value of u over one cycle of switching frequency.Figure 3
Average switching model of the four-leg VSI in each phase.


## 3. Per-Phase Control Scheme

The independently controlled phase voltages allow the four-leg inverter to provide balanced output voltages under highly unbalanced load conditions. The per-phase control scheme is used in this paper due to its superior performance in providing balanced output voltages under extremely unbalanced load conditions. In this control scheme, three legs are switched independently from each other so that voltages can be regulated in their output filter capacitors. The fourth leg of the inverter provides a zero voltage at the neutral point of the inverter using the proposed controller and carrier-based PWM technique [23].The implementation of the independent control of the single-phase system in thedq frame needs to create a secondary orthogonal signal from each original phase signal through a complex orthogonal signal generation (OSG) technique [5]. Several attempts have been made in the literature to generate an orthogonal signal from an original single-phase signal such as second-order generalized integrator, Kalman filter, and first-order all-pass filter (APF) methods [24–27]. In this paper, the orthogonal signal is generated based on the reference values of the d- and q-axes [28, 29]. The proposed method exhibits improved steady-state and dynamic performances in comparison with the inverters equipped with the conventional orthogonal signal generation techniques.The structure of the suggested control scheme for phase “A” is presented in Figure 4. The control system consists of an inner current loop and an outer voltage loop in each phase. The main function of the external voltage loop is to control the instantaneous output voltages within the standard limits. The inner current loop is also adopted to generate the switching states of the PWM modulator. In addition, it improves the transient and steady-state performances of the proposed control scheme. A voltage decoupling feedforward (v∗) is also used to enhance the control system robustness [2]. It is noteworthy that the capacitor current is employed as the feedback signal in the inner loop due to its superior performance in rejecting disturbances rather than the inductor current. Furthermore, the use of the capacitor current is much easier and more cost-effective than the inductor current. According to the basic principles of control theory of cascaded control, these loops can be designed independently as long as the dynamics of the voltage loop is designed to be slower than the internal current controller [2].Figure 4
Per-phase cascaded controller for the four-leg inverter in phase “A.”The voltage loop operates in the synchronous reference frame, whereas the inner current loop functions in the stationary coordinate system. In the outer loop,VcA is the A-phase output voltage of the filter capacitor to the neutral line. Vα and Vβ are the real and the orthogonal components of VcA in the stationary reference frame, respectively. The dq components of the A-phase output voltage of the filter capacitor can be generated by applying the Park transformation, after creating the pseudo-two-phase system. A simple phase locked loop (PLL) is used to obtain the sin⁡θ and cos⁡θ terms [30]. The PI controllers are utilized in the voltage loop to regulate the instantaneous output voltages in the dq frame. The reference voltages for the three phases have equal amplitudes but are separated from the other voltages by a phase angle of 120°. The q-component of the reference voltages in each phase (Vq∗) is set at 0, whereas the d-component (Vd∗) is set at the peak value of the reference phase voltage.The reference signal of the internal current loop is provided by employing the inverse Park transformation to the output signals of the output voltage controller. As shown in Figure4, only the α-axis quantity generated by the outer voltage loop is fed to the internal current controller for compensation. It is the real signal of the two-phase system. Afterwards, the inner loop generates the switching states of the PWM using a simple proportional controller. The design approach of the proposed control strategy is discussed in detail in the following sections.


## 4. Stationary Reference Frame Representation of the PI Controller in thedq Frame

In the proposed control strategy, the PI controller regulates the instantaneous output voltages of the inverter in the synchronous reference frame, whereas the simple proportional controller regulates the current in the stationary reference frame. Hence, the stability analysis and design of the whole closed-loop system is not straightforward. To successfully cope with this challenge, the stationary frame equivalent model of the PI controller is derived in this section [26, 27]. The equivalent model of the used PI controller in the stationary reference frame is depicted in Figure 5. In this block, ic,αβ∗ stands for outputs, whereas Eαβ stands for inputs. The GP is the transfer function of the proportional gain (KP), and GIis the transfer function of the integral controller (KI).Figure 5
Equivalent control block.The equivalent model of the PI controller depicted in Figure5 can be considered as a two-input-two-output system. It can be explained in the time domain as(5)ic,α∗tic,β∗t=cos⁡wft-sin⁡wftsin⁡wftcos⁡wftGPIt00GPIt∗cos⁡wftsin⁡wft-sin⁡wftcos⁡wftEαtEβt,where ∗ is the convolution operator.The Laplace transformation is used for both sides of (5). After some mathematical manipulation it can be written as(6)ic,α∗sic,β∗s=12GPIs+jwf+GPIs-jwf-jGPIs+jwf+jGPIs-jwf+jGPIs+jwf-jGPIs-jwfGPIs+jwf+GPIs-jwfEαsEβs.In (6), GPI can be replaced by KP+KI/s. After performing some mathematical manipulation this yields(7)ic,α∗sic,β∗s=KP+KIss2+wf2-KIwfs2+wf2KIwfs2+wf2KP+KIss2+wf2EαsEβs.Lastly, the transfer function of the real reference current ic,α∗ to the real voltage error Eα by replacing Eβs=((wf-s)/(wf+s))Eα(s) can be obtained as(8)ic,α∗s=a3s3+a2s2+a1s+a0s3+wfs2+wf2s+wf3Eαs=HsEαs,where a3=KP, a2=KPwf+KI, a1=KPwf2+2wfKI, and a0=KPwf3-KIwf2.H ( s ) is the stationary reference frame representation of the PI controller in the dq frame. Figure 6 shows the Bode plot of transfer function H(s) for a typical controller in wf=2π60 rad/s. From this figure, it can be concluded that for fundamental frequency, the phase and amplitude characteristics of the PI controller in the dq frame are equivalent to the PR controller in the stationary reference frame. The use of this technique considerably simplifies the stability analysis and control parameter design.Figure 6
Bode plot of transfer functionH(s) for KP=0.1 and KI=10.


## 5. Design of the Current Controller

The block diagram of the inner current loop is presented in Figure7. A simple proportional controller is used for injecting clean current to the PWM [28, 29]. In spite of the complex structure of the PI compensator, the proportional controller provides more simplicity for the stability analysis and control parameter design. Moreover, it can prevent unwanted phase delays from the reference signal [5]. However, the use of the proportional controller in the internal loop requires a high proportional gain to eliminate the steady-state error. To successfully overcome this challenge, a feedforward path is adopted to simultaneously improve the performance of the inner loop and reduce the required control effort.Figure 7
Block diagram of inner current control loop.Since it can be assumed thatZ is the load impedance and io=v/Z, the closed-loop transfer function of the inner loop can be written as(9)Gs=icic∗=CZKsLCZs2+CZr+K+Ls+r+Z.It is obvious that the performance of the internal controller significantly depends on the load impedance and controller parameters. The Bode plot of the corresponding transfer function with a typical value for the proportional compensator in different loading conditions is shown in Figure 8.Figure 8
Bode plots ofG(s) for K=1, under (solid line) nominal load, (dashed line) one-fifth of nominal load, and (dotted line) one-tenth of nominal load.It can be seen that the minimum bandwidth can be achieved at the nominal load. Hence, the proportional gain of the current controller must be tuned under nominal loading conditions to ensure the expected bandwidth in the inner loop. The proportional gain value of the current loop can be calculated usingG(jwbi)2=1/2 and assuming that wbi is the required bandwidth of the inner loop. Hence, the proportional gain can be obtained as(10)K=L+rCZ+2rCZrCZ+L+L22+C2Z2wbi2CZ.Basically, the required bandwidth must be selected lower than the switching frequency to put a limit on the inner loop response to the switching noise. Hence, it is chosen as one-fourth of the switching frequency. From (10) and with wbi=2π(0.25×(fs=5kHz))kHz≅8krad/s, the proportional gain of the inner current loop is set on 1.


## 6. Design of the Voltage Controller

The next step after determining the gain of the inner loop is to design the outer voltage loop. The block diagram of the cascaded controller and its simplified block diagram are illustrated in Figure9. In this figure, the internal controller and the external loop are, respectively, replaced by Gs and Hs. Moreover, v∗=vα∗=vd∗cos⁡wft-vq∗sin⁡wft is the voltage decoupling feedforward to enhance the system robustness. The Bode plots of the open-loop transfer function of the simplified block diagram for K=1, KP=0.1, and KI=0 under different loading conditions are depicted in Figure 10. The effect of various loading conditions on the outer loop performance can be investigated from this figure. It can be observed that the stability of the closed-loop system and the phase margin under light-load or no-load conditions are moderately decreased.Figure 9
(a) Block diagram of the suggested control scheme. (b) Its simplified representation.
(a) (b)Figure 10
Bode plots ofH(s)G(s)/Cs, for K=1, KP=0.1, and KI=0, under (solid line) nominal load, (dashed line) one-fifth of nominal load, and (dotted line) one-tenth of nominal load.To guarantee the proper performance of the inverter in all load conditions, the PI regulator is designed under light-load conditions. Since, under light-load conditions, the load impedance tends to infinity (Z→∞), the transfer function of (9) can be approximated as(11)icic∗≅KLs+r+K.Additionally, by assuming that the inverter operates under the light-load condition, the open-loop and closed-loop transfer functions of the control system can be written as (12) and (13), respectively:(12)vv∗-v=Ka3s3+a2s2+a1s+a0LCs5+bs4+bwfs3+bwf2s2+r+KCwf3s.(13)vv∗=Ka3s3+a2s2+a1s+a0LCs5+bs4+bwf+Ka3s3+bwf2+Ka2s2+r+KCwf3+Ka1s+Ka0.In the PI controller, the proportional gain and the integral parameter should be accurately selected to ensure a fast transient response and zero tracking steady-state error. The selection of the proportional gain is a compromise between the stability of the controller and the desired voltage regulation bandwidth. In this study, the proportional gain is chosen so that the required bandwidth (wbv) can be achieved for (13). On the other hand, the integral gain is chosen so that the minimum steady-state error for the outer loop can be ensured. In this case, the selection of the proportional parameter is performed based on this assumption that the dynamic of the voltage loop is unaffected by the integral gain. In other words, the proportional gain is responsible for the transient response, whereas the steady-state response is determined by the integral parameter at the fundamental frequency. Hence, it can be assumed that KI=0, during tuning the proportional parameter. Based on this assumption, the transfer function of the closed-loop system in the frequency domain and under light-load condition can be rewritten as(14)vv∗=KPKKPK-LCw2+jr+KCw.Assuming that the expected bandwidth is wbv, KP can be obtained as(15)KP=Cwbv2L2wbv2+K2-LwbvK.In practice, in order to achieve a satisfactory tradeoff between the disturbance rejection and the proper transient response in inverter applications, the system bandwidth must be selected between ten times of the fundamental frequency and one-tenth of the switching frequency. In this study, it is chosen as 550 Hz, which is a value between 600 Hz and 500 Hz. Consequently, the system bandwidth and the proportional gain can be determined as wbv=2π×550 Hz ≃ 3 krad/s and 0.15, respectively. The next step is to determine the integrator gain of the PI controller. The stability analysis is used to achieve an accurate value for integral parameter. The use of the Routh-Hurwitz criterion can be satisfied by the integrator objectives in the voltage loop. The system characteristic polynomial can be written as(16)LCs5+bs4+bwf+Ka3s3+bwf2+Ka2s2+r+KCwf3+Ka1s+Ka0=0.By applying the Routh-Hurwitz criterion, the system stability analysis can discriminate as (17)K>0,KP>0,KI<KP×wf.The proportional gain of the PI controller has been already determined. Therefore, the value of KP×wf can be calculated equal to 55. To evaluate the performance of the system stability, the open-loop Bode plots of H(s)G(s)/Cs for different values of KI are depicted in Figure 11. What is interesting in this figure is that KI has no effect on the phase margin. It is noteworthy that an infinitive magnitude at the fundamental frequency provides a zero steady-state error. However, it has a considerable influence on the operation of the controller in the area near the fundamental frequency. Additionally, based on the stationary reference frame equivalent of the integral term in Figure 6, which affects the system performance in vicinity of the fundamental frequency, the integral gain should be minimized to ensure that the integral term does not affect other frequencies. Indeed, this gain should be selected enough lower than the stability criterion in applications where variations of the fundamental frequency are expected, which may happen in the case of autonomous grids. Hence, the choice of KI should be done based on a tradeoff between eliminating the steady-state error and not affecting other frequencies. Based on this compromise and the Routh-Hurwitz criterion, KI is chosen to be 42.Figure 11
Open-loop Bode plots ofH(s)G(s)/Cs, for K=1, KP=0.15, and KI=10 (solid line), for K=1, KP=0.15, and KI=20 (dashed line).


## 7. The Carrier-Based PWM Method for the Generation of the Inverter Output Voltage

Kim and Sul [23] propose a voltage modulation technique on the basis of a triangular carrier wave for three-phase four-leg VSIs to make three lines to neutral output voltages using an additional leg. In this modulation method, the concept of offset voltage is implemented using a single carrier. The method has a strong performance and can be implemented easily. Therefore, it is used in this study to generate the inverter output voltage.The block diagram of the used PWM scheme is shown in Figure12. In this figure, VAf,VBf,VCf are the “α” component generated by the proposed cascaded controller. N stands for the fictive midpoint of the DC link, and VfN is the offset voltage, which is calculated quite different from three-phase three-leg VSI using (18). The output voltages of the four-leg inverter (VAN,VBN,VCN) and pertaining constraint can be obtained by (19) and (20). Moreover, the ON-times of the upper switch of respective legs can be obtained as (21):(18)VfN=mid-Vmax2,-Vmin2,-Vmax+Vmin2.(19)VAN=VAf+VfN,VBN=VBf+VfN,VCN=VCf+VfN,(20)-Vdc≤VAf,VBf,VCf≤Vdc,(21)TA=Ts2+VANVdcTs,TB=Ts2+VBNVdcTs,TC=Ts2+VCNVdcTs,TF=Ts2+VfNVdcTs,where Ts is the period of the triangular carrier.Figure 12
Block diagram of the used PWM scheme for the four-leg inverter.


## 8. Simulation Results

To validate the performance of the proposed control strategy, the test system of Figure1 has been simulated in the DIgSILENT PowerFactory software. The four-leg VSI is equipped with the suggested control scheme. The types of loads are resistive, and other parameters of the system are presented in Table 2. Different simulation case studies under various load scenarios are carried out to determinate the effectiveness of both the steady-state and the transient performances of the suggested control scheme.Table 2
System parameters for the simulation study.
Load voltage 155.56 V/phase (peak)  Frequency 60 Hz  Current controller parameter K = 1  PI voltage controller parameters K P = 0.15, KI=42  Balanced load R A = R B = R C = 8 Ω  Unbalanced loads (1)RA = 10 Ω, RB = 7 Ω, RC = 8 Ω (2)RA = RB = 8 Ω, RC = ∞ (3)RB = 8 Ω, RA = RC = ∞


### 8.1. Steady-State Performance

The evaluation of the steady-state behavior of the proposed control strategy is made for a three-phase balanced load (RA=RB=RC=8 Ω) and three various unbalanced load cases, including (RA=10 Ω, RB=7 Ω, RC=8 Ω), (RA=RB=8 Ω, RC=∞), and (RB=8 Ω, RA=RC=∞).


#### 8.1.1. With a Three-Phase Balanced Load

The purpose of this part is to investigate the steady-state performance of the suggested controller strategy when a three-phase balanced load is connected to the four-leg VSI. The balanced load includes a resistor of 8 Ω for each phase. The three-phase pole voltage references(VAN,VBN,VCN) and the offset voltage reference (VfN) are shown in Figure 13. It can be seen from this figure that the three-phase four-leg VSI has the considerable ability to provide desired pole voltage references with the expected amplitude for the three-phase balanced load.Figure 13
Three-phase pole voltage references and the offset voltage reference.The output waveforms of load voltages, load currents, and neutral current for the four-leg VSI for the balanced load are also depicted in Figure14. The results indicate that the proposed control strategy is capable of regulating the fundamental component of the load voltage close to the desired peak for the balanced load.Figure 14
Steady-state load voltages, load currents, and neutral current for the balanced load.


#### 8.1.2. With Single-Phase and Three-Phase Unbalanced Loads

In this part, the steady-state performance of the proposed control strategy for various unbalanced load cases, including (RA=10 Ω, RB=7 Ω, RC=8 Ω), (RA=RB=8 Ω, RC=∞), and (RB=8 Ω, RA=RC=∞) are investigated. The simulation results of load voltages and currents for these different unbalanced load scenarios are depicted in Figures 15–17. Since the control structure adopts separate controller for each phase, the unbalanced loads have no influence on the voltage controller performance, and the load voltages remain balanced. From these figures, it is apparent that the proposed control technique has a significant ability to provide balanced output voltages for the four-leg VSI even under extremely unbalanced load condition containing a single-phase load between the phase and neutral.Figure 15
Steady-state load voltages and currents for the unbalanced load (RA=10 Ω, RB=7 Ω, and RC=8 Ω).Figure 16
Steady-state load voltages and currents for the unbalanced load(RA=RB=8 Ω, and RC=∞).Figure 17
Steady-state load voltages and currents for the unbalanced load(RB=8 Ω, RA=RC=∞).According to the IEEE standards, the voltage imbalance needs to be maintained low, below 2% for sensitive loads [30, 31]. The performance of the suggested multiloop control strategy has been compared with the conventional control scheme [15, 16], with the same specification for the inner and outer control loops. In order to evaluate the value of phase voltage unbalance rate (PVUR), the magnitudes of the fundamental components of the three-phase voltages and the PVUR of all tested scenarios for both the conventional and the suggested control schemes are presented in Table 3. The results show that the load voltages can remain balanced in steady-state for both the conventional and the proposed control scheme at all tested conditions. Moreover, the value of the PVUR is maintained below 2% at all tested conditions for both control strategies. However, the steady-state performance of the suggested per-phase control scheme is improved because of avoiding the use of slow filter-based symmetrical components calculators.Table 3
Comparison of two control strategies in steady-state.
Load type Conventional control scheme Proposed control strategy Load peak voltages (V) PVUR (%) Load peak voltages (V) PVUR (%) PhaseA PhaseB PhaseC PhaseA PhaseB PhaseC Balanced 155.32 155.55 155.54 0.096 155.50 155.54 155.56 0.021 Unb. 1 155.25 155.52 155.58 0.128 155.38 155.49 155.56 0.062 Unb. 2 155.15 155.56 155.6 0.184 155.23 155.52 155.75 0.173 Unb. 3 155.55 155.65 155.15 0.192 155.79 155.25 155.45 0.188


### 8.2. Transient Performance

In this part, the evaluation of the transient behavior of the proposed control strategy is made for a three-phase unbalanced load (RA=10 Ω, RB=7 Ω, and RC=8 Ω). To verify the transient performance of the proposed voltage control strategy a step change in the d-components of voltage references (Vdref) in all phases of the four-leg inverter is applied and then returns to its initial voltage value (while keeping Vqref=0).For theA-phase a step change from 155.56 to 75 V (peak) at 26 ms is applied and then returns to its initial voltage value at 79 ms. The transient behaviors of the voltage reference (VA,dref) and the actual voltage (VA,d) of the respective phase are shown in Figure 18. The d-reference voltage (peak) value in phase “B” (VB,dref) is step changed from 155.56 to 140 V (peak) at 39 ms, afterwards back to 155.56 V at 79 ms. Figure 19 also depicts the transient response of the voltage (VB,dref) reference and the actual voltage (VB,d) of the b-phase.Figure 18
Transient response of the PI controller to step changes in phase “A.”Figure 19
Transient response of the PI controller to step changes in phase “B.”For theC-phase also a step change from 155.56 to 135 V (peak) at 46 ms is applied and then returns to its initial voltage value at 79 ms. Figure 20 illustrates the waveforms of the voltage (VC,dref) reference and actual voltage (VC,d) of the pertaining phase. As can be seen, the voltage controllers in each phase demonstrate very fast dynamic, and the actual voltages are capable of following closely their references. The PI controllers take about 1 cycle to track reference voltage in each phase. It is apparent that the proposed controller can change the load voltages close to their references with very fast dynamic.Figure 20
Transient response of the PI controller to step changes in phase “C.”


#### 8.2.1. Comparison between the Conventional and the Proposed Control Scheme

In this part, the transient performance of the proposed control strategy has been compared with the conventional control scheme [15, 16], with the same specification for the voltage and current controller. In this simulation, while the three-phase four-leg grid-forming unit is initially supplying a balanced load (8 Ω/ph), a single-phase inductive load (R = 20 Ω and L = 2 mH) is added between phases “A” and “C” at 0.3 s. After 0.2 s, the connected load between phase “C” and neutral is changed from the nominal load to pure resistance of 5.7 Ω. Lastly, the nominal load between phase “A” and neutral is disconnected at 0.7 s.The output waveforms of load voltages under varying unbalanced load conditions are depicted in Figure21, for both the conventional and the suggested control schemes. As can be seen, both control strategies can keep the load voltages balanced in steady-state under varying unbalanced load conditions. To compare the speed of response of two control schemes, the transient load voltages for both control strategies are provided with zoomed Figures. It can be seen that the load voltage waveforms are unaffected by the load transients in the proposed scheme. Comparing the two results, it can be seen that no significant changes in the load voltages can be observed with the proposed scheme. While there exist at least three line cycles transient with the conventional approach, the results show that the suggested controller has a significant ability to balance the output voltages under severe unbalanced load conditions with zero steady-state error and fast dynamic response.Figure 21
Waveforms of output voltages of the four-leg inverter for different load condition. (a) Proposed control scheme. (b) Conventional scheme [15, 16].
(a) (b)


## 8.1. Steady-State Performance

The evaluation of the steady-state behavior of the proposed control strategy is made for a three-phase balanced load (RA=RB=RC=8 Ω) and three various unbalanced load cases, including (RA=10 Ω, RB=7 Ω, RC=8 Ω), (RA=RB=8 Ω, RC=∞), and (RB=8 Ω, RA=RC=∞).


### 8.1.1. With a Three-Phase Balanced Load

The purpose of this part is to investigate the steady-state performance of the suggested controller strategy when a three-phase balanced load is connected to the four-leg VSI. The balanced load includes a resistor of 8 Ω for each phase. The three-phase pole voltage references(VAN,VBN,VCN) and the offset voltage reference (VfN) are shown in Figure 13. It can be seen from this figure that the three-phase four-leg VSI has the considerable ability to provide desired pole voltage references with the expected amplitude for the three-phase balanced load.Figure 13
Three-phase pole voltage references and the offset voltage reference.The output waveforms of load voltages, load currents, and neutral current for the four-leg VSI for the balanced load are also depicted in Figure14. The results indicate that the proposed control strategy is capable of regulating the fundamental component of the load voltage close to the desired peak for the balanced load.Figure 14
Steady-state load voltages, load currents, and neutral current for the balanced load.


### 8.1.2. With Single-Phase and Three-Phase Unbalanced Loads

In this part, the steady-state performance of the proposed control strategy for various unbalanced load cases, including (RA=10 Ω, RB=7 Ω, RC=8 Ω), (RA=RB=8 Ω, RC=∞), and (RB=8 Ω, RA=RC=∞) are investigated. The simulation results of load voltages and currents for these different unbalanced load scenarios are depicted in Figures 15–17. Since the control structure adopts separate controller for each phase, the unbalanced loads have no influence on the voltage controller performance, and the load voltages remain balanced. From these figures, it is apparent that the proposed control technique has a significant ability to provide balanced output voltages for the four-leg VSI even under extremely unbalanced load condition containing a single-phase load between the phase and neutral.Figure 15
Steady-state load voltages and currents for the unbalanced load (RA=10 Ω, RB=7 Ω, and RC=8 Ω).Figure 16
Steady-state load voltages and currents for the unbalanced load(RA=RB=8 Ω, and RC=∞).Figure 17
Steady-state load voltages and currents for the unbalanced load(RB=8 Ω, RA=RC=∞).According to the IEEE standards, the voltage imbalance needs to be maintained low, below 2% for sensitive loads [30, 31]. The performance of the suggested multiloop control strategy has been compared with the conventional control scheme [15, 16], with the same specification for the inner and outer control loops. In order to evaluate the value of phase voltage unbalance rate (PVUR), the magnitudes of the fundamental components of the three-phase voltages and the PVUR of all tested scenarios for both the conventional and the suggested control schemes are presented in Table 3. The results show that the load voltages can remain balanced in steady-state for both the conventional and the proposed control scheme at all tested conditions. Moreover, the value of the PVUR is maintained below 2% at all tested conditions for both control strategies. However, the steady-state performance of the suggested per-phase control scheme is improved because of avoiding the use of slow filter-based symmetrical components calculators.Table 3
Comparison of two control strategies in steady-state.
Load type Conventional control scheme Proposed control strategy Load peak voltages (V) PVUR (%) Load peak voltages (V) PVUR (%) PhaseA PhaseB PhaseC PhaseA PhaseB PhaseC Balanced 155.32 155.55 155.54 0.096 155.50 155.54 155.56 0.021 Unb. 1 155.25 155.52 155.58 0.128 155.38 155.49 155.56 0.062 Unb. 2 155.15 155.56 155.6 0.184 155.23 155.52 155.75 0.173 Unb. 3 155.55 155.65 155.15 0.192 155.79 155.25 155.45 0.188


## 8.1.1. With a Three-Phase Balanced Load

The purpose of this part is to investigate the steady-state performance of the suggested controller strategy when a three-phase balanced load is connected to the four-leg VSI. The balanced load includes a resistor of 8 Ω for each phase. The three-phase pole voltage references(VAN,VBN,VCN) and the offset voltage reference (VfN) are shown in Figure 13. It can be seen from this figure that the three-phase four-leg VSI has the considerable ability to provide desired pole voltage references with the expected amplitude for the three-phase balanced load.Figure 13
Three-phase pole voltage references and the offset voltage reference.The output waveforms of load voltages, load currents, and neutral current for the four-leg VSI for the balanced load are also depicted in Figure14. The results indicate that the proposed control strategy is capable of regulating the fundamental component of the load voltage close to the desired peak for the balanced load.Figure 14
Steady-state load voltages, load currents, and neutral current for the balanced load.


## 8.1.2. With Single-Phase and Three-Phase Unbalanced Loads

In this part, the steady-state performance of the proposed control strategy for various unbalanced load cases, including (RA=10 Ω, RB=7 Ω, RC=8 Ω), (RA=RB=8 Ω, RC=∞), and (RB=8 Ω, RA=RC=∞) are investigated. The simulation results of load voltages and currents for these different unbalanced load scenarios are depicted in Figures 15–17. Since the control structure adopts separate controller for each phase, the unbalanced loads have no influence on the voltage controller performance, and the load voltages remain balanced. From these figures, it is apparent that the proposed control technique has a significant ability to provide balanced output voltages for the four-leg VSI even under extremely unbalanced load condition containing a single-phase load between the phase and neutral.Figure 15
Steady-state load voltages and currents for the unbalanced load (RA=10 Ω, RB=7 Ω, and RC=8 Ω).Figure 16
Steady-state load voltages and currents for the unbalanced load(RA=RB=8 Ω, and RC=∞).Figure 17
Steady-state load voltages and currents for the unbalanced load(RB=8 Ω, RA=RC=∞).According to the IEEE standards, the voltage imbalance needs to be maintained low, below 2% for sensitive loads [30, 31]. The performance of the suggested multiloop control strategy has been compared with the conventional control scheme [15, 16], with the same specification for the inner and outer control loops. In order to evaluate the value of phase voltage unbalance rate (PVUR), the magnitudes of the fundamental components of the three-phase voltages and the PVUR of all tested scenarios for both the conventional and the suggested control schemes are presented in Table 3. The results show that the load voltages can remain balanced in steady-state for both the conventional and the proposed control scheme at all tested conditions. Moreover, the value of the PVUR is maintained below 2% at all tested conditions for both control strategies. However, the steady-state performance of the suggested per-phase control scheme is improved because of avoiding the use of slow filter-based symmetrical components calculators.Table 3
Comparison of two control strategies in steady-state.
Load type Conventional control scheme Proposed control strategy Load peak voltages (V) PVUR (%) Load peak voltages (V) PVUR (%) PhaseA PhaseB PhaseC PhaseA PhaseB PhaseC Balanced 155.32 155.55 155.54 0.096 155.50 155.54 155.56 0.021 Unb. 1 155.25 155.52 155.58 0.128 155.38 155.49 155.56 0.062 Unb. 2 155.15 155.56 155.6 0.184 155.23 155.52 155.75 0.173 Unb. 3 155.55 155.65 155.15 0.192 155.79 155.25 155.45 0.188


## 8.2. Transient Performance

In this part, the evaluation of the transient behavior of the proposed control strategy is made for a three-phase unbalanced load (RA=10 Ω, RB=7 Ω, and RC=8 Ω). To verify the transient performance of the proposed voltage control strategy a step change in the d-components of voltage references (Vdref) in all phases of the four-leg inverter is applied and then returns to its initial voltage value (while keeping Vqref=0).For theA-phase a step change from 155.56 to 75 V (peak) at 26 ms is applied and then returns to its initial voltage value at 79 ms. The transient behaviors of the voltage reference (VA,dref) and the actual voltage (VA,d) of the respective phase are shown in Figure 18. The d-reference voltage (peak) value in phase “B” (VB,dref) is step changed from 155.56 to 140 V (peak) at 39 ms, afterwards back to 155.56 V at 79 ms. Figure 19 also depicts the transient response of the voltage (VB,dref) reference and the actual voltage (VB,d) of the b-phase.Figure 18
Transient response of the PI controller to step changes in phase “A.”Figure 19
Transient response of the PI controller to step changes in phase “B.”For theC-phase also a step change from 155.56 to 135 V (peak) at 46 ms is applied and then returns to its initial voltage value at 79 ms. Figure 20 illustrates the waveforms of the voltage (VC,dref) reference and actual voltage (VC,d) of the pertaining phase. As can be seen, the voltage controllers in each phase demonstrate very fast dynamic, and the actual voltages are capable of following closely their references. The PI controllers take about 1 cycle to track reference voltage in each phase. It is apparent that the proposed controller can change the load voltages close to their references with very fast dynamic.Figure 20
Transient response of the PI controller to step changes in phase “C.”


### 8.2.1. Comparison between the Conventional and the Proposed Control Scheme

In this part, the transient performance of the proposed control strategy has been compared with the conventional control scheme [15, 16], with the same specification for the voltage and current controller. In this simulation, while the three-phase four-leg grid-forming unit is initially supplying a balanced load (8 Ω/ph), a single-phase inductive load (R = 20 Ω and L = 2 mH) is added between phases “A” and “C” at 0.3 s. After 0.2 s, the connected load between phase “C” and neutral is changed from the nominal load to pure resistance of 5.7 Ω. Lastly, the nominal load between phase “A” and neutral is disconnected at 0.7 s.The output waveforms of load voltages under varying unbalanced load conditions are depicted in Figure21, for both the conventional and the suggested control schemes. As can be seen, both control strategies can keep the load voltages balanced in steady-state under varying unbalanced load conditions. To compare the speed of response of two control schemes, the transient load voltages for both control strategies are provided with zoomed Figures. It can be seen that the load voltage waveforms are unaffected by the load transients in the proposed scheme. Comparing the two results, it can be seen that no significant changes in the load voltages can be observed with the proposed scheme. While there exist at least three line cycles transient with the conventional approach, the results show that the suggested controller has a significant ability to balance the output voltages under severe unbalanced load conditions with zero steady-state error and fast dynamic response.Figure 21
Waveforms of output voltages of the four-leg inverter for different load condition. (a) Proposed control scheme. (b) Conventional scheme [15, 16].
(a) (b)


## 8.2.1. Comparison between the Conventional and the Proposed Control Scheme

In this part, the transient performance of the proposed control strategy has been compared with the conventional control scheme [15, 16], with the same specification for the voltage and current controller. In this simulation, while the three-phase four-leg grid-forming unit is initially supplying a balanced load (8 Ω/ph), a single-phase inductive load (R = 20 Ω and L = 2 mH) is added between phases “A” and “C” at 0.3 s. After 0.2 s, the connected load between phase “C” and neutral is changed from the nominal load to pure resistance of 5.7 Ω. Lastly, the nominal load between phase “A” and neutral is disconnected at 0.7 s.The output waveforms of load voltages under varying unbalanced load conditions are depicted in Figure21, for both the conventional and the suggested control schemes. As can be seen, both control strategies can keep the load voltages balanced in steady-state under varying unbalanced load conditions. To compare the speed of response of two control schemes, the transient load voltages for both control strategies are provided with zoomed Figures. It can be seen that the load voltage waveforms are unaffected by the load transients in the proposed scheme. Comparing the two results, it can be seen that no significant changes in the load voltages can be observed with the proposed scheme. While there exist at least three line cycles transient with the conventional approach, the results show that the suggested controller has a significant ability to balance the output voltages under severe unbalanced load conditions with zero steady-state error and fast dynamic response.Figure 21
Waveforms of output voltages of the four-leg inverter for different load condition. (a) Proposed control scheme. (b) Conventional scheme [15, 16].
(a) (b)


## 9. Conclusion

In this study, a new per-phase cascaded voltage-current control strategy for a three-phase four-leg VSI operating with highly unbalanced loads in an autonomous distribution network is presented. The suggested control scheme provides balanced output voltages for the four-leg inverter even under extremely unbalanced loading conditions. It consists of an outer voltage loop in each phase to regulate the instantaneous output voltages and an inner current loop in each phase to improve both the steady-state and transient behaviors of the control system. The frequency response approach is used for tuning and stability analysis. The transient and steady-state performances of the suggested control scheme are investigated using simulation studies. The simulation results show that the suggested controller has a significant ability to balance the output voltages under severe unbalanced load conditions with zero steady-state error and fast dynamic response.



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*Source: 9123747-2016-08-29.xml*