# High-Frequency and Low-Power Output Stages Based on FGMOS Flipped Voltage Follower

Authors: Maneesha Gupta; Urvashi Singh; Richa Srivastava
Journal: ISRN Electronics
 (2013)

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## Abstract

Two new high-performance output stages are proposed. These output stages are basically designed by using a flipped voltage follower (FVF). The proposed low-power and low-voltage output stages have utilized the advantages of the FGMOS technology. They are characterized by low-power dissipation, reduced power supply requirement, and larger bandwidth. By using FGMOS-based FVF in place of conventional FVF, the linearity of the output stages has been highly improved. The small-signal analysis of FGMOS-based FVF is done to show the bandwidth enhancement of conventional FVF. The circuits are simulated to demonstrate the effectiveness using SPICE, in TSMC 0.25-micron CMOS device models. The simulation results show that the power supply requirement of the proposed output stages is highly reduced and bandwidths are extremely higher than the conventional circuits.


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## Body

## 1. Introduction

The challenge of designing of high performance low-voltage and low-power analog circuits is increasing due to the scaling down of CMOS technology and the increasing demand for portable electronic equipments [1]. The speed of conventional analog integrated circuits is degrading on reducing the supply voltage for a given technology. To fulfill these requirements, the researchers are focusing on the development of new integrated circuits that have low voltage supply requirement, without any degradation in the performance.One of the basic building blocks in analog signal processing circuits is voltage buffer, which is used to drive low-impedance loads (Figure1(a)). The flipped voltage follower (FVF) [2] is a low-voltage operating buffer that can be used in different circuits in place of conventional voltage buffer very efficiently. A FVF circuit is shown in Figure 1(b).(a) Voltage follower and (b) flipped voltage follower.
(a)
(b)A FVF cell has found increasing applications in areas where a voltage buffer is required. These applications include operational amplifier, current mirror, output stages, and arithmetic circuits and act as a basic building block in various analog circuits [2–7]. The advantages of FVF include low supply voltage requirement, almost unity gain, and high current-sinking capabilities [2].Ramirez-Angulo et al. [3] have introduced an FVF which is based on FGMOS level shifter stage, shown in Figure 2. Due to its high swing and low voltage operation, the FGMOS-based FVF can be preferred over conventional FVF in many high-swing, low-power, and wideband analog integrated circuits.Figure 2
FVF using floating gate level shifter [3].Applications for communication systems require low power, low voltage, and high frequency output stages. The supply voltage and the power dissipation of output stage can be reduced by using floating gate technology. There are several attractive features of FGMOS such as it can incorporate tuneable mechanisms and work below the operational limits of supply voltage levels for a particular technology, without affecting the other characteristics of the system, and thus power dissipation is also lesser than the minimum power required for a MOS circuit of the same technology [8–13].Usually buffers require an extra circuitry to achieve large bandwidth, which often increases power consumption. In this work, the FVF with floating gate level shifter [3] is used to replace the conventional FVF in different output stages, which have been investigated by Centurelli et al. in [14]. We have achieved high bandwidth of output stages, without affecting the gain of the system, and moreover the power consumption is highly reduced.This paper is organized as follows. Section2 covers the large signal analysis and small signal analysis of conventional FVF with a floating gate level shifter. Section 3 presents the proposed output stages based on FGMOS FVF. On the basis of simulation results, the performances of designed circuits are compared in Section 4. Finally, the conclusion is given in Section 5.


## 2. FVF with Floating Gate Level Shifter

### 2.1. Large Signal Analysis

The symbolic representation of two-input floating gate transistor, whose threshold voltage can be controlled by the values of capacitors, and its equivalent circuit are shown in Figures3(a) and 3(b), respectively.(a) Schematic symbol of 2-input FGMOS transistor and (b) equivalent circuit of FGMOS transistor.
(a)
(b)The input signal (V1) and bias (V2) are applied at gate G1 and G2, respectively. The drain current (ID) of the FGMOS operating in ohmic region is given by [8, 9]
(1)ID=β[{(C1CTotalV1+C2CTotalV2+CGDCTotalVDS)C1CTotal-VT}-VDS2]VDS,
where β is the transconductance parameter, C1 and C2 are the capacitances associated with G1 and G2, CTotal=C1+C2+CGS+CGD+CGB is the total floating-gate (FG) capacitance, and VT stands for the threshold voltage. The above equation can be simplified as
(2)ID=β(C1CTotal)[(V1-VT,eff)VDS-CTotal2C1VDS2],
where effective threshold voltage (VT,eff) is given by [8]
(3)VT,eff=VT+C2C1(VT-V2).From (3), it is obvious that the reduction in VT,eff can be done by selecting V2>VT  and C2>C1. Hence, VT,eff is controllable and it depends on the values of C1 and C2. The proposed output stage circuits utilize this property of the FGMOS transistor.The control gates (G1 and G2) develop a floating gate voltageVFG as a weighted sum of inputs voltages Vi, via a capacitive voltage divider. VFG is given by [8]
(4)VFG={∑i=1N(CiCTotal)Vi+(CGSCTotal)VS+(CGDCTotal)VD+(CGBCTotal)VB+QFGCTotal∑i=1N(CiCTotal)Vi},
where  VX is the voltage at X terminal, CGS, CGD, and CGB are the parasitic capacitances, Ci is capacitance at input, terminal, CTotal is the total capacitance seen by floating gate and QFG refers to the amount of charge that has been trapped in floating gate during fabrication. Using (4) to find the floating gate voltage of FGMOS-based FVF (Figure 2) and an approximation given in [8], we obtain
(5)VFG≈(C1C1+C2)VD1+(C2C1+C2)VGND,
or
(6)VFG=(C1C1+C2)VD1.
Hence, the voltage at drain terminal of M1 is
(7)VD1=(C1+C2C1)VFG=(1+C2C1)VFG.
It is obvious from (7) thatVD1 is level shifted by (C2/C1).


### 2.2. Small Signal Analysis

The small signal model of FGMOS-based FVF is shown in Figure4. The FGMOS-based FVF is analyzed to obtain the transfer function.Figure 4
Small-signal equivalent model of FVF with floating gate level shifter.In the analysis,ro1 and ro2 are the resistances due to channel length modulation effect, Cgs1 and Cgs2 are the gate to source capacitances, and gm1 and gm2 are the transconductances of transistors M1 and M2, respectively. C1 and C2 are the capacitances associated with two different inputs of floating gate transistor M2, respectively, and Rb  is the output impedance of the current source Ib.On applying KCL at nodes (a), (b), and (c) in Figure4, the obtained equations are
(8)Vout(sCgs1+gm1+1ro1+1ro2)-Vin(gm1+sCgs1)-Vd1ro1+gm2(C1C2)Vd1=0,(9)Vd1(1Rb+1ro1+sC1)-Voro1+gm1(Vin-Vo)-sC1Vg2=0,(10)Vg2(sCT)=Vd1(sC1),
where CT=C1+C2+Cgs2.Substituting the value ofVg2 from (10) in (9), it gives
(11)Vd1(1Rb+1ro1+sC1(1-C1CT))=Vo(1+gm1ro1ro1)-gm1Vin.
And, thus,
(12)Vd1=(RbCT{Vo(1+gm1ro1)-gm1ro1Vin}CT(ro1+Rb)+sC1(CT-C1)ro1Rb).
Replacing  Vd1  by using (12) in (8), the transfer function is given by
(13)AV(s)=(ro1ro2(sCgs1+gm1)X+gm1ro1ro2Rb(gm2ro1C1-CT))×(ro1ro2(sCgs1+gm1)X+X(ro1+ro2)+gm1ro1ro2Rb(gm2ro1C1-CT)+ro2Rb(gm2ro1C1-CT))-1,
where X=CT(ro1+Rb)+sC1ro1Rb(CT-C1).Assumingro1=ro2=ro, C1=C2=C, and Cgs1=Cgs2=Cgs,   (13) transforms into
(14)AV(s)=a2s2+a1s+a0a2s2+(a1+Δa1)s+(a0+Δa0),
where
(15)a2=CgsC(Cgs+C)ro3Rb,a1=ro2{gm1roRbC(Cgs+C)+Cgs(ro+Rb)(Cgs+2C)},Δa1=2CRb(Cgs+C),a0=gm1ro3(Cgs+2C)+gm1gm2ro3RbC,Δa0={gm2ro2RbC+roRb(Cgs+2C)+2ro2(Cgs+2C)}.
By definition, at ω=ωo, |AV|2=1/2 [16], and thus
(16)12=(a0-a2ω2)2+(a1ω)2((a0+Δa0)-a2ω2)+((a1+Δa1)ω)2.
The −3 dB frequency is
(17)ω0=1a2Δa12+2a1Δa1+2a0a2-a12-2a2Δa0.
(Since the expression of the lower 3-dB frequency is too large, the symbols are used to represent it.) By placing the values of symbols, it can be easily observed that the lower 3-dB frequency of floating gate FVF is much greater than that of simple FVF [7].To enhance the speed and reduce the power supply requirement, the wideband FGMOS-based FVF is used in conventional buffers [14] and is explained in the next section.


## 2.1. Large Signal Analysis

The symbolic representation of two-input floating gate transistor, whose threshold voltage can be controlled by the values of capacitors, and its equivalent circuit are shown in Figures3(a) and 3(b), respectively.(a) Schematic symbol of 2-input FGMOS transistor and (b) equivalent circuit of FGMOS transistor.
(a)
(b)The input signal (V1) and bias (V2) are applied at gate G1 and G2, respectively. The drain current (ID) of the FGMOS operating in ohmic region is given by [8, 9]
(1)ID=β[{(C1CTotalV1+C2CTotalV2+CGDCTotalVDS)C1CTotal-VT}-VDS2]VDS,
where β is the transconductance parameter, C1 and C2 are the capacitances associated with G1 and G2, CTotal=C1+C2+CGS+CGD+CGB is the total floating-gate (FG) capacitance, and VT stands for the threshold voltage. The above equation can be simplified as
(2)ID=β(C1CTotal)[(V1-VT,eff)VDS-CTotal2C1VDS2],
where effective threshold voltage (VT,eff) is given by [8]
(3)VT,eff=VT+C2C1(VT-V2).From (3), it is obvious that the reduction in VT,eff can be done by selecting V2>VT  and C2>C1. Hence, VT,eff is controllable and it depends on the values of C1 and C2. The proposed output stage circuits utilize this property of the FGMOS transistor.The control gates (G1 and G2) develop a floating gate voltageVFG as a weighted sum of inputs voltages Vi, via a capacitive voltage divider. VFG is given by [8]
(4)VFG={∑i=1N(CiCTotal)Vi+(CGSCTotal)VS+(CGDCTotal)VD+(CGBCTotal)VB+QFGCTotal∑i=1N(CiCTotal)Vi},
where  VX is the voltage at X terminal, CGS, CGD, and CGB are the parasitic capacitances, Ci is capacitance at input, terminal, CTotal is the total capacitance seen by floating gate and QFG refers to the amount of charge that has been trapped in floating gate during fabrication. Using (4) to find the floating gate voltage of FGMOS-based FVF (Figure 2) and an approximation given in [8], we obtain
(5)VFG≈(C1C1+C2)VD1+(C2C1+C2)VGND,
or
(6)VFG=(C1C1+C2)VD1.
Hence, the voltage at drain terminal of M1 is
(7)VD1=(C1+C2C1)VFG=(1+C2C1)VFG.
It is obvious from (7) thatVD1 is level shifted by (C2/C1).


## 2.2. Small Signal Analysis

The small signal model of FGMOS-based FVF is shown in Figure4. The FGMOS-based FVF is analyzed to obtain the transfer function.Figure 4
Small-signal equivalent model of FVF with floating gate level shifter.In the analysis,ro1 and ro2 are the resistances due to channel length modulation effect, Cgs1 and Cgs2 are the gate to source capacitances, and gm1 and gm2 are the transconductances of transistors M1 and M2, respectively. C1 and C2 are the capacitances associated with two different inputs of floating gate transistor M2, respectively, and Rb  is the output impedance of the current source Ib.On applying KCL at nodes (a), (b), and (c) in Figure4, the obtained equations are
(8)Vout(sCgs1+gm1+1ro1+1ro2)-Vin(gm1+sCgs1)-Vd1ro1+gm2(C1C2)Vd1=0,(9)Vd1(1Rb+1ro1+sC1)-Voro1+gm1(Vin-Vo)-sC1Vg2=0,(10)Vg2(sCT)=Vd1(sC1),
where CT=C1+C2+Cgs2.Substituting the value ofVg2 from (10) in (9), it gives
(11)Vd1(1Rb+1ro1+sC1(1-C1CT))=Vo(1+gm1ro1ro1)-gm1Vin.
And, thus,
(12)Vd1=(RbCT{Vo(1+gm1ro1)-gm1ro1Vin}CT(ro1+Rb)+sC1(CT-C1)ro1Rb).
Replacing  Vd1  by using (12) in (8), the transfer function is given by
(13)AV(s)=(ro1ro2(sCgs1+gm1)X+gm1ro1ro2Rb(gm2ro1C1-CT))×(ro1ro2(sCgs1+gm1)X+X(ro1+ro2)+gm1ro1ro2Rb(gm2ro1C1-CT)+ro2Rb(gm2ro1C1-CT))-1,
where X=CT(ro1+Rb)+sC1ro1Rb(CT-C1).Assumingro1=ro2=ro, C1=C2=C, and Cgs1=Cgs2=Cgs,   (13) transforms into
(14)AV(s)=a2s2+a1s+a0a2s2+(a1+Δa1)s+(a0+Δa0),
where
(15)a2=CgsC(Cgs+C)ro3Rb,a1=ro2{gm1roRbC(Cgs+C)+Cgs(ro+Rb)(Cgs+2C)},Δa1=2CRb(Cgs+C),a0=gm1ro3(Cgs+2C)+gm1gm2ro3RbC,Δa0={gm2ro2RbC+roRb(Cgs+2C)+2ro2(Cgs+2C)}.
By definition, at ω=ωo, |AV|2=1/2 [16], and thus
(16)12=(a0-a2ω2)2+(a1ω)2((a0+Δa0)-a2ω2)+((a1+Δa1)ω)2.
The −3 dB frequency is
(17)ω0=1a2Δa12+2a1Δa1+2a0a2-a12-2a2Δa0.
(Since the expression of the lower 3-dB frequency is too large, the symbols are used to represent it.) By placing the values of symbols, it can be easily observed that the lower 3-dB frequency of floating gate FVF is much greater than that of simple FVF [7].To enhance the speed and reduce the power supply requirement, the wideband FGMOS-based FVF is used in conventional buffers [14] and is explained in the next section.


## 3. Proposed High-Frequency and Low-Power Output Stages

In many analog circuits, it is required to drive the impedance by a voltage buffer like that in operational amplifiers. For low-power circuits, low-power voltage buffers are used as output stages. The FVF has overcome the drawbacks of conventional voltage buffers. It has low-power dissipation, large output signal swing, low settling time, and almost unity gain [2]. Moreover, class AB biasing can be employed to reduce power consumption without affecting the ability to drive large capacitive loads [14]. Figure 5 shows an output stage based on conventional FVF [15]. But a FVF will not work properly in class AB. Centurelli et al. [14] have developed an output stage which was based on FVF operating in class AB (Figure 6).Figure 5
Output stage based on FVF [15].Figure 6
Class AB output stage based on FVF [14].In this paper, we have introduced two output stages which are based on FVF with FGMOS level shifter. The proposed output stages are shown in Figures7 and 8.Figure 7
The proposed output stage based on floating gate FVF.Figure 8
The proposed class AB output stage based on floating gate FVF.The output stage shown in Figure8 operates in class AB. It is shown in Section 2.2 that a FVF with a floating gate level shifter has larger bandwidth in comparison to the conventional FVF. This motivates us to replace MOS transistor M2 by a two-input FGMOS transistor. Moreover, the proposed circuits have high linearity, low power consumption, and power supply requirement.The effects and advantages of replacing conventional transistor by floating gate transistor can be easily observed through the simulation results.


## 4. Simulation Results

The designed circuits are simulated using PSPICE in TSMC 0.25 um CMOS technology. The FGMOS circuits have been simulated by using the model given by EdgarSánchez-Sinencio [9].In this work, the performance of a simple FVF and floating-gate-based FVF is compared. The circuit parameters of simple FVF and FGMOS-based FVF are given in Table1.Table 1
Circuit parameters of simple FVF and FGMOS-based FVF.
Parameters
Values
Aspect ratio of M1
(10/0.25)μm
Aspect ratio of M2
(10/1)μm
Bias currentIbias
500μA
FGMOS capacitorsC1=C2
175 fF
FGMOS resistorsR1=R2
10 GΩIt is obvious from the DC response (shown in Figure9) that, by using floating gate transistor in place of MOS transistor, the linearity and gain of the system have been improved.Figure 9
DC responses of simple and floating-gate-based FVF.Figure10 shows the frequency responses of these two circuits. The bandwidth is extended from 1.17 GHz to 4.78 GHz.Figure 10
Frequency responses of simple and floating-gate-based FVF.The paper has presented two new buffers that can be used as output stage in many analog and mixed-signal circuits. The circuit parameters of FVF-based output buffer and class AB output buffers are given in Tables2 and 3, respectively.Table 2
Circuit parameters of conventional FVF-based output stage and proposed FVF-based output stage.
Parameters
Values
Aspect ratio of M1 and M2
(13/0.25)μm
Aspect ratio of M3
(100/0.5)μm
Aspect ratio of M4 and M5
(50/0.5)μm
Bias voltageVbias_p = Vbias_n
0.3 V
Bias voltageVb
0.2 V
FGMOS capacitorsC1=C2
175 fF
FGMOS resistorsR1=R2
10 GΩTable 3
Circuit parameters of conventional and proposed class AB FVF buffer.
Parameters
Values
Aspect ratio of M1 and M2
(2/0.25)μm
Aspect ratio of M3 and M4
(3/0.25)μm
Aspect ratio of M5 and M6
(15/0.25)μm
Aspect ratio of M7
(1/0.25)μm
Bias voltageVbias
1 V
Bias voltageVb
0.2 V
FGMOS capacitorsC1=C2
175 fF
FGMOS resistorsR1=R2
10 GΩThe DC responses of the proposed and conventional buffer circuits are shown in Figures11 and 12. The use of FGMOS technology has improved the linearity of the buffers to a large extent and power consumption is reduced. The frequency responses of the conventional and proposed buffers are shown in Figures 13 and 14.Figure 11
DC responses of conventional (shown by solid line) and proposed FVF-based output stage.Figure 12
DC responses of conventional and proposed class AB FVF buffer.Figure 13
Frequency responses of conventional and proposed FVF-based output stage.Figure 14
Frequency responses of conventional and proposed class AB buffers.The level shifting in output signal can be easily observed in the proposed circuits. The bandwidth has been largely enhanced by using floating-gate-based FVF. The comparative results are given in Table4.Table 4
Simulation results of designed conventional and proposed circuits.
Simulated circuit
Power supply (V)
Output impedance (Ω)
Voltage gain
Power dissipation (mW)
Simple FVF
3.0
54.34
0.91
1.5
Conv. FGMOS-based FVF
1.0
65.09
0.95
0.5
Conv. FVF-based output stage
3.0
52.82
0.89
1.18
Prop. FVF-based output stage
0.8
51.45
0.91
0.0062
Conv. class AB FVF buffer
3.0
196.91
0.93
1.22
Prop. class AB FVF buffer
1.8
106.71
0.99
0.071


## 5. Conclusion

In this paper, two new low-power low-voltage and wideband output stages based on FVF with floating gate level shifter have been proposed. The use of floating gate technology provides the advantages of low-power consumption and low-power supply requirement. Moreover it gives a significant improvement in the bandwidth of the systems and the ability of the buffers to drive heavy capacitive loads by decreasing the output impedance. The simulation results have shown that the proposed buffers display good characteristics when compared with the reported works achieved so far. These improved buffer structures can be useful as output stage in many analog signal processing applications.



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