# Single OTRA Based Analog Multiplier and Its Applications

Authors: Rajeshwari Pandey; Neeta Pandey; B. Sriram; Sajal K. Paul
Journal: ISRN Electronics
 (2012)

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## Abstract

This paper presents an analog multiplier using single operational transresistance amplifier (OTRA). The proposed circuit is suitable for integration as it does not use any external passive component. It can be used as a four-quadrant multiplier. Theoretical propositions are verified through PSPICE simulations using 0.5μm CMOS parameters provided by MOSIS (AGILENT). The simulation results are in close agreement with theoretical predictions. The workability of the proposed multiplier is also tested through two applications, namely, a squarer and an amplitude modulator.


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## Body

## 1. Introduction

Analog multipliers find extensive application in the field of telecommunication, control, instrumentation, measurement, and signal processing [1]. A number of circuits are reported in literature relating to analog multipliers [1–12]. Circuits presented in [2–7] are based on Gilbert multiplier [12] and are suitable for CMOS integrated technology. The other class of the circuits is implemented using active analog blocks such as operational transconductance amplifier [1], differential difference current conveyors [8], current feedback amplifiers [9], current-controlled current conveyor [10], and current difference buffered amplifier [11].Recently the OTRA has emerged as an alternate analog building block [13–26] which inherits all the advantages of current mode techniques. The OTRA is a high gain current input voltage output device. The input terminals of OTRA are internally grounded, thereby eliminating response limitations due to parasitic capacitances and resistances [13] at the input. Several high performance CMOS OTRA topologies have been proposed in the literature [13–16]. In the recent past OTRA has been extensively used as an analog building block for realizing a number of analog signal processing [17–21] and generation circuits [22–24]. This paper presents a single OTRA based low voltage analog multiplier which does not use any external passive components and hence is suitable for integration. The proposed circuit can be used as a four quadrant multiplier without any change of topology. The workability of the proposed multiplier is demonstrated through two applications, namely, a squarer and an amplitude modulator.


## 2. The Proposed Multiplier Circuit

### 2.1. OTRA

OTRA is a three-terminal device, shown symbolically in Figure1 and its port relations are characterized by the following matrix:
(1)[VpVnVO]=[000000Rm-Rm0][IpInIO],
where Rm is transresistance gain of OTRA. For ideal operations Rm approaches infinity and forces the input currents to be equal. Thus OTRA must be used in a negative feedback configuration.Figure 1
OTRA circuit symbol.Figure2 Shows the CMOS realization of OTRA [15] which consists of the cascaded connection of the modified differential current conveyor (MDCC) [8] and common source amplifier. MDCC performs the current differencing operation and forces the two input terminals to be virtually grounded whereas the common source amplifier provides high gain.Figure 2
Figure6 CMOS implementation of OTRA [15].


### 2.2. Basic Multiplier Circuit

Figure3 Shows OTRA based multiplier structure. The transistors M1, M2,  M3, and M4 are matched transistors and operate in the linear region. In this paper v1 and v2 represent small signals, whereas VC1, VC2, and VDC are the bias voltages. OTRA inputs keep the sources of the two transistors M1 and M2 virtually grounded. The drain current for the MOS transistor operating in triode region is given by [27]
(2)ID=kWL((VGS-VT)-VDS2)VDS,
where k is transconductance; W and L respectively represent the channel width and length of the of the MOSFET. The other terms have their usual meaning.Figure 3
Proposed OTRA based multiplier structure.Using (2) the currents through p and n terminals of OTRA, that is, ip and in, respectively, can be expressed as
(3)ip=KnWL(((VDC+v1)-VT)-v22)v2+KnWL((VC1-VT)-vo2)vo,(4)in=KnWL((VDC-VT)-v22)v2+KnWL((VC2-VT)-vo2)vo.
As Rm approaches infinity the input currents are forced to be equal resulting in
(5)vo=v1v2(VC2-VC1)=Kv1v2,
where K is a proportionality constant and is the inverse of difference of gate voltages of M3 and M4.


### 2.3. Implementation Scheme for Superimposition of a Small Signal on DC Bias

As can be seen from Figure3 the gate voltage of M1 is (VDC+v1) which is a small signal superimposed over a dc bias. This voltage addition can be implemented using a scheme proposed in Figure 4 wherein vx is a small signal voltage and VC is a  bias voltage.Figure 4
Scheme for implementing an ac superimposed on dc bias.IfMP1 and MP2 are matched transistors and are operating in saturation then their drain currents will be equal resulting in
(6)12KpWL((v-VC)-Vtp)2=12KpWL((vx-v)-Vtp)2,
which gives
(7)v=(VC+vx)2.The voltage given by (7) can be used as the gate voltage for transistor M1 of Figure 3. Similarly gate voltage for transistor M2 can be obtained from (7) by making vx=0. Substituting these values of gate voltages in (5) the output of the multiplier gets modified to
(8)vo=K′v1v2,whereK′=K2.


### 2.4. The Proposed MOS Based Multiplier Structure

The complete MOS based multiplier structure is depicted in Figure5 which incorporates the voltage addition scheme of Figure 4.Figure 5
Complete multiplier circuit.As the transistors M1, M2, M3, and M4 need to operate in the triode region for proper operation of the multiplier the following conditions should be satisfied:
(9)((VC+v1)2-Vtn)>v2,((VC2)-Vtn)>v2,(VC1-Vtn)>vo,(VC2-Vtn)>vo.Now using (7) along with (9) the conditions for input signals v1 and v2 can be computed as
(10)Vtp<v1<(VC+2Vtp),v2<(VC+v1)2-Vtn.These equations suggest that the dynamic input range of the multiplier is controlled byVC.


## 2.1. OTRA

OTRA is a three-terminal device, shown symbolically in Figure1 and its port relations are characterized by the following matrix:
(1)[VpVnVO]=[000000Rm-Rm0][IpInIO],
where Rm is transresistance gain of OTRA. For ideal operations Rm approaches infinity and forces the input currents to be equal. Thus OTRA must be used in a negative feedback configuration.Figure 1
OTRA circuit symbol.Figure2 Shows the CMOS realization of OTRA [15] which consists of the cascaded connection of the modified differential current conveyor (MDCC) [8] and common source amplifier. MDCC performs the current differencing operation and forces the two input terminals to be virtually grounded whereas the common source amplifier provides high gain.Figure 2
Figure6 CMOS implementation of OTRA [15].


## 2.2. Basic Multiplier Circuit

Figure3 Shows OTRA based multiplier structure. The transistors M1, M2,  M3, and M4 are matched transistors and operate in the linear region. In this paper v1 and v2 represent small signals, whereas VC1, VC2, and VDC are the bias voltages. OTRA inputs keep the sources of the two transistors M1 and M2 virtually grounded. The drain current for the MOS transistor operating in triode region is given by [27]
(2)ID=kWL((VGS-VT)-VDS2)VDS,
where k is transconductance; W and L respectively represent the channel width and length of the of the MOSFET. The other terms have their usual meaning.Figure 3
Proposed OTRA based multiplier structure.Using (2) the currents through p and n terminals of OTRA, that is, ip and in, respectively, can be expressed as
(3)ip=KnWL(((VDC+v1)-VT)-v22)v2+KnWL((VC1-VT)-vo2)vo,(4)in=KnWL((VDC-VT)-v22)v2+KnWL((VC2-VT)-vo2)vo.
As Rm approaches infinity the input currents are forced to be equal resulting in
(5)vo=v1v2(VC2-VC1)=Kv1v2,
where K is a proportionality constant and is the inverse of difference of gate voltages of M3 and M4.


## 2.3. Implementation Scheme for Superimposition of a Small Signal on DC Bias

As can be seen from Figure3 the gate voltage of M1 is (VDC+v1) which is a small signal superimposed over a dc bias. This voltage addition can be implemented using a scheme proposed in Figure 4 wherein vx is a small signal voltage and VC is a  bias voltage.Figure 4
Scheme for implementing an ac superimposed on dc bias.IfMP1 and MP2 are matched transistors and are operating in saturation then their drain currents will be equal resulting in
(6)12KpWL((v-VC)-Vtp)2=12KpWL((vx-v)-Vtp)2,
which gives
(7)v=(VC+vx)2.The voltage given by (7) can be used as the gate voltage for transistor M1 of Figure 3. Similarly gate voltage for transistor M2 can be obtained from (7) by making vx=0. Substituting these values of gate voltages in (5) the output of the multiplier gets modified to
(8)vo=K′v1v2,whereK′=K2.


## 2.4. The Proposed MOS Based Multiplier Structure

The complete MOS based multiplier structure is depicted in Figure5 which incorporates the voltage addition scheme of Figure 4.Figure 5
Complete multiplier circuit.As the transistors M1, M2, M3, and M4 need to operate in the triode region for proper operation of the multiplier the following conditions should be satisfied:
(9)((VC+v1)2-Vtn)>v2,((VC2)-Vtn)>v2,(VC1-Vtn)>vo,(VC2-Vtn)>vo.Now using (7) along with (9) the conditions for input signals v1 and v2 can be computed as
(10)Vtp<v1<(VC+2Vtp),v2<(VC+v1)2-Vtn.These equations suggest that the dynamic input range of the multiplier is controlled byVC.


## 3. Nonideal Analysis

In this section the effect of finite transresistance gain of OTRA on multiplier is considered and compensation is employed for high frequency applications.  Ideally the transresistance gainRm is assumed to approach infinity. However, practically Rm is a frequency dependent finite value [13]. Considering a single pole model for the transresistance gain, Rm can be expressed as
(11)Rm(s)=(R01+s/ω0).For high frequency applications the transresistance gainRm(s) reduces to
(12)Rm(s)≈(1sCp),whereCp=1R0ω0.For high frequency applications the effect of transistor capacitances needs to be considered. Taking this effect into account the currentsip given by (3) modifies to
(13)ip=KnWL(((VDC+v1)-VT)-v22)v2+KnWL((VC1-VT)-vo2)vo+v1sCgs1,
where Cgs1 is the gate to source capacitance of M1; however, the current in remains the same as (4). The effect of Cgs1 can be compensated by adding a MOSFET M9, operating in triode region, at the inverting terminal of OTRA as shown in Figure 6. The effective gate to source capacitance of M9 should be equal to Cgs1. This would result in in as
(14)in=KnWL((VDC-VT)-v22)v2+KnWL((VC2-VT)-vo2)vo+v1sCgs1.Figure 6
Complete multiplier circuit withCgs compensation of transistor M1.The third term in (14) results due to gate to source capacitance of M9.Substituting (12), (13), and (14) in (1), vo, the output of multiplier can be evaluated as
(15)vo=v1v2/(VC2-VC1)1+sCp/{Kn(W/L)(VC2-VC1)}.And hence the 3 dB bandwidth of the multiplier can be expressed as(16)Kn(W/L)(VC2-VC1)Cp.


## 4. Simulation Results

The performance of the proposed multiplier of Figure5 is verified through SPICE simulation using 0.5 μm CMOS process parameters provided by MOSIS (AGILENT).  CMOS implementation of the OTRA [15] shown in Figure 2 is used and  supply voltages are taken as ±1.5 V. Aspect ratios used for different transistors of OTRA are the same as in [15] and are given in Table 1. All the transistors M1–M8 were used with equal aspect ratios having W/L=1μ/0.5μ. Control voltage is taken as VC=2 V, VC1=1 V, and VC2=1.25 V.Table 1
Aspect ratio of the transistors in OTRA circuit.
Transistor
W (μm)/L (μm)
MO1–MO3
100/2.5
MO4
10/2.5
MO5, MO6
30/2.5
MO7
10/2.5
MO8–MO11
50/2.5
MO12, MO13
100/2.5
MO14
50/0.5Figure7 depicts the dc transfer characteristics of the proposed multiplier. The transfer curve vo versus v1, with v2 kept constant at 250 mV, is shown in Figure 7(a). It is observed that vo varies almost linearly with v1. The nonlinearity curve representing maximum percent deviation of the ideal transfer characteristic as a function of input voltage v1 is shown in Figure 7(b). It is observed that the maximum nonlinearity over the entire input range does not exceed 2.05%. In Figure 7(c)vo is plotted with respect to v1 for different values of v2. Voltage v1 is swept from −300 mV to 300 mV while v2 is varied from −150 mV to 150 mV in steps of 50 mV. It shows that the proposed circuit is a four-quadrant multiplier.DC transfer characteristic.
(a)
v
o versus v1 with v2=250 mV
(b)
Nonlinearity curve withv2=250 mV
(c)
v
o versus v1 when v2 is varied from −150 mV to 150 mVThe frequency response of the proposed multiplier is shown in Figure8 for which v1 is kept constant at 200 mV whereas v2 is taken as an ac source having amplitude 250 mV. The 3 dB bandwidth is found to be 8 MHz.Figure 8
AC characteristic of the proposed multiplier.Figure9 shows the total harmonic distortion (THD) as a function of input signal amplitude when a constant dc voltage (250 mV) is applied to v2 while a 1 KHz sinusoidal signal is applied to v1 with varying amplitude. It can be seen that the maximum THD remains under 0.2% for the entire input range. Total power consumption of the proposed multiplier is 0.83 mw when v1=v2=0 V, VC=2 V, VC1=1 V, and VC2=1.25 V.Figure 9
THD versus input signal amplitude.


## 5. Applications

### 5.1. Squarer

The proposed multiplier can be used as a squarer circuit ifv1=v2=vin. The output of the multiplier is given by
(17)vo=K′vin2.Figure10 shows the square transfer characteristics wherein vin is varied from −400 mV to 400 mV.Figure 10
Square transfer characteristics.The observed output of the squarer is shown in Figure11. The input signal is taken as a 300 mV, 500 KHz sinusoid. The squared output is shown in Figure 11(a) and the spectrum of the squared output is shown in Figure 11(b).Output of the squarer.
(a)
Time domain output of the squarer
(b)
Spectrum of squared sine wave


### 5.2. Amplitude Modulator

The proposed multiplier, being a four-quadrant multiplier, can be used as an amplitude modulator (AM). A 5 KHz signal with 200 mV amplitude is multiplied by 250 mV, 50 KHz signal. Figure12 shows the output of the proposed multiplier confirming the modulation function. The time domain response of the multiplier is shown in Figures 12(a) and 12(b) displays the frequency spectrum.Multiplication of two sinusoids.
(a)
Time domain response
(b)
Frequency spectrum


## 5.1. Squarer

The proposed multiplier can be used as a squarer circuit ifv1=v2=vin. The output of the multiplier is given by
(17)vo=K′vin2.Figure10 shows the square transfer characteristics wherein vin is varied from −400 mV to 400 mV.Figure 10
Square transfer characteristics.The observed output of the squarer is shown in Figure11. The input signal is taken as a 300 mV, 500 KHz sinusoid. The squared output is shown in Figure 11(a) and the spectrum of the squared output is shown in Figure 11(b).Output of the squarer.
(a)
Time domain output of the squarer
(b)
Spectrum of squared sine wave


## 5.2. Amplitude Modulator

The proposed multiplier, being a four-quadrant multiplier, can be used as an amplitude modulator (AM). A 5 KHz signal with 200 mV amplitude is multiplied by 250 mV, 50 KHz signal. Figure12 shows the output of the proposed multiplier confirming the modulation function. The time domain response of the multiplier is shown in Figures 12(a) and 12(b) displays the frequency spectrum.Multiplication of two sinusoids.
(a)
Time domain response
(b)
Frequency spectrum


## 6. Conclusion

A single OTRA based analog multiplier is proposed which can be used as a four-quadrant multiplier also. The circuit does not require any passive element thus making it suitable for integration. Its application as a squarer and an amplitude modulator is also discussed. Theoretical propositions are verified through PSPICE simulations using 0.5μm CMOS parameters provided by MOSIS (AGILENT). Various performance parameters are analyzed through simulations and are found in close agreement to theoretical predictions.



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*Source: 890615-2012-11-14.xml*