# A Methodology for an FPGA Implementation of a Programmable Logic Controller to Control an Atomic Layer Deposition System

Authors: Peter Jamieson; Donald Blank; Janelle Ghanem; Tyler McGrew; Giancarlo Corti
Journal: International Journal of Reconfigurable Computing
 (2022)

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## Abstract

In this work, we present an industrial cold walled Atomic Layer Deposition (ALD) system, which can be controlled by either a traditional programmable logic controller (PLC) system or a field-programmable gate array (FPGA) prototyping board. This work presents an FPGA controlled system that takes ladder diagram (LD) control for a PLC and converts this control to Verilog HDL and programs an FPGA such that the FPGA prototyping board is used to control a real industrial application. We explore this approach since FPGA implementation of LD control could significantly reduce the cost of implementing these controllers with other potential advantages such as the improved granularity of timing control from milliseconds to nanoseconds, additional available pins for inputs and outputs far exceeding that of microprocessors, and lower power consumption for control. In this work, we provide details and descriptions of our industrial system (ALD), the LD control of this system and its implementation, our software flow to convert LDs to Verilog HDL, and our FPGA prototype board design to replace the existing electronic controller. We show how our LD-Verilog HDL converter in conjunction with FPGAs matches a PLC and demonstrate some of the benefits of using an FPGA.


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## Body

## 1. Introduction

The five major manufacturers of Programmable Logic Controllers (PLCs) for controlling industrial manufacturing processes include Allen-Bradley, Siemens, Schneider Electric, Mitsubishi Electric, and Omron (https://www.businesswire.com/news/home/20160502005493/en/Technavio-Announces-Top-Vendors-Global-Micro-PLC accessed March 10, 2020). These companies tend to provide software for designing the controller, the hardware to execute the control logic with, and several tools for advanced features such as monitoring, safety, and data analytics.One aspect of this space, which we believe can be improved, is the hardware implementation for the actual computational control. The invention and use of ladder logic (initially designed to control relays) to create these control systems are somewhat antiquated. The shift from relay-based control to programmable electronic implementation has resulted in the design of computational systems that enables the implementation of control algorithms for a wide range of applications.PLCs consist of circuitry that senses inputs and generates control signals and a CPU that generates the appropriate signals for an industrial system to implement a control algorithm. The CPU implements this control using timers, counters, mathematical operators, internal state, and signals of both analog and digital inputs from the system. This logic control can be executed on a broad range of computational substrates other than a traditional CPU, and in particular for this work, an implementation of Field-Programmable Gate Arrays (FPGAs) has the potential to significantly reduce the cost of the controller and reduce the execution time of the process from the millisecond range to the nanosecond range. Not only is a small FPGA, costing less than 50 USD, more than capable of running the control logic specified in LD, but it is also designed to execute these types of designs efficiently. It can be wired into these systems, and it uses less power than a traditional microprocessor-PLC controller [1] (noting, however, that power is not a major issue in many industrial applications).The goal of this paper is to show a real industrial system controlled via an FPGA. In particular, our contributions are as follows:(1)
A description and real implementation of the LD control into an industrial system, an Atomic Layer Deposition (ALD) system. This is the second, as we are aware of, demonstration of a real system being controlled via LD control that is converted and mapped to an FPGA.(2)
A tool (which is released open-source) to convert LDs into Verilog.(3)
A high-level method to map ladder logic control algorithms (using our open-source tool) to an FPGA prototyping board and the wiring and interfacing of that board into an industrial system. Though this may not be considered a major contribution, this workflow is key to achieving our second contribution and will help researchers and developers in the future.(4)
A demonstration of why FPGAs can improve the control of manufacturing as compared to traditional PLC controllers for the ALD system.The remainder of this paper is organized as follows: Section2 provides some background information and research, Section 3 describes the ALD system and the standard PLC implementation and wiring, Section 4 describes our software, the flow, and the wiring to use an FPGA to replace the PLC, Section 5 provides some results of our comparison of the two controllers, and Section 6 concludes the work and provides ideas for future work.


## 2. Background

This section reviews the basic concepts of an ALD system, ladder logic as ladder diagrams (LDs), and FPGA-based PLC implementations.


### 2.1. Atomic Layer Deposition System

The main idea of an Atomic Layer Deposition (ALD) system, first proposed by Aleskovskii [2], is to build up a physical material one atomic layer at a time by sequentially introducing gaseous precursors into the system that chemically modifies the material. Specifically, gases, called precursors, are introduced in a time-based sequence to create the material.Puurunen [3] published a history of ALD systems, which is a nice introductory academic reference to this topic. More recently, Oviroh et al. [4] wrote a comprehensive paper on the state of ALD systems providing insights on new materials that this process may create and how advances in computation and experimentation are impacting this technology. In terms of the PLC integration with the ALD system, the control is not overly complex, and there has been little published research on this topic. Maula’s research paper [5] briefly describes an industrial ALD system and the existence of the PLC controller. Additionally, there are several patents for this technology (for example, Patent 10,186,426), but we do not include those references here.The details of our ALD system are provided in Section3, including the LD algorithm.


### 2.2. Ladder Diagrams

The control of PLCs includes the use of ladder logic with what is called a ladder diagram (LD) and is formalized in the IEC61131-3 standard [6]. LD is a design language for describing control. Zhou and Twiss [7] provided an introduction explaining the workings of LDs compared to Petri nets. Also, for more information on LDs, there are many good basic introductions, for example, Hooper’s book [8].Figure1 shows an example of an LD system that has three inputs called Start, Stop, and Input and three outputs called Out0, Out1, and Out2. These signals are shown in the diagram, labeling either contacts (two parallel vertical lines) or coils (opening and closing round brackets). In this LD, there are three rungs of a ladder (Rung0, Rung1, and Rung2 colored green, red, and blue, respectively), where the term ladder comes from how the LD looks like a ladder.Figure 1
A simple LD example in diagram form.Processing LD is done from top to bottom; in Figure1, Rung0, Rung1, and Rung2 are processed in that sequential order, and the processing of all the rungs is known as a “scan.” For Rung0, we can interpret it as a logical AND, where if both Input and Start have been pressed/activated, then the coil Out0 generates an on signal. Once Rung0 is evaluated, we next evaluate Rung1, but the inputs for Rung1 are the outputs of both Rung0 and Rung2 organized as a logical OR operation. Since Rung2 has not been evaluated yet, we use the value of Out2 from the previous scan. From a finite state machine’s perspective, we would say we use the previous state value of Out2. It is important to understand that LD proceeds from top to bottom as it suggests that an LD needs to be sequentially evaluated to maintain the designer’s intended functionality, but if there are no dependencies in a rung, then, in theory (and as described by Milik [9]), the rung can be calculated in parallel with other rungs. Finally, the last rung is a latch (implemented with an OR followed by an AND); in that, once the Start input is activated, the Out2 signal will stay on until a Stop signal is pressed.Other special-purpose functions (called block functions or boxes by Siemens) can be defined in LDs, such as timers, counters, conditionals, and more complex finite state machines. Our work uses some of these structures, in particular timers and counters, and we will define them as they appear in our designs.


### 2.3. FPGAs as PLCs

FPGAs are a type of Integrated Chip (IC) that is reconfigurable devices, meaning that the functionality can be programmed or, possibly, reprogrammed after being manufactured. This means that these ICs can be programmed to implement a digital design. The FPGAs programmability, compared to ASICs, comes at a cost in terms of speed, power, and area [10], but to create an IC for a specific application is only viable for mass markets due to the high cost of the nonrecurring engineering cost in the millions to hundreds of millions of dollars. FPGAs are a common approach to designing digital systems in low-volume markets and for prototyping designs. For these reasons, an FPGA might be an appropriate device that could replace the PLC, and FPGAs only cost from tens of dollars to tens of thousands of dollars depending on capacity and speed requirements. Intel and Xilinx are the two largest FPGA companies.Researchers have and are still working on how reconfigurable devices can be used to implement LDs. The first implementation of an alternative control for Programmable Logic Devices (PLDs) was by Adamski and Monteiro [11]. The goal was to implement control on a PLD and to convert existing PLC designs into a PLD. They followed up this work with a later publication [12] that improved on their original work. Also, this work was further extended with Wegrzyn et al. [13], where they used the Petri net descriptions, but in this case, mapped their design to VHDL [14] so that they could target commercial CAD flows which map to devices such as FPGAs and Application-Specific Integrated Chips (ASICs).Petko and Karpiel [15] developed another technique to create control algorithms for FPGAs and ASICs and map them to Simulink so that their complete system environment could be simulated both electrically and mechanically. Their methodology is not an autonomous flow, but they provide many steps, both automated and manual, to map their control designs to a silicon implementation in either Verilog or VHDL. The input to their system, however, is not LD, and instead, the complete control is designed by an engineer familiar with their flow.Economakos and Economakos [16, 17] developed a fully automated flow that takes in a PLC language input (Siemens Statement List programming language of the well-known SIMATIC S7-300/400 PLCs) and converts a design to a C implementation which is then converted by the Catapult C tool flow (created by Mentor Graphics) to target an FPGA. Their main motivation is to efficiently implement more complex control designs that may not be feasibly implemented on a PLC.Du et al. [18] created a tool to map LDs to VHDL. Their motivation is to improve performance by using an FPGA, and they target Xilinx FPGAs. The limitation with their work is the tool, which is not open-source, and there has been no continuance or commercialization of their original work. Milik [9] created a flow from IEC61131-3 LDs to FPGAs via Verilog as the CAD flow design entry language. Milik spends significant time on optimizations in the conversion using compile-time approaches such as building a directed flow graph and analyzing these graphs. More recently, Milik et al. have furthered our understanding of compiling LD to FPGAs by direct FPGA synthesis [19].Ichikawa et al. [20] also demonstrate their conversion tool from LDs to VHDL and map their hardware design to Altera FPGAs. This work demonstrated a real FPGA interfaced with a real “perfect layer winder,” and they are the first group to demonstrate a full and real system controlled via an FPGA-based controller. Additionally, they created a custom FPGA prototyping board for this work since they could not find a board on the market that satisfied their needs.In Corti et al. [21], we created a tool to take Allen-Bradley LD and convert it to synthesizable Verilog targetting an FPGA. Similarly, Eassa et al. [22] implemented a RISC-V processor on an FPGA that can execute the control logic.


## 2.1. Atomic Layer Deposition System

The main idea of an Atomic Layer Deposition (ALD) system, first proposed by Aleskovskii [2], is to build up a physical material one atomic layer at a time by sequentially introducing gaseous precursors into the system that chemically modifies the material. Specifically, gases, called precursors, are introduced in a time-based sequence to create the material.Puurunen [3] published a history of ALD systems, which is a nice introductory academic reference to this topic. More recently, Oviroh et al. [4] wrote a comprehensive paper on the state of ALD systems providing insights on new materials that this process may create and how advances in computation and experimentation are impacting this technology. In terms of the PLC integration with the ALD system, the control is not overly complex, and there has been little published research on this topic. Maula’s research paper [5] briefly describes an industrial ALD system and the existence of the PLC controller. Additionally, there are several patents for this technology (for example, Patent 10,186,426), but we do not include those references here.The details of our ALD system are provided in Section3, including the LD algorithm.


## 2.2. Ladder Diagrams

The control of PLCs includes the use of ladder logic with what is called a ladder diagram (LD) and is formalized in the IEC61131-3 standard [6]. LD is a design language for describing control. Zhou and Twiss [7] provided an introduction explaining the workings of LDs compared to Petri nets. Also, for more information on LDs, there are many good basic introductions, for example, Hooper’s book [8].Figure1 shows an example of an LD system that has three inputs called Start, Stop, and Input and three outputs called Out0, Out1, and Out2. These signals are shown in the diagram, labeling either contacts (two parallel vertical lines) or coils (opening and closing round brackets). In this LD, there are three rungs of a ladder (Rung0, Rung1, and Rung2 colored green, red, and blue, respectively), where the term ladder comes from how the LD looks like a ladder.Figure 1
A simple LD example in diagram form.Processing LD is done from top to bottom; in Figure1, Rung0, Rung1, and Rung2 are processed in that sequential order, and the processing of all the rungs is known as a “scan.” For Rung0, we can interpret it as a logical AND, where if both Input and Start have been pressed/activated, then the coil Out0 generates an on signal. Once Rung0 is evaluated, we next evaluate Rung1, but the inputs for Rung1 are the outputs of both Rung0 and Rung2 organized as a logical OR operation. Since Rung2 has not been evaluated yet, we use the value of Out2 from the previous scan. From a finite state machine’s perspective, we would say we use the previous state value of Out2. It is important to understand that LD proceeds from top to bottom as it suggests that an LD needs to be sequentially evaluated to maintain the designer’s intended functionality, but if there are no dependencies in a rung, then, in theory (and as described by Milik [9]), the rung can be calculated in parallel with other rungs. Finally, the last rung is a latch (implemented with an OR followed by an AND); in that, once the Start input is activated, the Out2 signal will stay on until a Stop signal is pressed.Other special-purpose functions (called block functions or boxes by Siemens) can be defined in LDs, such as timers, counters, conditionals, and more complex finite state machines. Our work uses some of these structures, in particular timers and counters, and we will define them as they appear in our designs.


## 2.3. FPGAs as PLCs

FPGAs are a type of Integrated Chip (IC) that is reconfigurable devices, meaning that the functionality can be programmed or, possibly, reprogrammed after being manufactured. This means that these ICs can be programmed to implement a digital design. The FPGAs programmability, compared to ASICs, comes at a cost in terms of speed, power, and area [10], but to create an IC for a specific application is only viable for mass markets due to the high cost of the nonrecurring engineering cost in the millions to hundreds of millions of dollars. FPGAs are a common approach to designing digital systems in low-volume markets and for prototyping designs. For these reasons, an FPGA might be an appropriate device that could replace the PLC, and FPGAs only cost from tens of dollars to tens of thousands of dollars depending on capacity and speed requirements. Intel and Xilinx are the two largest FPGA companies.Researchers have and are still working on how reconfigurable devices can be used to implement LDs. The first implementation of an alternative control for Programmable Logic Devices (PLDs) was by Adamski and Monteiro [11]. The goal was to implement control on a PLD and to convert existing PLC designs into a PLD. They followed up this work with a later publication [12] that improved on their original work. Also, this work was further extended with Wegrzyn et al. [13], where they used the Petri net descriptions, but in this case, mapped their design to VHDL [14] so that they could target commercial CAD flows which map to devices such as FPGAs and Application-Specific Integrated Chips (ASICs).Petko and Karpiel [15] developed another technique to create control algorithms for FPGAs and ASICs and map them to Simulink so that their complete system environment could be simulated both electrically and mechanically. Their methodology is not an autonomous flow, but they provide many steps, both automated and manual, to map their control designs to a silicon implementation in either Verilog or VHDL. The input to their system, however, is not LD, and instead, the complete control is designed by an engineer familiar with their flow.Economakos and Economakos [16, 17] developed a fully automated flow that takes in a PLC language input (Siemens Statement List programming language of the well-known SIMATIC S7-300/400 PLCs) and converts a design to a C implementation which is then converted by the Catapult C tool flow (created by Mentor Graphics) to target an FPGA. Their main motivation is to efficiently implement more complex control designs that may not be feasibly implemented on a PLC.Du et al. [18] created a tool to map LDs to VHDL. Their motivation is to improve performance by using an FPGA, and they target Xilinx FPGAs. The limitation with their work is the tool, which is not open-source, and there has been no continuance or commercialization of their original work. Milik [9] created a flow from IEC61131-3 LDs to FPGAs via Verilog as the CAD flow design entry language. Milik spends significant time on optimizations in the conversion using compile-time approaches such as building a directed flow graph and analyzing these graphs. More recently, Milik et al. have furthered our understanding of compiling LD to FPGAs by direct FPGA synthesis [19].Ichikawa et al. [20] also demonstrate their conversion tool from LDs to VHDL and map their hardware design to Altera FPGAs. This work demonstrated a real FPGA interfaced with a real “perfect layer winder,” and they are the first group to demonstrate a full and real system controlled via an FPGA-based controller. Additionally, they created a custom FPGA prototyping board for this work since they could not find a board on the market that satisfied their needs.In Corti et al. [21], we created a tool to take Allen-Bradley LD and convert it to synthesizable Verilog targetting an FPGA. Similarly, Eassa et al. [22] implemented a RISC-V processor on an FPGA that can execute the control logic.


## 3. Implementation of the ALD System

A schematic of the general ALD setup is depicted in Figure2. The ALD reactor used for all experiments is a cold wall thermal ALD reactor, meaning that all energy required for the reaction is provided by heat, as opposed to plasma/radical-enhanced ALD [23]. The reactor uses an inert carrier gas (N2) to carry the precursors into and out of the chamber. Although the use of carrier gases results in less efficient utilization of precursors, it also allows for shorter purge times to effectively clear the chamber, allowing for shorter cycle times overall [23].Figure 2
An image of our ALD system (a), schematic with valves and sensors (b), and corresponding signals as a general-purpose I/O pin layout (c).
(a)(b)(c)


### 3.1. Control of Our ALD System with PLC

The ALD sequence begins by pressing the start button (start), which prompts the vacuum valves VV1 and VV2 to open and start the controllers of the precursor bottles and reactor heater (Pbot and RH), respectively. When the chamber pressure (Pstch) is below 1 mbar, the controller turns on the mass flow controllers (MFC) to continuously flow N2 until the end of the deposition sequence. With the N2 flowing, the ALD waits until the PIDs signal the controller that the bottle (TP1) and reactor (TR) temperatures reach their setpoint. When the system is up to temperature, the deposition cycle shown in Figure 3 begins by closing the VV1 and VV2 valves. Then, the ALD controller follows the deposition pattern; first, it activates precursor valve (SV1) for a precursor pulse of tpp1 msec, waits for twp1 msec, and activates vacuum valve one (VV1) for tvp1 msec; when the VV1 closes, it activates the water valve (SV4) for a water pulse of tw msec, waits for tww msec, and then activates vacuum valve two (VV2) for tvw msec, and when the VV2 closes, the controller counts one cycle. Finally, when either the desired number of cycles have occurred or the stop button (stop) is pressed, the controller will shut down the heaters Pbot and RH and close the vacuum valves VV1 and VV2. The N2 must flow until the pressure in the chamber equals to atmospheric pressure (Patm). We have implemented this algorithm as an LD design with 37 rungs for both Allen-Bradley PLCs and Siemens PLCs, where the first is available to view on our GitHub repository (https://github.com/ghanemja/senior-design).Figure 3
A timing diagram of the valve signals for our ALD system.Figure2 shows a picture of the ALD system at Miami University. The picture gives researchers a view of what this type of manufacturing system is and how it is interfaced. The main chamber is held within the cabinet. Additionally, the front panel has a red emergency stop button, a human-machine interface (HMI), and another button to start operation. When the FPGA is wired into the system, the PLC (also contained in the cabinet) is disconnected, and the FPGA interface replaces this controlling connection.


## 3.1. Control of Our ALD System with PLC

The ALD sequence begins by pressing the start button (start), which prompts the vacuum valves VV1 and VV2 to open and start the controllers of the precursor bottles and reactor heater (Pbot and RH), respectively. When the chamber pressure (Pstch) is below 1 mbar, the controller turns on the mass flow controllers (MFC) to continuously flow N2 until the end of the deposition sequence. With the N2 flowing, the ALD waits until the PIDs signal the controller that the bottle (TP1) and reactor (TR) temperatures reach their setpoint. When the system is up to temperature, the deposition cycle shown in Figure 3 begins by closing the VV1 and VV2 valves. Then, the ALD controller follows the deposition pattern; first, it activates precursor valve (SV1) for a precursor pulse of tpp1 msec, waits for twp1 msec, and activates vacuum valve one (VV1) for tvp1 msec; when the VV1 closes, it activates the water valve (SV4) for a water pulse of tw msec, waits for tww msec, and then activates vacuum valve two (VV2) for tvw msec, and when the VV2 closes, the controller counts one cycle. Finally, when either the desired number of cycles have occurred or the stop button (stop) is pressed, the controller will shut down the heaters Pbot and RH and close the vacuum valves VV1 and VV2. The N2 must flow until the pressure in the chamber equals to atmospheric pressure (Patm). We have implemented this algorithm as an LD design with 37 rungs for both Allen-Bradley PLCs and Siemens PLCs, where the first is available to view on our GitHub repository (https://github.com/ghanemja/senior-design).Figure 3
A timing diagram of the valve signals for our ALD system.Figure2 shows a picture of the ALD system at Miami University. The picture gives researchers a view of what this type of manufacturing system is and how it is interfaced. The main chamber is held within the cabinet. Additionally, the front panel has a red emergency stop button, a human-machine interface (HMI), and another button to start operation. When the FPGA is wired into the system, the PLC (also contained in the cabinet) is disconnected, and the FPGA interface replaces this controlling connection.


## 4. Replacing a PLC with an FPGA

The two primary steps required to convert an LD to work on an FPGA to control an industrial system are as follows: first, converting the LD into a form that can be inputted and passed through an FPGA CAD flow to program the FPGA, and second, a wiring interface between the FPGA and the industrial system to properly send the electrical signals to the system.


### 4.1. Converting LDs to Verilog HDL

In previous work, we created Hashigo and released the open-source code athttps://github.com/NigoroJr/hashigo that was a complete LD to Verilog conversion system using Flex and Bison to parse the LD and back-end code that compiles the LD to Verilog [21]. We, however, learned that a complex full compiler approach is not needed to process LDs to Verilog. Instead, in this version of our work, we present a complex Python script that can perform the same conversion process and has support for timers and counters, the latter of which Hashigo could only implement via alternative methods.Algorithm 1 shows the high-level steps the Python script and the associated environment take to convert LDs to Verilog files. Note that specific details, such as read, write, and processing details of the conversion, can be seen in the open-source code:https://github.com/ghanemja/senior-design. This file type is structured in XML format, shown in Figure 4, and contains all the information about an Allen-Bradley ladder logic program and environment needed to convert the program to HDL. This .L5X file is parsed using the ElementTree XML python library to obtain the root of the XML tree.Algorithm 1: Pseudocode for steps taken to convert LDs to Verilog HDL.
(1)
function Ladder2Verilog(L5X_filename)(2)
L5X_File=readL5X_file.l5x(3)
Find physical IOs, logical rungs, and function modules information(4)
writeHashigo_File.hshg(5)
Hashigo_File=readHashigo_File.hshg(6)
Verilog_File=readVerilog_Template.v(7)
Assign physical IOS to FPGA pins(8)
for all rungs do(9)
Convertrung to nodes_list(10)
Makeoutput_functions list from nodes_list(11)
Create Veriloglogical_expression from nodes_list(12)
Construct Verilogrung_text assignment statements(13)
end for(14)
Addrung assigning memory registers to outputs(15)
Create register declarations and reset assignments(16)
Create function module instantiations(17)
for all placeholders do(18)
Verilog_File=Verilog_File.replaceplaceholder,text(19)
end for(20)
writeVerilog_File.v(21)
end functionFigure 4
An example of a logical rung found in an L5X XML tree.Using an XML input format, shown in Figure4, from the LD programming environment and Algorithm 1, we parse each rung of the ladder sequentially and convert the rungs into a simplified, intermediate data structure, as shown in Figure 5. Once this intermediate file exists, it is then converted into a Verilog file that represents the LD, shown in Figure 6. This logical Verilog expression is created by using a dictionary or look-up table, shown in Table 1, where each node type corresponds directly to a string segment which is added to the overall expression string, as shown in Figure 6.Figure 5
An example of the logical rung converted from XML to the intermediate data structure.Figure 6
Verilog assignment statement created from the intermediate data structure.Table 1
Dictionary of ladder logic functions with their Verilog equivalents.
LD functionLD XMLVerilog textandand&&ororNO contactxic(a)aNC contactxio(a)!aComparator ≥GEQ(a, b)(a≥b)Comparator ==EQu(a, b)(a==b)One shots relayONS(a)(a&&!prev_a)FB timerTON()Timer()FB counterCTU()Counter()This approach interprets each LD rung sequentially and creates the Verilog assignment statements. Then, the system creates an extra rung to assign each register’s memory value and the register declarations and assignments based on the information from the date structures previously created. Then, the system creates module instantiations for each function module used in the ladder logic (timers, counters, etc.) and wires these modules into the main module. Finally, the system uses all of the text sections to write the final Verilog file to the directory. Our Python approach is easy for researchers to understand and extend, and our controller implementation on an FPGA results in an implementation that is fast enough to process the control required by the industrial applications we are targeting.


#### 4.1.1. Timer and Counterimplementation Details

Our previous research and software in this space, Hashigo, supported LD conversion, but it did not include the implementation of timers and counters. However, our tool flow in the Python version has a way of implementing both timers and counters, and we added this functionality since we needed both for interfacing with the ALD system.To implement timers or counters (or, in theory, any functional block), we implement a configurable Verilog module that has inputs and outputs of a timer, where the inputs can be set to parametrize the needed functionality. The Python scripts read the type of functional block in the LD and set the appropriate signals. These blocks have been previously added to the dictionary or look-up table, shown in Table1. Specific details on the generation of these function blocks can be found on the open-source code: https://github.com/ghanemja/senior-design. Our system, however, targets a Verilog implementation but is not provided with the clocking speed of the FPGA prototype board, and therefore, the designer of the FPGA control system will have to do some calculations to set up the parameters for the required timer rate.


### 4.2. FPGA Prototype Board as a Controller

Once the Verilog files have been generated by the script, the next step is to map the design onto an FPGA and interface the FPGA with the system replacing the PLC. Our replacement PLC is a DE2-115 FPGA prototyping board from Terasic that includes a Cyclone IV Intel FPGA. This board is commercially available and used by universities and undergraduate students to learn how to use FPGAs.To map the Verilog files onto the FPGA, we use a commercial CAD tool that converts design files into programmable bit files that, when loaded on a specific FPGA, implements the logic design on the FPGA. Since we are using Intel FPGAs, the corresponding Intel tool is Quartus [24]. Within Quartus, we create a project, set up the appropriate Verilog design files, and most importantly, map the pins of the FPGA to particular signals in the design. Pin-mapping maps the inputs and outputs of the ALD system to the pins of the FPGA controller, and on the DE2-115 board, the general-purpose input-output (GPIO) pins allow for these connections.Once the digital signals are mapped to the GPIO pins, the next step is to take the three to five volt signal with low amperage output and convert the control signals to the industrial standard 24 volts [25]. Once the signals are conditioned to meet the ALD input and outputs, we can connect the FPGA board into the system to control it.Figure7 shows the printed circuit board (PCB) developed to interface the FPGA GPIOs with the ALD systems’ circuitry. Since both ALD and the FPGA use a 40-pin connection, we developed this PCB to interface the two systems with two integrated circuits (IC) components.Figure 7
Our PCB developed for interfacing the FPGA with the ALD.To convert the 24 V digital of the ALD signal to 3.3 V level for FPGA input, a TA ULN2003AN IC is used. This 7-channel Darlington transistor array, commonly used for switching applications, is operated in an inverting, common-emitter configuration, as can be seen in Figure8(a), where VIN is a 0–24 V digital signal from the ALD, VCC is 3.3 V, and RL is a digital input to the FPGA.Figure 8
Simplified switching topologies used for interfacing the FPGA and ALD: (a) the switch used as an inverting, low-side switch to convert 24 V ALD signals to 3.3 V FPGA signals and (b) the switch used as a noninverting high-side switch to drive 24 V inductive ALD loads from a 3.3 V FPGA signal.
(a)(b)However, this low-side driver configuration cannot be used to drive ALD inputs (solenoid valves, relays, etc.) from FPGA signals because this topology is not able to deliver the required 400 mA of current to inductive loads,ZL. Instead, a high-side driver topology based on the MIC2981 IC is used to drive the ALD inputs from the FPGA, as shown in Figure 8(b), where VIN is a 0–3.3 V digital signal from the FPGA, VCC is 24 V, and ZL is an ALD valve coil.


## 4.1. Converting LDs to Verilog HDL

In previous work, we created Hashigo and released the open-source code athttps://github.com/NigoroJr/hashigo that was a complete LD to Verilog conversion system using Flex and Bison to parse the LD and back-end code that compiles the LD to Verilog [21]. We, however, learned that a complex full compiler approach is not needed to process LDs to Verilog. Instead, in this version of our work, we present a complex Python script that can perform the same conversion process and has support for timers and counters, the latter of which Hashigo could only implement via alternative methods.Algorithm 1 shows the high-level steps the Python script and the associated environment take to convert LDs to Verilog files. Note that specific details, such as read, write, and processing details of the conversion, can be seen in the open-source code:https://github.com/ghanemja/senior-design. This file type is structured in XML format, shown in Figure 4, and contains all the information about an Allen-Bradley ladder logic program and environment needed to convert the program to HDL. This .L5X file is parsed using the ElementTree XML python library to obtain the root of the XML tree.Algorithm 1: Pseudocode for steps taken to convert LDs to Verilog HDL.
(1)
function Ladder2Verilog(L5X_filename)(2)
L5X_File=readL5X_file.l5x(3)
Find physical IOs, logical rungs, and function modules information(4)
writeHashigo_File.hshg(5)
Hashigo_File=readHashigo_File.hshg(6)
Verilog_File=readVerilog_Template.v(7)
Assign physical IOS to FPGA pins(8)
for all rungs do(9)
Convertrung to nodes_list(10)
Makeoutput_functions list from nodes_list(11)
Create Veriloglogical_expression from nodes_list(12)
Construct Verilogrung_text assignment statements(13)
end for(14)
Addrung assigning memory registers to outputs(15)
Create register declarations and reset assignments(16)
Create function module instantiations(17)
for all placeholders do(18)
Verilog_File=Verilog_File.replaceplaceholder,text(19)
end for(20)
writeVerilog_File.v(21)
end functionFigure 4
An example of a logical rung found in an L5X XML tree.Using an XML input format, shown in Figure4, from the LD programming environment and Algorithm 1, we parse each rung of the ladder sequentially and convert the rungs into a simplified, intermediate data structure, as shown in Figure 5. Once this intermediate file exists, it is then converted into a Verilog file that represents the LD, shown in Figure 6. This logical Verilog expression is created by using a dictionary or look-up table, shown in Table 1, where each node type corresponds directly to a string segment which is added to the overall expression string, as shown in Figure 6.Figure 5
An example of the logical rung converted from XML to the intermediate data structure.Figure 6
Verilog assignment statement created from the intermediate data structure.Table 1
Dictionary of ladder logic functions with their Verilog equivalents.
LD functionLD XMLVerilog textandand&&ororNO contactxic(a)aNC contactxio(a)!aComparator ≥GEQ(a, b)(a≥b)Comparator ==EQu(a, b)(a==b)One shots relayONS(a)(a&&!prev_a)FB timerTON()Timer()FB counterCTU()Counter()This approach interprets each LD rung sequentially and creates the Verilog assignment statements. Then, the system creates an extra rung to assign each register’s memory value and the register declarations and assignments based on the information from the date structures previously created. Then, the system creates module instantiations for each function module used in the ladder logic (timers, counters, etc.) and wires these modules into the main module. Finally, the system uses all of the text sections to write the final Verilog file to the directory. Our Python approach is easy for researchers to understand and extend, and our controller implementation on an FPGA results in an implementation that is fast enough to process the control required by the industrial applications we are targeting.


### 4.1.1. Timer and Counterimplementation Details

Our previous research and software in this space, Hashigo, supported LD conversion, but it did not include the implementation of timers and counters. However, our tool flow in the Python version has a way of implementing both timers and counters, and we added this functionality since we needed both for interfacing with the ALD system.To implement timers or counters (or, in theory, any functional block), we implement a configurable Verilog module that has inputs and outputs of a timer, where the inputs can be set to parametrize the needed functionality. The Python scripts read the type of functional block in the LD and set the appropriate signals. These blocks have been previously added to the dictionary or look-up table, shown in Table1. Specific details on the generation of these function blocks can be found on the open-source code: https://github.com/ghanemja/senior-design. Our system, however, targets a Verilog implementation but is not provided with the clocking speed of the FPGA prototype board, and therefore, the designer of the FPGA control system will have to do some calculations to set up the parameters for the required timer rate.


## 4.1.1. Timer and Counterimplementation Details

Our previous research and software in this space, Hashigo, supported LD conversion, but it did not include the implementation of timers and counters. However, our tool flow in the Python version has a way of implementing both timers and counters, and we added this functionality since we needed both for interfacing with the ALD system.To implement timers or counters (or, in theory, any functional block), we implement a configurable Verilog module that has inputs and outputs of a timer, where the inputs can be set to parametrize the needed functionality. The Python scripts read the type of functional block in the LD and set the appropriate signals. These blocks have been previously added to the dictionary or look-up table, shown in Table1. Specific details on the generation of these function blocks can be found on the open-source code: https://github.com/ghanemja/senior-design. Our system, however, targets a Verilog implementation but is not provided with the clocking speed of the FPGA prototype board, and therefore, the designer of the FPGA control system will have to do some calculations to set up the parameters for the required timer rate.


## 4.2. FPGA Prototype Board as a Controller

Once the Verilog files have been generated by the script, the next step is to map the design onto an FPGA and interface the FPGA with the system replacing the PLC. Our replacement PLC is a DE2-115 FPGA prototyping board from Terasic that includes a Cyclone IV Intel FPGA. This board is commercially available and used by universities and undergraduate students to learn how to use FPGAs.To map the Verilog files onto the FPGA, we use a commercial CAD tool that converts design files into programmable bit files that, when loaded on a specific FPGA, implements the logic design on the FPGA. Since we are using Intel FPGAs, the corresponding Intel tool is Quartus [24]. Within Quartus, we create a project, set up the appropriate Verilog design files, and most importantly, map the pins of the FPGA to particular signals in the design. Pin-mapping maps the inputs and outputs of the ALD system to the pins of the FPGA controller, and on the DE2-115 board, the general-purpose input-output (GPIO) pins allow for these connections.Once the digital signals are mapped to the GPIO pins, the next step is to take the three to five volt signal with low amperage output and convert the control signals to the industrial standard 24 volts [25]. Once the signals are conditioned to meet the ALD input and outputs, we can connect the FPGA board into the system to control it.Figure7 shows the printed circuit board (PCB) developed to interface the FPGA GPIOs with the ALD systems’ circuitry. Since both ALD and the FPGA use a 40-pin connection, we developed this PCB to interface the two systems with two integrated circuits (IC) components.Figure 7
Our PCB developed for interfacing the FPGA with the ALD.To convert the 24 V digital of the ALD signal to 3.3 V level for FPGA input, a TA ULN2003AN IC is used. This 7-channel Darlington transistor array, commonly used for switching applications, is operated in an inverting, common-emitter configuration, as can be seen in Figure8(a), where VIN is a 0–24 V digital signal from the ALD, VCC is 3.3 V, and RL is a digital input to the FPGA.Figure 8
Simplified switching topologies used for interfacing the FPGA and ALD: (a) the switch used as an inverting, low-side switch to convert 24 V ALD signals to 3.3 V FPGA signals and (b) the switch used as a noninverting high-side switch to drive 24 V inductive ALD loads from a 3.3 V FPGA signal.
(a)(b)However, this low-side driver configuration cannot be used to drive ALD inputs (solenoid valves, relays, etc.) from FPGA signals because this topology is not able to deliver the required 400 mA of current to inductive loads,ZL. Instead, a high-side driver topology based on the MIC2981 IC is used to drive the ALD inputs from the FPGA, as shown in Figure 8(b), where VIN is a 0–3.3 V digital signal from the FPGA, VCC is 24 V, and ZL is an ALD valve coil.


## 5. Results and Testing

For our experiments, we run two tests. First, we show that the FPGA implementation is equivalent to the PLC by comparing the signals generated by both systems and verifying them. For our second result, we show how the FPGA has the potential for finer timing-granularity compared to a PLC. Finally, we describe our complete system where the FPGA controls the ALD system in a real-world test.


### 5.1. ALD Equivalent Control with FPGA Prototyping Board

In our first experiment, we show how the signals generated by the FPGA (which are mapped by our Python scripts and used to create the design files that are programmed to the FPGA) are timing equivalent to the PLC-generated signals programmed from the Allen-Bradley tool and mapping flow.Figure9 shows a screenshot of our comparison method. The full video can be viewed at https://www.youtube.com/watch?v=cyB6Dcb55wc, and the comparison of the FPGA (top) and PLC (bottom) starts at timestamp 4 : 30 of the video. In Figure 9, we can see that the FPGA has lit two of the LEDs on the FPGA prototyping board, which matches the two LEDs, 6 and 7, on the PLC. In the film, we show how the prototyping board LEDs match the PLC lights. This is a functional demonstration of the equivalency of the two controllers, and it also shows how our alternative flow that maps to the FPGA is equivalent to the PLC program noting that we use the same LD, our Python tool converts this LD design to be implemented on the FPGA on the DE2-115.Figure 9
A comparison of the output signals on an FPGA (top with red LEDs) to the PLC controller (bottom with orange LEDs).The current processing cost on the FPGA (which we call a duty-cycle, equivalent to a PLC scan) is 37 rungs plus one cycle to update all the outputs. On the FPGA, we execute this; this means that the duty-cycle is 760 ns. Note that this duty-cycle could be decreased if we included the optimization capabilities to analyze the dependencies between rungs and parallelizing independent rungs. However, the current scan of 760 ns is already fast compared to the PLC emulation.


### 5.2. Finer Grain Timing Implementation on an FPGA

Next, we show how the granularity of control timing possible on the FPGA is significantly faster than what PLCs are currently capable of doing. Most PLCs smallest granularity of timing is one millisecond to implement a toggling signal (clock). On the DE2-115, it is possible to implement a granularity of toggling that is equal to the clock speed of the FPGA.The clock on the DE2-115 prototyping board is 50 MHz, meaning the clock period is 20 ns, and the granularity of the timing toggle would be 20 ns or 10,000 times faster than the 1 ms granularity of the PLC (note that the phase-locked loop functional units on this FPGA allow us to control the clock, but this is unnecessary). We note, however, that not many mechanical and manufacturing systems need this small granularity of control, but it is possible with this capability that new applications for this could be introduced within the field.


### 5.3. Real FPGA as Controller for ALD

The testing setup for the full ALD system with the FPGA controller is shown in Figure10. An interfacing PCB (previously described) is connected to the FPGA and the ALD using two 40-pin ribbon cables, which fit into the 40-pin connectors on the PCB. Two wires are used to connect 24 V and ground from the ALD to the PCB through screw terminals. The 3.3 V and ground from the FPGA are connected to the PCB through two of the connections on the 40-pin ribbon cable. A BI1-EG05-AP6X inductive proximity sensor is attached to the SV1 valve to measure its physical actuation. This valve was powered at 24 V using a DC power supply. Finally, a Keysight oscilloscope is attached to both the FPGA control signal and the valve sensor to compare the intended and physical response of the SV1 valve within the ALD system.Figure 10
Our ALD system interfaced with the DE2-115 (bottom right).With the hardware integration between the FPGA and ALD completed, we test the system to determine the capabilities of the FPGA. Initially, valve timings with the ALD cycle are programmed in seconds. This works well when simulating the outputs of the FPGA in simulation tests; however, since we could not physically see the outputs of the PLC and FPGA turning on and off at speed, we were unsure how the system would respond once switching speed is increased. To test whether the system is operating as desired, we attached an oscilloscope probe to the output of SV1 on the FPGA and a valve position sensor on the corresponding valve on the ALD. This valve is the first valve that is opened during the ALD cycle (as can be seen in Figure2), so measuring its response allows us to determine the cycle time of the ALD by measuring the rising edge to rising edge period of the valve position feedback. The valve position sensor is an on/off switch, and the rising edges are easy to identify in the waveforms.We measure the response time of the ALD valve to determine what is the minimum cycle time the valve can be operated at. Figure11 shows the switching waveform in red (lower peaks) and the valve’s physical response to a switch in blue (larger peaks). As can be seen in Figure 11, once valve timing is at 5-6 ms (Figure 11(b)), the valve can still respond, but at a switching speed of 600 μs, the valve fails to respond (Figure 11(c)). Therefore, to ensure that the system is stable, valve timing on the FPGA is set to 20 ms.Figure 11
Control and response of the valve for decreasing actuation times: valve actuated for (a) 60 ms, (b) 6 ms, and (c) 0.6 ms.
(a)(b)(c)Next, to show what the FPGA controller is capable of compared to a PLC, we reduce the timing of the internal timers within the ALD cycle called “twait1” and “twaitw” first to the minimum time that the PLC can control them, which is 1 ms. The cycle time for the ALD cycle is recorded as the peak-to-peak timing of the rising edge of the valve response, as can be seen in Figure12. The ALD cycle time (a complete control cycle) takes 168 ms when controlled by the PLC.Figure 12
Control and response of the valve when using 1 ms internal timers. Rising and falling edge times are labeled in the bottom of the two timing waveforms.By changing these two internal timers so that they are faster than what the PLC is capable of, we record the ALD cycle time for the FPGA. As shown in Figure13, the internal timers are reduced to 1 μs, which results in a 2 ms reduction in one ALD deposition cycle. For example, a 50 nm copper oxide layer deposited via ALD has an average growth per cycle of ≈0.15 [26], which represents a 3.3 sec reduction per batch. This shows that an FPGA controller (even a simple, cheap one) is able to improve the overall production time a PLC controller can achieve. Note, however, that we are showing these results to demonstrate the capability of an FPGA-based controller and not stating that this would be recommended for the ALD system.Figure 13
Control and response of the valve when using 1μs internal timers. Rising and falling edge times are labeled in the bottom of the two timing waveforms.


## 5.1. ALD Equivalent Control with FPGA Prototyping Board

In our first experiment, we show how the signals generated by the FPGA (which are mapped by our Python scripts and used to create the design files that are programmed to the FPGA) are timing equivalent to the PLC-generated signals programmed from the Allen-Bradley tool and mapping flow.Figure9 shows a screenshot of our comparison method. The full video can be viewed at https://www.youtube.com/watch?v=cyB6Dcb55wc, and the comparison of the FPGA (top) and PLC (bottom) starts at timestamp 4 : 30 of the video. In Figure 9, we can see that the FPGA has lit two of the LEDs on the FPGA prototyping board, which matches the two LEDs, 6 and 7, on the PLC. In the film, we show how the prototyping board LEDs match the PLC lights. This is a functional demonstration of the equivalency of the two controllers, and it also shows how our alternative flow that maps to the FPGA is equivalent to the PLC program noting that we use the same LD, our Python tool converts this LD design to be implemented on the FPGA on the DE2-115.Figure 9
A comparison of the output signals on an FPGA (top with red LEDs) to the PLC controller (bottom with orange LEDs).The current processing cost on the FPGA (which we call a duty-cycle, equivalent to a PLC scan) is 37 rungs plus one cycle to update all the outputs. On the FPGA, we execute this; this means that the duty-cycle is 760 ns. Note that this duty-cycle could be decreased if we included the optimization capabilities to analyze the dependencies between rungs and parallelizing independent rungs. However, the current scan of 760 ns is already fast compared to the PLC emulation.


## 5.2. Finer Grain Timing Implementation on an FPGA

Next, we show how the granularity of control timing possible on the FPGA is significantly faster than what PLCs are currently capable of doing. Most PLCs smallest granularity of timing is one millisecond to implement a toggling signal (clock). On the DE2-115, it is possible to implement a granularity of toggling that is equal to the clock speed of the FPGA.The clock on the DE2-115 prototyping board is 50 MHz, meaning the clock period is 20 ns, and the granularity of the timing toggle would be 20 ns or 10,000 times faster than the 1 ms granularity of the PLC (note that the phase-locked loop functional units on this FPGA allow us to control the clock, but this is unnecessary). We note, however, that not many mechanical and manufacturing systems need this small granularity of control, but it is possible with this capability that new applications for this could be introduced within the field.


## 5.3. Real FPGA as Controller for ALD

The testing setup for the full ALD system with the FPGA controller is shown in Figure10. An interfacing PCB (previously described) is connected to the FPGA and the ALD using two 40-pin ribbon cables, which fit into the 40-pin connectors on the PCB. Two wires are used to connect 24 V and ground from the ALD to the PCB through screw terminals. The 3.3 V and ground from the FPGA are connected to the PCB through two of the connections on the 40-pin ribbon cable. A BI1-EG05-AP6X inductive proximity sensor is attached to the SV1 valve to measure its physical actuation. This valve was powered at 24 V using a DC power supply. Finally, a Keysight oscilloscope is attached to both the FPGA control signal and the valve sensor to compare the intended and physical response of the SV1 valve within the ALD system.Figure 10
Our ALD system interfaced with the DE2-115 (bottom right).With the hardware integration between the FPGA and ALD completed, we test the system to determine the capabilities of the FPGA. Initially, valve timings with the ALD cycle are programmed in seconds. This works well when simulating the outputs of the FPGA in simulation tests; however, since we could not physically see the outputs of the PLC and FPGA turning on and off at speed, we were unsure how the system would respond once switching speed is increased. To test whether the system is operating as desired, we attached an oscilloscope probe to the output of SV1 on the FPGA and a valve position sensor on the corresponding valve on the ALD. This valve is the first valve that is opened during the ALD cycle (as can be seen in Figure2), so measuring its response allows us to determine the cycle time of the ALD by measuring the rising edge to rising edge period of the valve position feedback. The valve position sensor is an on/off switch, and the rising edges are easy to identify in the waveforms.We measure the response time of the ALD valve to determine what is the minimum cycle time the valve can be operated at. Figure11 shows the switching waveform in red (lower peaks) and the valve’s physical response to a switch in blue (larger peaks). As can be seen in Figure 11, once valve timing is at 5-6 ms (Figure 11(b)), the valve can still respond, but at a switching speed of 600 μs, the valve fails to respond (Figure 11(c)). Therefore, to ensure that the system is stable, valve timing on the FPGA is set to 20 ms.Figure 11
Control and response of the valve for decreasing actuation times: valve actuated for (a) 60 ms, (b) 6 ms, and (c) 0.6 ms.
(a)(b)(c)Next, to show what the FPGA controller is capable of compared to a PLC, we reduce the timing of the internal timers within the ALD cycle called “twait1” and “twaitw” first to the minimum time that the PLC can control them, which is 1 ms. The cycle time for the ALD cycle is recorded as the peak-to-peak timing of the rising edge of the valve response, as can be seen in Figure12. The ALD cycle time (a complete control cycle) takes 168 ms when controlled by the PLC.Figure 12
Control and response of the valve when using 1 ms internal timers. Rising and falling edge times are labeled in the bottom of the two timing waveforms.By changing these two internal timers so that they are faster than what the PLC is capable of, we record the ALD cycle time for the FPGA. As shown in Figure13, the internal timers are reduced to 1 μs, which results in a 2 ms reduction in one ALD deposition cycle. For example, a 50 nm copper oxide layer deposited via ALD has an average growth per cycle of ≈0.15 [26], which represents a 3.3 sec reduction per batch. This shows that an FPGA controller (even a simple, cheap one) is able to improve the overall production time a PLC controller can achieve. Note, however, that we are showing these results to demonstrate the capability of an FPGA-based controller and not stating that this would be recommended for the ALD system.Figure 13
Control and response of the valve when using 1μs internal timers. Rising and falling edge times are labeled in the bottom of the two timing waveforms.


## 6. Conclusion

This work demonstrates how an ALD system is controlled with an FPGA prototyping board that replaces the typical PLC. To achieve this, we describe our ALD system, its control requirements, and the tools we have created to automatically convert LD (the design method for PLCs) into Verilog files that can then be synthesized and programmed to an FPGA. The FPGA with electronic conditioning of signals can then be used to replace the existing PLC, and we show that we can match the control signals designed in LD for a PLC to the FPGA. This means that our ALD system can be controlled via this system.Additionally, we show that the potential for using an FPGA instead of PLC systems has the capability to increase the granularity of control. Note that the parallel capabilities and number of pins available on the FPGA mean that these devices have great potential to revolutionize control in manufacturing. This benefit comes at no cost as the traditional design flow used for these devices can be used, and our flow can convert the designs to the FPGA. Additionally, FPGAs are off-the-shelf components that are not overly expensive.The future of the FPGA as a standard device in the control systems is promising; however, FPGAs are difficult to design for, and manufacturing engineers are not trained in their use. We have shown, in two cases, that if LD continues to be the design entry system of choice, then it is not too difficult to build tools to convert these designs to map to an FPGA. The real future of this work is for either a PLC company or a startup to embrace the idea of the FPGA, create a tool flow, and generate prototyping boards and breakout boards with a focus on PLC controlled manufacturing.



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*Source: 8827417-2022-05-06.xml*