# Deadbeat Control of a Modified Single-Phase Five-Level Photovoltaic Inverter with Reduced Number of Switches

Authors: Mohsen Ghorbanali Afjeh; Mojtaba Babaei; Mohsen Alizadeh Bidgoli; Amir Ahmarinejad
Journal: International Journal of Photoenergy
 (2020)

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## Abstract

In this article, a modified single-phase five-level photovoltaic inverter is proposed with a single DC voltage source and six semiconductor switches. Compared with the presented inverters, the introduced topology has the advantage of decreased device count and the first switching frequency for high blocking voltage switches. The proposed PV inverter is implemented without clamping diodes and transformers, which leads to a decrement in size and, consequently, the weight of the converter. In addition, for the proposed topology, space vector pulse width modulation (SVPWM) is deployed that reduces the complexity of multilevel modulation. In order to obtain the optimal output voltage of the inverter, the deadbeat controller is suggested as a rapid dynamic, low-computation digital control method. This closed-loop inverter is implemented in TMS320f28335 digital signal controller to evaluate the performance of the proposed inverter under nonlinear and linear loads. Simulation and laboratory prototype results show that IEC 62040-3 harmonic constraints is met for the proposed photovoltaic inverter in standalone applications.


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## Body

## 1. Introduction

Increased greenhouse gas emissions have led to the development of renewable energy. In recent years, a large number of zero fossil fuel energy buildings were built in the world that uses renewable energy as a source of whole energy. The use of off-grid photovoltaic inverters is preferred at loads that are located far away from the grid. By this method, there will be no need for transmission lines or it can also decrease the network congestion issue such as new transmission line costs. Under these conditions, a hybrid network, consisting of renewable distributed generation resources and the energy storage system, is designed to be responsive to load with high reliability. An inverter converts DC voltage of the photovoltaic system to sinusoidal voltage with constant amplitude and frequency. The inverter must be able to provide the desired voltage quality in a variety of single-phase linear or nonlinear loads. Multilevel inverters (MLI) have an appropriate harmonic spectrum. Currently, multilevel renewable energy inverters have presented to increase efficiency and reduce the space and weight of converters [1].MLI have several advantages over conventional two-level inverters. Some of these advantages include generating the voltage with low harmonic distortion, reducing thedv/dt stress on the semiconductor switches, decreasing switch failure rate, increasing reliability, improving electromagnetic compatibility, and improving common-mode voltage. Besides these, the rated voltage of the switches is less, which reduces the cost of the inverter [2].Less individual and total harmonic distortion in MLI reduces the LC filter size, which diminishes the converter’s weight and transportation costs. Series switches in multilevel inverters increase conductive losses, but collector-emitter voltage is decreased which leads to the reduced inverter switching losses.Therefore, increasing the efficiency of MLI reduces energy consumptions and reduces greenhouse gas emissions. On the other hand, utilizing multilevel converters results in less THD and less switching frequency, which reduces switching losses. Therefore, MLI can use low-frequency semiconductors [3].Different topologies are presented for the five-level inverters, for example, neutral point clamp (NPC), flying capacitor (FC), and cascaded H bridge (CHB) converters, which are known as traditional multilevel topologies [4].Clamping diodes are required in NPC topology, and the blocking voltage on each power switch or diode is equal to a quarter of the total blocking voltage of five-level inverter. The principal advantage of the NPC inverter is the low switching frequency, while its weakness is the uneven distribution of thermal losses in semiconductors. This issue limits the switching frequency of this topology.The active neutral point clamp (ANPC) inverter has been developed as a treatment for NPC problems in power loss distribution, and clamping diodes have been replaced with switches [5].The FC converter has a modular structure. Each switch pair with a capacitor forms a power cell. These inverters have higher voltage levels than other converters, and their disadvantages are the large capacitors and the converter control complexity in balancing the capacitor voltage [6]. The CHB inverter has a rapid dynamic response; furthermore, in a symmetrical type, two or more single-phase H series inverters are connected, which reduces the repairing time and the overhaul costs. The CHB converter has a redundant switching state which increases the fault tolerance [7]. The voltage stress on each switch of this converter is equal to the DC voltage source voltage. The main disadvantage of this topology is its requirement of isolated DC voltage sources, which means more transformers are required. Therefore, in CHB inverters, costs and dimensions are increased [8].MLI have some limitations such as the increased number of power electronic switch, which increases installation space, overall MLI cost, and complexity of the inverter system.According to the above goals, the remainder of the paper is organized as follows. In Section2, the structure and switching vectors of this single-phase five-level reduced device count inverter are introduced. In Section 3, the single-phase SVPWM is presented to be applied to the inverter. Also, the open-loop simulation results of the converter are discussed in this section, and the proposed converter is compared with the presented inverters. In Section 4, the proposed MLI and some of the presented structures are compared in terms of the number of parts such as the number of unidirectional and bidirectional switches, independent DC voltage sources, capacitors, and diode clamps. In Section 5, some predictive control methods are evaluated, and finally, the deadbeat controller is proposed. In Section 6, MATLAB simulations and laboratory prototype results are performed to investigate the performance of the converter under nonlinear and linear loads. Finally, the conclusion and the suggestion are given in Section 7.


## 2. Proposed Topology

The proposed single-phase MLI can be categorized as a combining with some change between full bridges and the active neutral point clamp MLI topology. The topology is represented in Figure1. One semiconductor switch is connected to the middle of the DC link capacitors to create a five-level inverter. The switching states are classified in Table 1. With proper control, the DC voltage of two series capacitors can balance; therefore, this topology does not require two independent DC voltage sources. This converter is called the Γu5L inverter, due to the location of the switches.Figure 1
Proposed five-level inverter drawings.Table 1
Proposed five-level inverter general switching vectors.
S1S2S3S4S5S6VoutVectorC1C2100101-VDCV1--100110-VDC/2V2∗-10100֍00-V3∗∗0101010+V4∗∗010110VDC/2V5-∗01100֍0VDCV6--∗: no effect; -: discharging.According to Table1 except in the case of zero modes, at each level, maximum of three conducts and three changes occurred.Table1 is the general switching mode of the converter. But in the SVPWM method, when switching is happening between V2 and V3 in section C, there is chance of an intermediate unwanted switching state and same thing happens during the switching between V6 and V5 in section A. Therefore, the switching table in the SVPWM method is modified so that only two switches change position in each section. This is done by turning on the S5[֍] in V3 and V6 that do not affect the output voltage.Figure2 shows the inverter operation, including different switching vectors. V1 and V6 vectors discharge C1 and C2 capacitors. V2 discharges C2 capacitor. V5 discharges C1 capacitor. Zero voltage vectors are V4 and V3, and their application has no effect on the voltage of C1 and C2.Figure 2
Γu inverter operation in the following vectors: (a) -VDC/2. (b) -VDC. (c) +VDC/2. (d) +VDC. (e) Positive zero voltage. (f) Negative zero voltage.
(a)(b)(c)(d)(e)(f)


## 3. Modulation Method

Various two-level modulation methods have been entered into MLI. The PWM method is changed into phase shift (PS-PWM) and level shift (LS-PWM) techniques, and in any MLI has many impacts on the voltage balancing in capacitors and THD of the inverters [8].The existence of several carrier waves in the MLI which has also the requirement to apply dead time to prevent short circuit has led to the need for FPGA, which increases the complexity of the converter design.Few works have been published SVPWM algorithm for single-phase MLI, and this method is often used for three-phase inverters [9].A single-phase five-level SVPWM technique is proposed forΓu5L inverter. This technique is recommended for ease of implementation of modulation in DSP and decreases the complexity in the switching time calculation [10].Figure3 illustrates the voltage vectors and four voltage sections determination in Γu5L inverter. Voltage and switching vectors have been shown in Table 1.Figure 3
SVPWM switching mode ofΓu inverter.According to Equation (1), T is the modulation period. T1 and T2 are the duty cycles of the actuated voltage vectors in each section, respectively.
(1)T=T1+T2.Solving these two unknown variables,T1 and T2 require another equation obtained from the following equations in each section.Section A: in this section, amplitude of the inverter reference,Vr, is located between 0.5 VDC and VDC or V5 and V6, respectively. The switching time, T, is divided between these two effective vectors according to Equation (2).
(2)VrT=V6T1+V5T2=VDC2T1+VDCT2,T1=2−2VrVDCT,T2=2VrVDC−1T.Section B: when the inverter reference voltage,Vr, is between 0.5 VDC and zero or V4 and V5, respectively, the switching times are divided between these two effective vectors according to Equation (3), where T1 and T2 are the duty cycles of the zero voltage vector and 0.5 VDC level, respectively.
(3)VrT=V4T1+V5T2=VDC2T2,T1=1−2VrVDCT,T2=2VrVDCT.Section C: when the inverter reference vector,Vr is between -0.5 VDC and zero voltage vector or V4 and V2, respectively. According to Equation (4), T1 and T2 are duty cycles of zero voltage vector and -0.5 VDC level, respectively.
(4)VrT=V4T1+V2T2=−VDC2T2,T1=1+2VrVDCT,T2=−2VrVDCT.Section D: when the amplitude of the inverter reference voltage is between -0.5VDC and -VDC voltages or V1 and V2, respectively, switching times are divided between these two vectors according to Equation (5), where T1 is the duty cycle of -0.5 VDC and T2 is the duty cycle of -VDC level.
(5)VrT=V2T1+V1T2=−VDC2T1−VDCT2,T1=2+2VrVDCT,T2=−2VrVDC+1T.Due to the symmetry of the positive and also negative cycles of the sinusoidal waveform and inverter operation, at linear loads, the voltage ofC1 and C2 capacitors will be almost balanced and there is no need for a voltage sensor or compensator design as shown in Figure 4. However, from experience, the voltage of capacitors can hardly be balanced in practical application due to the nonideal factors of inverter and nonlinear load. By changing the duty cycle of the activated voltage vectors, the voltage can be balanced. Therefore, a proportional integral (pi) compensator and control loop are proposed in Figure 5 for voltage balancing.Figure 4
DC link capacitor voltage range without compensator.Figure 5
DC link capacitor voltage balancing control loop.


## 4. Open-Loop Simulations

Open-loop simulations forΓu inverter in MATLAB software are performed using the space vector pulse width modulation and based on the parameters in Table 2.Table 2
Open- and closed-loop simulation parameters.
ParametersCarrier frequency20 kHzFrequency60 HzLoad resistance80 ΩDC link voltage180 VFilter inductance (L)5 mHFilter capacitors (C)4.3μFDead time2μsDC link capacitors2200μFModulation index open-loop test0.8642Figure6 shows the five-level voltage waveform of the proposed converter.Figure 6
Output voltage waveform of proposed inverter without LC filter.Figure7 shows the filtered voltage waveform and the output current of the converter. The simulations demonstrate that the voltage total harmonic distortion is 1.25%.Figure 7
Output voltage and current waveform with LC filter.Figure8 depicts the gate switching signals. In this figure, the switching frequency of S1, S2 switches is 60 Hz, and in the S5, S6, average switching frequency is 14670 Hz and average switching frequency of S3, S4 is 16680 Hz. The S1, S2 switches are switching in fundamental frequency. Reducing the switching frequency is improving the converter efficiency, so low-switching semiconductors such as IGBTs or GTOs are applicable for this segment, but in the S3-S6, high-frequency switches like MOSFETs can be used.Figure 8
S1-S6 switching gate signals.As shown in Figure4, the voltage ripple of the capacitors is reasonable, and this voltage is stabilized without any compensation in open-loop simulation.Criteria such as the number of switches, independent DC voltage sources, capacitor clamps, and diode clamps about device counts are definable [11]. Furthermore, breakdown voltages of the switches, switching frequency, and converter controllability are determinable. According to Table 3, the Γu5L inverter has the advantage of implements with a single DC source and without transformer and clamping diodes. Therefore, this topology is a suitable MLI with the advantage of reducing device counts.Table 3
Comparison between the proposed topology and some of the presented structures.
Five-level MLIDC sourcesSwitch×breakdown voltagePrice[12]2×VDC/24×VDC/2, 4×VDC8×SW+2×SD[13]1×VDC4×VDC/2, 2×VDC6×SW+DI+2×C+SD[14]4 × (VDC/2)8×VDC/28×SW+4×SD[15]2×VDC/21×VDC/2, 4×VDC5×SW+4×DI+2×SD[16]1×VDC2×VDC/2, 4×VDC6×SW+2×DI+2×C+SD[17]2×VDC/22×VDC/2, 4×VDC6×SW+2×SD[18]1×VDC2×VDC/2, 4×VDC6×SW+2×C+SD[19]1×VDC8×VDC/28×SW+4×DI+2×C+SDNPC4×VDC/22×2VDC, 2×1.5VDC, 2×VDC, 2×VDC/28×SW+6×DI+4×SDFC2×VDC2×2VDC,2×1.5VDC, 2×VDC, 2×VDC/28×SW+3×C+2×SDCHB2×VDC/28×VDC/28×SW+2×SDProposed1×VDC3×VDC/2, 3×VDC6×SW+2×C+SDSW: price of an IGBTswitch+gatedriver; SD: price of DC sources; DI: price of a diode; C: price of a capacitor.NPC, FC, and CHB require several isolated DC voltage sources and transformers, which have increased their cost and mass compared toΓu inverter [12, 14, 17].Inverter [18] has four high breakdown voltage switches, but the Γu5L inverter has three switches, which means more switch prices and according to the equal number of commutations means higher switching losses.The bidirectional switches have different varieties; some of which are shown in Figure9. In comparison, DE_IGBT has the highest conduction losses between all types of bidirectional switches. Although the topology [15] has a five IGBT but due to the presence of DE_IGBT, this structure has four more diodes and more losses. The CC_IGBT is implemented with two unidirectional switches, and it requires two gate drivers.Figure 9
Bidirectional switches: (a) DE_IGBT: diode-embedded IGBT; (b) CC_IGBT: common collector; (c) CE_IGBT: common emitter.
(a)(b)(c)Fault detection in MLI is an important and complex issue. Industrial gate drivers require a collector-emitter voltage sample. When the IGBT is in an overcurrent condition, the DESAT (VCE) exceeds an internal reference voltage; in this time, gate driver applies soft turn off, so isolated pulse generators as gate drivers do not have DESAT protection; because of this, in T5MLC [14] and T-type [18]topologies, two gate drivers with error detection capability are considered for each CC_IGBT or CE_IGBT bidirectional switch.Classic five-level inverters NPC, FC, and CHB have eight high-frequency switches with maximum of four switch conductions in each level that increase the cost and conduction losses. According to Table4, the proposed topology has four high-frequency switches. In comparison with conventional five-level structures, the proposed topology has two low-frequency switches, which reduce the switching loss of MLI . At each level, maximum of three conducts and three changes occurred. Regarding a smaller number of conduction and commutation, conduction and switching losses decreased.Table 4
Comparison betweenΓu inverter and some of topologies.
Five-level MLIMaximum conduction lossesSwitch type[12]4×SW4×L4×H[13]4×SW4×L2×H[14]2×SW—8×H[15]2×SW+2×DI2×L3×H[16]3×SW+DI4×L2×H[17]3×SW2×L4×H[18]3×SW2×L4×H[19]4×SW—8×HNPC4×SW—8×HFC4×SW—8×HCHB4×SW—8×HProposed3×SW2×L4×HL: low-frequency switch; H: high-frequency switch.Because of fundamental switching frequency for high blocking voltage switches leg and reducing switching losses due to the three-level structure on the other leg, the efficiency of this converter is higher than the conventional two-level inverters. According to the test conditions in [17], simulations of losses have been performed and comparison of losses is shown in Table 5.Table 5
Comparison between losses.
Five-level MLISwitching loss (w)Conduction loss (w)Total loss (w)Unipolar16.927.144[15]10.73646.7[16]6.54248.5[17]6.435.742.1Proposed9.132.441.5


## 5. Proposed Control Method forΓu Inverter

In inverters, due to the nonlinear current passing through the LC filter and applying dead time during switching, the waveform becomes nonsinusoidal. The task of removing the high-frequency harmonics is the responsibility of the LC filter and controlling the low-voltage harmonics of the compensator. The filter inductor is calculated as follows:(6)L=VDC4fS×ΔIlp−p,whereΔIlp−p is the peak-to-peak inductor current and fS is the switching frequency. The capacitor is also designed to have a cut-off frequency at least ten times smaller than the inverter switching frequency. The filter capacitor is calculated as follows:
(7)fC=12πLC.Deadbeat (DB) has a rapid dynamic, low-computation digital control method based on a discrete-time model of the system. The deadbeat is a stabilize closed-loop system. The positioning of the poles is located at the center of thez plane and within the unit circle [20]. The inverter state-space model is determined based on LC filter parameters and inductor current and capacitor voltage. The load current is considered as a disturbance. The values of matrices A, B, and D are as follows:
(8)ddtILVo=AILVo+BVi+DIo,A=0−1L1C0,B=1L0,D=0−1C.The KVL and KCL equations for the converter are as follows:(9)KCL⇒Ic=Cdvodt=IL−Io,KVL⇒Vi=LdILdt+Vo⇒LdILdt=Vi−Vo.According to the sampling time (Ts) in Equation (9), discrete time derivative is as follows.
(10)ILz+1−ILzTs=1LViz−Voz,Voz+1−VozTs=1CILz−Ioz.The state variables at timez+1 are as follows:
(11)ILz+1=ILz+1LfsViz−Voz,Voz+1=Voz+1CfsILz−Ioz=Voz+1CfsIcz.The state variables in the next sampling timez+2 are as follows:
(12)ILz+2−ILz+1=1LfsViz+1−Voz+1,Voz+2−Voz+1=1CfsIcz+1.If the high sampling frequency is selected, the voltage and current changes can be considered linear and can be written as follows:(13)ILz+1−ILz=1LfsViz+1−Voz+1,Voz+1−Voz=1CfsIcz+1.In the DB method, the values ofz+1 are the same as the reference values, so the reference values of the output voltage and the reference capacitors and inductor currents at time Z can be written as follows:
(14)Vi∗z=Vo∗z+LfsIL∗z−ILz,IL∗z=Ioz+CfsVo∗z−Voz.Compared to the model predictive control MPC method, DB has two advantages of reducing compute volume and constant switching frequency. The MPC method requires the calculation of the cost function and the selection of the optimal vectors, so in this method, the switching frequency is variable. However, in the DB method, the computation volume is low, and the inverter reference voltage is generated by the modulator. Hence, the switching frequency is constant, and the modulator also makes the LC filter easier to design.


## 6. Closed-Loop Simulation and Experimental Results

The compensator must stabilize the amplitude of the main component of the voltage in all conditions and provide the required current for linear and nonlinear loads.The closed-loopΓu5L inverter is implemented based on the parameters in Table 2.The prototype is illustrated in Figure10, which achieved a closed-loop system according to Figure 11, using a TMS320F28335 floating-point TI DSP and LUH100G1202 IGBT modules. The Hantek 6022BE PC-Based USB Digital Oscilloscope and Chauvin Arnoux C.A 8220 power analyser are used to sample the prototype’s voltage, current, and total harmonic distortion waveforms.Figure 10
Γu converter prototype.Figure 11
DC link capacitor voltage and deadbeat compensator.The response of the inverterΓu5L is investigated by applying the linear and nonlinear loads.


### 6.1. Linear Load Closed-Loop Simulation and Experimental Results

The simulation and the experimental results of the linear resistive load for theΓu5L inverter are illustrated in Figure 12 and Figure 13, and laboratory prototype results confirm the simulation results.Figure 12
Linear load simulation result.VDC=180, VAC=110, and THDv=0.5%.Figure 13
Linear load experimental result.The closed-loop voltage FFT of theΓu inverter before the LC filter is illustrated in Figure 14, which shows the proper design of the DB controller and the LC filter. The LC filter is responsible for removing high-frequency harmonics, and the compensator is responsible for controlling low-frequency harmonics. The filter reduces the voltage total harmonic distortion from 38.27% to 0.5% to comply with IEC 62040-3.Figure 14
The closed-loop voltage FFT before filter.In order to investigate the linear inductive loads, the RL load simulation is performed as follows: the voltage and current waveform is as Figure15.Figure 15
RL load simulation result.VDC=180, VAC=110.1, THDv=0.6%, R=80Ω, and L=10mH.


### 6.2. Nonlinear Load Closed-Loop Simulation and Experimental Results

According to IEC620-40-3, the nonlinear load parameters can be defined as follows in Figure16:Figure 16
Nonlinear load test.RL=272Ω, CS=458μF, and RS=4.8Ω.The simulation and the experimental results for the nonlinear load are represented in Figures17–19, and laboratory prototype results confirm the simulation results.Figure 17
Nonlinear load simulation results.VDC=180, VAC=110, and THDv=2.6%.Figure 18
DC link capacitor voltage in nonlinear load.Figure 19
Nonlinear load experimental results.The THD value calculated before the LC filter is 45% for nonlinear load and 38.2% for linear load using MATLAB FFT analysis. The comparison between standard limit and individual harmonic value of theΓu5L inverter at the nonlinear load in laboratory prototype test is shown in Table 6. According to Figure 20, voltage total harmonic distortion less than 0.6% at linear load and voltage total harmonic distortion less than 2.6% at nonlinear load indicate compliance with IEC620-40-3 [21].Table 6
Standard limit and individual harmonic ofΓu inverter.
Even harmonicOdd harmonicHarmonic orderIEC62040-3%Γu inverter %Harmonic orderIEC62040-3%Γu inverter %220.11350.66410.2456160.50.14751.0280.50.1291.50.71100.20.09113.50.38120.20.051330.12140.20.09150.30.14160.20.041720.11180.20.06191.50.09200.20.03210.20.05220.20.03231.50.06240.20.03251.50.03Figure 20
Experimental THD in linear load (a) and nonlinear load (b).
(a)(b)


## 6.1. Linear Load Closed-Loop Simulation and Experimental Results

The simulation and the experimental results of the linear resistive load for theΓu5L inverter are illustrated in Figure 12 and Figure 13, and laboratory prototype results confirm the simulation results.Figure 12
Linear load simulation result.VDC=180, VAC=110, and THDv=0.5%.Figure 13
Linear load experimental result.The closed-loop voltage FFT of theΓu inverter before the LC filter is illustrated in Figure 14, which shows the proper design of the DB controller and the LC filter. The LC filter is responsible for removing high-frequency harmonics, and the compensator is responsible for controlling low-frequency harmonics. The filter reduces the voltage total harmonic distortion from 38.27% to 0.5% to comply with IEC 62040-3.Figure 14
The closed-loop voltage FFT before filter.In order to investigate the linear inductive loads, the RL load simulation is performed as follows: the voltage and current waveform is as Figure15.Figure 15
RL load simulation result.VDC=180, VAC=110.1, THDv=0.6%, R=80Ω, and L=10mH.


## 6.2. Nonlinear Load Closed-Loop Simulation and Experimental Results

According to IEC620-40-3, the nonlinear load parameters can be defined as follows in Figure16:Figure 16
Nonlinear load test.RL=272Ω, CS=458μF, and RS=4.8Ω.The simulation and the experimental results for the nonlinear load are represented in Figures17–19, and laboratory prototype results confirm the simulation results.Figure 17
Nonlinear load simulation results.VDC=180, VAC=110, and THDv=2.6%.Figure 18
DC link capacitor voltage in nonlinear load.Figure 19
Nonlinear load experimental results.The THD value calculated before the LC filter is 45% for nonlinear load and 38.2% for linear load using MATLAB FFT analysis. The comparison between standard limit and individual harmonic value of theΓu5L inverter at the nonlinear load in laboratory prototype test is shown in Table 6. According to Figure 20, voltage total harmonic distortion less than 0.6% at linear load and voltage total harmonic distortion less than 2.6% at nonlinear load indicate compliance with IEC620-40-3 [21].Table 6
Standard limit and individual harmonic ofΓu inverter.
Even harmonicOdd harmonicHarmonic orderIEC62040-3%Γu inverter %Harmonic orderIEC62040-3%Γu inverter %220.11350.66410.2456160.50.14751.0280.50.1291.50.71100.20.09113.50.38120.20.051330.12140.20.09150.30.14160.20.041720.11180.20.06191.50.09200.20.03210.20.05220.20.03231.50.06240.20.03251.50.03Figure 20
Experimental THD in linear load (a) and nonlinear load (b).
(a)(b)


## 7. Conclusion

In this paper, the following works have been done and new results have been obtained, which are as follows:(1)
Γu inverter is proposed that has less devices with a single DC voltage source and does not require clamping diodes. This transformerless structure reduces the installation space and weight. Also, this converter has self-balanced capacitor voltage property under linear loads. Results show that the efficiency of this converter is higher than the conventional five-level and two-level inverters(2)
Single-phase five-level space vector pulse width modulation forΓu5L inverter was proposed. This technique reduces the complexity of modulation implementation(3)
According to the proposed balancing method, there is no need for two independent sources, and the structure can be controlled with two bulk capacitors(4)
Two predictive control methods are analysed forΓu5L inverter, and a rapid dynamic, low-computation cost digital control method with SVPWM modulator, and constant switching frequency was proposed for closed-loop control(5)
The performance of the proposed converter under nonlinear and linear loads was confirmed by performing an analytical study, including simulation and an experimental result(6)
According to test results, it was shown that voltage total harmonic distortion becomes less than 1% at linear load and voltage total harmonic distortion is less than 3% at nonlinear load, which indicates compliance with the sensitive critical loads standard in standalone photovoltaic inverters



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