# Enhanced Device and Circuit-Level Performance Benchmarking of Graphene Nanoribbon Field-Effect Transistor against a Nano-MOSFET with Interconnects

Authors: Huei Chaeng Chin; Cheng Siong Lim; Weng Soon Wong; Kumeresan A. Danapalasingam; Vijay K. Arora; Michael Loong Peng Tan
Journal: Journal of Nanomaterials
 (2014)

---

## Abstract

Comparative benchmarking of a graphene nanoribbon field-effect transistor (GNRFET) and a nanoscale metal-oxide-semiconductor field-effect transistor (nano-MOSFET) for applications in ultralarge-scale integration (ULSI) is reported. GNRFET is found to be distinctly superior in the circuit-level architecture. The remarkable transport properties of GNR propel it into an alternative technology to circumvent the limitations imposed by the silicon-based electronics. Budding GNRFET, using the circuit-level modeling software SPICE, exhibits enriched performance for digital logic gates in 16 nm process technology. The assessment of these performance metrics includes energy-delay product (EDP) and power-delay product (PDP) of inverter and NOR and NAND gates, forming the building blocks for ULSI. The evaluation of EDP and PDP is carried out for an interconnect length that ranges up to 100μm. An analysis, based on the drain and gate current-voltage (Id-Vd and Id-Vg), for subthreshold swing (SS), drain-induced barrier lowering (DIBL), and current on/off ratio for circuit implementation is given. GNRFET can overcome the short-channel effects that are prevalent in sub-100 nm Si MOSFET. GNRFET provides reduced EDP and PDP one order of magnitude that is lower than that of a MOSFET. Even though the GNRFET is energy efficient, the circuit performance of the device is limited by the interconnect capacitances.


---

## Body

## 1. Introduction

The number of transistors on a typical 1 × 1 cm chip has grown exponentially with twofold increase every 18 months keeping Moore’s Law [1] on track. Serious hindrances are in sight as transistor scaling enters the nanometer domain. Short-channel effects are significant as devices are scaled below sub-100 nm, providing challenges and opportunities for device and process engineers. Researchers across the globe are exploring new nanomaterials with transformed architecture to circumvent the roadblocks of silicon-based nanotechnology for enhanced circuit performance. Interconnects also play a key role as channels reach nanometer scale and resistance surge takes on an increasing importance [2]. Carbon-based allotropes offer a distinct advantage in a variety of applications [3–8]. Graphene nanoribbons (GNRs) are one-dimensional (1D) nanostructures restricting carrier motion in only one direction, reducing scattering for enhanced mobility [6, 9]. The transistor current is quite high as electrons are injected from the source and transit to the drain terminal [6, 10–12]. A narrow width semiconducting GNR is utilized as a channel in a top-gated transistor [13–15]. This pushes the limits of complementary metal-oxide-semiconductor (CMOS) type of technology beyond its limits in a GNR. This paper focuses on modeling, simulation, and benchmarking of top-gated graphene nanoribbon field-effect transistors (GNRFETs) against MOSFET. In addition, the evaluation of logic performance is carried out for both devices. It is observed that there is a good agreement between GNRFET and MOSFET based on the drain current-voltage (I-V) characteristics. The energy-delay product (EDP) and power-delay product (PDP) are the performance metrics that represent the energy efficiencies of GNRFET and MOSFET logic gates. The simulations in this work are carried out for the 16 nm manufacturing processes. In the following, device model framework of our previous work [7, 16–19] is extended for the simulation and analysis of GNRFET and MOSFET at 16 nm node. Circuit-level models of GNRFET are benchmarked against MOSFET. Logic performances of carbon and silicon-based inverter and NAND and NOR gates are assessed. For a fair assessment, the same channel length, L=16 nm, is adopted for GNRFET, PMOS, and NMOS. The device modeling is carried out in MATLAB and circuit development and simulation is performed using HSPICE and Cosmoscope.


## 2. Device Modeling

The simulated silicon MOSFET is based on Berkeley short-channel IGFET model (BSIM) which was the standard model for deep submicron CMOS circuit design in the early 2000s [20]. IC companies including Intel, IBM, AMD, National Semiconductor, and Samsung widely use the charge-based model as an electronic computer-aided design (ECAD) tool. BSIM4 version 4.7 MOSFET model is utilized in the simulation of NMOS and PMOS [21] in the present assessment. The top view of GNRFET with source and drain contacts is depicted in Figure 1. Various values of C and S (see Figure 2) are given in Table 1.Table 1
Design specificationsC and S for various channel lengths.
Channel length (nm)
C (nm)
S (nm)
W (nm)
16
30
8
46
32
50
16
82
45
60
20
100
65
90
40
170
90
120
50
220
180
220
100
420Figure 1
Top view of GNRFET device structure with contact and channel design layout architecture.Interpolation of (a) contact and (b) spacer sizes.
(a)
(b)


## 3. Proposed Layout and Design

The interpolated contact sizeC and spacer size S of 16 nm node process technology are illustrated in Figures 2(a) and 2(b), respectively.The channel width,W, is a function of C and S as given by
(1)W=C+2S.Table1 gives design specifications for channel lengths from 16 to 180 nm range.


## 4. Analytical Modeling of GNRFET

In this section, the analytical model of GNRFET is derived. The channel surface potentialVSC, or self-consistent voltage as is commonly known, is solved numerically in MATLAB using Newton-Raphson algorithm to obtain the voltage potential at the top barrier along the channel [23]. The VSC is given by
(2)VSC=VL+Vp=-Qt+ΔQCΣ,
where CΣ is the total sum of capacitance at all the four terminals and Qt is the total charge. ΔQ is the additional charge due to the increase of VSC. VL is the potential appearing across the channel region and VP is existing across the parasitic regions. The other symbols in (2) are given as follows where Ns is the density of positive velocity states, Nd is the density of negative velocity states and N0 is the electron density at equilibrium:
(3)Qt=CsVs+CgVg+CdVd+CsubVsub,CΣ=Cs+Cg+Cd+Csub,ΔQ=q(Ns+Nd+N0).
The carriers obey the Fermi-Dirac probability distribution as follows:
(4)Ns=12∫-∞+∞D(E)f(E-USF)dE,Nd=12∫-∞+∞D(E)f(E-UDF)dE,N0=∫-∞+∞D(E)f(E-EF)dE,
where USF and UDF are defined as
(5)USF=EF-qVSC,UDF=EF-qVSC-qVd.
The one-dimensional (1D) density of state (DOS) function in (4) is defined as
(6)D(E)=2gvgs3πacct∑iEE2-(EG/2)2,
where acc=0.142 nm is the C–C bond length and t=3 eV is the C–C bonding energy. In (6), EG is the bandgap energy, gs is the spin degeneracy, and gv is the valley degeneracy. In an armchair GNR (aGNR), gv=1. A nonlinear regression model of VSC is obtained through the use of the polynomial fit [24, 25]. The nonlinear approximation for VSC dependence on Vd and Vg in the form of fifth-order polynomial is given to replace the Newton-Raphson algorithm in (2). The regression model is given as
(7)VSC(Vg,Vd)=AVd+BVg5+CVg4+DVg3+EVg2+FVg+G,
where A, B, C, D, E, F, and G are the coefficients extracted from MATLAB curve fitting tool.The coefficientsA to G in Table 2 are empirical parameters used for curve fitting (2).Table 2
Values for the coefficientsA to G.
Coefficient
Value
A
−3.5000 × 10−2
B
1.0737 × 10−3
C
−2.7542 × 10−3
D
2.3754 × 10−3
E
−6.3691 × 10−4
F
−8.8009 × 10−1
G
−3.5738 × 10−4HSPICE utilizes (8) to simulate the drain and gate I-V characteristic of GNRFET and MOSFET. The noniterative model allows cross-platform simulation, shorter execution time, and reduced computational cost [26]. In GNRFET, when gate and drain voltages are applied, VSC is reduced by VL. This would result in a flow of electron in the channel that increases VSC by VP due to introduction of the additional charges [27]. In the Id-Vd simulation of GNRFET, the Id-Vd equation can be written in Vd, Vs and Vg coefficients as given by
(8)Id(Vg,Vd,Vs)=GONkBTq[log⁡(1+exp⁡(q(EF-VSC(Vg,Vd,Vs))kBT))]…-GONkBTq×[log⁡(1+exp⁡(q(EF-VSC(Vg,Vd,Vs)-Vd-Vs)kBT))],
where GON is the on-conductance.


## 5. Device Simulation

The device performance of GNRFET and MOSFET are compared by evaluating their respectiveId-Vd characteristic as shown in Figure 3. The output response of p-type and n-type MOSFETs is superimposed for comparison purposes. Also, the Id-Vd characteristics of p-type and n-type GNRFETs are symmetrical as in a CMOS and thus coincide with each other. Figure 4 illustrated the Id-Vg transfer characteristic of n-type and p-type MOSFET and GNRFET. DIBL and SS are calculated from the Id-Vg curve and are given as(9)DIBL=∂VT∂Vd,SS=∂Vg∂(log10Id).
The range of the DIBL measurement is taken between |Vd|=0.1 V and |Vd|=1 V and the SS measurement is for the drain current curve at |Vd|=0.1 V. As deduced from Figure 3, GNRFET has a lower linear on-conductance compared to MOSFET. In addition, GNRFET achieves higher saturation current values than those of MOSFET for most gate voltages.Figure 3
I
d
-
V
d characteristics n-type GNRFET, p-type, and n-type MOSFET for various gate voltages starting from Vg=1 V at the top in 0.1 V decrement.I
d
-
V
g transfer characteristic of n-type and p-type (a) MOSFET and symmetrical n-type and p-type (b) GNRFET FET for |Vd|=0.1 V and |Vd|=1 V.
(a)
(b)As listed in Table3, the DIBL of MOSFET is better than GNRFET. The subthreshold swing (SS) of both devices is comparable. The Ion⁡/Ioff⁡ ratio of GNRFET is two-order magnitude lower than that of MOSFET. This is due to a lower linear on-conductance limit of a ballistic GNRFET. The on-conductance limit, GON, with zero contact resistance is given by
(10)GON=2q2h,
where q is the electronic charge and h is Planck’s constant. The simulation is carried out using a high gate dielectric constant (high-k) with high thermal stability. In a practical microfabrication, zirconium dioxide which has high-k values between 20 and 25 is considered [28].Table 3
Device parameters and performance metrics of GNRFET, n-type, and p-type MOSFET.
Parameter
GNRFET
n-type MOSFET
p-type MOSFET
Electrical gate oxide thickness (nm)
2.0
1.0
1.6
Gate dielectric constant relative to vacuum
25
25
25
Subthreshold swing (mV/decade)
70.1704
61.7527
70.7253
Drain-induced barrier lowering (mV/V)
40.7448
35.2515
36.6697
On/off ratio, (Ion⁡/Ioff⁡)
3.42 × 104
1.25 × 106
6.9868 × 105Note that different values of oxide thickness are being used to obtain almost symmetricalI-V characteristics for both p-type and n-type MOSFET, namely, in the linear region. It is found that when all the transistors adopt equal oxide thickness, the maximum current at Vd=1 V and Vg=1 V differs from one another. The output waveform will not have uniform square wave anymore. The propagation delay, rise time, and fall time will be significantly affected. Thus, they are no longer suitable for logic application due to the mismatch of the p-type and n-type Id-Vd curves at the voltage transfer characteristics.


## 6. Circuit Design

In this Section, circuit simulation is considered. As part of the circuit design process, parasitic capacitance, namely, load capacitanceCL is determined for an accurate circuit representation. The top diagram in Figure 5 shows a typical arrangement of two inverters in series with CL. The components of CL are gate-drain capacitance Cgd1, Cgd2, drain-bulk capacitance Cdb1, Cdb2, and wire capacitance CW as depicted in the bottom diagram of Figure 5. Note that the term wire capacitance is used interchangeably with interconnect capacitance. Table 4 lists the local, intermediate, and global copper and GNRFET interconnect capacitances for 32 nm, 22 nm, and 14 nm technology process. The finite element method (FEM) charts the pathways in obtaining capacitances as in [29]. The interconnects used in the simulation are considered to be in the intermediate layer [30] and vary from 1 μm to 100 μm in length [31]. It is found that for 0.18 μm technology, average interconnect lengths are considered to be 7 μm per fan-out [31]. These interconnect specifications from ITRS 2005 are shown in Table 4.Table 4
ITRS 2005 based simulation parameters (adapted from [22]).
Technology process (nm)
32
22
14
Local and intermediate
WidthW (nm)
32
22
14
ILD thicknesstox (nm)
54.40
39.60
25.20
Ccu (pF/m)
144.93
131.01
111.83
Cgnrfet (pF/m)
130.15
117.70
100.51
Global
WidthW (nm)
48
32
21
ILD thicknesstox (nm)
110.40
76.80
52.50
Ccu (pF/m)
179.78
163.30
139.30
Cgnrfet (pF/m)
163.81
148.90
126.78Figure 5
Two-cascaded inverter gate with parasitic capacitance.Table5 shows the extrapolated interconnect capacitances for the 90 nm, 65 nm, 45 nm, and 16 nm process technologies. The capacitance values of copper and metallic GNR are extrapolated from Figure 6 using a linear function based on the intermediate capacitance in Table 4.Table 5
Interconnect capacitances for 16, 45, 65, and 90 nm nodes.
Capacitance
Technology process (nm)
90
65
45
16
C
cu    (pF/m)
252.32
206.60
170.03
116.99
C
gnr   (pF/m)
226.87
185.70
152.76
105.01Extrapolation of interconnect capacitance for copper and GNR.
(a)
(b)Table6 contains the relevant equations for the load and output capacitance for the logic gates.Table 6
Load and output capacitance for logic gates NOT, two-input NAND, two-input NOR, three-input NAND, and three-input NOR.
Gate logic
Capacitance
NOT
C
L
=
C
gd1
+
C
gd2
+
C
db1
+
C
db2
+
C
W
Two-input NAND
C
1
=
C
db1
+
C
sb2
+
C
gd1
+
C
gs2
Two-input NOR
C
L
=
C
db2
+
C
db3
+
C
db4
+
C
gd2
+
C
gd3
+
C
gd4
+
C
W
Three-input NAND
C
1
=
C
db1
+
C
sb2
+
C
gd1
+
C
gs2
Three-input NOR
C
2
=
C
db2
+
C
sb3
+
C
gd2
+
C
gs3
C
L
=
C
db3
+
C
db4
+
C
db5
+
C
db6
+
C
gd3
+
C
gd4
+
C
gd5
+
C
gd6
+
C
W


## 7. Performance Analysis of Digital Circuit

HSPICE is used to simulate the logic operations of GNRFET and MOSFET. The schematic diagram and input-output waveforms of GNRFET and MOSFET NOT, two-input NAND (NAND2), two-input NOR (NOR2), three-input NAND (NAND3), and three-input NOR (NOR3) gates are delineated in Figures7, 8, 9, 10, and 11, respectively. All the logic gates consist of 1 μm copper interconnects at the output terminals. In the simulation, the maximum fan-in for a gate is limited to 3. Correct logical operations are confirmed from the simulation results as shown in the input-output waveforms. Voltage spikes observed are found to be negligible in the output waveform of MOSFET in Figures 7(b)–11(b). The circuit inductance possibly causes spikes that are possible to be compensated by incorporating an on-chip decoupling capacitor at the output in parallel. Note that Figures 7–11 are important to calculate the propagation delay which is computed between 50% of the input rising to the 50% of the output rising. Together with the average power consumption, the metric performance of logic gates in term of EDP and PDP is obtained. PDP and EDP parameters are the figure of merit for logic devices. PDP and EDP are given by
(11)PDP=Pav×tp,EDP=PDP×tp,
where Pav is the average power and tp is the propagation delay. Table 7 lists the Pav and tp for various logic gates as obtained from the simulation. The PDP and EDP for GNRFET are an order of lower magnitude compared to MOSFET due to smaller tp and its ultralow Pav during logic operation as revealed in Table 7. GNRFET power consumption is by at least 1 order of magnitude lower than that of a MOSFET.Table 7
Propagation delay and average power consumption of GNRFET and MOSFET withL = 16 nm and 1 µm interconnect for various logic gates.
Logic gates
Propagation delay,tp (ps)
Average power,Pav (nJ/s)
GNRFET
MOSFET
GNRFET
MOSFET
Inverter
4.825
14.02
2.90
96.11
Two-input NAND
7.059
44.90
3.13
124.04
Three-input NAND
9.555
58.82
3.24
270.18
Two-input NOR
7.059
44.95
3.07
122.12
Three-input NOR
9.589
58.19
3.24
286.58(a) Schematic of NOT gate. (b) Input and output waveforms for GNRFET and MOSFET with 1μm interconnect.
(a)
(b)(a) Schematic of NAND2 gate. (b) Input and output waveforms for GNRFET and (b) MOSFET with 1μm interconnect.
(a)
(b)(a) Schematic of NOR2 gate. (b) Input and output waveforms for GNRFET and (b) MOSFET with 1μm interconnect.
(a)
(b)(a) Schematic of NAND3 gate. (b) Input and output waveforms for GNRFET and (b) MOSFET with 1μm interconnect.
(a)
(b)(a) Schematic of NOR3 gate. (b) Input and output waveforms for GNRFET and (b) MOSFET with 1μm interconnect.
(a)
(b)Figure12 depicts the layout for GNRFET NOR2 schematic shown in Figure 9(a). In the top-gated design, the GNR is placed under the metal gate and thus hidden from the view. The Vg is supplied to the device through terminals A and B. The vertical-interconnect-access (via) as labeled in Figure 12 allows a conductive connection between different layers. To realize the number of p-type and n-type transistors as given in Figure 9(a), three and four electrode contacts, respectively, are implemented in the layout. While the series configuration of the p-type transistors requires only three electrode contacts, and four electrode contacts are needed for the n-type transistors connected in parallel.Figure 12
Proposed layout of GNRFET NOR2 gate with metal contacts and interconnects.The Fermi velocity in a GNRFET is distinctly higher than that in a heavily doped MOSFET. Obviously, degenerate statistics is applicable in heavily doped channels. The intrinsic velocity for a nondegenerate low-doping level is limited to the thermal velocity which is lower than the Fermi velocity in heavily doped semiconductors. The device modeling of GNR adopts similar modeling framework in [17] where we have modified the density of states and quantum conductance limit of a ballistic SWCNT to GNR. The maximum drain current for a monolayer GNRFET is found to be at 19 μA. For CNTFET, the maximum drain current is at 46 μA. Nevertheless, both low dimensional carbon devices outperform silicon MOSFET in term of power-delay-product (PDP) and energy-delay-product (EDP) by at least one order of magnitude.Figure13 depicts the GNRFET PDP and EDP, respectively, for 0–100 μm copper interconnects in length for various logic gates. Figure 14 shows the MOSFET PDP and EDP, respectively, for 0–100 μm copper interconnect in length for various logic gates. The logic gates with high fan-in exhibit increased EDP and PDP as exhibited by these plots. The cutoff frequency at which the current gain is 1 is used to describe the high-frequency performance of a transistor. The current unity gain cutoff frequency of the intrinsic transistor [32, 33] with interconnect capacitance is given by
(12)fT=12πgmCg+CL+Csub,
where Cg is the gate capacitance, CL is the load capacitance, and Csub is the substrate capacitance. Devices with thicker substrate insulator (for instances, 500 nm) and smaller contact area have higher unity cutoff frequency. The unity current gain cutoff frequency for GNRFET circuit model is depicted in Figure 15. The model uses a copper interconnect of the 16 nm, 45 nm, 65 nm, 9 and 0 nm nodes technology. The simulation shows that a 16 nm GNRFET can deliver a unity cutoff frequency of 400 GHz. The interconnect length varies from 0.01 μm to 100 μm. It is found that cutoff frequency is inversely proportional to interconnect length. When the interconnects are longer than 10 μm, the frequency remains the same regardless of the technology nodes. Therefore, it is essential to utilize interconnects as short as possible to tap the high-frequency capability of the CNTFETs [17] and GNRFETs. Our finding is consistent with the state-of-the-art graphene transistors that have been shown to reach operating frequencies up to 300 GHz experimentally [34].(a) PDP and (b) EDP of GNRFET logic gates for copper interconnect length from 0 to 100μm.
(a)
(b)(a) PDP and (b) EDP of MOSFET logic gates for copper interconnect length from 0 to 100μm.
(a)
(b)Figure 15
Unity cutoff frequency for GNRFET based on 16 nm, 45 nm, 65 nm, and 90 nm process technology.


## 8. Conclusions

Complementary CMOS based onn-type and p-type MOSFETs has been at the center stage in industrial environments because of low power consumption. A CMOS circuit draws power from the source only when an inverter is switching from low to high or vice versa. A CMOS inverter is a building block for other gates to build a complete ultralarge-scale-integrated (ULSI) ensemble. After the 2010 Nobel Prize awarded to graphene, graphene allotropes have overwhelmed the center stage to capture the advantage ofMore than Moore’s Era. In fact, Arora and Bhattacharyya [35] show that CNT band structure can be drawn from that of graphene nanolayer with rollover in various chirality directions. GNR [36] offers similar endless opportunities. Considering these noteworthy developments, we believe that graphene allotropes offer distinct advantage over and above the CMOS architecture for a variety of applications in creating sensors, actuators, and transistors for implementation in the ULSI. As graphene allotropes bring to focus the advanced applications, we consider GNR as an example to demonstrate its superiority over the CMOS. Primary reason why graphene is superior to silicon is its intrinsic velocity. The drift in graphene is limited to the Fermi velocity vF≈106 m/s that is 10 times than that of a silicon (vi≈105 m/s). Saturation velocity limited to the intrinsic velocity vi determines the high-frequency cutoff of a ULSI circuit. That is the reason that graphene-based electronics will offer unique advantage in high-frequency circuit design. As current saturates, the power in a ULSI circuit is governed by P=VIsat⁡ and hence becomes a linear function of voltage, in direct contrast to square law dictated by Ohm’s law. The power consumption will be much lower in a graphene circuit affording the opportunity to lower the scale of the voltage source. Power-frequency product is a figure of merit in ULSI applications. The paper shows distinct advantages of graphene-based integration in ULSI circuits in designing various Boolean gates. The comparative study stretches the landscape ofMore than Moore era as traditional scaling reaches its limit. As demonstrated by Greenberg and del Alamo [37], interconnect degrades the device behavior. That is why it is important to include interconnects in the total package of these studies. The rise in the resistance in scaled-down channels also affects the voltage divider and current divider principles, normally based on Ohm’s law. When interconnects are considered in series with the channel, the resistance surges for a smaller length resistor, creating the importance of comprehensive study [38]. Similarly, when parasitic channels are considered in parallel with the conducting channel, the resistance can be higher than what is predicted from Ohm’s law. This rise in resistance can increase the RC time constants as demonstrated in [38, 39]. GNRFET with proper architecture can extend the domain ofMore than Moore era in meeting the requirements of the future. Short-channel effects that restrict the silicon technology to reach its full potential are controllable in GNRFET architecture. GNRFET has shown comparable device performance against 16 nm CMOS node. In terms of circuit performance in logic design, the PDP and EPD of GNRFET are distinctly better. The modern adage is “silicon comes from geology, but carbon comes from biology.” This transformation from silicon to carbon-based graphene will usher new era for circuit design based on carbon electronics that is expected to be compatible with bioelements. ULSI designers will greatly benefit from this comparative study as they change their mode of thinking from CMOS to new graphene-based ULSI. We are also expecting that parasitic elements that inhibit the speed of ULSI circuits will pose less of a problem in future architectures based on our findings. The all-encompassing landscape covered in this paper will find broader applications benefitting not only the research labs in their characterization and performance evaluation, but also in giving new directions to the industry in product development that will benefit global community.



---

*Source: 879813-2014-03-26.xml*