# Modeling and Simulation of Ultra-Wideband Communication Receiver Based on Balanced Sampling and Integrating Circuit

Authors: Zhiqi Wang; Zhonghua Huang; Shijun Hao; Zhe Guo; Kaiwei Wu
Journal: Mobile Information Systems
 (2022)

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## Abstract

In order to solve the problem of extracting signals from impulse radio ultra-wideband (IR-UWB) receivers in a low signal-to-noise ratio (SNR) environment, this paper uses circuit transient analysis to establish a mathematical model of an ultra-wideband wireless communication receiver based on a balanced sampling and integration circuit (BSIC). The effect of receiver circuit component parameters on the output signal is simulated and tested, and the optimization of circuit component parameters for UWB wireless communication receivers is achieved. The sampling capacitance in the receiver circuit ranges from 1 pF to 6 pF, depending on the 200 ps pulse width. The output signal amplitude increases as the sampling capacitance increases. The range of integral capacitance is from 2.5 pF to 25 pF, which is based on a 100 ns interval between two pulses. The output signal amplitude decreases as the integration capacitance increases and the signal waveform becomes better as the integration capacitance increases. The effect of SNR from 0 to −30 dB on the receiver output is simulated, and the results show that the Bit Error Ratio (BER) of the receiver is less than 10−3 when the SNR is greater than −15 dB. The simulation and test results show that the model developed in this paper is useful as a guide for optimizing the receiver parameters at low SNR.


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## Body

## 1. Introduction

Impulse radio ultra-wideband (IR-UWB) has high application value in the Internet of Things (IoT) and wireless communications [1–3], and IR-UWB technology has been widely used in short-range communications, positioning, and radars [4, 5].Receiver is the basis for the realization of IR-UWB technology. At present, there are many types of IR-UWB signal receiver. In [6–9], there are incoherent energy detection receivers for the additive Gaussian white noise channel environment and matched filter receivers for correlated reception. In [10, 11], there are RAKE receivers consisting of multiple parallel correlators for complex multipath channel environments and transmission reference (TR) receivers [12–15], which do not require complex channel estimation compared to RAKE receivers. In [16–21], the structure of the low-noise amplifier (LAN) is optimized to improve the gain of the LAN and reduce the noise so as to improve the data speed of the receiver and reduce the bit error rate (BER). In [22–25], the algorithm of analog-to-digital converter (ADC) is optimized to reduce the bit error rate of the receiver. These improvements can effectively reduce the BER of UWB receiver, and the data speed can reach 100 Mbps to 1 Gbps. And in [10, 12, 13, 20, 24], the effect of the environment on UWB receivers has been studied. However, most of these studies are carried out in high signal-to-noise ratio (SNR) environment, which has poor antinoise ability.The balanced sampling and integration circuit (BSIC) [26] is a simple and low-complexity circuit for recovering rapidly changing weak signals that are drowning in noise. The difference between this receiver and other receivers is the different position of the amplifier. In other receivers, the received signal is first processed by LNA and then by energy detection or correlator. In contrast, sampling and integration receivers process the received signal before amplification by an amplifier, which reduces the amplifier requirements.In order to enhance the anti-interference ability of UWB receiver, the circuit in [26] is improved by adding two resistors, so it is necessary to establish a new model of the receiving circuit. This article mainly adopts the circuit transient analysis method to establish the mathematical model of the UWB wireless communication receiver and obtain the receiver output signal expression through Laplace transform. The influence of receiver circuit component parameters on the output signal is studied, and the circuit component parameters of IR-UWB wireless communication receiver are optimized. The influence of different SNR on the output signal of receiver is studied by simulation.The paper is structured in the following sections: Section2 establishes the receiver model. Section 3 introduces simulation and measurement methods. Section 4 presents and discusses simulation and measured results. Section 5 describes the summary and future work of this article.


## 2. IR-UWB Receiver Modeling

In this section, an IR-UWB wireless communication receiver using a BSIC to achieve correlation calculations between sampling pulses and received signals is studied. The IR-UWB receiver block diagram is shown in Figure1. The receiver consists of two parts, the signal receiving module and the signal processing module. The signal receiving module consists of an antenna, a BSIC, and an IR-UWB signal generation circuit. The signal processing module consists of an amplifier circuit, a level conversion circuit and a CPLD. Signal capture and decoding are performed on the CPLD.Figure 1
Block diagram of the IR-UWB receiver.The BSIC in IR-UWB wireless communication receiver is shown in Figure2, which is composed of three parts: a sampling circuit, an integration circuit, and a high-pass filter circuit. The circuit in Figure 2 is an improvement on [26]. Resistors R2 and R3 in Figure 2 have been added to increase the anti-interference capability of the circuit.Figure 2
IR-UWB receiver circuit schematic diagram.The sampling circuit is composed of sampling capacitorsC1, C2, diodes D1, D2, and resistance R1, and the sampling pulse is Up. The exponential integrating circuit is composed of integrating capacitors C3, C4 and resistors R4, R5. The high-pass filter circuit is composed of filter capacitors C5, C6 and resistors R6, R7. The input signal of the IR-UWB wireless communication receiver is the signal received by the antenna. Diode conduction is controlled by sampling pulse, and input signal is sampled by the sampling capacitor. The sampling values are integrated by capacitors C3 and C4 after the diodes are cut off. The low-frequency part of the integrated signal is filtered out by capacitors C5 and C6, and the signal is input to the differential amplifier. After multiple sampling periods, the output signal of the IR-UWB wireless communication receiver can be obtained.


### 2.1. Circuit Model of Sampling Process of IR-UWB Communication Receiver

According to the two different working states of IR-UWB communication receiver, the sampling process and the integration process, the mathematical models of the two working stages are established in one signal period.The sampling process is the process in which IR-UWB wireless communication receiving circuit samples the input signal after the sampling pulse conducting the diodesD1 and D2. The resistors R1, R2, and R3 are connected in parallel with an equivalent resistance of Rq when the diode is conducting. The circuit in the sampling process is shown in Figure 3. And ignore the effect of conduction diode resistors, because the resistors value of diode conduction is much smaller than R1, R2, and R3.Figure 3
Equivalent circuit diagram of sampling process.Rq in the figure is(1)Rq=R1//R2//R3=R1R2R3R2R3+R1R3+R1R2.Since the upper and lower parts of the BSIC have the same circuit principles, this article only elaborates on the derivation process of the upper part of the circuit model.In thenth period, the initial states of C1, C3, and C5 are assumed to be un1, un3, and un5, respectively, when the diode is conduction. According to Kirchhoff's voltage law, the simplified circuit model from Figure 3 is shown below.(2)ur+=u1+RqC1du1dt−C3du3dt−C5du5dt+up,ur+=u1+R4C3du3dt+C5du5dt+u3,u3=u5+R6C5du5dt.Because the frequency of the received UWB signal is on the order of GB, the parameters of the upper part of the circuit in Figure3 satisfy R6≫R4≫Rq, R4+R6+1/jωC5//1/jωC3≫Rq, and R6+1/jωC5≫1/jωC3. So iC1≫iC3≫iC5; then, the system of equations (2) can be simplified to(3)ur+=u1+RqC1du1dt+up,ur+=u1+R4C3du3dt+u3,u3=u5+R6C5du5dt.Perform Laplace transform on the system of equations (3), and perform inverse Laplace transform on the equations to get u1t, u3t, and u5t as follows:(4)u1t=un1−ur++upe−t/RqC1+ur+−up,u3t=un3e−t/R4C3+up1−e−t/R4C3−RqC1RqC1−R4C3un1−ur−+upe−t/RqC1−e−t/R4C3,u5t=un5e−t/R6C5−un3R4C3R4C3−R6C5e−t/R4C3−e−t/R6C5,+up1−e−t/R6C5−upR4C3R4C3−R6C5e−t/R4C3−e−t/R6C5,−RqC1RqC1−R4C3un1−ur++upRqC1RqC1−R6C5e−t/RqC1−e−t/R6C5−R4C3R4C3−R6C5e−t/R4C3−e−t/R6C5.As shown in Figure3, the upper part and the lower part of the BSIC are symmetrical. Assume that the initial states of the capacitors C2, C4, and C6 during diode conduction are un2, un4, and un6, respectively. Similarly, the solutions of u2t, u4t, and u6t can be obtained as follows:(5)u2t=un2−ur−+upe−t/RqC2+ur−−up,u4t=un4e−t/R5C4+up1−e−t/R5C4,−RqC2RqC2−R5C4un2−ur−+upe−t/RqC2−e−t/R5C4,ut6=un5e−t/R7C6−un4R5C4R5C4−R7C6e−t/R5C4−e−t/R7C6+up1−e−t/R7C6,−upR5C4R5C4−R7C6e−t/R5C4−e−t/R7C6−RqC2RqC2−R5C4un2−ur−+up,RqC2RqC2−R7C6e−t/RqC2−e−t/R7C6−R5C4R5C4−R7C6e−t/R5C4−e−t/R7C6.


### 2.2. Circuit Model of Integration Process of IR-UWB Communication Receiver

At the interval between two sampling pulses, diodesD1 and D2 are cut off, and the input signal of the receiving circuit sampled by the sampling capacitors C1 and C2 is transferred to the integrating capacitors C3 and C4. After multiple sampling cycles, the integration process of the input signal of the receiving circuit is completed, and the low-frequency part of the signal is filtered out by the high-pass filter circuit. The equivalent circuit diagram is shown in Figure 4.Figure 4
Equivalent circuit diagram of integration process.When the diode is cut off in thenth cycle, the initial states of the capacitors C1, C3, and C5 in the upper half of the circuit are un1′, un3′, and un5′, respectively. The equations can be obtained from the equivalent circuit diagram in Figure 4.(6)ur+=u1+R2C1du1dt−C3du3dt−C5du5dt,ur+=u1+R4C3du3dt+C5du5dt+u3,u3=u5+R6C5du5dt.ForiC3≫iC5, therefore, C5du5/dt in the first two equations can be ignored. So, the solution of the equation system can be simplified to(7)u1s=C3R4C1R2s2un1′+C3R2ur+−un3′s+ur+C1R4C3R2s2+C3R2s+1s,u3s=C3R2un3′R4C1s+1+C1R2ur+C3R4R2C1s2+C3R2s+1,u5s=C5R6un5′C1R2C3R4s2+C3R2s+1C5R6s+1C3R4C1R2s2+C3R2s+1.The result of the inverse Laplace transforms of the simplifiedu1t, u3t, and u5t can be obtained as follows:(8)u1t=ur++e−t/2R4C1un1′−ur+coshαR4C1t−2αun3′+un1′−ur+sinhαR4C1t,u3t=ur++un3′−ur+e−t/2R4C1coshαR4C1t+12αsinhαR4C1t,u5t=un5′e−t/R6C5.where α=R2C3−4R4C1/4R2C3.As shown in the equivalent circuit diagram of the integration process of the receiving circuit in Figure3, the upper and lower parts of the circuit are symmetrical during the integration process of the BSIC. In the same way, suppose the initial states of the capacitors C2, C4, and C6 are un2′, un4′, and un6′, respectively, and the results of u2t, u4t, and u6t can be obtained as(9)u2t=ur−+e−t/2R5C2un2′−ur−coshβR5C2t−2βun4′+un2′−ur−sinhβR5C2t,u4t=ur−+un4′−ur−e−t/2R5C2coshβR5C2t+12βsinhβR5C2t,u6t=un6′e−t/2R7C6.where β=R3C4−4R5C2/4R3C4.In the process of circuit model calculation, the received UWB signal is iterated through equations (8) and (9), according to the initial states un1, un3, and un5 of the three capacitors in the upper part of the circuit during diode conduction, and the final state values of un1′, un3′, and un5′ of the capacitors C1, C3, and C5 in the circuit sampling process are obtained. un1′, un3′, and un5′ are the initial state values of capacitors C1, C3, and C5 in the circuit integration process at diode cutoff. Through the iterative operation of equations (8), the final state values of the three capacitors in the upper half of the nth cycle circuit can be obtained. un+11, un+13, and un+15 are the initial states of the three capacitors during diode conduction in the next period.The output signal of the upper part of the BSIC can be obtained by iterative calculation with the above method. In the same way, the output signal of the lower half of the BSIC can be obtained. The BSIC is connected to the differential amplifier, andu2−u3−u5+u6 is taken as the output result of the whole circuit.(10)uOUT=ur++un3′−ur+e−t/2R4C1coshαR4C1t+12αsinhαR4C1t−un5′e−t/R6C5,−ur−−un4′−ur−e−t/2R5C2coshβR5C2t+12βsinhβR5C2t+un6′e−t/R7C6,where α=R2C3−4R4C1/4R2C3, β=R3C4−4R5C2/4R3C4.


## 2.1. Circuit Model of Sampling Process of IR-UWB Communication Receiver

According to the two different working states of IR-UWB communication receiver, the sampling process and the integration process, the mathematical models of the two working stages are established in one signal period.The sampling process is the process in which IR-UWB wireless communication receiving circuit samples the input signal after the sampling pulse conducting the diodesD1 and D2. The resistors R1, R2, and R3 are connected in parallel with an equivalent resistance of Rq when the diode is conducting. The circuit in the sampling process is shown in Figure 3. And ignore the effect of conduction diode resistors, because the resistors value of diode conduction is much smaller than R1, R2, and R3.Figure 3
Equivalent circuit diagram of sampling process.Rq in the figure is(1)Rq=R1//R2//R3=R1R2R3R2R3+R1R3+R1R2.Since the upper and lower parts of the BSIC have the same circuit principles, this article only elaborates on the derivation process of the upper part of the circuit model.In thenth period, the initial states of C1, C3, and C5 are assumed to be un1, un3, and un5, respectively, when the diode is conduction. According to Kirchhoff's voltage law, the simplified circuit model from Figure 3 is shown below.(2)ur+=u1+RqC1du1dt−C3du3dt−C5du5dt+up,ur+=u1+R4C3du3dt+C5du5dt+u3,u3=u5+R6C5du5dt.Because the frequency of the received UWB signal is on the order of GB, the parameters of the upper part of the circuit in Figure3 satisfy R6≫R4≫Rq, R4+R6+1/jωC5//1/jωC3≫Rq, and R6+1/jωC5≫1/jωC3. So iC1≫iC3≫iC5; then, the system of equations (2) can be simplified to(3)ur+=u1+RqC1du1dt+up,ur+=u1+R4C3du3dt+u3,u3=u5+R6C5du5dt.Perform Laplace transform on the system of equations (3), and perform inverse Laplace transform on the equations to get u1t, u3t, and u5t as follows:(4)u1t=un1−ur++upe−t/RqC1+ur+−up,u3t=un3e−t/R4C3+up1−e−t/R4C3−RqC1RqC1−R4C3un1−ur−+upe−t/RqC1−e−t/R4C3,u5t=un5e−t/R6C5−un3R4C3R4C3−R6C5e−t/R4C3−e−t/R6C5,+up1−e−t/R6C5−upR4C3R4C3−R6C5e−t/R4C3−e−t/R6C5,−RqC1RqC1−R4C3un1−ur++upRqC1RqC1−R6C5e−t/RqC1−e−t/R6C5−R4C3R4C3−R6C5e−t/R4C3−e−t/R6C5.As shown in Figure3, the upper part and the lower part of the BSIC are symmetrical. Assume that the initial states of the capacitors C2, C4, and C6 during diode conduction are un2, un4, and un6, respectively. Similarly, the solutions of u2t, u4t, and u6t can be obtained as follows:(5)u2t=un2−ur−+upe−t/RqC2+ur−−up,u4t=un4e−t/R5C4+up1−e−t/R5C4,−RqC2RqC2−R5C4un2−ur−+upe−t/RqC2−e−t/R5C4,ut6=un5e−t/R7C6−un4R5C4R5C4−R7C6e−t/R5C4−e−t/R7C6+up1−e−t/R7C6,−upR5C4R5C4−R7C6e−t/R5C4−e−t/R7C6−RqC2RqC2−R5C4un2−ur−+up,RqC2RqC2−R7C6e−t/RqC2−e−t/R7C6−R5C4R5C4−R7C6e−t/R5C4−e−t/R7C6.


## 2.2. Circuit Model of Integration Process of IR-UWB Communication Receiver

At the interval between two sampling pulses, diodesD1 and D2 are cut off, and the input signal of the receiving circuit sampled by the sampling capacitors C1 and C2 is transferred to the integrating capacitors C3 and C4. After multiple sampling cycles, the integration process of the input signal of the receiving circuit is completed, and the low-frequency part of the signal is filtered out by the high-pass filter circuit. The equivalent circuit diagram is shown in Figure 4.Figure 4
Equivalent circuit diagram of integration process.When the diode is cut off in thenth cycle, the initial states of the capacitors C1, C3, and C5 in the upper half of the circuit are un1′, un3′, and un5′, respectively. The equations can be obtained from the equivalent circuit diagram in Figure 4.(6)ur+=u1+R2C1du1dt−C3du3dt−C5du5dt,ur+=u1+R4C3du3dt+C5du5dt+u3,u3=u5+R6C5du5dt.ForiC3≫iC5, therefore, C5du5/dt in the first two equations can be ignored. So, the solution of the equation system can be simplified to(7)u1s=C3R4C1R2s2un1′+C3R2ur+−un3′s+ur+C1R4C3R2s2+C3R2s+1s,u3s=C3R2un3′R4C1s+1+C1R2ur+C3R4R2C1s2+C3R2s+1,u5s=C5R6un5′C1R2C3R4s2+C3R2s+1C5R6s+1C3R4C1R2s2+C3R2s+1.The result of the inverse Laplace transforms of the simplifiedu1t, u3t, and u5t can be obtained as follows:(8)u1t=ur++e−t/2R4C1un1′−ur+coshαR4C1t−2αun3′+un1′−ur+sinhαR4C1t,u3t=ur++un3′−ur+e−t/2R4C1coshαR4C1t+12αsinhαR4C1t,u5t=un5′e−t/R6C5.where α=R2C3−4R4C1/4R2C3.As shown in the equivalent circuit diagram of the integration process of the receiving circuit in Figure3, the upper and lower parts of the circuit are symmetrical during the integration process of the BSIC. In the same way, suppose the initial states of the capacitors C2, C4, and C6 are un2′, un4′, and un6′, respectively, and the results of u2t, u4t, and u6t can be obtained as(9)u2t=ur−+e−t/2R5C2un2′−ur−coshβR5C2t−2βun4′+un2′−ur−sinhβR5C2t,u4t=ur−+un4′−ur−e−t/2R5C2coshβR5C2t+12βsinhβR5C2t,u6t=un6′e−t/2R7C6.where β=R3C4−4R5C2/4R3C4.In the process of circuit model calculation, the received UWB signal is iterated through equations (8) and (9), according to the initial states un1, un3, and un5 of the three capacitors in the upper part of the circuit during diode conduction, and the final state values of un1′, un3′, and un5′ of the capacitors C1, C3, and C5 in the circuit sampling process are obtained. un1′, un3′, and un5′ are the initial state values of capacitors C1, C3, and C5 in the circuit integration process at diode cutoff. Through the iterative operation of equations (8), the final state values of the three capacitors in the upper half of the nth cycle circuit can be obtained. un+11, un+13, and un+15 are the initial states of the three capacitors during diode conduction in the next period.The output signal of the upper part of the BSIC can be obtained by iterative calculation with the above method. In the same way, the output signal of the lower half of the BSIC can be obtained. The BSIC is connected to the differential amplifier, andu2−u3−u5+u6 is taken as the output result of the whole circuit.(10)uOUT=ur++un3′−ur+e−t/2R4C1coshαR4C1t+12αsinhαR4C1t−un5′e−t/R6C5,−ur−−un4′−ur−e−t/2R5C2coshβR5C2t+12βsinhβR5C2t+un6′e−t/R7C6,where α=R2C3−4R4C1/4R2C3, β=R3C4−4R5C2/4R3C4.


## 3. Simulation and Test

### 3.1. Simulation and Test Methods

In this paper, the mathematical model of equation (10) BSIC is simulated, and the output signal of the actual circuit is measured to study the influence of circuit element parameters on the output signal so as to determine the parameters. The schematic block diagram of circuit parameter simulation and measurement is shown in Figure 5.Figure 5
Circuit simulation and measurement principle block diagram.As shown in Figure5, a modulated received signal is generated, and the received signal is input into a receiving circuit that has replaced different capacitance values. The capacitance values of the sampling capacitor, the integrating capacitor, and the high-pass filter capacitor in the circuit have been replaced, respectively. The influence of sampling capacitance, integrating capacitance and high-pass filter capacitance on the output signal of receiver, is studied through the waveform of output signal of receiving circuit.The measured receiving circuit is shown in Figure6.Figure 6
The measured receiver. (a) Front of the receiver. (b) Back of the receiver.
(a)(b)In Figure6, on the front side of the receiver (Figure 6(a)) are the BSIC and the amplification circuit. On the back of the receiver (Figure 6(b)) is the IR-UWB signal generation circuit. The BSIC, shown in Figure 5, is above the first black package amplifier in Figure 6(a). And ports 1 and 8 are 12 V and −12 V power supply. Port 2 is the output of differential amplifier. Port 3 is the output of comparator. Port 4 is the output of amplifier. Ports 5 and 6 connected to ground. Port 7 is the input signal, which controls the sampling switch. Ports 9 and 10 are connected to IR-UWB symmetrical dipole antennas.The measured principle block diagram of the output signal of IR-UWB wireless communication receiver is shown in Figure7, which is mainly composed of a transmitter, a receiver, an encoder, a DC stabilized power supply, an oscilloscope, and a synchronization line.Figure 7
Block diagram and measurement photo. (a) Block diagram of the measurement receiver. (b) Photo of measurement receiver.
(a)(b)Equipment models are as follows. Encoder: ALTERA Cyclone IV EP4CE6E22C8N. DC stabilized power supply: DH1718E-4. Oscilloscope: Tektronix DPO 7254 2.5 GHz 40 GS/s. Synchronization line: Coaxial line. The transmitter and receiver are made by ourselves.As shown in Figures7 and 8, the encoded signal generated by the encoder is modulated and then emitted by the transmitter, and the signal reaches the receiver through the wireless channel. At the same time, the transmitter sends the synchronous signal to the receiver through the synchronous line. Power supply for UWB wireless communication transmitter and receiver by DC stabilized power supply. The oscilloscope tests the output signal of receiver and the encoded signal of transmitter in different channels. The mathematical model of the receiver proposed in this paper is verified by measuring the output signal of the receiver, which has replaced the values of sampling capacitance, integrating capacitance and high-pass filter capacitance in the receiver.Figure 8
Photo of encoder, transmitter, receiver, and synchronization line.When the parameters of the receiver are determined, a channel simulation module is added between the modulation signal and the receiver to simulate the channel noise, and the noise category is Gaussian white noise. The SNR is changed during simulation to test the receiver’s antinoise ability.


### 3.2. Simulation and Test Setup

The single narrow pulse signal received by the receiver in the simulation is an ultra-wideband signal with a narrow pulse width of 200 ps. The normalized waveform is shown in Figure9.Figure 9
Single narrow pulse signal received by the receiving circuit.The signal in Figure9 is obtained from a Gaussian second-order derivative by simulation of the antenna model in the CST software.The OOK modulated binary code is used in the simulation, the narrow pulse repetition period is 50 ns, and the unit code length is 25μs. The resistance R1 is 51 Ω, R2 and R3 are 1 MΩ, R4 and R5 are 10 kΩ, R6 R6 and R7 are 200 kΩ, the capacitors C1 and C2 are 4 pF, C3 and C4 are 25 nF, and C5, C6 are 19.5 nF.The narrow pulse signal transmitted by the transmitter during the test is shown in Figure10, and the pulse width is about 250 ps.Figure 10
Single narrow pulse signal transmitted by the transmitter.The OOK modulated binary code is used in the simulation, the narrow pulse repetition period is about 52 ns, and the unit code length is 25μs. The resistance R1 is 51 Ω, R2 and R3 are 1 MΩ, R4 and R5 are 10 kΩ, R6 and R7 are 200 kΩ, the capacitors C1 and C2 are 4 pF, C3 and C4 are 22 nF, and C5, C6 are 18 nF.


## 3.1. Simulation and Test Methods

In this paper, the mathematical model of equation (10) BSIC is simulated, and the output signal of the actual circuit is measured to study the influence of circuit element parameters on the output signal so as to determine the parameters. The schematic block diagram of circuit parameter simulation and measurement is shown in Figure 5.Figure 5
Circuit simulation and measurement principle block diagram.As shown in Figure5, a modulated received signal is generated, and the received signal is input into a receiving circuit that has replaced different capacitance values. The capacitance values of the sampling capacitor, the integrating capacitor, and the high-pass filter capacitor in the circuit have been replaced, respectively. The influence of sampling capacitance, integrating capacitance and high-pass filter capacitance on the output signal of receiver, is studied through the waveform of output signal of receiving circuit.The measured receiving circuit is shown in Figure6.Figure 6
The measured receiver. (a) Front of the receiver. (b) Back of the receiver.
(a)(b)In Figure6, on the front side of the receiver (Figure 6(a)) are the BSIC and the amplification circuit. On the back of the receiver (Figure 6(b)) is the IR-UWB signal generation circuit. The BSIC, shown in Figure 5, is above the first black package amplifier in Figure 6(a). And ports 1 and 8 are 12 V and −12 V power supply. Port 2 is the output of differential amplifier. Port 3 is the output of comparator. Port 4 is the output of amplifier. Ports 5 and 6 connected to ground. Port 7 is the input signal, which controls the sampling switch. Ports 9 and 10 are connected to IR-UWB symmetrical dipole antennas.The measured principle block diagram of the output signal of IR-UWB wireless communication receiver is shown in Figure7, which is mainly composed of a transmitter, a receiver, an encoder, a DC stabilized power supply, an oscilloscope, and a synchronization line.Figure 7
Block diagram and measurement photo. (a) Block diagram of the measurement receiver. (b) Photo of measurement receiver.
(a)(b)Equipment models are as follows. Encoder: ALTERA Cyclone IV EP4CE6E22C8N. DC stabilized power supply: DH1718E-4. Oscilloscope: Tektronix DPO 7254 2.5 GHz 40 GS/s. Synchronization line: Coaxial line. The transmitter and receiver are made by ourselves.As shown in Figures7 and 8, the encoded signal generated by the encoder is modulated and then emitted by the transmitter, and the signal reaches the receiver through the wireless channel. At the same time, the transmitter sends the synchronous signal to the receiver through the synchronous line. Power supply for UWB wireless communication transmitter and receiver by DC stabilized power supply. The oscilloscope tests the output signal of receiver and the encoded signal of transmitter in different channels. The mathematical model of the receiver proposed in this paper is verified by measuring the output signal of the receiver, which has replaced the values of sampling capacitance, integrating capacitance and high-pass filter capacitance in the receiver.Figure 8
Photo of encoder, transmitter, receiver, and synchronization line.When the parameters of the receiver are determined, a channel simulation module is added between the modulation signal and the receiver to simulate the channel noise, and the noise category is Gaussian white noise. The SNR is changed during simulation to test the receiver’s antinoise ability.


## 3.2. Simulation and Test Setup

The single narrow pulse signal received by the receiver in the simulation is an ultra-wideband signal with a narrow pulse width of 200 ps. The normalized waveform is shown in Figure9.Figure 9
Single narrow pulse signal received by the receiving circuit.The signal in Figure9 is obtained from a Gaussian second-order derivative by simulation of the antenna model in the CST software.The OOK modulated binary code is used in the simulation, the narrow pulse repetition period is 50 ns, and the unit code length is 25μs. The resistance R1 is 51 Ω, R2 and R3 are 1 MΩ, R4 and R5 are 10 kΩ, R6 R6 and R7 are 200 kΩ, the capacitors C1 and C2 are 4 pF, C3 and C4 are 25 nF, and C5, C6 are 19.5 nF.The narrow pulse signal transmitted by the transmitter during the test is shown in Figure10, and the pulse width is about 250 ps.Figure 10
Single narrow pulse signal transmitted by the transmitter.The OOK modulated binary code is used in the simulation, the narrow pulse repetition period is about 52 ns, and the unit code length is 25μs. The resistance R1 is 51 Ω, R2 and R3 are 1 MΩ, R4 and R5 are 10 kΩ, R6 and R7 are 200 kΩ, the capacitors C1 and C2 are 4 pF, C3 and C4 are 22 nF, and C5, C6 are 18 nF.


## 4. Results and Discussion

### 4.1. Receiver Output Signal with Different Sampling Capacitors

The value of the sampling capacitor depends on the pulse width of the received UWB signal. The approximate value range of the sampling capacitor can be calculated by the principle of capacitor charging.(11)uC1t=ur+1−e−t/RqC1,where ur+ is the receive voltage, uC1 is the voltage of sampling capacitor, and RqC1 is the time constant τ.For the UWB signal pulse width is 200 ps,τ can be 50 ps, 100 ps, 200 ps, and 300 ps. The corresponding sampling capacitors C1 and C2 are, respectively, 1 pF, 2 pF, 4 pF, and 6 pF; the output signal of the receiving circuit can be obtained through the simulation of (10) as shown in Figure 11.Figure 11
Simulation output waveforms of receiving circuit models with different sampling capacitors. (a) Sampling capacitance is 1 pF, (b) sampling capacitance is 2 pF, (c) sampling capacitance is 4 pF, and (d) sampling capacitance is 6 pF.
(a)(b)(c)(d)The relationship between the value of sampling capacitanceC1, C2 and the output waveform amplitude obtained by simulation of the receiving circuit through equation (10) is shown in Figure 12.Figure 12
The relationship between the sampling capacitor and the normalized amplitude of the output signal of the receiving circuit simulated by equation (10).It can be clearly seen from Figures11 and 12 that when the sampling capacitance C1 and C2 is changed, the output waveform amplitude of the BSIC changes significantly. The output signal of the receiving circuit increases with the increase of the sampling capacitance. When the sampling capacitance is 6 pF, the output signal amplitude of the receiving circuit decreases slightly.When the sampling capacitorsC1 and C2 are, respectively, 1 pF, 2 pF, and 4 pF, the output signal waveform of the BSIC is shown in Figure 13.Figure 13
The influence of different sampling capacitors on the output signal of the BSIC. (a) Sampling capacitance is 1 pF. (b) Sampling capacitance is 2 pF. (c) Sampling capacitance is 4 pF.
(a)(b)(c)The influence of different sampling capacitors on the output signal amplitude of the BSIC is shown in Table1.Table 1
Output signal amplitude of BSIC with different sampling capacitors.
Sampling capacitance value (pF)Circuit output signal amplitude (mV)18021604380As shown in Figure13 and Table 1, the amplitude of the output signal of the BSIC increases with the increase of the sampling capacitance, and the trend is the same as the simulation result, when the sampling capacitance does not exceed 8 pF.


### 4.2. Receiver Output Signal with Different Integral Capacitance

The value of the integrating capacitor is determined by the interval between two narrow pulses. The charging process of the integrating capacitorC3 is the same as the discharge process of the sampling capacitor C1. The discharge time constant for the sampling capacitor is as follows:(12)τ=C1C3C1+C3R4.Because the interval between two narrow pulses is 100 ns, the integrating capacitorsC3 and C4 are 2.5 nF, 5 nF, 25 nF, and 50 nF, respectively, the output signal of the receiving circuit can be obtained through the simulation of (10), as shown in Figure 14.Figure 14
The simulation output waveform of the mathematical model of the receiving circuit with different integrating capacitors. (a) Integral capacitance is 2.5 nF. (b) Integral capacitance is 5 nF. (c) Integral capacitance is 25 nF. (d) Integral capacitance is 50 nF.
(a)(b)(c)(d)Figure15 shows the relationship between the integrating capacitors C3, C4 and the receiving circuit through the simulation of equation (10).Figure 15
The relationship between the integrating capacitance and the output signal amplitude simulated by equation (10).As shown in Figures14 and 15, the amplitude of the output signal of the receiving circuit decreases as the integral capacitance C3 and C4 increase. When the integrating capacitance increases to 5 nF, the output signal amplitude of the receiving circuit decreases rapidly. When the integrating capacitance increases from 5 nF to 50 nF, the output signal amplitude of the receiving circuit decreases gradually.When the integrating capacitorsC3 and C4 are, respectively, 22pF, 4.7 nF, and 22 nF, the output signal waveform of the BSIC is shown in Figure 16.Figure 16
The influence of different integral capacitance on the output signal of the balanced sampling integral receiver circuit. (a) Integrating capacitance is 22 pF. (b) Integrating capacitance is 4.7 nF. (c) Integrating capacitance is 22 nF.
(a)(b)(c)The influence of different integrating capacitors on the output signal amplitude of the BSIC is shown in Table2.Table 2
Output signal amplitude of different integral capacitor BSIC.
Integrating capacitance value (pF)Circuit output signal amplitude (mV)22—470064822000640As shown in Figure16 and Table 2, when the integrating capacitor is 22 pF, there is no obvious waveform amplitude as a DC voltage. When the integrating capacitor is 4.7 nF, part of the waveform amplitude can be seen to be 648 mV. When the integrating capacitor is 22 nF, obvious waveforms can be seen, with an amplitude of 640 mV.The simulated and measured results are the same in that the output waveform becomes better when the integrating capacitor is around 22 nF. The difference is in the output waveform when the integration capacitance is less than 22 nF.


### 4.3. Receiver Output Signal with Different Filter Capacitance

When the filter capacitorsC5 and C6 are, respectively, 9.75 nF, 19.5 nF, 39 nF, and 78 nF, the output signal of the receiving circuit obtained by the simulation based on equation (10) is shown in Figure 17.Figure 17
The simulation output waveform of the mathematical model of the receiving circuit with different filter capacitors. (a) Filter capacitance is 9.75 nF. (b) Filter capacitance is 19.5 nF. (c) Filter capacitance is 39 nF. (d) Filter capacitance is 78 nF.
(a)(b)(c)(d)The amplitude relationship between different filter capacitorsC5, C6 and the output signal of the receiving circuit simulated through equation (10) is shown in Figure 18.Figure 18
The relationship between the high-pass filter capacitance and the output signal amplitude simulated by equation (10).It can be seen from Figures17 and 18 that the amplitude of the output signal of the receiving circuit increases with the increase of the filter capacitors C5 and C6.When the filter capacitorsC5 and C6 are 10 nF, 18 nF, and 39 nF, respectively, the output signal waveform of the BSIC is shown in Figure 19.Figure 19
The influence of different high-pass filter capacitors on the output signal of the balanced sampling and integrating receiver circuit. (a) Filter capacitance is 10 nF. (b) Filter capacitance is 18 nF. (c) Filter capacitance is 39 nF.
(a)(b)(c)The influence of different high-pass filter capacitors on the output signal amplitude of the BSIC is shown in Table3.Table 3
Output signal amplitude of different filter capacitor BSIC.
Filter capacitance value (nF)Circuit output signal amplitude (mV)103001892039984As shown in Figure19 and Table 3, the output signal amplitude of the BSIC increases with the increase of the high-pass filter capacitor value, but the waveform is obviously distorted when the waveform reaches 39 nF. The measured result trend is the same as the model simulation result.


### 4.4. Simulation Results of Received Signals under Different SNR

When SNR is −30 dB, the time-domain waveform diagram of the received signal and the receiver output signal is shown in Figure20.Figure 20
The time-domain waveform of the received signal and output signal of the receiver when SNR is −30 dB. (a) Receive signal. (b) Receiver output signal.
(a)(b)To show the differences between all receiver output signals, the receiver output SNR and BER of receiver output signal is provided in Figure21. The input SNR is the ratio of signal to noise in the channel. The output SNR is the ratio of the receiver output signal to the output noise. The BER is obtained by dividing the number of error bits by the total number of bits transmitted. The number of erroneous bits is obtained by statistical method.Figure 21
Receiver performance in low SNR environments. (a) Receiver output SNR. (b) BER of receiver output signal.
(a)(b)The receiver output SNR decreases as the SNR decreases in Figure21, and the BER also increases as the SNR decreases. Figure 21 shows that the BER of the receiver output signal is less than 10–3 when the input SNR is greater than −15 dB.The antinoise performance of the receivers in this paper is compared with other receivers in Table4. The operating environment, BER, and pulse width of the receivers are compared in Table 4. It can be seen from the table that the UWB signal pulse width used in this paper is the narrowest. When BER is the highest, it is in the same order of magnitude as other receivers, but its corresponding SNR is the lowest, which is −30 dB. The receiver proposed in this paper is 1 to 4 orders of magnitude lower than other receivers at the minimum BER, and its corresponding SNR is also the lowest. This indicates that the receiver’s antinoise ability is stronger than other receivers operating in high SNR environments.Table 4
Comparing with other published works.
This workRef. [10]Ref. [12]Ref. [13]Ref. [22]Ref. [20]Pulse width (ns)0.20—Less 330.850.800.22SNR of max. BER (dB)−3008091Maximum BER10–110–110–110–110–110–1SNR of min. BER (dB)02018203014Minimum BER10–910–810–410–510–510–5


## 4.1. Receiver Output Signal with Different Sampling Capacitors

The value of the sampling capacitor depends on the pulse width of the received UWB signal. The approximate value range of the sampling capacitor can be calculated by the principle of capacitor charging.(11)uC1t=ur+1−e−t/RqC1,where ur+ is the receive voltage, uC1 is the voltage of sampling capacitor, and RqC1 is the time constant τ.For the UWB signal pulse width is 200 ps,τ can be 50 ps, 100 ps, 200 ps, and 300 ps. The corresponding sampling capacitors C1 and C2 are, respectively, 1 pF, 2 pF, 4 pF, and 6 pF; the output signal of the receiving circuit can be obtained through the simulation of (10) as shown in Figure 11.Figure 11
Simulation output waveforms of receiving circuit models with different sampling capacitors. (a) Sampling capacitance is 1 pF, (b) sampling capacitance is 2 pF, (c) sampling capacitance is 4 pF, and (d) sampling capacitance is 6 pF.
(a)(b)(c)(d)The relationship between the value of sampling capacitanceC1, C2 and the output waveform amplitude obtained by simulation of the receiving circuit through equation (10) is shown in Figure 12.Figure 12
The relationship between the sampling capacitor and the normalized amplitude of the output signal of the receiving circuit simulated by equation (10).It can be clearly seen from Figures11 and 12 that when the sampling capacitance C1 and C2 is changed, the output waveform amplitude of the BSIC changes significantly. The output signal of the receiving circuit increases with the increase of the sampling capacitance. When the sampling capacitance is 6 pF, the output signal amplitude of the receiving circuit decreases slightly.When the sampling capacitorsC1 and C2 are, respectively, 1 pF, 2 pF, and 4 pF, the output signal waveform of the BSIC is shown in Figure 13.Figure 13
The influence of different sampling capacitors on the output signal of the BSIC. (a) Sampling capacitance is 1 pF. (b) Sampling capacitance is 2 pF. (c) Sampling capacitance is 4 pF.
(a)(b)(c)The influence of different sampling capacitors on the output signal amplitude of the BSIC is shown in Table1.Table 1
Output signal amplitude of BSIC with different sampling capacitors.
Sampling capacitance value (pF)Circuit output signal amplitude (mV)18021604380As shown in Figure13 and Table 1, the amplitude of the output signal of the BSIC increases with the increase of the sampling capacitance, and the trend is the same as the simulation result, when the sampling capacitance does not exceed 8 pF.


## 4.2. Receiver Output Signal with Different Integral Capacitance

The value of the integrating capacitor is determined by the interval between two narrow pulses. The charging process of the integrating capacitorC3 is the same as the discharge process of the sampling capacitor C1. The discharge time constant for the sampling capacitor is as follows:(12)τ=C1C3C1+C3R4.Because the interval between two narrow pulses is 100 ns, the integrating capacitorsC3 and C4 are 2.5 nF, 5 nF, 25 nF, and 50 nF, respectively, the output signal of the receiving circuit can be obtained through the simulation of (10), as shown in Figure 14.Figure 14
The simulation output waveform of the mathematical model of the receiving circuit with different integrating capacitors. (a) Integral capacitance is 2.5 nF. (b) Integral capacitance is 5 nF. (c) Integral capacitance is 25 nF. (d) Integral capacitance is 50 nF.
(a)(b)(c)(d)Figure15 shows the relationship between the integrating capacitors C3, C4 and the receiving circuit through the simulation of equation (10).Figure 15
The relationship between the integrating capacitance and the output signal amplitude simulated by equation (10).As shown in Figures14 and 15, the amplitude of the output signal of the receiving circuit decreases as the integral capacitance C3 and C4 increase. When the integrating capacitance increases to 5 nF, the output signal amplitude of the receiving circuit decreases rapidly. When the integrating capacitance increases from 5 nF to 50 nF, the output signal amplitude of the receiving circuit decreases gradually.When the integrating capacitorsC3 and C4 are, respectively, 22pF, 4.7 nF, and 22 nF, the output signal waveform of the BSIC is shown in Figure 16.Figure 16
The influence of different integral capacitance on the output signal of the balanced sampling integral receiver circuit. (a) Integrating capacitance is 22 pF. (b) Integrating capacitance is 4.7 nF. (c) Integrating capacitance is 22 nF.
(a)(b)(c)The influence of different integrating capacitors on the output signal amplitude of the BSIC is shown in Table2.Table 2
Output signal amplitude of different integral capacitor BSIC.
Integrating capacitance value (pF)Circuit output signal amplitude (mV)22—470064822000640As shown in Figure16 and Table 2, when the integrating capacitor is 22 pF, there is no obvious waveform amplitude as a DC voltage. When the integrating capacitor is 4.7 nF, part of the waveform amplitude can be seen to be 648 mV. When the integrating capacitor is 22 nF, obvious waveforms can be seen, with an amplitude of 640 mV.The simulated and measured results are the same in that the output waveform becomes better when the integrating capacitor is around 22 nF. The difference is in the output waveform when the integration capacitance is less than 22 nF.


## 4.3. Receiver Output Signal with Different Filter Capacitance

When the filter capacitorsC5 and C6 are, respectively, 9.75 nF, 19.5 nF, 39 nF, and 78 nF, the output signal of the receiving circuit obtained by the simulation based on equation (10) is shown in Figure 17.Figure 17
The simulation output waveform of the mathematical model of the receiving circuit with different filter capacitors. (a) Filter capacitance is 9.75 nF. (b) Filter capacitance is 19.5 nF. (c) Filter capacitance is 39 nF. (d) Filter capacitance is 78 nF.
(a)(b)(c)(d)The amplitude relationship between different filter capacitorsC5, C6 and the output signal of the receiving circuit simulated through equation (10) is shown in Figure 18.Figure 18
The relationship between the high-pass filter capacitance and the output signal amplitude simulated by equation (10).It can be seen from Figures17 and 18 that the amplitude of the output signal of the receiving circuit increases with the increase of the filter capacitors C5 and C6.When the filter capacitorsC5 and C6 are 10 nF, 18 nF, and 39 nF, respectively, the output signal waveform of the BSIC is shown in Figure 19.Figure 19
The influence of different high-pass filter capacitors on the output signal of the balanced sampling and integrating receiver circuit. (a) Filter capacitance is 10 nF. (b) Filter capacitance is 18 nF. (c) Filter capacitance is 39 nF.
(a)(b)(c)The influence of different high-pass filter capacitors on the output signal amplitude of the BSIC is shown in Table3.Table 3
Output signal amplitude of different filter capacitor BSIC.
Filter capacitance value (nF)Circuit output signal amplitude (mV)103001892039984As shown in Figure19 and Table 3, the output signal amplitude of the BSIC increases with the increase of the high-pass filter capacitor value, but the waveform is obviously distorted when the waveform reaches 39 nF. The measured result trend is the same as the model simulation result.


## 4.4. Simulation Results of Received Signals under Different SNR

When SNR is −30 dB, the time-domain waveform diagram of the received signal and the receiver output signal is shown in Figure20.Figure 20
The time-domain waveform of the received signal and output signal of the receiver when SNR is −30 dB. (a) Receive signal. (b) Receiver output signal.
(a)(b)To show the differences between all receiver output signals, the receiver output SNR and BER of receiver output signal is provided in Figure21. The input SNR is the ratio of signal to noise in the channel. The output SNR is the ratio of the receiver output signal to the output noise. The BER is obtained by dividing the number of error bits by the total number of bits transmitted. The number of erroneous bits is obtained by statistical method.Figure 21
Receiver performance in low SNR environments. (a) Receiver output SNR. (b) BER of receiver output signal.
(a)(b)The receiver output SNR decreases as the SNR decreases in Figure21, and the BER also increases as the SNR decreases. Figure 21 shows that the BER of the receiver output signal is less than 10–3 when the input SNR is greater than −15 dB.The antinoise performance of the receivers in this paper is compared with other receivers in Table4. The operating environment, BER, and pulse width of the receivers are compared in Table 4. It can be seen from the table that the UWB signal pulse width used in this paper is the narrowest. When BER is the highest, it is in the same order of magnitude as other receivers, but its corresponding SNR is the lowest, which is −30 dB. The receiver proposed in this paper is 1 to 4 orders of magnitude lower than other receivers at the minimum BER, and its corresponding SNR is also the lowest. This indicates that the receiver’s antinoise ability is stronger than other receivers operating in high SNR environments.Table 4
Comparing with other published works.
This workRef. [10]Ref. [12]Ref. [13]Ref. [22]Ref. [20]Pulse width (ns)0.20—Less 330.850.800.22SNR of max. BER (dB)−3008091Maximum BER10–110–110–110–110–110–1SNR of min. BER (dB)02018203014Minimum BER10–910–810–410–510–510–5


## 5. Discussion

Through the simulation and measured results in Sections4.1 to 4.3, it can be seen that the BSIC model established in this paper is consistent with the real circuit. However, in order to simplify the calculation, some parameters in the model are ignored, which leads to a little difference between the calculated results using the model and the measured results.In Section4.4, the simulation results of the model in different SNR environments are compared with the results of some articles. The comparison results show that the anti-interference ability of BSIC receiver is stronger than other compared receivers. However, due to the characteristics of capacitor charging and discharging, the upper limit of data rate of BSIC receiver is lower than receivers with other structures. Therefore, the BSIC receiver can be mainly used in areas with relatively bad channel environment.


## 6. Conclusions

The IR-UWB receiver based on BSIC is improved to enhance its anti-interference ability. The mathematical model of the improved BSIC is established by using the circuit transient analysis method, and the expression of the output signal of the UWB wireless communication receiver is obtained by Laplace transform. The receiver parameters are studied and optimized based on BSIC model. The results of the study show that the integration capacitance in the receiver circuit has the greatest impact on the received signal waveform at an interval of 100 ns with a width of 200 ps; the smaller the integration capacitance, the worse the received signal waveform, in the range of 2.5 pF to 25 pF. This is basically the same as the test results. Simulation and test results show that the receiver model developed in this paper can serve as a guide for optimizing the receiver circuit parameters. The effect of noise on the output signal of the receiver was investigated and compared, and the results showed that the BER of the receiver is less than 0.005 when the SNR is greater than −15 dB. The comparison results show that the anti-interference ability of the improved BSIC receiver is stronger than that of other receivers. This improvement is effective. The next step is to increase the data transmission rate of this receiver.



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