# Design of Wireless Automatic Synchronization for the Low-Frequency Coded Ground Penetrating Radar

Authors: Zhenghuan Xia; Qunying Zhang; Shengbo Ye; Zhiwu Xu; Jie Chen; Guangyou Fang; Hejun Yin
Journal: Journal of Electrical and Computer Engineering
 (2015)

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## Abstract

Low-frequency coded ground penetrating radar (GPR) with a pair of wire dipole antennas has some advantages for deep detection. Due to the large distance between the two antennas, the synchronization design is a major challenge of implementing the GPR system. This paper proposes a simple and stable wireless automatic synchronization method based on our developed GPR system, which does not need any synchronization chips or modules and reduces the cost of the hardware system. The transmitter omits the synchronization preamble and pseudorandom binary sequence (PRBS) at an appropriate time interval, while receiver automatically estimates the synchronization time and receives the returned signal from the underground targets. All the processes are performed in a single FPGA. The performance of the proposed synchronization method is validated with experiment.


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## Body

## 1. Introduction

Low-frequency ground penetrating radar (GPR) is an advanced geophysical technique that is rapidly and widely applied in deep detection [1, 2]. In order to achieve high signal-to-noise ratio (SNR), pseudorandom coded signals had been applied in some detection applications, such as through-the-wall tracking and life detection [3–6]. Meanwhile, pseudorandom coded signals had also been used in GPR to obtain the deeper detection [7, 8]. In practical applications, wire dipole antennas are more suitable for low-frequency GPR system with large transmit power. However, the synchronization between transmitter and receiver is a major challenge.Synchronization with long cables introduces severe interference to the returned signals, which could mask the returned signals from the underground targets. Synchronization with fibers increases the power consumption, complicates the structure, and increases the cost of the radar system. Additionally, it is terribly difficult to carry out experiments with complicate and heavy low-frequency GPR in polar glacier and high tableland [9, 10].In order to simplify the low-frequency GPR structure and reduce the cost of hardware system, a simple and efficient wireless automatic synchronization method is proposed. Firstly, our developed low-frequency coded GPR will be described briefly. Secondly, the wireless automatic synchronization method will be discussed in detail, and the estimation error of synchronization time will be analyzed. Thirdly, the performance of the proposed method of wireless automatic synchronization will be validated with experiment.


## 2. Description of Our Developed Low-Frequency Coded GPR

Our developed low-frequency coded GPR consists of a pair of resistively loaded wire dipole antennas with a length of 12 m, a transmitter with a peak power of 200 W, and a receiver with two sampling channels, which is shown in Figure1. In practical applications, the distance between the two antennas is from 3 m to 5 m.Figure 1
The architecture of our developed low-frequency coded GPR.


### 2.1. Transmitter

One steady-state 150 MHz clock source is the reference clock of the signal generator. The coded signals produced by the signal generator are amplified by a power amplifier (PA) with a maximal peak power of 56 dBm to feed the transmitting antenna. In order to achieve good synchronization without affecting the radar echo, the transmit signals consist of a synchronization preamble andm-sequence of 2047 chips at a time interval of 10 us as shown in Figure 2. The synchronization preamble includes a monocycle and m-sequence of 31 chips at a time interval of 3.5 us. The monocycle is used to estimate coarsely the time of arrival of the direct wave of the m-sequence with 31 chips, which is used to determine accurately the synchronization time. The m-sequence of 2047 chips is used to obtain the impulse response of the deep targets with low side-lobes.Figure 2
The transmit signal from the signal generator.Additionally, the peak power of the monocycle,m-sequence with 31 chips, and m-sequence of 2047 chips are 56 dBm, 44 dBm, and 50 dBm, respectively. Both the two m-sequences are modulated with a 12 MHz sine wave, and the width of each chip of m-sequence is about 80 ns.


### 2.2. Receiver

Another steady-state 150 MHz clock source is used as the main clock of the receiver. As shown in Figure1, the 150 MHz clock is sent to the fan-out chip to generate three synchronized clocks, which are used as the clocks of the two ADCs and FPGA. The limiter is used to prevent the receiver from damage. During the estimation of synchronization time, the synchronization preamble is switched to the low-gain circuit with 3 dB gain and sampled by the first ADC at the sampling rate of 150 MHz, and FPGA estimates the synchronization time. Once the synchronization time has been estimated, the radar echo is switched to high-gain circuit with 30 dB and is sampled by the second ADC at the same sampling rate of 150 MHz. Then the FPGA performs the cross-correlation between the sampled radar echo and the responding reference signal to obtain the impulse response of the detection scenarios.Additionally, the main parameters of the proposed low-frequency coded GPR are summarized in Table1.Table 1
Parameters of the low-frequency coded GPR.
Parameter
Value
Width of the monocycle
80 ns
Width of each chip
80 ns
Length of the longm-sequence
2047 chips
Peak power
50 dBm
Receiver sensitivity
−115 dBm
Real-time sampling rate of ADC
150 Mbps
The linear average factor
512
The scanning rate
8 scans/s
Pulse repeated period
200 us
Maximal detection time window
4 us


## 2.1. Transmitter

One steady-state 150 MHz clock source is the reference clock of the signal generator. The coded signals produced by the signal generator are amplified by a power amplifier (PA) with a maximal peak power of 56 dBm to feed the transmitting antenna. In order to achieve good synchronization without affecting the radar echo, the transmit signals consist of a synchronization preamble andm-sequence of 2047 chips at a time interval of 10 us as shown in Figure 2. The synchronization preamble includes a monocycle and m-sequence of 31 chips at a time interval of 3.5 us. The monocycle is used to estimate coarsely the time of arrival of the direct wave of the m-sequence with 31 chips, which is used to determine accurately the synchronization time. The m-sequence of 2047 chips is used to obtain the impulse response of the deep targets with low side-lobes.Figure 2
The transmit signal from the signal generator.Additionally, the peak power of the monocycle,m-sequence with 31 chips, and m-sequence of 2047 chips are 56 dBm, 44 dBm, and 50 dBm, respectively. Both the two m-sequences are modulated with a 12 MHz sine wave, and the width of each chip of m-sequence is about 80 ns.


## 2.2. Receiver

Another steady-state 150 MHz clock source is used as the main clock of the receiver. As shown in Figure1, the 150 MHz clock is sent to the fan-out chip to generate three synchronized clocks, which are used as the clocks of the two ADCs and FPGA. The limiter is used to prevent the receiver from damage. During the estimation of synchronization time, the synchronization preamble is switched to the low-gain circuit with 3 dB gain and sampled by the first ADC at the sampling rate of 150 MHz, and FPGA estimates the synchronization time. Once the synchronization time has been estimated, the radar echo is switched to high-gain circuit with 30 dB and is sampled by the second ADC at the same sampling rate of 150 MHz. Then the FPGA performs the cross-correlation between the sampled radar echo and the responding reference signal to obtain the impulse response of the detection scenarios.Additionally, the main parameters of the proposed low-frequency coded GPR are summarized in Table1.Table 1
Parameters of the low-frequency coded GPR.
Parameter
Value
Width of the monocycle
80 ns
Width of each chip
80 ns
Length of the longm-sequence
2047 chips
Peak power
50 dBm
Receiver sensitivity
−115 dBm
Real-time sampling rate of ADC
150 Mbps
The linear average factor
512
The scanning rate
8 scans/s
Pulse repeated period
200 us
Maximal detection time window
4 us


## 3. Design of Wireless Automatic Synchronization

The transmitter omits the coded signals at a pulse repeated period (PRP) of 200 us, and the receiver estimates accurately the synchronization time and receives the radar echoes. The responding reference signals of the twom-sequences can be obtained in close-loop situation as shown in Figure 3, and the two reference signals are stored in two on-chip RAMs of the FPGA. The reference signal of the m-sequence with 31 chips is denoted as m(i), and the reference signal of the m-sequence with 2047 chips is denoted as ml(i). The architecture of wireless automatic synchronization in the receiver is shown in Figure 4.Figure 3
Obtain the reference signal of them-sequence in close-loop situation.Figure 4
Estimation of the synchronization time based on FPGA.


### 3.1. Estimation of the Synchronization Time

Firstly, the direct wave of the monocycle sampled by the first ADC, which is denoted asy(i), is filtered by the digital low pass filter (LPF) to remove the noise and compared with the threshold Cthreshold. The threshold Cthreshold should be chosen according to the amplitude of the direct wave and the level of the noise or clutter. For our low-frequency GPR system, the maximum clutter or noise is about 42 mV, and the amplitude of the direct wave is about 610 mV when the distance between the two antennas is 3 m. When the distance is increased to 5 m, the amplitude of the direct wave is decreased to about 220 mV. Thus the threshold is fixed at 150 mV in this work, and the distance between the two antennas should be less than 5 m in practical applications.Secondly, when the filtered signalyl(i) is more than the threshold, the first timer Timer 1 is enabled to count. The TOA of the m-sequence with 31 chips comes when the timer Timer 1 counts to 3.5 us. At this time, the sampled signal y(i) could be considered coarsely as the direct wave of the m-sequence of 31 chips and sent to the parallel cross-correlation module to obtain the cross-correlation Rsyn(k) as(1)Rsynk=∑i=0371mi·yk+i,k=0,1,…,K,where mi is the reference signal of the m-sequence of 31 chips and stored in a RAM of FPGA. M-sequence with 31 chips lasts for about 2.48 us and the sampling clock of ADC is 150 MHz, and the length of the reference signal mi is 372. The clock of the parallel cross-correlation module is 150 MHz synchronized with the sampling clock of ADCs. The pipeline delay and throughput rate of the parallel cross-correlation module are 372 clock periods and 150 Msps, respectively. Then FPGA can find the maximum value of the cross-correlation by comparison between the two adjacent cross-correlations in a time window of 2.48 us. Ultimately, the synchronization time can be determined by the maximal value of cross-correlation.Thirdly, when the synchronization time is estimated, the timer Timer 2 is enabled to count and the radar echo is switched to the high-gain circuit and sampled by the second ADC when the timer Timer 2 counts to 10 us. Then the cross-correlationRechok of the echo is performed to obtain the impulse response of detection scenarios. In order to perform correctly the linear averaging to improve the SNR of the radar echoes, the maximal value of the cross-correlation Rechok in each returned signal should be found and then performs addition among the adjacent 512 traces to obtain the ultimate impulse response of the underground targets.


### 3.2. Analysis of the Estimation Error

As shown in Figure1, the two reference clocks, Clock 1 and Clock 2, are not synchronized, which induces the estimation error of synchronization time. It is equivalent to the fact that the estimation error comes from the random jitter of the initial sampling time of the receiver, and the maximal jitter is one period of Clock 2. In close-loop situation as shown in Figure 3, all the reference signals of the cross-correlation have been sampled at a sampling clock of Clock 2 and stored in FPGA beforehand. According to (1), the cross-correlation of the sampled m-sequence with 31 chips in close-loop situation is shown in Figure 5(a). Figure 5(b) shows the estimation errors of synchronization time come from different jitter of the initial sampling time of the receiver, which indicates that the maximal estimation error is also one period of Clock 2 when the jitter is more than a half period of Clock 2. Then the estimation error will affect the initial acquisition time for the radar echo.Figure 5
Cross-correlation of them-sequence with 31 chips in close-loop situation. (a) Cross-correlation of the sampled m-sequence with 31 chips. (b) Cross-correlations of the sampled m-sequence with unstable initial sampling time.
(a)
(b)Figure6 shows the comparison between the cross-correlation of the received m-sequence of 2047 chips with one-period estimation error of synchronization time and that of no estimation error. It can be seen that the main-lobe to side-lobe ratio of the two cross-correlations is almost the same because of the high sampling rate relative to the low-frequency m-sequence. However, the location of the maximal value of the cross-correlation with one-period error is ahead one period of that of the cross-correlation without error. In order to perform correctly the linear averaging with 512 traces, the maximal value of the cross-correlation should be found firstly, and the 512 additions are performed from the maximal value of the 512 cross-correlations.Figure 6
Comparison between the cross-correlation of them-sequence with 2047 chips with one-period estimation error and that of m-sequence with no estimation error.


## 3.1. Estimation of the Synchronization Time

Firstly, the direct wave of the monocycle sampled by the first ADC, which is denoted asy(i), is filtered by the digital low pass filter (LPF) to remove the noise and compared with the threshold Cthreshold. The threshold Cthreshold should be chosen according to the amplitude of the direct wave and the level of the noise or clutter. For our low-frequency GPR system, the maximum clutter or noise is about 42 mV, and the amplitude of the direct wave is about 610 mV when the distance between the two antennas is 3 m. When the distance is increased to 5 m, the amplitude of the direct wave is decreased to about 220 mV. Thus the threshold is fixed at 150 mV in this work, and the distance between the two antennas should be less than 5 m in practical applications.Secondly, when the filtered signalyl(i) is more than the threshold, the first timer Timer 1 is enabled to count. The TOA of the m-sequence with 31 chips comes when the timer Timer 1 counts to 3.5 us. At this time, the sampled signal y(i) could be considered coarsely as the direct wave of the m-sequence of 31 chips and sent to the parallel cross-correlation module to obtain the cross-correlation Rsyn(k) as(1)Rsynk=∑i=0371mi·yk+i,k=0,1,…,K,where mi is the reference signal of the m-sequence of 31 chips and stored in a RAM of FPGA. M-sequence with 31 chips lasts for about 2.48 us and the sampling clock of ADC is 150 MHz, and the length of the reference signal mi is 372. The clock of the parallel cross-correlation module is 150 MHz synchronized with the sampling clock of ADCs. The pipeline delay and throughput rate of the parallel cross-correlation module are 372 clock periods and 150 Msps, respectively. Then FPGA can find the maximum value of the cross-correlation by comparison between the two adjacent cross-correlations in a time window of 2.48 us. Ultimately, the synchronization time can be determined by the maximal value of cross-correlation.Thirdly, when the synchronization time is estimated, the timer Timer 2 is enabled to count and the radar echo is switched to the high-gain circuit and sampled by the second ADC when the timer Timer 2 counts to 10 us. Then the cross-correlationRechok of the echo is performed to obtain the impulse response of detection scenarios. In order to perform correctly the linear averaging to improve the SNR of the radar echoes, the maximal value of the cross-correlation Rechok in each returned signal should be found and then performs addition among the adjacent 512 traces to obtain the ultimate impulse response of the underground targets.


## 3.2. Analysis of the Estimation Error

As shown in Figure1, the two reference clocks, Clock 1 and Clock 2, are not synchronized, which induces the estimation error of synchronization time. It is equivalent to the fact that the estimation error comes from the random jitter of the initial sampling time of the receiver, and the maximal jitter is one period of Clock 2. In close-loop situation as shown in Figure 3, all the reference signals of the cross-correlation have been sampled at a sampling clock of Clock 2 and stored in FPGA beforehand. According to (1), the cross-correlation of the sampled m-sequence with 31 chips in close-loop situation is shown in Figure 5(a). Figure 5(b) shows the estimation errors of synchronization time come from different jitter of the initial sampling time of the receiver, which indicates that the maximal estimation error is also one period of Clock 2 when the jitter is more than a half period of Clock 2. Then the estimation error will affect the initial acquisition time for the radar echo.Figure 5
Cross-correlation of them-sequence with 31 chips in close-loop situation. (a) Cross-correlation of the sampled m-sequence with 31 chips. (b) Cross-correlations of the sampled m-sequence with unstable initial sampling time.
(a)
(b)Figure6 shows the comparison between the cross-correlation of the received m-sequence of 2047 chips with one-period estimation error of synchronization time and that of no estimation error. It can be seen that the main-lobe to side-lobe ratio of the two cross-correlations is almost the same because of the high sampling rate relative to the low-frequency m-sequence. However, the location of the maximal value of the cross-correlation with one-period error is ahead one period of that of the cross-correlation without error. In order to perform correctly the linear averaging with 512 traces, the maximal value of the cross-correlation should be found firstly, and the 512 additions are performed from the maximal value of the 512 cross-correlations.Figure 6
Comparison between the cross-correlation of them-sequence with 2047 chips with one-period estimation error and that of m-sequence with no estimation error.


## 4. Experiments and Results

The typical configuration for the low-frequency GPR is shown in Figure7. The distance between the two wire antennas is about 3.8 m, and the synchronization is implemented with two methods: high-performance ORTEL’s fiber models (including OTS-1RefR-100 and OTS-1RefT-100 [11]) and the proposed wireless automatic synchronization method. For this wireless automatic synchronization, the received direct wave of the monocycle as the blue line is shown in Figure 8(a), while the filtered signal as the red line is shown in Figure 8(a). The direct wave of the m-sequence with 31 chips is received, and its cross-correlation can be obtained as shown in Figure 8(b). The synchronization time can be estimated by the maximal value of the cross-correlation.Figure 7
The typical configuration for the low-frequency coded GPR.Figure 8
Received synchronization preamble. (a) The direct wave of the monocycle. (b) The cross-correlation of the direct wave of them-sequence with 31 chips.
(a)
(b)The red line as shown in Figure9(a) is the obtained impulse response with the proposed wireless automatic synchronization method, while the blue line in Figure 9(a) is the obtained impulse response with the fiber modules. The difference between the two impulse responses is shown in Figure 9(b), which indicates that the two impulse responses are almost same, while different clutter and noise have been received in different time. Figure 10 shows the responding detection result with the proposed low-frequency coded GPR in desert. It can be seen that some clear layers in depth of 45 m and 70 m can be detected.Figure 9
The obtained impulse responses with the two methods. (a) Two impulse responses. (b) The difference between them.
(a)
(b)Figure 10
The detection result with the low-frequency coded GPR, and the dielectric constant is 8.


## 5. Conclusion

This paper presents a wireless automatic synchronization method for the low-frequency coded GPR without any other synchronization chips or modules, which simplify the architecture of the GPR system and reduce the hardware cost. Although the maximum synchronization error with the proposed method is one sampling period of ADC-clock, it degrades hardly the main-lobe to side-lobe ratio of pulse compression due to the high sampling rate relative to the low-frequencym-sequence. In order to reduce the effect from the synchronization error farther, the ADC-clock can be increased to an appropriate value to satisfy the requirement of different applications, such as 400 MHz or 1 GHz.



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*Source: 864153-2015-07-27.xml*