# Novel Switched Configuration-Based Multilevel Inverter Topology for Industrial Applications

Authors: V. Krishnakumar; P. Anbarasan; K. Ramash Kumar; M. Venmathi
Journal: Journal of Electrical and Computer Engineering
 (2022)

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## Abstract

Multilevel inverters proved its capabilities nowadays operating in the symmetrical and asymmetrical source of voltages to bring output voltage nearly to a sinusoid. Several variations in topological strategies put forth better output quality with lesser harmonic distortion. However, it suffers from several issues predominantly such as more number of devices, higher blocking voltage, and power loss for higher voltage levels. This paper forays a fresh topology on switched configuration multilevel inverters with optimum dc sources, switches, voltage level, and filter requirements. The proposed topology has the flexibility to extend for higher voltage levels with make use of less switches. The proposed structure has been simulated in MATLAB/Simulink and validated the results in a laboratory setup.


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## Body

## 1. Introduction

Multilevel inverters (MLI) have been fostered up to 230 kV voltage with applications such as industrial drives, static compensators, and renewable energy applications [1–4]. Multilevel inverters have been devised to synthesize stepped waveform through several isolated dc sources or dc link capacitors and accord minimum harmonic distortion, lower voltage stress across the devices compared with overall inverting operating voltage and lower electromagnetic interference [5]. These advantages explore multilevel inverters to put forth for lower power applications over high-voltage medium-power applications [6, 7]. Precisely, multilevel inverters acknowledge good harmonic profile only when a number of voltage levels tends to increase utilizing more number of IGBT or MOSFET devices and voltage sources which raises the cost of the entire device [8, 9]. The fundamental topology in the multilevel inverter family is cascaded-type topologies which include several isolated dc sources with the arrangement of switching devices to bring multilevel structure voltage waveform without the issue of d-link voltage balancing [10]. Several researches have been carried out with the goal of developing innovative topologies with fewer components and dc voltage sources. Several asymmetrical inverter structures with unequal source voltage ratios and modulation strategies comprising carrier-based pulse width modulation (PWM), space vector PWM (SVPWM), selective harmonic elimination PWM (SHE-PWM) in the field of multilevel power converters have been reported [11–14].A new topology for producing multilevel voltage waveforms has been reported in the literature, using isolated symmetric input DC sources coupled in reverse polarities in a laddered structure through a series of power semiconductor devices. The higher voltage levels can be reached by extending the inverter by simply adding a voltage source with a preceding voltage source in the reverse direction with two series switches. If one of the outer layer switches is under fault, the topology is inefficient to produce alternating multilevel waveform [15, 16]. A single-phase cascaded-type multilevel inverter topology includes two five-level transistor-clamped multilevel inverters in series connection to offer nine-level output voltage has been presented. The system employs an array of split capacitors to synthesize pole voltage waveform which results in capacitor balancing issues [17]. A new topology has been reported for the concatenation of several sub-MLI blocks in the H six structure to offer a stepped voltage waveform [18] that slightly varied in a structure presented in [15, 16]. A new topology using half bridge cells and a level doubling network (LDN) to double the output voltage levels has been conceived in [19]. A new inverter topology using cascaded H Bridge cells having asymmetric binary voltage ratio is devised to eliminate the need for isolated dc sources by dc capacitors adapting only one DC source for the whole structure. The magnitude of the voltage source has been selected as the highest value while the remaining DC capacitors magnitudes are chosen as half of the preceding DC capacitor voltages and remain unbalanced dc link voltages with the same number of switching devices as used in classical cascaded H Bridge inverter [20]. A topology based on dual voltage sources with an H Bridge inverter has been introduced using several switching devices and diodes. The topology suffers from the requirement of more number of switching devices and diodes for the increased number of voltage levels [21].A switched capacitor module is suggested using a single dc source and two capacitors to generate 9 levels with a voltage boosting gain of two and also to ensure total device blocking voltage is limited to dc source voltage [22]. In [23], a new MLI topology connects the level generation module and polarity reversal unit to achieve any required level depending on the configuration of the level generation units to be added with the developed topology. A new cascaded MLI consists of high-frequency magnetic link (HFML) and full bridge rectifiers in addition to compact cascaded MLI has been reported in the literature. To obtain higher voltage levels in the output voltage, more cascaded cells have been added, which is a key weakness of this proposed topology for low-power applications [24]. Two new MLI topologies have been suggested to achieve reduced components. However, the topology is incapable of generating a voltage ratio with a binary voltage ratio of voltage source magnitudes [25]. An improved symmetrical four-level submodule and polarity reversal inverter is used to generate multiple voltage levels has been presented in [26]. The topology losses its modularity to produce succeeding voltage levels in the output voltage. A new topology has been formulated to reduce switches, isolated dc voltage sources without losing modularity for an increase in output voltage levels [27]. A new cascaded MLI structure to offer minimum switches has been reported in [28], but this topology requires switches with high blocking voltage capability for achieving an increased number of voltage levels.The detailed literature review in the field of multilevel inverter topologies brings an avenue to draw out new multilevel inverter structure with a view of reduced component counts. The developed work has been oriented to bring new cascaded-type multilevel inverter topology overwhelming the drawbacks in classical cascaded type.


## 2. Detail Explanation of Proposed Multilevel Inverter Topology

The generalized circuit for the proposed topology is represented in Figure1 that uses voltage sources (V1 − Vn) and the switches (S1 − Sn + 5) to synthesize multilevel dc link voltage and an H Bridge inverter with switches (Sa − Sd) for polarity reversal in the proposed topology.Figure 1
Generalized structure of proposed multilevel inverter topology.The diode (D1) in the proposed structure helps to avoid interlooping problems between the voltage sources V3 and (V2 − Vn). The voltage sources (V1 − V3) act as permanent voltage source module, and the voltage sources (V4 − Vn) act as add-on module to synthesize higher voltage levels. With the voltage sources (V1 − V3), the proposed topology produces 7 level in the output side with an equal value of voltage sources. To understand the modes of operation, the generalized topology is configured to generate nine-level output as depicted in Figure 2. Figure 3 forges to synthesize level 1 (magnitude of V1) in the output voltage by switching the devices in a sequence of (S1, S3, S4, S5, Sa, and Sb) and (S1, S3, S4, S5, Sc, and Sd), respectively while the switches (S1, S9, S4, S6, Sa, and Sb) and (S1, S9, S4, S6, Sc, and Sd) in Figure 4 are switched on to produce level 4 (magnitudes of (V1 + V2 + V3 + V4)) in the output voltage, respectively. The proposed topology is capable of generating more voltage levels by properly choosing the magnitude of voltage sources as asymmetrical values. Table 1 tabulates the switching states for different modes of operation. Switches S7 and S8 are utilized for the inductive load (RL-Load) to freewheel the current.Figure 2
Proposed nine-level inverter.Figure 3
Operating mode: ±V1.Figure 4
Operating mode: ± (V1 + V2 + V3 + V4).Table 1
Switching states for different operating modes.
Operating modesS1S2S3S4S5S6S7S8S9SaSbScSd+V1ONOFFONONONOFFOFFOFFOFFONONOFFOFF−V1ONOFFONONONOFFOFFOFFOFFOFFOFFONON+(V1+V2)ONONOFFONONOFFOFFOFFOFFONONOFFOFF−(V1+V2)ONONOFFONONOFFOFFOFFOFFOFFOFFONON+(V1+V2+V3)ONOFFONONOFFONOFFOFFOFFONONOFFOFF−(V1+V2+V3)ONOFFONONOFFONOFFOFFOFFOFFOFFONON+(V1+V2+V3+V4)ONOFFOFFONOFFONOFFOFFONONONOFFOFF−(V1+V2+V3+V4)ONOFFOFFONOFFONOFFOFFONOFFOFFONONThe relationship between the voltage sources and switches in the proposed topology is (n+9), where “n” is the number of voltage sources and is greater than 3, while the number of voltage levels with given “n” is ((2×n)+1). The blocking voltage across each switch will be(1)VS2=VS5=VS6=Vdc,VS1=VS3=VS4=VS7=VS8=VS9=2×Vdc,VSa=VSb=VSc=VSd=4×Vdc.The primary goal of formulating any innovative topology is to generate all voltage levels which depend on the selection of the magnitude of voltage sources. Therefore, in order to generate all desired voltage levels, seven techniques have been conceived to find out the voltage sources’ magnitude.Table2 tabulates the design equations suitable for the proposed topology relating to the magnitude of voltage sources and voltage levels to be acquired using these equations. To evaluate the methods tabulated in Table 2, a submultilevel topology with four dc voltage sources is considered in this study, and the structure is represented in Figure 5. It is mandatory to compare the proposed methods among them and identify the best one suited to offer higher voltage levels with least switching devices, voltage sources, blocking voltages, and gate drivers for the developed topology. The number of switching devices employing the proposed submultilevel inverter modules is compared in Figure 6. The switching devices increase as the number of sub-MLI modules increases. Figure 7 shows the variation of voltage levels with proposed inverter modules using proposed voltage magnitude determination methods. It is confirmed that higher voltage is achieved in the sixth and seventh proposed methods with a minimum number of switching devices.Table 2
Magnitude value of voltage sources for different methods.
MethodsMagnitude value of voltage sourcesNumber of voltage levelsMaximum output voltagesTotal blocking voltagesIV1,1=V1,2=V1,3=V1,4=VdcVj,1=Vj,2=Vj,3=Vj,4=Vdc;j=1,2,…,n((8 ×n) + 1)(4 ×n) × Vdc(32 ×n) × VdcIIV1,1=V1,2=V1,3=V1,4=VdcVj,1=Vj,2=Vj,3=Vj,4=2Vdc;j=1,2,…,n((16 ×n) − 7)((8 ×n) − 4) × Vdc((64 ×n) − 32)  × VdcIIIV1,1=V1,2=V1,3=V1,4=VdcVj,1=Vj,2=Vj,3=Vj,4=2j−1Vdc;j=2,…,n8×∑i=1n2i−1+14×∑i=1n2i−1×Vdc32×∑i=1n2i−1×VdcIVV1,1=V1,2=V1,3=V1,4=VdcVj,1=Vj,2=Vj,3=Vj,4=3Vdc;j=1,2,…,n((24 ×n) − 15)((12 ×n) − 8) × Vdc((96 ×n) − 64) × VdcVV1,1=V1,2=V1,3=V1,4=VdcVj,1=Vj,2=Vj,3=Vj,4=3j−1Vdc;j=2,…,n8×∑i=1n3i−1+14×∑i=1n3i−1×Vdc32×∑i=1n3i−1×VdcVIV1,1=V1,2=V1,3=V1,4=VdcVj,1=Vj,2=Vj,3=Vj,4=4Vdc;j=1,2,…,n((32 ×n) − 23)((16 ×n) − 12) × Vdc((128 ×n) − 96) × VdcVIIV1,1=V1,2=V1,3=V1,4=VdcVj,1=Vj,2=Vj,3=Vj,4=4j−1Vdc;j=2,…,n8×∑i=1n4i−1+14×∑i=1n4i−1×Vdc32×∑i=1n4i−1×VdcFigure 5
Submultilevel inverter topology.Figure 6
Variation of switching devices with proposed submultilevel inverters.Figure 7
Voltage level variation with proposed submultilevel inverters.Figures8 and 9 elaborate the maximum output voltage and total blocking voltage required by the proposed topology for different proposed methods, respectively. From Figures 8 and 9, the seventh proposed method needs a lower number of inverter modules to generate particular levels with reduced blocking voltage. Moreover, the first proposed algorithm requires more numbers of dc voltage sources as it is common for any topology. It is observed that the first proposed method has lower voltage amplitudes of the used sources, and the seventh proposed method needs a minimum number of switching devices and high combinations magnitudes of the voltage sources. However, its performance is better than the other proposed methods except the first one. Therefore, it is concluded that the seventh method forays a better performance among all the proposed methods.Figure 8
Variation of maximum output voltage with proposed submultilevel inverters.Figure 9
Variation of total blocking voltage with proposed submultilevel inverters.Table3 elaborates the mathematical relations to achieve switching devices, dc sources, and switching devices in the current conduction path for symmetrical configurations. Figures 10–12 represent a plot between number of voltage levels and dc sources, switching devices, and switches in the current conduction path. In Figure 10, the proposed topology requires less number of dc sources to produce higher voltage levels. From Figures 11 and 12, the proposed topology requires a marginal increase in switching devices compared with R [32] and the same number of current conducting switches except R [29–31].Table 3
Mathematical relations to achieve switching devices and dc sources for “m” levels.
TopologyMinimum no. of voltage levelsNo. of switchesNo. of DC sourcesNo. of freewheeling diodesNo. of switches in the current conduction pathR [29]5(m+1)(m+1)/2—(m+1)/2R [30]5(m+3)(m − 1)/2—(m+3)/2R [31]5(m+1)(m+1)/2—(m+1)/2R [32]5(m+11)/2(m −1)/2(m −5)/2(m+3)/2Proposed7(m+17)/2(m −1)/2—(m+3)/2Figure 10
No. of voltage levels vs no. of DC sources.Figure 11
No. of voltage levels vs no. of switching devices.Figure 12
No. of voltage levels vs no. of switches in current conduction path.It is essential to investigate the cost reduction of the component counts in comparison between the proposed and reduced counts topologies in view of producing higher number of voltage levels in symmetrical configuration. The recent component count topologies reported in the literature [21, 33–36] are devised by arranging the dc sources in a suitable way to reduce the number of components for producing the desired voltage levels in output. In this perspective, an analysis has been taken to consider two different voltage levels 45 and 47 to showcase the drastic reduction in the switch count with a fixed number of voltage sources. For 47-level inverter, the topology reported in [33] requires 50 and the topologies in [34, 35] utilize 48, while the proposed topology requires only 32 switching devices. Similarly, for 45-level inverter, the proposed topology requires only 31, and the topologies reported in [21, 36] need 41 and 66 switching devices, respectively. It shows that proposed topology is compact and more economical.


## 3. Measured Simulation and Experimental Results

The effectiveness and viability of the topology have been simulated with Matlab R2015b, and the same simulation specifications are taken to construct the laboratory prototype for experimental investigations. The topology shown in Figure1 is reconfigured to produce 9 level in the output voltage, and the input dc voltage source magnitudes are considered as 75 V each with the specifications 2 kHz switching frequency, RL load of resistance 150 Ω, and inductance 100 mH, respectively. Figure 13 portrays the gating pulses for the switches (S1 to S9) in the switched configured stage of the proposed topology to produce 9 levels in the output voltage waveform. Figures 14 and 15 demonstrate nine-level output voltage of proposed inverter topology and inductive load current waveforms, respectively. The THD spectrum with THD of 12.67% is displayed in Figure 16.Figure 13
Gating pulse for 9-level inverter.Figure 14
Output voltage of proposed 9-level inverter forR-L load.Figure 15
Inductive load current waveform.Figure 16
Voltage THD waveform.The pictorial representation of the experimental prototype built in the laboratory has been depicted in Figure17 to showcase the practical reliability of the proposed topology. The gating pulse generation avails LUTs to synthesize the desired pulse train using the Xilinx Spartan 3E FPGA controller as portrayed in Figure 18. Gating pulses for the switches (S1 to S8) in the switched configured stage of the proposed topology to produce 9 level in the output voltage waveform are shown in Figure 19.Figure 17
Experimental setup of proposed inverter topology.Figure 18
Experimental flow chart for FPGA pulse generation.Figure 19
Gating pulses for proposed nine-level inverter switches (a)S1 to S4 and (b) S5 to S8.
(a)(b)The nine-level output voltage waveform of improved quality in near sinusoidal shape along with better harmonic spectrum has been depicted in Figure20. From the harmonic spectrum, it is observed that the total harmonic distortion (THD) of the output voltage waveform is near to the specified acceptable limits, and it results in the minimum requirement of the output filter size. Figure 21 depicts the experimental inductive load current waveform. Figure 22 represents the output voltage variation with a change in amplitude modulation index. It is inferred that the developed topology responds well with change in voltage variation. The experimental results accorded with simulation results.Figure 20
Output voltage waveform and voltage spectrum.Figure 21
Inductive load current waveform.Figure 22
Variation of output voltage with change in modulation index.


## 4. Conclusion

In comparison to traditional MLI topologies, the proposed topology is formulated with a view of figuring out reduced components to produce a higher number of voltage levels. The operating modes for generating nine levels have been presented with the flow path. The proposed MLI topology has been described in depth, as well as methods for determining the magnitude of voltage sources. The proposed topology requires only one switching device to add a single voltage source with the parent module and thus making the reduced number of switches in the current conduction path thereby making less power loss. The simulation and experimental results showcase the merits of the proposed topology for the practical applications like renewable and drive sectors.



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