# Digital Noise Generator Design Using Inverted 1D Tent Chaotic Map

Authors: Leonardo Palacios-Luengas; Gonzalo Isaac Duchen-Sánchez; José Luis Aragón-Vera; Rubén Vázquez-Medina
Journal: VLSI Design
 (2012)

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## Abstract

This paper shows a digital noise generator designed in FPGA, based on a variant of the one-dimensional (1D) chaotic tent map (T-1D). The T-1D map is a piecewise linear 1D chaotic map that defines the statistical behavior of the generated sequences using its control parameter. In this way, the proposed noise generator is a highly competitive alternative in cryptographic systems when the statistical behavior of the sequences is closer to the uniform statistical distribution. The proposed system uses the inverted tent chaotic map (IT-1D), which has the same statistical behavior as the T-1D map. The fundamental algorithm used in this system was developed based on a 64-bit double precision format according to the numerical representation of floating point numbers defined in the IEEE-754 standard. The proposed system is analized using mechanical statistic tools and some statistical tests defined in the NIST 800-22SP (USA) standard. The main contribution of this work is the possibility of generating binary sequence of pseudorandom appearance by a procedure implemented in an FPGA device that translates real numbers to natural numbers preserving the statistical properties of sequences of real numbers that can be generated with the tent chaotic map in its original definition domain.


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## Body

## 1. Introduction

Chaotic systems have interesting features such as their sensitivity to initial conditions, the use of control parameters, and the ergodicity and mixing properties. These features have a great impact and application on cryptographic systems because they match diffusion and confusion properties of the cryptographic systems required by Information Theory. In this paper, the piecewise linear chaotic maps are the chaotic systems used in the implementation of the proposed digital noise generator. Basically, a chaotic map is defined in a specific intervalI=[a,b]∈ℜ and generates a dispersion process based on its sensitive dependence to initial conditions. This kind of maps can offer uniformly distributed binary sequences and then can be used as deterministic generators of unpredictable appearance sequences. There are some published works related with the application of Chaos Theory to the generation of noise sequences and cryptographic systems. In 2011, Rojas-Lopez [1] proposed a block cipher using a chaotic map and scaling and discretizing processes. In 2010, Qi et al., [2] proposed a switched chaotic system to generate pseudorandom sequences. In 2011 Dabal and Pelka [3] presented a stream cipher based on a logistic map for real time applications. Also in 2010, Pande and Zambreno [4] presented a stream cipher based on a variant of the logistic map.On the architecture of the system proposed in this paper the one-dimensional tent chaotic map (T-1D map) was used. This map has been extensively studied [5, 6] due to its simplicity of hardware and software implementations. The T-1D map is generally evaluated on the domain of real numbers, but when it is implemented in a digital system two options must be considered: (1) the scaling and discretizing processes of the T-1D map to be used on the natural numbers domain, and (2) the use a dictionary of binary words related to the real numbers produced by the T-1D map. In both alternatives the final sequence must be restricted to the interval [0,2n], where n is the number of bits in each resulting binary word.For the implementation of the T-1D map on an FPGA device it is necessary to take account of different aspects, like the limitation of logic resources in the FPGA device, the efficiency of the designed circuit, and the criteria of cost and velocity. Additionally, a digital noise generator must have good statistic properties to be used in cryptographic systems, that is, its statistical behavior must be similar to the uniform statistical distribution.In this work a variant of the T-1D map has been proposed to implement the digital noise generator. This variant of T-1D map is named inverted tent map (IT-1D), which has a similar statistic behavior to the T-1D map. IT-1D map has been used due to the possible reduction of the logic elements used to design the digital noise generator in an FPGA device.The architecture of the proposed digital noise generator is based on four modules: (a) Control System Module (CSM), (b) Arithmetic Module (AM), (c) Register Module (RM), and (d) Constant Register Module (CRM). The functionality of each module is described in Section3 of this paper.The algorithm that define the IT-1D map was developed using a 64-bit double precision format, according to the floating point numerical representation defined in the standard IEEE-754 [7] and it is analyzed using mechanical statistic tools such as the bifurcation diagram and the trajectories diagram.


## 2. Implementation of Inverted Tent Map

The T-1D map family is a subclass of piecewise linear maps (PWL), which can be described according to [8, 9]. But, in this work, this map family can be expressed by
(1)fμ(xn)={2μxn+(1-μ2),a≤xn≤12,-2μ(xn-1)+(1-μ2),12<xn≤b.Equation (1) is an iterated function when xn+1=fμ(xn), which generates orbits ℘ℜ={x0,x1,x2,x3,…} that are sequences of real numbers defined at [a,b]∈ℜ with a<b∈[0,1]. Each orbit produced by iterating (1) depends on an initial condition xo, which is known but arbitrarily selected and a control parameter, μ. Both parameters are defined on the interval [a,b]. Figure 1(a) shows the graphic representation for the T-1D map, which has a maximum at x=0.5 and two piecewise linear segments in the intervals, [0,0.5] and (0.5,1].Graphical representation of tent chaotic map: (a) T-1D and (b) IT-1D maps.
(a)
(b)On the other hand, the IT-1D map is expressed by (2) and graphically represented by Figure 1(b) one has
(2)fμ(xn)=μ(2|xn-0.5|)+(1-μ2).To observe the dispersion process produced by these chaotic maps, (1) and (2) must be evaluated using different values of μ to generate the bifurcation diagram. These diagrams are showed in Figures 2(a) and 2(b) to (1) and (2), respectively. Notice that when μ→1 the sequences are more disperse in both cases.Bifurcation diagram of tent maps: (a) T-1D and (b) IT-1D maps.
(a)
(b)As mentioned before, there are two alternatives for the implementation of the T-1D and IT-1D maps in a digital electronic circuit:(1), realize the scaling and discretizing processes on the chaotic map, or (2) the use of a dictionary that associates each real number produced by the chaotic map to a binary number of n bits according to some associating rules. Considering the analysis realized by Martínez-Ñonthe et al. [10], a discretized and scaled chaotic map is an approximation of the original chaotic map; thus, a new domain interval at the integer numbers appears. In other words, fμ(xn) defined at [0,1]∈ℜ, is transformed in a new function σμ(xn), where n is the iteration number of the chaotic map is transformed in a new function σμ(xn) defined at [0,2i]∈ℕ, where σμ(xn) depends on the precision of the used binary word considering i bits. This alternative produces binary sequences, which do not have a statistical behavior congruent with the original chaotic map, since the numbers rounding produced by the discretization process induces an error. This error is propagated and increased with each iteration of the chaotic map, and then the statistical behavior of the resulting sequence of real numbers is strongly affected. In this sense, because T-1D map is a PWL map and the representation of each number has a finite size, an initial condition applied to the chaotic map is really a macroscopic number, which is an ensemble of numbers in the form
(3)x=0·b1b2b3b4⋯bn.This expression corresponds to the numbers set with cardinality2n. Thus, the digital noise generator will produce real numbers, which are represented by a finite set instead of an infinite set. Therefore, it is necessary to define in the FPGA device the registers with the appropriate length. This consideration defines the memory resources required for the FPGA device.Another alternative to avoid the scaling and discretizing processes of the chaotic maps was described by Martínez-Ñonthe et al. in 2011 [11]. This alternative is used in the architecture of the digital noise generator proposed in this work. This alternative for a chaotic map fμ:[a,b]→[a,b]∈ℜ defines a regular partition A={A1,…,AS} of S intervals, in which each interval At with t=1,…,S has a length given by
(4)L(At)=L=b-aS.In this case, the generated orbits are conformed by natural numbers depending on the subinterval to which the respective real number belongs. This new orbit of natural numbers can be expressed by℘ℕ={y0,y1,y2,y3,…}, in [0,2i]∈ℕ. The relationship between ℘ℜ and ℘ℕ is given by
(5)ym=dec(At),if(IAt(xm))=1,
where m=1,2,3,4,…,  t=1,2,3…S,dec(At) represents the decimal value of the subinterval At, and IAt(xm) is the belong function, which indicates if xm is in At according to following expression:
(6)IAt(x)={1,ifx∈At0,ifx∉At.The second alternative is more complex to be designed than the first, because it considers the implementation of the chaotic map and a specific associating function. According to Martínez-Ñonthe et al. in 2011 [11], this second alternative offers better results, since the statistical behavior of the orbits conformed by natural numbers is closest to the statistical behavior of the orbits conformed by real number produced by the chaotic map. Notice that in this alternative the floating point representation of the real numbers is the unique factor that will affect the resulting orbits. Using the same initial condition, the first alternative generates orbits of natural numbers very different from the real orbits due to the discretization process of the chaotic map. Therefore, their statistical behavior will be different.In order to implement the IT-1D map in Xilinx FPGA devices, it is needed to consider that (2) has four constants: −0.5, 0.5, 1, and 2, which must be represented using a floating point format according to the digital core design of Xilinx defined on [12]. Therefore, the arithmetic operations must be implemented considering that the length of the constants must be the same as the data length (64 bits). The definition of the constants in the hardware implementation allows the realization of the arithmetic operations directly and, so, the temporary storage of data in some register will be avoided. In this way, there are only two variables, μ and xn, in (2) that must be considered in calculations. Notice that (1) has the same constants used in (2). In both cases, the term 0.5(1-μ) must be considered through a sum. Next, the number of operations to perform must be defined. In (2) three sums and three multiplications are made. The absolute value of the first term in (2) is obtained through a logic AND operation between the sum and the known value 0x7FFFFFFFFFFFFFFF. This operation changes the most significative bit of the sum to zero. Regarding (1), in first instance, two cases must be identified comparing the value of xn with the constant 0.5. In the first case, when xn≤0.5, three multiplications and two sums are made. On the second case, when xn>0.5, three sums and three multiplications are required and, additionally, the constants −1 and −2 must be declared.Due that the proposed system will be considered in a communications system to protect voice signals, we considered that the voice samples are obtained from the PCM frames, which have a length of 13 bits. In this way, it is a requirement to design a digital noise generator that must produce 13-bits binary numbers. Therefore, the expression in (3) must consider n=13 and in (4) the partition size must be S=213. In the hardware implementation of the proposed system additional considerations were made and they are described in the following sections. Table 1 shows a comparison of the number of arithmetic operations realized with both chaotic maps. It is remarkable that also the operations number is similar, but in the case of T-1D map some other processes are needed, like a comparator to evaluate if xn≤0.5 or xn>0.5 in (1).Table 1
Arithmetic operations required.
Chaotic map
Operations(multiplier module)
Operations(adder module)
T-1D
3
2
3
3
IT-1D
3
3


## 3. FPGA Architecture of the Noise Generator

Figure3 shows the proposed digital noise generator. In Figure 3(a), the noise generator can be designed using the T-1D or IT-1D map, which must be initialized with 64-bit real numbers but, at the end, the noise generator must produce natural numbers using a 13-bit representation. Figure 3(b) shows the architecture of the proposed noise generator. This architecture is based on (2) and uses a 64-bit data bus for the information exchange. The implementation of (1) uses a similar architecture. However, there are two variants: (a) CSM has additional state controls which are used to an adequate representation; (b) the resulting architecture is based on the use of RAM instead of the registers block.(a) Digital noise generator. (b) Hardware architecture to considering T-1D or IT-1D maps.
(a)
(b)


### 3.1. Control System Module (CSM)

It is based on a finite state machine to communicate with RM using the 128-bit PC register, which introduces togetherμ and x0 in parallel form. Next, the d1-d2 register separates μ and x0 in a 64-bit length each one. Additionally, the output of AM is introduced to the register named evaluation, which indicates if the operations required in (1) or (2) were completed. If the operations were completed the content of the evaluation register is sent to CRM; in other cases, that information is sent to the PC register to be stored in RM.


### 3.2. Arithmetic Module (AM)

It is defined to carry on the sum and multiplication with 64-bit format considering the IEEE-754 standard. These arithmetic operations are described as follows.


#### 3.2.1. Floating Point Sum Module

This module calculates the sum of two floating point numbers considering that two numbersz and w can be defined according to
(7)z=mx2xe,w=my2ye,
where e=E-Ebias, E is the normalized value of the exponent value, Ebias is a constant equal to 1023, which depends on the precission used in the calculations, and m represents the mantissa. Also, this Arithmetic Module must cover the representations defined by
(8)z+w=(mx2xe-yx+my)2ye=(mx+my2ye-xe)2xe.Figure4 shows the flowchart of the sum module implementation. This algorithm is based on the standard IEEE-754. For the implementation of a floating point sum the following considerations must be observed. (1) For each number, exponent and mantissa must be previously separated. (2) A new representation for the original exponent must be obtained using the lower possible integer and then the mantissa must be right shifted the number of positions that correspond, according to the difference between original exponent and its new representation; (3) The exponent of the result obtained for the realized arithmetic operations must be equal to the greater exponent between the exponents of the two involved numbers. (4) The sum and subtraction operations must be performed using the mantissa. (5) If it is necessary, the result obtained from arithmetic operations must be normalized. This process consists of shifting the bits of the mantissa from left to right; thus the exponent value will change. (6) In the calculations of these arithmetic operations the overflow conditions must be checked.Figure 4
Algorithm of floating point sum module.


#### 3.2.2. Floating Point Multiplicative Module

The operations made by this module are showed in Figure5 and when two variables are considered the arithmetic multiplication can be represented by
(9)a*b=mx2xe×my2ye=(mx×my)2xe+ye.Figure 5
Floating point multiplier module.This module consists of the following steps.(1) Equal to step (1) in the floating point sum module. (2) Realize the sum or subtraction between exponents of each variable. (3) Multiply the mantissas of the two involved numbers and then the resulting sign must be determined in the operation realized in the step (2). (4) Normalize the result obtained in step (2) according to the procedure indicated in step (1). (5) The overflow conditions must be verified.Finally, Table2 shows the time access for the two implemented operations for the IT-1D map.Table 2
Latencies and data widths of AM.
Module
Data widths
Latency (clock cycles)
Inputs
a
,
b (64 bit)
—
Multiplier
64 bit
8
Adder
64 bit
8
Output
Result (64 bit)
—


### 3.3. Constant Register Module (CRM)

The registers defined in this module are 64-bit constants arrays. However, due to the savings of logic elements required on the FPGA device the reduction of constants to 24 bits were made. CRM is showed in Figure6 and its functionality is defined according to the flowchart showed in Figure 7.Figure 6
Constant Register Module.Figure 7
Flowchart of Constant Register Module.Additionally, it must be noticed that the cardinality of the defined domain for the digital noise generator is213=8192. In this way, in CRM four registers are defined. (a) BInf. It is based on an array composed by 33 registers with 24 bits each one. These registers define the limits of 32 subsets, which correspond to the partition of the domain for the digital noise generator. The prefix of the real number labeled as prefix24(xn) will be searched in BInf as a first approximation to the regular partition A. Notice in Figure 7 that j is the auxiliary variable in the searching process on BInf. Therefore, the final searching to find the corresponding number is limited to 256 possibilities for each subset; this searching will be performed using InterV13b. (b) InterV13b. It defines 32 subsets with 256 elements each one. prefix24(xn) will be searched now in this register allowing the determination of the particular natural number that must be used to represent each real number. The length of this register is 213 × 24 bits. (c) MMDirInf and MMdisSup. These registers contain the natural numbers in a representation of 13 bits, which are used to generate the output sequence. Notice in Figure 7 that z is the auxiliary variable in the searching process on InterV13b and it is used to compare the values in MMDirInf with the real number xn. When the value of xn is found in MMDirInf, z contains the associated natural number, which has 13-bit length. These natural numbers will be associated to the numbers found using InterV13b. These registers have a length of 32×13 bits, and they work according to Figure 6, which shows the functionality of these registers by a flowchart. Additionally, two auxiliary variables are defined to compare the real number produced by chaotic map with the found number in the searching process described previously. These auxiliary variables are sup64 and inf64, which are conformed concatenating the found 24-bit number and a 40-bit binary word, which contains 40 zeros. In Figure 7, the symbol ⊙ has used to represent the concatenation function.


## 3.1. Control System Module (CSM)

It is based on a finite state machine to communicate with RM using the 128-bit PC register, which introduces togetherμ and x0 in parallel form. Next, the d1-d2 register separates μ and x0 in a 64-bit length each one. Additionally, the output of AM is introduced to the register named evaluation, which indicates if the operations required in (1) or (2) were completed. If the operations were completed the content of the evaluation register is sent to CRM; in other cases, that information is sent to the PC register to be stored in RM.


## 3.2. Arithmetic Module (AM)

It is defined to carry on the sum and multiplication with 64-bit format considering the IEEE-754 standard. These arithmetic operations are described as follows.


### 3.2.1. Floating Point Sum Module

This module calculates the sum of two floating point numbers considering that two numbersz and w can be defined according to
(7)z=mx2xe,w=my2ye,
where e=E-Ebias, E is the normalized value of the exponent value, Ebias is a constant equal to 1023, which depends on the precission used in the calculations, and m represents the mantissa. Also, this Arithmetic Module must cover the representations defined by
(8)z+w=(mx2xe-yx+my)2ye=(mx+my2ye-xe)2xe.Figure4 shows the flowchart of the sum module implementation. This algorithm is based on the standard IEEE-754. For the implementation of a floating point sum the following considerations must be observed. (1) For each number, exponent and mantissa must be previously separated. (2) A new representation for the original exponent must be obtained using the lower possible integer and then the mantissa must be right shifted the number of positions that correspond, according to the difference between original exponent and its new representation; (3) The exponent of the result obtained for the realized arithmetic operations must be equal to the greater exponent between the exponents of the two involved numbers. (4) The sum and subtraction operations must be performed using the mantissa. (5) If it is necessary, the result obtained from arithmetic operations must be normalized. This process consists of shifting the bits of the mantissa from left to right; thus the exponent value will change. (6) In the calculations of these arithmetic operations the overflow conditions must be checked.Figure 4
Algorithm of floating point sum module.


### 3.2.2. Floating Point Multiplicative Module

The operations made by this module are showed in Figure5 and when two variables are considered the arithmetic multiplication can be represented by
(9)a*b=mx2xe×my2ye=(mx×my)2xe+ye.Figure 5
Floating point multiplier module.This module consists of the following steps.(1) Equal to step (1) in the floating point sum module. (2) Realize the sum or subtraction between exponents of each variable. (3) Multiply the mantissas of the two involved numbers and then the resulting sign must be determined in the operation realized in the step (2). (4) Normalize the result obtained in step (2) according to the procedure indicated in step (1). (5) The overflow conditions must be verified.Finally, Table2 shows the time access for the two implemented operations for the IT-1D map.Table 2
Latencies and data widths of AM.
Module
Data widths
Latency (clock cycles)
Inputs
a
,
b (64 bit)
—
Multiplier
64 bit
8
Adder
64 bit
8
Output
Result (64 bit)
—


## 3.2.1. Floating Point Sum Module

This module calculates the sum of two floating point numbers considering that two numbersz and w can be defined according to
(7)z=mx2xe,w=my2ye,
where e=E-Ebias, E is the normalized value of the exponent value, Ebias is a constant equal to 1023, which depends on the precission used in the calculations, and m represents the mantissa. Also, this Arithmetic Module must cover the representations defined by
(8)z+w=(mx2xe-yx+my)2ye=(mx+my2ye-xe)2xe.Figure4 shows the flowchart of the sum module implementation. This algorithm is based on the standard IEEE-754. For the implementation of a floating point sum the following considerations must be observed. (1) For each number, exponent and mantissa must be previously separated. (2) A new representation for the original exponent must be obtained using the lower possible integer and then the mantissa must be right shifted the number of positions that correspond, according to the difference between original exponent and its new representation; (3) The exponent of the result obtained for the realized arithmetic operations must be equal to the greater exponent between the exponents of the two involved numbers. (4) The sum and subtraction operations must be performed using the mantissa. (5) If it is necessary, the result obtained from arithmetic operations must be normalized. This process consists of shifting the bits of the mantissa from left to right; thus the exponent value will change. (6) In the calculations of these arithmetic operations the overflow conditions must be checked.Figure 4
Algorithm of floating point sum module.


## 3.2.2. Floating Point Multiplicative Module

The operations made by this module are showed in Figure5 and when two variables are considered the arithmetic multiplication can be represented by
(9)a*b=mx2xe×my2ye=(mx×my)2xe+ye.Figure 5
Floating point multiplier module.This module consists of the following steps.(1) Equal to step (1) in the floating point sum module. (2) Realize the sum or subtraction between exponents of each variable. (3) Multiply the mantissas of the two involved numbers and then the resulting sign must be determined in the operation realized in the step (2). (4) Normalize the result obtained in step (2) according to the procedure indicated in step (1). (5) The overflow conditions must be verified.Finally, Table2 shows the time access for the two implemented operations for the IT-1D map.Table 2
Latencies and data widths of AM.
Module
Data widths
Latency (clock cycles)
Inputs
a
,
b (64 bit)
—
Multiplier
64 bit
8
Adder
64 bit
8
Output
Result (64 bit)
—


## 3.3. Constant Register Module (CRM)

The registers defined in this module are 64-bit constants arrays. However, due to the savings of logic elements required on the FPGA device the reduction of constants to 24 bits were made. CRM is showed in Figure6 and its functionality is defined according to the flowchart showed in Figure 7.Figure 6
Constant Register Module.Figure 7
Flowchart of Constant Register Module.Additionally, it must be noticed that the cardinality of the defined domain for the digital noise generator is213=8192. In this way, in CRM four registers are defined. (a) BInf. It is based on an array composed by 33 registers with 24 bits each one. These registers define the limits of 32 subsets, which correspond to the partition of the domain for the digital noise generator. The prefix of the real number labeled as prefix24(xn) will be searched in BInf as a first approximation to the regular partition A. Notice in Figure 7 that j is the auxiliary variable in the searching process on BInf. Therefore, the final searching to find the corresponding number is limited to 256 possibilities for each subset; this searching will be performed using InterV13b. (b) InterV13b. It defines 32 subsets with 256 elements each one. prefix24(xn) will be searched now in this register allowing the determination of the particular natural number that must be used to represent each real number. The length of this register is 213 × 24 bits. (c) MMDirInf and MMdisSup. These registers contain the natural numbers in a representation of 13 bits, which are used to generate the output sequence. Notice in Figure 7 that z is the auxiliary variable in the searching process on InterV13b and it is used to compare the values in MMDirInf with the real number xn. When the value of xn is found in MMDirInf, z contains the associated natural number, which has 13-bit length. These natural numbers will be associated to the numbers found using InterV13b. These registers have a length of 32×13 bits, and they work according to Figure 6, which shows the functionality of these registers by a flowchart. Additionally, two auxiliary variables are defined to compare the real number produced by chaotic map with the found number in the searching process described previously. These auxiliary variables are sup64 and inf64, which are conformed concatenating the found 24-bit number and a 40-bit binary word, which contains 40 zeros. In Figure 7, the symbol ⊙ has used to represent the concatenation function.


## 4. Results

A chaotic map generates a dispersion process using specific values of the parameter control and the initial condition on a particular interval. This process can be observed using three alternatives: (a) the bifurcation diagram (see Figure8), (b) the histogram of the produced sequences for different values of parameter control and initial conditions (see Figure 9), and (c) the trajectories diagrams, which show how the iterated chaotic map covers gradually the plane formed by xn and xn+1 depending on the parameter control and initial conditions (see Figure 10).Bifurcation diagrams obtained from sequences of natural numbers produced by the tent maps: (a) T-1D map and (b) IT-1D map.
(a)
(b)Histogram of the sequences produced by tent map consideringμ=0.9999, x0=0.45 and 1000 iterations of the chaotic map: (a) T-1D map, and (b) IT-1D map.
(a)
(b)Diagram showing the evolution of the trajectories using (a) T-1D map and (b) IT-1D map for 200 iterations withμ=0.9999 and x0=0.45.
(a)
(b)To observe the dispersion process produced by the chaotic maps the tent map was implemented using an FPGA device SPARTAN 3E XC3S500e [13]. Figures 8(a) and 8(b) show the bifurcation diagrams for the T-1D and IT-1D maps, respectively, considering a 213 domain and natural numbers in the output sequences. Notice that Figure 8 has a similar behavior to Figure 2. The dispersion process produced by chaotic maps occurs when μ≥0.5 starting with two bands and then when μ≥0.73 the dispersion process occurs in a lonely band until reaching a maximal dispersion when μ→1. The bifurcation diagrams in Figure 8 have been built considering that the control parameter is increased using steps of Δμ=0.0001 and an initial condition x0 = 0.45. This behavior can be observed also in the histograms of produced sequences (see Figure 9) and the trajectories diagrams (see Figure 10) if the parameter control is changed.Figures10(a) and 10(b) show the trajectories diagrams considering 200 iterations, x0=0.45 and μ=0.9999. Notice that the statistical behavior is close to a uniform distribution, and then the produced sequences can be considered pseudorandom sequences. Table 3 shows the hardware requirements when the tent maps are implemented in an FPGA device using (1) and (2).Table 3
Hardware required by T-1D and IT-1D maps in a FPGA device.
Logic utilization
Available
Utilization(IT-1D)
Utilization(T-1D)
Number of slice flip flops
9,312
2,169(23%)
2,689(28%)
Number of 4 input LUTS
9,312
2,376(25%)
2,674(28%)
Number of occupied slices
4,656
1,853(39%)
2,146(46%)
Total number of 4 inputs LUTS
9,312
2,535(27%)
2,867(30%)
Number used as logic
—
2,313
2,575
Number used as a route thru
—
159
193
Number used as shift register
—
63
99
Number of bonded IOBs
232
15(6%)
194(83%)
Number of MULT18X18SIOs
20
16(80%)
16(80%)
Average fan-out of nonclock nets
—
2.43
2.60
Number of RAMB16s
20
—
1(5%)Table4 shows the hardware requirements when the IT-1D map is implemented in an FPGA device when the regular partition is defined to translate the real numbers to natural numbers. Figure 11 shows the evidence of the sequences of natural numbers produced by the noise generator proposed in this work. These evidences have been obtained using programs defined with MATLAB and ISIM-Xilinx toolboxes.Table 4
Hardware resources required by IT-1D when the regular partition is defined to translate the reals numbers to natural numbers.
Logic utilization
Available
Utilization (IT-1D)
Number of slice Flip flops
9,312
2,287 (24%)
Number of 4 input LUTS
9,312
2,926 (31%)
Number of occupied slices
4,656
2,167 (46%)
Total number of 4 inputs LUTS
9,312
3,098 (33%)
Number used as logic
—
2,863
Number used as a route-thru
—
172
Number used as shift register
—
63
Number of bonded IOBs
232
15 (6%)
Number of MULT18X18SIOs
20
16 (80%)
Average fan-out of nonclock nets
—
2.66Sequences of natural numbers produced by noise generator using tent map. (a) simulation results using programs defined in Xilinx and (b) simulation results using programs defined in MATLAB.
(a)
(b)Finally, to show that the sequences produced by the digital noise generator proposed in this work have random appearance, some statistical tests of the NIST 800-22SP standard were applied. Table5 shows the statistical tests used to evaluate the sequences.Table 5
Statistical tests applied to the sequences produced by the digital noise generator.
Test
P value
Result
Monobit Frequency Test
0.2301393404
True
Block Frequency Test
0.2727182697
True
Runs Test
1.9119631770
True
Spectral Test
0.6036850480
True
Maurer’s Universal Test
0.4712780830
True
Cumulative Sums Test
0.2471130325
True
Random Excursions Test
0.3140488026
True
Random Excursions VarTest
0.2093446041
TrueThese results are congruent with the statistical behavior showed in Figure9 relative to the natural number sequences produced by the digital noise generator proposed in this work. Due to the simplicity of the tent map the statistical tests relative to linear complexity were not considered.


## 5. Conclusions

This paper presents a configurable architecture in a small capacity FPGA device that generates digital noise sequences. The proposed system is optimized and the resultant sequences are used to be combined with 13-bit length data. Some goals that were achieved on the design of the proposed system are the following. the architecture of the digital noise generator proposed in this work was implemented using two versions of the tent chaotic map, T-1D and IT-1D maps. Both alternatives have similar performance characteristics. The experimental work has considered evaluating the functionality of the architecture proposed. Regarding the precision to represent natural and real numbers, it is possible to have similitudes with the processes defined in a personal computer. The results obtained from MATLAB represent the evidence of the behavior of the proposed system. The digital noise generator has been developed using a sequential architecture, where theCSM coordinates the activities of different modules. All registers used in this implementation have been depurated to avoid the delays and excessive clock cycles. An example of this one is that the Arithmetic Module takes 8 clock cycles for placing data after an operation.Considering the bifurcation diagrams, it can be assumed that the natural numbers sequences produced by the digital noise generator have a similar statistical behavior as the real numbers sequences produced by the tent chaotic map.The architecture of the digital noise generator produces noise sequences using the tent map when the control parameter isμ≥0.73. This behavior is shown by bifurcations diagrams, trajectories diagrams, and statistical distribution. The precision to represent the natural or real numbers is an important factor when the noise sequences are produced an FPGA device. For this reason, the proposed system was defined using the IEEE-754 standard. If the precision to represent the numbers is increased the demand of logic resources will be increased and the design of the system will be more complicated.The proposed digital noise generator avoids the scaling and discretization processes on the chaotic map; instead of this an associating rule was defined to relate each real number with a natural number. The implementation of this function in an FPGA device considers a searching process established in two steps using a 24-bit prefix of each real number. We consider that this process must be optimized because the natural numbers in the noise sequences do not have the same permanence time in the output of the system (see Figure11).On the other hand, using some statistical test defined in the NIST 800-22SP standard, the pseudorandomness of the produced sequences was verified. Considering that the tent map is a simple chaotic system, statistical tests relative to the linear complexity were not applied.



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*Source: 849120-2012-10-04.xml*