# Mathematical Modeling and Performance Evaluation of 3D Ferroelectric Negative Capacitance FinFET

Authors: Sayem Ul Alam; Rukon Uddin; Md. Jahangir Alam; Ahamed Raihan; Sheikh S. Mahtab; Subrata Bhowmik
Journal: Modelling and Simulation in Engineering
 (2022)

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## Abstract

Ferroelectric negative capacitance materials have now been proposed for lowering electronics energy dissipation beyond basic limitations. In this paper, we presented the analysis on the performance of negative capacitance (NC) FinFET in comparison with conventional gate dielectrics by using a separation of variables approach, which is an optimal quasi-3D mathematical model. The result has been signified steeper surface potential (ψ), lower threshold voltage (Vth), 1.2 mA of on-state current (Ion), and enhanced immunity of negative capacitance FinFET against short channel effects (SCE’s) like 35.3 mV/V of drain-induced barrier lowering (DIBL), 60 mV/dec of subthreshold swing (SS) along with smallest off state current (Ioff) among another conventional gate dielectric. Hence, NC FinFET can be a potential candidate for low power and high-performance device.


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## Body

## 1. Introduction

Lower power consumption is now highly concerned issue for developing digital technology using metal oxide semiconductor field effect transistors (MOSFETs), which follows Moore’s law and, down scaling the size of semiconductor device improves number of transistors per chip, exponentially increases functionality. Nevertheless, lower scale transistors are more prone to short channel effects (SCE’s) [1]. A significant short channel phenomenon known as threshold voltage roll off occurs when the threshold voltage drops as the gate length decreases. Short-channel MOSFETs switch on at a smaller gate voltage than long-channel MOSFETs as a consequence [2–4]. By lowering the channel length, the area of the gate oxide and the gate oxide capacitance have dropped. But, a minimum amount of gate oxide capacitance is required for improved channel control [5]. This is accomplished by lowering the thickness of the gate oxide. Quantum mechanical tunneling happens when the thickness of SiO2 is less than 1.2 nm [6, 7]. Gate oxide leakage current rises when the gate oxide is scaled further. In addition, the device’s power usage increases significantly when it is turned off. This difficulty may be mitigated by utilizing a high-k dielectric material, which has a large dielectric constant. The use of a high-k dielectric material allows for a larger gate oxide than SiO2 with the same oxide capacitance. The phrase equivalent oxide thickness, or EOT, refers to the thickness of a SiO2 film that must be employed in substitute of a high-k dielectric to achieve the same oxide capacitance [7]. Nitride SiO2 were used to increase dielectric constant about 5 along with reduction of EOT to 2 nm [8]. Besides that, HfO2 dielectric-based FET technology enable down scaling of EOT to 0.8 nm in recent device [9]. Nevertheless, even if EOT can be reduced to zero, some basic limits resists decline of Vdd [10]. One of the limits addressed as, “Boltzmann limit,” because of that it is not possible to decrease Vdd below 0.5 V [11]. For overcoming this limit, band to band tunneling can be useful. But, tunneling device has lower on-state current [12, 13]. Moreover, it is proposed that whenever the insulator capacitance is negative, then device can overcome Boltzmann limit by reducing Vdd further. The negative capacitance (NC), in this situation, would result in an internal amplification of the surface potential in response to the applied gate voltage Vg [13]. In 2016, transient NC was measured in ferroelectric HfO2 with Gd doping by the application of low voltage [13]. At the same time, similar NC effect was verified in ferroelectric Zr doped hafnium dioxide, widely known as HZO [14]. NC FET with HZO exhibit larger on/off ration at constant on state current, reported in 2018 [16]. GaAs/InN Tunnel NC FET shows higher immunity to Short Channel Effects (SCE’s) [17]. It is expected that if gate oxide is replaced by ferroelectric negative capacitance material, the performance of device can be improved. In this paper, we used HZO as ferroelectric negative capacitance material to form a FinFET structure. The performance parameters like threshold voltage, surface potential profile, on-state current, and short channel effects (SCE’s) of HZO with silicon channel are investigated in comparison with HfO2 and Al2O3 as gate oxide by using compact mathematical model. The physical architecture of our proposed 3D FinFET can be observed from different direction in Figure 1, and the parameters value used for the architecture has been listed in Table 1.Figure 1
(a) 3D-FinFET Cross-sectional diagram. (b) XY direction. (c) XZ direction.
(a)(b)(c)Table 1
Proposed device parameters.
SymbolDesignationValueLeffEffective channel length16 nmHfinHeight of fin10 nmTfinThickness of fin4 nmToxOxide thickness1 nmNchChannel concentration1016 cm−3TboxBuried oxide thickness20 nm


## 2. Physical Architecture

Table2, describes the research on NC-FinFET from 2017 to 2020, where the impact of negative capacitance material can easily be realized.Table 2
Previous study on NC-FinFET.
HighlightsTfin (nm)Tox (nm)Hfin (nm)Lg (nm)SS (mV/decade)Year [reference]Sub-10 nm NC-FinFET is analyzed operating at 0.25 V30.7—9—2017 [18]Investigation of CMOS logic circuits using NC-FinFET8—3430—2017 [19]FE capacitor of Sub-60 mV/decade NC-FinFET with sub-10 nm101.4409036.312017 [20]NC-FinFET with minimal hysteresis of 0.48Vand sub-20 mV/dec SS401.44070<202017 [21]Design and evaluation of performance of SRAM using 7 nm-node NC-FinFET6.513221—2017 [22]Analysis of fin-LER variability in NC-FinFET9.622522—2017 [23]TCAD simulation to design NC-FinFET to avoid instability of NC state40.5—20482017 [24]Analysis of process variations impact on NC-FinFET6.513221—2018 [25]Analysis of spacer designs for FinFET and NC-FinFET60.9421665.62019 [26]Ge NC-FinFET in presence of fixed trap charges is analyzed81920—2019 [27]Improved SS and drain current in NC-FinFET771140405002034.5532019 [41]Relation between TFE and stability of 6 T NC-FinFET-based SRAM cell80.654220—2019 [28]GIDL issue in NC-FinFET is analyzed70.95020752020 [29]


## 3. Mathematical Model

### 3.1. Surface Potential Model

A field effect transistor (FET) is a voltage-controlled semiconductor device. Electrostatic potential between source and drain in FET is induced by DC biasing voltage. The area between the source and drain is known as channel or Si-body and the electrostatic potential in channel is controlled by DC gate voltage. Generally, FinFET exhibit three-dimensional surface potential. The surface potential can be expressed by the following equation [30, 31].
(1)δ2ψx,y,zδx2+δ2ψx,y,zδy2+δ2ψx,y,zδz2=qNchϵch,where Nchis channel doping, ϵch is permittivity of channel material, and ψ is surface potential.The total surface potential can be expressed through the following equation [30],
(2)ψx,y,z=ψsb+EsbHfin−x+q2ɛsiNAHfin−x2+∑r=1∞1sinhγrLeffVr′sinhγry+VrsinhγrLeff−ysinγrx+εsiεoxtoxfγrcosγrx∑s=1∞∑r=1∞PsrsinhχsrTfin−z+sinhχsrzsinαsy−LeffcosαsLeffsinβrx+εsiεoxtoxfβrcosβrx.


### 3.2. Threshold Voltage Model

Threshold voltage is another important parameter for MOSFET, which can be defined by the minimal voltage required for turning on MOSFET. Threshold voltage can be derived by following equations:(3)VTF=VTF0−ΔVTF1−ΔVTF2.VTF0,ΔVTF1,andΔVTF2can be calculated as follows [32]:
(4)VTF0=Vfbf+2ϕb+QitfCoxf−εchCoxfdψ1Dx∂xx=0=Vfbf+1+Cs+CitfCoxf2ϕb−CsCoxfψsb+qNchts2Coxf,ΔVTF1=εchCoxf∂ψ2Dx,y∂xx=0,y=yminf=εchCoxf∑r=1∞γrsinhγrLeff×Vr′sinhγryminf+VrsinhγrLeff−yminf,ΔVTF2=εchCoxf∂ψ3Dx,y,z∂xx=0,y=yminf,z=Tfin/2=2εchCoxf∑s=1∞∑r=1∞PsrsinhχsrTfin2×sinαsyminf−LeffcosαsLeffβr.


### 3.3. Drain Current Model

Subthreshold current, the small amount of drain current, which can flow through the channel for below threshold voltage, is an important parameter for determining the performance of MOSFET, which can be expressed by following equation [33]:
(5)IDS=qμnkT/qni2/Na1−exp−VDS/kT/q∫0Leffdy/∫0Hfin∫0Wfinexpqψx,y,z/kTdxdz.


### 3.4. Transconductance

Transconductance, directly related to gain, determines how rapidly a transistor may activate when sweeping the gate voltage. [34]. Due to change in surface charge, a higher value of transconductance cause higher drain current, which is responsible for increasing device sensitivity. Operation point of a sensor can be determined by using the maximum transconductance gate voltage. Most of the devices tested have maximum transconductances greater than 10 uS. [35]The transconductance can be defined by following equation:(6)gm=dIDdVGS.


#### 3.4.1. Drain Induced Barrier Lowering (DIBL)

DIBL reduces the nanoscale MOS threshold voltage by modifying the source-to-drain potential barrier. This permits the device channel to conduct lesser gate voltages. [36]. The DIBL is calculated as the proportion of the difference in threshold voltage observed at the minimal value to the maximum priority of the drain current. Shift in threshold voltage (Vth) to alter in drain voltage (Vds) is characterized as a drain-induced barrier lower [37].
(7)DIBLmVV=ΔVthΔVds.


#### 3.4.2. Subthreshold Swing

The switching effectivity of low power digital device can be evaluated by the characteristics of drain current at the subthreshold region of device, which is commonly known as subthreshold swing. The analytical model of subthreshold swing is developed by solving the Poisson’s equation in the channel region at cutline positionx=Tf/2, y=Hfin [38].According to [39], the subthreshold swing expression is
(8)S=q2.3kT∂Ψx,y,z∂VGS−1,S=q2.3kT∂ψ1D∂VGS+∂ψ2D∂VGSz=0+∂ψ2D∂VGSz=Lf+∂ψ3D∂VGSy=0+∂ψ3D∂VGSy=Hfin1.


### 3.5. Off Current

Off current is directly depending on Subthreshold Slope (SS). It can be calculated by following equation [40]:
(9)Ioff=100WL10−VTh/SS.


### 3.6. Short Channel Effects in NC-FinFET

Negative capacitance is used to counteract short-channel effects in highly scaled FETs [18, 20, 22]. The key short channel parameter of inverse subthreshold swing can be written as
(10)SS=2.3KBTq∂Vg∂ψs=2.3KBTq1+CdipCox,whereψs is surface potential, KBT is multiplication of Boltzman constant and temperature, and Cdep and Cox are depletion layer capacitance and gate oxide capacitance. In conventional MOSFET, the factor 1+Cdip/Cox is always above unity. By making oxide capacitance negative in nature is one method to lower the value of Subthreshold Swing. If ferroelectric material, which adopts the property of negative capacitance, is chosen, this will be attainable [15, 42–44]. Equivalent oxide capacitance Cox′ in NCFET is achieved by adding ferroelectric CF and dielectric capacitance Cox in series.
(11)Cox′=CoxCFCF−Cox.Therefore, the NCFET’s subthreshold swing can be represented as(12)SS=2.3KBTq∂Vg∂ψs=2.3KBTq1+CdipCox′.Confirming that theSS for the condition can be lowered to the Boltzmann limit.Drain Induced Barrier Lowering (DIBL) can be calculated as mentioned in Equation (7). As DIBL depends on threshold voltage, threshold voltage of NCFET computed by the following expression:
(13)VTh′=VTh0+ηVd,whereη is the factor of DIBL and VTh0 is threshold voltage at zero drain voltage. The factor of DIBL is positive for conventional MOSFET, on the other hand negative for NCFET [45]. With the increment of drain voltage, the threshold voltage will increase in NCFET and that is opposite to conventional MOSFET. This results to negative DIBL factor. Hence, DIBL is lower for NCFET.


## 3.1. Surface Potential Model

A field effect transistor (FET) is a voltage-controlled semiconductor device. Electrostatic potential between source and drain in FET is induced by DC biasing voltage. The area between the source and drain is known as channel or Si-body and the electrostatic potential in channel is controlled by DC gate voltage. Generally, FinFET exhibit three-dimensional surface potential. The surface potential can be expressed by the following equation [30, 31].
(1)δ2ψx,y,zδx2+δ2ψx,y,zδy2+δ2ψx,y,zδz2=qNchϵch,where Nchis channel doping, ϵch is permittivity of channel material, and ψ is surface potential.The total surface potential can be expressed through the following equation [30],
(2)ψx,y,z=ψsb+EsbHfin−x+q2ɛsiNAHfin−x2+∑r=1∞1sinhγrLeffVr′sinhγry+VrsinhγrLeff−ysinγrx+εsiεoxtoxfγrcosγrx∑s=1∞∑r=1∞PsrsinhχsrTfin−z+sinhχsrzsinαsy−LeffcosαsLeffsinβrx+εsiεoxtoxfβrcosβrx.


## 3.2. Threshold Voltage Model

Threshold voltage is another important parameter for MOSFET, which can be defined by the minimal voltage required for turning on MOSFET. Threshold voltage can be derived by following equations:(3)VTF=VTF0−ΔVTF1−ΔVTF2.VTF0,ΔVTF1,andΔVTF2can be calculated as follows [32]:
(4)VTF0=Vfbf+2ϕb+QitfCoxf−εchCoxfdψ1Dx∂xx=0=Vfbf+1+Cs+CitfCoxf2ϕb−CsCoxfψsb+qNchts2Coxf,ΔVTF1=εchCoxf∂ψ2Dx,y∂xx=0,y=yminf=εchCoxf∑r=1∞γrsinhγrLeff×Vr′sinhγryminf+VrsinhγrLeff−yminf,ΔVTF2=εchCoxf∂ψ3Dx,y,z∂xx=0,y=yminf,z=Tfin/2=2εchCoxf∑s=1∞∑r=1∞PsrsinhχsrTfin2×sinαsyminf−LeffcosαsLeffβr.


## 3.3. Drain Current Model

Subthreshold current, the small amount of drain current, which can flow through the channel for below threshold voltage, is an important parameter for determining the performance of MOSFET, which can be expressed by following equation [33]:
(5)IDS=qμnkT/qni2/Na1−exp−VDS/kT/q∫0Leffdy/∫0Hfin∫0Wfinexpqψx,y,z/kTdxdz.


## 3.4. Transconductance

Transconductance, directly related to gain, determines how rapidly a transistor may activate when sweeping the gate voltage. [34]. Due to change in surface charge, a higher value of transconductance cause higher drain current, which is responsible for increasing device sensitivity. Operation point of a sensor can be determined by using the maximum transconductance gate voltage. Most of the devices tested have maximum transconductances greater than 10 uS. [35]The transconductance can be defined by following equation:(6)gm=dIDdVGS.


### 3.4.1. Drain Induced Barrier Lowering (DIBL)

DIBL reduces the nanoscale MOS threshold voltage by modifying the source-to-drain potential barrier. This permits the device channel to conduct lesser gate voltages. [36]. The DIBL is calculated as the proportion of the difference in threshold voltage observed at the minimal value to the maximum priority of the drain current. Shift in threshold voltage (Vth) to alter in drain voltage (Vds) is characterized as a drain-induced barrier lower [37].
(7)DIBLmVV=ΔVthΔVds.


### 3.4.2. Subthreshold Swing

The switching effectivity of low power digital device can be evaluated by the characteristics of drain current at the subthreshold region of device, which is commonly known as subthreshold swing. The analytical model of subthreshold swing is developed by solving the Poisson’s equation in the channel region at cutline positionx=Tf/2, y=Hfin [38].According to [39], the subthreshold swing expression is
(8)S=q2.3kT∂Ψx,y,z∂VGS−1,S=q2.3kT∂ψ1D∂VGS+∂ψ2D∂VGSz=0+∂ψ2D∂VGSz=Lf+∂ψ3D∂VGSy=0+∂ψ3D∂VGSy=Hfin1.


## 3.4.1. Drain Induced Barrier Lowering (DIBL)

DIBL reduces the nanoscale MOS threshold voltage by modifying the source-to-drain potential barrier. This permits the device channel to conduct lesser gate voltages. [36]. The DIBL is calculated as the proportion of the difference in threshold voltage observed at the minimal value to the maximum priority of the drain current. Shift in threshold voltage (Vth) to alter in drain voltage (Vds) is characterized as a drain-induced barrier lower [37].
(7)DIBLmVV=ΔVthΔVds.


## 3.4.2. Subthreshold Swing

The switching effectivity of low power digital device can be evaluated by the characteristics of drain current at the subthreshold region of device, which is commonly known as subthreshold swing. The analytical model of subthreshold swing is developed by solving the Poisson’s equation in the channel region at cutline positionx=Tf/2, y=Hfin [38].According to [39], the subthreshold swing expression is
(8)S=q2.3kT∂Ψx,y,z∂VGS−1,S=q2.3kT∂ψ1D∂VGS+∂ψ2D∂VGSz=0+∂ψ2D∂VGSz=Lf+∂ψ3D∂VGSy=0+∂ψ3D∂VGSy=Hfin1.


## 3.5. Off Current

Off current is directly depending on Subthreshold Slope (SS). It can be calculated by following equation [40]:
(9)Ioff=100WL10−VTh/SS.


## 3.6. Short Channel Effects in NC-FinFET

Negative capacitance is used to counteract short-channel effects in highly scaled FETs [18, 20, 22]. The key short channel parameter of inverse subthreshold swing can be written as
(10)SS=2.3KBTq∂Vg∂ψs=2.3KBTq1+CdipCox,whereψs is surface potential, KBT is multiplication of Boltzman constant and temperature, and Cdep and Cox are depletion layer capacitance and gate oxide capacitance. In conventional MOSFET, the factor 1+Cdip/Cox is always above unity. By making oxide capacitance negative in nature is one method to lower the value of Subthreshold Swing. If ferroelectric material, which adopts the property of negative capacitance, is chosen, this will be attainable [15, 42–44]. Equivalent oxide capacitance Cox′ in NCFET is achieved by adding ferroelectric CF and dielectric capacitance Cox in series.
(11)Cox′=CoxCFCF−Cox.Therefore, the NCFET’s subthreshold swing can be represented as(12)SS=2.3KBTq∂Vg∂ψs=2.3KBTq1+CdipCox′.Confirming that theSS for the condition can be lowered to the Boltzmann limit.Drain Induced Barrier Lowering (DIBL) can be calculated as mentioned in Equation (7). As DIBL depends on threshold voltage, threshold voltage of NCFET computed by the following expression:
(13)VTh′=VTh0+ηVd,whereη is the factor of DIBL and VTh0 is threshold voltage at zero drain voltage. The factor of DIBL is positive for conventional MOSFET, on the other hand negative for NCFET [45]. With the increment of drain voltage, the threshold voltage will increase in NCFET and that is opposite to conventional MOSFET. This results to negative DIBL factor. Hence, DIBL is lower for NCFET.


## 4. Result and Discussion

The performance parameter like surface potential, threshold voltage along with short channel effects have been studied for negative capacitance ferroelectric hafnium zirconium oxide (HZO) in FinFET (NC-FinFET). Surface potential along the channel length is shown for different dielectric material in Figure2, considering drain voltage 1 V. FinFET with HZO has higher potential around 0.9 V, while other dielectric-based FinFET has 0.79 V and 0.6 V simultaneously. Furthermore, the rise of potential in drain side of channel is steeper for NC-FinFET. This is due to ferroelectric negative capacitance property of channel, which results faster rising of surface potential [46]. Also, the steeper slope increases the total electric field along with the rate of electron velocity, thus, significantly higher on-state current, shown in Figure 3. For the range of 0 to 1 V of drain voltage, NC-FinFET with HZO shows 3 to 4 times higher drains current than FinFET with Al2O3 and HfO2, respectively. Moreover, sharp change of surface potential restricts increased carrier velocity. Hence, velocity saturation problem is reduced drastically.Figure 2
Comparison of surface potential profiles of HZO, Al2O3, and HfO2-based FinFET with channel length L=12nm.Figure 3
Comparison of on-state saturated current characteristics with variation of oxide, HZO, Al2O3, and HfO2 in FinFET.The threshold voltage profile for different gate dielectric is shown in Figure4. HZO-based NC-FinFET exhibits lower threshold voltage, which further results high on-state current together with high operational speed of device [47], whereas the threshold voltages are constant for these three dielectric with decrements of channel length. Ferroelectric thickness [48] and temperature [49] have a significant impact on ferroelectric capacitance. Threshold voltage drops when ferroelectric thickness rises because ferroelectric capacitance reduces because of increased ferroelectric thickness. Besides that, negative oxide capacitance of NCFET might also result in a drop in threshold voltage [50]. Afterwards, the transfer characteristic plotted for different oxide in Figure 5, considering drain voltage 1.2 V, depicts lowest threshold voltage and highest after threshold current for HZO-based NC-FinFET.Figure 4
Comparison of threshold voltage estimated for HZO, Al2O3, and HfO2-based FinFET for different channel length.Figure 5
Comparison of transfer characteristics for HZO, Al2O3, and HfO2-based FinFET by varying gate voltage.The DIBL signifies the difference of threshold voltage with variation of drain voltage. In Figure6, DIBL’s are plotted for three gate dielectrics HZO, HfO2, and Al2O3. These curves depict increment of DIBL with the declination of channel length. The maximum level of DIBL for lowering channel length of HZO-based NC-FinFET is about 35.3 mV/V and it is around 54.5 mV/V for HfO2-based FinFET. That is because the reverse DIBL effect of negative capacitance material. The overall charge in the channel decreases with rising drain voltage as negative flowing charges are drawn out. As a result, reduction of DIBL is triggered [51]. Because of lower DIBL, the output resistance will be substantially higher for NCFET’s. Moreover, drain voltage induced breakdown is significantly reduced for NCFET’s [52].Figure 6
Comparison of DIBL for HZO, Al2O3, and HfO2-based FinFET’s keeping channel thickness, W fixed at 4 nm and effective channel length, Leff varies from 2 to 16 nm.The reciprocal of the steepest slope of transfer characteristics yielded the subthreshold slope (SS). Smaller SS exhibits lower off state leakage current. In Figure7, it is demonstrated that the reduction of SS occurs when the channel length is larger. That is because of having the opposite proportionality of channel length and drain current. As HZO has ferroelectric negative capacitance property and higher dielectric constant, therefore SS for HZO-based NC-FinFET reaches theoretical limit of 60 mV/decade. Hence, this lower value presents higher immunity to SCE’s [53].Figure 7
Comparison subthreshold swing (SS) for HZO, Al2O3, and HfO2-based FinFET’s.Transconductance is the derivative of transfer characteristics of FET and implies speed of device. In Figure8, it can be observed that after threshold voltage, transconductance of HZO-based device is significantly shot up and the rate is around 4 times higher than conventional HfO2-based device. Here, the drain voltage is varied from 0 to 2 V by considering step size of 0.5 V.Figure 8
Comparison of transconductance for HZO, Al2O3, and HfO2-based FinFET’s by stepping up the gate voltage, Vg from 0 to 2 V.As gate length is reduced, the drain depletion zone and source depletion region slowly contact and penetrate each other, reducing barrier heights. Lowering the source barrier increases charge carrier injection via the short channel, and the gate may lose control, hence off-state current increased. It can be seen from Figure9, FinFET with HZO have less off-state current as compared to HfO2, and Al2O3 dielectric-based FinFET.Figure 9
Comparison of transconductance for HZO, Al2O3, and HfO2-based FinFET’s keeping channel thickness, W fixed at 4 nm and effective channel length, Leff varies from 2 to 16 nm.Table3 depicts the figure of merits from mathematical analysis for comparing three-gate oxide from this work and recent literature at a glance. It is seen that the drain current for HZO is around 2 and 10 times higher from FinFET with HfO2 and Al2O3 subsequently. Moreover, 40 μS of transconductance, which is around 4 times higher than conventional HfO2 gate oxide-based device and significantly lower DIBL. Additionally, FinFET with HZO have comparatively less off-state current from device with other gate oxide.Table 3
Comparison of different characteristic of FET technology.
FET technologyDrain current (mA)Threshold voltage (V)Minimum subthreshold slopeOff current (A)Transconductance (μS)DIBLNC-FinFET with HZO1.2 mA0.3 V60 mV/dec6.82×10−15A40μS35.3 mV/VFinFET with HfO20.5 mA0.67 V61 mV/dec7.30×10−15A10μS54.4 mV/VFinFET with Al2O3 dielectric0.15 mA1.8 V70 mV/dec9.21×10−15A0.1μS67.8 mV/VFinFET withSiO2+HfO2 dielectric [54]0.073 mA0.128 V72.7 mV/dec4.16×10−5A—30 mV/VHetero-junction Si1-xGex FinFET [55]——52.67 mV/dec1.38×10–18A—52.37 mV/VBulk MOSFET [56]——88 mV/dec5×10−5A——SOI MOSFET [56]——65 mV/dec50μA/μm—150 mV/V


## 5. Conclusion

In this research work, the performance parameter of NC-FinFET with HZO in comparison with Al2O3 and HfO2-based FinFET’s are investigated. The surface potential, threshold voltage, DIBL, Subthreshold Swing, off current, output, and transfer characteristics are thoroughly investigated for all of three channel dielectrics. The stepper surface potential of HZO-based NC-FinFET is the major cause for the controllability of velocity saturation. The 0.3 V threshold voltage found in NC-FinFET guarantees high on state current, which is 16 times higher than FinFET with SiO2+HfO2 dielectric. Besides that, the 35.3 mV/V of DIBL and 60 mV/dec of Subthreshold Swing (SS) reveal worthiness of NC-FinFET with HZO in a very low dimension. The off-state current of NC-FinFET is around 98% and 35.04% lower than SiO2+HfO2 dielectric and Al2O3 dielectric-based FinFET simultaneously. Therefore, hafnium zirconium-based negative capacitance FinFET device outperforms the conventional FinFET with Al2O3 and HfO2 dielectric in case of suppression of SCE’s and off-state current. Hence, it can be the potential candidate for low power and high-speed device fabrication.



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