# Prime Field ECDSA Signature Processing for Reconfigurable Embedded Systems

Authors: Benjamin Glas; Oliver Sander; Vitali Stuckert; Klaus D.  Müller-Glaser; Jürgen Becker
Journal: International Journal of Reconfigurable Computing
 (2011)

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## Abstract

Growing ubiquity and safety relevance of embedded
systems strengthen the need to protect their functionality against
malicious attacks. Communication and system authentication
by digital signature schemes is a major issue in securing such
systems. This contribution presents a complete ECDSA signature
processing system over prime fields for bit lengths of up to 256
on reconfigurable hardware. By using dedicated hardware implementation,
the performance can be improved by up to two orders
of magnitude compared to microcontroller implementations. The
flexible system is tailored to serve as an autonomous subsystem
providing authentication transparent for any application. Integration
into a vehicle-to-vehicle communication system is shown
as an application example.


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## Body

## 1. Introduction

With emerging ubiquity of embedded electronic systems and a growing part of distributed systems and functions even in safety relevant areas, the security of embedded systems and their communication gains importance quickly. One major concern of security is authenticity of communication peers and information exchange. Especially if many different remote participants have to communicate or not all participants are known in advance, asymmetric signature schemes are beneficial for authentication purposes. In contrast to symmetric schemes like the Keyed-Hash Message Authentication Code HMAC [1], asymmetric signature schemes like RSA [2], DSA [3], and the ECDSA scheme [3] considered in this contribution get along without key exchange or predistributed keys, relying usually on a certification authority as trusted third party instead.This benefit comes at the cost of a much greater computational complexity of these schemes compared to authentication techniques based on symmetric ciphers or solely on hashing. This imposes major problems especially for embedded systems, where resources are scarce.This contribution presents a hardware-implemented system for complete prime field ECDSA signature processing on FPGAs. It can be integrated as an autonomous subsystem for signature processing in embedded devices. As an application example the integration in a vehicle-to-vehicle communication unit is presented.The remainder of this paper is organized as follows. In Section2 some related work is given, Section 3  presents basics of the implemented signature scheme ECDSA, and Section 4 outlines the assumed situation and requirements for the system. The structure and implementation of the signature system itself is presented in Section 5, and Section 6 shows an application example and integration in a wireless communication system. Section 7 details performance and resource usage that are further discussed in Section 8. The paper is concluded in Section 9.


## 2. Related Work

Since elliptic curves were proposed as basis for public key cryptography in 1985 by Koblitz [4] and Miller [5] independently, many implementations of the prime field Elliptic Curve Digital Signature Algorithm (ECDSA) and Elliptic Curve Cryptography (ECC) in general have been published. Software implementations on general purpose processors need a lot of computation power. The eBACS ECRYPT benchmark [6] gives values for 256-bit ECDSA of, for example, 1.88 ms for generation and 2.2 ms for verification on an Intel Core 2 Duo at 1.4 GHz and 2.9 ms respectively, 3.4 ms on an Intel Atom 330 at 1.6 GHz. Values for a crypto system based on an ARM7 32-bit microcontroller are given in [7] for a key bit length of 233 bit. Using a comb table precomputation (w=4) 742 ms are needed for a generation and 1240 ms for a verification of an ECDSA signature. An implementation for a RIM Blackberry [8] using an ARM 9EJ-S core realizes 150 ms for a signature generation and 168 ms for a signature verification [9].To achieve usable throughputs and latencies on embedded systems, various specialized hardware solutions have been proposed, for example, many approaches for implementation of𝔽p arithmetic and the ECC primitives point add and point double on reconfigurable hardware. A survey of hardware implementations can be found in [10]. McIvor et al. [11] propose a special ECC processor for 𝔽p on a Virtex II Pro FPGA, calculating a 256-bit scalar multiplication in 3.86 ms using a clock frequency of 39.5 MHz. Orlando and Paar [12] achieve for a bit length of 192 a scalar multiplication in 3 ms on a Virtex-E FPGA. Güneysu and Paar present in [13] a very fast approach based on special DSP FPGA slices, achieving processing times of 620 μs for a 256-bit scalar multiplication on a Virtex-4 FPGA. The implementation presented here is based on an 𝔽p ALU presented by Ghosh et al. in [14]. Implementation approaches on CMOS standard cells can be found, for example, in [15, 16], achieving scalar multiplications in 256-bit length in 2.68 ms and 4.3 ms, respectively.Nevertheless, open implementations of full signature processing units performing complete ECDSA are scarce. Järvinen and Skyttä [17] present a Nios II-based ECDSA system on an Altera Cyclone II FPGA for a key length of 163-bit performing signature generation in 0.94 ms and verification in 1.61 ms.This contribution presents an FPGA-based autonomous ECDSA system for longer key lengths of 256 bit containing all necessary subsystems for application in embedded systems on reconfigurable hardware.


## 3. ECDSA Fundamentals

The Elliptic Curve Digital Signature Algorithm (ECDSA) is based on a group structure defined on an elliptic curveE over a finite field 𝔽q. Mostly two types of underlying finite fields are technically used: binary fields 𝔽2n of characteristic two and prime fields 𝔽p with large primes p and corresponding characteristic. This paper focuses on prime fields 𝔽p with characteristic char (𝔽p)≫3. In this case the group E and the respective operation is defined as follows.Definition 1 (group operation onE).
LetE be an elliptic curve over a finite field 𝔽p of characteristic char (𝔽p)≫3 given by the Weierstrass equation
(1)E:y2=x3+ax+b,
with a,b∈𝔽p, 4a3+27b2≠0, and P=(x1,y1), Q=(x2,y2) points on E. A group on E∪{𝒪},𝒪 being the special point at infinity, and the group law
(2)+:E×E⟶E,(P,Q)⟼P+Q=:R=(x3,y3)
on E is defined by the following  (i)
P+𝒪=𝒪+P=P for all P∈E.(ii)
ForP=(x1,y1)∈E, the point P=(x1,-y1) is also ∈E and P+(-P)=𝒪.(iii)
ForP≠±Q and P≠-P, the operation for R=P+Q=(x3,y3) is given by
(3)x3=(y2-y1x2-x1)2-x1-x2,y3=(y2-y1x2-x1)(x1-x3)-y1.(iv)
ForP=Q and P≠-P, there is R=2P=(x3,y3) defined by
(4)x3=(3x12+a2y1)2-2x1,y3=(3x12+a2y1)(x1-x3)-y1.The set E∪{𝒪} with the defined group law + is an abelian group with neutral element 𝒪. The inverse to a point P=(x,y) is given by -P=(x,-y).For the use of ECDSA a set of common domain parameters is needed to be known to all participants. These are the modulusp identifying the underlying field, parameters a,b defining the elliptic curve E used, a base point G∈E, the order n of G, and the cofactor h=order(E)/n. In addition a cryptographic hash function H is needed. The signature generation and verification for a key pair (Q,d), Q∈E being a point on the curve and d a scalar factor with Q=dG, can then be performed using the secret key d or the public key Q, respectively. The procedures needed are shown in Algorithms 1 and 2.Algorithm 1:ECDSA signature generation.
Input:  Domain parameter D=(q,a,b,G,n,h), secret key d,messagemOutput:  Signature (r,s)(1)  Chose randomk∈[1,n-1],k∈ℕ(2)  ComputekG=(x1,y1)(3)  Computer=x1modn. If r=0 goto step 1.(4)  Computee=H(m)(5)  Computes=k-1(e+dr)modn. If s=0 goto step 1.(6)return  (r,s).Algorithm 2:ECDSA signature verification.
Input:  Domain parameter D=(q,a,b,G,n,h),public keyQ, message m, signature (r,s).Output:  Acceptance or Rejection of the signature(1)if¬(r,s∈[1,n-1]∩ℕ)  then(2)return“reject”(3)end  if(4)  Computee=H(m)(5)  Computew=s-1modn.(6)  Computeu1=ewmodn and u2=rwmodn.(7)  ComputeX=(xX,yX)=u1G+u2Q.(8)ifX=∞  then(9)return“reject”(10)end  if(11)  Computev=xXmodn.(12)ifv=r  then(13)return“accept”(14)else(15)return“reject”(16)end ifFor identification of the most demanding operations, a tracing of the algorithms based on the hardware implementation presented in Section5 and the possible parallelization was done. Of the total of 395,521 clock cycles needed for signature generation with the modulus p256 used (see Section 4), a percentage of 99.8% or 394,752 cycles were spent computing the scalar multiplication kG. For signature verification the amount of cycles spent for the double scalar multiplication X=u1G+u2Q is even 99.9%. So in the further consideration we focus on these central operations.


## 4. Setup and Situation

Objective of a digital signature is to guarantee authenticity and integrity of a signed message to the receiver and prove the identity of the sender, including nonrepudiation. The usual method based on an asymmetric primitive like ECDSA contains three protocol steps. First the sender generates a key pair consisting of a secret signature key SK (d in the ECDSA case) and a public verification key VK (Q for ECDSA) and publishes VK to all possible verifiers. To sign a message m of arbitrary length, the sender generates a digest H(m) of the message using a publicly known cryptographic hash function H. This digest is of a fixed length and can be seen as a fingerprint of the message in the sense that finding a different message m′≠m with H(m)=H(m′) is infeasible. This digest is then signed, meaning encrypted using the signing key SK of the sender, and sent along with the original plain text message m. The receiver or verifier is then able to verify the signature by decrypting the received hash value using the sender's public verification key PK and comparing the decrypted value to the output of H applied to the received plain message. If the two values match, the signature is positively verified (see Algorithm 3).Algorithm 3:General digital signature procedure.
Input:  Sender:  Hash function H, secret key SK of sender, message m.Output:  Signed message (m,Sig(m))(1)  Compute hash valueH(m) of m.(2)  ComputeSig(m)=EncSK(H(m)) by encrypting the hash digestH(m) using the sender's secret key.(3)  Send(m,Sig(m)) to receiver.Input:  Receiver:  Hash function H, public key PK of sender,received packet (m′,x).Output:  Proof that Message m′ originates from sender.(1)  Computey=DecPK(x) by decrypting the received signature x usingthe public key of sender.(2)  Compute hash valueH(m′) of received message m′.(3)ify==H(m′)  thenaccept signature(4)elsereject signature(5)end ifThe security and correctness of the signature method is based on the assumption that a signed value (encrypted with the secret key) can only be verified (decrypted) with knowledge of the corresponding public key and vice versa and that the secret key cannot be computed from the public key. Secondly the mapping of public keys to identities has to be guaranteed in some way. This is usually done using certification authorities as trusted third parties that verify the identity and issue a certificate for the public key.We assume an embedded system communicating with several peers which are not entirely known in advance. Therefore, the exchanged signed messages are sent with a certificate attached, that is, issued, to a commonly trusted certification authority. As an example scenario the vehicle-to-vehicle (V2V) communication is considered in Section6.This contribution focuses on prime field ECDSA as it is proposed for vehicle-to-vehicle communications which is our general focus application (see also Application Example). Implemented are especially two elliptic curves recommended by the U.S. National Institute of Standards and Technology (NIST) in [18] and Certicom Research in [19], namely, the curves p224 (secp224r1) and p256 (secp256r1) with bit lengths 224 and 256, respectively, and the corresponding domain parameters also given in the standard.The proposed system works as a security subsystem exclusively performing signature processing and passing and receiving messagesm to and from the external system.


## 5. Signature Processing System

Processing of ECDSA consists of several layers of computation. On the top level the signature generation and verification algorithms as well as the certificate validation are performed. This signature scheme-dependent layer is based on the group operations point add (PA) and point double (PD) in the underlying elliptic curve. These are in turn based on the underlying finite prime field (𝔽p) arithmetic, that is, modular arithmetic modulo a prime p. For the main operation of signature verification, the double scalar multiplication kG+rQ, the respective number of underlying operations needed on each layer to perform a single operation on the respective upper layer is given in Figure 1. In an even higher layer, there is also the communication protocol to consider at least partially as needed for the signature system.Figure 1
Execution layers of double scalar multiplication onE. On each layer the numbers of operations are given that are needed for a single operation on the respective upper layer.The architecture and presentation of the system reflects this layering. The two upper layers are implemented as finite state machines (FSM) and make use of a basic𝔽p arithmetic logical unit (ALU) and some additional auxiliary modules. Figure 2 outlines the structure of the system. The different building blocks are detailed in the following paragraphs.Figure 2
Overview of the signature system.


### 5.1.𝔽p Modular ALU

The central processing is done by a specialized𝔽p-ALU for primes of maximum 256-bit length. It is based on the ALU proposed by Ghosh et al. in [14]. Figure 3 depicts the implemented structure. The ALU contains one 𝔽p adder, subtractor, multiplier, and divider/inverter each. All registers and datapaths between the modules are 256 bit wide so that complete operands up to 256-bit width (as in the p256 case) can be stored and transmitted within a single clock cycle. Four inputs, two outputs, and four combined operand/result register as well as a flexible interconnect allow a start of two operations each at the same time as long as they do not use the same basic arithmetic units. The units perform operations independently, so that using different starting points parallel execution in all four subunits is possible. This allows parallelisation especially in the scalar multiplication (see Section 5.2.1).Figure 3
Schematic overview of the𝔽p ALU.The𝔽p-adder and -subtractor perform each operation in a single clock cycle as a general addition/subtraction with subsequent reduction. The 𝔽p multiplying module computes the modular multiplication iteratively as shift-and-add with reduction mod p in every step. It therefore needs |p| clock cycles for one modular multiplication, |p| being the bit length of the modulus and thereby also the maximum bit length of the operands.Modular inversion and division is the most complex task of the ALU. It is based on a binary division algorithm on𝔽p; see [14] for details. The runtime depends on the input values, maximum runtime being 2|p| clock cycles, in the p256 case therefore up to 512 cycles. Statistical analysis showed an average runtime of 1.5·|p| clock cycles.ALU control is performed over multiplexer and module control wires and is implemented as a finite state machine presented in the following paragraph. The complete ALU allocates 14256 LUT/FF pairs in a Xilinx Virtex-5 FPGA and allows a maximum clock frequency of 41.2 MHz (after synthesis).In addition to the 256-bit arithmetic based on the modulusp256 the ECDSA unit also implements the arithmetic for modulus p224. This is done using the same hardware and is also implemented in the overlaying FSM. Theoretically all moduli up to 256-bit width are supported by the ALU. Nevertheless, in the following, all given data refers to the 256-bit key case. Details on resource consumption and performance values are given in Section 7.


### 5.2. Elliptic Curve Processing

On the elliptic curveE addition of points is defined as group operation. Doubling of a point is specially implemented as it requires a different computation because general point addition is not defined with operands being equal (see Section 3). A comprehensive introduction to elliptic curve arithmetic including algorithms can be found in [20]. To map the algorithms to the implemented specific ALU, the single operation steps have to be scheduled to the respective units. The operation schedules for point addition and point doubling for execution on the ALU are given in Tables 1 and 2.Table 1
Hardware execution of point addition.
Step𝔽p unitNo. of cycles(1)t1=y2-y1Sub1(2)t2=x2-x1Sub1(3)t2=t1/t2(=λ); t3=x1+x2div; addmax.2|p|(4)t1=t2·t2Mult|p|(5)t1=t1-t3(=x3)Sub1(6)t1=x1-t1Sub1(7)t1=t2·t1Mult|p|(8)t1=t1-y1(=y3)Sub1max.4|p|+5Table 2
Hardware execution of point doubling.
Step𝔽p unitNo. of cycles(1)t1=x1·x1Mult|p|(2)t2=t1+t1Add1(3)t1=t1+t2Add1(4)t1=t1+aAdd1(5)t2=y1+y1Add1(6)t2=t1/t2(=λ); t3=x1+x1div; addmax.2|p|(7)t1=t2·t2Mult|p|(8)t1=t1-t3(=x3)Sub1(9)t1=x1-t1Sub1(10)t1=t2·t1Mult|p|(11)t1=t1-y1(=y3)Sub1max.5|p|+7In the tables,|p| stands for the bit length of the modulus p. In the case of p256, this means |p|=256. The execution schedules map the operations to the executing units using three auxiliary register t1, t2, t3 for storing intermediate results. As can be seen in the tables, the third register t3 is used only once in each point operation and reduces the cycle count in each case by one. If this additional clock cycle is accepted, one 256-bit register can be saved.


#### 5.2.1. Scalar Multiplication onE

Scalar multiplication in step 2 is the central operation of the signature generation of Algorithm1. Computation is done iteratively using the so-called Montgomery ladder [21, 22] showed in Algorithm 4.Algorithm 4:Scalar multiplication in E.
Input:  Point P∈E; Integer k=∑i=0l-1ki2iwithki∈{0,1} and kl-1=1.Output:  Point Q=kP∈E.(1)P1=P(2)P2=2P(3)fori=l-2 downto 0  do(4)ifk=0  then(5)P1new=2P1old(6)P2new=P1old+P2old(7)else(8)P1new=P1old+P2old(9)P2new=2P2old(10)end  if(11)end  for(12)returnQ=P1The operations in the branches inside the for-loop, meaning steps 5 and 6 in the if-branch, respectively, steps 8 and 9 in the else-branch, can be executed in parallel. Since it is a point addition and a point doubling each, a real parallel execution on the ALU is possible using a tailored scheduling. Figure4 depicts the implemented schedule. Although the computation of PA and PD is now done in parallel, a total of five registers for intermediate results is sufficient because the respective t3 register of PA and PD is not needed at the same time and can therefore be shared.Figure 4
Parallel Scheduling of PA and PD.The execution time using this schedule is6|p|+7 clock cycles for a single pair of point addition and point doubling. Compared to the time of (4|p|+5)+(5|p|+7)=9|p|+12 clock cycles needed for a sequential processing of PA and PD, a performance gain of 33% can be achieved. Execution time for the complete scalar multiplication is therefore at maximum ((|p|-1)·(6|p|+7)+(5|p|+7))=6|p|2+6|p| clock cycles for the combination of point add and point double.


#### 5.2.2. Double Scalar Multiplication

For verification of ECDSA signatures two independent scalar multiplications have to be executed (see Algorithm2, step 7). Instead of computing independently in sequence, it is faster to compute them together using an approach proposed originally by Shamir (see [23]) also known as “Shamir's trick” shown in Algorithm 5.Algorithm 5:Simultaneous multiple point multiplication.
Input:  Point P,Q∈E; Integers k=∑i=0l-1ki2i andr=∑i=0l-1ri2i with ki,ri∈{0,1} and kl-1∨rl-1=1.Output:  Point X=kP+rQ∈E.(1)  Precomputation:P+Q(2)X=O (point at infinity)(3)for  i=l-2 downto 0  do(4)X=2X(5)X=X+(kiP+riG)(6)end  for(7)returnXIn contrast to Algorithm4, the central operations in steps 4 and 5 of Algorithm 5 cannot be parallelized as they depend directly on each other. The maximum time consumption of the algorithm is therefore (5)(4|p|+5)+|p|⋅((5|p|+7)+(4|p|+5))=9|p|2+16|p|+5
clock cycles for a double scalar multiplication. This is nevertheless less than the (6)2⋅((6|p|2+6|p|)+(4|p|+5))=12|p|2+16|p|+5
cycles that two independent scalar multiplications would consume. Assuming uniform distribution step 5 is omitted in 25% of the cases leaving an estimated runtime of (7)((4|p|+5)+|p|⋅((5|p|+7)+0.75⋅(4|p|+5)))=8|p|2+14.75|p|+5
clock cycles. The composition of the double scalar multiplication on the different levels of computation is shown in Figure 5.Figure 5
Complexity of execution layers of double scalar multiplication onE. On each level, the number of clock cycles needed for the respective operation is given. The times given refer to a clock frequency of 50 MHz.


### 5.3. Signature and Certificate Control System

On top of the elliptic curve (EC) operations and the control FSM performing them, the actual signature algorithms and the certificate verification are implemented. This is done in a separate FSM, controlling the EC arithmetic FSM, some registers, and the auxiliary hashing and random number generation. Figure6 shows the sequence of operations of the signature verification. See Algorithms 1 and 2 for the implemented procedures.Figure 6
Procedure for signature and certificate verification on the implemented ALU. The blue states mark the main steps.This FSM is the upmost layer of the signature module and provides a register interface for operands like messages, signatures, certificates, and keys. For integration in an embedded system, it has to be wrapped to support the message format and create the inputs to select the function needed. An example for an integration is given in Section6.


### 5.4. SHA2 Hashing Module

The SHA2 hashing unit provides functions SHA-224 and SHA-256 according to the Secure Hash Algorithm (SHA) standard [24]. It is based on a freely available verilog SHA-256 IP-core (available as SHA IP Core at http://opencores.com/) adapted with a wrapper performing precomputation of the input data and providing a simple register interface accepting data in 32-bit chunks. In addition the core has been enhanced to support SHA-224.The unit processes input data in blocks of 512 bit needing 68 clock cycles each at a maximum clock frequency of 120 MHz (after synthesis) and a resource usage of 2277 LUT/FF pairs. After finishing the operation, the result is available in a 256-bit output register.


### 5.5. Pseudorandom Number Generation

For ECDSA signature generation, a random valuek is needed. To provide this k the system incorporates a Pseudorandom Number Generator (PRNG) consisting of two linear feedback shift registers (LFSR), one with 256 bit length, feedback polynomial x255+x251+x246+1, and a cycle length of 2256-1 and a second LFSR with 224 bit length, feedback polynomial x222+x217+x212+1, and a cycle length of 2224-1, both taken from [25].The LFSR occupies 480 LUT/FF pairs and allows a maximum clocking of 870 MHz although operated in the system in the general system clock of 50 MHz. It is operated continuously to reduce predictability of the produced numbers. The current register content is read out on demand.For further improvement of the security level, a True Random Number Generator (TRNG) could be integrated. An example implementation of an FPGA-based TRNG can be found in [26].


### 5.6. Certificate Cache

Usually digital signatures or their respective public keys needed for verification are endorsed by a certificate issued by a trusted third party, a so-called certification authority (CA), to prove its authenticity. Verification of the certificate requires a signature verification itself and is therefore equally complex as the main signature verification of the message. If communicating several messages with the same communication peer using the same signature key, the certificate can be stored hence saving the effort for repetitive verification.The system incorporates a certificate cache for up to 81 certificates stored in two BRAM blocks. It can be searched in parallel with the signature verification (see Figure6). Replacement of certificates is performed using a least recently used (LRU) policy.


## 5.1.𝔽p Modular ALU

The central processing is done by a specialized𝔽p-ALU for primes of maximum 256-bit length. It is based on the ALU proposed by Ghosh et al. in [14]. Figure 3 depicts the implemented structure. The ALU contains one 𝔽p adder, subtractor, multiplier, and divider/inverter each. All registers and datapaths between the modules are 256 bit wide so that complete operands up to 256-bit width (as in the p256 case) can be stored and transmitted within a single clock cycle. Four inputs, two outputs, and four combined operand/result register as well as a flexible interconnect allow a start of two operations each at the same time as long as they do not use the same basic arithmetic units. The units perform operations independently, so that using different starting points parallel execution in all four subunits is possible. This allows parallelisation especially in the scalar multiplication (see Section 5.2.1).Figure 3
Schematic overview of the𝔽p ALU.The𝔽p-adder and -subtractor perform each operation in a single clock cycle as a general addition/subtraction with subsequent reduction. The 𝔽p multiplying module computes the modular multiplication iteratively as shift-and-add with reduction mod p in every step. It therefore needs |p| clock cycles for one modular multiplication, |p| being the bit length of the modulus and thereby also the maximum bit length of the operands.Modular inversion and division is the most complex task of the ALU. It is based on a binary division algorithm on𝔽p; see [14] for details. The runtime depends on the input values, maximum runtime being 2|p| clock cycles, in the p256 case therefore up to 512 cycles. Statistical analysis showed an average runtime of 1.5·|p| clock cycles.ALU control is performed over multiplexer and module control wires and is implemented as a finite state machine presented in the following paragraph. The complete ALU allocates 14256 LUT/FF pairs in a Xilinx Virtex-5 FPGA and allows a maximum clock frequency of 41.2 MHz (after synthesis).In addition to the 256-bit arithmetic based on the modulusp256 the ECDSA unit also implements the arithmetic for modulus p224. This is done using the same hardware and is also implemented in the overlaying FSM. Theoretically all moduli up to 256-bit width are supported by the ALU. Nevertheless, in the following, all given data refers to the 256-bit key case. Details on resource consumption and performance values are given in Section 7.


## 5.2. Elliptic Curve Processing

On the elliptic curveE addition of points is defined as group operation. Doubling of a point is specially implemented as it requires a different computation because general point addition is not defined with operands being equal (see Section 3). A comprehensive introduction to elliptic curve arithmetic including algorithms can be found in [20]. To map the algorithms to the implemented specific ALU, the single operation steps have to be scheduled to the respective units. The operation schedules for point addition and point doubling for execution on the ALU are given in Tables 1 and 2.Table 1
Hardware execution of point addition.
Step𝔽p unitNo. of cycles(1)t1=y2-y1Sub1(2)t2=x2-x1Sub1(3)t2=t1/t2(=λ); t3=x1+x2div; addmax.2|p|(4)t1=t2·t2Mult|p|(5)t1=t1-t3(=x3)Sub1(6)t1=x1-t1Sub1(7)t1=t2·t1Mult|p|(8)t1=t1-y1(=y3)Sub1max.4|p|+5Table 2
Hardware execution of point doubling.
Step𝔽p unitNo. of cycles(1)t1=x1·x1Mult|p|(2)t2=t1+t1Add1(3)t1=t1+t2Add1(4)t1=t1+aAdd1(5)t2=y1+y1Add1(6)t2=t1/t2(=λ); t3=x1+x1div; addmax.2|p|(7)t1=t2·t2Mult|p|(8)t1=t1-t3(=x3)Sub1(9)t1=x1-t1Sub1(10)t1=t2·t1Mult|p|(11)t1=t1-y1(=y3)Sub1max.5|p|+7In the tables,|p| stands for the bit length of the modulus p. In the case of p256, this means |p|=256. The execution schedules map the operations to the executing units using three auxiliary register t1, t2, t3 for storing intermediate results. As can be seen in the tables, the third register t3 is used only once in each point operation and reduces the cycle count in each case by one. If this additional clock cycle is accepted, one 256-bit register can be saved.


### 5.2.1. Scalar Multiplication onE

Scalar multiplication in step 2 is the central operation of the signature generation of Algorithm1. Computation is done iteratively using the so-called Montgomery ladder [21, 22] showed in Algorithm 4.Algorithm 4:Scalar multiplication in E.
Input:  Point P∈E; Integer k=∑i=0l-1ki2iwithki∈{0,1} and kl-1=1.Output:  Point Q=kP∈E.(1)P1=P(2)P2=2P(3)fori=l-2 downto 0  do(4)ifk=0  then(5)P1new=2P1old(6)P2new=P1old+P2old(7)else(8)P1new=P1old+P2old(9)P2new=2P2old(10)end  if(11)end  for(12)returnQ=P1The operations in the branches inside the for-loop, meaning steps 5 and 6 in the if-branch, respectively, steps 8 and 9 in the else-branch, can be executed in parallel. Since it is a point addition and a point doubling each, a real parallel execution on the ALU is possible using a tailored scheduling. Figure4 depicts the implemented schedule. Although the computation of PA and PD is now done in parallel, a total of five registers for intermediate results is sufficient because the respective t3 register of PA and PD is not needed at the same time and can therefore be shared.Figure 4
Parallel Scheduling of PA and PD.The execution time using this schedule is6|p|+7 clock cycles for a single pair of point addition and point doubling. Compared to the time of (4|p|+5)+(5|p|+7)=9|p|+12 clock cycles needed for a sequential processing of PA and PD, a performance gain of 33% can be achieved. Execution time for the complete scalar multiplication is therefore at maximum ((|p|-1)·(6|p|+7)+(5|p|+7))=6|p|2+6|p| clock cycles for the combination of point add and point double.


### 5.2.2. Double Scalar Multiplication

For verification of ECDSA signatures two independent scalar multiplications have to be executed (see Algorithm2, step 7). Instead of computing independently in sequence, it is faster to compute them together using an approach proposed originally by Shamir (see [23]) also known as “Shamir's trick” shown in Algorithm 5.Algorithm 5:Simultaneous multiple point multiplication.
Input:  Point P,Q∈E; Integers k=∑i=0l-1ki2i andr=∑i=0l-1ri2i with ki,ri∈{0,1} and kl-1∨rl-1=1.Output:  Point X=kP+rQ∈E.(1)  Precomputation:P+Q(2)X=O (point at infinity)(3)for  i=l-2 downto 0  do(4)X=2X(5)X=X+(kiP+riG)(6)end  for(7)returnXIn contrast to Algorithm4, the central operations in steps 4 and 5 of Algorithm 5 cannot be parallelized as they depend directly on each other. The maximum time consumption of the algorithm is therefore (5)(4|p|+5)+|p|⋅((5|p|+7)+(4|p|+5))=9|p|2+16|p|+5
clock cycles for a double scalar multiplication. This is nevertheless less than the (6)2⋅((6|p|2+6|p|)+(4|p|+5))=12|p|2+16|p|+5
cycles that two independent scalar multiplications would consume. Assuming uniform distribution step 5 is omitted in 25% of the cases leaving an estimated runtime of (7)((4|p|+5)+|p|⋅((5|p|+7)+0.75⋅(4|p|+5)))=8|p|2+14.75|p|+5
clock cycles. The composition of the double scalar multiplication on the different levels of computation is shown in Figure 5.Figure 5
Complexity of execution layers of double scalar multiplication onE. On each level, the number of clock cycles needed for the respective operation is given. The times given refer to a clock frequency of 50 MHz.


## 5.2.1. Scalar Multiplication onE

Scalar multiplication in step 2 is the central operation of the signature generation of Algorithm1. Computation is done iteratively using the so-called Montgomery ladder [21, 22] showed in Algorithm 4.Algorithm 4:Scalar multiplication in E.
Input:  Point P∈E; Integer k=∑i=0l-1ki2iwithki∈{0,1} and kl-1=1.Output:  Point Q=kP∈E.(1)P1=P(2)P2=2P(3)fori=l-2 downto 0  do(4)ifk=0  then(5)P1new=2P1old(6)P2new=P1old+P2old(7)else(8)P1new=P1old+P2old(9)P2new=2P2old(10)end  if(11)end  for(12)returnQ=P1The operations in the branches inside the for-loop, meaning steps 5 and 6 in the if-branch, respectively, steps 8 and 9 in the else-branch, can be executed in parallel. Since it is a point addition and a point doubling each, a real parallel execution on the ALU is possible using a tailored scheduling. Figure4 depicts the implemented schedule. Although the computation of PA and PD is now done in parallel, a total of five registers for intermediate results is sufficient because the respective t3 register of PA and PD is not needed at the same time and can therefore be shared.Figure 4
Parallel Scheduling of PA and PD.The execution time using this schedule is6|p|+7 clock cycles for a single pair of point addition and point doubling. Compared to the time of (4|p|+5)+(5|p|+7)=9|p|+12 clock cycles needed for a sequential processing of PA and PD, a performance gain of 33% can be achieved. Execution time for the complete scalar multiplication is therefore at maximum ((|p|-1)·(6|p|+7)+(5|p|+7))=6|p|2+6|p| clock cycles for the combination of point add and point double.


## 5.2.2. Double Scalar Multiplication

For verification of ECDSA signatures two independent scalar multiplications have to be executed (see Algorithm2, step 7). Instead of computing independently in sequence, it is faster to compute them together using an approach proposed originally by Shamir (see [23]) also known as “Shamir's trick” shown in Algorithm 5.Algorithm 5:Simultaneous multiple point multiplication.
Input:  Point P,Q∈E; Integers k=∑i=0l-1ki2i andr=∑i=0l-1ri2i with ki,ri∈{0,1} and kl-1∨rl-1=1.Output:  Point X=kP+rQ∈E.(1)  Precomputation:P+Q(2)X=O (point at infinity)(3)for  i=l-2 downto 0  do(4)X=2X(5)X=X+(kiP+riG)(6)end  for(7)returnXIn contrast to Algorithm4, the central operations in steps 4 and 5 of Algorithm 5 cannot be parallelized as they depend directly on each other. The maximum time consumption of the algorithm is therefore (5)(4|p|+5)+|p|⋅((5|p|+7)+(4|p|+5))=9|p|2+16|p|+5
clock cycles for a double scalar multiplication. This is nevertheless less than the (6)2⋅((6|p|2+6|p|)+(4|p|+5))=12|p|2+16|p|+5
cycles that two independent scalar multiplications would consume. Assuming uniform distribution step 5 is omitted in 25% of the cases leaving an estimated runtime of (7)((4|p|+5)+|p|⋅((5|p|+7)+0.75⋅(4|p|+5)))=8|p|2+14.75|p|+5
clock cycles. The composition of the double scalar multiplication on the different levels of computation is shown in Figure 5.Figure 5
Complexity of execution layers of double scalar multiplication onE. On each level, the number of clock cycles needed for the respective operation is given. The times given refer to a clock frequency of 50 MHz.


## 5.3. Signature and Certificate Control System

On top of the elliptic curve (EC) operations and the control FSM performing them, the actual signature algorithms and the certificate verification are implemented. This is done in a separate FSM, controlling the EC arithmetic FSM, some registers, and the auxiliary hashing and random number generation. Figure6 shows the sequence of operations of the signature verification. See Algorithms 1 and 2 for the implemented procedures.Figure 6
Procedure for signature and certificate verification on the implemented ALU. The blue states mark the main steps.This FSM is the upmost layer of the signature module and provides a register interface for operands like messages, signatures, certificates, and keys. For integration in an embedded system, it has to be wrapped to support the message format and create the inputs to select the function needed. An example for an integration is given in Section6.


## 5.4. SHA2 Hashing Module

The SHA2 hashing unit provides functions SHA-224 and SHA-256 according to the Secure Hash Algorithm (SHA) standard [24]. It is based on a freely available verilog SHA-256 IP-core (available as SHA IP Core at http://opencores.com/) adapted with a wrapper performing precomputation of the input data and providing a simple register interface accepting data in 32-bit chunks. In addition the core has been enhanced to support SHA-224.The unit processes input data in blocks of 512 bit needing 68 clock cycles each at a maximum clock frequency of 120 MHz (after synthesis) and a resource usage of 2277 LUT/FF pairs. After finishing the operation, the result is available in a 256-bit output register.


## 5.5. Pseudorandom Number Generation

For ECDSA signature generation, a random valuek is needed. To provide this k the system incorporates a Pseudorandom Number Generator (PRNG) consisting of two linear feedback shift registers (LFSR), one with 256 bit length, feedback polynomial x255+x251+x246+1, and a cycle length of 2256-1 and a second LFSR with 224 bit length, feedback polynomial x222+x217+x212+1, and a cycle length of 2224-1, both taken from [25].The LFSR occupies 480 LUT/FF pairs and allows a maximum clocking of 870 MHz although operated in the system in the general system clock of 50 MHz. It is operated continuously to reduce predictability of the produced numbers. The current register content is read out on demand.For further improvement of the security level, a True Random Number Generator (TRNG) could be integrated. An example implementation of an FPGA-based TRNG can be found in [26].


## 5.6. Certificate Cache

Usually digital signatures or their respective public keys needed for verification are endorsed by a certificate issued by a trusted third party, a so-called certification authority (CA), to prove its authenticity. Verification of the certificate requires a signature verification itself and is therefore equally complex as the main signature verification of the message. If communicating several messages with the same communication peer using the same signature key, the certificate can be stored hence saving the effort for repetitive verification.The system incorporates a certificate cache for up to 81 certificates stored in two BRAM blocks. It can be searched in parallel with the signature verification (see Figure6). Replacement of certificates is performed using a least recently used (LRU) policy.


## 6. Application Example

The system offers complete ECDSA signature and certificate handling and can be used in a variety of embedded systems seeking authentication and security of communication. As an application example, we show the integration into a vehicle-to-X (V2X) communication system. V2X communication is an emerging topic aiming at information exchange between vehicles on the road and between vehicles and infrastructure like roadside units [27]. This can be used to enhance safety on roads, optimize traffic flow, and help to avoid traffic congestions [28]. Usually two types of broadcasted messages are used, a network beacon sent regularly with a frequency of 2–10 Hz containing status information of the sender and additional event-triggered messages notifying about special events and situations. Latter messages can also be forwarded over several hops to reach receivers outside the direct wireless communication range.To be able to base decisions and applications on information received from other vehicles, trustworthiness of this information is mandatory. To ensure the validity and authenticity of information, signature schemes are used to protect the messages broadcasted by the participating vehicles against malicious attacks [29, 30]. As V2X communication is at present in the process of standardization, no fixed settings are available yet, but the use of ECDSA is proposed in the IEEE 1609 Wireless Access in Vehicular Environments (WAVE) standard draft [31] as well as the proposals of European consortia [32], put together by the COMeSafety project [33].In the chosen realization V2X communication is performed by a modular FPGA-based On Board-Unit (OBU) presented in [34]; see Figure 7.Figure 7
Schematic overview of the V2X-OBU.It consists of different functional modules connected by a packet-based on-chip communication system [35]. The signature verification system is integrated as a submodule and performs signature handling for incoming and outgoing messages automatically, being therefore transparent to the other modules except for the unavoidable processing latency. It is connected to two different on-chip communication systems, one transmitting unsecured messages over an 8-bit wide communication structure (BusNoC small), and the other (BusNoC wide) transmitting only secured messages containing signatures and certificates. These messages are larger because of the additional data, and the latter communication structure is therefore 32 bit wide. A short description of the security system and its system integration is given in [36]. Figure 8 depicts the wrapped signature system with the interfacing to both communication structures.Figure 8
Wrapping of the signature system for V2X integration.This interfacing consists of a Direct Network Access (DNA) controller and two interfaces to the Network-on-Chip (NoC) communication structures. An 8-bit PicoBlaze processor controls and configures the components. The DNA controller manages the intramodular procedure and generates the input and control data to the encapsulated ECDSA module. The register set serves as data interface and buffer for intermediate results.The signature system accepts incoming messages, verifies signatures and certificates, and passes only verified messages on to the Information Processing Module (IPM) for further processing. In case of an invalid signature the outer system (IPM and Routing) is informed. For outgoing messages, signatures are generated, and the corresponding certificate is attached to the message which is then passed on to the wireless interface.


### 6.1. Key Container

In the V2X environment privacy of participants is of major importance. As messages containing vehicle type and further information like current position, speed, and heading are continuously broadcasted from twice to up to ten times a second, these messages could easily be used by an eavesdropper to trace participants. To counter such attempts anonymity in the form of pseudonyms is used that are changed on a regular basis. A number of pseudonyms for change are stored directly in the signature module's key container (see Figure8). It also contains the public keys of trusted certification authorities needed for verification of certificates. The change itself is triggered by a dedicated message sent to the signature processing system by the central information processing module of the C2X system. For all other modules this privacy function is fully transparent as well.


### 6.2. Caching of Certificates

As V2X communication is not deployed in the fleet so far and also realistic field tests with larger numbers of vehicles are only just beginning (e.g., simTD [39] in Germany), large-scale predictions of message numbers and network behaviour have to be based on simulations and estimations. For an estimation of the expected cache hit rate results from the literature are used. Seada [40] show based on real-world measurements on American freeways that the average communication time between two vehicles is approximately 65 seconds. Based on that and assuming a beaconing frequency of 10 Hz and a sufficient cache size in only one out of 650 messages, the certificate has to be validated. In addition pseudonym change has to be regarded. Papadimitratos et al. [41] propose exchange of pseudonyms every 60 seconds. Assuming stochastical independence of both values, a cache hit rate of 99.68% is possible. Since the communication is regular while the peer vehicle is in range, an LRU strategy is suitable. The required cache size depends strongly on the number of vehicles in range and should therefore be adapted to the expected situations.


## 6.1. Key Container

In the V2X environment privacy of participants is of major importance. As messages containing vehicle type and further information like current position, speed, and heading are continuously broadcasted from twice to up to ten times a second, these messages could easily be used by an eavesdropper to trace participants. To counter such attempts anonymity in the form of pseudonyms is used that are changed on a regular basis. A number of pseudonyms for change are stored directly in the signature module's key container (see Figure8). It also contains the public keys of trusted certification authorities needed for verification of certificates. The change itself is triggered by a dedicated message sent to the signature processing system by the central information processing module of the C2X system. For all other modules this privacy function is fully transparent as well.


## 6.2. Caching of Certificates

As V2X communication is not deployed in the fleet so far and also realistic field tests with larger numbers of vehicles are only just beginning (e.g., simTD [39] in Germany), large-scale predictions of message numbers and network behaviour have to be based on simulations and estimations. For an estimation of the expected cache hit rate results from the literature are used. Seada [40] show based on real-world measurements on American freeways that the average communication time between two vehicles is approximately 65 seconds. Based on that and assuming a beaconing frequency of 10 Hz and a sufficient cache size in only one out of 650 messages, the certificate has to be validated. In addition pseudonym change has to be regarded. Papadimitratos et al. [41] propose exchange of pseudonyms every 60 seconds. Assuming stochastical independence of both values, a cache hit rate of 99.68% is possible. Since the communication is regular while the peer vehicle is in range, an LRU strategy is suitable. The required cache size depends strongly on the number of vehicles in range and should therefore be adapted to the expected situations.


## 7. Resources and Performance

The presented system has been realized using a Xilinx XC5VLX110T Virtex-5 FPGA [42] on a Digilent XUP ML509 evaluation board [43]. The following values refer to an implementation of the complete signature generation and verification unit with interfacing for the application example given previously. Table 3 shows an overview of the resource usage.Table 3
Resource usage on an XC5VLX110T with 69.120 LUTs.
LUT-FF Pairs  (synthesis)Rel. res. usage on FPGAMax. frequency (MHz)Signature unit32.29946.7%50ECDSA unit24.63736%50.1Hashing unit2.2773%120.8PRNG4820.7%872.6𝔽p-ALU14.25620%41.2𝔽p-ADD8581.2%83𝔽p-SUB8571.2%92.8𝔽p-MUL2.3203.4%42.3𝔽p-DIV5.6708.2%73.4After integration of all submodules, the ECDSA unit allows a maximum clock frequency of 50 MHz that has been successfully tested. Table4 shows signature verification performance values of the ECDSA unit at 50 MHz. Values for signature generation are given in Table 5.Table 4
Performance of signature verification at 50 MHz.
Verificationsecp224r1secp256r1Compute timeWorst case7.239.42(ms/Sig)Simulated7.179.09ThroughputWorst case138106(Sig/s)Simulated140110LatencyWorst case361.151471.111(Cycles/Sig)Simulated358.478454.208Table 5
Performance of signature generation at 50 MHz.
Generationsecp224r1secp256r1Compute timeWorst case5.567.26(ms/Sig)Simulated5.457.15ThroughputWorst case180138(Sig/s)Simulated184140LatencyWorst case278.097362.881(Cycles/Sig)Simulated272.345357.315In both tables theworst case values given are calculations based on the statistically estimated runtime of the algorithms for scalar multiplication. As these runtimes depend on the operand values, the measured average computation times are different.Direct comparison of the system's performance is difficult, because implementations of complete ECDSA signature and verification units with certificate handling are scarce. So we can only compare the performance of the GF(p) processing unit, where values are available. Table 6 gives an overview in comparison to some implementations presented already in Section 2.Table 6
Performance comparison for signature verification and generation for ECDSA on GF(p). Values marked with an asterisk (*) are only for the core operations scalar multiplication and multiple scalar multiplication, respectively, without all pre- and postprocessing and hashing.
Bit length|p|Hardware resourcesClk (MHz)Generation (kG)Verification (Kg + rQ)Time#/sTime#/sMicrocontroller implementationsDrutarovsky and Varchola [7]233ARM725742 ms1.351240 ms0.8RIM [9]256ARM9EJ-SN.a.168 ms5.95150 ms6.7PC processor implementationseBACS [6]256Motorola PowerPC G4 741053311.7 ms85.214.1 ms70.7Petit [37]256Intel Pentium D34003.33 ms3006.63 ms151eBACS [6]256Intel Atom 33016002.9 ms3453.4 ms294eBACS [6]256Intel Core 2 Duo U940014001.88 ms5322.2 ms455Brown et al. [38]256Intel Pentium II400*1.67 ms*599*6.4 ms*156FPGA implementationsMcIvor et al. [11]256Xilinx Virtex II Pro, 15755 CLB, 256 MUL39.5*3.86 ms*259N.a.N.a.Orlando and Paar [12]192Xilinx Virtex-E, 11416 LUT, 35 BRAM40*3 ms*333N.a.N.a.This paper256Xilinx Virtex 5, 14256 LUT/FF pairs207.15 ms1409.09 ms110ASIC implementationsSakiyama et al. [16]256243K gates (0.25μm)159*4.3 ms*233N.a.N.a.Satoh and Takano [15]256120K gates (0.13μm)138*2.68 ms*373N.a.N.a.


## 8. Discussion

The presented system implements the complete ECDSA signature processing in a modular way. As shown in the application example, it can be integrated as an autonomous subsystem to authenticate message traffic and provide verified information to the overlaying system. In comparison to known full implementations (see Section2), the system's performance of up to 110 verifications per second is by one to two orders of magnitude better than software implementations on microcontrollers, providing sufficient performance for most applications. For high-performance applications like the V2X application example given in detail in Section 6, a still higher throughput of up to 1600 [41, 44], respectively, over 2500 [45] signatures per second is needed though. This can be achieved by a number of optimization steps; see Section 9.The complete signature module from Section6 is nevertheless prepared for further improvements. As can be seen in Figure 8, the ECDSA system is encapsulated as a submodule wrapped by the control and communication system that fits to the external system structure. The ECDSA system can therefore easily be replaced by a more performant system without having to adapt the overall system structure.


## 9. Conclusion and Further Work

We presented a hardware-implemented subsystem for ECDSA signature processing for integration into embedded systems based on reconfigurable hardware. It can be integrated as a stand-alone subsystem performing transparent authentication functionality for communication systems. Applicability of the system has been shown using vehicle-to-X communication as a practical example.The performance values presented in Section7 are sufficient for applications like entry control systems or electronic payment, where the number of communication peers is small. For V2X communication even larger throughput is necessary. Further work therefore includes speeding up the computation. Promising approaches that are subject to ongoing work here are the use of windowing techniques on algorithmic level, the tailored use of optimized representations like projective coordinates on mathematical level, and the speedup of the field operations on implementation level, for example, by the use of hardware multipliers. Also the use of low-cost FPGAs and reduction of the footprint is required for the use in embedded systems.



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*Source: 836460-2011-04-17.xml*