# Demonstration of Ultra-Fast Switching in Nanometallic Resistive Switching Memory Devices

Authors: Xiang Yang
Journal: Journal of Nanoscience
 (2016)

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## Abstract

Interdependency of switching voltage and time creates a dilemma/obstacle for most resistive switching memories, which indicates low switching voltage and ultra-fast switching time cannot be simultaneously achieved. In this paper, an ultra-fast (sub-100 ns) yet low switching voltage resistive switching memory device (“nanometallic ReRAM”) was demonstrated. Experimental switching voltage is found independent of pulse width (intrinsic device property) when the pulse is long but shows abrupt time dependence (“cliff”) as pulse width approaches characteristicR
C time of memory device (extrinsic device property). Both experiment and simulation show that the onset of cliff behavior is dependent on physical device size and parasitic resistance, which is expected to diminish as technology nodes shrink down. We believe this study provides solid evidence that nanometallic resistive switching memory can be reliably operated at low voltage and ultra-fast regime, thus beneficial to future memory technology.


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## Body

## 1. Introduction

Resistive random access memory (ReRAM) offers a competitive solution to future digital memory, given its superior properties such as long data retention, nanosecond speed, high endurance, multibit capability, and flexible scalability [1, 2]. Extensive studies have been conducted to explore the resistive switching speed, which intends to answer the question: how fast “1” can be converted to “0” [3–8]. Researchers found that, in ion-migration system, such switching speed is strongly correlated with applied voltage. Specifically, a larger voltage can inject more energy to the filamentary system, consequently generating higher temperature to facilitate ion migration. Therefore, it requires shorter time to complete resistive switching process. Further numerical simulation confirms such argument, quantitatively predicting that required switching voltage keeps increasing over 4 times from 100 seconds to 100 nanoseconds [5]. This nonlinear switching kinetics is not preferred to the practical demands of fast speed yet low voltage/power in emerging memory systems. On the other hand, in a real integrated memory array, substantial circuit effect could further worsen the situation by introducing R
C delay and voltage partition from interconnect lines [9–12]. A feasible solution to aforementioned problem is through non-temperature related system, such as electronic switching ReRAM [13–16]. In general, electronic resistance switching occursvia trapping or detrapping of electrons, where negligible temperature effects are involved and switching itself only depends on energy landscapes determined by intrinsic material or structure properties. On the other hand, electrons generally “move” faster than ions given its small mass. In this sense, intrinsic switching speed of electronic devices should exceed that of ionic devices. A subpicosecond electronic switching has been demonstrated in [7].In this paper, we demonstrate a switching-time independent ReRAM and explicitly address circuit related problems based on a recent developed nanometallic device. Nanometallic ReRAM is a purely electronic, metal-insulator switching memory built on a hybrid structure, which is composed of atomically dispersed metal inside an insulator matrix. Such ReRAMs exhibit outstanding device properties such as long retention and endurance [17], low power [10], and multilevel capability [9, 11, 12]. Although nanometallic ReRAM can be constructed using a large variety of insulator:metal paring [7, 17], here we focus on Si3N4:Pt films. We will demonstrate that Si3N4:Pt nanometallic ReRAMs can achieve ultra-fast (sub-100 ns) yet low switching voltage and thus are promising to be implemented in future memory systems.


## 2. Materials and Method

A Mo film (20 nm thick), as the bottom electrode, was firstly deposited to an unheated SiO2/Si substrate using DC sputtering. Then the mixture film Si3N4:Pt was cosputtered using separate Si3N4 and Pt targets in a magnetron sputtering system (Initial chamber pressure of Denton sputter system was better than 3 × 10−7 Torr). Afterwards, conventional photolithography and e-beam lithography techniques were used to pattern top electrodes with various sizes, ranging from 512 μm to 5 μm (photolithography) or from 2 μm to 50 nm (e-beam lithography). Eventually, a top Pt electrode (40 nm) was RF-sputter deposited followed by lift-off process. The composition of the nanometallic films was determined to be 93% SiN4/3:7% Pt according to Rutherford Backscattered Spectroscopy (RBS). Figure 1(a) shows top view of SEM image of micron and nano devices. Figure 1(b) shows high resolution TEM image of fabricated SiN4/3:Pt film, where sub-1 nm Pt nanoparticles are distributed evenly in the SiN4/3 film. All pads are well separated and sizes were consistent with our nominal sizes. To characterize the device properties, micron devices were tested using a probe station (Signatone S1160) while nano devices were tested using a conducting atomic force microscope (CAFM, Asylum MFP-3D), by routing electrical signal out to a semiconductor analyzer (Keithley 237) or pulse generator (Agilent 81104A). The schematic of experiment setup is shown in Figure 1(c). For pulse width dependence measurement, we used a pump-probe method: excitation pulse signal with certain pulse width (from 20 ns to 1 s) and voltage height was firstly sent to device and then a small DC voltage (0.2 V) was used to probe the resultant resistance states. A switch box was employed to avoid interference between two electrical sources.Figure 1
(a) Top view SEM image of devices ranging from 512 × 512μm2 to 100 × 100 nm2. (b) Planar view TEM image of 93% SiN4/3:7% Pt films. Dark regions are clustered Pt nanoparticles (<1 nm). (c) The schematic for fabricated Mo/Si3N4:Pt/Pt devices and the experimental setup.
(a)
(b)
(c)


## 3. Results and Discussion

As-fabricated ReRAM devices exhibit bipolar switching behavior, as shown in theR
-
V curve of Figure 2(a). The R-V curve was obtained using the following voltage sweep sequence: 0 V, to 4 V, to −3 V, and to 0 V. Here a positive bias means current flowing from top to bottom electrode. The fabricated devices are electroforming free and thus show a flat resistance in the R
-
V curve (corresponding to a linear I
-
V curve). With an incremental positive voltage, the device gets abruptly “turned off” at V
o
n
→
o
f
f = 3 V. Next, it stays at an insulating or high-resistance state (HRS), which exhibits a nonlinear R
-
V behavior. Under a negative voltage, the HRS jumps back to low-resistance state (LRS) at V
o
f
f
→
o
n = −1 V. In fact, several intermediate states can be observed until the device reaches its final state. Figure 2(b) shows the on → off switching under different pulse widths and heights for a 400 × 400 μm2 cell. Device was initially set at LRS. Then a pulse sequence (0.1 V → 0.2 V → 0.3 V → etc.) with certain width was sent in and a probe signal was followed to check the resistance after each individual pulse (definition: R
=
V
/
I at V = 0.2 V). The test was continued until the device jumps to HRS ~MΩ. After resistance change, the cell was reset to LRS using −3 V DC voltage, which ensures each test starting from exactly same condition. As shown in Figure 2(b), on → off switching voltages are independent of pulse widths ranging from 1 s to 10 μs. As pulse widths are shorter than ~
μs, on → off switching voltage rapidly increases. As pulse width reaches 100 ns, required voltage is as high as 10 V. Similar phenomenon was observed for off → on switching process in Figure 2(c): off → on switching voltage keeps ~−1 V until pulse width <
μs, followed by a rapid increase up to −9 V for 100 ns pulse. It is worthwhile to mention that off → on resistance further decreases with higher voltage, indicating multilevel resistance exists, which is consistent with earlier reports [7, 9–11]. The switching voltage defined in this paper refers to the critical voltage for the first abrupt drop of resistance.Figure 2
(a) Characteristic resistance-voltage (R
-
V) switching curve. The arrows indicate switching direction. (b) Off → on switching by using different pulse widths for a 400 × 400 μm2 device. (c) On → off switching by using different pulse widths for a 400 × 400 μm2 device.
(a)
(b)
(c)Similar phenomenon occurs for other sizes as well. As shown in Figures3(a) and 3(b), every size shows a constant switching voltage up to a threshold pulse width (“cliff”). However, such cliff varies with device lateral dimensions. Smaller sizes exhibit cliff behavior at shorter pulse while larger sizes start to show cliff behavior at a longer pulse. For nano devices with sizes less than 2 × 2 μm2, both on → off and off → on switching voltages are completely independent of pulse width within our testing range (from 20 ns to 1 s). The detailed transient behavior during off → on and on → off is generally abrupt within our instrument capability, which has been reported elsewhere [18].Figure 3
(a) Experimentally measured on → off switching voltageversus pulse widths for various device sizes. (b) Experimentally measured off → on switching voltageversus pulse widths for various device sizes.
(a)
(b)The most intriguing property is switching voltage-time independence before threshold pulse width, which is quite different from any reported data in the literature [5, 8]. Nonlinear switching voltage-time relation is usually observed in traditional ionic systems. Such nonlinearity arises from a voltage induced temperature increase in a few-nanometer-thick region near electrode and an exponential increase in oxygen-vacancy mobility [5]. In this scenario, required switching voltage keeps changing as pulse width varies from ~second to ~nanosecond. However, such ionic migration related phenomenon is absent in nanometallic system, which confirms its electronic switching nature. In nanometallic RERAM, switching depends on whether external voltage can overcome energy barriers and consequently induce electron trapping or detrapping. Such process involves only electron tunneling and thus shows time independency. Of course, electron tunneling speed could determine the ultimate limit of switching speed, but that is far beyond nanosecond region and thus not an issue for current electronic devices.Next, we discuss the “threshold pulse width (cliff)” phenomenon. Apparently, this is not likely an intrinsic property because of device size dependency. Required pulse voltage starts to change at longer pulses for a larger size while remaining unchanged for extreme small size. Such threshold phenomenon can be well understood if we consider theR
C circuit effect. An equivalent circuit of the device is illustrated in Figure 4(a), where a resistor R
B
E is serially connected to R
⫽
C cell. The serial resistor R
B
E can originate from bottom electrode resistance, interface resistance, or any parasitic line resistance. Intrinsic cell can be represented as an ideal R
C parallel circuit. As an ideal square pulse is applied on the entire structure, cells cannot acquire voltage instantly because of capacitor charging effect. Rather, it experiences transient time roughly ~
R
B
E
C to reach the steady state voltage, which is given by V
c
e
l
l
∗
=
(
R
c
e
l
l
/
(
R
c
e
l
l
+
R
B
E
)
)
V. However, if the applied pulse is so short that it starts to disappear before capacitor achieving the designated voltage, then such R
⫽
C cell can never obtain its steady state V
c
e
l
l
∗. As a result, higher voltage V is required to compensate this R
C-delay induced voltage inefficiency. An analytical solution for transient cell voltage can be derived from(1)
i
=
V
-
V
c
e
l
l
R
B
E
=
V
c
e
l
l
R
c
e
l
l
+
C
d
V
c
e
l
l
d
t
.Figure 4
(a) Equivalent circuit: device structure composed of electrode resistorR
B
E (mostly due to spreading resistance in bottom electrode) serially connected to a set of parallel cell resistance R
c
e
l
l and cell capacitance C. Apparent voltage V is larger than the actual cell voltage V
c
e
l
l. (b) Simulated on → off switching voltageversus pulse widths for various device sizes. (c) Simulated off → on switching voltageversus pulse widths for various device sizes.
(a)
(b)
(c)Assuming the square pulse starts fromt
=
0, the cell voltage can be expressed as(2)
V
c
e
l
l
=
R
c
e
l
l
R
c
e
l
l
+
R
B
E
1
-
exp
⁡
-
R
c
e
l
l
+
R
B
E
C
R
c
e
l
l
R
B
E
t
×
V
.R
C-delay time is modified as C
R
c
e
l
l
R
B
E
/
(
R
c
e
l
l
+
R
B
E
), due to shunt effect of cell resistance, which has an upper limit R
B
E
C as cell resistance is infinitely high. Because cell capacitance is linear dependent on size following C
=
ε
d
2
/
δ (ε: dielectric constant, d: cell lateral length, and δ: film thickness) while R
B
E is independent of size, we can expect the delay time ~
R
B
E
C to exhibit strong size dependence. By applying the above expression and assuming the intrinsic cell switching voltage is V
c
e
l
l
o
n
→
o
f
f
=
3
V and V
c
e
l
l
o
f
f
→
o
n
=
-
1
V (from DC switching data in Figure 2(a)) with further assumptions ofC(400 μm) = 700 pF, R
B
E = 800 Ω, R
c
e
l
l
,
H
R
S(400 μm) = 1 MΩ, and R
c
e
l
l
,
L
R
S = 400 Ω, we can obtain Figures 4(b) and 4(c) for on → off and off → on switching, respectively. Consistent with experimental data in Figure 3, larger sizes start to exhibit switching voltage increase at longer pulse width, while smaller sizes postpone such effect to a shorter pulse. For extremely small size (2 × 2 μm2 or less), there is no obvious increase within nanosecond to second range, because delay time ~
R
B
E
C
=
800 Ω  × 18 fF = 15 ps, way below nanosecond. Therefore, it suggests this “threshold” phenomenon is a purely circuit effect.In fact, such switching voltage-time independence is universal in many nanometallic films. Other than Si3N4:Pt film, SiO2:Pt and perovskite nanometallic film LaAlO3:LaNiO3 also exhibit similar independence as illustrated in [19, 20] (SiO2:Pt) and [21] (LaAlO3:LaNiO3). In both cases, required switching voltage again rises up only as pulse widths are less than 100 ns, consistent with circuit induced R
C delay time.Before closing, we discuss the impact of this circuit effect on ever shrinking technology nodes. According to general capacitor theory, device capacitance scales down with device size, followingC
∝
d
2. Such relation is indeed beneficial in terms of extrinsic circuit delay. Although interconnect line resistance would increase as storage size builds up, it follows a weaker (linear) relation R
l
∝
N, where N
×
N is memory size. To provide a rough estimation, we consider the state-of-the-art CMOS technology, for which the typical sheet resistance for metal conductor layers is 0.05 Ω/sq. For 1 Tbits (106  ×  106) memory, such interconnect line resistance reaches 0.05 Ω/sq ×  106 sq or 50 kΩ and a 100 × 100 nm2 cell capacitance is on the order of 0.1 fF (typically C = 100 pF for a 100 × 100 μm2 cell). Therefore, associated R
C delay is as low as 5 ps, which would be trivial for a nanosecond memory device.As for intrinsic switching time, we can conclude that it should be less than our measured lower limit 20 ns. Such bound is acquired from the best case (2μm device) in Figure 3, which possesses the least capacitance and thus smallest R
C time. It is currently difficult to make further conclusion regarding switching time because of experiment limit, but we believe intrinsic switching time is ultimately determined by electrons tunneling time within nanometer barrier, typically ~femtosecond. Such high speed is far beyond state-of-the-art electrical circuit limit (~picosecond) and thus not an issue for current electronic memory at all.


## 4. Conclusion

In conclusion, we have demonstrated and analyzed a switching-time independent electronic ReRAM. By shrinking the device dimension and thus its capacitance, switching voltage can maintain its intrinsic value within a wide range of 1 s to 20 ns and thus a low voltage yet ultra-fast device can be achieved. These results are applicable to other electronic ReRAM systems, which may shed light on future ultra-fast memory. Further advances in developing low voltage, fast switching materials may accelerate the adoption of highly integrated ReRAM in future generations of digital memory.



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*Source: 8132701-2016-08-15.xml*