# High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability

Authors: Ting-Li Chu; Sin-Hong Yu; Chorng-Sii Hwang
Journal: VLSI Design
 (2013)

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## Abstract

In this paper, a high-accuracy programmable timing generator with wide-range tuning capability is proposed. With the aid of dual delay-locked loop (DLL), both of the coarse- and fine-tuning mechanisms are operated in precise closed-loop scheme to lessen the effects of the ambient variations. The timing generator can provide sub-gate resolution and instantaneous switching capability. The circuit is implemented and simulated in TSMC 0.18μm 1P6M technology. The test chip area occupies 1.9 mm2. The reference clock cycle can be divided into 128 bins by interpolation to obtain 14 ps resolution with the clock rate at 550 MHz. The INL and DNL are within −0.21~+0.78 and −0.27~+0.43 LSB, respectively.


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## Body

## 1. Introduction

Time is one of the important properties of the nature. Timing generators, a.k.a. delay generators, are used to produce accurate clock signals with adjustable timing which can be widely applied in the instrumentation and chip system [1–5], like IC testers, pulse generators, logic analyzers, oscilloscopes, and time-to-digital converters. With the advancing progress in IC technology, the timing generator can be implemented and integrated as the analog front-end circuitry with other digital circuitry inside the same chip. In recent designs, delay-locked loops (DLLs) are suitable to provide the timing function in all time issues. And DLLs can also offer precise timing reference signals to ensure the system operation properly. For most timing generators using DLL often providing the resolution of single buffer gate delay, the sub-gate resolution is acquired via gate delay difference [1], external control [2], or phase interpolation [5]. However, these approaches work in open-loop manners. Thus, the open-loop circuitry is very sensitive to ambient variations caused by process, voltage, and temperature. In this paper, a high-accuracy programmable timing generator with wide-range tuning capability is proposed to offer the sub-gate resolution with closed-loop control which alleviates the ambient impacts. With the aid of dual DLL, the delay resolution can be monitored and regulated continuously in switching the timing setting instantaneously.


## 2. Circuit Architecture and Principle of Operation

The proposed circuit architecture and timing operation of the programmable timing generator are depicted in Figure1. Since the aim of the proposed circuit is to divide the clock cycle of the input reference clock into different phases by digital controlled codes, the timing generator is constructed by coarse and fine stages to generate resolutions which are one buffer gate delay and sub-gate delay, respectively. Unlike the conventional architecture using open-loop scheme for the fine tuning, the DLL-based fine timing generator resides in front of the coarse one to provide a delay range less than one gate delay (tC). With a small delay variation on the fine output, the phase deviation of the coarse input can be compensated much easily. Therefore, the closed-loop control can be applied not only to the coarse stage but also the fine stage due to this new topology.Timing generator.
(a)
Architecture
(b)
Timing diagram


## 3. Circuit Description

In this section, the important circuit blocks of the proposed timing generator are explained in the following in detail.


### 3.1. Pseudo-Differential Delay Cell

In order to mitigate the effect of the switching noise caused by the supply potential, the Pseudo-differential delay cell is employed as illustrated in Figure2. The cross-coupled inverters are functioned as a latch to reduce the duty cycle mismatch of the differential output signals. Figure 3 shows the starving-current delay cell (SCDC) with extra controlled current sources and sinks for wide frequency range setting [6]. The coarse control voltage (VC) can tune the charging/discharging currents of SCDC and then the delay inherently. When the current sources and sinks are chosen to be on or off by switch control, SW[0:1], different delay ranges can be selected. SCDC is dedicated for the coarse tuning. As long as the delay transfer characteristics are overlapped in the adjacent digital setting, the delay line consisting of several Pseudo-differential delay cell can accept a continuous frequency range for the input reference clock. Another way to contribute delay is the digital controlled load (DCL) (Figure 4). The DCL with binary-weighted loading will be further fine-tune its delay characteristic via the input analog control (VCTRL). When the value of the digital selection signal (S[0:3]) increases by one, the added delay of the DCL will be equal to one-sixteenth of the delay of SCDC.Figure 2
Pseudo-differential delay cell.Figure 3
Wide-range starving-current delay cell.Figure 4
Digital controlled load.


### 3.2. Fine Timing Generator

The fundamental architecture of the fine timing generator shown in Figure5 looks like the simple delay-locked loop. The coarse control voltage (VC) is derived from the coarse timing generator. The fine timing generator will start its operation when it receives the locking signal (LOCK) from the coarse timing generator. However, in order to obtain the correct control voltage for fine tuning (VCTRL), the number of delay cells is reduced from eight to six. Then the delay line lacks two-buffer gate delay that should be balanced by the digital controlled load. As discussed in previous sub-session, the overall value of the digital selection signals (FSEL and FS1~FS5) in these Pseudo-differential delay cells must be equal to 32 (=16 × 2).Figure 5
Fine timing generator.In order to achieve the instantaneous switching capability, the criteria of setting the digital selection signals are the following two equations:(1)FSEL+FS1=15,(2)FS2+FS3+FS4+FS5=17.
By adding (1) and (2), all the values of the digital selection signals are summed to be 32 which satisfy the requirement of balanced delay described previously. Equation (1) is specially designed to simplify the control mechanism in high-speed operation since FS1 can be the one’s complement of FSEL without any extra arithmetic circuitry. All the other signal values can be preset to derive the best performance.


### 3.3. Coarse Timing Generator

The key design concept of the coarse timing generator depicted in Figure6 comes from the conventional multiphase DLL. The Pseudo-differential delay cells described in previous sub-session are utilized by setting all the digital selection signals to be zeros so as to disable all DCLs. The phase multiplexor accepts and selects the multiphase clocks according to the coarse select signals (CSEL). The coarse resolution is exactly equal to the buffer gate delay of one SCDC. When the input clock (CLKFINE) changes its phase with the different fine selection value (FSEL), the feedback clock (CLKC7) will not be aligned with the input clock. The system stability will be destroyed and the timing jitter will become larger. To compensate the error caused by the instantaneous switching phenomenon, a timing correction circuitry in front of the phase detector (PD) by recalling the previous delay setting is also invented to maintain the loop stability and to eliminate the possible jitter.Figure 6
Coarse timing generator.


## 3.1. Pseudo-Differential Delay Cell

In order to mitigate the effect of the switching noise caused by the supply potential, the Pseudo-differential delay cell is employed as illustrated in Figure2. The cross-coupled inverters are functioned as a latch to reduce the duty cycle mismatch of the differential output signals. Figure 3 shows the starving-current delay cell (SCDC) with extra controlled current sources and sinks for wide frequency range setting [6]. The coarse control voltage (VC) can tune the charging/discharging currents of SCDC and then the delay inherently. When the current sources and sinks are chosen to be on or off by switch control, SW[0:1], different delay ranges can be selected. SCDC is dedicated for the coarse tuning. As long as the delay transfer characteristics are overlapped in the adjacent digital setting, the delay line consisting of several Pseudo-differential delay cell can accept a continuous frequency range for the input reference clock. Another way to contribute delay is the digital controlled load (DCL) (Figure 4). The DCL with binary-weighted loading will be further fine-tune its delay characteristic via the input analog control (VCTRL). When the value of the digital selection signal (S[0:3]) increases by one, the added delay of the DCL will be equal to one-sixteenth of the delay of SCDC.Figure 2
Pseudo-differential delay cell.Figure 3
Wide-range starving-current delay cell.Figure 4
Digital controlled load.


## 3.2. Fine Timing Generator

The fundamental architecture of the fine timing generator shown in Figure5 looks like the simple delay-locked loop. The coarse control voltage (VC) is derived from the coarse timing generator. The fine timing generator will start its operation when it receives the locking signal (LOCK) from the coarse timing generator. However, in order to obtain the correct control voltage for fine tuning (VCTRL), the number of delay cells is reduced from eight to six. Then the delay line lacks two-buffer gate delay that should be balanced by the digital controlled load. As discussed in previous sub-session, the overall value of the digital selection signals (FSEL and FS1~FS5) in these Pseudo-differential delay cells must be equal to 32 (=16 × 2).Figure 5
Fine timing generator.In order to achieve the instantaneous switching capability, the criteria of setting the digital selection signals are the following two equations:(1)FSEL+FS1=15,(2)FS2+FS3+FS4+FS5=17.
By adding (1) and (2), all the values of the digital selection signals are summed to be 32 which satisfy the requirement of balanced delay described previously. Equation (1) is specially designed to simplify the control mechanism in high-speed operation since FS1 can be the one’s complement of FSEL without any extra arithmetic circuitry. All the other signal values can be preset to derive the best performance.


## 3.3. Coarse Timing Generator

The key design concept of the coarse timing generator depicted in Figure6 comes from the conventional multiphase DLL. The Pseudo-differential delay cells described in previous sub-session are utilized by setting all the digital selection signals to be zeros so as to disable all DCLs. The phase multiplexor accepts and selects the multiphase clocks according to the coarse select signals (CSEL). The coarse resolution is exactly equal to the buffer gate delay of one SCDC. When the input clock (CLKFINE) changes its phase with the different fine selection value (FSEL), the feedback clock (CLKC7) will not be aligned with the input clock. The system stability will be destroyed and the timing jitter will become larger. To compensate the error caused by the instantaneous switching phenomenon, a timing correction circuitry in front of the phase detector (PD) by recalling the previous delay setting is also invented to maintain the loop stability and to eliminate the possible jitter.Figure 6
Coarse timing generator.


## 4. Implementation and Simulated Results

To verify the feasibility of the proposed architecture, the two-stage timing generator is designed and implemented in TSMC 0.18μm 1P6M technology. The layout diagram of the proposed circuit is shown in Figure 7. The circuit is implemented and simulated in TSMC 0.18 μm 1P6M technology. The test chip area occupies 1.9 mm2 including I/O pads. The delay transfer characteristic of different setting is shown in Figure 8.Figure 7
Layout diagram.Figure 8
Delay transfer characteristic.All the curves are overlapped to ensure the frequency range is continuous. The locking process is illustrated in Figure9. When the coarse DLL is in lock, the fine DLL starts to work. The reference clock cycle can be divided into 128 bins by interpolation to obtain 14 ps resolution with the clock rate at 550 MHz. The peak-to-peak jitter of the DLL output clock in the static mode is 4.6 ps as shown in Figure 10(a). In the switching mode as depicted in Figure 10(b), the peak-to-peak jitter of the DLL output clock is slightly increased to 6.9 ps. The first 48 clock output phases of the timing generator are demonstrated in Figure 11. The plots of integral and differential nonlinearity (INL/DNL) at 550 MHz are sketched in Figure 12. The INL and DNL are within −0.21~+0.78 and −0.27~+0.43 LSB, respectively. The timing generator can operate at a frequency range within 280–550 MHz. The overall simulated performance is summarized in Table 1.Table 1
Simulated performance summary.
Item
Specification
Technology
TSMC 0.18μm 1P6M
Supply voltage
1.8 V
Reference clock
280~550 MHz
Interpolation bin
8 × 16
Resolution
14 ps*
Output jitter
6.9 ps (p-p)*
INL (LSB)
−0.21~+0.78*
DNL (LSB)
−0.27~+0.43*
Chip area
1.37 × 1.39 mm2
Power consumption
41 mW*
* Represents that input reference clock rate is 550 MHz.Figure 9
Locking process.Simulated jitter histogram.
(a)
In static mode
(b)
In switching modeFigure 11
The first 48 output phases of the timing generator.Nonlinearity performance.
(a)
Integral nonlinearity
(b)
Differential nonlinearity


## 5. Conclusion

In this paper, the high-accuracy programmable timing generator with wide-range tuning capability has been proposed and designed. With the aid of dual DLLs, the timing generator can provide accurate sub-gate resolution with closed-loop delay control and instantaneous switching capability. The circuit is implemented and simulated in TSMC 0.18μm 1P6M technology. The area of the test chip is 1.9 mm2. It can interpolate the reference clock cycle with 128 divisions to obtain 14 ps resolution when running at 550 MHz. The INL and DNL are within −0.21~+0.78 and −0.27~+0.43 LSB, respectively.



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*Source: 803616-2013-05-09.xml*