# A Double-Boost Converter Based on Coupled Inductance and Magnetic Integration

Authors: Hongzhu Li; Ling Zhu; Le Wang
Journal: Active and Passive Electronic Components
 (2021)

---

## Abstract

High-voltage gain converter has a high-frequency use in some industrial fields, for instance, the fuel cell system, the photovoltaic system, electric vehicles, and the high-intensity discharge lamp. In order to solve the problem of the low-voltage gain of traditional boost converter, the double-boost converter with coupled inductance and doubled voltage is proposed, which connects the traditional boost converter in parallel. The voltage gain of the converter is further improved by introducing the voltage-doubled unit of the coupled inductance. Moreover, the clamp capacitor can absorb the leakage inductance in the circuit and reduce the voltage stress of the switch. In addition, two coupled inductors are magnetically collected; then, the loss of the core is analyzed under the same gain. The detailed analysis of the proposed converter and a comparison considering other topologies previously published in the literature are also presented in this article. In order to verify the proposed converter performance, a prototype has been built for a power of 200 W, input and output voltages of 12 and 84 V, respectively, and a switching frequency of 50 kHz. Experimental results validate the effectiveness of the theoretical analysis proving the satisfactory converter performance, whose peak efficiency is 95.5%.


---

## Body

## 1. Introduction

The output voltage of the photovoltaic circuit board is low. A first-level DC converter should be used to connect the grids, which can set the output voltage of the photovoltaic circuit board to reach the voltage requirement of the grid-connected inverter. Meanwhile, due to the influence of light intensity, the output voltage range of the photovoltaic circuit is quite large, so high-gain DC converters have always been one of the research hotspots at home and abroad [1–4].In addition, in order to achieve a high-voltage gain in a conventional boost converter, a high duty cycle should be used, which may result in high power loss. Most converters are required to operate at a higher duty cycle and a higher number of component counts, making it easier to saturate the topology with inductive cores. This puts limitations on the converter. Literature [5] proposed an optimized integration of active switching inductor configuration, trapezoidal voltage doubling unit combined with regenerative boost configuration, suitable for DC-DC converter with a wide range of voltage gain in low duty cycle range, because the input clamped peak current can achieve higher voltage gain at a low duty cycle. In literature [6], switching inductance, switching capacitance, and coupled inductance techniques are implemented using three-winding coupled inductance to achieve high-voltage gain with low turns ratio. With the use of a low-voltage stress power switch, through the recovery of leakage energy, the voltage peak on the power switch can be well suppressed so as to improve the efficiency of the system. The proposed converter in literature [7] is composed of a double switching structure, a three-winding coupling inductor, and two voltage multipliers. The double switching structure is beneficial to reduce the voltage stress and current stress of the switch. Clamping capacitors recover energy from leakage inductors, and the problem of inductor leakage and diode reverse recovery is alleviated, improving efficiency. A novel noncoupled high step-up DC-DC converter is presented in literature [8, 9], which combines passive switched capacitance (PSC) network (also known as 2-cell step (SU2C) with ASL network. The ASL-SU2C converter is formed. The current output feature of ASL-SU2C-CO (which is called in the article ASL-SU2C-CO) and the voltage output (VO) feature of ASL-SU2C-VO are studied, respectively. ASL-SU2C-CO uses fewer switching devices to effectively reduce losses and improve efficiency. There are only two power switches on the current path, and the voltage stress on the active switch is lower. ASL-SU2C-VO has the characteristics of ASL-SU2C-CO and can provide higher static gain, while its switching is subjected to lower voltage stress, which can be better applied in solar and small-scale wind energy systems, storage energy systems, and other applications requiring nonisolated high-order converters. In literature [10], a novel DC/DC converter combining active switch and coupled inductor structure is proposed. The ASL structure reduces the current stress on the switches during the charge interval, the active clamp technology provides zero-voltage transition (ZVT) for all switches, and the leakage inductance can alleviate the reverse recovery problem of the output diode. Literature [11] proposed that the first coupled inductor-based converter employs two-diode capacitor voltage multipliers (VMs) inserted in an innovative way to give it many advantages. The first involves VMs located near the switch and an output circuit, and two VMs work together to provide a very large DC gain. The second method combines forming a new hybrid VM cell with a single VM. The recovery problem of the output diode is eliminated. No spike occurs at its turn-off. Its advantage is eliminating the output diode recovery problem and thus does not result in spikes at its turn-off. In literature [12], a voltage multiplier unit and a switching capacitor unit are combined to achieve low voltage and low current stress efficiency between components. In literature [13–17], a three-phase asymmetric inductor was used to replace a three-phase discrete inductor and an integrated magnetic structure technology was adopted. This reduces the total volume of the core, thus increasing the efficiency of the system. Literature [18] connected the basic boost converter and the voltage-doubled unit in parallel. All stages are activated by the boost switch. Each converter contains a switched capacitor circuit, which has a simple structure and can recover leakage inductance energy. In literature [19], the traditional boost converter and SEPIC converter are used as an alternative structure of the series output module. The boost converter and the SEPIC converter use the same boost inductor and the same switch, which can reduce the input current ripple while maintaining the characteristics of the boost converter. The circuit topology proposed in [20] uses switched capacitor voltage doubler and an integrated LC2D output network to increase the voltage gain of the converter and reduce the voltage stress on the power switch. It has a continuous input current, low-voltage stress on its semiconductor device (less than half of the output voltage), and a constant potential difference between its input and output grounded terminals. The converter is under a wide range of voltage gain and can adapt to the soft output characteristics of the fuel cell. This research proposes a dual boost converter with coupled inductance voltage doubling unit clamped to the ground. In order to effectively improve the voltage gain of the converter, two traditional boost converters are combined in parallel, the clamp capacitor reduces the voltage stress of the switch tube, and the latter stage of the converter adds a coupled inductance voltage double unit composed of a coupled inductor, a diode, and a capacitor, which improves the gain and reduces the voltage stress of the switch tube. Analysis of the topological structure and working principle of the converter is quite detailed and exhaustive. The theoretical analysis shows that the gain of the converter is related to the turns ratio and the duty cycle of the coupled inductor. The coupled inductor is integrated together. Under the same voltage gain, a different duty cycle is obtained by changing the original and secondary side turns ratio n of the coupled inductor. The loss of the magnetic core under different duty cycles is analyzed to obtain the highest efficiency of the converter output. A practical 200 W prototype is built to verify the correctness of the theoretical analysis.


## 2. Topological Structure and Working Principle of the Converter

### 2.1. Topological Structure

The topological structure of the converter is shown in Figure1. Two traditional boost converter topologies are connected in parallel at the input end, and the same structure is combined. The output ends are superimposed in a series to form the front stage of the output converter. The introduction of a coupled inductance voltage-doubled unit in the backstage of the converter further improves the output-input voltage ratio, forming a high-voltage gain boost converter, as shown in Figure 2. On this basis, a clamping capacitor is introduced to absorb the leakage inductance in the coupled inductor and suppress the reverse problem of the diode.Figure 1
Parallel double-boost structure.Figure 2
Double-boost combined converter with the double-voltage coupled inductor.For the convenience of the analysis, the following assumptions are proposed:(1)
All switching tubes and diodes are ideal devices, both switching tubes and diodes are ideal devices, and the conduction voltage drop is zero(2)
The coupled inductor is an ideal device, ignoring its parasitic parameters(3)
The capacitor in the converter is an ideal device, and its capacitance value is large enough to ignore capacitor voltage fluctuations


### 2.2. Working Modes of the Converter

The equivalent circuit of the converter is shown in Figure3. In a switching cycle, the CCM (continuous conduction mode) of the converter has five working modes, and the working waveforms of each mode are presented in Figure 4. Different working modes of each converter have different equivalent circuit diagrams, as shown in Figure 5:(1)
Mode I [t0−t1]: from t0−t1, the switches S1 and S2 are closed; the diodes D1, D2, and D4 are off, and D3 and D5 are on. The equivalent circuit is shown in Figure 5(a). The excitation current iLm starts to rise linearly under the action of the power supply Vin, and the secondary side currents iL1, iL2 present a linearly decreased trend. The power supply, along with the primary and secondary sides of the coupled inductor and the capacitors C1, C2, C3, C4, provides power to C5 and the load together. When the secondary side currents iL1 and iL2 drop to 0, the diodes D3 and D5 are cut off, and mode I ends.(2)
Mode II [t1−t2]: from t1−t2, the switches S1 and S2 are closed; the diodes D1, D2, D3, and D5 are off, and D4 is on. The equivalent circuit is presented in Figure 5(b). The power supply continues to store energy, and that energy goes to the primary side of the coupled inductor. The leakage current iLk and the excitation current iLm rise linearly. The power supply, along with the secondary side of the coupled inductor and also the capacitors C1, C2, C3, C4, forms a closed loop, and the capacitor C5 supplies energy to the load alone. Leakage inductance current iLk shows a linearly rising trend, and when reaching the maximum state, mode II ends.(3)
Mode III [t2−t3]: from t2−t3, the switches S1 and S2 are off, and the diodes D1, D2, and D4 are on. The equivalent circuit is presented in Figure 5(c). The leakage inductance current is reversed, which will cause a linear decrease of the current on the primary side of the coupled inductor. Capacitors C1 and C2 can absorb the leakage inductance in the circuit through diodes, which will result in reducing the voltage stress at both ends of the switch tube; the power supply, the secondary side of the coupled inductor, and also the capacitors C1, C2, C3, C4 together establish a closed loop. As a result, the secondary side of the current of the coupled inductor will gradually decrease. The capacitor C5 supplies energy to the load alone. When the secondary side current drops to 0, diode D4 is off while D5 is on, and mode III ends.(4)
Mode IV [t3−t4]: from t3−t4, the switches S1 and S2 are off; the diodes D1, D2, D3, and D5 are on, while D4 is off. Figure 5(d) shows the equivalent circuit. The leakage inductance current Lk presents a linearly decreasing trend, as it is consistently absorbed by the capacitors, both C1 and C2. The power supply, the primary and secondary sides of the coupled inductor, the diodes D1, D5, and the capacitor C3 together charge C5 and power the load; when the current of diodes D1, D2 drops to 0, the diodes D1, D2 are off, and modal IV ends.(5)
Mode V [t4−t5]: from t4−t5, the switches S1 and S2 are off; the diodes D1, D2, and D4 are off, and D3 and D5 are on. The equivalent circuit is shown in Figure 5(e). At this time, the capacitors C1 and C2 are equivalent to the power supply. The power supply and capacitors C1, C2, and C3 supply energy to the load through the diode D5. When the switches S1 and S2 are on, mode V ends.Figure 3
Equivalent circuit diagram.Figure 4
Converter operation waveform.Figure 5
Equivalent circuit of each operating mode of the converter. (a) Operating mode I. (b) Operating mode II [t1−t2]. (c) Operating mode III [t2−t3]. (d) Operating mode IV [t3−t4]. (e) Operating mode V [t4−t5].
(a)(b)(c)(d)(e)


## 2.1. Topological Structure

The topological structure of the converter is shown in Figure1. Two traditional boost converter topologies are connected in parallel at the input end, and the same structure is combined. The output ends are superimposed in a series to form the front stage of the output converter. The introduction of a coupled inductance voltage-doubled unit in the backstage of the converter further improves the output-input voltage ratio, forming a high-voltage gain boost converter, as shown in Figure 2. On this basis, a clamping capacitor is introduced to absorb the leakage inductance in the coupled inductor and suppress the reverse problem of the diode.Figure 1
Parallel double-boost structure.Figure 2
Double-boost combined converter with the double-voltage coupled inductor.For the convenience of the analysis, the following assumptions are proposed:(1)
All switching tubes and diodes are ideal devices, both switching tubes and diodes are ideal devices, and the conduction voltage drop is zero(2)
The coupled inductor is an ideal device, ignoring its parasitic parameters(3)
The capacitor in the converter is an ideal device, and its capacitance value is large enough to ignore capacitor voltage fluctuations


## 2.2. Working Modes of the Converter

The equivalent circuit of the converter is shown in Figure3. In a switching cycle, the CCM (continuous conduction mode) of the converter has five working modes, and the working waveforms of each mode are presented in Figure 4. Different working modes of each converter have different equivalent circuit diagrams, as shown in Figure 5:(1)
Mode I [t0−t1]: from t0−t1, the switches S1 and S2 are closed; the diodes D1, D2, and D4 are off, and D3 and D5 are on. The equivalent circuit is shown in Figure 5(a). The excitation current iLm starts to rise linearly under the action of the power supply Vin, and the secondary side currents iL1, iL2 present a linearly decreased trend. The power supply, along with the primary and secondary sides of the coupled inductor and the capacitors C1, C2, C3, C4, provides power to C5 and the load together. When the secondary side currents iL1 and iL2 drop to 0, the diodes D3 and D5 are cut off, and mode I ends.(2)
Mode II [t1−t2]: from t1−t2, the switches S1 and S2 are closed; the diodes D1, D2, D3, and D5 are off, and D4 is on. The equivalent circuit is presented in Figure 5(b). The power supply continues to store energy, and that energy goes to the primary side of the coupled inductor. The leakage current iLk and the excitation current iLm rise linearly. The power supply, along with the secondary side of the coupled inductor and also the capacitors C1, C2, C3, C4, forms a closed loop, and the capacitor C5 supplies energy to the load alone. Leakage inductance current iLk shows a linearly rising trend, and when reaching the maximum state, mode II ends.(3)
Mode III [t2−t3]: from t2−t3, the switches S1 and S2 are off, and the diodes D1, D2, and D4 are on. The equivalent circuit is presented in Figure 5(c). The leakage inductance current is reversed, which will cause a linear decrease of the current on the primary side of the coupled inductor. Capacitors C1 and C2 can absorb the leakage inductance in the circuit through diodes, which will result in reducing the voltage stress at both ends of the switch tube; the power supply, the secondary side of the coupled inductor, and also the capacitors C1, C2, C3, C4 together establish a closed loop. As a result, the secondary side of the current of the coupled inductor will gradually decrease. The capacitor C5 supplies energy to the load alone. When the secondary side current drops to 0, diode D4 is off while D5 is on, and mode III ends.(4)
Mode IV [t3−t4]: from t3−t4, the switches S1 and S2 are off; the diodes D1, D2, D3, and D5 are on, while D4 is off. Figure 5(d) shows the equivalent circuit. The leakage inductance current Lk presents a linearly decreasing trend, as it is consistently absorbed by the capacitors, both C1 and C2. The power supply, the primary and secondary sides of the coupled inductor, the diodes D1, D5, and the capacitor C3 together charge C5 and power the load; when the current of diodes D1, D2 drops to 0, the diodes D1, D2 are off, and modal IV ends.(5)
Mode V [t4−t5]: from t4−t5, the switches S1 and S2 are off; the diodes D1, D2, and D4 are off, and D3 and D5 are on. The equivalent circuit is shown in Figure 5(e). At this time, the capacitors C1 and C2 are equivalent to the power supply. The power supply and capacitors C1, C2, and C3 supply energy to the load through the diode D5. When the switches S1 and S2 are on, mode V ends.Figure 3
Equivalent circuit diagram.Figure 4
Converter operation waveform.Figure 5
Equivalent circuit of each operating mode of the converter. (a) Operating mode I. (b) Operating mode II [t1−t2]. (c) Operating mode III [t2−t3]. (d) Operating mode IV [t3−t4]. (e) Operating mode V [t4−t5].
(a)(b)(c)(d)(e)


## 3. Performance Analysis

### 3.1. Voltage Gain Analysis

In order to facilitate calculation and analysis, setLk1=Lk2=Lk, Lm1=Lm2=Lm, The coupling coefficients of the two coupled inductors are both k, and the coupling coefficient k can be expressed as follows:(1)k=LmLm+Lk.Assuming that the turns ratios of the coupled inductors are the same, that is,n, the turns ratio n can be expressed as follows:(2)n=ns1np1=ns2np2.The short transition modes I, III, and V are ignored in order to better analyze the steady state. Only modes II and IV are considered here.In mode II, the loop voltage equation is(3)VLm1=VLm2=kVin,VL1=VL2=nVLm1=nVLm2,VC2−VC4−VL1+VC3−VL2+VC1−Vin=0.In mode IV, the loop voltage equation is(4)VLm1=kVin−VC1,VLm2=kVin−VC2,VLm1+VL1+VC4+VLm2−Vin=0,VLm1+VL2−VC3+VC5+VLm2−Vin=0.On the grounds of the volt-second balance principle of the coupled inductorLm, the following expression of an integral equation is obtained:(5)∫0DTVLmIIdt+∫DTTVLmIVdt=0.According to equations (1) and (3)–(5), the voltage expression of capacitors C1 and C2 is obtained:(6)VC1=VC2=11−DVin.According to equations (1) and (3), the voltage expression of capacitors C3 and C4 is obtained:(7)VC3=2nk−nkD1−DVin,VC4=1+nkD+D1−DVin.According to equations (4), (6), and (7), the voltage gain expression of the converter working in CCM mode is obtained:(8)M=VoVin=1+D+2nk1−D.According to equation (8), there is a strong relationship between the actual gain of the converter, the coupled inductance turns ratio n, and the coupled coefficient k. The relationship curve is presented in Figure 6, which shows that the greater the turns ratio n of the coupled inductor, the more significant the effect of the converter voltage gain. The increase of the leakage inductance Lk will result in a reduction to the coupled coefficient k. In that case, the voltage gain of the converter presents a decreasing trend, which will bring a certain loss of the duty cycle. So in practical applications, the primary and secondary sides of the coupled inductor should be as tightly coupled as possible. Therefore, the higher the coupling degree, the better when the turns ratio is the same.Figure 6
Voltage gain of the converter and the coupled coefficient k and turns ration.Whenk = 1, the voltage gain of the converter is as follows:(9)M=V0Vin=1+D+2n1−D.The voltage stress of the switch tubesS1 and S2 is(10)VvpsS1=VvpsS2=Vin−VLm=11+D+2nVo.The voltage stress of diodesD1 and D2 is(11)VvpsD1=VvpsD2=VC1=Vin1−D=11+D+2nVo.The voltage stress of diodesD3 and D4 is(12)VvpsD3=n1+D+2nVo,VvpsD4=2n1+D+2nVo.The voltage stress of diodeD5 is(13)VvpsD5=2n−1+D+nD1+D+2nVo.According to formulas (10)–(12), the three-dimensional curved surface diagram of the ratio of voltage stress at both ends of switches S1, S2 and diodes D1, D2, D3, D4 to output voltage Vvps/Vo, the coupled inductance turns ratio n, and duty cycle D is shown in Figure 7. It can be seen from Figure 7 that the voltage stress of all power devices is less than the output voltage under different duty cycle D and different turns ratio n. With the increase of turns ratio n, the voltage stress of switch tubes S1 and S2 decreases gradually, the voltage stress of diodes D1 and D2 decreases slowly, and the voltage stress of diodes D3, D4, and D5 increases slowly.Figure 7
The relationship between the voltage stress of switches, diodes, the turns ration, and the duty cycle D.According to the analysis in Section1 above, the voltage stress of the capacitors C1, C2, C3, and C4 is(14)VC1=VC2=11+D+2nVo,VC3=2n−nD1+D+2nVo,VC4=1+nD+D1+D+2nVo.The voltage stress of the output capacitorC5 is(15)VC5=Vo.The three-dimensional surface diagram of the ratio of voltage stress at both ends of the capacitorsC1, C2, C3, C4 to the output voltage Vo, the coupled inductance turns ratio n, and the duty cycle D is shown in Figure 8. It can be seen from Figure 8 that the voltage stress of all capacitors is less than the output voltage if there are different duty cycle D and turns ratio n. The voltage stress of the capacitor C4 will reduce significantly if the turns ratio n improves. However, in this case, the voltage stress of the capacitor C3 will increase greatly. As duty cycle D increases, the voltage stress of capacitors C1 and C2 increases gradually, the voltage stress of C3 reduces significantly, and the voltage stress of C4 increases significantly.Figure 8
Voltage stress of capacitors, turns ration, and duty cycle D.


### 3.2. Comparison of Converter Performance

This section compares the proposed topology with similar high-gain nonisolated structures, such as the three-winding coupled inductor converter [6], ASL-SU2CCO [8], ASL-SU2CVO [9], ZVT converter [10], and the proposed structure in literature [20–24]. The proposed converter is compared with the revealed topologies in the component counts, voltage gain, and the stress of the power switch, as illustrated in Table 1. Under n = 2, the voltage gain curves versus duty cycle and voltage stress on the power switch versus voltage gain are shown in Figures 9 and 10, respectively. The proposed converter can achieve high-voltage gain with lower voltage stress on the power switch.Table 1
Performance comparison of different converters.
TopologySwitches countDiodes countCapacitors countInductors countVoltage gain (M)Power switch voltage stress (Vds/Vin)Common groundProposed24521+2n+D/1−D1/1+D+2nNo[6]23313+n+D/1−D1+Vo/4+n1/1−DNo[8]22331+3D/1−D1/1−DNo[9]23323+D/1−D1/1−DNo[10]42411+n+D/1−D1/1+n+DNo[12]25525+D/1−D1/1−DNo[17]14521+n+nD/1−D1/1+n+nDYes[18]14411+n+nD/1−D1/1+n+nDYes[25]12333+D/1−D1/1−DNo[21]13422+n/1−D3+D/1−DYes[22]14421+n+D/1−D1/2+n+DYes[20]13531+2D/1−D1/1+2DNo[23]1342n+2/1−D1/2+nYes[24]15732+2D/1−D1/2+2DNoFigure 9
Voltage gain comparison curve of the converters.Figure 10
Voltage stress comparison curve of converters’ switches.


## 3.1. Voltage Gain Analysis

In order to facilitate calculation and analysis, setLk1=Lk2=Lk, Lm1=Lm2=Lm, The coupling coefficients of the two coupled inductors are both k, and the coupling coefficient k can be expressed as follows:(1)k=LmLm+Lk.Assuming that the turns ratios of the coupled inductors are the same, that is,n, the turns ratio n can be expressed as follows:(2)n=ns1np1=ns2np2.The short transition modes I, III, and V are ignored in order to better analyze the steady state. Only modes II and IV are considered here.In mode II, the loop voltage equation is(3)VLm1=VLm2=kVin,VL1=VL2=nVLm1=nVLm2,VC2−VC4−VL1+VC3−VL2+VC1−Vin=0.In mode IV, the loop voltage equation is(4)VLm1=kVin−VC1,VLm2=kVin−VC2,VLm1+VL1+VC4+VLm2−Vin=0,VLm1+VL2−VC3+VC5+VLm2−Vin=0.On the grounds of the volt-second balance principle of the coupled inductorLm, the following expression of an integral equation is obtained:(5)∫0DTVLmIIdt+∫DTTVLmIVdt=0.According to equations (1) and (3)–(5), the voltage expression of capacitors C1 and C2 is obtained:(6)VC1=VC2=11−DVin.According to equations (1) and (3), the voltage expression of capacitors C3 and C4 is obtained:(7)VC3=2nk−nkD1−DVin,VC4=1+nkD+D1−DVin.According to equations (4), (6), and (7), the voltage gain expression of the converter working in CCM mode is obtained:(8)M=VoVin=1+D+2nk1−D.According to equation (8), there is a strong relationship between the actual gain of the converter, the coupled inductance turns ratio n, and the coupled coefficient k. The relationship curve is presented in Figure 6, which shows that the greater the turns ratio n of the coupled inductor, the more significant the effect of the converter voltage gain. The increase of the leakage inductance Lk will result in a reduction to the coupled coefficient k. In that case, the voltage gain of the converter presents a decreasing trend, which will bring a certain loss of the duty cycle. So in practical applications, the primary and secondary sides of the coupled inductor should be as tightly coupled as possible. Therefore, the higher the coupling degree, the better when the turns ratio is the same.Figure 6
Voltage gain of the converter and the coupled coefficient k and turns ration.Whenk = 1, the voltage gain of the converter is as follows:(9)M=V0Vin=1+D+2n1−D.The voltage stress of the switch tubesS1 and S2 is(10)VvpsS1=VvpsS2=Vin−VLm=11+D+2nVo.The voltage stress of diodesD1 and D2 is(11)VvpsD1=VvpsD2=VC1=Vin1−D=11+D+2nVo.The voltage stress of diodesD3 and D4 is(12)VvpsD3=n1+D+2nVo,VvpsD4=2n1+D+2nVo.The voltage stress of diodeD5 is(13)VvpsD5=2n−1+D+nD1+D+2nVo.According to formulas (10)–(12), the three-dimensional curved surface diagram of the ratio of voltage stress at both ends of switches S1, S2 and diodes D1, D2, D3, D4 to output voltage Vvps/Vo, the coupled inductance turns ratio n, and duty cycle D is shown in Figure 7. It can be seen from Figure 7 that the voltage stress of all power devices is less than the output voltage under different duty cycle D and different turns ratio n. With the increase of turns ratio n, the voltage stress of switch tubes S1 and S2 decreases gradually, the voltage stress of diodes D1 and D2 decreases slowly, and the voltage stress of diodes D3, D4, and D5 increases slowly.Figure 7
The relationship between the voltage stress of switches, diodes, the turns ration, and the duty cycle D.According to the analysis in Section1 above, the voltage stress of the capacitors C1, C2, C3, and C4 is(14)VC1=VC2=11+D+2nVo,VC3=2n−nD1+D+2nVo,VC4=1+nD+D1+D+2nVo.The voltage stress of the output capacitorC5 is(15)VC5=Vo.The three-dimensional surface diagram of the ratio of voltage stress at both ends of the capacitorsC1, C2, C3, C4 to the output voltage Vo, the coupled inductance turns ratio n, and the duty cycle D is shown in Figure 8. It can be seen from Figure 8 that the voltage stress of all capacitors is less than the output voltage if there are different duty cycle D and turns ratio n. The voltage stress of the capacitor C4 will reduce significantly if the turns ratio n improves. However, in this case, the voltage stress of the capacitor C3 will increase greatly. As duty cycle D increases, the voltage stress of capacitors C1 and C2 increases gradually, the voltage stress of C3 reduces significantly, and the voltage stress of C4 increases significantly.Figure 8
Voltage stress of capacitors, turns ration, and duty cycle D.


## 3.2. Comparison of Converter Performance

This section compares the proposed topology with similar high-gain nonisolated structures, such as the three-winding coupled inductor converter [6], ASL-SU2CCO [8], ASL-SU2CVO [9], ZVT converter [10], and the proposed structure in literature [20–24]. The proposed converter is compared with the revealed topologies in the component counts, voltage gain, and the stress of the power switch, as illustrated in Table 1. Under n = 2, the voltage gain curves versus duty cycle and voltage stress on the power switch versus voltage gain are shown in Figures 9 and 10, respectively. The proposed converter can achieve high-voltage gain with lower voltage stress on the power switch.Table 1
Performance comparison of different converters.
TopologySwitches countDiodes countCapacitors countInductors countVoltage gain (M)Power switch voltage stress (Vds/Vin)Common groundProposed24521+2n+D/1−D1/1+D+2nNo[6]23313+n+D/1−D1+Vo/4+n1/1−DNo[8]22331+3D/1−D1/1−DNo[9]23323+D/1−D1/1−DNo[10]42411+n+D/1−D1/1+n+DNo[12]25525+D/1−D1/1−DNo[17]14521+n+nD/1−D1/1+n+nDYes[18]14411+n+nD/1−D1/1+n+nDYes[25]12333+D/1−D1/1−DNo[21]13422+n/1−D3+D/1−DYes[22]14421+n+D/1−D1/2+n+DYes[20]13531+2D/1−D1/1+2DNo[23]1342n+2/1−D1/2+nYes[24]15732+2D/1−D1/2+2DNoFigure 9
Voltage gain comparison curve of the converters.Figure 10
Voltage stress comparison curve of converters’ switches.


## 4. Working Characteristics of Magnetic Components in Converters

### 4.1. Preselection of Cores

It is known that the output power of the coupled converter is 200 W; the efficiency is assumed to be 80%; the working frequency is 50 kHz; the power loss density per unit volume is 100 mW/cm3; the maximum temperature of the converter is less than 100°C. Choose the core model suitable for the experiment. The design parameters of the converter are presented in Table 2.Table 2
Transformer design parameters.
ParametersNumerical valueInput voltageVin (V)12Output voltageVO (V)84Full-load currentiFL (A)9Magnetic inductanceL (uH)68Switching frequencyf (kHz)50Maximum ripple currentΔIA11Peak short circuit currentisp (A)40Saturation flux densityBs (T)0.3The magnetic core in this article is made of materialF from the Magnetics company. According to the magnetic core manual, the material has the lowest loss when used at 50°C to 80°C. According to the AP method, the preselected magnetic core formula is as follows:(16)Ap=Ae⋅Aw=LispBs⋅iFLK14/3≈1.45,where Bs is the saturation magnetic flux density; isp is the maximum peak current; iFL represents the effective value of the full-load current; K1 stands for the product of the current density and window utilization coefficient, and generally the value is 0.0085. There is a strong connection between the effective cross-sectional area Ae and the maximum power in the magnetic core. Aw is the window area where the magnetic core can wind the wire, which is related to the space of the winding. Therefore, within the allowable space, the larger the product of the two, the better. According to the above formula and the actual application, the model PC36 can be selected for experimental verification. The effective parameters of the magnetic core selected in the experiment are shown in Table 3 [26].Table 3
Effective parameters of the magnetic core.
Magnetic parametersNumerical valuele (mm): length of a magnetic path53.2Ae (mm2): net sectional area202Aemin (mm2)172Ve (mm3): active volume10700AL (nH/T2): inductance coefficient10200Outside diameter, inside diameter, height (mm)35.5, 10.95, 26.2


### 4.2. Design Air Gap Length

According to the working frequency and output power of the experimental design, the pot-shaped magnetic core is adopted. Considering the convenience of winding manufacturing and the magnetic component installation process, the primary side of the two coupled inductors is tightly wound on the core column, which can better make the secondary side coils closely wound on the surface of the primary side, effectively improving the coupling between the inductors. In order to obtain the required inductance, it is necessary to make the hysteresis loop work in the linear region to avoid saturation of the core and to add an air gapδ on the core column. The calculation of the air gap is an approximate iterative process. Assuming that the initial air gap value is δ0, a new air gap value can be obtained by substituting it into the air gap formula δ1. The error between the two air gap values is less than the required value, and the iterative calculation ends.(17)δ=μ0n2AeL1+δDcp2.For the selected PC36 magnetic core,Dcp is the diameter of the core column; μ0 is the permeability in the air. Assuming the initial air gap length δ0=0.7mm, the iterative process is carried out, and the value δ1 is obtained by putting the specific data of the magnetic core into formula (17). Compare the values of δ1 and δ0, if the error is too large, continue the iteration; when the error is less than 0.4%, stop the iterative process.(18)δ=0.75mm.


### 4.3. Core Loss Simulation Analysis

In the general calculation of total loss, the loss value is usually ignored, which means that the core loss is roughly regarded as the sum of hysteresis loss and eddy current loss. Figure11(a) shows the image of the experimental magnetic core, which consists of a cylindrical core of radius r and length l. Here, dr is the differential of the radius r. Assume that the magnetic flux B generated by the current is perpendicular to the cross-section upward. The voltage and current waveforms at both ends of the excitation inductance are shown in Figure 11(b).Figure 11
Core analogy diagram and excitation inductance voltage and current diagram.
(a)(b)When sine wave excitation is applied and switchesS1 and S2 are closed, voltage Vlm and magnetic induction intensity Bsin at both ends of the inductor are follows:(19)VLm=Vin=Ldidt,Bsin=Vo2πfnAe.When the duty cycleD = 0.5, under the excitation of the square wave, the relationship between the electromagnetic induction intensity B0.5 and the excitation voltage Vo can be obtained from the law of electromagnetic induction as follows:(20)B0.5=VoT4nAe.When the duty cycleD changes, so will the magnetic flux density of the core, and the hysteresis loss generated by the magnetic core will also be different. The magnetic flux density amplitude B0 is expressed as follows:(21)B0=VoT2n+D1−DnAe1+D+2n2.Because the hysteresis loss is proportional to the square of the magnetic flux density [13], under the same working conditions, the hysteresis loss caused by different excitation waveforms is the same.(22)Ph∝B02f.According to formulas (21) and (22), the relationship between the hysteresis loss Pe excited by the rectangular wave and the hysteresis loss P0.5 excited by the duty cycle D = 0.5 is(23)PeP0.5=BeB0.52=641−D2n+D21+D+2n4.According to formulas (22) and (23), the relationship between the hysteresis loss under rectangular wave excitation and the hysteresis loss under sine wave excitation is(24)PePsin=641−D2n+D21+D+2n4.From Figure11(a), it can be seen that the expressions of the instantaneous electromotive force, the instantaneous power and the resistance generated by the magnetic core with radius R are(25)E=πr2dBdt,Pe=E2R,R=ρ2πrldr.According to formula (25), the expression of eddy current loss is(26)Pe=πr216πρVs⋅1T∫0TVLmt2dt,where ρ represents the resistivity of the magnetic materials; A = πr2 is the cross-sectional area through which the magnetic flux passes; Vs is the volume of the magnetic core, which is expressed as πr2l. When the circuit is working in a steady state, using the analysis of the working principle of the converters in the first section and the volt-second balance, the following expression can be derived.(27)Pe=18πρn2A⋅21−Dn+D1+D+2n2.When the duty cycle of the boost converter and the value of the duty cycle change, the square wave excitation is 0.5 and the expression of the eddy current loss is(28)PeP0.5=81−Dn+D1+D+2n2.Under the same working conditions, the relationship between the rectangular wave excitation eddy current lossPe and the sinusoidal excitation eddy current loss Psin is(29)PePsin=161−Dn+Dπ21+D+2n2.When the magnetic core of the converter works in the pulse-width modulation (PWM) waveform, the bias currentIdc will be generated, and the corresponding hysteresis loss will increase significantly. When different excitation waveforms produce the same magnetic flux density under the same conditions, even under the DC bias condition, the hysteresis loss will have a similar value. Therefore, the DC bias factor kdc is proposed to show the effect of DC bias on the hysteresis loss, and kdc is only related to magnetic materials.(30)kdc=PePsin.According to formulas (24), (29), and (30), the core loss of boost converter under different duty cycle conditions can be expressed as follows:(31)Pe=kdc641−D2n+D21+D+2n4Psin+161−Dn+Dπ21+D+2n2Psin.Ansoft Maxwell is used here for the finite element simulation. Assuming that the parameters of the two coupled inductors are the same and the voltage gainM is the same, the corresponding duty cycle D can be obtained by adjusting the winding turns ratio n of the primary and secondary sides, and the core loss is analyzed under different duty cycles.


### 4.4. Simulation of Core Loss

The magnetic core parameters are analyzed with a frequencyf of 50 kHz, the coupled inductance turns ratio n of 1, and the duty cycle D of 0.5. The magnetic flux density of the magnetic core Bm is 0.30884 T and the core loss simulation results are shown in Figure 12.Figure 12
Core simulation with duty cycleD = 0.5.Secondly, the model is verified and analyzed when the duty cycle is not 0.5. Frequencyf is still unchanged, and the value of the turns ratio n in the primary and secondary sides is 2; thus, the core loss with the magnetic flux density Bm=2.519×10−2T is shown in Figure 13. The value of the turns ratio n in the primary and secondary sides is 1.5, the core loss with the magnetic flux density Bm=2.5198×10−2T is shown in Figure 14. Table 4 is the analysis and comparison of the theoretical calculation results and the simulation results. It can be seen that the model proposed in this article can accurately evaluate the core loss under different duty cycles.Figure 13
Core simulation with duty cycleD = 0.25.Figure 14
Core simulation with duty cycleD = 0.375.Table 4
Core loss comparison.
Duty cycleDCore lossWSimulation resultCalculation result0.252.417 × 10−42.932 × 10−40.3754.955 × 10−26.178 × 10−20.51.393 × 10−11.824 × 10−1


### 4.5. Loss Analysis

The analytical loss analysis of the proposed converter is performed by considering the parasitic elements of the components. MOSFETs’losses comprise conduction losses (Pcond) and switching losses (Psw), calculated as follows:(32)Pcond,S1=RDSonIS1rms2,Pcond,S2=RDSonIS2rms2,Psw,S1=fswVS1CossVS1+12ILm1ton+toff,Psw,S2=fswVS2CossVS2+12ILm2ton+toff,PS=Pcond,S1+Pcond,S2+Psw,S1+Psw,S2.The conduction losses of the diodes are calculated by(33)Pcond,D1=VF0,D1ID1Avg+Ron,D1ID1rms2,Pcond,D2=VF0,D2ID2Avg+Ron,D2ID2rms2,Pcond,D3=VF0,D3ID3Avg+Ron,D3ID3rms2,Pcond,D4=VF0,D4ID4Avg+Ron,D4ID4rms2,Pcond,D5=VF0,D5ID5Avg+Ron,D5ID5rms2,PD=Pcond,D1+Pcond,D2+Pcond,D3+Pcond,D4+Pcond,D5.The conduction losses of the capacitors are calculated by(34)PC1=RC1IC1rms2,PC2=RC2IC2rms2,PC3=RC3IC3rms2,PC4=RC4IC4rms2,PC5=RC5IC5rms2,PC=PC1+PC2+PC3+PC4+PC5.Coupled inductors losses include copper losses (Pcu, CI) and core losses (Pe, CI):(35)Pcu,CI1=Rp1ILk1rms2,Pcu,CI2=Rp2ILk2rms2,PCI=Pcu,CI1+Pcu,CI2+Pe,CI1+Pe,CI2,PLoss=PS+PD+PC+PCI.The analytical efficiency of the converter is obtained from(36)η%=100×PoutPout+PLoss.Whenfsw = 50 kHz and existing data are substituted into the formula, the final total loss can be obtained as PLoss = 7.46 W, including PS = 2.96 W, PD = 3.34 W, PCI = 0.36 W, and PC = 0.8 W (the loss of coupling inductance is calculated at duty cycle D = 0.5).


## 4.1. Preselection of Cores

It is known that the output power of the coupled converter is 200 W; the efficiency is assumed to be 80%; the working frequency is 50 kHz; the power loss density per unit volume is 100 mW/cm3; the maximum temperature of the converter is less than 100°C. Choose the core model suitable for the experiment. The design parameters of the converter are presented in Table 2.Table 2
Transformer design parameters.
ParametersNumerical valueInput voltageVin (V)12Output voltageVO (V)84Full-load currentiFL (A)9Magnetic inductanceL (uH)68Switching frequencyf (kHz)50Maximum ripple currentΔIA11Peak short circuit currentisp (A)40Saturation flux densityBs (T)0.3The magnetic core in this article is made of materialF from the Magnetics company. According to the magnetic core manual, the material has the lowest loss when used at 50°C to 80°C. According to the AP method, the preselected magnetic core formula is as follows:(16)Ap=Ae⋅Aw=LispBs⋅iFLK14/3≈1.45,where Bs is the saturation magnetic flux density; isp is the maximum peak current; iFL represents the effective value of the full-load current; K1 stands for the product of the current density and window utilization coefficient, and generally the value is 0.0085. There is a strong connection between the effective cross-sectional area Ae and the maximum power in the magnetic core. Aw is the window area where the magnetic core can wind the wire, which is related to the space of the winding. Therefore, within the allowable space, the larger the product of the two, the better. According to the above formula and the actual application, the model PC36 can be selected for experimental verification. The effective parameters of the magnetic core selected in the experiment are shown in Table 3 [26].Table 3
Effective parameters of the magnetic core.
Magnetic parametersNumerical valuele (mm): length of a magnetic path53.2Ae (mm2): net sectional area202Aemin (mm2)172Ve (mm3): active volume10700AL (nH/T2): inductance coefficient10200Outside diameter, inside diameter, height (mm)35.5, 10.95, 26.2


## 4.2. Design Air Gap Length

According to the working frequency and output power of the experimental design, the pot-shaped magnetic core is adopted. Considering the convenience of winding manufacturing and the magnetic component installation process, the primary side of the two coupled inductors is tightly wound on the core column, which can better make the secondary side coils closely wound on the surface of the primary side, effectively improving the coupling between the inductors. In order to obtain the required inductance, it is necessary to make the hysteresis loop work in the linear region to avoid saturation of the core and to add an air gapδ on the core column. The calculation of the air gap is an approximate iterative process. Assuming that the initial air gap value is δ0, a new air gap value can be obtained by substituting it into the air gap formula δ1. The error between the two air gap values is less than the required value, and the iterative calculation ends.(17)δ=μ0n2AeL1+δDcp2.For the selected PC36 magnetic core,Dcp is the diameter of the core column; μ0 is the permeability in the air. Assuming the initial air gap length δ0=0.7mm, the iterative process is carried out, and the value δ1 is obtained by putting the specific data of the magnetic core into formula (17). Compare the values of δ1 and δ0, if the error is too large, continue the iteration; when the error is less than 0.4%, stop the iterative process.(18)δ=0.75mm.


## 4.3. Core Loss Simulation Analysis

In the general calculation of total loss, the loss value is usually ignored, which means that the core loss is roughly regarded as the sum of hysteresis loss and eddy current loss. Figure11(a) shows the image of the experimental magnetic core, which consists of a cylindrical core of radius r and length l. Here, dr is the differential of the radius r. Assume that the magnetic flux B generated by the current is perpendicular to the cross-section upward. The voltage and current waveforms at both ends of the excitation inductance are shown in Figure 11(b).Figure 11
Core analogy diagram and excitation inductance voltage and current diagram.
(a)(b)When sine wave excitation is applied and switchesS1 and S2 are closed, voltage Vlm and magnetic induction intensity Bsin at both ends of the inductor are follows:(19)VLm=Vin=Ldidt,Bsin=Vo2πfnAe.When the duty cycleD = 0.5, under the excitation of the square wave, the relationship between the electromagnetic induction intensity B0.5 and the excitation voltage Vo can be obtained from the law of electromagnetic induction as follows:(20)B0.5=VoT4nAe.When the duty cycleD changes, so will the magnetic flux density of the core, and the hysteresis loss generated by the magnetic core will also be different. The magnetic flux density amplitude B0 is expressed as follows:(21)B0=VoT2n+D1−DnAe1+D+2n2.Because the hysteresis loss is proportional to the square of the magnetic flux density [13], under the same working conditions, the hysteresis loss caused by different excitation waveforms is the same.(22)Ph∝B02f.According to formulas (21) and (22), the relationship between the hysteresis loss Pe excited by the rectangular wave and the hysteresis loss P0.5 excited by the duty cycle D = 0.5 is(23)PeP0.5=BeB0.52=641−D2n+D21+D+2n4.According to formulas (22) and (23), the relationship between the hysteresis loss under rectangular wave excitation and the hysteresis loss under sine wave excitation is(24)PePsin=641−D2n+D21+D+2n4.From Figure11(a), it can be seen that the expressions of the instantaneous electromotive force, the instantaneous power and the resistance generated by the magnetic core with radius R are(25)E=πr2dBdt,Pe=E2R,R=ρ2πrldr.According to formula (25), the expression of eddy current loss is(26)Pe=πr216πρVs⋅1T∫0TVLmt2dt,where ρ represents the resistivity of the magnetic materials; A = πr2 is the cross-sectional area through which the magnetic flux passes; Vs is the volume of the magnetic core, which is expressed as πr2l. When the circuit is working in a steady state, using the analysis of the working principle of the converters in the first section and the volt-second balance, the following expression can be derived.(27)Pe=18πρn2A⋅21−Dn+D1+D+2n2.When the duty cycle of the boost converter and the value of the duty cycle change, the square wave excitation is 0.5 and the expression of the eddy current loss is(28)PeP0.5=81−Dn+D1+D+2n2.Under the same working conditions, the relationship between the rectangular wave excitation eddy current lossPe and the sinusoidal excitation eddy current loss Psin is(29)PePsin=161−Dn+Dπ21+D+2n2.When the magnetic core of the converter works in the pulse-width modulation (PWM) waveform, the bias currentIdc will be generated, and the corresponding hysteresis loss will increase significantly. When different excitation waveforms produce the same magnetic flux density under the same conditions, even under the DC bias condition, the hysteresis loss will have a similar value. Therefore, the DC bias factor kdc is proposed to show the effect of DC bias on the hysteresis loss, and kdc is only related to magnetic materials.(30)kdc=PePsin.According to formulas (24), (29), and (30), the core loss of boost converter under different duty cycle conditions can be expressed as follows:(31)Pe=kdc641−D2n+D21+D+2n4Psin+161−Dn+Dπ21+D+2n2Psin.Ansoft Maxwell is used here for the finite element simulation. Assuming that the parameters of the two coupled inductors are the same and the voltage gainM is the same, the corresponding duty cycle D can be obtained by adjusting the winding turns ratio n of the primary and secondary sides, and the core loss is analyzed under different duty cycles.


## 4.4. Simulation of Core Loss

The magnetic core parameters are analyzed with a frequencyf of 50 kHz, the coupled inductance turns ratio n of 1, and the duty cycle D of 0.5. The magnetic flux density of the magnetic core Bm is 0.30884 T and the core loss simulation results are shown in Figure 12.Figure 12
Core simulation with duty cycleD = 0.5.Secondly, the model is verified and analyzed when the duty cycle is not 0.5. Frequencyf is still unchanged, and the value of the turns ratio n in the primary and secondary sides is 2; thus, the core loss with the magnetic flux density Bm=2.519×10−2T is shown in Figure 13. The value of the turns ratio n in the primary and secondary sides is 1.5, the core loss with the magnetic flux density Bm=2.5198×10−2T is shown in Figure 14. Table 4 is the analysis and comparison of the theoretical calculation results and the simulation results. It can be seen that the model proposed in this article can accurately evaluate the core loss under different duty cycles.Figure 13
Core simulation with duty cycleD = 0.25.Figure 14
Core simulation with duty cycleD = 0.375.Table 4
Core loss comparison.
Duty cycleDCore lossWSimulation resultCalculation result0.252.417 × 10−42.932 × 10−40.3754.955 × 10−26.178 × 10−20.51.393 × 10−11.824 × 10−1


## 4.5. Loss Analysis

The analytical loss analysis of the proposed converter is performed by considering the parasitic elements of the components. MOSFETs’losses comprise conduction losses (Pcond) and switching losses (Psw), calculated as follows:(32)Pcond,S1=RDSonIS1rms2,Pcond,S2=RDSonIS2rms2,Psw,S1=fswVS1CossVS1+12ILm1ton+toff,Psw,S2=fswVS2CossVS2+12ILm2ton+toff,PS=Pcond,S1+Pcond,S2+Psw,S1+Psw,S2.The conduction losses of the diodes are calculated by(33)Pcond,D1=VF0,D1ID1Avg+Ron,D1ID1rms2,Pcond,D2=VF0,D2ID2Avg+Ron,D2ID2rms2,Pcond,D3=VF0,D3ID3Avg+Ron,D3ID3rms2,Pcond,D4=VF0,D4ID4Avg+Ron,D4ID4rms2,Pcond,D5=VF0,D5ID5Avg+Ron,D5ID5rms2,PD=Pcond,D1+Pcond,D2+Pcond,D3+Pcond,D4+Pcond,D5.The conduction losses of the capacitors are calculated by(34)PC1=RC1IC1rms2,PC2=RC2IC2rms2,PC3=RC3IC3rms2,PC4=RC4IC4rms2,PC5=RC5IC5rms2,PC=PC1+PC2+PC3+PC4+PC5.Coupled inductors losses include copper losses (Pcu, CI) and core losses (Pe, CI):(35)Pcu,CI1=Rp1ILk1rms2,Pcu,CI2=Rp2ILk2rms2,PCI=Pcu,CI1+Pcu,CI2+Pe,CI1+Pe,CI2,PLoss=PS+PD+PC+PCI.The analytical efficiency of the converter is obtained from(36)η%=100×PoutPout+PLoss.Whenfsw = 50 kHz and existing data are substituted into the formula, the final total loss can be obtained as PLoss = 7.46 W, including PS = 2.96 W, PD = 3.34 W, PCI = 0.36 W, and PC = 0.8 W (the loss of coupling inductance is calculated at duty cycle D = 0.5).


## 5. Experimental Results and Analysis

### 5.1. Circuit Experimental Verification

To verify the correctness of the principles in this article, a 200 W experimental prototype was made in the laboratory. The parameters of the experimental prototype are as follows: input voltageVin = 12 V, switching frequency f = 50 kHz, capacitance C1 = C2 = C3 = C4 = 100 μF/50 V, C5 = 100 μF/250 V, load R = 100 Ω. Coupled inductance turns ratio n is 1. The coupled inductor adopts the tank-type soft ferrite PC36 core. The main circuit parameters are shown in Table 5.Table 5
Main circuit parameters.
Experimental parameters/componentsNumber/modelInput voltageVin (V)12Output voltageVo (V)84Rated powerPo (W)200Coupled inductance turnnns/np = 1 : 1InductanceL1 (μH)68InductanceL2 (μH)67.8Leakage inductanceLk (μH)1.28CapacitanceC1/C2/C3/C4100μF/50 VOutput capacitanceC5100μF/250 VSwitch tubeS1/S2IRF540NDiodeD1/D2MBR20100CTDiodeD3/D4MBR20100CTDiodeD5MBR20100CTSwitching frequencyf (kHz)50Figure15 shows the input and output waveforms of the converter. It can be seen that the converter achieves a high-gain conversion of 12 V input and 84 V output, which conforms to the theoretical analysis. Figure 16 shows the driving waveforms of the two switch tubes of the converter. Figures 17 and 18, respectively, indicate the voltage stress waveform diagrams of the diode. It can be seen from the figure that the voltage stress of the switch and the diode are less than the output voltage, and the converter has relatively small voltage stress.Figure 15
Output/input waveform.Figure 16
Waveform ofVs1 and Vs2.Figure 17
Waveform ofVD1 and VD2.Figure 18
Waveform ofVD3 and VD4.Figure19 shows the current waveforms of the coupled inductor and the switching tube. Figures 20 and 21 show the current waveforms of the main diodes. It can be seen that the diodes have achieved zero current cutoff, and the theoretical analysis is confirmed by all the experimental results.Figure 19
Coupled inductor/switch waveform.Figure 20
Waveform ofiD1 and iD5.Figure 21
Waveform ofiD3 and iD4.When the output voltage is constant at 84 V, the efficiency curve of the converter is obtained by changing the power load, as shown in Figure22. The load can be adjusted and tends to be stable when the efficiency of the prototype keeps increasing. When the output power increases, so does the efficiency of the prototype. Moreover, when the output power is equal to 50 W, the efficiency of the prototype is the highest, about 95.5%.Figure 22
Efficiency curve of the prototype.


## 5.1. Circuit Experimental Verification

To verify the correctness of the principles in this article, a 200 W experimental prototype was made in the laboratory. The parameters of the experimental prototype are as follows: input voltageVin = 12 V, switching frequency f = 50 kHz, capacitance C1 = C2 = C3 = C4 = 100 μF/50 V, C5 = 100 μF/250 V, load R = 100 Ω. Coupled inductance turns ratio n is 1. The coupled inductor adopts the tank-type soft ferrite PC36 core. The main circuit parameters are shown in Table 5.Table 5
Main circuit parameters.
Experimental parameters/componentsNumber/modelInput voltageVin (V)12Output voltageVo (V)84Rated powerPo (W)200Coupled inductance turnnns/np = 1 : 1InductanceL1 (μH)68InductanceL2 (μH)67.8Leakage inductanceLk (μH)1.28CapacitanceC1/C2/C3/C4100μF/50 VOutput capacitanceC5100μF/250 VSwitch tubeS1/S2IRF540NDiodeD1/D2MBR20100CTDiodeD3/D4MBR20100CTDiodeD5MBR20100CTSwitching frequencyf (kHz)50Figure15 shows the input and output waveforms of the converter. It can be seen that the converter achieves a high-gain conversion of 12 V input and 84 V output, which conforms to the theoretical analysis. Figure 16 shows the driving waveforms of the two switch tubes of the converter. Figures 17 and 18, respectively, indicate the voltage stress waveform diagrams of the diode. It can be seen from the figure that the voltage stress of the switch and the diode are less than the output voltage, and the converter has relatively small voltage stress.Figure 15
Output/input waveform.Figure 16
Waveform ofVs1 and Vs2.Figure 17
Waveform ofVD1 and VD2.Figure 18
Waveform ofVD3 and VD4.Figure19 shows the current waveforms of the coupled inductor and the switching tube. Figures 20 and 21 show the current waveforms of the main diodes. It can be seen that the diodes have achieved zero current cutoff, and the theoretical analysis is confirmed by all the experimental results.Figure 19
Coupled inductor/switch waveform.Figure 20
Waveform ofiD1 and iD5.Figure 21
Waveform ofiD3 and iD4.When the output voltage is constant at 84 V, the efficiency curve of the converter is obtained by changing the power load, as shown in Figure22. The load can be adjusted and tends to be stable when the efficiency of the prototype keeps increasing. When the output power increases, so does the efficiency of the prototype. Moreover, when the output power is equal to 50 W, the efficiency of the prototype is the highest, about 95.5%.Figure 22
Efficiency curve of the prototype.


## 6. Conclusion

On the basis of the parallel double-boost structure, a unit with coupled inductance and doubled voltage is proposed, as well as a new type of converters with high-gain and low-voltage stress. Moreover, the voltage gain of the coupled inductance high-gain converter in CCM mode, along with the voltage stress of switches and diodes, is derived. Secondly, a core loss model of the converter is formed and then verified through the finite element simulation results. Experimental analyses and verification are done and the converter proposed in this article has the following features:(1)
A coupled inductance doubled-voltage unit is introduced into the converter, which greatly improves the voltage gain and simplifies the design difficulty of the converter.(2)
The leakage inductance in the coupled inductor affects the parasitic capacitance generated by the converter. The clamping capacitor can absorb the energy of the leakage inductance in the coupled inductor, which can effectively reduce the voltage impulse in the switch tube.(3)
Taking ferrite magnetic materials as the research object, while maintaining the same voltage gain, the core loss modeling calculation of the converter is compared with the finite element analysis; the core loss of the converter is evaluated; the model of core loss analysis and modeling is correct.(4)
If the converter is used in a special case (PV systems), techniques for reducing common-mode voltage and leakage current must be employed since, in the proposed converter, there is no common ground between the input and output.



---

*Source: 8014620-2021-12-31.xml*