# Large-Signal DG-MOSFET Modelling for RFID Rectification

Authors: R. Rodríguez; B. González; J. García; A. Lázaro; B. Iñiguez; A. Hernández
Journal: Advances in Condensed Matter Physics
 (2016)

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## Abstract

This paper analyses the undoped DG-MOSFETs capability for the operation of rectifiers for RFIDs and Wireless Power Transmission (WPT) at microwave frequencies. For this purpose, a large-signal compact model has been developed and implemented in Verilog-A. The model has been numerically validated with a device simulator (Sentaurus). It is found that the number of stages to achieve the optimal rectifier performance is inferior to that required with conventional MOSFETs. In addition, the DC output voltage could be incremented with the use of appropriate mid-gap metals for the gate, as TiN. Minor impact of short channel effects (SCEs) on rectification is also pointed out.


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## Body

## 1. Introduction

Nowadays, SOI technology offers wafers with thin and uniformly distributed oxide layers, exhibiting excellent electrical insulation and very high quality silicon/oxide interfaces. These properties encourage the design of different multiple-gate devices [1–4] and development of compact models to account for their performance [5–7]. However, there is a lack of papers on applications with this type of transistors. The aim of this work, based on electrical simulations, is to demonstrate the feasibility of using Double Gate MOSFETs (DG-MOSFETs) in rectifier circuits for RFIDs and Wireless Power Transmission (WPT) applications [8, 9] at microwave frequencies. The application of this technology for rectifier circuits has not yet been reported elsewhere, as far as we know.The topology of the rectifier under consideration is shown in Figure1, where two n-channel transistors, acting as charge pump, are connected [10]. The rectifier converts RF input to DC output power, as Figure 2 indicates. Gate and drain interconnections force transistors to operate in saturation or cut-off regimes. Thus, when the RF input signal, VRF, is in its negative half cycle, with VRF>Vth>0 and Vth being the threshold voltage, the drain current of transistor DG-M1, Ids1, flows from ground to the coupling capacitor, with Cc=1pF, and transistor DG-M2 remains off. Conversely, in the positive half cycle, with VRF>Vth, DG-M2 turns on, flowing its current, Ids2, from the input terminal to the smoothing capacitor, with Cs = 1 pF, with DG-M1 remaining off. In another case, both currents, Ids1 and Ids2, are null. This process is repeated until the steady state is reached, when a DC output voltage is generated [10].Figure 1
Schematic of the rectifier.Figure 2
Rectification mechanism.When DG-M2 switches off,Cs can be discharged through load resistance, causing output ripples. In our study, we will assume a 10 kΩ output load to compare our results with those reported in [11].The structure of this paper is as follows. In Section2, the compact model implemented in the large-signal equivalent circuit is presented, including intrinsic capacitance for DG-MOSFETs. Section 3 is devoted to analyse the rectifier performance, which is validated through numerical simulations with Sentaurus [12]. Technological and design aspects, as the use of different gate metal and number of stages, are also analysed in this section. Finally, some conclusions are exposed in Section 4.


## 2. Large-Signal Equivalent Circuit

The large-signal equivalent circuit proposed for the undoped DG-MOSFETs, with pads, is shown in Figure3 [13]. It is composed by the intrinsic current, Ids, and capacitance from gate-to-source, Cgs, gate-to-drain, Cgd, and drain-to-source, Cds, and extrinsic source and drain resistances, Rs=Rd=0.32 Ω, and the extrinsic inductances, Ls=Ld=10-13 H.Figure 3
DG-MOSFET large-signal equivalent circuit.The intrinsic current, based on the charge control model in [6], is given by(1)Ids=WμL2βQs-Qd+Qs2-Qd24Cox+8β2CSiln⁡Qd+2QoQs+2Qo,with the inversion charge, Q, being evaluated as(2)Q=2Cox-2Coxβ2Qo+2Coxβ2Qo2+4β2ln2⁡1+exp⁡Vgs-Vth+ΔVth-V2β,where β is the thermal voltage, Qo=4βCSi(CSi=εSi/tSi),Cox=εSiO2/tox,Qs=Q(V=0), and Qd=Q(V=Vds), with Vth and ΔVth (to assure the correct behaviour of Q above threshold) as in [5].For DG-M1 and DG-M2, a constant mobility,μ = 300 cmV−1s−1, is assumed, and the gate length, L, and gate width, W, are set to 0.18 μm and 3.6 μm, respectively, with a gate oxide thickness of tox = 2 nm, n+ polysilicon gate, and tSi = 20 nm for the thickness of the nonintentionally doped silicon layer.Setting the gate-to-drain bias voltage,Vgd, the gate-to-source capacitance can be obtained as(3)Cgs=dQTotdVgsVgd=dQTotdQs+dQTotdIds·dIdsdQs·dQsdVgsVgd,where QTot is the total channel charge in [6] and(4)dQTotdQs=W2μIds·Qs22Cox+βQs+βQs2Qs+2Qo,(5)dIdsdQs=WμL·2β+Qs2Cox-8β2CSiQs+2Qo,(6)dQsdVgs=11/2Cox+β1/Qs+1/Qs+2Qo.Substituting (4)–(6) in (3), with dQTot/dIds=-QTot/Ids,Cgs, finally results in(7)Cgs=W2μ/IdsQs2/2Cox+βQs+βQs2/Qs+2Qo-QTot/WL·2β+Qs/2Cox-8β2CSi/Qs+2Qo1/2Cox+β1/Qs+1/Qs+2Qo.In a similar way, the drain-to-source capacitance can be written as(8)Cds=-dQDdVdsVgd=-dQDdQs+dQDdIds·dIdsdQs·dQsdVdsVgd,where QD is the total drain charge in [6]. Then, by replacing (5) in (8), with dQs/dVds=dQs/dVgs (see (6)) and dQD/dIds=-2QD/Ids,Cds is given by(9)Cds=2WμQD/LIds·2β+Qs/2Cox-8β2CSi/Qs+2Qo-dQD/dQs1/2Cox+β1/Qs+1/Qs+2Qo,with(10)dQDdQs=Qd3-Qs3/βCox+6Qd2-Qs2-12QoQd-Qs+24Qo2ln⁡2Qo+Qd/2Qo+Qs12CoxLIds22Qo+Qs/βW3μ24βCoxQo+Qs+2QoQs2.Finally,Cgd can be obtained by replacing Qs by Qd in (7), taking into account the DG-MOSFET symmetry. Therefore, Cgd is given by(11)Cgd=W2μ/IdsQd2/2Cox+βQd+βQd2/Qd+2Qo-QTot/WL·2β+Qd/2Cox-8β2CSi/Qd+2Qo1/2Cox+β1/Qd+1/Qd+2Qo.Note that all the capacitance and the drain current can be explicitly expressed in terms of the charge density in source and drain,Qs and Qd.


## 3. Rectifier Performance

We implement the large-signal equivalent circuit for the DG-MOSFET in Keysight Advanced Design System (ADS), using Verilog-A, which is the industry standard modelling language for analogic circuits [14].In the rectifier under consideration (see Figure1), gate and drain terminals in both DG-MOSFETs are short-circuited. Thus, Cgd can be ignored, and Cgs and Cds depend only on the drain-to-source voltage, Vds. Additionally, as Figure 4 shows, to avoid divergence problems by asymptotical response for Vds close to zero, Cgs modelled capacitance and Cds modelled capacitance (represented with symbols) are approximated by sigmoidal functions (represented with lines) as(12)CξdVgd=0≈A0ξ1+eA1ξ+A2ξVds+A3ξ,withξ≡g,d,with A0ξ,A1ξ,A2ξ, and A3ξ being fitting parameters, summarised in Table 1.Table 1
Fitting parameters forCgs and Cds.
A 0 g , A 0 d A 1 g ,  A 1 d A 2 g , A 2 d A 3 g , A 3 d (×10−14 Fcm−2) — (V−1) (×10−14 Fcm−2) −1.3, 3.3 −15.3, −4.9 15.1, 11.4 1.3, −3.3Figure 4
ModelledCgs and Cds (with symbols) and their sigmoidal approximations (with lines) versus drain-to-source voltage.The electrical simulations for the rectifier in ADS are validated through numerical simulations with Sentaurus, accounting for the extrinsic elements of the transistors. Thus, Figures5(a) and 5(b) show the dynamic drain current for DG-M1 and DG-M2, respectively, with RF input signal of 1 V amplitude at 1 GHz, after 10 ns (i.e., at steady values). It can be noticed that the numerical dynamic current (with symbols) is correctly modelled (with line) in both transistors. An unexpected negative modelled current for DG-M2, being off, appears, when ADS artificially adds auxiliary resistance, between gate and source, to facilitate convergence. However, its short duration, inferior to 0.1 ns, makes DC output voltage deviations irrelevant.Figure 5
Numerical (with symbols) and modelled (with solid line) steady-state dynamic current for (a) DG-M1 and (b) DG-M2, with an input signal of 1 V amplitude at 1 GHz.
(a) (b)Additionally, Figure6 shows the numerical (with symbols) and modelled (with line) DC output voltage, varying the RF input power, at 5 GHz, from −5 dBm to 10 dBm. A good agreement between both data is achieved, with a maximum relative error of 11.7%. Furthermore, the resulting power conversion efficiency (DC output − RF input power ratio) is similar to that reported in [10], with conventional MOSFETs.Figure 6
Numerical (with symbols) and modelled (with line) rectified output voltage as function of the RF input power at 5 GHz.Once the rectifier performance with ADS has been numerically validated, Figure7 compares the transistor response for the electrical output voltage (with squares), for an input power of 5 dBm at 5 GHz, with that for the rectifier implemented in HSPICE with commercial 0.18 μm-NMOS, from Texas Instruments, with identical dimensions (with solid line). Note that a similar DC output voltage of around 0.6 V is obtained, even when the threshold voltage for the NMOS is 0.18 volts lower than that for the DG-MOSFET (0.55 V), which is compensated with its double current capability.Figure 7
Transient response for the rectified output voltage with conventional DG-MOSFETs (squares), Texas Instruments 0.18μm-NMOS (solid line, with HSPICE), and DG-MOSFETs with TiN (dotted line), for an input power of 5 dBm at 5 GHz.When threshold voltage is reduced, by using alternative gate metals, a higher rectified output voltage is expected. The use of titanium nitride (TiN) films as gate electrode in MOS capacitors and in Schottky diodes on n-type Si (100) substrates has been reported in [15], having a work function of 4.2 eV and electrical resistivity of 270 μΩcm. Thus, when using TiN as the metal gate in the DG-MOSFETs, as Figure 7 indicates, the DC rectified voltage (with dotted line) grows (0,25 V) up to 0.83 V.On the other hand, the influence of the number of stages on the rectified output voltage has been analysed. In every stage (single rectifier in Figure1), the source of DG-M2 must be connected to the drain of DG-M1 in next stage, with all coupling capacitance connected to the common RF input signal. Thus, the output voltage (with an output load of 10 kΩ) is the sum of all voltages between the terminals of the smoothing capacitances, which are connected in series.Figure8 shows the electrical output voltage when varying the RF input power from −5 dBm to 10 dBm, for different number of stages: from one to five, at 5 GHz with TiN as gate metal. Note that, up to two stages, the output voltage increases, decreasing with additional stages: two is the optimal number of stages in the rectifier with DG-MOSFETs. This result differs from that reported in [10], with conventional N-MOSFETs, where six stages is the optimal configuration. Therefore, smaller number of stages than with conventional MOSFETs is necessary to produce the maximum output voltage with DG-MOSFETs.Figure 8
Modelled rectified output voltage for multiple stage configurations as function of the RF input power at 5 GHz with TiN.Finally, it can be pointed out that with short channel effects (SCEs) a superior current and, consequently, a higher DC output voltage would be expected. However, when incorporating the saturation velocity, effective mobility, and channel length modulation effects, as in [5], a minor impact on the DC output voltage is appreciated, which only increases 1.3% for an input power as high as 5 dBm (at 5 GHz, with TiN), evidencing a determinant circuital topology influence.


## 4. Conclusions

A compact model for DG-MOSFETs has been developed and implemented in ADS, with Verilog-A, to perform electrical simulations of RFID rectifiers, which have been validated through numerical simulations with Sentaurus.From transient simulations at microwave frequencies, it has been observed that the proposed rectifier with DG-MOSFETs efficiently produces a DC output voltage. Furthermore, using TiN as metal gate, the DC output voltage increases 0.25 V, compared with that obtained with n+ polysilicon. We have also demonstrated that just two stages are necessary to achieve the optimal performance of the rectifier, less than with conventional N-MOSFETs, and that SCEs have a minor impact on the DC output voltage.



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*Source: 8017139-2016-10-26.xml*