# Design of New High Step-Up DC-DC Converter Topology for Solar PV Applications

Authors: Shanthi Thangavelu; Prabha Umapathy
Journal: International Journal of Photoenergy
 (2021)

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## Abstract

A new topology for high step-up nonisolated DC-DC converter for solar PV applications is presented in this paper. The proposed high-voltage gain converter topology has many advantages like low-voltage stress on the switches, high gain with low duty ratio, and a continuous input current. The analytical waveforms of the proposed converter are presented in continuous and discontinuous modes of operation. Voltage stress analysis is conducted. The voltage gain and efficiency of the converter in presence of parasitic elements are also derived. Performance comparison of the proposed high-gain converter topology with the recently reported high-gain converter topologies is presented. Validation of theoretical analysis is done through the test results obtained from the simulation of the proposed converter. For the maximum duty ratio of 80%, the output voltage of 670 V is observed, and the voltage gain obtained is 14. Comparison of theoretical and simulation results is presented which validates the performance of the proposed converter.


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## Body

## 1. Introduction

The application of renewable energy sources for day-to-day life is increasing widely. This is due to clean and green nature of energy produced by renewable energy sources. Among the renewable energy sources, solar energy is most promising because of its pollution-free nature. But the output voltage obtained from the solar photovoltaic (PV) panels is very low, and therefore, it cannot be connected to high-voltage load or grid directly. Therefore, a dc-dc conversion stage with high gain is required to interface the solar PV with high-voltage load or grid. Many high-gain DC-DC converters were reported in the last one decade. But the design improvement of these high-gain DC-DC converters with respect to increased voltage gain, component reduction, increased efficiency, and reduced losses is still being reported by many researchers. These high-gain DC-DC converters also find their applications in fuel cells, electric vehicles, battery energy storage, automotive industries, and uninterrupted power supplies [1–4].Basically, there are two types of DC-DC converters, namely, nonisolated and isolated DC-DC converters. Isolated DC-DC converters mainly used in high power applications. But the presence of transformers increased the converter size. The conventional boost converters are used in the earlier stages for stepping up the voltage, but the limitation is the high-voltage stress on the switch, and hence, high-rating switch is needed.An interleaved high step-up boost converter was proposed in [5] for PV applications. This converter provides a high efficiency and high step-up gain, but this converter uses more number of components which leads to increase in losses at higher loads due to the effect of parasitic elements. Converters reported in [6, 7] employed a switched capacitor structures to achieve a high step-up conversion ratio. Even though this technique provides a high conversion ratio, the stability of the converter reduces due to the presence of impulse current.A nonisolated high step-up DC-DC converter with single-inductor energy storage cell based switched capacitor configuration was proposed in [8]. This configuration was derived from the basic boost-, buck-boost-, and type II boost/buck-boost-based converters. This converter integrates the merits of high gain of switched capacitor (SC) converter and high output voltage regulation of switching mode DC-DC converter.A high-gain nonisolated DC-DC converter for DC microgrids was proposed in [9]. This converter used voltage multiplier cell and hybrid switched-capacitor technique. Here, the switches are operated with a combined duty ratio of maximum 95% to achieve the gain. Clamping circuits used increase the circuit complexity. A nonisolated converter with automatic output voltage balancing was reported in [10]. High step-up DC-DC converter with active switched LC-network was proposed in [11]. This converter uses an active switched capacitor and inductor network. Input-parallel output-series dc-dc boost converter was reported in [12]. Here, the input current ripple is reduced by adopting interleaved structure. Though the gain and efficiency are more, the number of components used are more which increases the size and cost.A dc-dc multilevel boost converter which combines the boost converter and a switched capacitor was reported in [13]. This converter operates with a continuous input current and high switching frequency. Cascaded structure for n-stage conversion is also discussed. A nonisolated boost DC-DC converter based on voltage-lift technique with a single switch was reported in [14]. This technique is based on energy storage elements inductor and capacitor. But the increase in number of components makes the system complex. A new family of single-switch three-diode dc-dc pulse width-modulated (PWM) converters operating at constant frequency and constant duty cycle was discussed in [15]. There is a less-voltage stress on the diodes and decreased switch and conduction losses. Voltage multipliers can be integrated to increase the voltage gain.A transformerless inverter with active power decoupling was reported in [16]. An extended duty ratio (EDR) boost is implemented as the high-gain dc-dc stage. A high step-up DC-DC converter with active switched inductor and passive switched capacitor networks was proposed in [17]. Here, voltage stresses are minimal. Extendable nonisolated high-gain DC-DC converter based on active-passive inductor cells was proposed in [18]. The principle of operation is based on parallel charging and series discharging of the inductors. This uses more number of components; hence, more complex is the system. Recently, coupled inductors find their applications in DC-DC converters to obtain a high-voltage gain. This leads to a compact system because of only one inductor [19–23]. A single-switch buck-boost DC/DC converter [24], SEPIC-based single switch buck/boost DC/DC converter with continuous input current [25], and a single-switch quadratic buck/boost DC/DC converter with continuous input and output current [26] were also reported. In all these single-switch converters, the number of capacitors, inductors, and diodes are more. The converter reported in [27] used switched inductor concept and uses two switches. [29] reports the quasiswitched converter which produces high gain with the low duty ratio. An interleaved converter with inverting capability is reported in [28]; even though the gain is high, the total components required is more. Therefore, the need for a high-gain transformerless DC-DC converter with less number of components arises to enhance the dc-link voltage.Figure1 shows the application of high-gain DC-DC converter in grid-connected solar PV system. In this paper, a new topology for a high-gain DC-DC converter is introduced. The proposed high-gain DC-DC converter uses three switches. The operating principle of the proposed converter in continuous conduction mode (CCM) and discontinuous conduction mode (DCM) are explained, and the boundary conditions are derived. Performance comparison of the proposed high-gain converter topology and the other recent high-gain topologies is made and analyzed. Simulink model of the proposed converter is developed, and the results were presented and discussed in detail.Figure 1
A high-voltage gain DC-DC converter in grid tied solar PV application.


## 2. Principle of Operation of Proposed Converter

A high-gain DC-DC converter with crossconnected capacitors is proposed in this paper. Figure2 shows the circuit configuration of the proposed converter. The proposed converter consists of three switches S1, S2, and S3, two inductors L1 and L2, four diodes D1, D2, D3, and D4, and three capacitors C1, C2, and Co. The duty ratio of S1 and S3 is d1 and that of S2 is d2. The crossconnected capacitor structure used at the end of the converter circuit will double the output voltage; hence, increase in voltage gain is achieved in the proposed converter circuit. Depending on the switching operations of the switches S1, S2, and S3, there are three modes of operations present in the proposed converter during continuous conduction mode (CCM).Figure 2
Circuit diagram of proposed high-gain DC-DC converter.Mode 1: in this mode, all the three switches S1, S2, and S3 are simultaneously turned on at t0. The equivalent circuit shown in Figure 3(a) for this mode shows the current path clearly. Here, the inductors L1 and L2 are parallelly charged from the input source Vi. The diodes D1, D2, and D3 are reverse biased. Diode D4 is forward biased. The load current is supplied by the capacitors C1 and C2. The voltage across both the inductors L1 and L2 is equal to the input source voltage.Figure 3
Equivalent circuit of the proposed converter: (a) mode 1, (b) mode 2, (c) mode 3, and (d) mode 4.
(a)(b)(c)(d)Mode 2: when the switches S1 and S3 are turned off at t1, this mode of operation is established. Switch S2 still conducts. Figure 3(b) shows the equivalent circuit for this mode. Here, the diodes D1 and D4 are forward biased, and other diodes are reverse biased. Both the inductors will get connected in series and are charged from the input source. The voltage across each inductor is Vi/2. The output voltage Vo is equal to the sum of VC1 and VC2.Mode 3: this mode of operation is established when the switch S2 is turned off at t2. Equivalent circuit for this mode is shown in Figure 3(c). Diode D4 is reverse biased, and the other diodes are forward biased. The inductors will discharge the stored energy to the load with a voltage of 2Vi−Vo/4.From the analytical waveforms in Figure4(a), the expression for voltage gain of the proposed converter in CCM is obtained. By applying the volt-second balance principle for the inductor L1, the voltage gain expression is derived as
(1)MCCM=VoVi=21+d11−d2.Figure 4
Analytical waveforms of the proposed converter. (a) CCM and (b) DCM.
(a)(b)


## 3. Performance Analysis of Proposed Converter

### 3.1. DCM Operation

The proposed converter operates in four modes for the DCM. Mode 1: all the switches S1, S2, and S3 are turned on at t0. The current through the inductors L1 and L2 increases from zero and reaches IL1 at t1. Hence, this operating mode in DCM and CCM is identical. The peak value of inductor current is expressed as
(2)IL1pk=ViLd1Ts.Mode 2: here, switches S1 and S3 are turned off. From the instant t1, the current of the inductors further increases and reaches the peak value IL2 at t2. The magnitude of the inductor current during mode 2 operation is expressed as
(3)IL2pk=Vi2Ld2−d1Ts+IL1pk.Mode 3: when S2 is also turned off at t2, the inductor current starts decreasing and reaches zero at the instant dxTs. The magnitude of the inductor current in mode 3 operation is expressed as
(4)IL2pk=2Vi−Vo4LdxTs.Mode 4: the equivalent circuit of the proposed converter in this mode is shown in Figure3(d). Since the inductor current reached zero state, the load current is supplied by the capacitor Co.From (9) and (10), dx can be calculated as
(5)dx=2Vid1+d22Vi−Vo.The average current of capacitorCo is expressed as
(6)ICo=12dxIL2−Io.From Equations (4), (5), and (6) the expression for ICo can be found as
(7)ICo=Vi2d1+d222Vi−VCTs2L−VCoR.Solving Equation (7), the DCM gain of the proposed converter is derived as
(8)MDCM=1+1+d1+d222τL,where τL=L/RTsis the inductor time constant.


### 3.2. Boundary Condition Operation

The boundary condition for the proposed converter is determined by considering the CCM and DCM voltage gains are equal.Therefore,(9)MDCM=MCCM.By substituting Equations (1) and (8) in (9), the time constant of the inductor current at the boundary for the proposed converter is obtained
(10)τLB=d1+d21−d2281+d1.The variation of the time constant of the inductorτLB with respect to the duty cycle variation is depicted in Figure 5. The margins of CCM and DCM operation for the proposed converter are clearly shown.Figure 5
Boundaries of the proposed high-gain DC-DC converter.


### 3.3. Analysis of Dc-Voltage Gain and Converter Efficiency with Parasitic Elements

In this section, the effect of parasitic elements on the voltage gain and the efficiency of the proposed converter is discussed. Figure6 shows the equivalent circuit of the proposed converter configuration with the presence of parasitic elements. The internal resistances of the inductors L1 and L2 are represented by RL1 and RL2, respectively. The on-state resistances of the switches S1, S2, and S3 are represented by RS1, RS2, and RS3, respectively. The internal resistances and the forward voltages of the diodes D1, D2, D3, and D4 are represented as RD1, RD2, RD3, and RD4 and VF1, VF2, VF3, and VF4, respectively. Series equivalent resistances of the capacitors C1, C2, and Co are shown as RC1, RC2, and RCo, respectively.Figure 6
Equivalent circuit of the proposed converter with parasitic elements.Assuming that the internal resistances of all the diodes are equal to RD, series equivalent resistance of all the capacitors are equal to RC, forward voltages of all the diodes are equal to VF, on-state resistances of all the switches are equal to RS, and the internal resistances of both the inductors are equal to RL the output voltage expression of the proposed converter with parasitic elements is derived as
(11)Vo=21+d1Vi+2VFd1+d2−21−d2−ARL/Ro−BRS/Ro−CRD/Ro,where
(12)A=42d12−d1d2+d1−2d21−d2,B=4d1,andC=4d12+d1d2+d1−d21−d2.The efficiency of the proposed converter in presence of parasitic elements is expressed as given in(13)η=η′−PSPi,where
(14)η′=1+VF/Vid1+d2−2/1+d11−ARL/Ro1/1−d2−BRS/Ro1/1−d2−CRD/Ro1/1−d2.Efficiency of the converter in presence of parasitic elements is plotted and is given in Figure7. The values of various parameters are taken as follows: VF=0.74V; RL=0.01Ω; RS=0.027Ω; RD=0.0177Ω. From the graph, it can be observed that the efficiency of the converter in presence of parasitic elements is varying between 95% and 95.65%.Figure 7
Efficiency vs. output power with parasitic elements.The switching loss is given in(15)PS=ViIStr+tffs.The input power is given in(16)Pi=MIDEALViVoRo.The constantsA, B, C, and D are same as described above in Equation (11).


## 3.1. DCM Operation

The proposed converter operates in four modes for the DCM. Mode 1: all the switches S1, S2, and S3 are turned on at t0. The current through the inductors L1 and L2 increases from zero and reaches IL1 at t1. Hence, this operating mode in DCM and CCM is identical. The peak value of inductor current is expressed as
(2)IL1pk=ViLd1Ts.Mode 2: here, switches S1 and S3 are turned off. From the instant t1, the current of the inductors further increases and reaches the peak value IL2 at t2. The magnitude of the inductor current during mode 2 operation is expressed as
(3)IL2pk=Vi2Ld2−d1Ts+IL1pk.Mode 3: when S2 is also turned off at t2, the inductor current starts decreasing and reaches zero at the instant dxTs. The magnitude of the inductor current in mode 3 operation is expressed as
(4)IL2pk=2Vi−Vo4LdxTs.Mode 4: the equivalent circuit of the proposed converter in this mode is shown in Figure3(d). Since the inductor current reached zero state, the load current is supplied by the capacitor Co.From (9) and (10), dx can be calculated as
(5)dx=2Vid1+d22Vi−Vo.The average current of capacitorCo is expressed as
(6)ICo=12dxIL2−Io.From Equations (4), (5), and (6) the expression for ICo can be found as
(7)ICo=Vi2d1+d222Vi−VCTs2L−VCoR.Solving Equation (7), the DCM gain of the proposed converter is derived as
(8)MDCM=1+1+d1+d222τL,where τL=L/RTsis the inductor time constant.


## 3.2. Boundary Condition Operation

The boundary condition for the proposed converter is determined by considering the CCM and DCM voltage gains are equal.Therefore,(9)MDCM=MCCM.By substituting Equations (1) and (8) in (9), the time constant of the inductor current at the boundary for the proposed converter is obtained
(10)τLB=d1+d21−d2281+d1.The variation of the time constant of the inductorτLB with respect to the duty cycle variation is depicted in Figure 5. The margins of CCM and DCM operation for the proposed converter are clearly shown.Figure 5
Boundaries of the proposed high-gain DC-DC converter.


## 3.3. Analysis of Dc-Voltage Gain and Converter Efficiency with Parasitic Elements

In this section, the effect of parasitic elements on the voltage gain and the efficiency of the proposed converter is discussed. Figure6 shows the equivalent circuit of the proposed converter configuration with the presence of parasitic elements. The internal resistances of the inductors L1 and L2 are represented by RL1 and RL2, respectively. The on-state resistances of the switches S1, S2, and S3 are represented by RS1, RS2, and RS3, respectively. The internal resistances and the forward voltages of the diodes D1, D2, D3, and D4 are represented as RD1, RD2, RD3, and RD4 and VF1, VF2, VF3, and VF4, respectively. Series equivalent resistances of the capacitors C1, C2, and Co are shown as RC1, RC2, and RCo, respectively.Figure 6
Equivalent circuit of the proposed converter with parasitic elements.Assuming that the internal resistances of all the diodes are equal to RD, series equivalent resistance of all the capacitors are equal to RC, forward voltages of all the diodes are equal to VF, on-state resistances of all the switches are equal to RS, and the internal resistances of both the inductors are equal to RL the output voltage expression of the proposed converter with parasitic elements is derived as
(11)Vo=21+d1Vi+2VFd1+d2−21−d2−ARL/Ro−BRS/Ro−CRD/Ro,where
(12)A=42d12−d1d2+d1−2d21−d2,B=4d1,andC=4d12+d1d2+d1−d21−d2.The efficiency of the proposed converter in presence of parasitic elements is expressed as given in(13)η=η′−PSPi,where
(14)η′=1+VF/Vid1+d2−2/1+d11−ARL/Ro1/1−d2−BRS/Ro1/1−d2−CRD/Ro1/1−d2.Efficiency of the converter in presence of parasitic elements is plotted and is given in Figure7. The values of various parameters are taken as follows: VF=0.74V; RL=0.01Ω; RS=0.027Ω; RD=0.0177Ω. From the graph, it can be observed that the efficiency of the converter in presence of parasitic elements is varying between 95% and 95.65%.Figure 7
Efficiency vs. output power with parasitic elements.The switching loss is given in(15)PS=ViIStr+tffs.The input power is given in(16)Pi=MIDEALViVoRo.The constantsA, B, C, and D are same as described above in Equation (11).


## 4. Analysis of Voltage Stress and Current Stress

### 4.1. Voltage Stress Analysis

The voltage stress across the three switches S1, S2, and S3 during off state are given in Equations (17), (18), and (19), respectively.
(17)VSW1=2Vi+Vo4,(18)VSW2=Vo2,(19)VSW3=2Vi−Vo4.The voltage stress across the various diodes during reverse biased condition are given as follows:(20)VD1=−Vi,VD2=VD3=VD4=−Vo2,where VD1, VD2, VD3, and VD4 are the voltages across the diodes D1, D2, D3, and D4, respectively, during the reverse biased condition.


### 4.2. Current Stress Analysis

The maximum current flowing through the various components of the proposed converter is determined by applying Kirchoff’s Current Law (KCL) during various modes of operation. From Figures3(a)–3(c), the current through the inductors L1 and L2 is derived as
(21)IL1=IL2=Io2+d1−d121−d2.In the same way, the current through the switches S1, S2, and S3 are derived as
(22)ISW1=ISW3=Io1+d11−d2,ISW2=2Io1+d11−d2.Similarly, the current through the diodes D1, D2, D3, and D4 are derived as
(23)ID1=2Io1−d121−d2,ID2=ID3=Io1+d11−d2,ID4=Io1+d11−d2.


## 4.1. Voltage Stress Analysis

The voltage stress across the three switches S1, S2, and S3 during off state are given in Equations (17), (18), and (19), respectively.
(17)VSW1=2Vi+Vo4,(18)VSW2=Vo2,(19)VSW3=2Vi−Vo4.The voltage stress across the various diodes during reverse biased condition are given as follows:(20)VD1=−Vi,VD2=VD3=VD4=−Vo2,where VD1, VD2, VD3, and VD4 are the voltages across the diodes D1, D2, D3, and D4, respectively, during the reverse biased condition.


## 4.2. Current Stress Analysis

The maximum current flowing through the various components of the proposed converter is determined by applying Kirchoff’s Current Law (KCL) during various modes of operation. From Figures3(a)–3(c), the current through the inductors L1 and L2 is derived as
(21)IL1=IL2=Io2+d1−d121−d2.In the same way, the current through the switches S1, S2, and S3 are derived as
(22)ISW1=ISW3=Io1+d11−d2,ISW2=2Io1+d11−d2.Similarly, the current through the diodes D1, D2, D3, and D4 are derived as
(23)ID1=2Io1−d121−d2,ID2=ID3=Io1+d11−d2,ID4=Io1+d11−d2.


## 5. Design and Selection of Components

### 5.1. Inductor Design

The minimum value of inductance for both the inductors L1 and L2 are determined using
(24)L1=L2=VidΔiLfS,where ΔiL is the ripple current and is generally taken as 10% of the load current and fS is the switching frequency equal to 50 KHz.


### 5.2. Capacitor Design

The value of capacitors C1, C2, and Co are determined using
(25)C1=C2=Co=PoVoΔVCfS,where ΔVC is the ripple voltage and is usually assumed as 2% of the load voltage and Po is the load power.


## 5.1. Inductor Design

The minimum value of inductance for both the inductors L1 and L2 are determined using
(24)L1=L2=VidΔiLfS,where ΔiL is the ripple current and is generally taken as 10% of the load current and fS is the switching frequency equal to 50 KHz.


## 5.2. Capacitor Design

The value of capacitors C1, C2, and Co are determined using
(25)C1=C2=Co=PoVoΔVCfS,where ΔVC is the ripple voltage and is usually assumed as 2% of the load voltage and Po is the load power.


## 6. Performance Comparison

This section analyses the comparative performance of the proposed converter and the other recent converters reported in the references, i.e., [12, 13, 24–26], and the conventional boost and SEPIC converters. Detailed comparison of the proposed converter and the above converters is presented in Table 1. The plot of duty ratio versus the voltage gain of these converters is shown in Figure 8. A fixed duty ratio of 0.4 is assumed as d1 for the proposed converter. This plot clearly illustrates that the voltage gain attained by the proposed converter is higher compared to the other seven converters. It can be observed that the proposed converter attains a gain of higher value at the lowest duty ratio d2, whereas the other reported converters achieves the similar gain with higher duty ratio.Table 1
Performance comparison of proposed and other existing converter topologies.
TopologyProposed converterConventional boost converterSEPIC converterSC-boost [13]Converter [12]Converter [25]Converter [24]Converter [26]Voltage gain21+d1/1−d21/1−dd/1−d2/1−d2/1−d3d/1−d2d/1−dd/1−d2Switches31112111Diodes41133325Capacitors31233633Inductors21212423Total device count124681014812Voltage stress on switchesVo/2VoVo/dVo/2Vo/2Vo/3dVo/2dVo/d2Continuous input currentYesYesYesYesYesYesNoYesFigure 8
DC-voltage gain vs. duty ratio of the proposed converter and the compared converters.From Table1, it is clearly noted that the switches in the proposed converter are subjected to a minimum voltage stress compared to the other converters reported. In conventional boost converter, the voltage stress across the switch is equal to the output voltage. So higher rating switch is needed. Even though the number of components used in the proposed converter seems to be slightly higher, it is of comparable value with the total component count in the recently reported converters. The increase in component count in the proposed converter is due to the use of crossconnected capacitor structure in the circuit for doubling the output voltage. The proposed converter shows a continuous input current which is most preferable for solar PV applications. Therefore, the proposed converter shows better performance than the reported converters.


## 7. Results and Discussion

Simulation of the proposed converter has been carried out using MATLAB/Simulink platform. Converter parameter values taken for simulation are given in Table2. Input voltage is taken as 48 V and the load resistance is 75 ohms. Various parameters of the proposed converter are measured, and the results are produced in this section. Waveforms of various parameters were observed and presented. Figure 9 shows the pulses applied to the switches. Duty ratio is taken as 40% (d1) for switches S1 and S3 and is 80% (d2) for S2. Figure 10 shows the output voltage and is observed as 670.5 V. Therefore, the gain of the proposed converter is 13.97 and is closely matches with its theoretical value.Table 2
Simulation parameters.
ParameterValueInput voltage48 VResistance of load75 ohmsFrequency50 kHzInductors L1 andL20.5 mHCapacitors C1, C2, Co250μFDuty cycle for S1 and S340%Duty cycle for S280%Figure 9
Switching pulses for S1,S3, and S2.Figure 10
Output voltage of the proposed converter.Figure11 shows the voltage stress appearing across the switches in the proposed converter. Figure 12 shows the voltage across the inductors L1 and L2. Both the inductors are charged to a voltage equal to input voltage of 48 V during mode 1. In mode 2, the voltage across the inductors is equal to half of the input voltage 24 V. During mode 3, when the switch S2 is turned off, the inductor discharges the stored energy, and the voltage across each inductor is observed as -143.5 V. Voltage stress across the switch S2 is measured as 335.4 V which is half of the output voltage (Vo/2). Voltage stress across the switch S1 is measured as 191.7 V. Voltage stress across the switch S3 is measured as -143.6 V. This validates the theoretical performance calculations.Figure 11
Voltage stress across the switches (a) S1, (b) S2, and (c) S3.
(a)(b)(c)Figure 12
Voltage across the inductors (a) L1 and (b) L2.
(a)(b)Comparison of the simulated results and theoretical analysis with respect to various parameters is done and given in Table3. From this, it is observed that both the results closely match which validate the performance of the proposed converter.Table 3
Comparison of theoretical and simulation results.
ParametersTheoretical valueSimulated valueVoltage gain1413.97Output voltage670 V670 VVoltage stress across switch S1191.5 V191.7 VVoltage stress across switch S2335 V335.4 VVoltage stress across switch S3-143.5 V-143.6 V


## 8. Conclusions

In this paper, a high step-up nonisolated DC-DC converter was proposed, analyzed, and validated through the simulation results. The proposed converter used a crossconnected capacitor structure which doubled the output voltage of the converter, and hence, the voltage gain is also doubled. The proposed converter was operated withd1=0.4 and d2=0.8, and the voltage conversion ratio was theoretically calculated as 14. Also, the highest value of voltage across the switch is half of the output voltage, and therefore, the switching losses are reduced. Theoretical analysis was done in CCM, DCM, and BCM using the analytical waveforms. Comparative performance analysis was made with the recently reported converters and presented in the paper. Comparison of the voltage gain is done through the gain plot also. Comparative analysis shows that the proposed converter has a better performance than the other reported converters. The performance of the proposed converter was analyzed in presence of parasitic elements, and the expressions for output voltage and efficiency were derived. Finally, the simulation results and waveforms were presented to validate the proposed converter. Comparison of theoretical and simulation results is executed which validates the working of the proposed converter. Therefore, the proposed converter is best suitable for grid connected as well as for standalone solar PV applications.



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*Source: 7833628-2021-12-16.xml*