# Modeling and Simulation of Special Shaped SOI Materials for  the Nanodevices Implementation

Authors: Cristian Ravariu; Florin Babarada
Journal: Journal of Nanomaterials
 (2011)

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## Abstract

In the industrial chain of the nanomaterials for electronic devices, a main stage is represented by the wafer characterization. This paper is starting from a standard SOI wafer with 200 nm film thickness and is proposing two directions for the SOI materials miniaturization, indexing the static characteristics by simulation. The first SOI nanomaterial is a sub-10 nm Si-film with a rectangular shape. The influence of the buried interface fixed charges has to be approached by the distribution theory. The second proposal studies the influence of the vacuum cavity in a “U” shaped SOI nanofilm. In all cases, with rectangular or “U” shape film, the simulations reveal transfer characteristics with a maximum and output characteristics with a minimum for sub-10 nm thickness of the SOI film.


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## Body

## 1. Introduction

The modeling of the classical devices [1] or novel nanodevices [2] improves the design and explains some phenomena experimentally encountered [3].In the SOI structures, two oxide-semiconductor interfaces exist with specific associated charges. Conventional models ignore the charges situated at the buried oxide-substrate interface, being focused just on the front and back channels conduction in the silicon film. All these fixed charges, expressed in electrons per cm2, are physically spread into a small volume that becomes significant in ultra-thin films. This paper presents a suitable model for the flat-band voltage, based on the δ-distribution strings, which include this bottom interface. Hence, the model accuracy increases in the SOI nanofilms materials, accordingly with our theory and numerical simulations. The electrons confinement effect is continuing to be studied in “U” shape SOI films. Whether the conduction channel occurs at the film bottom, the upper part of the SOI film was removed, monitoring the static characteristics of some SOI-MOSFETs.This paper proposes two directions for the electrical characterization of the nano-SOI (silicon on insulator) materials, by simulation of the electrical characteristics of some devices. The first class of the studied SOI transistors has a rectangular film shape. In this case, the effect of the buried interface fixed charges is modeled with the distribution theory [4, 5].The classical HTA SIMOX (high temperature annealing separation by implanted oxygen), technology offers SOI wafers with 200 nm Si-film on 400 nm BOX with fixed charges in the rangeQox=1010÷1012e/cm2, [6]. This charge is located in a shallow oxide slice. An SOI device has the interfaces: I1-Si-film/BOX, I2-BOX/Substrate, and eventually the upper interface I0-gate oxide/Si-film; see Figure 1. The classical model strongly insists on the electric charges from I0 and I1 interfaces, [7]. In fact, all these fixed charges are physically spread into a small volume. In ultra-thin oxide structures, this kind of charge must be modeled as a bulk charge density [8].Figure 1
The current flow in a cross-section of a rectangular SOI-MOSFET, with SOI film thickness less than 200 nm.This paper emphasizes that the effect of a fixed charges about 1012 e/cm2, at the bottom interface I2 could be neglected in a classical SOI-MOSFET with 200 nm Si/400 nm BOX sizes, while it is the main charge in a nano-SOI-MOSFET with 10 nm × 10 nm × 10 nm Si/10 nm × 10 nm × 10 nm BOX.Transforming 1012e/cm2 in 10−2 e/nm2= 1 electron per 10 nm × 10 nm that means that the back interface I2 (Si/BOX) is charged with one indivisible elementary charge. A model with a discontinuous function escapes from the integration operation. Just the Dirac distribution can correctly describe it as a bulk charge density.Beside to the strong effect of the buried interface charge on the current through a SOI nanotransistor, the current confinement is modulated by the shape of the SOI material, in sub-10 nm Si-film devices, [9]. The influence of the vacuum cavity on the static characteristics, in a “U” shape nanotransistor, was the second direction of study for this paper; see Figure 2.Figure 2
The conceptual architecture of the nanotransistor with a cavity, with SOI film thickness less than 10 nm.The notations from Figures1 and 2 are tn+: the Si-n+ region thickness, tf: the Si-p film thickness, tBOX: the buried oxide (BOX) thickness, tSb: the Si-substrate thickness, ln+:  the Si-n+ region length, lC: the cavity length, and Wn+: the Si-n+ region width.The joint of both subjects will be finally motivated by similar output characteristics with minimum and transfer characteristics with maximum, both for rectangular shape sub-10 nm or “U” shaped SOI films.


## 2. The Analytical Model with Distributions

Firstly, the characterization of the back interface of a nano-SOI-MOSFET, using the pseudo-MOS transistor technique [10], will be presented.  This is a dedicated transistor for the in situ electrical characterization, working like an upside down SOI-MOSFET controlled by the back gate, [11]. All unprocessed SOI wafers contain a pseudo-MOS transistor with two metals in contact with the semiconductor layer, as source and drain. The substrate acts like the gate contact in a classical SOI-MOSFET, Figure 1. One key parameter that contains information about the back interface charge is the flat band voltage, VFB, [12]. This parameter is extracted from the measured ID-VGS curves or directly from simulations with its definition.In order to be focused just on the fixed interface charge density, others effects like interface traps, mobile ionic charge and metal semiconductor work function are neglected in the analytical model and in simulations.The SOI structure associated with the pseudo-MOS transistor is modeled. Identical doping concentrations in film and substrate,NA, are considered to avoid the film-substrate work function in the flat-band voltage expression.The source and drain are grounded, while the gate is biased atVFB voltage, Figure 3(a). By Poisson’s equation integration, the flat-band voltage VFBC is computed by the classical method [13](1)VFBC=-QI1εox⋅tBOX-(QI1+QI2)22εSiqNA,
where tBOX is the buried oxide thickness, εSi, εox, respectively, are the dielectric permittivity of silicon and oxide, VFBC is the classical flat-band voltage given by the condition of the potential zeroing in the entire SOI film. The depleted film thickness tdf→ 0 for VG→VFB, QI1, QI2 are, respectively, the sheet charge densities from the upper and buried interface and the last term, VFB-Sb models the substrate depletion on distance tds in Figures 3(a) and 3(b) presents the interface charges scattered into smalls volumes, as a real situation, both in micro- or nano-SOI structures. Hence, a relationship between surface charge density QI and the bulk electric charge density qV for whatever I1 or I2 interface is (2)QI=lim⁡Δt→0∫0ΔtqV⋅dt=lim⁡Δt→0qV⋅Δt,
where Δt is interpreted as a spreading coefficient. The surface charge QI was spread into an infinitesimal volume: Δt·S, with Δt→0 and qV = ct, S being the area. If qV is modeled with a function like this(3)qV={qS,expressedine/cm3,fort=0,0,fort∈R-{0},
where qS is a real number associated with QI/Δt. Then, QI becomes zero, accordingly with (2), escaping from the integration operation. In order to obtain QI finite in (2), qV must tend to ∞, considering Δt→0. But this is a δ distribution. On the horizontal axis Ot, along the SOI structure from Figure 2(a), the bulk charge density can be written with the Dirac distribution(4)qV(t)=QI1⋅δ0(t)+QI2⋅δtBOX(t).A segment of SOI structure with localization of interface charges (a) withQI1, QI2 as sheet charge density and (b) with QI1, QI2 scattered onto the Δt1,Δt2 thicknesses.
(a)(b)The electric field distribution is expressed as a Heaviside distribution after the first integration. The potential imposes a second integration that is difficult in distribution terms. Due to this reason, is preferred a model based onδ-generator strings. The functional analysis demonstrated that Dirac distribution is the limit of the following string of regulates distribution, pulse-type [14](5)Dti(t)={1Δti,fort∈[ti,ti+Δti],0,fort∉[ti,ti+Δti],
where ti is the spatial coordinate for QIi, i = 1 or 2 and  Δti→0 (∀i) represent the spreading coefficients for QI1, QI2; see Figure 2(b). Now, the bulk electric charge distribution can be written with δ-generators string(6)qV(t)=QI1⋅D0(t)+QI2⋅DtBOX(t).
The string Dti (t) has the advantage of being an integrable function. The integral ∫-∞∞Dti(t)dt gives 1 like δ distribution. The convergence toward δ-distribution is successfully fulfilled for Δti→0. In the old SOI technologies, Δti = 20 nm = 2·10−8 m [15], but in the ultimate stage of nanotechnologies, Δti could reach the atomic sizes— Δti≈ 0.3 nm = 3·10−10 m, closer to zero, [16]. Hence, our model is more accurate for nanodevices. After two integration operations of the Poisson’s equation, the following potential drops result:(7)Fort∈(-tf,0)⟶Φfilm=0,Fort∈(0,Δt1)⟶ΦΔt1=-QI12εox⋅Δt1,Fort∈(Δt1,tBOX-Δt2)⟶ΦBOX=-QI1εox⋅(tBOX-Δt1-Δt2),Fort∈(tBOX-Δt2,tBOX)⟶ΦΔt2=-QI1εox⋅Δt2-QI22εox⋅Δt2.
Adding the previous voltages, Φfilm, ΦBOX, ΦΔt1, ΦΔt2—the potentials drops, respectively, over film, neutral oxide, and Δt1 and Δt2 regions from the buried oxide, with the potential drop over the depleted substrate, VFB-Sb, the complete flat-band voltage expression with distribution terms, VFBC, is(8)VFBD=-QI1εox⋅(tBOX-Δt12)-QI22εox⋅Δt2-(QI1+QI2)22εSi⋅qNA.If the spreading coefficients are approximated with zero (Δt1,2 = 0), the new model (8) becomes the conventional model (1). The validity of the new model (8) will be discussed in the next paragraph, in comparison with classical model (1).


## 3. The Simulation Results for the SOI Structure with 200 nm Thickness

In this paragraph, the previous models (1) and (8) are tested using Atlas simulations of a pseudo-MOS transistor integrated on a SOI wafer with 200 nm Si-p-film and 400 nm buried oxide. The constructive data were [17]: tn+ = 0.2 μm, tBOX = 0.4 μm, tSb = 1 μm, the doping concentrations in film and substrate is NA = 2 × 1015 cm−3.The applied voltages wereVD = 0 V⋯ + 4 V, VS = 0 V and VG = 0 V⋯ − 3 V in order to estimate the simulated flat-band voltage that must be applied on gate.Figure4(a) presents the potential distribution and the holes concentration in an intermediate situation at VG = −1.8 V, through the structure with 200 nm Si-film thickness. A negative gate bias induces a holes crowding in the p-type film. Near drain, where VGD is higher than VGS, the holes reached p=8×1015 cm−3 and near source p=4×1015 cm−3> 2 ×1015 cm−3 = NA, Figure 4(b).  From the longitudinal holes distribution can be observed the holes concentration decreasing in the substrate; see Figure 4(c). This simulation proves the substrate depletion effect.(a) The potential distribution in the 200 nm SOI structure; (b) the holes concentration across the structure; (c) the holes concentration along the structure.
(a)(b)(c)Figure5 presents the electron concentration in the same structure with 200 nm film thickness. A positive gate bias induces an electron inversion channel in p-type film (e.g., n|y=0.2um=1016cm-3> 5·1015 cm−3 = NA-film); see Figure 5.Detail in film for the electron concentration rised for a positive gate voltage.
(a)(b)Atlas takes into account the interface electric charge by the statements(9)Interfaceymin=0.1ymax=0.5,QF=5e10,Interfaceymin=0.5ymax=0.8,QF=1e12.The metal semiconductor work function was zero for the source, drain, and gate contacts, defined as “neutral”. The simulated flat-band voltage value,VFBS was searched accordingly with the theoretical definition. For VS = 0 V, the VG voltage was searched so that the potential in the film bottom becomes zero.Figure6 presents the potential distribution between source and gate, after Atlas running. Initially, the potential distribution was extracted for VGS = 0 V in order to observe the potential bending in the absence of some external electrical voltages due to the interface charges densities QI1 and QI2. In this case, the potential at the film bottom reaches +0.28 V at x = 0.2 μm; see Figure 6. Then, the gate voltage was increased so that the potential at the coordinate x = 0.2 μm decreases to 0 V. This occurs for VGS = −1.95 V in Figure 6 consequently; VFBS = −1.95 V.Figure 6
The potential distribution in the 200 nm structure between source and gate.On the other hand, the classical model (1) provides a fix value VFBC = −1.77 V and the new model (8) based on the distribution generation strings gives VFBD = −1.93 V, fitting the spreading coefficients to Δt1 = 0.5 nm and Δt2 = 7 nm.All these results are briefly shown in Figure7, where the old model (1) gives 9.3% error, while the new model (8) can adjust the error to 1.03%.Figure 7
The flat-band voltages:VFBS = −1.95 V, VFBC = −1.77 V, and VFBD= −1.93 V, besides to the relative errors for VFBC, VFBD in respect with VFBS.A comparison of the simulated parameterVFBS with a measured flat-band voltage, VFBM, is possible, monitoring the transfer characteristics of the pseudo-MOS transistor made on the SOI wafer with 200 nm Si-p-film and 400 nm buried oxide, [17]. In order to extract the flat-band voltage, the source was grounded, while the drain was maintained at +0.3 V, and the gate voltage was varied from −5 V up to +5 V in order to induce the flat-band conditions in the device. From the transfer characteristics, the measured flat-band voltage results: VFBM = −2.16 V for p-type film and +4.25 V for n-type film, [17, 18]. In our case, the closest values to the experimental parameter, VFBM = −2.16 V, are the simulated and distribution model: VFBS = −1.95 V and VFBD = −1.93 V. Obviously, the classical model (1), VFBC = −1.77 V, loses the accuracy, neglecting the buried oxide interface. However, the discrepancy among experiments, simulations, and analytical values is still small at 200 nm film thickness and is predictable to becomes consistent for sub-20 nm films.


## 4. Simulation Results for Sub-10 nm Rectangular SOI Structures with Interface Charges

The investigation of the nano-SOI-MOSFETs is continuing with the downscale of the film thicknesses: for Si-film from 200 nm to 50 nm, 10 nm, and 2 nm and for BOX layer from 400 nm to 50 nm, 10 nm, and 4 nm. The doping concentrations areNA=5×1015 cm−3 both in film and substrate. The interface electric charge densities are QI1=5×1015 e/cm2 and QI2 = 1012 e/cm2.The simulated transfer characteristics show the evolution of theID-VGS curves from: (a) 50 nm, (b) 10 nm, (c) 2 nm thickness of the semiconductor SOI film; see Figure 8. The typical characteristic shape of a standard SOI-MOSFET is fulfilled till 10 nm. From these curves, the simulated flat-band voltage can be extracted, as the voltage that opens the accumulation channel and produces the current increases: VFBS = −0.9 V for 50 nm structure and VFBS = −0.8 V for 10 nm structure. Under this value, an ID-VGS curve with a maximum occurs, probably due to the electrons confinement effect. The simulated flat-band voltage cannot be still extracted from the ID-VGS curve.TheID-VGS characteristics for (a) 50 nm (b) 10 nm and (c) 2 nm thickness of the semiconductor SOI film.
(a)(b)(c)In order to check these assessments, the output characteristics are also investigated, to observe the typical effect of transistor. Figure8 comparatively presents the ID-VDS curves for different semiconductor SOI thickness: 10 nm and 2 nm. The typical shape with saturation occurs till 10 nm film thickness. For sub-10 nm the characteristics takes atypical shape with minimum, Figure 8 for tf = 2 nm.A comparison among the simulated, classical, and distribution flat-band voltage fortf = 50 nm, 10 nm, and 2 nm is available in Figure 9, besides to the error versus the VFBS. This analysis proofs that the model (8) with distributions is closer to the simulations than the classical model (1), which provides higher errors at lower thicknesses.Figure 9
The flat-band voltages:VFBS, VFBC, and VFBD, besides to the relative errors for VFBC, VFBD in respect to VFBS, for tf  = 50, 10, and 2 nm.Figure10 comparatively presents the output characteristics when the drain-source voltage was increased from 0 V up to +5 V, at a constant VGS, for two nanosizes of the SOI film.Figure 10
The ID-VDS characteristics at VGS = 3 V and rectangular shape of the SOI film with 10 nm and 2 nm thickness.Besides to the model with distribution accuracy, the prior simulations of the statics characteristics highlights classical shape of characteristics fortf > 10 nm and atypical shape for tf < 10 nm.Another direction of the SOI nanotransistors investigation is related to a special shape of the SOI film. Taking into account that the current occurs only at the Si-film bottom, results that the 90% from the upper Si-film region does not participate to conduction. Hence, this Si-film region was removed in next simulations, obtaining a SOI nanotransistor with a cavity or “U” shaped.


## 5. Simulation Results for Sub-10 nm Special Shaped SOI Nanotransistor without Interface Charges

In the simulations, the constructive data were those described in the paragraph 4. The aim of this paragraph is to highlight only the special shape effect of the semiconductor on the static characteristics.The main physical effects included as “nanoeffects” were band to band tunnelling, Fowler-Nordheim tunnelling, Fermi distribution, including in the MODEL statement the following parameters: BBT, FNORD, and FERMI. Figure11 presents the total current vectors in a structure with tn+ = 7 nm, tf = 1 nm, and tBOX = 10 nm, at VDS = 4 V, VGS = 3 V, besides to the electrons concentration in the channel region. The vectors through the vacuum (emphasised by dotted line), proved the tunnel effect.Figure 11
Total current vectors in the 1 nm transistor.In Figure12 family of curves ID-VGS for yfilm = 200 nm, 10 nm, 1 nm, and 0.3 nm are presented. These curves have a maximum for yfilm ≤ 1 nm, like SET transistor [19] or atypical nanodevices [20].Figure 12
TheID-VGS transfer characteristics.Figure13 shows the curves ID-VDS at VGS = 3 V. The shape of the ID-VDS curves with a minimum proves the tunnel effect, [21].Figure 13
TheID-VDS output characteristics.Figure14 presents the global potential distribution (left) and a detail of the electron concentration (right) for the 0.3 nm structure with cavity, biased at a high drain voltage in this last case: VS = 0 V, VG = 3 V, and VD = 4 V.The potential and the electron concentration in the 0.3 nm structure.
(a)(b)In this case, the saturation occurred, and an unbalanced electron distribution can be seen in the film 1.1·1016 cm−3 in the source region, 7·1015 cm−3 in the channel near the source, 2·1015 cm−3 in the channel near the drain, and decrease up to 1.4·1015 cm−3 in the drain, region at the film bottom; see Figure 14.


## 6. Possible Set Implementation

The single electron devices (SEDs) tend to become the main rivals for the sub-50 nm classical CMOS devices [22]. Advantages of SED’s are low-power dissipation, ultra-high-density of integration, a natural technology evolution inspired from miniaturized CMOS processes, and hence reasonable costs.The simulations suggest the SET (single electron transistor) like behavior of the SOI nanotransistor with cavity for sub 1 nm film thickness. The electrons must be transferred from source to drain one by one [23].As in the case of SOI-MOSFETs, a positive gate bias induces an electron inversion channel in the p-type film. The DC analysis used the following voltages:VG = 3 V, VD = 0.1 V, VS = 0 V. The nanoeffects were simulated taking into account the Fowler-Nordheim tunneling and the Fermi distribution, using in the MODEL statement the following parameters: FNORD, FERMI: models conmob srh auger fermi fldmob fnord print, meaning: constant mobility, Shockley-Read-Hall and Auger recombination model and mobility attenuation with lateral field. For electron concentration study in the inversion channel, the drain voltage was maintained at 0.1V and the gate voltage was increased from 0 V to +3 V with a 0.05 V step. Despite of the very thin p film, a high electron concentration occurs in the channel at VGS = +3 V, as is shown in Figure 15. With VDS increasing, the current arise as a superposition, when the source-drain vacuum is tunneled.Figure 15
The electron concentrations in 0.3 nm SET: global.However, the device is in strong inversion at this gate voltage, becausenchannel=2 × 1020 cm−3 > 5 × 1015 cm−3 = NA-film. The electron concentration in the 0.3 nm p-type SOI film is: nchannel= 2 × 1020 cm−3 = 0.2 nm−3≈ 1 electron per channel volume, V, Figure 16. The channel volume is V = 0.3 nm × 3 nm × 6 nm = 5.4 nm3. Then, the electrons transport, from source to drain, is one by one. Therefore, the SET principle is satisfied.Figure 16
The electron concentrations in the 1 nm transistor-a detail in a cross-section.


## 7. Conclusions

This paper presented a nanotransistor with silicon on insulator structure in different situations. When the film thickness varied between 200 nm to 10 nm the electrical characteristics preserve the classical shape. When the film thickness varied from 1 nm to 0.3 nm and a cavity occurs above the film, the device presents atypical electrical characteristicsID-VGS, having a maximum like the SET transistor. The shape of the ID-VDS curves with a minimum proves the presence of the tunnel effect. The electron transport in the p-film is one by one, proving the Single Electron Technology for our proposed SOI nanotransistor.Also, the new model with distribution presented in this paper, improves the flat-band voltage modeling of the SOI nanostructures, introducing new fitting parameters:Δt1,2—the spreading coefficients. However, neither the presence or absence of the interface charge QI1,2 is defining for the atypical shape of the transfer characteristics, because the curves with maximum arose both in rectangular SOI film with QI2 both in “U” shape SOI film without QI2; the only conditions was to exist a ultra-thin SOI film under 2 nm.The simulations revealed that the SOI nanotransistor with a thinner film in the channel body represents a solution for the SET’s implementation, with possible applications in industry like digital ULSI, invertors with SET, memories with SEM-single electron memory, and communications cells [24].These simulations and the model with the distribution represent an important chapter in the devices design—a key stage during the industrial manufacturing.



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