# Model-Based Control Design of Series Resonant Converter Based on the Discrete Time Domain Modelling Approach for DC Wind Turbine

Authors: Yu-Hsing Chen; Catalin Gabriel Dincan; Philip Kjær; Claus Leth Bak; Xiongfei Wang; Carlos Enrique Imbaquingo; Eduard Sarrà; Nicola Isernia; Alberto Tonellotto
Journal: Journal of Renewable Energy
 (2018)

---

## Abstract

This paper focuses on the modelling of the series resonant converter proposed as a DC/DC converter for DC wind turbines. The closed-loop control design based on the discrete time domain modelling technique for the converter (named SRC#) operated in continuous-conduction mode (CCM) is investigated. To facilitate dynamic analysis and design of control structure, the design process includes derivation of linearized state-space equations, design of closed-loop control structure, and design of gain scheduling controller. The analytical results of system are verified in z-domain by comparison of circuit simulator response (in PLECS™) to changes in pulse frequency and disturbances in input and output voltages and show a good agreement. Furthermore, the test results also give enough supporting arguments to proposed control design.


---

## Body

## 1. Introduction

MEDIUM-voltage DC (MVDC) collection of wind power is an attractive candidate to reduce overall losses and installation cost, especially within offshore HVDC-connected wind generation as illustrated in Figure1 [1]. To connect DC wind turbine with MVDC network (±50k
V
D
C), the series resonant converter (SRC) serves as a step-up solid-state transformer as shown in Figure 2. With the series resonant converter, the DC turbine converter can take advantages of high efficiency, high voltage transformation ratio, and galvanic fault isolation for different ratings of turbine generator [2–6].Figure 1
Generic configuration of the wind power plant with MVDC power collection.Figure 2
Circuit topology of series resonant converter (SRC#).Traditional closed-loop control of SRC for the DC distribution system is easily implemented by detecting the zero-crossing of the resonant inductor currenti
r and controlling the length of transistor and diode conduction angle α without considering circuit parameters of SRC [7]. Additionally, the output power flow control of SRC for DC network is achieved by controlling the phase-shift angle and frequency between the two arms of H-bridge inverter [6, 8, 9].Based on the discrete time domain modelling approach, the small-signal model of an improved SRC (named SRC#) is proposed [9, 10]. This paper continues with the small-signal plant model addressed in Section 3 and the Appendix and mainly focuses on the closed-loop control design for the system. In the following sections, the mode of operation of SRC# and small-signal plant model based on the discrete time domain modelling approach will be briefly introduced first. The structure of closed-loop control based on the proposed small-signal plant model and the improvement in the disturbance rejection capability will be revealed. To satisfy the power flow control with variable switching frequency, the gain scheduling technique will be given. Finally, the analytical solution of overall system is revealed and verified by comparing with time-domain trace in circuit simulation model implemented in PLECS™ under different operating points. Furthermore, the proposed control deign will be demonstrated by a scaled-down laboratory test bench.


## 2. Mode of Operation of Series Resonant Converter

The mode of operation of series resonant converter (SRC#) in Figure2 is decided by the ratio between natural frequency of tank (L
r and C
r) and the switching frequency of H-bridge inverter: subresonant, resonant, and super resonant mode. In subresonant mode, the switching frequency of H-bridge inverter is lower than the natural frequency of tank. The resonant operating mode is selected when the switching frequency is equal to the natural frequency of tank. If converter’s switching frequency is higher than the natural frequency of tank, the converter is operated in the super resonant mode [9].Contrasting with the constant frequency with phase shift control which is normally applied for operation in super resonant mode, to achieve ZVS at turn-on, Figure3 illustrates the concept of frequency-depended power flow control of SRC#. The converter leg of SRC# consisting of switches T1 and T2 is referred to as the leading leg and the one consisting of switches T3 and T4 is referred to as the lagging leg as indicated in Figure 2. Both converter legs operate at a 50% duty cycle [6, 9].Figure 3
Frequency-depended power flow control of SRC#.To achieve ZCS character at turn-off or minimize the turn-off current, the IGBT-based SRC# is designed to operate at subresonant continuous-conduction mode (subresonant CCM). This control design can drive the implemented phase shift having the same length as the resonant pulse without sacrificing the advantage of linear relation to the number of resonant pulses, as depicted in Figure3. Compared to a traditional SRC with frequency control design in subresonant mode, therefore, the medium frequency transformer in the SRC# addressed in this paper can be designed for a higher frequency and avoids saturation for lower frequencies.


## 3. Discrete Time Domain Modelling Approach for Series Resonant Converter

Considering the efficiency, subresonant mode is selected for the mode of operation of SRC# for the DC wind turbine [5, 6]. Based on the circuit topology shown in Figure 2, Figure 5 illustrates the steady-state voltage and current waveforms of SRC# in subresonant mode, where ω
s is the switching frequency (ω
s=2π·f
s) of SRC#. To apply the linear control theory to the SRC# control design, deriving the plant model of SRC# with the discrete time domain modelling approach includes the derivation of large-signal equations based on the interesting interval shown in Figure 5, linearization of discrete state equations, and derivation of small-signal transfer function. In the derivation, the voltages v
M
V
D
C
(
t
) and v
L
V
D
C
(
t
) are assumed to be discrete in nature, having the constant values V
o
(
k
) and V
g
(
k
) in interval of k
t
h event, and then switch to next states V
o
(
k
+
1
) and V
g
(
k
+
1
) at the start of k
+
1
t
h event. This procedure is only valid when the variation in v
o
(
t
) orv
g
(t) in the event is relatively smaller than its initial and final values [10].With the discrete time domain modelling approach, (1) gives a linearized state-space model of SRC# in subresonant mode and the transfer functions between input state variables and the defined interesting states are shown in (3) and (5). To simplify the derivation, the output filter of SRC# (i.e.,L
f andC
f) is neglected and only the DC component of output current diode rectifieri
out,Rec is selected as an output variableI
o.To obtain the harmonic model of DC turbine converter, Figure4 gives a complete flow chart of mathematical derivation of SRC# plant model, which describes how the SRC# plant model is obtained. First of all, the circuit topology and mode of operation are decided as shown in Figures 2 and 5 and then the equivalent circuit based on the switching sequence of transistors is generated in Figure 6. Based on the circuit topology shown in Figure 2, Figure 5 illustrates the voltage and current waveforms of SRC# n subresonant mode and the equivalent circuit for each event (switching interval) is given in Figure 6. According to Figure 6, the large signal model of converter is created (step 4) and then the interesting state variables (step 5) are defined to generate the small-signal equation and the space model of converter as in steps 6 and 7, respectively ([
A
], [
B
], [
C
], and [
D
]). Eventually, the converter plant model (power stage of converter) is established based on the interesting transfer function (g1, g2, and g3, in step 8). The correction of model (plant model) has been confirmed and the details of derivation are given in the Appendix.(1)
x
~
˙
1
x
~
˙
2
=
A
x
~
1
x
~
2
+
B
α
~
V
~
g
V
~
o
I
~
o
=
C
x
~
1
x
~
2
+
D
α
~
V
~
g
V
~
owhere(2)
x
~
1
=
I
~
r
,
x
~
2
=
v
~
c
rand the derivation of [A], [B], [C], and [D] matrixes is shown in the Appendix. Transfer functions between defined internal state variables and input states are given by(3)
X
~
=
I
~
r
v
~
c
r
=
x
~
1
x
~
2
=
g
x
u
,
11
g
x
u
,
12
g
x
u
,
13
g
x
u
,
21
g
x
u
,
22
g
x
u
,
23
α
~
V
~
g
V
~
owhere(4)
g
x
u
,
11
=
I
~
r
α
~
V
~
g
s
=
0
,
V
~
0
s
=
0
,
g
x
u
,
12
=
I
~
r
V
~
g
α
~
s
=
0
,
V
~
0
s
=
0
,
g
x
u
,
13
=
I
~
r
V
~
o
α
~
s
=
0
,
V
~
g
s
=
0
g
x
u
,
21
=
v
~
c
r
α
~
V
~
g
s
=
0
,
V
~
0
s
=
0
,
g
x
u
,
22
=
v
~
c
r
V
~
g
α
~
s
=
0
,
V
~
0
s
=
0
,
g
x
u
,
23
=
v
~
c
r
V
~
o
α
~
s
=
0
,
V
~
g
s
=
0and transfer functions between converter output current and input state variables are (5)
I
~
o
s
=
g
1
s
g
2
s
g
3
s
α
~
V
~
g
V
~
owhere the transfer functions g
1
(
s
), g
2
(
s
), and g
3
(
s
) can be obtained via (6)
g
1
s
g
2
s
g
3
s
=
C
S
I
-
A
-
1
B
+
D
,
(7)
g
1
s
=
I
~
o
s
α
~
s
V
~
g
s
=
0
,
V
~
0
s
=
0
,
g
2
s
=
I
~
o
s
V
~
g
s
α
~
s
=
0
,
V
~
0
s
=
0
,
g
3
s
=
I
~
o
s
V
~
0
s
α
~
s
=
0
,
V
~
g
s
=
0The transfer function g
1
(
s
) describes how the output current I
~
o is influenced by the control input variable α
~ and the transfer functions g
2
(
s
) and g
3
(
s
) describe how the output current I
~
o is affected if any disturbance occurs in input voltage V
g (∝
V
L
V
D
C) and the output voltage V
o (∝
V
M
V
D
C). For example, the array network (MVDC grid) contains voltage harmonics. The transfer function g
3
(
s
) can be used to evaluate the effect of voltage harmonics on the converter output current. Detailed derivation of the above linearized state-space model and the expression of elements in [A], [B], [C], and [D] matrix in (1) have been revealed in the Appendix.Figure 4
Flow chart of derivation of plant model of SRC#.Figure 5
Resonant inductor current and resonant capacitor voltage waveforms of SRC# in subresonant CCM.Figure 6
Equivalent circuit of SRC for large-signal analysis of conduction intervals in subresonant CCM.
(a)
t
0
(
k
)
≤
t
≤
t
1
k
(
T
1
,
T
4
O
N
)
(b)
t
1
(
k
)
≤
t
≤
t
2
k
(
D
1
,
T
3
O
N
)
(c)
t
0
(
k
+
1
)
≤
t
≤
t
1
(
k
+
1
) (T2, T3 ON)
(d)
t
1
(
k
+
1
)
≤
t
≤
t
2
(
k
+
1
) (D2, T4 ON)


## 4. Model-Based Closed-Loop Control Design

Figure7 gives an overview of small-signal control model of SRC# based on the average plant model in (5) and (6). The control design of SRC# includes derivation of small-signal plant model and the design of the compensator g
c. The small-signal transfer functions of SRC# between converter output current and input state variables are given by (5) and (6), where the output current variation is the expression of linear combination of the three independence inputs. The relationship between α andf
s in subresonant CCM in large-signal model is (8)
α
=
1
2
f
s
-
1
2
f
r
2
π
f
s
=
π
-
π
f
r
f
swhere(9)
f
r
=
1
2
π
L
r
C
rBy substituting the perturbation terms of small-signal analysis into expression in (8), the small-signal expression of α andf
s can be obtained(10)
α
¯
+
α
~
=
π
-
π
f
r
f
s
¯
+
f
~
swhere the AC component is(11)
α
~
=
-
π
f
r
f
~
sEventually, the system transfer function in Figure 5 can be expressed as(12)
I
~
o
s
=
1
/
V
M
V
D
C
g
c
-
π
/
f
r
g
1
1
+
g
c
-
π
/
f
r
g
1
P
~
R
E
F
+
g
2
1
+
g
c
-
π
/
f
r
g
1
V
~
g
+
g
3
1
+
g
c
-
π
/
f
r
g
1
V
~
oEquation (12) can be further expressed as the following:(13)
I
~
o
s
=
1
V
M
V
D
C
T
1
+
T
P
~
R
E
F
+
g
2
1
+
T
V
~
g
+
g
3
1
+
T
V
~
owith aloop gain.(14)
T
s
=
g
c
-
π
f
r
g
1where theloop gain is defined by the product of gains around forward and feedback paths [11].Figure 7
Small-signal control model of the series resonant converter SRC# in subresonant CCM.


## 5. Disturbance Rejection Capability

The closed-loop control design of SRC# is implemented via the compensatorg
c, which is applied to shape the loop gain of the system (i.e., T
(
s
)). Considering the transfer function of output current given in (13), the relationship between I
~
o and V
~
g is shaped by closed-loop control as(15)
I
~
o
s
V
~
g
s
P
~
R
E
F
=
0
,
V
~
0
=
0
=
g
2
1
+
TThe variation in output currentI
o caused by V
~
g can be alleviated by increasing the magnitude of the loop gain T
(
s
) when the closed-loop control design is integrated with the SRC# plant model. The system transfer functions in (13) also show that the variation reduction ofI
o due to variation in MVDC network will benefit from a high loop gain T
(
s
):(16)
I
~
o
s
V
~
0
s
P
~
R
E
F
=
0
,
V
~
g
=
0
=
g
3
1
+
TFurthermore, consider the tracking performance of output current control in (17).(17)
I
~
o
s
P
~
R
E
F
V
~
g
=
0
,
V
~
o
=
0
=
1
V
M
V
D
C
T
1
+
TAssume that a constant power reference P
R
E
F is applied to the control loop with a constant MVDC source and a constant LVDC source. A large loop gain T
s (i.e., T
s
≫
1) can also make sure of a good DC current tracking performance as shown in (18)(18)
I
¯
o
P
¯
R
E
F
≈
1
V
M
V
D
CTherefore, the objective of the compensatorg
c is to govern the system with a desired loop gain (i.e., T
(
s
)
=
T
s
t
a
r
g
e
t), where the deviation of desired loop transfer function T
s
t
a
r
g
e
t can be found by simply evaluating the magnitude asymptote in Figure 8:(19)
T
s
=
g
c
-
π
f
r
g
1
=
T
0
×
1
+
s
/
ω
z
1
+
s
/
Q
ω
p
1
+
s
/
Q
ω
p
1
2
1
+
s
/
ω
p
2Considering the desired loop gain T
s
t
a
r
g
e
t illustrated in Figure 8, the disturbance rejection capability of the output current for a frequency range below the crossover frequency (f
c) can be improved with closed-loop control. For example, at the low frequency range (f
<
f
c), the output current I
o is almost in direct proportion to the power reference signal P
R
E
F. (20)
T
1
+
T
≈
1
for
f
<
f
c
T
≫
1
T
for
f
>
f
c
T
≪
1
⇒
I
~
o
s
P
~
R
E
F
V
~
g
=
0
,
V
~
o
=
0
≈
1
V
M
V
D
CFurthermore, a high loop gain provides a good disturbance reduction to the variation on input voltage V
g and output voltage V
o by the factor 1/T.(21)
1
1
+
T
≈
1
T
for
f
<
f
c
T
≫
1
1
for
f
>
f
c
T
≪
1
⇒
I
~
o
s
V
~
g
s
P
~
R
E
F
=
0
,
V
~
0
=
0
≈
g
2
T
,
I
~
o
s
V
~
0
s
P
~
R
E
F
=
0
,
V
~
g
=
0
≈
g
3
TTypically, thecrossover frequency f
c should be less than approximately 10% of switching frequency of SRC# (f
c < 0.1f
s) to limit the harmonics caused by PWM switching [11]. Based on (19), therefore, compensator g
c
O
P under a certain operating point (OP) can be expressed by(22)
g
c
O
P
=
T
O
P
,
t
a
r
g
e
t
-
π
/
f
r
g
1
O
P
=
f
r
-
π
1
g
1
O
P
T
0
×
1
+
s
/
ω
z
1
+
s
/
Q
ω
p
1
+
s
/
Q
ω
p
1
2
1
+
s
/
ω
p
2
O
P
,
t
a
r
g
e
tFigure 8
Illustration of magnitude asymptote of desired loop gainT
s
t
a
r
g
e
t (target curve of loop gain) [11].Equations (23)–(27) summarize the parameters (i.e.,Q, ω
p
1, ω
p
2, ω
z, ω
c, and θ) which are used to shape the loop gain T
(
s
) via the compensator g
c. The crossover frequencyf
c and the low-frequency pole at f
p
1 are defined as(23)
f
c
=
0.1
f
s
,
(24)
f
p
1
=
1
4.5
f
cThe low-frequency zero at f
z and high-frequency pole at f
p
2 can be chosen according to crossover frequency f
c and required phase margin θ as follows:(25)
f
z
=
f
c
1
-
sin
⁡
θ
1
+
sin
⁡
θ
,
(26)
f
p
2
=
f
c
1
+
s
i
n
θ
1
-
s
i
n
θwhere the angle θ is a phase lead angle of compensator atf
c. The DC gain of target loop gain T
s
t
a
r
g
e
t is(27)
T
o
=
f
c
f
p
1
2
×
f
z
f
p
2TheQ-factor is used to characterize the transient response of closed-loop system. Using a highQ-factor can increase the dynamic response during transient, but it can also cause overshoot and ringing on power devices. In practical application, theQ-factor must be sufficiently low to keep enough phase margins and alleviate voltage and current stress on power devices [11]. Additionally, since the power flow control of SRC# depends on the control of switching frequencyf
s, the parameters of target curve and the coefficient of transfer functiong
c have to be changed according to different operating points (different output powers). To make sure that the compensatorg
c can match with different output power requirements, therefore, a gain scheduling approach is proposed which will be revealed in the next section.


## 6. Design of Digital Gain Scheduling Controller

Gain scheduling controller is designed to access the parameter of compensatorg
c in real time and then adjust it based on the different operating points. Figure 9 gives a complete digital controller of SRC# based on the small-signal control model and the bilinear transformation. The digital controller of SRC# consists of a small-signal controller, a gain scheduling controller, a feedforward control loop, and a DC component calculator (I
o calculator). The controller is implemented in z-domain with a variable interrupt frequency f
i
n
t (f
i
n
t
∝ switching frequency f
s). With the bilinear transform, the general form of the discrete-time representation of the compensator g
c can be expressed as(28)
g
c
z
=
a
5
z
5
+
a
4
z
4
+
a
3
z
3
+
a
2
z
2
+
a
1
z
+
a
0
b
5
z
5
+
b
4
z
4
+
b
3
z
3
+
b
2
z
2
+
b
1
z
+
b
0where coefficients a
n and b
n (n=0~5) are used to specify the coefficients of numerator and denominator.Figure 9
Control block of the series resonant converter SRC# in z-domain.To design the gain scheduling controller, coefficientsa
n andb
n in (28) are evaluated under different operating points (i.e., different output power) with (22)–(27). A trend in the variation of each coefficient (i.e.,P
REF vs.a
n andb
n) is recorded and then is formulated via the polynomial approximation as shown in Figures 12 and 13 which will be discussed in the next section (Section 7). Eventually, the coefficient ofg
c
(z) for SRC# in the subresonant CCM can be adjusted by a continuous function such as a
n
=
f
(
P
R
E
F
) and b
n
=
f
(
P
R
E
F
) in real time to avoid any potential turbulences caused by gain-changing.


## 7. Verification of Closed-Loop Control Design

With the SRC# topology in Figure2 and the controller shown in Figure 9, Tables 1 and 2 give the parameters used in the state-space model and circuit simulation models (tools) for verifying the validation of overall system in z-domain. The control model in the subresonant CCM is verified to identify the accuracy of proposed small-signal model, and then the results of coefficient assessment of g
c
(
z
) with the gain scheduling controller are integrated with control loop and are tested by a ramp-power reference.Table 1
Parameters of SRC# plant model.
Low voltage DC (V
L
V
D
C)
4.04 (k
V
D
C)
Medium voltage DC (V
M
V
D
C)
100.0 (k
V
D
C)
Transformer winding voltage ratio (N1: N2)
1: 25
Rated output powerP
o
u
t
10 (MW)
Resonant inductorL
r
78.1 (mH)
Resonant capacitorC
r
0.25 (uF)Table 2
Specifications of digital controller.
Switching frequencyf
s
1.0k (Hz) (full load)
Interrupt frequency of digital controllerf
i
n
t (i.e. f
i
n
t
=
2
f
s)
2.0k (Hz) (full load)
Q-factor
1.0
Phase marginθ
52°
Power reference signalP
R
E
F
10MW (full load)
Sampling rate of A/D conversion
1M (Hz)
Duty cycle
50%By applying a +0.5% stepping perturbation to all input state variables, Figures10 and 11 give the analytical solutions of small-signal model of SRC# and the results obtained from the time-domain switching model implemented in PLECS™. The SRC# with closed-loop control is commanded to deliver around 9.0MW DC power and 7.5MW DC power to MVDC network, respectively. Figures 10 and 11 show that both the steady state and transient state in the analytical model match with the results generated by switching model. Therefore, dynamics of SRC# switching model can be predictable and controlled with the proposed small-signal model.Figure 10
Dynamics of output currentI
o generated by both the switching model and derived state-space model with the closed-loop controller when +0.5% of step-changing is applied inP
REF,V
g, andV
o, respectively (P
R
E
F: 9.0MW → 9.045MW,V
g: 101.01k
V
D
C → 101.515k
V
D
C,V
o: 100.0k
V
D
C → 100.5k
V
D
C; blue circle: dynamic of state-space model in z-domain, red line: dynamic of electrical signal inPLECS circuit model, the interrupt time of digital controller:T
int=1/(2
x
f
s
o
p) =1/(2x900Hz) sec).Figure 11
Dynamics of output currentI
o generated by both the switching model and derived state-space model with the closed-loop controller when +0.5% of step-changing is applied inP
REF,V
g, andV
o, respectively (P
REF: 7.5MW → 7.5375MW,V
g: 101.01k
V
D
C → 101.515k
V
D
C,V
o: 100.0k
V
D
C → 100.5k
V
D
C; blue circle: dynamic of state-space model in z-domain, red line: dynamic of electrical signal inPLECS circuit model, the interrupt time of digital controller:T
int=1/(2
x
f
s
o
p) =1/(2x750Hz) sec).Figure 12
Design of gain scheduling controller: piecewise continuous functions of numerator ofg
c
(
z
) and its polynomial approximation (3
r
d) in subresonant CCM.Figure 13
Design of gain scheduling controller: piecewise continuous functions of denominator ofg
c
(
z
) and its polynomial approximation (3
r
d) in subresonant CCM.Figures12 and 13 give the result of coefficient assessment of g
c
(
z
) for the design of the gain scheduling controller. Based on (28), the trend in the variation of coefficients a
n and b
n in subresonant CCM from 5.75MW to 10MW (0.5MW/step) is identified and then the variation of each coefficient is approximated with a 3
r
d polynomial (i.e., a
n
P
R
E
F
P
o
l
y
F
i
t and b
n
P
R
E
F
P
o
l
y
F
i
t). According to the variation in output power reference P
R
E
F, the gain scheduling controller accesses the polynomial g
c
(
z
) to regulate its coefficient in real time. To evaluate the adequacy of control design of overall system, finally, the time-trace simulation of output power flow control is given in Figure 14 with a ramp-power reference P
R
E
F from 0.1MW to 10MW, and vice versa. The results show that the output current/power (I
o) of the series resonant converter can be well controlled when magnitude output powers references are changed.Figure 14
Output current (I
o) of the series resonant converter with a ramp-power reference P
R
E
F to verify the design of gain scheduling controller and demonstrate the start-up process of DC wind converter.
(a)
Ramp-up power:P
R
E
F=P
o
u
t=0.1MW → 10MW, slop=4.95MW/sec
(b)
Ramp-down power:P
R
E
F=P
o
u
t=10MW → 0.1MW, slop=-4.95MW/sec


## 8. Laboratory Test Results

To verify the control design, first the circuit simulation is carried out with circuit simulation tool of PLECS™, and then the controller is implemented in a scaled-down laboratory test bench. The circuit configuration of test bench and the corresponding parameters are shown in Figure15 and Table 3, respectively, where the MVDC network is simulated by a unidirectional power flow DC power source with a controllable perturbation.Table 3
Specifications of laboratory test bench.
Low voltage DC source (V
L
V
D
C)
216 (V
D
C)
DC component of medium voltage source (V
M
V
D
C
,
0)
400 (V
D
C)
Transformer winding voltage ratio (N
1: N
2)
1: 2
Rated output powerP
o
u
t
550 (W)
Resonant inductorL
r
20.0 (mH)
Resonant capacitorC
r
1.0 (uF)
Switching frequencyf
s
800 (Hz)
Output filter inductorL
f
2.5 (mH)
Output filter capacitorC
f
1.0 (mF)
Resistive loadR
l
o
a
d
125 (Ω)
Interrupt frequencyf
i
n
t (i.e. f
i
n
t
=
2
f
s)
1.6k (Hz)
Sampling rate of A/D conversion
1M (Hz)
Duty cycle
50%Figure 15
Configuration of laboratory test bench (V
M
V
D
C
,
0: DC component of medium voltage power source, V
M
V
D
C
,
h: perturbation source).Figures16(a) and 16(b) depict the system response when a positive and a negative step perturbation (0.01p.u) in MVDC network are applied, respectively. The control design exhibits a close behavior in either simulation or experimental test. There is some small tracking error during the transient between the simulation and test results. This usually is caused by the estimated error of components and stray inductance which is not considered in simulation model. Figure 16(c) represents how the output current behaves when a step-change (0.26p.u) is applied in the power reference signal P
R
E
F. Under the proposed control law for SRC#, both the simulation and test result show that the DC component of DC turbine output current (i
¯
t
u
r
b) tracking performance can be guaranteed. However, a small oscillation (≈40Hz) during the transient of step-change of power reference signal in the experimental test is observed due to the series diode D
A
u
x (in Figure 15) which is reverse-biased at this test occasion.Figure 16
Dynamic response of output current of DC wind turbine converter (i
t
u
r
b) when a step-up/-down disturbance is injected in system att=1.0 [
s
].
(a)
4.0V
D
C step-up disturbance (0.01p.u) in the MVDC voltage (V
M
V
D
C)
(b)
4.0V
D
C step-down disturbance (0.01p.u) in the MVDC voltage (V
M
V
D
C)
(c)
Step-up disturbance (0.26p.u) in the power reference signalP
R
E
F (equivalent of current reference signal: 1.37A→1.73A)


## 9. Conclusion

A model-based control design of SRC# for DC wind power plant based on small-signal plant model in the discrete time-domain modelling is revealed. This paper continues with the modelling of SRC# given in the Appendix and mainly addresses the closed-loop control design for the system. The control design process contains the derivation of state-space plant model, design of closed-loop control structure, and design of gain scheduling controller. Compared with the traditional frequency-depended power flow control which relied on open-loop structure, the SRC# with the closed-loop structure can gain a better disturbance rejection capability for the output power control. The verification of proposed digital controller including plant model is addressed in both the analytical model and the time-domain circuit simulation implemented in PLECS™ in Section7 by evaluating the SRC# with the stepping-perturbation under the subresonant CCM. Furthermore, gain scheduling approach is implemented by the polynomial approximation and tested under different operating points (different output powers). Integrating the gain scheduling controller with closed-loop structure enables the system to automatically adjust parameters of controller in real time to satisfy different output power requirements without sacrificing the control performance. Finally, Section 8 shows that all the test results give enough supporting arguments to the proposed control design.



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*Source: 7898679-2018-12-02.xml*