# CMOS Realization of All-Positive Pinched Hysteresis Loops

Authors: B. J. Maundy; A. S. Elwakil; C. Psychalinos
Journal: Complexity
 (2017)

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## Abstract

Two novel nonlinear circuits that exhibit an all-positive pinched hysteresis loop are proposed. These circuits employ two NMOS transistors, one of which operates in its triode region, in addition to two first-order filter sections. We show the equivalency to a charge-controlled resistance (memristance) in a decremental state via detailed analysis. Simulation and experimental results verify the proposed theory.


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## Body

## 1. Introduction

Pinched hysteresis was proposed to be a signature of memristive devices [1, 2], yet it can also be observed in several other nonlinear devices such as nonlinear inductors (capacitors) with quadratic-type current (voltage) dependence [3]. Finding a general model for pinched hysteresis behavior was attempted in [4] for specific devices labeled as memristors [5]. In [6] and from a simplified mathematical point of view, the following model was proposed and shown to exhibit a pinched hysteresis behavior which can fit both charge-controlled and flux-controlled memristance definitions:(1)yt=xt×a+1T∫0txτdτ,where if y(t)=v(t) and x(t)=i(t), the charge-controlled memristance is obtained, while for the alternative setting y(t)=i(t) and x(t)=v(t), the flux-controlled memristance is obtained. In (1), the constants a and T are scaling and integration time constants, respectively. Note that circuit realization of this model for the purpose of emulating its pinched hysteresis behavior in non-solid-state devices requires a multiplier block, an integrator block, and an adder [6]. Several other emulator circuits have recently been proposed in the literature [7–13]. It is important to note that (1) is nonlinear due to the multiplication term and that pinched hysteresis cannot appear in a linear system. It is also possible to include other forms of nonlinearity that apply to the shaping of the loop as a result of shaping the applied excitation. This means replacing x(t) in (1) more generally with fx(t).Pinched hysteresis loop is generally observed as a result of applying a bipolar sinusoidal voltage or current excitation signal and is thus symmetrical around the origin. Nonsymmetrical loops can also be obtained when the pinch point is shifted away from the origin. However, an all-positive pinched loop, to the best of our knowledge, has not been demonstrated before. It is the purpose of this work to introduce two simple circuits where this behavior is observed. We rely on the inherent nonlinearity of a MOS transistor to perform the multiplication operation required by (1) in order to obtain a charge-controlled memristance. Recall that a MOS transistor current-voltage relation can be described by(2)ids=kvgs-VTvds-vds22,where ids is the drain-to-source current, vgs and vds are, respectively, the gate-to-source and drain-to-source voltage, VT is the threshold voltage, and k is a constant in A/V2 units. It is obvious from (2) that a multiplication operation is inherent through the term vgs-VTvds. However, for an NMOS transistor, the current is unidirectional and the condition vgs>VT is necessary for the transistor to switch on. Therefore, if (2) is successfully reconfigured to implement (1), an all-positive pinched hysteresis loop can be obtained. In the first part of this work, we do not attempt to remove the extra nonlinear term vds2/2 and therefore it remains affecting the pinched loop. However, this effect is minimized via proper selection of the design parameters. In a later section of the work, we employ a linearization circuit to remove this quadratic term and hence ensure that only the multiplication nonlinearity term remains. As a result and comparing (2) to (1) assuming vds2/2 is minimized or eliminated, it is clear that the mapping ids→y(t), vds→x(t), and K(vgs-VT)→a+1/T∫0t‍x(τ)dτ is necessary. To achieve this, we adopt a frequency-domain approach which also allows independent adjustment of the fixed part and the charge-controlled part of the memristance. We stress and clarify the role played by the capacitors in the proposed circuits, which is crucial to the understanding of pinched hysteresis behavior in general, as clearly seen in [17, 18] for solid-state devices as well. Note that, in reconfiguring (2) to realize (1) via this mapping, we are essentially modifying the MOS transistor transconductance such that it is state-controlled, with the state variable being the terminal voltage of the transconductance vds. The time constant T necessary in (1) can only be obtained with an embedded capacitance (physical or parasitic) [17, 18]. Finally, it must be stated that this paper is concerned with the “pinched hysteresis behavior” as a behavior rather than with proposing yet another memristor emulator. The design concept of the circuits under study here is completely new and relies on a frequency-domain approach rather than a time-domain approach. It also shows for the first time that pinched hysteresis can even be unipolar, something not possible with memristors as they are so defined.This manuscript is organized as follows. Section2 looks at the proposed circuits and presents the theory behind their operation that leads to pinched hysteresis behavior. Section 3 computes the memristance of the proposed circuits, with numerical simulations, and presents pinch-off analysis of the proposed circuits. In Section 4, a method to linearize the main transistor in triode is presented which removes the extra nonlinear term vds2/2 in (2). In Section 5, simulation and experimental results are presented, and finally our conclusions are given in Section 6.


## 2. The Proposed Circuits

Consider the circuits shown in Figure1 both consisting of opamp A1 connected as a buffer and opamp A2 along with the NMOS transistor M2 as a simple voltage to current converter which converts the voltage of the noninverting terminal of A2 into a current iin through NMOS transistor M1. It is essential for M1 to remain in triode, hence acting as a transconductance. Both circuits contain a lossy integrator comprising R1,C1, and a DC bias voltage Vdc1 required to maintain M1 in triode (Vdc1>VT, VDS1<Vdc1-VT). The difference between the two circuits can be seen in their high-pass filter sections. In the case of Figure 1(a), it consists of R2,C2 with an additional DC source Vdc2 providing a DC voltage to the drain of M1. For Figure 1(b), the high-pass filter is made up of r1,2,C2 and here the drain-to-source DC biasing of M1 comes from Vdc1 through r1,2 as αVdc1, where α=r1/r1+r2. Note that maintaining transistor M1 in triode in both circuits requires that Vdc1-Vdc2>VT and (1-α)Vdc1>VT for Figures 1(a) and 1(b), respectively.Figure 1
The proposed nonlinear circuits with unipolar pinched hysteresis loop.
(a)
(b)The lossy integrator of each circuit has a response given in the frequency domain which can be written as(3)H1ω=H1ω∠-θ1=11+ω2τ12∠tan-1ωτ1,where τ1=R1C1. Meanwhile, the high-pass filter in Figure 1(a) has a response(4)H2aω=H2aω∠θ2a=ωτ21+ω2τ22∠90∘-tan-1ωτ2,with τ2=R2C2, and likewise the response of the high-pass filter in Figure 1(b) is(5)H2bω=H2bω∠θ2b=α1+ω2τz21+ω2τp2∠tan-1ωτz-tan-1ωτp,where τz=r2C2 and τp=r1//r2C2. Clearly, both high-pass filters provide a leading phase shift by different amounts while DC biasing voltages are allowed to be passed on to the transistor M1 to set VDS1. For an input voltage of amplitude A and frequency ωo in the form vin(t)=Asinωot+Vdc1, it follows that the time dependent VGS voltage of M1 is(6)VGS1t=AH1ωosinωot-θ1+Vdc1,while the time dependent VDS voltages in Figures 1(a) and 1(b) are, respectively,(7)VDS1t=AH2aωosinωot+θ2a+Vdc2,VDS1t=AH2bωosinωot+θ2b+αVdc1,where, for (7), A<Vdc2 and A<αVdc1, respectively. Substituting (6)-(7) into (2) yields after considerable simplification(8)iinat=-A^cos2ωot-θ1+θ2a+B^sinωot-θ1+C^sinωot+θ2a+D^cos2ωot+2θ2a+E^+I^off,for Figure 1(a), and(9)iinbt=-A^cos2ωot-θ1+θ2b+B^sinωot-θ1+C^sinωot+θ2b+D^cos2ωot+2θ2b+E^+I^off,for Figure 1(b). The coefficients of the sin· and cos· terms in (8) and (9) are given in Table 1. Note that, with the exception of I^off, all coefficients in Table 1 are frequency dependent. This implies that it is necessary to choose proper values for time constants in order to observe the hysteresis behavior.Table 1
Summary of the coefficients in (8) and (9) for Figures 1(a) and 1(b).
Coefficient
Figure1(a)
Figure1(b)
A^
1
2
k
A
2
H
1
ω
o
H
2
a
ω
o
12kA2H1ωoH2bωo
B^
k
A
H
1
ω
o
V
d
c
2
αkAH1ωoVdc1
C^
k
A
H
2
a
ω
o
V
d
c
1
-
V
d
c
2
-
V
T
kAH2bωo1-αVdc1-VT
D^
1
4
k
A
2
H
2
a
ω
o
2
14kA2H2bωo2
E^
A
^
c
o
s
θ
1
+
θ
2
a
-
D
^
A^cosθ1+θ2b-D^
I^off
k
V
d
c
1
-
V
T
V
d
c
2
-
1
2
V
d
c
2
2
αk1-α2Vdc1-VTVdc1Close inspection of (8) under the assumption that θ2a≅π/2-θ1 shows that it can be rewritten in the dimensionless form(10)yt+yoff=xtH1ω1-ωH2aω∫0txτdτ+H2aωωx˙t-H2aωo22ω2x˙t2+xoff,where x(t)=sinωt-θ1 represents an already phase shifted input signal. The term in the square brackets is clearly similar to (1) while additional x˙(t) and x˙2(t) terms outside the brackets are unwanted and will result in a nonsymmetrical loop. Note that the offset terms yoff and xoff present are a result of the input being DC level shifted. However, using (10) and assuming that ω is sufficiently large such that the second and third terms are negligible and in addition translating the origin to (x0,y0)=(xoff,yoff), we obtain(11)yt=xt×H1ω-ωH2aωH1ω∫0txτdτ,which compared to (1) has the slightly modified form y(t)=x(t)×a+ab/T∫0t‍x(τ)dτ, where a=|H1(ω)| and b=-|H2a(ω)|.Finally, in comparison with other circuits which also exhibit pinched hysteresis behavior and some of which are labeled as analog memristor emulators as shown in Table2, about half of them use discrete multiplier blocks which are inefficient. By far, the vast majority use second-generation current conveyors with the only commercial one being the AD844, and several use additional hardware in the form of buffers, multiplexers, diodes, and switches. If the total component count is used as a figure of merit, then the proposed circuits of Figure 1 have the lowest count with their main drawback being operation in one quadrant. Note that even though our proposed circuits are listed among those identified as “memristors” or “memristor emulators,” we refrain from labeling our proposed circuits as “memristor emulators” and simply label them as among circuits having pinched hysteresis behavior.Table 2
Summary of several analog circuits with pinched hysteresis and actual analog memristor emulators to date and their designs. MB: multiplier block; OPA: operational amplifier; CCII: second-generation current conveyors; AH: additional hardware, which may be in the form of buffers, multiplexers, diodes, inverters, switches, and so forth; I/D: incremental/decremental memristance emulation. The number (#) of transistors refers to the discrete number of external transistors.∗An OTA was used here in place of an OPA.
Reference [ ]
MB
OPAs
CCIIs
# of trans.
AH
Quadrant
I/D
[6]
1
—
3
—
Yes
2
Both
[7]
—
1
∗
2
—
No
2
I
[8]
1
—
2
—
No
2
I
[9]
—
2
1
2
No
2
D
[10]
1
5
—
10
Yes
2
Both
[11]
—
2
1
1
No
2
I
[12]
—
—
3
1
No
2
I
[13]
1
2
—
—
Yes
2
D
[14]
1
—
2
—
Yes
2
I
[15]
—
1
∗
1
2
No
2
Both
[16]
—
—
4
—
Yes
2
NA
This work
—
2
—
2
No
1
D


## 3. Charge-Controlled Resistance (Memristance) Calculation

Using (11) and setting x(t)=i(t)/Iref,y(t)=v(t)/IrefRs, where Iref is an arbitrary reference current and Rs is an arbitrary scaling resistor, the memristance value for Figure 1(a) can be obtained as(12)Rma=RsH1ω1-ωH2aωIrefqt,where q(t) is the electrical charge. Note that since the input signal has a fixed ω=1/T, we can rewrite this memristance as(13)Rma=RsH11T1-1TH2a1/TIrefqt,which has a fixed resistive part equal to RsH11/T and a charge-controlled part equal to RsH11/TH2a1/T. It is thus clear that while the transfer function H1 controls the magnitude of both parts, H2a can change the magnitude of the charge-controlled part alone. Note that this memristance is decremental [6]. Furthermore, note that, for sufficiently high frequency such that ω≫1/τ1, |H1(ω)|≈1/ωτ1 and it follows that the fixed part of the realized memristance is approximately RsT/τ1. However, for sufficiently high frequency such that ω≫1/τ2, we also note that |H2a(ω)|≈1 and therefore the realized memristance can be approximated as(14)Rma≈RsTτ11-RsT×1Vqt.We can further express the electrical charge as q(t)=C1vC1(t) since the only capacitor in the circuit in this case capable of holding a charge is C1 following the fact that |H2a(ω)|≈1. Accordingly,(15)Rma≈RsTR1C11-RsTC1vC1ntRma=Rs2R1TRsC1-vC1nt,where vC1n(t) is the normalized (by 1V) voltage across C1. In a final step, we may freely express the period T of the applied signal as a ratio of RsC1 (i.e., T=mRsC1) leading to the simplified expression(16)Rma≈Rs2R1m-vC1nt=Rsm-vC1nt,if we select the arbitrary reference resistance as Rs=R1. Note that, for the condition ω≫1/τ1 to be satisfied, it follows that m≪1.The expression in (16) is significantly important for two aspects:(i)
It shows that although the circuit has an all-positive input resistance, theoretically and according to (16), the memristance is not always positive. However, it remains positive because the origin has been already shifted to (x0,y0)=(xoff,yoff). With reference back to the origin (x0,y0)=(0,0), (16) then becomes(17)Rma≈Rsm-vC1nt+Roffa,where Roffa=Vdc1/Vdc2/k2-Vdc2/Vdc1Vdc1-VT. Figures 2(a) and 2(b) show the variation of the memristance versus the capacitor voltage vC1 and versus frequency ω, respectively. In Figure 2(a), for the values chosen: m=vC1/100, Vdc1=1 V,Vdc2=0.4 V,VT=0.35 V, and k=0.15 mA/V2, we obtain Roffa=12.67 kΩ. Correspondingly, selecting a suitable reference current such as Iref=0.15 mA leads to a nominal value for Rs of 6.7 kΩ (i.e., IrefRs≈1 V). For Figure 2(b), we fixed vC1=1 V and C1=10 μF and show the decremental nature of the memristance whereas the frequency increases when Rma asymptotically approaches Rs.(ii)
It highlights the significance and necessity of the existence of a capacitor in order to hold the charge. In this circuit, this capacitor isC1; however, in solid-state devices, this capacitor may well be a parasitic capacitor or equivalent of parasitic capacitances as observed in [17, 18]. It thus appears to the authors that it is not possible to isolate the appearance of pinched hysteresis loops from the existence of a capacitive effect.In a similar manner, the memristance of the circuit in Figure 1(b) can be obtained as(18)Rmb=RsH11Tα-1TH2b1/TIrefqt,which unlike (13) has a fixed resistive part equal to αRsH11/T but an identical charge-controlled part. Noting that H2b1/T=α for 1/T≫1/τ1 and making the same assumptions as before, a generalized expression for Rmb can be given as(19)Rmb≈αRs2R1m-vC1nt+RoffbRmb=αRsm-vC1nt+Roffb,where Roffb=1/αk2-αVdc1-VT.Figure 2
(a) Plot of memristanceRma versus capacitor voltage vC1n=vC1/1V when m=vC1n/100, Rs=6.7 kΩ, Roffa=12.67 kΩ, and ω≫1/τ1. (b) Plot of Rma versus frequency when C1=10 μF.
(a)
(b)


### 3.1. Numerical Simulations

Sample Matlab plots of (8) and (9) are shown in Figures 3(a)–3(c) to normalized values of k=1 mA/V2,A=0.4 V,Vdc1=1 V, and VT=0.35 V. In the first of the plots shown in Figure 3(a), τ2=τ1=τz, τp=ατz with α=0.4 and the applied sinusoidal voltage frequency ωo>1/τ1 and Vdc2=0.4 V. Note that having α=0.4 is equivalent to setting Vdc2=αVdc1 and that θ2b≈θ2a=π/2-θ1. In this figure, we see that neither loop is symmetrical which is attributed to the x˙(t) and x˙2(t) terms (see (10)) and the phase shift term introduced by the lossy integrator. In the second plot, shown in Figure 3(b), τ2=10τ1=τz, τp=ατz with α=0.4 and Vdc2=0.4 V as before but θ2a≈θ2b≅0. The pinched loops from the two circuits are nearly identical and the upper lobe is far bigger than the lower one. In Figure 3(c), τ2=τ1=τz, τp=ατz with α=0.286, Vdc2=0.3 V, and θ2b≈θ2a=π/2-θ1. Clearly, as α or Vdc2 decreases, the upper lobe decreases in size and the pinch point increases. Note the reduced value of A for the circuit (Figure 1(a) or (8)). This implies that the circuit of Figure 1(a) must work with reduced input amplitudes compared to the circuit of Figure 1(b), unless Vdc1 and Vdc2 are adjusted in tandem. This is not the case for the circuit of Figure 1(b) where DC bias voltages are related by α which is fixed for ωo>1/τ1.Figure 3
Matlab simulation of theI-V characteristics of Figures 1(a) and 1(b) as given by (8) and (9), respectively. (a) τ2=τ1=τz, τp=ατz with α=0.4. (b) τ2=10τ1=τz, τp=ατz with α=0.4. (c) τ2=τ1=τz, τp=ατz with α=0.286 and Vdc2=0.3 V. (d) τ2=τ1=0.1τz, τp=ατz with α=0.33, Vdc2=0.3 V, and A=0.5 V and A=0.3 V for Figures 1(a) and 1(b), respectively.
(a)
(b)
(c)
(d)Finally, in Figure3(d), ω<1/τ1 with τ2=τ1=0.1τz, τp=ατz, α=0.33, and Vdc2=0.3 V. Under these conditions, θ2b≪θ2a=π/2-θ1, and decreased amplitudes must now be used in the circuit of Figure 1(b) or (9) compared to the circuit of Figure 1(a) or (8). Therefore, we select A=0.5 V and A=0.3 V for the two circuits, respectively, in this case.


### 3.2. Pinch Point Analysis

The unique form of (8) and (9) allows for a closed-loop solution of the pinch-off point in these circuits. It can be shown after considerable simplification that (8) and (9) have a pinch-off point V^inp,I^inp given by(20)V^inp=Vdc1-AX^Θ,I^inp=-A^cos2sin-1XΘ+θ2a,2b-θ1-B^sinsin-1XΘ-θ1-C^sinsin-1XΘ+θ2a,2b+D^cos2sin-1XΘ+2θ2a,2b+E^+I^off,where(21)X^Θ=B^/2sin-θ1+C^/2sinθ2a,2bA^sinθ2a,2b-θ1-D^sin2θ2a,2b,and the subscripts a,b refer to (8) and (9), respectively. The frequency dependent nature of (20) makes their analysis difficult; however, several observations can be deduced. First, X^Θ can be positive or negative depending on the values of θ1,θ2a, and θ2b as observed in Figure 3. In addition, C2 plays an important role even though it is not the main charge holding or integrating capacitor. In Figure 1(a), its minor role is to block Vdc1 as Vdc2 is passed, but in both circuits, its main contribution is to add a leading phase shift opposed to the lagging phase shift caused by C1. For example, in the circuit of Figure 1(b), in the absence of C2, that is, if C2=0, then sinθ2b=sin2θ2b=0, because θ2b=0, and with H2bω=α, (21) reduces to X^Θ=Vdc1/A, setting V^inp=0. That is, no pinch point will occur.Secondly, under the assumptionτ2=τ1, we find that V^inp=Vdc1 when tanθ1=C^/B^ or when Vdc2=Vdc1-VT/2. Under this condition, M1 remains in triode so long as Vdc1>3VT which is easily satisfied. For the general case when τ2=βτ1, implying that θ2a≠π/2-θ1 (unless β=1), the general solution to X^Θ=0 yields(22)Vdc2=ββ+1τ12ω2+1βτ12ω2+1Vdc1-VT.Likewise, the value for α in the circuit of Figure 1(b) that results in V^inp=Vdc1 can be expressed as(23)α=1-VTVdc1-ωτ1cscθ2bω2τ12+11+ω2τp21+ω2τz2.In both general cases, (22) and (23) are frequency dependent, the exception being when β=1 for (22), but both can be minimized for frequency dependance by ensuring that ωτ1>1, ωτz>1, and ωτp>1. Sample plots of theI-V characteristic for the circuit of Figure 1(a) governed by (8) to the conditions A=0.3 V, τ2=τ1=500 μs, Vdc1=1 V, VT=0.35 V, k=1 mA/V2, and Vdc2=Vdc1-VT/2=0.325 V are shown in Figure 4(a).Figure 4
(a) Matlab simulation of theI-V characteristic of Figure 1(a) governed by (8) to A=0.3 V, τ2=τ1=500 μs,Vdc1=1 V, VT=0.35 V, k=1 mA/V2, and Vdc2=0.325 V. (b) Input voltage vin(t) and current iina(t) plotted as a function of time at a frequency of ω=2π×800 rad/s.
(a)
(b)Note that becauseβ=1 and Vdc2=Vdc1-VT/2, V^inp=Vdc1 is independent of the input frequency which is verified at the three frequencies fo=[500,800,1500] Hz, as theoretically predicted. In Figure 4(b), vin(t) and iina(t) are plotted as a function of time.Finally, no pinch point occurs whenX^Θ=Vdc1/A or X^Θ=-Vdc1/A and if β=1 this happens at the two frequencies ω1,2: (24)ω1=1τ12Vdc2+VT3Vdc1-2Vdc2-VT,ω2=1τ12Vdc1-2Vdc2-VTVdc1+2Vdc2+VT.Furthermore, if Vdc2=1/2Vdc1-VT, a unique frequency at which no pinch point exists is(25)ω1=ω2=12τ1.In the case of Figure1(b), no easy closed-loop form of the solution exists, but when τz=τ1 the frequencies at which the pinch point occurs can be obtained by numerically solving, for ω, the equation(26)γ1ω4+δ1ω2+2α-1Vdc1+VT=0,whenX^Θ=Vdc1/A or(27)γ2ω4+δ2ω2+2αVdc1+VTτ1-τp+2Vdc1τp=0,whenX^Θ=-Vdc1/A, where (28)γ1=τp3τ1Vdc1+α-1Vdc1+VTτp2τ12+ατpτ13Vdc1,δ1=α-2τp2+α+1τpτ1+2α-1τ12Vdc1+τ12+τp2VT,γ2=τp4τ1Vdc1+2-αVdc1-VTτp3τ12+VT-Vdc1τp2τ13+ατpτ14Vdc1,δ2=2-αVdc1-VTτp3+Vdc1+VTτp2τ1+2-αVdc1-VTτpτ12+2α-1Vdc1+VTτ13.


## 3.1. Numerical Simulations

Sample Matlab plots of (8) and (9) are shown in Figures 3(a)–3(c) to normalized values of k=1 mA/V2,A=0.4 V,Vdc1=1 V, and VT=0.35 V. In the first of the plots shown in Figure 3(a), τ2=τ1=τz, τp=ατz with α=0.4 and the applied sinusoidal voltage frequency ωo>1/τ1 and Vdc2=0.4 V. Note that having α=0.4 is equivalent to setting Vdc2=αVdc1 and that θ2b≈θ2a=π/2-θ1. In this figure, we see that neither loop is symmetrical which is attributed to the x˙(t) and x˙2(t) terms (see (10)) and the phase shift term introduced by the lossy integrator. In the second plot, shown in Figure 3(b), τ2=10τ1=τz, τp=ατz with α=0.4 and Vdc2=0.4 V as before but θ2a≈θ2b≅0. The pinched loops from the two circuits are nearly identical and the upper lobe is far bigger than the lower one. In Figure 3(c), τ2=τ1=τz, τp=ατz with α=0.286, Vdc2=0.3 V, and θ2b≈θ2a=π/2-θ1. Clearly, as α or Vdc2 decreases, the upper lobe decreases in size and the pinch point increases. Note the reduced value of A for the circuit (Figure 1(a) or (8)). This implies that the circuit of Figure 1(a) must work with reduced input amplitudes compared to the circuit of Figure 1(b), unless Vdc1 and Vdc2 are adjusted in tandem. This is not the case for the circuit of Figure 1(b) where DC bias voltages are related by α which is fixed for ωo>1/τ1.Figure 3
Matlab simulation of theI-V characteristics of Figures 1(a) and 1(b) as given by (8) and (9), respectively. (a) τ2=τ1=τz, τp=ατz with α=0.4. (b) τ2=10τ1=τz, τp=ατz with α=0.4. (c) τ2=τ1=τz, τp=ατz with α=0.286 and Vdc2=0.3 V. (d) τ2=τ1=0.1τz, τp=ατz with α=0.33, Vdc2=0.3 V, and A=0.5 V and A=0.3 V for Figures 1(a) and 1(b), respectively.
(a)
(b)
(c)
(d)Finally, in Figure3(d), ω<1/τ1 with τ2=τ1=0.1τz, τp=ατz, α=0.33, and Vdc2=0.3 V. Under these conditions, θ2b≪θ2a=π/2-θ1, and decreased amplitudes must now be used in the circuit of Figure 1(b) or (9) compared to the circuit of Figure 1(a) or (8). Therefore, we select A=0.5 V and A=0.3 V for the two circuits, respectively, in this case.


## 3.2. Pinch Point Analysis

The unique form of (8) and (9) allows for a closed-loop solution of the pinch-off point in these circuits. It can be shown after considerable simplification that (8) and (9) have a pinch-off point V^inp,I^inp given by(20)V^inp=Vdc1-AX^Θ,I^inp=-A^cos2sin-1XΘ+θ2a,2b-θ1-B^sinsin-1XΘ-θ1-C^sinsin-1XΘ+θ2a,2b+D^cos2sin-1XΘ+2θ2a,2b+E^+I^off,where(21)X^Θ=B^/2sin-θ1+C^/2sinθ2a,2bA^sinθ2a,2b-θ1-D^sin2θ2a,2b,and the subscripts a,b refer to (8) and (9), respectively. The frequency dependent nature of (20) makes their analysis difficult; however, several observations can be deduced. First, X^Θ can be positive or negative depending on the values of θ1,θ2a, and θ2b as observed in Figure 3. In addition, C2 plays an important role even though it is not the main charge holding or integrating capacitor. In Figure 1(a), its minor role is to block Vdc1 as Vdc2 is passed, but in both circuits, its main contribution is to add a leading phase shift opposed to the lagging phase shift caused by C1. For example, in the circuit of Figure 1(b), in the absence of C2, that is, if C2=0, then sinθ2b=sin2θ2b=0, because θ2b=0, and with H2bω=α, (21) reduces to X^Θ=Vdc1/A, setting V^inp=0. That is, no pinch point will occur.Secondly, under the assumptionτ2=τ1, we find that V^inp=Vdc1 when tanθ1=C^/B^ or when Vdc2=Vdc1-VT/2. Under this condition, M1 remains in triode so long as Vdc1>3VT which is easily satisfied. For the general case when τ2=βτ1, implying that θ2a≠π/2-θ1 (unless β=1), the general solution to X^Θ=0 yields(22)Vdc2=ββ+1τ12ω2+1βτ12ω2+1Vdc1-VT.Likewise, the value for α in the circuit of Figure 1(b) that results in V^inp=Vdc1 can be expressed as(23)α=1-VTVdc1-ωτ1cscθ2bω2τ12+11+ω2τp21+ω2τz2.In both general cases, (22) and (23) are frequency dependent, the exception being when β=1 for (22), but both can be minimized for frequency dependance by ensuring that ωτ1>1, ωτz>1, and ωτp>1. Sample plots of theI-V characteristic for the circuit of Figure 1(a) governed by (8) to the conditions A=0.3 V, τ2=τ1=500 μs, Vdc1=1 V, VT=0.35 V, k=1 mA/V2, and Vdc2=Vdc1-VT/2=0.325 V are shown in Figure 4(a).Figure 4
(a) Matlab simulation of theI-V characteristic of Figure 1(a) governed by (8) to A=0.3 V, τ2=τ1=500 μs,Vdc1=1 V, VT=0.35 V, k=1 mA/V2, and Vdc2=0.325 V. (b) Input voltage vin(t) and current iina(t) plotted as a function of time at a frequency of ω=2π×800 rad/s.
(a)
(b)Note that becauseβ=1 and Vdc2=Vdc1-VT/2, V^inp=Vdc1 is independent of the input frequency which is verified at the three frequencies fo=[500,800,1500] Hz, as theoretically predicted. In Figure 4(b), vin(t) and iina(t) are plotted as a function of time.Finally, no pinch point occurs whenX^Θ=Vdc1/A or X^Θ=-Vdc1/A and if β=1 this happens at the two frequencies ω1,2: (24)ω1=1τ12Vdc2+VT3Vdc1-2Vdc2-VT,ω2=1τ12Vdc1-2Vdc2-VTVdc1+2Vdc2+VT.Furthermore, if Vdc2=1/2Vdc1-VT, a unique frequency at which no pinch point exists is(25)ω1=ω2=12τ1.In the case of Figure1(b), no easy closed-loop form of the solution exists, but when τz=τ1 the frequencies at which the pinch point occurs can be obtained by numerically solving, for ω, the equation(26)γ1ω4+δ1ω2+2α-1Vdc1+VT=0,whenX^Θ=Vdc1/A or(27)γ2ω4+δ2ω2+2αVdc1+VTτ1-τp+2Vdc1τp=0,whenX^Θ=-Vdc1/A, where (28)γ1=τp3τ1Vdc1+α-1Vdc1+VTτp2τ12+ατpτ13Vdc1,δ1=α-2τp2+α+1τpτ1+2α-1τ12Vdc1+τ12+τp2VT,γ2=τp4τ1Vdc1+2-αVdc1-VTτp3τ12+VT-Vdc1τp2τ13+ατpτ14Vdc1,δ2=2-αVdc1-VTτp3+Vdc1+VTτp2τ1+2-αVdc1-VTτpτ12+2α-1Vdc1+VTτ13.


## 4. Linearization ofM1

It is possible to reduce the distortion inM1 as a result of the Vds2/2 term in (2) by a number of techniques. One such technique is bisection of the input range first popularized by [19–21] and exploited by many others. Consider therefore the circuit shown in Figure 5 where M1 is replaced by transistors M1-6. Voltages vgsi and vdshp form the output voltages of the lossy integrator and high-pass filters, respectively. Transistors M1,2 are identical in size as are M3,4 and M5,6. Transistors M3,4 and M5,6 are to function as an adder as first proposed by [22] in the use of low voltage multipliers. Under the correct bias conditions, it follows that vo=vgsi+vdshp, and then given that both M1 and M2 have the same vds and each drain current is governed by I1=kvgsi-VTvdshp-vdshp2/2 and I2=kvo-VTvdshp-vdshp2/2, the total current It through M1 and M2 simplifies to It=I1+I2=2kvgsi-VTvdshp or an equivalent resistance of Req=1/2kVgsi-VT. Under these conditions, (8) and (9) change to(29)iinat=-A~cos2ωot-θ1+θ2a+B~sinωot-θ1+C~sinωot+θ2a+A~cosθ1+θ2a+I~off,and for Figure 1(b)(30)iinbt=-A~cos2ωot-θ1+θ2b+B~sinωot-θ1+C~sinωot+θ2b+A~cosθ1+θ2b+I~off, where the new coefficients A~,B~, and C~ are given in Table 3. Comparing (8)-(9) with (29)-(30) and likewise Tables 1 and 3, one notices fewer terms for the linearized resistor, with coefficients A~=A^ and B~=B^. In addition, both C~>C^ and I~off>I^off, with all other terms in the coefficients being equal. The corresponding new pinch point V~inp,I~inp is given by(31)V~inp=Vdc1-AX~Θ,(32)I~inp=-A~cos2sin-1X~Θ+θ2a,2b-θ1-B~sinsin-1X~Θ-θ1-C~sinsin-1X~Θ+θ2a,2b+A~cosθ1+θ2a,2b+I~off,where(33)X~Θ=B~/2sin-θ1+C~/2sinθ2a,2bA~sinθ2a,2b-θ1.The benefits to linearizing M1 are immediately clear upon close inspection of (31)–(33). In particular, for the circuit of Figure 1(a) in the general case when τ2=βτ1, the general solution to X~Θ=0 now yields(34)Vdc2=βτ12ω2+1β2τ12ω2+1Vdc1-VT,which, for β=1, implies that, for V~inp=Vdc1, Vdc2 is chosen such that Vdc2=Vdc1-VT. Of course, under these conditions, the composite linearized resistor is at the edge of the triode and a more practical solution would be for a given β≠1, ω, and τ1 to simply choose βτ12ω2+1/β2τ12ω2+1>Vdc2/Vdc1-VT. For the circuit of Figure 1(b) employing a linearized M1, the choice of α does not affect the pinch point; however, the value of Vdc1 that results in V~inp=Vdc1 is given by(35)Vdc1=VT1-ωτ1cscθ2b1+τp2ω2/1+τz2ω21+τ12ω2,which is still frequency dependent, but minimization is still possible if ωτ1>1, ωτz>1, and ωτp>1. Last but not least, no pinching occurs for the circuit of Figure 1(a) using the linearized resistor at frequencies (36)ω1=1τ1Vdc2+VT2Vdc1-Vdc2-VT,ω2=1τ12Vdc1-Vdc2-VTVdc1+2Vdc2+VTassuming τ2=τ1 and at (37)ω1=2Vdc1-VTVdc1τ1τp-τ12Vdc1-VT,ω2=2Vdc1-VTτp+VTτ1τ13-2τ12τp-τp2Vdc1+τp-τ1τ12VT,Table 3
Summary of the coefficients of the input currentiin(t) of Figures 1(a) and 1(b) in response to an input voltage vin(t) when M1 is replaced by a linearized resistor such as the one shown in Figure 5.
Coefficient
Figure1(a)
Figure1(b)
A~
1
2
k
A
2
H
1
ω
o
H
2
a
ω
o
1
2
k
A
2
H
1
ω
o
H
2
b
ω
o
B~
k
A
H
1
ω
o
V
d
c
2
α
k
A
H
1
ω
o
V
d
c
1
C~
k
A
H
2
a
ω
o
V
d
c
1
-
V
T
k
A
H
2
b
ω
o
V
d
c
1
-
V
T
I~off
k
V
d
c
1
-
V
T
V
d
c
2
α
k
V
d
c
1
-
V
T
V
d
c
1Figure 5
An improved linear resistor obtained by replacingM1 in Figure 1 with transistors M1-6.for the circuit of Figure1(b) when τz=τ1=ατp.


## 5. Simulation and Experimental Results

The circuits in Figures1(a) and 1(b) were simulated and built experimentally. In the sections that follow, simulations of Figures 1(a) and 1(b) without and with linearization of M1 were conducted. For the experiments, off-the-shelf discrete components were used without linearization of M1.


### 5.1. Simulation Results: WithoutM1 Linearization

For simulation purposes, Cadence was used employing the Design Kit offered by the AMS 0.35μm CMOS process. The opamp utilized in simulations is demonstrated in Figure 6, where the bias scheme was VDD=-VSS=5 V and Io=300 μA. The MOS transistors’ aspect ratio is given in Table 4 with Rc=140 Ω and Cc=2 pF to achieve a phase margin of 60∘. Also, the aspect ratio of transistor M1 in Figure 1(a) was 100 μm/1 μm; for M2, the aspect ratio was 12 μm/2 μm and thus its gain factor was k=1 mA/V2.Table 4
MOS transistors’ aspect ratio for Figure6.
Transistor
W
/
L
Mb1
50μm/2 μm
Mb2-Mb3
100μm/2 μm
Mn1-Mn2
200μm/0.5 μm
Mp1-Mp2
50μm/0.5 μm
Mp3
200μm/0.5 μmFigure 6
Opamp used in simulations.The resistor and capacitor values used in simulations wereR1= 820 Ω and C1=C2=470 nF and, therefore, τ1=τ2. The DC voltages were Vdc1=2 V and Vdc2=0.74 V. Considering a sinusoidal input with 700 mV amplitude and variable frequency, the obtained iina-υin characteristics, for f= 600 Hz, 1 kHz, and 1.5 kHz, are demonstrated in Figure 7. The time-domain behavior of the scheme in Figure 1(a) is demonstrated in Figure 8 for a 1 kHz input voltage. Likewise, the obtained iinb-υin characteristics, for Figure 1(b) for f= 400 Hz, 700 Hz, and 2 kHz, are demonstrated in Figure 9 with the corresponding time-domain behavior shown in Figure 10 for a 700 Hz input voltage.Figure 7
Simulatediina-υin characteristics for f= 600 Hz, 1 kHz, and 1.5 kHz.Figure 8
Time-domain behavior of the circuit in Figure1(a) for f= 1 kHz.Figure 9
Simulatediinb-υin characteristics for f= 400 Hz, 700 Hz, and 2 kHz.Figure 10
Time-domain behavior of the circuit in Figure1(b) for f= 700 Hz.The effect ofr2 in the operation of the topology in Figure 1(b) has also been studied under the conditions r2=0.4r1,0.56r1,and0.7r1, which sets α=0.26,0.36,and0.41, respectively. The derived iinb-υin characteristics, for f= 700 Hz, are given in Figure 11.Figure 11
Simulatediinb-υin characteristics for α=0.26,0.36,and0.41.


### 5.2. Simulation Results: WithM1 Linearization

The improved linear resistor shown in Figure5 was also used for linearizing transistor M1. The power supply voltage was equal to 2 V and the aspect ratio of M1-M2 and M5-M6 was 1 μm/2 μm, while for M3-M4 it was 3.2 μm/2 μm. Considering a sinusoidal input with 700 mV amplitude and variable frequency, the obtained iina-υin characteristics, for the circuit in Figure 1(a), derived at the same conditions as in the previous subsection, and for f= 600 Hz, 1 kHz, and 1.5 kHz, are demonstrated in Figure 12. The corresponding time-domain behavior is depicted in Figure 13 for a 1 kHz input voltage.Figure 12
Simulatediina-υin characteristics for the circuit in Figure 1(a) with f= 600 Hz, 1 kHz, and 1.5 kHz and linearization of M1.Figure 13
Time-domain behavior of the circuit in Figure1(a) for f= 1 kHz and linearization of M1.In a similar way, the plots for the circuit in Figure1(b), obtained at the same conditions as in the previous subsection, are given in Figure 14. The time-domain behavior is given in Figure 15 for a 700 Hz input voltage.Figure 14
Simulatediinb-υin characteristics for the circuit in Figure 1(b) with f= 400 Hz, 700 Hz, and 2 kHz and linearization of M1.Figure 15
Time-domain behavior of the circuit in Figure1(b) for f= 700 Hz and linearization of M1.


### 5.3. Experimental Results

In the first of a series of experimental tests, the circuit of Figure1(a) was constructed using 741 opamps powered by a ±15 V supply. The resistor and capacitor values used were R1=R2=820 Ω and C1=C2=470 nF ensuring that τ1=τ2. Transistors M1 and M2 were taken from Fairchild’s dual complementary pair CD4007CN chip. The DC biasing voltages used were Vdc1=4.6 V, Vdc2=1.12 V, and =1Vpp. The current iina was measured by inserting a 10Ω resistor in series with vin and measuring the voltage drop across this resistor using an instrumentation amplifier with a gain of 10; that is, iina=v10Ω. The results of vin versus iina are shown in Figure 16 for several frequencies starting at 1 kHz with the pinch point remaining nearly constant for Vdc2=1.12 V. Note that this result is consistent with (22) where SPICE models for the CD4007 (the actual value of VT is both foundry and process dependent but unfortunately actual data on the CD4007CN chips used was not available) place VT in the order of around 2~2.3V. Bending of the lobes can be observed towards a downward trend when the frequency is decreased below 1 kHz and upwards when the frequency is increased above 1 kHz. The usable range of this circuit was found to be from 300 Hz to 10 kHz. Note that the lower frequency limit on the operation of the circuit (300 Hz) is also consistent with (25) where, for Vdc2=1/2Vdc1-VT, R1=820 Ω, C1=470 nF, with τ1=τ2, yields a calculated value of ω1,2= 292 Hz. The upper frequency limit was observed when the lobes of the pinch hysteresis were too close to be distinguishable and in addition would also be set by limitations associated with A2 losing gain in its closed-loop configuration with M2.Figure 16
(a) Experimental results of the plot ofvin(t) and iina(t) at 1 kHz for the circuit of Figure 1(a). (b) Oscilloscope trace of the pinched hysteresis loop of the memristor emulator circuit of Figure 1(a) at 1 kHz, (c) at 600 Hz, and (d) at 1.5 kHz.
(a)
(b)
(c)
(d)In a second experimental test, the circuit of Figure1(b) was set up and the resistor and capacitor values used were R1=r2= 2 kΩ and C1=C2=470 nF ensuring that τz=τ1. The current iinb was likewise measured through a 10Ω resistor using an instrumentation amplifier set to a gain of 10. Resistor r1 was adjusted by a potentiometer at a value of r1=1031 Ω which set α=0.34. Input voltages were set at Vdc1=4 V and A=3Vpp and the initial frequency was set at 700 Hz. The results shown in Figure 17 indicate that the pinch point and symmetry of the lobes are highly dependent on the input frequency. For this configuration, pinching was lost for frequencies below 300 Hz and above 10 kHz.Figure 17
(a) Experimental results of the plot ofvin(t) and iinb(t) at 700 Hz for the circuit of Figure 1(b). (b) Oscilloscope trace of the pinched hysteresis loop at 700 Hz, (c) at 400 Hz, and (d) at 2 kHz.
(a)
(b)
(c)
(d)Finally, it should be mentioned that the circuits of Figures1(a) and 1(b) were also tested using different time constants such as τ1≠τ2 and τ1≠τz and all results not shown here were consistent with the expected theory.


## 5.1. Simulation Results: WithoutM1 Linearization

For simulation purposes, Cadence was used employing the Design Kit offered by the AMS 0.35μm CMOS process. The opamp utilized in simulations is demonstrated in Figure 6, where the bias scheme was VDD=-VSS=5 V and Io=300 μA. The MOS transistors’ aspect ratio is given in Table 4 with Rc=140 Ω and Cc=2 pF to achieve a phase margin of 60∘. Also, the aspect ratio of transistor M1 in Figure 1(a) was 100 μm/1 μm; for M2, the aspect ratio was 12 μm/2 μm and thus its gain factor was k=1 mA/V2.Table 4
MOS transistors’ aspect ratio for Figure6.
Transistor
W
/
L
Mb1
50μm/2 μm
Mb2-Mb3
100μm/2 μm
Mn1-Mn2
200μm/0.5 μm
Mp1-Mp2
50μm/0.5 μm
Mp3
200μm/0.5 μmFigure 6
Opamp used in simulations.The resistor and capacitor values used in simulations wereR1= 820 Ω and C1=C2=470 nF and, therefore, τ1=τ2. The DC voltages were Vdc1=2 V and Vdc2=0.74 V. Considering a sinusoidal input with 700 mV amplitude and variable frequency, the obtained iina-υin characteristics, for f= 600 Hz, 1 kHz, and 1.5 kHz, are demonstrated in Figure 7. The time-domain behavior of the scheme in Figure 1(a) is demonstrated in Figure 8 for a 1 kHz input voltage. Likewise, the obtained iinb-υin characteristics, for Figure 1(b) for f= 400 Hz, 700 Hz, and 2 kHz, are demonstrated in Figure 9 with the corresponding time-domain behavior shown in Figure 10 for a 700 Hz input voltage.Figure 7
Simulatediina-υin characteristics for f= 600 Hz, 1 kHz, and 1.5 kHz.Figure 8
Time-domain behavior of the circuit in Figure1(a) for f= 1 kHz.Figure 9
Simulatediinb-υin characteristics for f= 400 Hz, 700 Hz, and 2 kHz.Figure 10
Time-domain behavior of the circuit in Figure1(b) for f= 700 Hz.The effect ofr2 in the operation of the topology in Figure 1(b) has also been studied under the conditions r2=0.4r1,0.56r1,and0.7r1, which sets α=0.26,0.36,and0.41, respectively. The derived iinb-υin characteristics, for f= 700 Hz, are given in Figure 11.Figure 11
Simulatediinb-υin characteristics for α=0.26,0.36,and0.41.


## 5.2. Simulation Results: WithM1 Linearization

The improved linear resistor shown in Figure5 was also used for linearizing transistor M1. The power supply voltage was equal to 2 V and the aspect ratio of M1-M2 and M5-M6 was 1 μm/2 μm, while for M3-M4 it was 3.2 μm/2 μm. Considering a sinusoidal input with 700 mV amplitude and variable frequency, the obtained iina-υin characteristics, for the circuit in Figure 1(a), derived at the same conditions as in the previous subsection, and for f= 600 Hz, 1 kHz, and 1.5 kHz, are demonstrated in Figure 12. The corresponding time-domain behavior is depicted in Figure 13 for a 1 kHz input voltage.Figure 12
Simulatediina-υin characteristics for the circuit in Figure 1(a) with f= 600 Hz, 1 kHz, and 1.5 kHz and linearization of M1.Figure 13
Time-domain behavior of the circuit in Figure1(a) for f= 1 kHz and linearization of M1.In a similar way, the plots for the circuit in Figure1(b), obtained at the same conditions as in the previous subsection, are given in Figure 14. The time-domain behavior is given in Figure 15 for a 700 Hz input voltage.Figure 14
Simulatediinb-υin characteristics for the circuit in Figure 1(b) with f= 400 Hz, 700 Hz, and 2 kHz and linearization of M1.Figure 15
Time-domain behavior of the circuit in Figure1(b) for f= 700 Hz and linearization of M1.


## 5.3. Experimental Results

In the first of a series of experimental tests, the circuit of Figure1(a) was constructed using 741 opamps powered by a ±15 V supply. The resistor and capacitor values used were R1=R2=820 Ω and C1=C2=470 nF ensuring that τ1=τ2. Transistors M1 and M2 were taken from Fairchild’s dual complementary pair CD4007CN chip. The DC biasing voltages used were Vdc1=4.6 V, Vdc2=1.12 V, and =1Vpp. The current iina was measured by inserting a 10Ω resistor in series with vin and measuring the voltage drop across this resistor using an instrumentation amplifier with a gain of 10; that is, iina=v10Ω. The results of vin versus iina are shown in Figure 16 for several frequencies starting at 1 kHz with the pinch point remaining nearly constant for Vdc2=1.12 V. Note that this result is consistent with (22) where SPICE models for the CD4007 (the actual value of VT is both foundry and process dependent but unfortunately actual data on the CD4007CN chips used was not available) place VT in the order of around 2~2.3V. Bending of the lobes can be observed towards a downward trend when the frequency is decreased below 1 kHz and upwards when the frequency is increased above 1 kHz. The usable range of this circuit was found to be from 300 Hz to 10 kHz. Note that the lower frequency limit on the operation of the circuit (300 Hz) is also consistent with (25) where, for Vdc2=1/2Vdc1-VT, R1=820 Ω, C1=470 nF, with τ1=τ2, yields a calculated value of ω1,2= 292 Hz. The upper frequency limit was observed when the lobes of the pinch hysteresis were too close to be distinguishable and in addition would also be set by limitations associated with A2 losing gain in its closed-loop configuration with M2.Figure 16
(a) Experimental results of the plot ofvin(t) and iina(t) at 1 kHz for the circuit of Figure 1(a). (b) Oscilloscope trace of the pinched hysteresis loop of the memristor emulator circuit of Figure 1(a) at 1 kHz, (c) at 600 Hz, and (d) at 1.5 kHz.
(a)
(b)
(c)
(d)In a second experimental test, the circuit of Figure1(b) was set up and the resistor and capacitor values used were R1=r2= 2 kΩ and C1=C2=470 nF ensuring that τz=τ1. The current iinb was likewise measured through a 10Ω resistor using an instrumentation amplifier set to a gain of 10. Resistor r1 was adjusted by a potentiometer at a value of r1=1031 Ω which set α=0.34. Input voltages were set at Vdc1=4 V and A=3Vpp and the initial frequency was set at 700 Hz. The results shown in Figure 17 indicate that the pinch point and symmetry of the lobes are highly dependent on the input frequency. For this configuration, pinching was lost for frequencies below 300 Hz and above 10 kHz.Figure 17
(a) Experimental results of the plot ofvin(t) and iinb(t) at 700 Hz for the circuit of Figure 1(b). (b) Oscilloscope trace of the pinched hysteresis loop at 700 Hz, (c) at 400 Hz, and (d) at 2 kHz.
(a)
(b)
(c)
(d)Finally, it should be mentioned that the circuits of Figures1(a) and 1(b) were also tested using different time constants such as τ1≠τ2 and τ1≠τz and all results not shown here were consistent with the expected theory.


## 6. Conclusion

Two simple nonlinear circuits that exhibit unipolar pinched hysteresis behavior were presented in this paper. The multiplication-type nonlinearity between a state variable and its past history, as given in (1), is fundamental in obtaining pinched hysteresis although the past history can also be replaced by the rate of change of the present state as shown in [3]. In this work, this multiplication is simply achieved using the MOS transistor transconductance equation. The proposed circuits have been analyzed, their pinch points were determined, and their behavior was verified in Matlab and experimentally. A method of linearization that enables the elimination of undesired higher-order nonlinear terms was also examined and verified via simulations in Cadence. Of significant importance in this work is the clarification of the role played by the charge holding capacitor in the value of the charge-controlled memristance. We argue that, in all solid-state devices that have been fabricated and that show pinched hysteresis, a parasitic capacitor combined with a modulation-type (multiplication-type) nonlinearity is behind the appearance of this behavior. Arguably, the authors of [18] conclude that both “memory resistance and memory capacitance must coexist.”



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*Source: 7863095-2017-08-06.xml*