# An Adaptive Amplifier System for Wireless Sensor Network Applications

Authors: Mónica Lovay; Gabriela Peretti; Eduardo Romero; Carlos Marqués
Journal: Journal of Electrical and Computer Engineering
 (2012)

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## Abstract

This paper presents an adaptive amplifier that is part of a sensor node in a wireless sensor network. The system presents a target gain that has to be maintained without direct human intervention despite the presence of faults. In addition, its bandwidth must be as large as possible. The system is composed of a software-based built-in self-test scheme implemented in the node that checks all the available gains in the amplifiers, a reconfigurable amplifier, and a genetic algorithm (GA) for reconfiguring the node resources that runs on a host computer. We adopt a PSoC device from Cypress for the node implementation. The performance evaluation of the scheme presented is made by adopting four different types of fault models in the amplifier gains. The fault simulation results show that GA finds the target gain with low error, maintains the bandwidth above the minimum tolerable bandwidth, and presents a runtime lower than exhaustive search method.


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## Body

## 1. Introduction

The advances in electronics have enabled the development of low cost, low power, and multifunctional wireless sensor nodes that consist of sensing, data processing, and communication components [1]. These small sensor nodes can be installed in a designated area to form a wireless network for performing specific functions. Usually, a host computer collects data from the sensors and carries out different actions depending on the particular purpose of the system. A broad range of applications has been proposed for this kind of systems such as industrial sensor networks, environmental monitoring, home automation, and medical care [2].The processing and communication units typically found in wireless sensor nodes can be implemented with microcontrollers (μCs). These offer benefits like low cost and power consumption, ability to perform data processing tasks in the nodes, and usually powerful communication interfaces. In addition, some modern μCs offer a wide pool of configurable digital and analog sections that enhance the node adaptation to a broad range of applications.In a number of applications, the nodes operate in harsh environments, under the action of a several agents that  could potentially deteriorate their performances. If the application is critical, reliable operation of the node can require characteristics of safe operation, adaptation to a changing environment, or ability for compensating degradations in its own circuitry. For achieving this purpose, two related characteristics are necessary: fault detection and circuit self-adaptation.The fault detection characteristic could be constrained by the low power operation of the node, which could make the use of dedicated test circuitry inconvenient for performing built-in self-test. Instead, a software-based self-test (SBST) strategy arises as an effective alternative that can provide in-field testing capabilities with very low area and performance overhead [3]. Particularly suitable for μCs, an SBST strategy utilizes the existing processing core to perform a self-test of the analog and digital components in a node [4, 5].Providing adaptive characteristics to the node requires configurable hardware sections and a reconfiguration methodology. Evolvable hardware (EHW) is a methodology that offers self-adaptation by combining reconfigurable hardware with evolutionary algorithms. In EHW, the designer establishes performance goals and usually a genetic algorithm [6] searches for the possible hardware configurations for reaching them [7, 8]. In this way, EHW offers an alternative to traditional fault tolerant schemes [7, 9]. Additionally, even if EHW does not always guarantee that a complete functionality can be restored, it allows maintaining the system operation with graceful degradation [10].In this paper, we focus our efforts in the development of an adaptive amplifier embedded in theμC that is part of the node. We implement the amplifier on a platform that presents analog reconfigurable sections, a PSoC1 device from Cypress. One of the goals of our work is the development of a very low cost SBST strategy for the analog configurable sections. The other goal is the development of an EHW strategy that uses a GA-based reconfiguration strategy, which runs on the host computer. In this way, the amplifier maintains its targeted functional parameters between limits established by the user, without direct human intervention.


## 2. System Description

### 2.1. Architecture of the PSoC Device

As it was above mentioned, we adopt a PSoC1 device from Cypress for implementing the nodes. The PSoC1 device is a programmable system-on-chip platform with an 8-bit processor core [11]. The device presents an on-chip clocking solution and includes flash memory, SRAM, configurable blocks of analog and digital circuits, programmable interconnect, and configurable IO in a low-cost chip. Figure 1 shows its architecture.Figure 1
Architecture of PSoC1 device.Analog functions in the device are implemented by the combination (using programmable interconnection) of groups of general-purpose analog blocks that can be configured for user-determined functions with a design editing software tool. The control for these blocks is register-based and can be dynamically reconfigured during operation. There are two basic types of analog blocks: continuous-time (CT) and switched-capacitor (SC). The organization of the analog blocks is in columns. Each column contains one CT block and two types of SC blocks. The blocks are connected to direct port inputs, input multiplexers, column clock resources and output buffers for each column [12].Some of the available configurations for the analog arrays are up to 14-bits analog-to-digital converters (ADC), up to 9 bits digital-to-analog converters (DAC), programmable gain amplifiers (PGA), programmable filters, and comparators. These functions could employ one analog PSoC block, a combination of more than one analog type (CT or SC), and even the inclusion of digital blocks.


### 2.2. The Programmable Gain Amplifier (PGA)

The PGA user module implements an opamp-based noninverting amplifier with user-programmable gain (Figure2). This amplifier, built in one CT block, has high input impedance, wide bandwidth, and selectable reference. The PGA gain is set by programming a selectable tap in a resistor string located in the opamp feedback path  (Ra and Rb in Figure 2(a)). Figure 2(b) shows in detail the resistor ladder configuration and the signals; RtapMux and EXGAIN, which select the tap connection. For gains greater than or equal to one, the top of the resistor string is connected to the opamp output and the resistor tap is connected to the inverting input of the opamp. Under this condition, the output voltage (Vo) is(1)Vo=(Vin-VGND)(1+RbRa)+VGND.(a) PGA diagram. (b) Resistor ladder configuration.
(a)(b)For gains less than one, the opamp is set as voltage follower and the user module output is connected to the resistor tap. The amplifier output value is obtained by evaluating(2)Vo=(Vin-VGND)(RaRa+Rb)+VGND.In (1) and (2), Vin is the voltage at the PGA input and VGND is a reference voltage. The user can specify the reference as one of the following: a fixed value derived from the internal bandgap reference, a value ratiometric to the supply voltage, analog ground, or an external input. There are 36 programmable values for the PGA gain, ranging from 0.0208 to 48 [13].The CT block allows a configuration (Figure3) that connects VDD at the top of the resistor string and VSS at the bottom, while routes at the output the voltage value of the tap resistor. By the proper setting of the signals EXGAIN and RtapMux, it is possible to check all the values available at the tap resistor. This configuration is used in test mode to be explained in Section 3.Figure 3
CT configuration for testing the resistor matrix (simplified diagram).


### 2.3. The Adaptive Amplifier

We assume that each node of the wireless sensor network requires an adaptive amplifier. For implementing the amplifier, we propose the use of programmable gain amplifiers (PGAs) in cascade connection. It should be noted that preliminary results about the amplifier were reported in [14]. However, the two key components of the system, the SBST and the GA used in the reconfiguration, are different in this new proposal.The use of PGAs is frequent in systems that require an analog front-end for signal conditioning. Particularly, a wide range of applications employs PSoC1 PGAs for this end, [15–18]. This allows devising a wide range of application possibilities for the presented system, even if the analog blocks do not present the same high performance characteristics that could present specific-purpose analog devices.In this paper, we use four amplifiers in the chain (PGA1, PGA2, PGA3, and PGA4 in Figure4) one for each column of the PSoC analog array (shown in Figure 1). This configuration presents a broad range of alternative values for establishing the overall gain that contributes to achieve a better self-adaptation. However, the cascade connection could reduce the overall bandwidth below the user specifications. For this reason, we consider that the system has a target gain that has to be maintained despite the presence of faults, while its bandwidth must be larger than the one required by the application.Figure 4
Amplifier system diagram.An SBST strategy checks during the idle times of the system the available gains of each amplifier and determines if it is necessary a system reconfiguration. Additionally, several routines (running in theμC) control the overall operation of the node. The host computer runs the genetic algorithm (GA) that finds the values for the system reconfiguration. The evolved values of gain are loaded back into the hardware for continuing the normal operation.


## 2.1. Architecture of the PSoC Device

As it was above mentioned, we adopt a PSoC1 device from Cypress for implementing the nodes. The PSoC1 device is a programmable system-on-chip platform with an 8-bit processor core [11]. The device presents an on-chip clocking solution and includes flash memory, SRAM, configurable blocks of analog and digital circuits, programmable interconnect, and configurable IO in a low-cost chip. Figure 1 shows its architecture.Figure 1
Architecture of PSoC1 device.Analog functions in the device are implemented by the combination (using programmable interconnection) of groups of general-purpose analog blocks that can be configured for user-determined functions with a design editing software tool. The control for these blocks is register-based and can be dynamically reconfigured during operation. There are two basic types of analog blocks: continuous-time (CT) and switched-capacitor (SC). The organization of the analog blocks is in columns. Each column contains one CT block and two types of SC blocks. The blocks are connected to direct port inputs, input multiplexers, column clock resources and output buffers for each column [12].Some of the available configurations for the analog arrays are up to 14-bits analog-to-digital converters (ADC), up to 9 bits digital-to-analog converters (DAC), programmable gain amplifiers (PGA), programmable filters, and comparators. These functions could employ one analog PSoC block, a combination of more than one analog type (CT or SC), and even the inclusion of digital blocks.


## 2.2. The Programmable Gain Amplifier (PGA)

The PGA user module implements an opamp-based noninverting amplifier with user-programmable gain (Figure2). This amplifier, built in one CT block, has high input impedance, wide bandwidth, and selectable reference. The PGA gain is set by programming a selectable tap in a resistor string located in the opamp feedback path  (Ra and Rb in Figure 2(a)). Figure 2(b) shows in detail the resistor ladder configuration and the signals; RtapMux and EXGAIN, which select the tap connection. For gains greater than or equal to one, the top of the resistor string is connected to the opamp output and the resistor tap is connected to the inverting input of the opamp. Under this condition, the output voltage (Vo) is(1)Vo=(Vin-VGND)(1+RbRa)+VGND.(a) PGA diagram. (b) Resistor ladder configuration.
(a)(b)For gains less than one, the opamp is set as voltage follower and the user module output is connected to the resistor tap. The amplifier output value is obtained by evaluating(2)Vo=(Vin-VGND)(RaRa+Rb)+VGND.In (1) and (2), Vin is the voltage at the PGA input and VGND is a reference voltage. The user can specify the reference as one of the following: a fixed value derived from the internal bandgap reference, a value ratiometric to the supply voltage, analog ground, or an external input. There are 36 programmable values for the PGA gain, ranging from 0.0208 to 48 [13].The CT block allows a configuration (Figure3) that connects VDD at the top of the resistor string and VSS at the bottom, while routes at the output the voltage value of the tap resistor. By the proper setting of the signals EXGAIN and RtapMux, it is possible to check all the values available at the tap resistor. This configuration is used in test mode to be explained in Section 3.Figure 3
CT configuration for testing the resistor matrix (simplified diagram).


## 2.3. The Adaptive Amplifier

We assume that each node of the wireless sensor network requires an adaptive amplifier. For implementing the amplifier, we propose the use of programmable gain amplifiers (PGAs) in cascade connection. It should be noted that preliminary results about the amplifier were reported in [14]. However, the two key components of the system, the SBST and the GA used in the reconfiguration, are different in this new proposal.The use of PGAs is frequent in systems that require an analog front-end for signal conditioning. Particularly, a wide range of applications employs PSoC1 PGAs for this end, [15–18]. This allows devising a wide range of application possibilities for the presented system, even if the analog blocks do not present the same high performance characteristics that could present specific-purpose analog devices.In this paper, we use four amplifiers in the chain (PGA1, PGA2, PGA3, and PGA4 in Figure4) one for each column of the PSoC analog array (shown in Figure 1). This configuration presents a broad range of alternative values for establishing the overall gain that contributes to achieve a better self-adaptation. However, the cascade connection could reduce the overall bandwidth below the user specifications. For this reason, we consider that the system has a target gain that has to be maintained despite the presence of faults, while its bandwidth must be larger than the one required by the application.Figure 4
Amplifier system diagram.An SBST strategy checks during the idle times of the system the available gains of each amplifier and determines if it is necessary a system reconfiguration. Additionally, several routines (running in theμC) control the overall operation of the node. The host computer runs the genetic algorithm (GA) that finds the values for the system reconfiguration. The evolved values of gain are loaded back into the hardware for continuing the normal operation.


## 3. PGA Resistor Ladder Test

The test strategy proposed here uses the processor core, on-chip analog resources, and the dynamic reconfiguration characteristic of the PSoC device. Consequently, this SBST approach virtually eliminates the need for additional test-specific hardware. Another characteristic of the SBST proposed here is that it does not require the host computer intervention. Consequently, it could also be used without restrictions as a low-cost, no hardware overhead test for the resistor arrays of the CT blocks in any PSoC1-based system.PSoC dynamic reconfiguration characteristic is a powerful feature that enables the designer to program multiple hardware configurations and dynamically change them while the device is running [19]. In this way, the amplifier system is placed in one hardware configuration, while the test hardware is configured in a different one. The processor loads from the program memory the setup of each configuration in runtime. The normal mode configuration presents only the PGAs connected in cascade, while the test mode configuration arranges the PGAs connections in order to obtain access to the resistor arrays (Figure 3). Additionally, the configuration employs other modules that are necessary for the test process, for example, ADCs.In test mode, besides loading the test hardware configuration, the processor executes an embedded routine that acquires data and performs the required calculations. At the end of the test process, the test routine delivers to the host computer the parameters that characterize the resistor relations for the four PGAs.The test configuration is shown in Figure5. The CT block (where each PGA is placed) is configured for testing the resistor matrix (Figure 3). A 12-bit analog-to-digital converter (ADC12) (one by column) acquires all the available voltage values from the resistor matrix. The test routine programs these values using the settings of the RtapMux and EXGAIN registers. The combination of RtapMux and EXGAIN used during the test and the nominal voltage values of the resistor tap (Vref) are shown in Table 1. Also presented in the table are the gain values that the PGA adopts (that also depends on the gain signal value) for the corresponding resistor-matrix relations.Table 1
Test conditions and expected values for the resistor matrix.
Test conditionRtapMux (hexadecimal values)EXGAINNominal value for Vref (Vdd Units)PGA gain value (gain ≥1)PGA gain value (gain ≤1)1010.020848.0000.02082110.041724.0000.04173000.062516.0000.06254100.12508.0000.12505200.18755.3330.18756300.25004.0000.25007400.31253.2000.31258500.37502.6670.37509600.43752.2860.437510700.50002.0000.500011800.56251.7780.562512900.62501.6000.625013A00.68751.4550.687514B00.75001.3330.750015C00.81251.2310.812516D00.87501.1430.875017E00.93751.0670.937518F01.00001.0001.0000Figure 5
Test hardware configuration.From the measurement of the voltage values, it is possible to establish all values of the programmed relations ofRa and Rb (Figure 2) and check if they are within the limits specified by the user. Because to the resistance ratios determine the gain values for the PGA module, the routine indirectly tests the correctness of the PGA gain values, avoiding the use of a test stimulus. If the gains are outside the limits allowed by the application needs (including the measurement errors), it is accepted that the system is faulty and a reconfiguration process starts in the host computer.It should be noted that in order to consider the whole node reliable, we assume that the tests of the other parts of the node are solved for instance with techniques and strategies like those presented in [20, 21].


## 4. System Self-Adaptation

### 4.1. Overview of GA

As previously stated, GA evolves the gain values of the four amplifiers with the goal of maintaining the system overall gain within specifications and the bandwidth as large as possible. As we consider that gain is the most important objective, we employ theε-constraint method for implementing the optimization. This method performs the optimization with respect to one objective and transforms the others into restrictions [22, 23]. The use of this method allows employing traditional GAs, as described in [6, 7, 24].Figure6 shows a flowchart of the GA used in this work. For the sake of clarity, in the following paragraph, numbers are related to the corresponding block in the flowchart. Appendix B shows Matlab code for the operations selection, crossover, and mutation.(1)
The algorithm randomly generates (with uniform probability) an initial population of individuals that are possible solutions to the problem. Each solution in the population is a string of bits, also called chromosomes or genotypes.(2)
For every evolutionary step, known as a generation, the individuals in the current population are evaluated according to some predefined quality criterion called the fitness function. To form a new population (the next generation), individuals are selected according to their fitness; high fitness individuals present better chances to appear (survive) in the next generation, while low fitness ones are more likely to disappear.(3)
The GA takes into account the restrictions by the use of a penalty technique (3.1 in the flowchart). By using this technique, the solutions violating the restrictions are modified in their fitness values (based on the violation degree) in order to decrease their chances of being selected.(4)
The selection of the individuals for the next generation is performed through the method of the rotating roulette. The probability of an individual to be selected for crossover is proportional to its fitness.(5)
The crossover operator selects two individuals, called parents, and exchanges parts of their information (the string of bits) to form two new individuals, called offspring. In its simplest form, it exchanges bits from one parent for bits from the other parent, creating two offspring. If the two parents do not undergo the crossover operation, they are copied unchanged to the new pool of individuals.(6)
The mutation operator is applied to the new pool of individuals produced after the application of crossover. This operator prevents premature convergence to local optima by flipping bits (of individuals) at random with some probability.(7)
If the individual generated does not represent a legal solution due to the nature of the encoding technique, then it is repaired (7.1 in the flowchart).(8)
This new generation goes through the process described above, from the fitness evaluation to the repair step. The cycle repeats until a stop criterion is met, such as a maximum number of generations is reached or a desired solution is found.Figure 6
Flowchart of the genetic algorithm.


### 4.2. GA Parameters

The GA has to find the four PGA gain values (G1 for PGA1, G2 for PGA2, G3 for PGA3, and G4 for PGA4) that reach the condition:(3)Min⁡(|Atar-G1⋅G2⋅G3⋅G4|)subjecttoBW≥ε.In (3), Atar is the target gain and ε is the minimum tolerable bandwidth (BW) of the system. The values available for each PGA are obtained by the SBST strategy presented in Section 3.The BW value of the adaptive amplifier is found as the real positive solution to (4) [25]. For formulating this equation, each PGA is modeled as a first-order system, as reported by the vendor(4)∏k=14[1+(BWpk)2]=2.In (4), pk is the pole of the kth PGA. Its value is calculated as(5)pk=GBWPGk⋯ifGk≥1,pk=GBWP⋯ifGk≤1.In (5), GBWP is the gain bandwidth product reported by the vendor and Gk is the gain of the kth amplifier.For simplifying the operation of the GA, the equation of the fitness function(f) is formulated for obtaining a maximum [6]:(6)f=B-|Atar-G1G2G3G4|,
where B is a constant added for avoiding negative numbers.For each PGA gain value, a simple binary codification of 6 bits is used. The length of the chromosome results consequently in 24 bits.The creation of the population in the first cycle of the algorithm is made by using uniform initialization. The population size is 30, and the number of generations is 25. The fitness of each individual is calculated using (6). The size of the population is chosen according to the guidelines of [24] and ensures that the probability of finding a binary value 1 or a binary value 0 at each position in the chromosome exceeds 99.9%.In order to apply the restrictions, the algorithm increases thef value to the individuals that present an overall gain within specification and BW greater than or equal to ε. The individuals with higher BW are assigned with a higher fitness value (Hf) as follows:(7)Hf=f+f⋅(BW-ε)ε.On the other hand, the algorithm penalizes the individuals with BW belowε, even if they present a gain within specification. Consequently, these individuals will adopt a lower fitness (Lf), according to the following expression:(8)Lf=f-f⋅(ε-BW)ε.The selection of the individuals for the crossover is performed through the method of the rotating roulette. The probability of an individual to be selected for crossover is proportional to its fitness. The probability of crossover is 0.5 and the probability of mutation is 0.3. These values are chosen using previous experimental guidelines [10, 24].In the new generation can exist illegal individuals, since there are 28 values (26–36) that cannot be adopted by the PGA. We propose for solving this problem a repair technique that replaces illegal individuals for legal ones. The technique assigns a legal value proportional to the value of the illegal solution (bigger illegal solutions are repaired as bigger legal solutions).


### 4.3. Fault Models and Fault Injection

The performance of the scheme presented here is evaluated by means of fault injection. To this end, it is necessary to define a fault model. As the system addressed in this paper is configurable, we adopt fault models similar to those used by the authors of [26–29]. In these papers, the authors propose fault models for the evaluation of test strategies for field-programmable analog circuits.If the PGA is well designed, the operational amplifier can present wide deviations in its functional parameters without effects in its closed loop performance. Consequently, we consider that the main cause of PGA gain faults comes from degradations in the resistances that establish the gain. In each PGA, we consider four different fault models for the gain determined by the resistancesRa and Rb (Figure 2(a)).The named Model 1, Model 2, and Model 3 are catastrophic, single fault models. Model 1 assumes that is not possible to establish a gain value in a PGA due to a stuck-open fault in one of the switches that configure the PGA. Model 2 considers that it is not possible to establish two gain values. This model takes into account that a stuck-open fault in one of the switches that connect the resistors (Figure2(b)) can lead to two different values of gain not available for the PGAs. These two gain values present the same setup for EXGAIN and RtapMux signals but differ in the value of the signal Gain, which determines if the PGA gain is less than or greater than one (see Section 2.2). Model 3 considers a stuck-on fault in a switch, which is always in on state. Finally, Model 4 is a parametric one and assumes that there is a deviation in the gain values. This model takes into account parametric faults present in the resistor array.Because PGAs are embedded in the PSoC devices, it is impossible to inject faults directly in the hardware. For this reason, we adopt a different approach. To inject a fault using Model 1, we eliminate from the search space used by the GA the gain value that is assumed as faulty. When Model 2 is used, we remove the two gain values that present the same combination of EXGAIN and RtapMux.The injection of fault Model 3 requires considering the location of the switch that presents the stuck-on fault and establishing the gain value under this condition. For instance, Figure7 shows a stuck-on in the switch that establishes a gain value of 16 (EXGAIN = 0, RtapMux = 0, and test condition 3 in Table 1). If under this fault it is programmed a gain value of 24 (EXGAIN  =  1, RtapMux  =  1, and test condition 2 in Table 1), then a gain value of 23.5 is obtained instead. This process is repeated for all the test conditions described in Table 1.Figure 7
Stuck-on fault injection example.For injecting faults using Model 4, we shift the gains values in the search space. Particularly, we consider that a PGA presents a deviation in its gain values in a percentage of its nominal values of ±10%, ±20%, ±30%, ±40%, and ±50%.


## 4.1. Overview of GA

As previously stated, GA evolves the gain values of the four amplifiers with the goal of maintaining the system overall gain within specifications and the bandwidth as large as possible. As we consider that gain is the most important objective, we employ theε-constraint method for implementing the optimization. This method performs the optimization with respect to one objective and transforms the others into restrictions [22, 23]. The use of this method allows employing traditional GAs, as described in [6, 7, 24].Figure6 shows a flowchart of the GA used in this work. For the sake of clarity, in the following paragraph, numbers are related to the corresponding block in the flowchart. Appendix B shows Matlab code for the operations selection, crossover, and mutation.(1)
The algorithm randomly generates (with uniform probability) an initial population of individuals that are possible solutions to the problem. Each solution in the population is a string of bits, also called chromosomes or genotypes.(2)
For every evolutionary step, known as a generation, the individuals in the current population are evaluated according to some predefined quality criterion called the fitness function. To form a new population (the next generation), individuals are selected according to their fitness; high fitness individuals present better chances to appear (survive) in the next generation, while low fitness ones are more likely to disappear.(3)
The GA takes into account the restrictions by the use of a penalty technique (3.1 in the flowchart). By using this technique, the solutions violating the restrictions are modified in their fitness values (based on the violation degree) in order to decrease their chances of being selected.(4)
The selection of the individuals for the next generation is performed through the method of the rotating roulette. The probability of an individual to be selected for crossover is proportional to its fitness.(5)
The crossover operator selects two individuals, called parents, and exchanges parts of their information (the string of bits) to form two new individuals, called offspring. In its simplest form, it exchanges bits from one parent for bits from the other parent, creating two offspring. If the two parents do not undergo the crossover operation, they are copied unchanged to the new pool of individuals.(6)
The mutation operator is applied to the new pool of individuals produced after the application of crossover. This operator prevents premature convergence to local optima by flipping bits (of individuals) at random with some probability.(7)
If the individual generated does not represent a legal solution due to the nature of the encoding technique, then it is repaired (7.1 in the flowchart).(8)
This new generation goes through the process described above, from the fitness evaluation to the repair step. The cycle repeats until a stop criterion is met, such as a maximum number of generations is reached or a desired solution is found.Figure 6
Flowchart of the genetic algorithm.


## 4.2. GA Parameters

The GA has to find the four PGA gain values (G1 for PGA1, G2 for PGA2, G3 for PGA3, and G4 for PGA4) that reach the condition:(3)Min⁡(|Atar-G1⋅G2⋅G3⋅G4|)subjecttoBW≥ε.In (3), Atar is the target gain and ε is the minimum tolerable bandwidth (BW) of the system. The values available for each PGA are obtained by the SBST strategy presented in Section 3.The BW value of the adaptive amplifier is found as the real positive solution to (4) [25]. For formulating this equation, each PGA is modeled as a first-order system, as reported by the vendor(4)∏k=14[1+(BWpk)2]=2.In (4), pk is the pole of the kth PGA. Its value is calculated as(5)pk=GBWPGk⋯ifGk≥1,pk=GBWP⋯ifGk≤1.In (5), GBWP is the gain bandwidth product reported by the vendor and Gk is the gain of the kth amplifier.For simplifying the operation of the GA, the equation of the fitness function(f) is formulated for obtaining a maximum [6]:(6)f=B-|Atar-G1G2G3G4|,
where B is a constant added for avoiding negative numbers.For each PGA gain value, a simple binary codification of 6 bits is used. The length of the chromosome results consequently in 24 bits.The creation of the population in the first cycle of the algorithm is made by using uniform initialization. The population size is 30, and the number of generations is 25. The fitness of each individual is calculated using (6). The size of the population is chosen according to the guidelines of [24] and ensures that the probability of finding a binary value 1 or a binary value 0 at each position in the chromosome exceeds 99.9%.In order to apply the restrictions, the algorithm increases thef value to the individuals that present an overall gain within specification and BW greater than or equal to ε. The individuals with higher BW are assigned with a higher fitness value (Hf) as follows:(7)Hf=f+f⋅(BW-ε)ε.On the other hand, the algorithm penalizes the individuals with BW belowε, even if they present a gain within specification. Consequently, these individuals will adopt a lower fitness (Lf), according to the following expression:(8)Lf=f-f⋅(ε-BW)ε.The selection of the individuals for the crossover is performed through the method of the rotating roulette. The probability of an individual to be selected for crossover is proportional to its fitness. The probability of crossover is 0.5 and the probability of mutation is 0.3. These values are chosen using previous experimental guidelines [10, 24].In the new generation can exist illegal individuals, since there are 28 values (26–36) that cannot be adopted by the PGA. We propose for solving this problem a repair technique that replaces illegal individuals for legal ones. The technique assigns a legal value proportional to the value of the illegal solution (bigger illegal solutions are repaired as bigger legal solutions).


## 4.3. Fault Models and Fault Injection

The performance of the scheme presented here is evaluated by means of fault injection. To this end, it is necessary to define a fault model. As the system addressed in this paper is configurable, we adopt fault models similar to those used by the authors of [26–29]. In these papers, the authors propose fault models for the evaluation of test strategies for field-programmable analog circuits.If the PGA is well designed, the operational amplifier can present wide deviations in its functional parameters without effects in its closed loop performance. Consequently, we consider that the main cause of PGA gain faults comes from degradations in the resistances that establish the gain. In each PGA, we consider four different fault models for the gain determined by the resistancesRa and Rb (Figure 2(a)).The named Model 1, Model 2, and Model 3 are catastrophic, single fault models. Model 1 assumes that is not possible to establish a gain value in a PGA due to a stuck-open fault in one of the switches that configure the PGA. Model 2 considers that it is not possible to establish two gain values. This model takes into account that a stuck-open fault in one of the switches that connect the resistors (Figure2(b)) can lead to two different values of gain not available for the PGAs. These two gain values present the same setup for EXGAIN and RtapMux signals but differ in the value of the signal Gain, which determines if the PGA gain is less than or greater than one (see Section 2.2). Model 3 considers a stuck-on fault in a switch, which is always in on state. Finally, Model 4 is a parametric one and assumes that there is a deviation in the gain values. This model takes into account parametric faults present in the resistor array.Because PGAs are embedded in the PSoC devices, it is impossible to inject faults directly in the hardware. For this reason, we adopt a different approach. To inject a fault using Model 1, we eliminate from the search space used by the GA the gain value that is assumed as faulty. When Model 2 is used, we remove the two gain values that present the same combination of EXGAIN and RtapMux.The injection of fault Model 3 requires considering the location of the switch that presents the stuck-on fault and establishing the gain value under this condition. For instance, Figure7 shows a stuck-on in the switch that establishes a gain value of 16 (EXGAIN = 0, RtapMux = 0, and test condition 3 in Table 1). If under this fault it is programmed a gain value of 24 (EXGAIN  =  1, RtapMux  =  1, and test condition 2 in Table 1), then a gain value of 23.5 is obtained instead. This process is repeated for all the test conditions described in Table 1.Figure 7
Stuck-on fault injection example.For injecting faults using Model 4, we shift the gains values in the search space. Particularly, we consider that a PGA presents a deviation in its gain values in a percentage of its nominal values of ±10%, ±20%, ±30%, ±40%, and ±50%.


## 5. Experimental Results

### 5.1. Test Results

The test routine is written in assembly language. The experiments were performed in a CY3210-PSoCEval1 board that provides the necessary hardware to evaluate the PSoC1 device CY8C29466-24PXI. In order to simplify the experiments, we implement in the device a communication module to the host computer through an RS-232 serial interface.Table2 shows the mean values of the resistor array for the test conditions depicted in Table 2. In the table, the values are very close to the ideal reported in Table 1 and the highest errors are for test conditions 1 to 4. The relative error to the nominal value is always below 5%, with the exception of PGA3, test condition 1. In this case, the error rises to 7%.Table 2
Resistor-matrix test results.
Test conditionPGA1 Vref (VDD units)PGA2 Vref (VDD units)PGA3 Vref (VDD units)PGA4 Vref (VDD units)10.01990.02150.02230.021120.04070.04230.04300.041130.06150.06340.06410.060440.12380.12580.12670.125550.18610.18820.18930.186760.24880.25080.25200.249970.31140.31320.31430.312580.37410.37560.37670.374290.43660.43800.43910.4373100.49920.50060.50120.4993110.56170.56330.56360.5634120.62390.62540.62570.6253130.68670.68800.68810.6860140.74920.75040.75050.7504150.81200.81310.81290.8120160.87450.87520.87500.8745170.93700.93760.93740.9376181.00001.00001.00001.0000


### 5.2. Fault Free Operation

We propose three different values for the target gain(Atar): 2, 8, and 15 with the aim of evaluating the ability of GA for finding an acceptable solution in different scenarios. We set the value of the minimum −3 dB BW (ε) in 4E+06 rad/s (636 kHz), also for demonstration purposes.As GA is a stochastic process, its results could change according to the statistical distribution of the initial population. In order to see how the results could be affected by the setting of the initial population, we change the seed of its random generation and consider that all gains are available for running the algorithm. The distribution of the obtained results can be observed in the dispersion diagram depicted in Figure8. In the figure, each point is a solution to the optimization problem changing the seed and shows the relative error of the gain versus the bandwidth for the three target gains. From the figure, the three target gains present relative errors in the range [−4.982%, 4.831%]. The lowest BW obtained for all the evaluated gains is 4.06E+6 rad/s, above the required.Figure 8
Gain relative error versus bandwidth. Fault-free operation.Table3 shows a characterization of the relative error for the three target gain values. We adopt the median as a measurement of central tendency because the data distribution is not normal. We also present the maximum and minimum as a measurement of dispersion. The table shows that the relative error for all the cases is below the required (±5%). Additionally, the median of the relative error is close to zero for all target gains.Table 3
Gain relative error characterization under fault-free condition.
Target gainMedian (%)Minimum error (%)Maximum error (%)150.244%−4.932%4.767%8−0.307%−4.847%4.686%20.070%−4.982%4.831%


### 5.3. Operation under Fault Condition

#### 5.3.1. Fault Model 1

For space reasons, we only report in Figure9 the fault injection results corresponding to PGA1 which presents the worst results. The figure shows the relative error of the overall gain versus the bandwidth for the three target gains. Each point is a solution to the optimization problem under Model 1 fault. The figure shows that the error in the gain is near ±5% for all the target gains, while the bandwidth is above the required.Figure 9
Gain relative error versus bandwidth. Operation under fault model 1 injected in PGA1.Table4 summarizes the fault injection results for the four PGAs. In this table, we grouped the results by gain value. Comparing the gain error results obtained from fault-free operation (Table 3) and faulty operation (Table 4), the faulty system presents in the worst case an increase of 0.405% in the error range for gain 8. The median of the relative error decreases for the three gains, suggesting that the error distribution changes between the fault-free and faulty operation. In all the experiments, the GA is capable of reaching the target gain, with errors for all the gains in the range [−4.996%, 4.963%]. The lowest BW obtained for all the simulated conditions is 4.03E+6 rad/s above the required.Table 4
Gain relative error characterization under fault model 1.
Target gainMedian (%)Minimum error (%)Maximum error (%)15−0.458%−4.918%4.746%8−0.825%−4.975%4.963%2−0.401%−4.996%4.841%


#### 5.3.2. Fault Model 2

Figure10 shows the results using Fault Model 2 in PGA3. We report only these results because this PGA presents the worst performance in the fault injection process. Each point in the figure is a solution to the problem when a Model 2 fault is injected in the PGA.Figure 10
Gain relative error versus bandwidth. Operation under fault model 2 in PGA3.Table5 summarizes the fault simulation results using Model 2. Comparing the gain error results obtained from fault-free operation (Table 3) and fault operation (Table 5), the faulty system presents in the worst case an increase of 0.286% in the error range for gain 8. The median of the relative error increases for the gains 8 and 15, while for gain 2 it decreases.Table 5
Gain relative error characterization under fault model 2.
Target gainMedian (%)Minimum error (%)Maximum error (%)150.283%−4.841%4.988%80.154%−4.853%4.966%2−0.762%−4.964%4.995%In all the experiments, the GA is capable of reaching the target gain, with errors for all the gains in the range [−4.964%, 4.995%]. The lowest BW obtained for all the simulated conditions is4.13E+6 rad/s above the required.


#### 5.3.3. Fault Model 3

Figure11 shows the results using Fault Model 3 in PGA3. We report only these results because this PGA presents the worst performance in the fault injection process. Each point in the figure is a solution to the problem when a Model 3 fault is injected in the PGA.Figure 11
Gain relative error versus bandwidth. Operation under fault model 3 in PGA3.From the simulation results (Table6), it is observed that the GA is able to reach the target gain with errors for all the gains in the range [−4.996%, 4.996%] and BW greater than 4.01E+06 rad/s. The comparison of these results with the ones obtained under fault-free conditions (Table 3) shows that the faulty system presents in the worst case an increase of 0.293% in the error range for gain 8. The median of the relative error decreases for the gains 2 and 15, while for gain 8 it increases.Table 6
Gain relative error characterization under fault model 3.
Target gainMedian (%)Minimum error (%)Maximum error (%)15−0.052%−4.996%4.996%8−0.062%−4.982%4.803%2−0.508%−4.897%4.903%


#### 5.3.4. Fault Model 4

Figure12 shows the deviation-fault simulation results for the PGA2, which presents the worst performance. The figure depicts the relative errors in the target gains versus the BW obtained for each deviation value in the gain. From the simulation results, it is observed that the GA is able to reach the target gain with errors for all the gains in the range [−4.943%, 4.571%] and BW greater than 4.08E+06 rad/s. In the worst case, the obtained BW is above the required.Figure 12
Gain relative error versus bandwidth. Operation under fault model 4 in PGA2.Table7 summarizes the effects of Model 4. Comparing the relative error under fault-free (Table 3) and fault conditions, the faulty system presents a diminution for all the gains, despite the presence of relatively high deviation faults. The median of the relative error increases for gain 15 while for the other two gains decreases, suggesting that the error distribution changes between the normal and faulty operation.Table 7
Gain relative error characterization under Fault Model 4.
Target GainMedian (%)Minimum error (%)Maximum error (%)150.718%−4.809%4.561%8−1.580%−4.792%4.571%2−0.946%−4.943%4.393%


## 5.1. Test Results

The test routine is written in assembly language. The experiments were performed in a CY3210-PSoCEval1 board that provides the necessary hardware to evaluate the PSoC1 device CY8C29466-24PXI. In order to simplify the experiments, we implement in the device a communication module to the host computer through an RS-232 serial interface.Table2 shows the mean values of the resistor array for the test conditions depicted in Table 2. In the table, the values are very close to the ideal reported in Table 1 and the highest errors are for test conditions 1 to 4. The relative error to the nominal value is always below 5%, with the exception of PGA3, test condition 1. In this case, the error rises to 7%.Table 2
Resistor-matrix test results.
Test conditionPGA1 Vref (VDD units)PGA2 Vref (VDD units)PGA3 Vref (VDD units)PGA4 Vref (VDD units)10.01990.02150.02230.021120.04070.04230.04300.041130.06150.06340.06410.060440.12380.12580.12670.125550.18610.18820.18930.186760.24880.25080.25200.249970.31140.31320.31430.312580.37410.37560.37670.374290.43660.43800.43910.4373100.49920.50060.50120.4993110.56170.56330.56360.5634120.62390.62540.62570.6253130.68670.68800.68810.6860140.74920.75040.75050.7504150.81200.81310.81290.8120160.87450.87520.87500.8745170.93700.93760.93740.9376181.00001.00001.00001.0000


## 5.2. Fault Free Operation

We propose three different values for the target gain(Atar): 2, 8, and 15 with the aim of evaluating the ability of GA for finding an acceptable solution in different scenarios. We set the value of the minimum −3 dB BW (ε) in 4E+06 rad/s (636 kHz), also for demonstration purposes.As GA is a stochastic process, its results could change according to the statistical distribution of the initial population. In order to see how the results could be affected by the setting of the initial population, we change the seed of its random generation and consider that all gains are available for running the algorithm. The distribution of the obtained results can be observed in the dispersion diagram depicted in Figure8. In the figure, each point is a solution to the optimization problem changing the seed and shows the relative error of the gain versus the bandwidth for the three target gains. From the figure, the three target gains present relative errors in the range [−4.982%, 4.831%]. The lowest BW obtained for all the evaluated gains is 4.06E+6 rad/s, above the required.Figure 8
Gain relative error versus bandwidth. Fault-free operation.Table3 shows a characterization of the relative error for the three target gain values. We adopt the median as a measurement of central tendency because the data distribution is not normal. We also present the maximum and minimum as a measurement of dispersion. The table shows that the relative error for all the cases is below the required (±5%). Additionally, the median of the relative error is close to zero for all target gains.Table 3
Gain relative error characterization under fault-free condition.
Target gainMedian (%)Minimum error (%)Maximum error (%)150.244%−4.932%4.767%8−0.307%−4.847%4.686%20.070%−4.982%4.831%


## 5.3. Operation under Fault Condition

### 5.3.1. Fault Model 1

For space reasons, we only report in Figure9 the fault injection results corresponding to PGA1 which presents the worst results. The figure shows the relative error of the overall gain versus the bandwidth for the three target gains. Each point is a solution to the optimization problem under Model 1 fault. The figure shows that the error in the gain is near ±5% for all the target gains, while the bandwidth is above the required.Figure 9
Gain relative error versus bandwidth. Operation under fault model 1 injected in PGA1.Table4 summarizes the fault injection results for the four PGAs. In this table, we grouped the results by gain value. Comparing the gain error results obtained from fault-free operation (Table 3) and faulty operation (Table 4), the faulty system presents in the worst case an increase of 0.405% in the error range for gain 8. The median of the relative error decreases for the three gains, suggesting that the error distribution changes between the fault-free and faulty operation. In all the experiments, the GA is capable of reaching the target gain, with errors for all the gains in the range [−4.996%, 4.963%]. The lowest BW obtained for all the simulated conditions is 4.03E+6 rad/s above the required.Table 4
Gain relative error characterization under fault model 1.
Target gainMedian (%)Minimum error (%)Maximum error (%)15−0.458%−4.918%4.746%8−0.825%−4.975%4.963%2−0.401%−4.996%4.841%


### 5.3.2. Fault Model 2

Figure10 shows the results using Fault Model 2 in PGA3. We report only these results because this PGA presents the worst performance in the fault injection process. Each point in the figure is a solution to the problem when a Model 2 fault is injected in the PGA.Figure 10
Gain relative error versus bandwidth. Operation under fault model 2 in PGA3.Table5 summarizes the fault simulation results using Model 2. Comparing the gain error results obtained from fault-free operation (Table 3) and fault operation (Table 5), the faulty system presents in the worst case an increase of 0.286% in the error range for gain 8. The median of the relative error increases for the gains 8 and 15, while for gain 2 it decreases.Table 5
Gain relative error characterization under fault model 2.
Target gainMedian (%)Minimum error (%)Maximum error (%)150.283%−4.841%4.988%80.154%−4.853%4.966%2−0.762%−4.964%4.995%In all the experiments, the GA is capable of reaching the target gain, with errors for all the gains in the range [−4.964%, 4.995%]. The lowest BW obtained for all the simulated conditions is4.13E+6 rad/s above the required.


### 5.3.3. Fault Model 3

Figure11 shows the results using Fault Model 3 in PGA3. We report only these results because this PGA presents the worst performance in the fault injection process. Each point in the figure is a solution to the problem when a Model 3 fault is injected in the PGA.Figure 11
Gain relative error versus bandwidth. Operation under fault model 3 in PGA3.From the simulation results (Table6), it is observed that the GA is able to reach the target gain with errors for all the gains in the range [−4.996%, 4.996%] and BW greater than 4.01E+06 rad/s. The comparison of these results with the ones obtained under fault-free conditions (Table 3) shows that the faulty system presents in the worst case an increase of 0.293% in the error range for gain 8. The median of the relative error decreases for the gains 2 and 15, while for gain 8 it increases.Table 6
Gain relative error characterization under fault model 3.
Target gainMedian (%)Minimum error (%)Maximum error (%)15−0.052%−4.996%4.996%8−0.062%−4.982%4.803%2−0.508%−4.897%4.903%


### 5.3.4. Fault Model 4

Figure12 shows the deviation-fault simulation results for the PGA2, which presents the worst performance. The figure depicts the relative errors in the target gains versus the BW obtained for each deviation value in the gain. From the simulation results, it is observed that the GA is able to reach the target gain with errors for all the gains in the range [−4.943%, 4.571%] and BW greater than 4.08E+06 rad/s. In the worst case, the obtained BW is above the required.Figure 12
Gain relative error versus bandwidth. Operation under fault model 4 in PGA2.Table7 summarizes the effects of Model 4. Comparing the relative error under fault-free (Table 3) and fault conditions, the faulty system presents a diminution for all the gains, despite the presence of relatively high deviation faults. The median of the relative error increases for gain 15 while for the other two gains decreases, suggesting that the error distribution changes between the normal and faulty operation.Table 7
Gain relative error characterization under Fault Model 4.
Target GainMedian (%)Minimum error (%)Maximum error (%)150.718%−4.809%4.561%8−1.580%−4.792%4.571%2−0.946%−4.943%4.393%


## 5.3.1. Fault Model 1

For space reasons, we only report in Figure9 the fault injection results corresponding to PGA1 which presents the worst results. The figure shows the relative error of the overall gain versus the bandwidth for the three target gains. Each point is a solution to the optimization problem under Model 1 fault. The figure shows that the error in the gain is near ±5% for all the target gains, while the bandwidth is above the required.Figure 9
Gain relative error versus bandwidth. Operation under fault model 1 injected in PGA1.Table4 summarizes the fault injection results for the four PGAs. In this table, we grouped the results by gain value. Comparing the gain error results obtained from fault-free operation (Table 3) and faulty operation (Table 4), the faulty system presents in the worst case an increase of 0.405% in the error range for gain 8. The median of the relative error decreases for the three gains, suggesting that the error distribution changes between the fault-free and faulty operation. In all the experiments, the GA is capable of reaching the target gain, with errors for all the gains in the range [−4.996%, 4.963%]. The lowest BW obtained for all the simulated conditions is 4.03E+6 rad/s above the required.Table 4
Gain relative error characterization under fault model 1.
Target gainMedian (%)Minimum error (%)Maximum error (%)15−0.458%−4.918%4.746%8−0.825%−4.975%4.963%2−0.401%−4.996%4.841%


## 5.3.2. Fault Model 2

Figure10 shows the results using Fault Model 2 in PGA3. We report only these results because this PGA presents the worst performance in the fault injection process. Each point in the figure is a solution to the problem when a Model 2 fault is injected in the PGA.Figure 10
Gain relative error versus bandwidth. Operation under fault model 2 in PGA3.Table5 summarizes the fault simulation results using Model 2. Comparing the gain error results obtained from fault-free operation (Table 3) and fault operation (Table 5), the faulty system presents in the worst case an increase of 0.286% in the error range for gain 8. The median of the relative error increases for the gains 8 and 15, while for gain 2 it decreases.Table 5
Gain relative error characterization under fault model 2.
Target gainMedian (%)Minimum error (%)Maximum error (%)150.283%−4.841%4.988%80.154%−4.853%4.966%2−0.762%−4.964%4.995%In all the experiments, the GA is capable of reaching the target gain, with errors for all the gains in the range [−4.964%, 4.995%]. The lowest BW obtained for all the simulated conditions is4.13E+6 rad/s above the required.


## 5.3.3. Fault Model 3

Figure11 shows the results using Fault Model 3 in PGA3. We report only these results because this PGA presents the worst performance in the fault injection process. Each point in the figure is a solution to the problem when a Model 3 fault is injected in the PGA.Figure 11
Gain relative error versus bandwidth. Operation under fault model 3 in PGA3.From the simulation results (Table6), it is observed that the GA is able to reach the target gain with errors for all the gains in the range [−4.996%, 4.996%] and BW greater than 4.01E+06 rad/s. The comparison of these results with the ones obtained under fault-free conditions (Table 3) shows that the faulty system presents in the worst case an increase of 0.293% in the error range for gain 8. The median of the relative error decreases for the gains 2 and 15, while for gain 8 it increases.Table 6
Gain relative error characterization under fault model 3.
Target gainMedian (%)Minimum error (%)Maximum error (%)15−0.052%−4.996%4.996%8−0.062%−4.982%4.803%2−0.508%−4.897%4.903%


## 5.3.4. Fault Model 4

Figure12 shows the deviation-fault simulation results for the PGA2, which presents the worst performance. The figure depicts the relative errors in the target gains versus the BW obtained for each deviation value in the gain. From the simulation results, it is observed that the GA is able to reach the target gain with errors for all the gains in the range [−4.943%, 4.571%] and BW greater than 4.08E+06 rad/s. In the worst case, the obtained BW is above the required.Figure 12
Gain relative error versus bandwidth. Operation under fault model 4 in PGA2.Table7 summarizes the effects of Model 4. Comparing the relative error under fault-free (Table 3) and fault conditions, the faulty system presents a diminution for all the gains, despite the presence of relatively high deviation faults. The median of the relative error increases for gain 15 while for the other two gains decreases, suggesting that the error distribution changes between the normal and faulty operation.Table 7
Gain relative error characterization under Fault Model 4.
Target GainMedian (%)Minimum error (%)Maximum error (%)150.718%−4.809%4.561%8−1.580%−4.792%4.571%2−0.946%−4.943%4.393%


## 6. Comparison with Exhaustive Search Method

For a better characterization of the efficiency of the GA, we compare it with exhaustive search method (ESM). This method consists of systematically enumerating all possible candidates for the solution and checking whether each candidate satisfies the problem statement [30].We performed the comparison using two parameters: number of objective function evaluations (OFE) and runtime. GA and ESM are both implemented in Matlab.GA performs at most 750 OFE (population sizex number of generations), while ESM performs 1.679.616 OFE (6) to find the best solution for fault-free, Model 3, and Model 4 fault operation. For Model 1, this method performs 1.632.960 evaluations and for Model 2 it performs 1.586.304 evaluations.Table8 summarizes the performance comparison between ESM and GA. The runtime of GA shown is the maximum value of the runtime obtained in the worst case (gain 8 for Fault Model 3 and gain 15 for the other fault models). In the worst condition (Model 1), GA is 482.81 times faster than ESM. In the best condition (fault-free), GA is 641.40 times faster than ESM.Table 8
Performance comparison between ESM and GA.
MethodMax Runtime (sec)Fault-free conditionModel 1Model 2Model 3Model 4GA0.31640.4040,3950.3880.371ESM202.94195.20192.57202.94202.94Regarding BW, we compare the one obtained by the GA against that obtained by using ESM, under normal and faulty operation. The bandwidths for the GA are close to the optimal ones obtained with the ESM, with the median between 17.19% and 31.23% lower. However, AG obtains these values in considerably less time and with fewer objective function evaluations.


## 7. Conclusions

We presented an adaptive amplifier implemented with programmable gain amplifiers in a PSoC device that is part of a sensor node in a wireless sensor network. The system is composed by an SBST scheme that checks all the available gains in the amplifier and by a GA for reconfiguring the chip resources that runs on a host computer. The GA presented is robust for the types of faults addressed in our evaluation. The fault simulation results show that the system maintains the overall gain and the bandwidth within specifications, despite the presence of catastrophic and deviation faults. In addition, its runtime is considerably lower than exhaustive search method.



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*Source: 762927-2012-06-13.xml*