# Companding Realizations of the Nonlinear Energy Operator

Authors: Andreas-Christos Demartinos; Chrysostomos Kasimis; Costas Laoudias; Costas Psychalinos
Journal: ISRN Biomedical Engineering
 (2013)

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## Abstract

Realizations of the nonlinear energy operator (NEO), using the concept of companding filtering, are introduced and compared in this work. For this purpose, the Log-Domain and Sinh-Domain filtering techniques have been followed. Both topologies are constructed from differentiator and multiplier blocks which have been realized through the utilization of nonlinear transconductor cells. Both of the proposed topologies offer the capability of ultra-low voltage operation, thanks to the employment of MOS transistors in the weak inversion. Considering a single power supply voltage of 0.5 V, the behavior of the proposed NEO realizations has been simulated using the Analog Design Environment of the Cadence software and the design kit of the TSMC 130 nm process. Comparison results show that the Sinh-Domain realization offers a more power efficient design than that offered by the Log-Domain realization.


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## Body

## 1. Introduction

Owing to its efficiency for estimating the instantaneous product of amplitude and frequency of a signal, the NEO is a very powerful tool for handling biomedical signals. A number of NEO realizations have been already introduced in the literature [1–4]. The topology in [1] operates in a supply voltage 1.8 V, while a dual ±1.65 V supply voltage scheme has been used in [3]. A power supply voltage 2 V has been utilized in the topology in [4], while the topology in [2] operates at 0.6 V.Conventional linear Operational Transconductance Amplifiers (OTAs) have been utilized for realizing the topologies in [1, 3]. A drawback of these realizations is the restriction for handling signals with relatively low amplitude, so that the conditions for small-signal operation are fulfilled, and the transconductance parameter of the corresponding MOS transistors can be employed. The same restriction is also valid for the realization in [2], where the small-signal transconductance parameter of current mirror has been utilized for realizing the required resistors.Companding realizations do not suffer from the aforementioned limitation, due to the fact that an externally linear system could be constructed from nonlinear active blocks. Thus, there is an absence of employment of linearization techniques and/or small-signal operation conditions for achieving the linear operation of the whole system. Therefore, for given amplitude of the input current, the bias current could be chosen smaller than that in the case of the conventional linear systems [5–13]. In the Log-Domain implementation in [4], the required nonlinear transconductors have been constructed from translinear loops formed by bipolar transistors operated in forward active region.In biomedical applications, an ultra-low power voltage environment is present, and also the power dissipation of the system should be as low as possible for increasing the life of the implanted device. Thus, MOS transistors operating in the weak inversion must be employed for the realization of the nonlinear transconductors.Realizations of the NEO, employing the concept of Log-Domain and Sinh-Domain filtering, are introduced in this work. The employment of MOS transistors operating in subthreshold region offers the advantage of operation in a single power supply voltage equal to 0.5 V, which is the minimum among the already known NEO realizations. The paper is organized as follows: the realization of the NEO using the concept of Log-Domain filtering is given in Section2, while the corresponding Sinh-Domain realization is given in Section 3. The evaluation and comparison of the performance of the proposed systems are given in Section 4, by employing the Analog Design Environment of the Cadence software and the design kit provided by the TSMC 130 nm process.


## 2. Log-Domain Realization of NEO

The Functional Block Diagram (FBD) of the NEO realization using the conventional filtering is given in Figure1(a), where the operation described by (1) is performed to the input signal iin(t) as follows:
(1)iout(t)=(ddtiin(t))2-iin(t)·(d2dt2iin(t)).
Following the concept of companding filtering, the input current should be converted into a compressed voltage which will be processed by the nonlinear intermediate blocks. The produced nonlinear compressed output voltages are converted into linear currents in order to preserve the linear operation of the whole system. This is demonstrated in the FBD in Figure 1(b). According to this FBD, the building blocks required for realizing the NEO are compression and expansion blocks, differentiators, and four-quadrant multipliers in order to realize the required quadrature and product terms.FBD of the NEO realization using the (a) conventional and (b) companding filtering.
(a)
(b)In the case that the concept of the Log-Domain filtering will be followed for realizing the required differentiators, the conversion of the input current (iin) into a compressed voltage (υ^in) and the expansion of the intermediate output voltages into linear currents (io1–io4) will be described by the following set of complementary operators:
(2)υ^in=LOG(iin)≡VDC+nVT·ln(iin+IoIo),(3)ioi=EXP(υ^oi)≡I0·e(υ^oi-VDC)/nVT-Ioi=1,…,4.
In (2)-(3), Io and VDC are a dc current and a dc voltage, respectively, VT is the thermal voltage, and n is the subthreshold slope factor of a MOS transistor. Also, variables with a circumflex represent compressed voltages [7–9, 13].Using (3), the expression in (1) could be alternatively rewritten as in (4)
(4)EXP[υ^out(t)]=(ddtEXP[υ^in(t)])2-EXP[υ^in(t)]·(d2dt2EXP[υ^in(t)]).
The realization of Log-Domain circuits is performed by employing nonlinear transconductors denoted as E+ and E− cells [8, 9, 13]. The expression of the output current for both of them is given by the formula in (5) as
(5)iout=I0·e(υ^in+-υ^in-)/nVT,
where υ^in+and υ^in- are the voltages at their noninverting and inverting inputs, respectively.Using (3) and (5), it is easily derived that the compression of the input current is achieved by an appropriately configured E+ cell, as it is depicted in Figure 2.Realization of (a) compression and (b) expansion in the Log-Domain.
(a)
(b)The topology of a Log-Domain differentiator is presented in Figure3. The current that flows through the capacitor C^ is given by the expression
(6)iC=C^dυ^out1dt=I0·e(υ^in-υ^out1)/nVT-Io.
Multiplying both terms in (6) with the factor e(υ^out1-VDC)/nVT and employing the definition of the EXP operator in (3), it is derived, after some algebraic manipulation, that
(7)EXP(υ^out1)EXP(υ^in)=iout1iin=1τ^s+1,
where τ^=C^nVT/Io is the realized time constant.Figure 3
Topology of differentiator in the Log-Domain.The output current of the E+ cell at the top of the Figure3 is equal to iin; taking into account that the output current is given by the expression iout=iin-iout1 and employing (7), the realized transfer function is
(8)H(s)=ioutiin=τ^sτ^s+1.
According to (8), the topology in Figure 3 approximates a differentiator within a frequency range where the condition f≪Io/2πC^nVT is valid.The topology of the proposed current-mode multiplier, constructed from only E cells, is depicted in Figure4. This is based on the concept introduced in [14], where conventional OTAs have been employed. The upper leftmost E+ cell is configured in a way that the input current i1 is converted into a compressed voltage given by (2). The same operation is performed by the E+ cell which is handling the other input current i2. The output current of the multiplier could be expressed as
(9)iout=iout1-(i1+i2+Io).
Using (2) and (5), the intermediate output current iout1 is expressed as
(10)iout1=(i1+Io)·(i2+Io)Io.
Substituting (10) into (9), the derived expression for the output current is
(11)iout=i1·i2Io.
Owing to the fact that either input currents could be positive or negative, the topology in Figure 4 is a four-quadrant multiplier. In addition, the following restriction should be fulfilled: i1+Io>0 and i2+Io>0. These are imposed from the fact that the currents i1+Io and i2+Io are bias currents for E cells, and therefore, the topology in Figure 4 is a class-A current-mode multiplier.Figure 4
Four-quadrant multiplier using E cells.


## 3. Sinh-Domain Realization of NEO

Another possible realization of the NEO is through the utilization of the concept of Sinh-Domain filtering. Compared with their Log-Domain counterparts, Sinh-Domain filters offer better compression for both positive and negative values of the input current and an intrinsic class-AB operation. Thus, they can handle currents with a level greater than that of the bias current. On the other hand, the circuit complexity is increased in comparison with that needed in the case of Log-Domain filters [6, 10, 11].The realization of the required compression and expansion operations denoted in the FBD in Figure1(b) will be performed by employing appropriate transconductor cells which are mentioned in the literature as S cells. Their output current is given by the expression in (12) as
(12)iout=2Io·sinh(υ^in+-υ^in-nVT),
where υ^in+ and υ^in- are the voltages at their noninverting and inverting inputs, respectively, [6, 11].In addition, the set of complementary operators introduced given in (13)-(14) will be used as follows:
(13)υ^=SINH-1(i)≡VDC+nVT·sinh-1(i2Io),(14)i=SINH(υ^)≡2I0·sinh(υ∧-VDCnVT).
Using (12)–(14), the topologies that perform the compression and expansion in the Sinh-Domain are depicted in Figure 5 [6, 11].Realization of (a) compression and (b) expansion in the Sinh-Domain.
(a)
(b)A Sinh-Domain first-order high-pass filter is demonstrated in Figure6. The current that flows through the capacitor C^ is given by the expression
(15)iC=C^dυ^out1dt=2Io·2Io·sinh(υ^in-VDC)/nVT-2Io·sinh(υ^out1-VDC)/nVT2Io·cosh(υ^out1-VDC)/nVT
Using the definition of the sinh operator in (14) and performing some algebraic manipulation, it is derived from (15) that
(16)SINH(υ^out1)SINH(υ^in)=iout1iin=1τ^s+1,
where τ^=C^nVT/2Io is the realized time constant.Figure 6
Topology of differentiator in the Sinh-Domain.The output current is established asiout=iin-iout1, and employing (16), the transfer function in (8) is also realized by the topology in Figure 6. Thus, it approximates a differentiator within a frequency range where the condition f≪Io/πC^nVT is valid.A four-quadrant class-AB current multiplier topology, constructed from S cells, has been already proposed in [15, 16]. In order to facilitate the reading, the topology is recalled in Figure 7, while the expression for the output current is given by (11).Figure 7
Four-quadrant multiplier using S cells.


## 4. Simulation and Comparison Results

### 4.1. Simulation and Results

The behavior of both Log-Domain and Sinh-Domain differentiators has been evaluated through the Analog Design Environment of the Cadence software. MOS transistor parameters provided by the TSMC 130 nm CMOS technology have been used in simulations. The employed E+ and S cells are given in Figures8 and 9, respectively. It should be mentioned at this point that the required E− cells could be realized through the utilization of an extra current mirror at the output of a E+ cell, while the required replicas of the hyperbolic sine outputs of the S cells could be implemented using multiple output current mirrors.Figure 8
Circuitry of an E+ cell.Figure 9
Circuitry of an S cell.With respect to the Log-Domain realization, the power supply voltages were chosen to beVDD=0.5 V and VDC=250 mV, while the dc current Io was equal to 0.6 nA. The aspect ratios (i.e., the ratio of the width over the length of the channel of a MOS transistor) of Mp1-Mp2, Mp3-Mp4, and Mp5 in Figure 8 were chosen to be 1 μm/1 μm, 1 μm/10 μm, and 1 μm/6 μm, respectively. The choice of these values has been performed in order to keep the operation of MOS transistors in the subthreshold region. In other words, the following conditions should be fulfilled: VGS-VTH<-100 mV, where VGS is the gate-source voltage and VTH is the threshold voltage, and VDS>100 mV, where VDS is the drain-source voltage. The obtained gain and phase responses of the Log-Domain differentiator are given in Figure 10. Taking into account that the frequency range of Action Potentials (APs) is within 100 Hz and 10 kHz [1], it is readily obtained from the provided plots that the topology fulfils the aforementioned requirement.Figure 10
Gain and phase responses of the topology in Figure3.The behavior of the Sinh-Domain differentiator has been evaluated through the utilization of the following bias scheme:VDD=0.5 V and VDC=250 mV, Io=0.3 nA. The choice of the halved bias current, with regards to the Log-Domain realization, has been done in order to achieve the same impedance level for both realizations, and this is achieved from the fact that a time constant in the Log-Domain is given by the formula: τ^=C^nVT/Io, while the corresponding formula in the Sinh-Domain is τ^=C^nVT/2Io. The aspect ratios of Mp1-Mp8, Mp9-Mp10, and Mn1-Mn8 were chosen to be 1 μm/1 μm, 1 μm/6 μm, and 1 μm/10 μm, respectively. The simulated frequency responses of the Sinh-Domain differentiator are given in Figure 11. According to the provided plots, the gain response is linear with the frequency, while the phase response is almost constant at 90° within the frequency range of APs (100 Hz–10 kHz).Figure 11
Gain and phase responses of the topology in Figure6.The time-domain behaviour of the proposed NEO realizations will be studied through the consideration of an EEG stimulus [17]. In the case of Log-Domain realization, the maximum amplitude of the EEG signal that could be successfully handled (i.e., recognition of the APs) is equal to 0.15 nA, and the corresponding input and output waveforms are depicted in Figure 12.Figure 12
Input and output waveforms of the proposed Log-Domain NEO realization.Due to the class-AB nature of the Sinh-Domain realization, an EEG signal with maximum amplitude about 0.45 nA could be handled, and the simulated waveforms are provided in Figure13. The total power dissipation of the whole Log-Domain system was 31.4 nW, while the corresponding value for the Sinh-Domain system was 63.4 nW.Figure 13
Input and output waveforms of the proposed Sinh-Domain NEO realization.


### 4.2. Discussion

According to the provided simulation results, the Sinh-Domain realization is capable of handling a maximum signal with amplitude three times the amplitude of the signal that could be successfully handled by the corresponding Log-Domain realization. On the other hand, the dc power dissipation of the Sinh-Domain realization is doubled compared to that of the Log-Domain realization. Therefore, the Sinh-Domain realization is attractive in terms of power efficiency, and this is originated from its inherent class-AB operation. On the other hand, the Log-Domain realization offers a simpler circuitry than that of its Sinh-Domain counterpart.With regards to the power supply voltage environment, the topologies in [1–4] operate in supply voltages 1.8V, ±1.65V, 2V, and 0.6V, respectively. Both the companding realizations operate in a 0.5 V supply voltage which is the minimum among the topologies under consideration. This is originated from their companding nature, where the intermediate voltages are compressed versions of the voltages of corresponding conventional topologies.The corresponding values of power dissipation were 170 nW for the topology in [1], 2.7 μW for the topology in [3], 7.2 μW for the topology in [4], and 76.2 nw for the topology in [2]. Thus, the proposed configurations offer the minimum required power dissipation compared with the corresponding already proposed schemes. Taking also into account that they are capable of operating in a 0.5 V power supply voltage, which is the minimum among the topologies under consideration, it is concluded that they simultaneously offer the benefits of both reduced power consumption and power supply voltage. On the other hand, the proposed topologies have the drawback of the increased circuit complexity, and this is originated from the inherent nonlinear internal nature, where there is absence of any small-signal (linear) approximation.


## 4.1. Simulation and Results

The behavior of both Log-Domain and Sinh-Domain differentiators has been evaluated through the Analog Design Environment of the Cadence software. MOS transistor parameters provided by the TSMC 130 nm CMOS technology have been used in simulations. The employed E+ and S cells are given in Figures8 and 9, respectively. It should be mentioned at this point that the required E− cells could be realized through the utilization of an extra current mirror at the output of a E+ cell, while the required replicas of the hyperbolic sine outputs of the S cells could be implemented using multiple output current mirrors.Figure 8
Circuitry of an E+ cell.Figure 9
Circuitry of an S cell.With respect to the Log-Domain realization, the power supply voltages were chosen to beVDD=0.5 V and VDC=250 mV, while the dc current Io was equal to 0.6 nA. The aspect ratios (i.e., the ratio of the width over the length of the channel of a MOS transistor) of Mp1-Mp2, Mp3-Mp4, and Mp5 in Figure 8 were chosen to be 1 μm/1 μm, 1 μm/10 μm, and 1 μm/6 μm, respectively. The choice of these values has been performed in order to keep the operation of MOS transistors in the subthreshold region. In other words, the following conditions should be fulfilled: VGS-VTH<-100 mV, where VGS is the gate-source voltage and VTH is the threshold voltage, and VDS>100 mV, where VDS is the drain-source voltage. The obtained gain and phase responses of the Log-Domain differentiator are given in Figure 10. Taking into account that the frequency range of Action Potentials (APs) is within 100 Hz and 10 kHz [1], it is readily obtained from the provided plots that the topology fulfils the aforementioned requirement.Figure 10
Gain and phase responses of the topology in Figure3.The behavior of the Sinh-Domain differentiator has been evaluated through the utilization of the following bias scheme:VDD=0.5 V and VDC=250 mV, Io=0.3 nA. The choice of the halved bias current, with regards to the Log-Domain realization, has been done in order to achieve the same impedance level for both realizations, and this is achieved from the fact that a time constant in the Log-Domain is given by the formula: τ^=C^nVT/Io, while the corresponding formula in the Sinh-Domain is τ^=C^nVT/2Io. The aspect ratios of Mp1-Mp8, Mp9-Mp10, and Mn1-Mn8 were chosen to be 1 μm/1 μm, 1 μm/6 μm, and 1 μm/10 μm, respectively. The simulated frequency responses of the Sinh-Domain differentiator are given in Figure 11. According to the provided plots, the gain response is linear with the frequency, while the phase response is almost constant at 90° within the frequency range of APs (100 Hz–10 kHz).Figure 11
Gain and phase responses of the topology in Figure6.The time-domain behaviour of the proposed NEO realizations will be studied through the consideration of an EEG stimulus [17]. In the case of Log-Domain realization, the maximum amplitude of the EEG signal that could be successfully handled (i.e., recognition of the APs) is equal to 0.15 nA, and the corresponding input and output waveforms are depicted in Figure 12.Figure 12
Input and output waveforms of the proposed Log-Domain NEO realization.Due to the class-AB nature of the Sinh-Domain realization, an EEG signal with maximum amplitude about 0.45 nA could be handled, and the simulated waveforms are provided in Figure13. The total power dissipation of the whole Log-Domain system was 31.4 nW, while the corresponding value for the Sinh-Domain system was 63.4 nW.Figure 13
Input and output waveforms of the proposed Sinh-Domain NEO realization.


## 4.2. Discussion

According to the provided simulation results, the Sinh-Domain realization is capable of handling a maximum signal with amplitude three times the amplitude of the signal that could be successfully handled by the corresponding Log-Domain realization. On the other hand, the dc power dissipation of the Sinh-Domain realization is doubled compared to that of the Log-Domain realization. Therefore, the Sinh-Domain realization is attractive in terms of power efficiency, and this is originated from its inherent class-AB operation. On the other hand, the Log-Domain realization offers a simpler circuitry than that of its Sinh-Domain counterpart.With regards to the power supply voltage environment, the topologies in [1–4] operate in supply voltages 1.8V, ±1.65V, 2V, and 0.6V, respectively. Both the companding realizations operate in a 0.5 V supply voltage which is the minimum among the topologies under consideration. This is originated from their companding nature, where the intermediate voltages are compressed versions of the voltages of corresponding conventional topologies.The corresponding values of power dissipation were 170 nW for the topology in [1], 2.7 μW for the topology in [3], 7.2 μW for the topology in [4], and 76.2 nw for the topology in [2]. Thus, the proposed configurations offer the minimum required power dissipation compared with the corresponding already proposed schemes. Taking also into account that they are capable of operating in a 0.5 V power supply voltage, which is the minimum among the topologies under consideration, it is concluded that they simultaneously offer the benefits of both reduced power consumption and power supply voltage. On the other hand, the proposed topologies have the drawback of the increased circuit complexity, and this is originated from the inherent nonlinear internal nature, where there is absence of any small-signal (linear) approximation.


## 5. Conclusion

The proposed companding realizations of NEO are attractive candidates for realizing high-performance biomedical signal processing systems. This is originated from the performed comparison results, where it was proved that they are capable of operating in an ultra-low voltage environment and simultaneously have the minimum power dissipation among the corresponding already published topologies. The Sinh-Domain realization offers more power efficiency compared to its Log-Domain counterpart.



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*Source: 750290-2013-06-20.xml*