# Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic

Authors: Shipra Upadhyay; R. K. Nagaria; R. A. Mishra
Journal: VLSI Design
 (2013)

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## Abstract

Efficiency of adiabatic logic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. The lesser will be these losses circuit will be more energy efficient. In this paper, a new approach is presented for minimizing power consumption in quasistatic energy recovery logic (QSERL) circuit which involves optimization by removing the nonadiabatic losses completely by replacing the diodes with MOSFETs whose gates are controlled by power clocks. Proposed circuit inherits the advantages of quasistatic ERL (QSERL) family but is with improved power efficiency and driving ability. In order to demonstrate workability of the newly developed circuit, a 4 × 4 bit array multiplier circuit has been designed. A mathematical expression to calculate energy dissipation in proposed inverter is developed. Performance of the proposed logic (improved quasistatic energy recovery logic (IQSERL)) is analyzed and compared with CMOS and reported QSERL in their representative inverters and multipliers in VIRTUOSO SPECTRE simulator of Cadence in 0.18μm UMC technology. In our proposed (IQSERL) inverter the power efficiency has been improved to almost 20% up to 50 MHz and 300 fF external load capacitance in comparison to CMOS and QSERL circuits.


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## Body

## 1. Introduction

With increased scaling in CMOS technology, modern designs are capable of performing very high speed computations as the complexity, and the number of devices on a given IC is no longer an issue. Much of the research efforts in the recent decades have been dedicated to improving the speed of digital systems. Thus, high speed computation has become an expected norm for average users. Higher switching activities lead to higher power consumption. Many methodologies have been proposed so far [1] which intended to reduce power consumption, among them adiabatic logic technique [2] is promising alternative. Concept of adiabatic logic circuits is generated from the adiabatic process which is a thermodynamically reversible process that is operated slowly, so that total energy dissipation tends towards zero. Energy dissipated in a circuit depends on how fast the circuit switches or charges and discharges which means that it depends on the approach taken to design the circuit. When the rate of charging will be lower, less amount of energy is drawn from the source. Adiabatic circuits also have another mechanism for energy saving [3] that is based on recovering the energy stored in nodal capacitances. The quality factor Q of any adiabatic process is also known as degree of adiabaticity or adiabatic gain, and it is the ratio between the total energy delivered and the energy that gets dissipated in the whole process.There are three types of losses in adiabatic circuits, nonadiabatic losses, adiabatic losses, and leakage losses. The last two losses are associated with fully adiabatic circuits, whereas nonadiabatic losses are related to quasi/semiadiabatic circuits. Nonadiabatic losses are proportional to the voltage drop across the terminals of a resistive switch, when it is on [4, 5]. Leakage losses are proportional to the clock period and are negligible in comparison to the other two. The third one is adiabatic loss which depends on current or voltage drawn from the source, load capacitance, charging path resistance, and transition time [6, 7]. It should be noted that nonadiabatic losses can be eliminated completely by using reversible logic, but adiabatic and leakage losses cannot be avoided. There are several remedies to reduce adiabatic losses. First one is by extending the charging time T. The second way is constant current charging [8] for capacitance through a resistance in a given time. Third method is by lowering the charging path resistance, which was not the case in CMOS.Another important mechanism for energy saving in adiabatic circuits is to recover the adiabatic losses. The energy which was stored in load capacitance during charging can be recovered again with a dissipation that depends inversely on charging time. This is possible if the current direction is reversed, and load capacitance is discharged through the same path. The difference between the nodal energy and dissipated part is recovered from the current source and can be used in next charging. For this purpose, the DC power source of CMOS is replaced by ramp, sinusoidal, trapezoidal, and triangular and so forth the power clock signals in adiabatic circuits [9, 10]. Initially most adiabatic circuits were based on multiphase power clocks. But they were not suitable for high speed design, because of their complex controlling mechanism. Comparatively single phase adiabatic circuits are suitable for operating at high speeds with high energy efficiency, because they have simple clock controlling mechanism. Considering these facts, we propose IQSERL circuit which inherits all the advantages of recent reported circuits [9] with additional improvement in energy efficiency and speed.The paper is organized into five sections as follows. Section1 deals with the introduction part. Section 2 describes the limitations of QSERL circuits. In Section 3, we have discussed the proposed energy recovery logic (IQSERL) inverter circuit. The result and performance analysis of IQSERL based inverter and 4×4 bit array multiplier circuit are carried out in Section 4. Section 5 summarizes the conclusion.


## 2. Limitations in QSERL Circuits

Many adiabatic circuits proposed over years based on multiphase clocking scheme suffer from several drawbacks like complex circuit structure, poor driving ability, inrobustness, and large delay. The trapezoidal power clock based efficient charge recovery logic (ECRL) [11], clocked adiabatic logic circuits (CAL) [12], and positive feedback adiabatic logic (PFAL) circuits [13] suffer from floating output nodes, problem of current leakage, and charge sharing. This limits their use at high frequency, and thus operating speed is slow.Glitch free cascadable adiabatic logic (GFCAL) [10] circuit is based on triangular power clock which have lowest power dissipation among all, but their main drawback is very large delay and hence very slow operating speed. Sinusoidal power clock based adiabatic circuits are QSERL, complementary energy path adiabatic logic (CEPAL) [14], and two-phase adiabatic static CMOS logic (2PASCL) circuits [15]. The 2PASCL has comparatively simple circuit structure and lower switching activity, but there exists a small amplitude ripple on both high and low logic voltage levels which was caused by the on/off resistances of switching transistors and load capacitances. Thus output amplitude is degraded.QSERL circuit has hold phase due to this dynamic switching, and thus energy dissipation is reduced, but output is floating which is not desirable. CEPAL circuit attempts to improve and remove the drawback of QSERL circuit by removing the hold phase. Its throughput is also better than QSERL and is twice. But it is comparatively less power efficient than QSERL. The significant delay derived from QSERL based combinational logic is very important thing to be discussed and remedied. Referring to Figure1, an eight-stage inverter chain has been simulated with 50 MHz input rate and 100 MHz power clock rate, and it has significant amount of delay at each stage which causes completely incorrect output logics at the seventh and eighth-stage. It makes QSERL slightly disadvantageous.(a) QSERL eight-stage inverter chain, (b) transient response.
(a)
(b)


## 3. Improved Quasistatic Energy Recovery Logic (IQSERL) Circuits

### 3.1. Circuit Description

The schematic of IQSERL circuit is shown in Figure2. It is composed of a P network, an N network, two complementary split-level sinusoidal power clocks (VΦ and Vϕ-), charging pMOS transistor (P1), and discharging nMOS transistor (N1) whose gates are controlled by the power clocks. Both the power clocks are 180 degree out of phase. The voltage level of the clock VΦ exceeds that of inverted clock Vϕ- by a factor of Vdd/2, this will minimize the voltage difference between the electrodes and consequently power dissipation. Split-level sinusoidal clock charges/discharges the load capacitances comparatively slowler than the other adiabatic power clocks.Figure 2
Proposed IQSERL circuit.This is desirable because efficiency of adiabatic logic circuits depends upon how slowly the load capacitance is charged/discharged. The peak-to-peak voltage of these power clocksVΦ and Vϕ- is 0.9 V:
(1)VΦ=Vdd4sin(ωt+θ)+34Vdd,Vϕ-=-Vdd4sin(ωt+θ)+14Vdd.The pMOS (P1) in the pull up network and nMOS (N1) in the pull down network are used to replace the diode used in QSERL circuit for the charging and discharging, respectively. Power clock (VΦ) controls the switching on and off of transistors (N1), and Vϕ- controls the switching on and off of transistors (P1). These power clocks can be generated and realized practically by a simple LC resonant oscillator as shown in [15]. The nonadiabatic source of power dissipation in reported QSERL circuits in charging and discharging path occurs at the (MOSFET) diodes due to the threshold voltage drop, whereas in our proposed circuit, power dissipation is due to the adiabatic losses of on resistance of channels of MOSFET transistors.As we discussed in previous sections that in irreversible circuits the nonadiabatic losses cannot be eliminated, whereas adiabatic losses can be reduced by several remedies, thus the drain to source voltage drop of charging/discharging transistors and hence power dissipation may be reduced by slowing down the charging/discharging time. However, because of irreversibility [16], it cannot be removed completely.


### 3.2. Circuit Operation

Based on the supply clock structure, operation of IQSERL circuit is divided into two phases, evaluation and hold. In evaluation phaseVΦ goes up, while Vϕ- goes down; however, in hold phase VΦ goes down, and Vϕ- goes up.In evaluation phase, when the output logic is low and P network is on,CL is charged through pMOS (P1) and P network resulting in the high logic at output. When output logic is high and N network is on, discharging and recycling of charges to the power clock (Vϕ-) via nMOS (N1) and N network occur, resulting in the low output logic.In hold phase,VΦ swings down, and Vϕ- swings up, and when they reaches below the threshold voltage, both the MOSFETs P1 and N1 turn off; thus no transitions occur at the output. Due to the hold phase, dynamic switching and hence energy dissipation are reduced.


### 3.3. Estimation of Energy Dissipation

The energy dissipated in the proposed inverter (in Figure2, P network is replaced by pMOS and N network by nMOS) is calculated for a triangular supply voltage (for simplicity) as shown in Figure 3 using the approximate expression.Figure 3
Energy dissipation estimation in IQSERL inverter.


#### 3.3.1. Energy Dissipation in Proposed Inverter during Charging

When P network is on (pMOS), and asVΦ increases to VDD and Vϕ-  decreases to 0 V or vice versa, load capacitor is charged through charging transistors P1 and pMOS:
(2)VΦ=3VDD4+2VDDTt,when0≤t≤T8=3VDD4-2VDDTt,whenT8≤t≤3T8=-VDD4+2VDDTt,when3T8≤t≤T2.
Let us assume that the charging path resistance is R1 and discharging path resistance is R2. One has
(3)i(t)=2VDDTC-VDD4TC(8-3TR1C)e-t/R1C0≤t≤T8i(t)=VDD4TR1[-8R1C+(3T-8R1C)e-t/R1C]T8≤t≤t1i(t)=VDD4TR1[(4T-8R1C)et/R1C-8R1C]t1≤t≤3T8i(t)=VDD4TR1[8R1C+(T-8R1C)et/R1C]3T8≤t≤t2i(t)=VDD4R1T[8R1C-(8R1C+T)e-t/R1C]t2≤t≤T2,ggggggggt1=TR1C3T-8R1Cggggggggt2=3T(T-4R1C)4(8R1C-T).Total energy dissipation in chargingEch=∫i2R1dt=E1ch+E2ch+E3ch+E4ch+E5ch,
(4)E1ch=VDD2C2R116T2×[8T-(32R1C+9T22R1C-24T)(e-T/4R1C-1)+(128R1C-48T)(e-T/8R1C-1)],(5)E2ch=VDD216T2R1×[64R12C2(-T8+t1)-R1C2(64R12C2+9T2-48R1CT)(e-2t1/R1C-e-T/4R1C)+16R12C2(3T-8R1C)(e-t1/R1C-e-T/8R1C)],(6)E3ch=VDD216T2R1×[64R12C2(3T8-t1)-R1C2(64R12C2+9T2-48R1CT)(e3T/4R1C-e2t1/R1C)-16R12C2(3T-8R1C)(e3T/8R1C-et1/R1C)],(7)E4ch=VDD216T2R1×[64R12C2(t2-3T8)-R1C2(64R12C2+T2-16R1CT)(e2t2/R1C-e3T/4R1C)-16R12C2(T-8R1C)(et2/R1C-e3T/8R1C)],(8)E5ch=VDD216T2R1×[64R12C2(T2-t2)-R1C2(64R12C2+T2+16R1CT)(e-T/R1C-e2t2/R1C)+16R12C2(T+8R1C)(e-T/2R1C-e-t2/R1C)].


#### 3.3.2. Energy Dissipation in the Inverter during Discharging

When the N network is on (i.e., nMOS) and P network is off, charging of the capacitor is prevented, and the load capacitor discharges through the discharging transistors N1 and nMOS. Consider(9)Vϕ-=5VDD4-2VDDTt,whenT2≤t≤5T8=2VDDTt-5VDD4,when5T8≤t≤7T8=9VDD4-2VDDTt,when7T8≤t≤T,(10)i(t)=VDD4R2T[-8R2C+(8R2C-5T)]et/R2CT2≤t≤5T8=VDD4R2T[8R2C+(5T-8R2C)]et/R2C5T8≤t≤t3=VDD4R2T[8R2C-(5T+8R2C)]e-t/R2Ct3≤t≤7T8=VDD4R2T[-8R2C+(9T+8R2C)]e-t/R2C7T8≤t≤t4=VDD4R2T[-8R2C+(8R2C-9T)]et/R2Ct4≤t≤T,(11)t3=-25T2R2C+2.5T3-8R22C2T(8R2C-T)(8R2C+5T),t4=(10T-16R2C)t3+7T2+36R2CT2(9T-8R2C).Total energy dissipation in discharging,Edisch=∫i2R2dt=E1disch+   E2disch+E3disch+E4disch+E5disch,
(12)E1disch=VDD216T2R2×[64R22C2(5T8-T2)+R2C2(64R22C2+25T2-80R2CT)(e5T/4R2C-eT/R2C)-16R22C2(8R2C-5T)(e5T/R2C-eT/2R2C)],E2disch=VDD216T2R2×[64R22C2(t3-5T8)+R2C2(64R22C2+25T2-80R2CT)(e2t3/R2C-e5T/4R2C)+16R22C2(5T-8R2C)(et3/R2C-e5T/8R2C)],E3disch=VDD216T2R2×[64R22C2(7T8-t3)+R2C2(64R22C2+25T2-80R2CT)(e-7T/4R2C-e-2t3/R2C)+16R22C2(8R2C+5T)(e-7T/8R2C-e-t3/R2C)],E4disch=VDD216T2R2×[64R22C2(t4-7T8)+R2C2(64R22C2+81T2+144R2CT)(e-2t4/R2C-e-7T/4R2C)-16R22C2(8R2C+9T)(e-t4/R2C-e-7T/8R2C)],(13)E5disch=VDD216T2R2×[64R22C2(T-t4)+R2C2(64R22C2+81T2-144R2CT)(e2T/R2C-e2t4/R2C)-16R22C2(8R2C-9T)(eT/R2C-et4/R2C)].


## 3.1. Circuit Description

The schematic of IQSERL circuit is shown in Figure2. It is composed of a P network, an N network, two complementary split-level sinusoidal power clocks (VΦ and Vϕ-), charging pMOS transistor (P1), and discharging nMOS transistor (N1) whose gates are controlled by the power clocks. Both the power clocks are 180 degree out of phase. The voltage level of the clock VΦ exceeds that of inverted clock Vϕ- by a factor of Vdd/2, this will minimize the voltage difference between the electrodes and consequently power dissipation. Split-level sinusoidal clock charges/discharges the load capacitances comparatively slowler than the other adiabatic power clocks.Figure 2
Proposed IQSERL circuit.This is desirable because efficiency of adiabatic logic circuits depends upon how slowly the load capacitance is charged/discharged. The peak-to-peak voltage of these power clocksVΦ and Vϕ- is 0.9 V:
(1)VΦ=Vdd4sin(ωt+θ)+34Vdd,Vϕ-=-Vdd4sin(ωt+θ)+14Vdd.The pMOS (P1) in the pull up network and nMOS (N1) in the pull down network are used to replace the diode used in QSERL circuit for the charging and discharging, respectively. Power clock (VΦ) controls the switching on and off of transistors (N1), and Vϕ- controls the switching on and off of transistors (P1). These power clocks can be generated and realized practically by a simple LC resonant oscillator as shown in [15]. The nonadiabatic source of power dissipation in reported QSERL circuits in charging and discharging path occurs at the (MOSFET) diodes due to the threshold voltage drop, whereas in our proposed circuit, power dissipation is due to the adiabatic losses of on resistance of channels of MOSFET transistors.As we discussed in previous sections that in irreversible circuits the nonadiabatic losses cannot be eliminated, whereas adiabatic losses can be reduced by several remedies, thus the drain to source voltage drop of charging/discharging transistors and hence power dissipation may be reduced by slowing down the charging/discharging time. However, because of irreversibility [16], it cannot be removed completely.


## 3.2. Circuit Operation

Based on the supply clock structure, operation of IQSERL circuit is divided into two phases, evaluation and hold. In evaluation phaseVΦ goes up, while Vϕ- goes down; however, in hold phase VΦ goes down, and Vϕ- goes up.In evaluation phase, when the output logic is low and P network is on,CL is charged through pMOS (P1) and P network resulting in the high logic at output. When output logic is high and N network is on, discharging and recycling of charges to the power clock (Vϕ-) via nMOS (N1) and N network occur, resulting in the low output logic.In hold phase,VΦ swings down, and Vϕ- swings up, and when they reaches below the threshold voltage, both the MOSFETs P1 and N1 turn off; thus no transitions occur at the output. Due to the hold phase, dynamic switching and hence energy dissipation are reduced.


## 3.3. Estimation of Energy Dissipation

The energy dissipated in the proposed inverter (in Figure2, P network is replaced by pMOS and N network by nMOS) is calculated for a triangular supply voltage (for simplicity) as shown in Figure 3 using the approximate expression.Figure 3
Energy dissipation estimation in IQSERL inverter.


### 3.3.1. Energy Dissipation in Proposed Inverter during Charging

When P network is on (pMOS), and asVΦ increases to VDD and Vϕ-  decreases to 0 V or vice versa, load capacitor is charged through charging transistors P1 and pMOS:
(2)VΦ=3VDD4+2VDDTt,when0≤t≤T8=3VDD4-2VDDTt,whenT8≤t≤3T8=-VDD4+2VDDTt,when3T8≤t≤T2.
Let us assume that the charging path resistance is R1 and discharging path resistance is R2. One has
(3)i(t)=2VDDTC-VDD4TC(8-3TR1C)e-t/R1C0≤t≤T8i(t)=VDD4TR1[-8R1C+(3T-8R1C)e-t/R1C]T8≤t≤t1i(t)=VDD4TR1[(4T-8R1C)et/R1C-8R1C]t1≤t≤3T8i(t)=VDD4TR1[8R1C+(T-8R1C)et/R1C]3T8≤t≤t2i(t)=VDD4R1T[8R1C-(8R1C+T)e-t/R1C]t2≤t≤T2,ggggggggt1=TR1C3T-8R1Cggggggggt2=3T(T-4R1C)4(8R1C-T).Total energy dissipation in chargingEch=∫i2R1dt=E1ch+E2ch+E3ch+E4ch+E5ch,
(4)E1ch=VDD2C2R116T2×[8T-(32R1C+9T22R1C-24T)(e-T/4R1C-1)+(128R1C-48T)(e-T/8R1C-1)],(5)E2ch=VDD216T2R1×[64R12C2(-T8+t1)-R1C2(64R12C2+9T2-48R1CT)(e-2t1/R1C-e-T/4R1C)+16R12C2(3T-8R1C)(e-t1/R1C-e-T/8R1C)],(6)E3ch=VDD216T2R1×[64R12C2(3T8-t1)-R1C2(64R12C2+9T2-48R1CT)(e3T/4R1C-e2t1/R1C)-16R12C2(3T-8R1C)(e3T/8R1C-et1/R1C)],(7)E4ch=VDD216T2R1×[64R12C2(t2-3T8)-R1C2(64R12C2+T2-16R1CT)(e2t2/R1C-e3T/4R1C)-16R12C2(T-8R1C)(et2/R1C-e3T/8R1C)],(8)E5ch=VDD216T2R1×[64R12C2(T2-t2)-R1C2(64R12C2+T2+16R1CT)(e-T/R1C-e2t2/R1C)+16R12C2(T+8R1C)(e-T/2R1C-e-t2/R1C)].


### 3.3.2. Energy Dissipation in the Inverter during Discharging

When the N network is on (i.e., nMOS) and P network is off, charging of the capacitor is prevented, and the load capacitor discharges through the discharging transistors N1 and nMOS. Consider(9)Vϕ-=5VDD4-2VDDTt,whenT2≤t≤5T8=2VDDTt-5VDD4,when5T8≤t≤7T8=9VDD4-2VDDTt,when7T8≤t≤T,(10)i(t)=VDD4R2T[-8R2C+(8R2C-5T)]et/R2CT2≤t≤5T8=VDD4R2T[8R2C+(5T-8R2C)]et/R2C5T8≤t≤t3=VDD4R2T[8R2C-(5T+8R2C)]e-t/R2Ct3≤t≤7T8=VDD4R2T[-8R2C+(9T+8R2C)]e-t/R2C7T8≤t≤t4=VDD4R2T[-8R2C+(8R2C-9T)]et/R2Ct4≤t≤T,(11)t3=-25T2R2C+2.5T3-8R22C2T(8R2C-T)(8R2C+5T),t4=(10T-16R2C)t3+7T2+36R2CT2(9T-8R2C).Total energy dissipation in discharging,Edisch=∫i2R2dt=E1disch+   E2disch+E3disch+E4disch+E5disch,
(12)E1disch=VDD216T2R2×[64R22C2(5T8-T2)+R2C2(64R22C2+25T2-80R2CT)(e5T/4R2C-eT/R2C)-16R22C2(8R2C-5T)(e5T/R2C-eT/2R2C)],E2disch=VDD216T2R2×[64R22C2(t3-5T8)+R2C2(64R22C2+25T2-80R2CT)(e2t3/R2C-e5T/4R2C)+16R22C2(5T-8R2C)(et3/R2C-e5T/8R2C)],E3disch=VDD216T2R2×[64R22C2(7T8-t3)+R2C2(64R22C2+25T2-80R2CT)(e-7T/4R2C-e-2t3/R2C)+16R22C2(8R2C+5T)(e-7T/8R2C-e-t3/R2C)],E4disch=VDD216T2R2×[64R22C2(t4-7T8)+R2C2(64R22C2+81T2+144R2CT)(e-2t4/R2C-e-7T/4R2C)-16R22C2(8R2C+9T)(e-t4/R2C-e-7T/8R2C)],(13)E5disch=VDD216T2R2×[64R22C2(T-t4)+R2C2(64R22C2+81T2-144R2CT)(e2T/R2C-e2t4/R2C)-16R22C2(8R2C-9T)(eT/R2C-et4/R2C)].


## 3.3.1. Energy Dissipation in Proposed Inverter during Charging

When P network is on (pMOS), and asVΦ increases to VDD and Vϕ-  decreases to 0 V or vice versa, load capacitor is charged through charging transistors P1 and pMOS:
(2)VΦ=3VDD4+2VDDTt,when0≤t≤T8=3VDD4-2VDDTt,whenT8≤t≤3T8=-VDD4+2VDDTt,when3T8≤t≤T2.
Let us assume that the charging path resistance is R1 and discharging path resistance is R2. One has
(3)i(t)=2VDDTC-VDD4TC(8-3TR1C)e-t/R1C0≤t≤T8i(t)=VDD4TR1[-8R1C+(3T-8R1C)e-t/R1C]T8≤t≤t1i(t)=VDD4TR1[(4T-8R1C)et/R1C-8R1C]t1≤t≤3T8i(t)=VDD4TR1[8R1C+(T-8R1C)et/R1C]3T8≤t≤t2i(t)=VDD4R1T[8R1C-(8R1C+T)e-t/R1C]t2≤t≤T2,ggggggggt1=TR1C3T-8R1Cggggggggt2=3T(T-4R1C)4(8R1C-T).Total energy dissipation in chargingEch=∫i2R1dt=E1ch+E2ch+E3ch+E4ch+E5ch,
(4)E1ch=VDD2C2R116T2×[8T-(32R1C+9T22R1C-24T)(e-T/4R1C-1)+(128R1C-48T)(e-T/8R1C-1)],(5)E2ch=VDD216T2R1×[64R12C2(-T8+t1)-R1C2(64R12C2+9T2-48R1CT)(e-2t1/R1C-e-T/4R1C)+16R12C2(3T-8R1C)(e-t1/R1C-e-T/8R1C)],(6)E3ch=VDD216T2R1×[64R12C2(3T8-t1)-R1C2(64R12C2+9T2-48R1CT)(e3T/4R1C-e2t1/R1C)-16R12C2(3T-8R1C)(e3T/8R1C-et1/R1C)],(7)E4ch=VDD216T2R1×[64R12C2(t2-3T8)-R1C2(64R12C2+T2-16R1CT)(e2t2/R1C-e3T/4R1C)-16R12C2(T-8R1C)(et2/R1C-e3T/8R1C)],(8)E5ch=VDD216T2R1×[64R12C2(T2-t2)-R1C2(64R12C2+T2+16R1CT)(e-T/R1C-e2t2/R1C)+16R12C2(T+8R1C)(e-T/2R1C-e-t2/R1C)].


## 3.3.2. Energy Dissipation in the Inverter during Discharging

When the N network is on (i.e., nMOS) and P network is off, charging of the capacitor is prevented, and the load capacitor discharges through the discharging transistors N1 and nMOS. Consider(9)Vϕ-=5VDD4-2VDDTt,whenT2≤t≤5T8=2VDDTt-5VDD4,when5T8≤t≤7T8=9VDD4-2VDDTt,when7T8≤t≤T,(10)i(t)=VDD4R2T[-8R2C+(8R2C-5T)]et/R2CT2≤t≤5T8=VDD4R2T[8R2C+(5T-8R2C)]et/R2C5T8≤t≤t3=VDD4R2T[8R2C-(5T+8R2C)]e-t/R2Ct3≤t≤7T8=VDD4R2T[-8R2C+(9T+8R2C)]e-t/R2C7T8≤t≤t4=VDD4R2T[-8R2C+(8R2C-9T)]et/R2Ct4≤t≤T,(11)t3=-25T2R2C+2.5T3-8R22C2T(8R2C-T)(8R2C+5T),t4=(10T-16R2C)t3+7T2+36R2CT2(9T-8R2C).Total energy dissipation in discharging,Edisch=∫i2R2dt=E1disch+   E2disch+E3disch+E4disch+E5disch,
(12)E1disch=VDD216T2R2×[64R22C2(5T8-T2)+R2C2(64R22C2+25T2-80R2CT)(e5T/4R2C-eT/R2C)-16R22C2(8R2C-5T)(e5T/R2C-eT/2R2C)],E2disch=VDD216T2R2×[64R22C2(t3-5T8)+R2C2(64R22C2+25T2-80R2CT)(e2t3/R2C-e5T/4R2C)+16R22C2(5T-8R2C)(et3/R2C-e5T/8R2C)],E3disch=VDD216T2R2×[64R22C2(7T8-t3)+R2C2(64R22C2+25T2-80R2CT)(e-7T/4R2C-e-2t3/R2C)+16R22C2(8R2C+5T)(e-7T/8R2C-e-t3/R2C)],E4disch=VDD216T2R2×[64R22C2(t4-7T8)+R2C2(64R22C2+81T2+144R2CT)(e-2t4/R2C-e-7T/4R2C)-16R22C2(8R2C+9T)(e-t4/R2C-e-7T/8R2C)],(13)E5disch=VDD216T2R2×[64R22C2(T-t4)+R2C2(64R22C2+81T2-144R2CT)(e2T/R2C-e2t4/R2C)-16R22C2(8R2C-9T)(eT/R2C-et4/R2C)].


## 4. Results and Analysis

### 4.1. Proposed IQSERL Inverter Circuit

#### 4.1.1. Driving Ability

Figure4 shows the driving ability of the proposed logic in eight-stage inverter chain. We tested the delay at each stage of the inverter chain (with simulation parameters as W/L of pMOS 540/180 nm and nMOS 240/180 nm and 50 MHz input rate and 200 MHz power clock rate) one by one and observed that delay is significantly reduced in comparison to the QSERL circuits as was observed in Figure 1(b). It may be observed that due to the very small amount of delay at each stage, correct output logics are observed throughout the eight-stages. Our attempt for delay reduction over QSERL is to ensure that the supply voltage is split-level sinusoidal instead of sinusoidal power clock, since it was observed that split-level power clock based circuits have lesser delay than the others [15]. Further by sizing of charging pMOS transistors (width is increased, i.e., 540 nm) and by increasing the frequency ratio (power clock frequency to the input frequency 4 times), delay is reduced.(a) IQSERL eight-stage inverter chain, (b) transient response.
(a)
(b)


#### 4.1.2. Power Efficiency with Frequency

The input and supply frequencies varied simultaneously (in IQSERL supply frequency is four times the input frequency for better performance) from 0.01 MHz to 50 MHz, and load capacitance at each stage is set to 10 fF as shown in Figure5. As frequency increases, power dissipation of all three types of circuits increases, whereas proposed inverter has lesser power dissipation at each frequency in comparison to CMOS and QSERL. However, after 33.3 MHz output levels of QSERL become incorrect and cause lesser power dissipation than the proposed IQSERL. We may also note that QSERL has larger power dissipation than CMOS at some points which again prove the poor performance of QSRL. Also a continuous decrease in percentage power saving of IQSERL inverter over CMOS and QSERL with frequency is observed.Figure 5
Simulation results of the performance comparison of 8-inverter chain  with frequency.From the Table1 we observe that the proposed inverter has lowest power dissipation, lower delay than QSERL, and comparable delay to the CMOS at all the observed frequencies.Table 1
Comparison of power, delay, and PDP of 8-inverter chain in 10 cycles of charging and discharging.
Power dissipation (μW)
Frequency (MHz)
0.01
0.1
1
10
20
33.3
50
CMOS
0.09
0.12
0.40
3.32
6.6
10.9
16.4
QSERL
0.02
0.10
0.66
3.69
6.2
8.95
11.7
IQSERL
0.01
0.02
0.13
1.92
4.8
8.92
15.2
Delay (ns)
CMOS
55.4
3.15
1.37
1.52
1.5
1.48
1.47
QSERL
4210
522
64.4
9.38
5.69
4.10
3.29
IQSERL
1.92
6.24
4.53
2.56
2.07
1.8
1.68
PDP (fJ)
CMOS
4.99
0.38
0.55
5.05
9.9
16.1
24.1
QSERL
84.2
52.2
42.5
34.6
35.3
36.7
38.5
IQSERL
0.02
0.12
0.59
4.92
9.94
16.0
25.5


#### 4.1.3. Power Efficiency with Load Capacitance

We tested the inverters by adding extra capacitive load at the output node one by one from 10 fF to 300 fF as shown in Figure6. Clock and data rate are kept fixed at 4 MHz and 1 MHz, respectively. When load capacitance is increased, power dissipation of all three types of circuits increases correspondingly; however, our proposed inverter has good power efficiency than CMOS and QSERL at each point. When load capacitance increases, percentage power saving decreases and power saving of IQSERL to the QSERL is more than the power saving to the CMOS in lower frequency range.Figure 6
Simulation results of the performance comparison of 8-inverter chain  with load capacitance.Table2 shows that the proposed IQSERL inverter has lowest power dissipation, lower delay than QSERL, and comparable delay to the CMOS at all the observed load capacitances.Table 2
Comparison of power, delay, and PDP of 8-inverter chain with load capacitance atfi=1 MHz.
Power dissipation (μW)
Capacitance (fF)
20
30
50
100
200
250
300
CMOS
0.66
0.93
1.4
2.7
5.4
6.8
8.1
QSERL
0.99
1.3
1.8
3.1
5.31
6.31
7.2
IQSERL
0.23
0.35
0.61
1.3
3.34
4.4
5.7
Delay (ns)
CMOS
2.7
4.1
6.6
12.8
24.9
30.9
36.9
QSERL
69.4
73.1
79.2
91
109
117
124
IQSERL
7.18
9.5
13.5
21.8
35
40.8
46.3
PDP (fJ)
CMOS
1.78
3.8
9.24
34.5
134
210
298
QSERL
68.7
95
142
282
578
738
892
IQSERL
1.65
3.32
8.24
28.3
116
179
263


#### 4.1.4. Layout of Proposed IQSERL Inverter

The layout of proposed inverter has been drawn as shown in Figure7. The chip area of IQSERL inverter has been characterized (20.7 μm2) to be higher than the CMOS (14.54 μm2) due to the extra nMOS and pMOS in discharging/charging paths. Thus the proposed logic requiring fewer transistors is comparable to the CMOS.Figure 7
Layout of proposed IQSERL inverter circuit.


### 4.2. Proposed IQSERL Multiplier Circuit

In this section a4×4 bit IQSERL array multiplier is designed and simulated to show the usefulness of the new logic family for large circuits. It consists of 16 IQSERL AND gates, 4 IQSERL half adders, 8 IQSERL full adders, and 8 IQSERL D flip flops as shown in Figure 8(a). D flip flops are used to store the 8-bit signals. The simulation is done with simulation parameters as W/L of pMOS 540/180 nm and nMOS 240/180 nm, and input rate was kept four times the power clock rate (in IQSERL). From Figure 8(b), the simulated input and output timing waveforms verify the 4-bit multiplier logic.(a) IQSERL4×4 bit array multiplier circuit, (b) transient response.
(a)
(b)Simulation results for the proposed IQSERL multiplier are compared with CMOS and recently reported (QSERL) multipliers [17–19] using the same logic implementation, equal switching probability of inputs, and the same simulation condition. The input and supply frequencies are varied simultaneously (keeping the supply frequency four times the input frequency in IQSERL) from 0.1 MHz to 20 MHz, and corresponding power dissipations for the multipliers have been measured. IQSERL multiplier has significant power saving to the CMOS and QSERL multipliers. As frequency increases, the power saving of IQSERL to the CMOS and QSERL multipliers decreases as shown in Figure 9. At 0.05 MHz 98% saving in power as compared to the QSERL multiplier and 94% power saving to the CMOS multiplier are obtained. At 20 MHz the power saving to the QSERL multiplier is 7% whereas to the CMOS multiplier is 11%. As frequency goes higher, the resistive dissipation (which is proportional to RC/T) increases, so power saving is less.Figure 9
Simulation results of the performance comparison of4×4 bit array multipliers with frequency.After a certain high frequency (here 20 MHz), incorrect output logics are obtained, so for larger complex circuits, our IQSERL circuit is limited in some high frequency range. Also from the layout of proposed IQSERL inverter circuit as in Figure7, we can generalize it for multiplier circuit also that, for a given performance, devices can be smaller for a CMOS multiplier circuit than the IQSERL multiplier circuit. Hence the proposed IQSERL circuit is more suitable for some specific applications where speed and area are not critical. Since a 4×4 bit array multiplier is a large complex circuit, so number of transistors on a chip (transistor count) is also an important parameter to be discussed. In Table 3, we have given the comparative study of transistor count of our proposed multiplier with others.Table 3
Comparison of transistor counts of 4 × 4 bit array multiplier.
Design style
Number of transistors
CMOS
744
QSERL
1432
IQSERL
1056It may be observed that the proposed IQSERL logic requiring fewer transistors is comparable to the CMOS, whereas IQSERL logic have less transistor counts than QSERL. Thus it needs less complex layout design and can be used to build larger circuits on a single chip.


## 4.1. Proposed IQSERL Inverter Circuit

### 4.1.1. Driving Ability

Figure4 shows the driving ability of the proposed logic in eight-stage inverter chain. We tested the delay at each stage of the inverter chain (with simulation parameters as W/L of pMOS 540/180 nm and nMOS 240/180 nm and 50 MHz input rate and 200 MHz power clock rate) one by one and observed that delay is significantly reduced in comparison to the QSERL circuits as was observed in Figure 1(b). It may be observed that due to the very small amount of delay at each stage, correct output logics are observed throughout the eight-stages. Our attempt for delay reduction over QSERL is to ensure that the supply voltage is split-level sinusoidal instead of sinusoidal power clock, since it was observed that split-level power clock based circuits have lesser delay than the others [15]. Further by sizing of charging pMOS transistors (width is increased, i.e., 540 nm) and by increasing the frequency ratio (power clock frequency to the input frequency 4 times), delay is reduced.(a) IQSERL eight-stage inverter chain, (b) transient response.
(a)
(b)


### 4.1.2. Power Efficiency with Frequency

The input and supply frequencies varied simultaneously (in IQSERL supply frequency is four times the input frequency for better performance) from 0.01 MHz to 50 MHz, and load capacitance at each stage is set to 10 fF as shown in Figure5. As frequency increases, power dissipation of all three types of circuits increases, whereas proposed inverter has lesser power dissipation at each frequency in comparison to CMOS and QSERL. However, after 33.3 MHz output levels of QSERL become incorrect and cause lesser power dissipation than the proposed IQSERL. We may also note that QSERL has larger power dissipation than CMOS at some points which again prove the poor performance of QSRL. Also a continuous decrease in percentage power saving of IQSERL inverter over CMOS and QSERL with frequency is observed.Figure 5
Simulation results of the performance comparison of 8-inverter chain  with frequency.From the Table1 we observe that the proposed inverter has lowest power dissipation, lower delay than QSERL, and comparable delay to the CMOS at all the observed frequencies.Table 1
Comparison of power, delay, and PDP of 8-inverter chain in 10 cycles of charging and discharging.
Power dissipation (μW)
Frequency (MHz)
0.01
0.1
1
10
20
33.3
50
CMOS
0.09
0.12
0.40
3.32
6.6
10.9
16.4
QSERL
0.02
0.10
0.66
3.69
6.2
8.95
11.7
IQSERL
0.01
0.02
0.13
1.92
4.8
8.92
15.2
Delay (ns)
CMOS
55.4
3.15
1.37
1.52
1.5
1.48
1.47
QSERL
4210
522
64.4
9.38
5.69
4.10
3.29
IQSERL
1.92
6.24
4.53
2.56
2.07
1.8
1.68
PDP (fJ)
CMOS
4.99
0.38
0.55
5.05
9.9
16.1
24.1
QSERL
84.2
52.2
42.5
34.6
35.3
36.7
38.5
IQSERL
0.02
0.12
0.59
4.92
9.94
16.0
25.5


### 4.1.3. Power Efficiency with Load Capacitance

We tested the inverters by adding extra capacitive load at the output node one by one from 10 fF to 300 fF as shown in Figure6. Clock and data rate are kept fixed at 4 MHz and 1 MHz, respectively. When load capacitance is increased, power dissipation of all three types of circuits increases correspondingly; however, our proposed inverter has good power efficiency than CMOS and QSERL at each point. When load capacitance increases, percentage power saving decreases and power saving of IQSERL to the QSERL is more than the power saving to the CMOS in lower frequency range.Figure 6
Simulation results of the performance comparison of 8-inverter chain  with load capacitance.Table2 shows that the proposed IQSERL inverter has lowest power dissipation, lower delay than QSERL, and comparable delay to the CMOS at all the observed load capacitances.Table 2
Comparison of power, delay, and PDP of 8-inverter chain with load capacitance atfi=1 MHz.
Power dissipation (μW)
Capacitance (fF)
20
30
50
100
200
250
300
CMOS
0.66
0.93
1.4
2.7
5.4
6.8
8.1
QSERL
0.99
1.3
1.8
3.1
5.31
6.31
7.2
IQSERL
0.23
0.35
0.61
1.3
3.34
4.4
5.7
Delay (ns)
CMOS
2.7
4.1
6.6
12.8
24.9
30.9
36.9
QSERL
69.4
73.1
79.2
91
109
117
124
IQSERL
7.18
9.5
13.5
21.8
35
40.8
46.3
PDP (fJ)
CMOS
1.78
3.8
9.24
34.5
134
210
298
QSERL
68.7
95
142
282
578
738
892
IQSERL
1.65
3.32
8.24
28.3
116
179
263


### 4.1.4. Layout of Proposed IQSERL Inverter

The layout of proposed inverter has been drawn as shown in Figure7. The chip area of IQSERL inverter has been characterized (20.7 μm2) to be higher than the CMOS (14.54 μm2) due to the extra nMOS and pMOS in discharging/charging paths. Thus the proposed logic requiring fewer transistors is comparable to the CMOS.Figure 7
Layout of proposed IQSERL inverter circuit.


## 4.1.1. Driving Ability

Figure4 shows the driving ability of the proposed logic in eight-stage inverter chain. We tested the delay at each stage of the inverter chain (with simulation parameters as W/L of pMOS 540/180 nm and nMOS 240/180 nm and 50 MHz input rate and 200 MHz power clock rate) one by one and observed that delay is significantly reduced in comparison to the QSERL circuits as was observed in Figure 1(b). It may be observed that due to the very small amount of delay at each stage, correct output logics are observed throughout the eight-stages. Our attempt for delay reduction over QSERL is to ensure that the supply voltage is split-level sinusoidal instead of sinusoidal power clock, since it was observed that split-level power clock based circuits have lesser delay than the others [15]. Further by sizing of charging pMOS transistors (width is increased, i.e., 540 nm) and by increasing the frequency ratio (power clock frequency to the input frequency 4 times), delay is reduced.(a) IQSERL eight-stage inverter chain, (b) transient response.
(a)
(b)


## 4.1.2. Power Efficiency with Frequency

The input and supply frequencies varied simultaneously (in IQSERL supply frequency is four times the input frequency for better performance) from 0.01 MHz to 50 MHz, and load capacitance at each stage is set to 10 fF as shown in Figure5. As frequency increases, power dissipation of all three types of circuits increases, whereas proposed inverter has lesser power dissipation at each frequency in comparison to CMOS and QSERL. However, after 33.3 MHz output levels of QSERL become incorrect and cause lesser power dissipation than the proposed IQSERL. We may also note that QSERL has larger power dissipation than CMOS at some points which again prove the poor performance of QSRL. Also a continuous decrease in percentage power saving of IQSERL inverter over CMOS and QSERL with frequency is observed.Figure 5
Simulation results of the performance comparison of 8-inverter chain  with frequency.From the Table1 we observe that the proposed inverter has lowest power dissipation, lower delay than QSERL, and comparable delay to the CMOS at all the observed frequencies.Table 1
Comparison of power, delay, and PDP of 8-inverter chain in 10 cycles of charging and discharging.
Power dissipation (μW)
Frequency (MHz)
0.01
0.1
1
10
20
33.3
50
CMOS
0.09
0.12
0.40
3.32
6.6
10.9
16.4
QSERL
0.02
0.10
0.66
3.69
6.2
8.95
11.7
IQSERL
0.01
0.02
0.13
1.92
4.8
8.92
15.2
Delay (ns)
CMOS
55.4
3.15
1.37
1.52
1.5
1.48
1.47
QSERL
4210
522
64.4
9.38
5.69
4.10
3.29
IQSERL
1.92
6.24
4.53
2.56
2.07
1.8
1.68
PDP (fJ)
CMOS
4.99
0.38
0.55
5.05
9.9
16.1
24.1
QSERL
84.2
52.2
42.5
34.6
35.3
36.7
38.5
IQSERL
0.02
0.12
0.59
4.92
9.94
16.0
25.5


## 4.1.3. Power Efficiency with Load Capacitance

We tested the inverters by adding extra capacitive load at the output node one by one from 10 fF to 300 fF as shown in Figure6. Clock and data rate are kept fixed at 4 MHz and 1 MHz, respectively. When load capacitance is increased, power dissipation of all three types of circuits increases correspondingly; however, our proposed inverter has good power efficiency than CMOS and QSERL at each point. When load capacitance increases, percentage power saving decreases and power saving of IQSERL to the QSERL is more than the power saving to the CMOS in lower frequency range.Figure 6
Simulation results of the performance comparison of 8-inverter chain  with load capacitance.Table2 shows that the proposed IQSERL inverter has lowest power dissipation, lower delay than QSERL, and comparable delay to the CMOS at all the observed load capacitances.Table 2
Comparison of power, delay, and PDP of 8-inverter chain with load capacitance atfi=1 MHz.
Power dissipation (μW)
Capacitance (fF)
20
30
50
100
200
250
300
CMOS
0.66
0.93
1.4
2.7
5.4
6.8
8.1
QSERL
0.99
1.3
1.8
3.1
5.31
6.31
7.2
IQSERL
0.23
0.35
0.61
1.3
3.34
4.4
5.7
Delay (ns)
CMOS
2.7
4.1
6.6
12.8
24.9
30.9
36.9
QSERL
69.4
73.1
79.2
91
109
117
124
IQSERL
7.18
9.5
13.5
21.8
35
40.8
46.3
PDP (fJ)
CMOS
1.78
3.8
9.24
34.5
134
210
298
QSERL
68.7
95
142
282
578
738
892
IQSERL
1.65
3.32
8.24
28.3
116
179
263


## 4.1.4. Layout of Proposed IQSERL Inverter

The layout of proposed inverter has been drawn as shown in Figure7. The chip area of IQSERL inverter has been characterized (20.7 μm2) to be higher than the CMOS (14.54 μm2) due to the extra nMOS and pMOS in discharging/charging paths. Thus the proposed logic requiring fewer transistors is comparable to the CMOS.Figure 7
Layout of proposed IQSERL inverter circuit.


## 4.2. Proposed IQSERL Multiplier Circuit

In this section a4×4 bit IQSERL array multiplier is designed and simulated to show the usefulness of the new logic family for large circuits. It consists of 16 IQSERL AND gates, 4 IQSERL half adders, 8 IQSERL full adders, and 8 IQSERL D flip flops as shown in Figure 8(a). D flip flops are used to store the 8-bit signals. The simulation is done with simulation parameters as W/L of pMOS 540/180 nm and nMOS 240/180 nm, and input rate was kept four times the power clock rate (in IQSERL). From Figure 8(b), the simulated input and output timing waveforms verify the 4-bit multiplier logic.(a) IQSERL4×4 bit array multiplier circuit, (b) transient response.
(a)
(b)Simulation results for the proposed IQSERL multiplier are compared with CMOS and recently reported (QSERL) multipliers [17–19] using the same logic implementation, equal switching probability of inputs, and the same simulation condition. The input and supply frequencies are varied simultaneously (keeping the supply frequency four times the input frequency in IQSERL) from 0.1 MHz to 20 MHz, and corresponding power dissipations for the multipliers have been measured. IQSERL multiplier has significant power saving to the CMOS and QSERL multipliers. As frequency increases, the power saving of IQSERL to the CMOS and QSERL multipliers decreases as shown in Figure 9. At 0.05 MHz 98% saving in power as compared to the QSERL multiplier and 94% power saving to the CMOS multiplier are obtained. At 20 MHz the power saving to the QSERL multiplier is 7% whereas to the CMOS multiplier is 11%. As frequency goes higher, the resistive dissipation (which is proportional to RC/T) increases, so power saving is less.Figure 9
Simulation results of the performance comparison of4×4 bit array multipliers with frequency.After a certain high frequency (here 20 MHz), incorrect output logics are obtained, so for larger complex circuits, our IQSERL circuit is limited in some high frequency range. Also from the layout of proposed IQSERL inverter circuit as in Figure7, we can generalize it for multiplier circuit also that, for a given performance, devices can be smaller for a CMOS multiplier circuit than the IQSERL multiplier circuit. Hence the proposed IQSERL circuit is more suitable for some specific applications where speed and area are not critical. Since a 4×4 bit array multiplier is a large complex circuit, so number of transistors on a chip (transistor count) is also an important parameter to be discussed. In Table 3, we have given the comparative study of transistor count of our proposed multiplier with others.Table 3
Comparison of transistor counts of 4 × 4 bit array multiplier.
Design style
Number of transistors
CMOS
744
QSERL
1432
IQSERL
1056It may be observed that the proposed IQSERL logic requiring fewer transistors is comparable to the CMOS, whereas IQSERL logic have less transistor counts than QSERL. Thus it needs less complex layout design and can be used to build larger circuits on a single chip.


## 5. Conclusion

The simulation results and comparative performance evaluation revealed that power dissipation in the IQSERL logic family is considerably lower than the CMOS and the reported adiabatic (QSERL) family; thus the proposed IQSERL family outperforms and provides almost 20% or greater power saving over CMOS and QSERL up to 50 MHz for the IQSERL inverter. A4×4 bit array IQSERL multiplier circuits has almost 11% or greater power saving to the CMOS and 7% or greater power saving to the QSERL multiplier up to 20 MHz. The layout of IQSERL inverter circuit (area 20.7 µm2) is larger than CMOS inverter (area 14.54 µm2) which reveals that devices can be smaller for a CMOS circuit than the IQSERL circuit. Thus the proposed IQSERL circuit is more suitable for some specific applications where speed and area are not critical.



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*Source: 726324-2013-11-07.xml*