# Formation of Various Pyramidal Structures on Monocrystalline Silicon Surface and Their Influence on the Solar Cells

Authors: Yangang Han; Xuegong Yu; Dong Wang; Deren Yang
Journal: Journal of Nanomaterials
 (2013)

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## Abstract

Texturization is a useful method to enhance the optical absorption of monocrystalline silicon wafers by light-trapping effect in solar cell processing. In present study, a series of textured wafers with various pyramid sizes ranging from 200 nm to 10μm were fabricated by modified wet-chemical method and characterized. The results show that there is little difference in the reflectance with the pyramid sizes from 1 to 10 μm, which is consistent with the ray-tracing simulation results. However, the light-trapping function of the 200 nm sample below the geometrical optics limit is much weaker. The solar cells fabricated from the 1 μm samples own the highest power conversion efficiency of 18.17% due to a better coverage of metal finger lines than the larger ones, and the 200 nm samples have the lowest efficiency of 10.53%.


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## Body

## 1. Introduction

The demand for utilizing solar energy has significantly increased in the past few years. Despite relevant photovoltaic technologies being available for more than half a century, the power conversion efficiencies remain relatively low, which lie in the 10–18% range for most of the manufactured output [1, 2]. Up to now, anisotropic etching on (100)-oriented monocrystalline silicon wafers to form square-based pyramid units randomly distributed over the surface using alkaline solution has been proved to be an important and effective way to reduce the reflectivity from the front surface of silicon solar cells and improve the efficiency [3, 4]. As a result, the reflectivity of the textured silicon wafers is about 20% lower than that of the flat ones. The alkaline solution containing sodium hydroxide (NaOH) and isopropyl alcohol (IPA) is widely used in industrial batch process [5]. Normally the average pyramid size is varying from 2 μm to 8 μm, and the corresponding reflectivity is in the range of 14-15% [6–9]. To maintain stability during the texturing process, IPA must be added to the solution frequently to keep it in the same concentration because of the evaporation of IPA. Recent researches have been concentrated on investigating new texturing methods and alternative solutions. Nishimoto and Vallejo textured silicon wafers by using sodium carbonate solution without adding IPA [10, 11], and the resultant pyramid size was in the range of 4–7 μm. Chu textured silicon wafers using a metal grid with suitable openings on them to confine the hydrogen bubbles, and the structure with the pyramid size of 6 to 9 μm was obtained [12, 13]. However, it was very difficult to fabricate large-area metal grids and control the distance between the grid and silicon wafers. Chen fabricated more uniform pyramids in the size of 1 μm using reactive ion etching (RIE) [14] and achieved a lower reflectivity. Mavrokefalos synthesized inverted nanopyramid applicable for thin silicon films using standard scalable microfabrication techniques based on interference lithography and wet silicon etching [15]. A broadband enhancement in absorption was achieved using that two-step method with prepatterned holes. Ordered pyramidal structures can also be fabricated by colloidal lithography with packed polystyrene spheres [16] or silica colloidal crystals as masks [17]. However, the process was complicated and needed expensive instruments.As we mentioned above, textured silicon wafers with different pyramid size can only be synthesized using separate method. And the influence of texture feature size on the optical performance and conversion efficiency of silicon solar cells is still unknown. In present study, textured monocrystalline silicon wafers with various pyramid sizes (from 200 nm to 10μm) were fabricated in the same way using different additives. The light-trapping function was evaluated by measuring the reflectivity of different textured wafers. Also the ray-tracing simulations of light-trapping in textured wafers based on geometrical optics were conducted. Finally, solar cells made from different textured wafers were fabricated, and a power conversion efficiency of 18.17% was achieved under optimized conditions.


## 2. Experimental Section

### 2.1. Texturing Process

The p-type, (100)-oriented monocrystalline silicon wafers with a resistivity of 0.5–3 Ω·cm and a thickness of 200 μm were used in our experiments. Before any etching process, the wafers were cleaned by Radio Corporation America (RCA) method to remove the metal ions and rinsed in deionized water (18 MΩ). Then, the saw damage removal (SDR) was carried out by dipping the wafers into an aqueous solution containing 20 wt% NaOH at 80°C for 10 min and then rinsed thoroughly. The thickness of the wafers decreased to about 170 μm after that procedure. After the pretreatments mentioned above, the wafers were dipped in modified texturing solutions containing NaOH (1.5 wt%), IPA (4 vol%), and one kind of additives (0.1 wt% of Na2SiO3, 0.06 vol% of PEG, and 0.01 vol% of NPE) for 25 min. The reaction vessel was sealed during the whole process in order to prevent the chemicals from evaporation, and no agitation was needed. The inside temperature was kept at 80°C. After etching, the wafers were rinsed again in the flowing deionized water and dried with blowing N2. The surface morphology of textured wafers was investigated by a HITACHI S-4800 Scanning Electron Microscope (SEM), and the optical property was measured with a HITACHI U-4100 Spectrophotometer.


### 2.2. Software Simulations

The process of simulations obeys the law of geometrical optics. When an incident ray arrives at the surface of the silicon wafer, it is divided into the refraction ray which is absorbed by the silicon and the reflection ray which is reflected back to the air. The intensities of those two kinds of rays depend on the refractive index of silicon [18]. The simulations were performed on TracePro 6.0 developed by Lambda Research Corporation based on geometrical optics. An area of 480 μm × 480 μm and a thickness of 170 μm were used in our simulations. The light source area was 240 μm × 240 μm and the wavelength of the light source was between 300 and 1100 nm. A ray of 90000 numbers was randomly generated with a total power of 1 W. The optical property of the reference model could be obtained by testing the reflectivity of a polished monocrystalline silicon wafer. The front surface of the wafer was textured to pyramidal structure with the top angle of 70.6°, while the back surface was polished as shown in Figure 1. The intensity of final reflection ray is much lower than that of initial incident ray because of the repetitious reflection and absorption by the silicon.(a) Model of textured silicon wafer used in our simulations and (b) schematic diagram of the simulation system. The block behind the light source is used to collect the reflective rays.
(a)
(b)


### 2.3. Fabrication of Solar Cell Devices

The solar cells were made from different types of textured wafers and fabricated via a conventional solar cell process, which includes phosphorous doping on the textured front side, thermal diffusion of phosphorus, formation of a silicon nitride antireflection coating on the textured front side, metallization, and firing. The size of the solar cells was 125 mm × 125 mm. After the device fabrication process, the I-V characteristics under illumination were measured using an Oriel I-V Test Station under Air Mass 1.5 Global (AM 1.5G) illumination conditions at room temperature. All measurements were carried out using 16 samples, and the mean values were used as the results.


## 2.1. Texturing Process

The p-type, (100)-oriented monocrystalline silicon wafers with a resistivity of 0.5–3 Ω·cm and a thickness of 200 μm were used in our experiments. Before any etching process, the wafers were cleaned by Radio Corporation America (RCA) method to remove the metal ions and rinsed in deionized water (18 MΩ). Then, the saw damage removal (SDR) was carried out by dipping the wafers into an aqueous solution containing 20 wt% NaOH at 80°C for 10 min and then rinsed thoroughly. The thickness of the wafers decreased to about 170 μm after that procedure. After the pretreatments mentioned above, the wafers were dipped in modified texturing solutions containing NaOH (1.5 wt%), IPA (4 vol%), and one kind of additives (0.1 wt% of Na2SiO3, 0.06 vol% of PEG, and 0.01 vol% of NPE) for 25 min. The reaction vessel was sealed during the whole process in order to prevent the chemicals from evaporation, and no agitation was needed. The inside temperature was kept at 80°C. After etching, the wafers were rinsed again in the flowing deionized water and dried with blowing N2. The surface morphology of textured wafers was investigated by a HITACHI S-4800 Scanning Electron Microscope (SEM), and the optical property was measured with a HITACHI U-4100 Spectrophotometer.


## 2.2. Software Simulations

The process of simulations obeys the law of geometrical optics. When an incident ray arrives at the surface of the silicon wafer, it is divided into the refraction ray which is absorbed by the silicon and the reflection ray which is reflected back to the air. The intensities of those two kinds of rays depend on the refractive index of silicon [18]. The simulations were performed on TracePro 6.0 developed by Lambda Research Corporation based on geometrical optics. An area of 480 μm × 480 μm and a thickness of 170 μm were used in our simulations. The light source area was 240 μm × 240 μm and the wavelength of the light source was between 300 and 1100 nm. A ray of 90000 numbers was randomly generated with a total power of 1 W. The optical property of the reference model could be obtained by testing the reflectivity of a polished monocrystalline silicon wafer. The front surface of the wafer was textured to pyramidal structure with the top angle of 70.6°, while the back surface was polished as shown in Figure 1. The intensity of final reflection ray is much lower than that of initial incident ray because of the repetitious reflection and absorption by the silicon.(a) Model of textured silicon wafer used in our simulations and (b) schematic diagram of the simulation system. The block behind the light source is used to collect the reflective rays.
(a)
(b)


## 2.3. Fabrication of Solar Cell Devices

The solar cells were made from different types of textured wafers and fabricated via a conventional solar cell process, which includes phosphorous doping on the textured front side, thermal diffusion of phosphorus, formation of a silicon nitride antireflection coating on the textured front side, metallization, and firing. The size of the solar cells was 125 mm × 125 mm. After the device fabrication process, the I-V characteristics under illumination were measured using an Oriel I-V Test Station under Air Mass 1.5 Global (AM 1.5G) illumination conditions at room temperature. All measurements were carried out using 16 samples, and the mean values were used as the results.


## 3. Results and Discussion

### 3.1. Morphology of Textured Wafers

Figure2 shows typical SEM images of the wafers etched in NaOH/IPA solutions at 80°C for 25 min. Different additives (Na2SiO3, PEG, and NPE) were used to moderate the reaction speed and reduce the silicon/electrolyte interfacial energy to obtain special pyramid units [5]. Etching without additives was also conducted for comparison. As shown in Figure 2, various sizes of upright pyramids ranging from 10 μm to 200 nm and distributed on the surface of the wafers have been prepared. For the traditional sample etched without additive, typical structure with the pyramid size of about 10 μm can be obtained. However, there are many smaller pyramids around larger ones. For the sample etched with Na2SiO3, the typical pyramid size decreases to about 5 μm, and the uniformity has been improved. Na2SiO3 aqueous solution contains large numbers of nonpolar and polar functional parts, which reduces the surface tension of the etching solution and provides sufficient pyramid nucleation points to make the surface arrangement closer. PEG and NPE, which have many hydroxyl groups on the polymer chains, might play the same role as IPA during etching. The etching solutions containing PEG or NPE could be employed to fabricate the pyramid units of about 1 μm or 200 nm, respectively.Figure 2
Typical SEM images of the wafers textured at 80°C for 25 min with different additives: (a) no additive, (b) and (c) Na2SiO3, (d) and (e) PEG, and (f) NPE.


### 3.2. Optical Property of Textured Wafers

The reflectivity of textured wafers with different pyramid sizes was plotted in Figure3. The 1 μm sample owns the lowest reflectivity of 11.2%, and there is little difference in the reflectivity especially in the visible region, with the exception of the 200 nm sample. The degradation of the reflectance with respect to the geometrical optics limit when the pyramid size is below 300 nm is then related to diffraction effects becoming noticeable, approaching that of a flat surface for smaller sizes [19].Figure 3
The reflectivity of textured wafers with different pyramid sizes.Nearly no dependence of reflectance on the pyramid size could be explained by ray-tracing in the geometrical optics regime when the surface features are much larger than the wavelength. When the pyramid size decreases to a value which is lower than the wavelength of the incident light, the law of geometrical optics does not fit for that structure because the light should be seen as a wave. Figure4 compares the reflectivity of simulation values and chemical-etching wafers with different pyramid sizes (1–10 μm). The wavelength of the incident light was 400, 500, 600, and 700 nm, respectively. The top angle was set to 70.6°, which is similar to the chemical-etching structure. As we can see from the picture, the simulated reflectivity is almost the same for different wafers under every incident light and the value is close to the experimental result. The experimental value is slightly higher than the simulated one because the structure used in our simulations is much more uniform and regular [18].Influence of the pyramid size on the reflectivity of textured wafers. The wavelength of the incident light is (a) 400 nm, (b) 500 nm, (c) 600 nm, and (d) 700 nm. Each point and error bar (in blue) represents the mean value and standard deviation of five replicate experiments, respectively.
(a)
(b)
(c)
(d)


### 3.3. Performance of Solar Cell Devices

The solar cells made from different types of textured wafers were fabricated via a conventional solar cell process, and the device parameters are summarized in Table1. The textured morphology does not affect the open circuit voltage (Voc) for all the devices. However, the cell made from the 200 nm wafer has a short circuit current (Isc) of 4.61 A and an overall conversion efficiency (Eff.) of 10.53%, which are both much lower than those of the other three devices because of high reflection loss and less formed electron-hole pairs [20]. The 10 μm and 5 μm devices have the similar cell performance. Although different textured samples except the 200 nm one show similar reflectance values, the device fabricated from the 1 μm wafer exhibits a highest conversion efficiency of 18.17% for the possible reason that the printing metal finger lines could have a better coverage on smaller pyramidal structure than larger one [21].Table 1
Device parameters of the solar cells based on textured wafers with different pyramid sizes.
Wafer type
I
sc (A)
V
oc (V)
FF
Eff. (%)
10μm
5.74 (0.0108a)
0.62 (0.0170)
0.77 (0.0117)
17.81 (0.1126)
5μm
5.72 (0.0108)
0.62 (0.0169)
0.76 (0.0115)
17.62 (0.1114)
1μm
5.76 (0.0109)
0.63 (0.0166)
0.78 (0.0118)
18.17 (0.1148)
200 nm
4.61 (0.0087)
0.62 (0.0129)
0.56 (0.0085)
10.53 (0.0665)
aStandard deviation.


## 3.1. Morphology of Textured Wafers

Figure2 shows typical SEM images of the wafers etched in NaOH/IPA solutions at 80°C for 25 min. Different additives (Na2SiO3, PEG, and NPE) were used to moderate the reaction speed and reduce the silicon/electrolyte interfacial energy to obtain special pyramid units [5]. Etching without additives was also conducted for comparison. As shown in Figure 2, various sizes of upright pyramids ranging from 10 μm to 200 nm and distributed on the surface of the wafers have been prepared. For the traditional sample etched without additive, typical structure with the pyramid size of about 10 μm can be obtained. However, there are many smaller pyramids around larger ones. For the sample etched with Na2SiO3, the typical pyramid size decreases to about 5 μm, and the uniformity has been improved. Na2SiO3 aqueous solution contains large numbers of nonpolar and polar functional parts, which reduces the surface tension of the etching solution and provides sufficient pyramid nucleation points to make the surface arrangement closer. PEG and NPE, which have many hydroxyl groups on the polymer chains, might play the same role as IPA during etching. The etching solutions containing PEG or NPE could be employed to fabricate the pyramid units of about 1 μm or 200 nm, respectively.Figure 2
Typical SEM images of the wafers textured at 80°C for 25 min with different additives: (a) no additive, (b) and (c) Na2SiO3, (d) and (e) PEG, and (f) NPE.


## 3.2. Optical Property of Textured Wafers

The reflectivity of textured wafers with different pyramid sizes was plotted in Figure3. The 1 μm sample owns the lowest reflectivity of 11.2%, and there is little difference in the reflectivity especially in the visible region, with the exception of the 200 nm sample. The degradation of the reflectance with respect to the geometrical optics limit when the pyramid size is below 300 nm is then related to diffraction effects becoming noticeable, approaching that of a flat surface for smaller sizes [19].Figure 3
The reflectivity of textured wafers with different pyramid sizes.Nearly no dependence of reflectance on the pyramid size could be explained by ray-tracing in the geometrical optics regime when the surface features are much larger than the wavelength. When the pyramid size decreases to a value which is lower than the wavelength of the incident light, the law of geometrical optics does not fit for that structure because the light should be seen as a wave. Figure4 compares the reflectivity of simulation values and chemical-etching wafers with different pyramid sizes (1–10 μm). The wavelength of the incident light was 400, 500, 600, and 700 nm, respectively. The top angle was set to 70.6°, which is similar to the chemical-etching structure. As we can see from the picture, the simulated reflectivity is almost the same for different wafers under every incident light and the value is close to the experimental result. The experimental value is slightly higher than the simulated one because the structure used in our simulations is much more uniform and regular [18].Influence of the pyramid size on the reflectivity of textured wafers. The wavelength of the incident light is (a) 400 nm, (b) 500 nm, (c) 600 nm, and (d) 700 nm. Each point and error bar (in blue) represents the mean value and standard deviation of five replicate experiments, respectively.
(a)
(b)
(c)
(d)


## 3.3. Performance of Solar Cell Devices

The solar cells made from different types of textured wafers were fabricated via a conventional solar cell process, and the device parameters are summarized in Table1. The textured morphology does not affect the open circuit voltage (Voc) for all the devices. However, the cell made from the 200 nm wafer has a short circuit current (Isc) of 4.61 A and an overall conversion efficiency (Eff.) of 10.53%, which are both much lower than those of the other three devices because of high reflection loss and less formed electron-hole pairs [20]. The 10 μm and 5 μm devices have the similar cell performance. Although different textured samples except the 200 nm one show similar reflectance values, the device fabricated from the 1 μm wafer exhibits a highest conversion efficiency of 18.17% for the possible reason that the printing metal finger lines could have a better coverage on smaller pyramidal structure than larger one [21].Table 1
Device parameters of the solar cells based on textured wafers with different pyramid sizes.
Wafer type
I
sc (A)
V
oc (V)
FF
Eff. (%)
10μm
5.74 (0.0108a)
0.62 (0.0170)
0.77 (0.0117)
17.81 (0.1126)
5μm
5.72 (0.0108)
0.62 (0.0169)
0.76 (0.0115)
17.62 (0.1114)
1μm
5.76 (0.0109)
0.63 (0.0166)
0.78 (0.0118)
18.17 (0.1148)
200 nm
4.61 (0.0087)
0.62 (0.0129)
0.56 (0.0085)
10.53 (0.0665)
aStandard deviation.


## 4. Conclusions

Different pyramidal surface structures were realized on etched monocrystalline silicon wafers with modified alkaline solutions, and the typical pyramid sizes were ranging from 200 nm to 10μm. Little dependence of reflectance on the size of the textured pyramids is observed except the 200 nm wafer, which is approved by the effective and reliable ray-tracing simulation technology. The solar cells fabricated using the 1 μm wafers own the highest conversion efficiency of 18.17% among all the four kinds of devices due to the better coverage of metal finger lines on smaller pyramidal structures.



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*Source: 716012-2013-07-30.xml*