# Sample-Data Modeling of a Zero Voltage Transition DC-DC Converter for On-Board Battery Charger in EV

Authors: Teresa R. Granados-Luna; Ismael Araujo-Vargas; Francisco J. Perez-Pinal
Journal: Mathematical Problems in Engineering
 (2014)

---

## Abstract

Battery charger is a key device in electric and hybrid electric vehicles. On-board and off-board topologies are available in the market. Lightweight, small, high performance, and simple control are desired characteristics for on-board chargers. Moreover, isolated single-phase topologies are the most common system in Level 1 battery charger topologies. Following this trend, this paper proposes a sampled-data modelling strategy of a zero voltage transition (ZVT) DC-DC converter for an on-board battery charger. A piece-wise linear analysis of the converter is the basis of the technique presented such that a large-signal model and, therefore, a small-signal model of the converter are derived. Numerical and simulation results of a 250 W test rig validate the model.


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## Body

## 1. Introduction

Advanced vehicular systems are based on the more electric systems (MES) concept. MES is the intensive application of power electronic converters (PEC), electric machines (EM), and advanced embedded control systems to aeronautical, automotive, and maritime systems. MES was initially applied to aeronautical systems toward the reduction and/or substitution of mechanical, pneumatic, and hydraulic systems, that is, the more electric aircraft (mea) and totally integrated more electric systems (TIMES), [1]. MES are more efficient compared to their counterparts due to (i) small utilization of electric energy, (ii) high energy efficiency, (iii) reduced weight, and (iv) low maintenance [2]. After that, MES was implemented in automotive sector resulting in the more electric vehicle (MEV). MEV includes electric vehicles (EV), hybrid electric vehicles (HEV), and plug-in hybrid electric vehicles (PHEV) [3]. In particular, MES applied to vehicular systems has become popular due to the market introduction of the HEV Toyota Prius in 1997 [4]. HEV are being developed by companies like BMW, Chrysler, Daimler AG, General Motors, PSA Peugeot Citroen, Suzuki Motor Corp, Toyota, and Volkswagen. Motivations to develop EV, HEV, and PHEV are based on economic, environmental, and energetic facts. Regardless of these kinds of configurations, at least two different sources of energy are needed to achieve the same performance compared to an internal combustion engine (ICE). Indeed, at least one EM and PEC are needed in the propulsion stage at any EV, HEV, and PHEV configuration. Series, parallel, series/parallel, and integrated starter alternator (ISA) with its optional plug-in capability are typical configurations available in the market.PHEV uses an off-board or on-board charger similar to EV. The standard SAEJ1772 is used in North America and comprises three charge methods: AC level 1 (supply voltage varies from 120VAC 1-phase), AC level 2 (208V to 240VAC and 600V DC maximum; with a maximum current (amps-continuous) from 12A, 32A and 400A), and DC charging. Additionally, SAEJ1772 provides a guide to the AC level-3 vehicle, an on-board charger capable of accepting energy from an AC supply source at a nominal voltage of 208V and 240VAC and a maximum current of 400A. In addition, SAEJ1772 provides information about the coupler requirements, general electric vehicle supply equipment (EVSE) requirements, control and data, and general conductive charging system description [5].Single- and three-phase, isolated and nonisolated, and unidirectional or bidirectional configurations have been proposed in literature as battery chargers, such as reported in [6]. Methods to improve their performance are using one or several combinations of the following techniques: power factor correction (PFC); interleaved, multicell, and resonant configurations; soft/hard switching; zero voltage switching (ZVS); and zero current switching (ZCS). Moreover, the control algorithms include proportional integral (PI), proportional-integral-derivative (PID), sliding modes, fuzzy logic, and adaptive neural network. Following this trend, this paper proposed a sample-data modeling strategy of a DC-DC ZVT to understand its dynamic characteristics as an on-board battery charger. In this topology, the switches are turned on during zero voltage reducing the switching losses; as a result, a compact, lightweight system with high switching frequency can be designed. A typical peak current method is used in this work for control purposes resulting in a simple and inexpensive control law.This paper is organized as follows. The principle of operation of the converter is described in Section2 using idealized waveforms. Then, a mathematical analysis based on a piece-wise linear analysis is provided in Section 3, where a phase control strategy is modeled to obtain a large-signal model of the converter. Using this model, a half-cycle, sample-data linear model is obtained, which helps provide the final small-signal transfer functions of the converter. Numerical and simulation results of a 250 W prototype are presented to validate the model obtained. Final conclusions are summarized in Section 5.


## 2. Principle of Operation of the Converter

### 2.1. Circuit Description

A typical system configuration for an EV battery charger is shown in Figure1(a), which normally consists of a boost power factor corrected (PFC) rectifier connected to an AC supply and a high frequency (HF) DC-DC converter to regulate the load of the batteries. The topology of the DC-DC ZVT converter is shown in Figure 1(b), which has a full bridge inverter supplied with a DC voltage source; a HF transformer with a turns ratio of1 : N to generate a quasisquare, phase-controlled wave; a stray inductance connected in series to the inverter output, mainly formed by the leakage inductance of the transformer; a full-bridge rectifier connected to the transformer secondary side; and, then, aLC filter to smooth the pulsating rectified voltage waveform of the output of the rectifier. The model also considers a disturbance current source in parallel with the load.System configuration (a) block diagram and (b) phase-shift controlled ZVT DC-DC converter.
(a)
(b)The left-hand leg of the inverter, denoted byleg
A, is used as the reference to describe the converter operation. The switches of leg
A operate complementarily with fixed duty ratios of 50% at high frequency. The switches of the right-hand inverter leg, leg
B, also operate complementarily with fixed duty ratios of 50%, but the operation of leg
B is delayed byδT/2 respective to leg
A, where T is the switching period and δ is the phase control variable, which ranges from 0 to 1.The steady state operation of the circuit of Figure1 may be explained with the steady state, voltage, and current waveforms of Figure 2.Figure 2
Ideal waveforms of the converter.The first four waveforms shown in Figure2 are the states of the switches of the inverter leg A. Then, the third and fourth waves show the states of the leg
B switches, which are delayed by δ
T
/
2 respective to the first and second waves of Figure 2. The fifth and sixth waveforms of Figure 2 are the inverter output voltage, v
A
B
=
v
A
2
-
v
B
2, and output current, i
A
B (also i
L
S). The next two waveforms of this figure are the rectifier output voltage, v
D
D, and the filter inductor current, i
L
f. i
L
f is a continuous wave with a small ripple component, which is also present in i
L
S, but amplified by the turns ratioN and reverted during the negative semicycle of v
A
B. The last three waveforms of Figure 2 are the current of diodes D
1 to D
4, i
D
1 to i
D
4, and the supply current waveform i
sum. When v
A
B
=
V
in, the current i
L
S is positive and flows through D
1 and D
4, whereas when v
A
B
=
-
V
in, the current i
L
S is negative and flows through D
2 and D
3 since these diodes are positively biased. When the v
A
B waveform changes from zero to ±
V
in, the diodes D
1 and D
4 are naturally commutated, short-circuiting the transformer secondary winding due to the overlapped operation of the diodes. The duration of the diodes overlap, T
O
L, causes a fast reversal of the inverter primary current i
L
S, being limited by the inductance L
S, which prevents a short circuit of the inverter output.The production ofT
O
L may be described using the waves i
D
1 to i
D
4 of Figure 2. When v
A
B changes from zero to V
in, the currents i
D
1 and i
D
4 rise from zero to the output current level and i
D
2 and i
D
3 fall to zero, whereas when v
A
B changes from zero to -
V
in, i
D
2 and i
D
3 rise from zero to the output current level and i
D
1 and i
D
4 fall to zero. During the T
O
L period, a gradual current transfer is effectuated from one diode pair to the other, in such a way that i
L
f continues the slight current slope which feeds the load. The steady state value of T
O
L may be calculated assuming that the rate of change of the current reversal of i
A
B, d
i
A
B
/
d
t, only depends on the supply voltage and the amplitude of the DC output filter current, I
O, [3], which may be expressed as
(1)
T
O
L
=
2
N
L
S
I
O
V
s
.


### 2.2. Piece-Wise Analysis of the ZVT Converter

From Figure2, i
L
S presents six different behaviour intervals, which may be termed operating modes I to VI.For each mode of operation a different circuit configuration may be obtained, which is shown in Figure3. These equivalent circuits may be described using the state-space equation (2) and the state-space output expression (3):
(2)
X
˙
=
A
n
X
+
B
n
U
,
(3)
Y
=
F
n
X
+
G
n
U
,
where X
=
[
i
L
S
i
L
f
v
o
]
T is the state vector, U
=
[
V
s
I
Z
]
T is the input vector, I
Z is the output current disturbance, Y
=
[
i
sec
i
D
1
i
D
2
i
sum
]
T is the output vector, i
sum is the supply current, and A
n, B
n, F
n, and G
n are the state matrixes of the six operating modes, being n
=
1,2
,
…
,
6.Equivalent circuits formed from the operation ZVT DC-DC converter. (a) Mode I, (b) Mode II, (c) Mode III, (d) Mode IV, (e) Mode V, and (f) Mode VI.
(a)
(b)
(c)
(d)
(e)
(f)Mode I is formed whenT
A
1 and T
B
2 are in the on state, T
A
2 and T
B
1 are in the off state, and D
1 to D
4 are conducting due to the overlap rectifier phenomena. The equivalent circuit of Mode I is shown in Figure 3(a), and the equations that describe this mode are shown in (2) and (3) with n
=
1. The matrixesA
1,B
1,F
1
, andG
1 are listed in Table 5.In Mode II, the state of the inverter switches is exactly as that of Mode I, butD
1 and D
4 are conducting and D
2 and D
3 are off. The equivalent circuit of Mode II is shown in Figure 3(b), and again (2) and (3) describe Mode II, but with n
=
2. The matrixes A
2, B
2, F
2, and G
2 are shown in Table 5.In Mode III,T
A
1 and T
B
1 are in the on state, T
A
2 and T
B
2 are in the off state, D
1 and D
4 are conducting, and D
2 and D
3 are off. The equivalent circuit of Mode III is shown in Figure 3(c), being (2) and (3) with n
=
3 the mathematical model of this mode. Again, the matrixes A
3, B
3, F
3, and G
3 are shown in Table 5.Mode IV is a mirror of Mode I, but withT
A
1 and T
B
2 in the off state and T
A
2 and T
B
1 in the on state, whilst Modes V and VI are mirrors of Modes II and III, respectively, since the state of the switches and diodes is complementary to that of Modes II and III. Again, (2) and (3) describe Modes IV, V, and VI but with n
=
4, 5, and 6, respectively. The corresponding matrixes to these operating modes are shown in Table 5.


### 2.3. Current Control Loop Description

The circuit shown in Figure4 is a DC-DC ZVT converter with peak current control loop, which has a current transducer with gain R
s that senses i
sum, oneSR flip-flop and twoDflip-flops, a clock signal, v
CLK, a sawtooth generator, v
SAW, and the reference current level, v
i
REF, which is provided by an outer voltage loop.Figure 4
DC-DC ZVT converter with current control loop.The operation of the circuit of Figure4 may be explained with the state voltage and current waveforms of Figure 5. The first waveform shown in Figure 5 is the clock signal of system, v
CLK. The second waveform is i
sum plotted together with the deference of v
i
REF with v
SAW, where v
SAW is a negative slope synchronized with v
CLK, while v
i
REF is the current reference that regulates the peak level of i
sum. v
COMP is the state of the output comparator, which is the third waveform of this figure. The fourth and fifth waveforms are theSR flip-flop outputs Q
A and Q
B, with Q
A set to the on state by v
CLK and to the off state when v
COMP switches to the on state. The fifth and sixth waveforms are the outputs of the first flip-flop, v
g
s
T
A
1 and v
g
s
T
A
2, which are controlled by the rising edge of Q
A, whereas v
g
s
T
B
1 and v
g
s
T
B
2, the outputs of the second D flip-flop, which are the last waves of this figure, are controlled by the rising edge of Q
B.Figure 5
Ideal waveform DC-DC ZVT converter with current control loop.


### 2.4. Numerical Estimation of theT
O
L and δ Periods

T
O
L defines the duration of Modes I and IV and may be numerically estimated by determining the instant when either i
D
2 or i
D
1 reaches zero. T
O
L may also be calculated using the Newton-Raphson method, [4]. This numerical method may be implemented using
(4)
T
O
L
(
n
+
1
)
=
T
O
L
(
n
)
-
f
(
T
O
L
)
f
′
(
T
O
L
)
,
where
(5)
f
(
T
O
L
)
=
F
D
1
(
φ
1
(
T
O
L
)
X
(
t
1
)
)
+
(
F
D
1
A
1
-
1
[
φ
1
(
T
O
L
)
-
I
d
]
B
1
+
G
D
1
)
U
,
f
′
(
T
O
L
)
=
F
D
1
A
1
e
A
1
T
O
L
X
(
t
1
)
+
F
D
1
[
∑
j
∞
(
j
+
1
)
A
1
j
T
O
L
j
(
j
+
1
)
!
]
B
1
U
.Equations of (5) use the output equation that includes i
D
1, which determine the duration of Mode I, whereas the duration of Mode IV is determined by i
D
2, such that (6) may be rewritten as follows:
(6)
f
(
T
O
L
)
=
F
D
2
(
φ
4
(
T
O
L
)
X
(
T
2
)
)
+
(
F
D
2
A
4
-
1
[
φ
4
(
T
O
L
)
-
I
d
]
B
4
+
G
D
4
)
,
f
′
(
T
O
L
)
=
F
D
2
A
4
e
A
4
T
O
L
X
(
T
2
)
+
F
D
2
[
∑
j
∞
(
j
+
1
)
A
4
j
T
O
L
j
(
j
+
1
)
!
]
B
4
U
.δ defines the duration of Modes II and V and may be numerically estimated by determining the instant when the equation v
i
REF
-
v
SAW is equal to R
s
i
sum. δ may also be calculated using the Newton-Raphson method, [4]. This numerical method may be implemented using
(7)
δ
(
n
+
1
)
=
δ
(
n
)
-
i
2
,
sum
(
δ
)
i
2
,
sum
′
(
δ
)
,
where
(8)
i
2
,
sum
(
δ
)
=
-
(
1
(
R
s
)
)
[
(
v
v
-
v
p
)
(
δ
T
/
2
T
/
2
)
+
v
p
]
,
f
′
(
δ
)
=
(
v
v
-
v
p
)
δ
-
F
2
,
sum
(
A
2
T
2
)
×
(
φ
2
(
δ
T
2
-
T
O
L
)
X
(
t
1
+
T
O
L
)
)
+
F
2
,
sum
T
2
[
∑
j
∞
(
j
+
1
)
A
2
j
(
(
δ
T
/
2
)
-
T
O
L
)
j
(
j
+
1
)
!
]
U
.Equations of (8) use the output equation that includes i
2
,
sum and the expression v
i
REF
-
v
SAW
=
R
s
i
sum, which determines the duration of Mode II, whereas the duration of Mode V is determined by i
5
,
sum and the expression v
i
REF
-
v
SAW
=
R
s
i
sum, such that (9) may be rewritten as follows:
(9)
i
5
,
sum
(
δ
)
=
-
(
v
v
-
v
p
)
(
(
δ
T
/
2
)
/
(
T
/
2
)
)
+
v
p
(
R
s
)
i
5
,
sum
′
(
δ
)
=
(
v
v
-
v
p
)
δ
-
F
5
,
sum
(
A
5
T
2
)
×
(
φ
5
(
δ
T
2
-
T
O
L
)
X
(
t
1
+
T
O
L
)
)
+
F
5
,
sum
T
2
[
∑
j
∞
(
j
+
1
)
A
5
j
(
(
δ
T
/
2
)
-
T
O
L
)
j
(
j
+
1
)
!
]
U
.


## 2.1. Circuit Description

A typical system configuration for an EV battery charger is shown in Figure1(a), which normally consists of a boost power factor corrected (PFC) rectifier connected to an AC supply and a high frequency (HF) DC-DC converter to regulate the load of the batteries. The topology of the DC-DC ZVT converter is shown in Figure 1(b), which has a full bridge inverter supplied with a DC voltage source; a HF transformer with a turns ratio of1 : N to generate a quasisquare, phase-controlled wave; a stray inductance connected in series to the inverter output, mainly formed by the leakage inductance of the transformer; a full-bridge rectifier connected to the transformer secondary side; and, then, aLC filter to smooth the pulsating rectified voltage waveform of the output of the rectifier. The model also considers a disturbance current source in parallel with the load.System configuration (a) block diagram and (b) phase-shift controlled ZVT DC-DC converter.
(a)
(b)The left-hand leg of the inverter, denoted byleg
A, is used as the reference to describe the converter operation. The switches of leg
A operate complementarily with fixed duty ratios of 50% at high frequency. The switches of the right-hand inverter leg, leg
B, also operate complementarily with fixed duty ratios of 50%, but the operation of leg
B is delayed byδT/2 respective to leg
A, where T is the switching period and δ is the phase control variable, which ranges from 0 to 1.The steady state operation of the circuit of Figure1 may be explained with the steady state, voltage, and current waveforms of Figure 2.Figure 2
Ideal waveforms of the converter.The first four waveforms shown in Figure2 are the states of the switches of the inverter leg A. Then, the third and fourth waves show the states of the leg
B switches, which are delayed by δ
T
/
2 respective to the first and second waves of Figure 2. The fifth and sixth waveforms of Figure 2 are the inverter output voltage, v
A
B
=
v
A
2
-
v
B
2, and output current, i
A
B (also i
L
S). The next two waveforms of this figure are the rectifier output voltage, v
D
D, and the filter inductor current, i
L
f. i
L
f is a continuous wave with a small ripple component, which is also present in i
L
S, but amplified by the turns ratioN and reverted during the negative semicycle of v
A
B. The last three waveforms of Figure 2 are the current of diodes D
1 to D
4, i
D
1 to i
D
4, and the supply current waveform i
sum. When v
A
B
=
V
in, the current i
L
S is positive and flows through D
1 and D
4, whereas when v
A
B
=
-
V
in, the current i
L
S is negative and flows through D
2 and D
3 since these diodes are positively biased. When the v
A
B waveform changes from zero to ±
V
in, the diodes D
1 and D
4 are naturally commutated, short-circuiting the transformer secondary winding due to the overlapped operation of the diodes. The duration of the diodes overlap, T
O
L, causes a fast reversal of the inverter primary current i
L
S, being limited by the inductance L
S, which prevents a short circuit of the inverter output.The production ofT
O
L may be described using the waves i
D
1 to i
D
4 of Figure 2. When v
A
B changes from zero to V
in, the currents i
D
1 and i
D
4 rise from zero to the output current level and i
D
2 and i
D
3 fall to zero, whereas when v
A
B changes from zero to -
V
in, i
D
2 and i
D
3 rise from zero to the output current level and i
D
1 and i
D
4 fall to zero. During the T
O
L period, a gradual current transfer is effectuated from one diode pair to the other, in such a way that i
L
f continues the slight current slope which feeds the load. The steady state value of T
O
L may be calculated assuming that the rate of change of the current reversal of i
A
B, d
i
A
B
/
d
t, only depends on the supply voltage and the amplitude of the DC output filter current, I
O, [3], which may be expressed as
(1)
T
O
L
=
2
N
L
S
I
O
V
s
.


## 2.2. Piece-Wise Analysis of the ZVT Converter

From Figure2, i
L
S presents six different behaviour intervals, which may be termed operating modes I to VI.For each mode of operation a different circuit configuration may be obtained, which is shown in Figure3. These equivalent circuits may be described using the state-space equation (2) and the state-space output expression (3):
(2)
X
˙
=
A
n
X
+
B
n
U
,
(3)
Y
=
F
n
X
+
G
n
U
,
where X
=
[
i
L
S
i
L
f
v
o
]
T is the state vector, U
=
[
V
s
I
Z
]
T is the input vector, I
Z is the output current disturbance, Y
=
[
i
sec
i
D
1
i
D
2
i
sum
]
T is the output vector, i
sum is the supply current, and A
n, B
n, F
n, and G
n are the state matrixes of the six operating modes, being n
=
1,2
,
…
,
6.Equivalent circuits formed from the operation ZVT DC-DC converter. (a) Mode I, (b) Mode II, (c) Mode III, (d) Mode IV, (e) Mode V, and (f) Mode VI.
(a)
(b)
(c)
(d)
(e)
(f)Mode I is formed whenT
A
1 and T
B
2 are in the on state, T
A
2 and T
B
1 are in the off state, and D
1 to D
4 are conducting due to the overlap rectifier phenomena. The equivalent circuit of Mode I is shown in Figure 3(a), and the equations that describe this mode are shown in (2) and (3) with n
=
1. The matrixesA
1,B
1,F
1
, andG
1 are listed in Table 5.In Mode II, the state of the inverter switches is exactly as that of Mode I, butD
1 and D
4 are conducting and D
2 and D
3 are off. The equivalent circuit of Mode II is shown in Figure 3(b), and again (2) and (3) describe Mode II, but with n
=
2. The matrixes A
2, B
2, F
2, and G
2 are shown in Table 5.In Mode III,T
A
1 and T
B
1 are in the on state, T
A
2 and T
B
2 are in the off state, D
1 and D
4 are conducting, and D
2 and D
3 are off. The equivalent circuit of Mode III is shown in Figure 3(c), being (2) and (3) with n
=
3 the mathematical model of this mode. Again, the matrixes A
3, B
3, F
3, and G
3 are shown in Table 5.Mode IV is a mirror of Mode I, but withT
A
1 and T
B
2 in the off state and T
A
2 and T
B
1 in the on state, whilst Modes V and VI are mirrors of Modes II and III, respectively, since the state of the switches and diodes is complementary to that of Modes II and III. Again, (2) and (3) describe Modes IV, V, and VI but with n
=
4, 5, and 6, respectively. The corresponding matrixes to these operating modes are shown in Table 5.


## 2.3. Current Control Loop Description

The circuit shown in Figure4 is a DC-DC ZVT converter with peak current control loop, which has a current transducer with gain R
s that senses i
sum, oneSR flip-flop and twoDflip-flops, a clock signal, v
CLK, a sawtooth generator, v
SAW, and the reference current level, v
i
REF, which is provided by an outer voltage loop.Figure 4
DC-DC ZVT converter with current control loop.The operation of the circuit of Figure4 may be explained with the state voltage and current waveforms of Figure 5. The first waveform shown in Figure 5 is the clock signal of system, v
CLK. The second waveform is i
sum plotted together with the deference of v
i
REF with v
SAW, where v
SAW is a negative slope synchronized with v
CLK, while v
i
REF is the current reference that regulates the peak level of i
sum. v
COMP is the state of the output comparator, which is the third waveform of this figure. The fourth and fifth waveforms are theSR flip-flop outputs Q
A and Q
B, with Q
A set to the on state by v
CLK and to the off state when v
COMP switches to the on state. The fifth and sixth waveforms are the outputs of the first flip-flop, v
g
s
T
A
1 and v
g
s
T
A
2, which are controlled by the rising edge of Q
A, whereas v
g
s
T
B
1 and v
g
s
T
B
2, the outputs of the second D flip-flop, which are the last waves of this figure, are controlled by the rising edge of Q
B.Figure 5
Ideal waveform DC-DC ZVT converter with current control loop.


## 2.4. Numerical Estimation of theT
O
L and δ Periods

T
O
L defines the duration of Modes I and IV and may be numerically estimated by determining the instant when either i
D
2 or i
D
1 reaches zero. T
O
L may also be calculated using the Newton-Raphson method, [4]. This numerical method may be implemented using
(4)
T
O
L
(
n
+
1
)
=
T
O
L
(
n
)
-
f
(
T
O
L
)
f
′
(
T
O
L
)
,
where
(5)
f
(
T
O
L
)
=
F
D
1
(
φ
1
(
T
O
L
)
X
(
t
1
)
)
+
(
F
D
1
A
1
-
1
[
φ
1
(
T
O
L
)
-
I
d
]
B
1
+
G
D
1
)
U
,
f
′
(
T
O
L
)
=
F
D
1
A
1
e
A
1
T
O
L
X
(
t
1
)
+
F
D
1
[
∑
j
∞
(
j
+
1
)
A
1
j
T
O
L
j
(
j
+
1
)
!
]
B
1
U
.Equations of (5) use the output equation that includes i
D
1, which determine the duration of Mode I, whereas the duration of Mode IV is determined by i
D
2, such that (6) may be rewritten as follows:
(6)
f
(
T
O
L
)
=
F
D
2
(
φ
4
(
T
O
L
)
X
(
T
2
)
)
+
(
F
D
2
A
4
-
1
[
φ
4
(
T
O
L
)
-
I
d
]
B
4
+
G
D
4
)
,
f
′
(
T
O
L
)
=
F
D
2
A
4
e
A
4
T
O
L
X
(
T
2
)
+
F
D
2
[
∑
j
∞
(
j
+
1
)
A
4
j
T
O
L
j
(
j
+
1
)
!
]
B
4
U
.δ defines the duration of Modes II and V and may be numerically estimated by determining the instant when the equation v
i
REF
-
v
SAW is equal to R
s
i
sum. δ may also be calculated using the Newton-Raphson method, [4]. This numerical method may be implemented using
(7)
δ
(
n
+
1
)
=
δ
(
n
)
-
i
2
,
sum
(
δ
)
i
2
,
sum
′
(
δ
)
,
where
(8)
i
2
,
sum
(
δ
)
=
-
(
1
(
R
s
)
)
[
(
v
v
-
v
p
)
(
δ
T
/
2
T
/
2
)
+
v
p
]
,
f
′
(
δ
)
=
(
v
v
-
v
p
)
δ
-
F
2
,
sum
(
A
2
T
2
)
×
(
φ
2
(
δ
T
2
-
T
O
L
)
X
(
t
1
+
T
O
L
)
)
+
F
2
,
sum
T
2
[
∑
j
∞
(
j
+
1
)
A
2
j
(
(
δ
T
/
2
)
-
T
O
L
)
j
(
j
+
1
)
!
]
U
.Equations of (8) use the output equation that includes i
2
,
sum and the expression v
i
REF
-
v
SAW
=
R
s
i
sum, which determines the duration of Mode II, whereas the duration of Mode V is determined by i
5
,
sum and the expression v
i
REF
-
v
SAW
=
R
s
i
sum, such that (9) may be rewritten as follows:
(9)
i
5
,
sum
(
δ
)
=
-
(
v
v
-
v
p
)
(
(
δ
T
/
2
)
/
(
T
/
2
)
)
+
v
p
(
R
s
)
i
5
,
sum
′
(
δ
)
=
(
v
v
-
v
p
)
δ
-
F
5
,
sum
(
A
5
T
2
)
×
(
φ
5
(
δ
T
2
-
T
O
L
)
X
(
t
1
+
T
O
L
)
)
+
F
5
,
sum
T
2
[
∑
j
∞
(
j
+
1
)
A
5
j
(
(
δ
T
/
2
)
-
T
O
L
)
j
(
j
+
1
)
!
]
U
.


## 3. Modeling of the ZVT Converter with Current Control Loop

### 3.1. Piece-Wise Linear Model

Equation (2) may be used to develop a piece-wise linear model of the converter of Figure 1 throughout all the modes of operation. The solution of (2) may be expressed as
(10)
X
(
t
n
-
1
+
t
n
)
=
φ
n
(
t
n
)
X
(
t
1
)
+
A
n
-
1
[
φ
n
(
t
n
)
-
I
d
]
B
n
U
,
where
(11)
φ
n
(
t
n
)
=
e
A
n
t
n
,
which defines in the first term of (10) the natural response of the system along the period of time t
n
-
t
n
-
1 with the initial condition X
(
t
n
-
1
) at Moden. The second term of (10) is the steady state response, which is obtained by using the convolution integral. Therefore, using (10) for the time interval of t
1
≤
t
<
t
1
+
T
O
L, together with the matrixes of Mode I, the solution of the state vector for Mode I is obtained as follows:
(12)
X
(
t
1
+
T
O
L
)
=
φ
1
(
T
O
L
)
X
(
t
1
)
+
A
1
-
1
[
φ
1
(
T
O
L
)
-
I
d
]
B
1
U
.In a similar way, the solutions for Modes II to VI at the time intervalst
1
+
T
O
L
≤
t
<
t
1
+
δ
T
/
2,t
1
+
δ
T
/
2
≤
t
<
t
1
+
T
/
2,  t
1
+
T
/
2
≤
t
<
t
1
+
T
/
2
+
T
O
L,  t
1
+
T
/
2
+
T
O
L
≤
t
<
t
1
+
(
1
+
δ
)
T
/
2, and  t
1
+
(
1
+
δ
)
T
/
2
≤
t
<
t
1
+
T become
(13)
X
(
t
1
+
δ
T
2
)
=
φ
2
(
δ
T
2
-
T
O
L
)
X
(
t
1
+
T
O
L
)
+
A
2
-
1
[
φ
2
(
δ
T
2
-
T
O
L
)
-
I
d
]
B
2
U
,
(14)
X
(
t
1
+
T
2
)
=
φ
3
(
T
2
-
δ
T
2
)
X
(
t
1
+
δ
T
2
)
+
A
3
-
1
[
φ
3
(
T
2
-
δ
T
2
)
-
I
d
]
B
3
U
,
(15)
X
(
t
1
+
T
2
+
T
O
L
)
=
φ
4
(
T
O
L
)
X
(
t
1
+
T
2
)
+
A
4
-
1
[
φ
4
(
T
O
L
)
-
I
d
]
B
4
U
,
(16)
X
(
t
1
+
(
1
+
δ
)
T
2
)
=
φ
5
(
δ
T
2
-
T
O
L
)
X
(
t
1
+
T
2
+
T
O
L
)
+
A
5
-
1
[
φ
5
(
δ
T
2
-
T
O
L
)
-
I
d
]
B
5
U
,
(17)
X
(
t
1
+
T
)
=
φ
6
(
(
1
-
δ
)
T
2
)
X
(
t
1
+
(
1
+
δ
)
T
2
)
+
A
6
-
1
[
φ
6
(
(
1
-
δ
)
T
2
)
-
I
d
]
B
6
U
.


### 3.2. Large-Signal Model

The large-signal model of the ZVT converter may be obtained by substituting (12) in (13), (13) in (14), (14) in (15), (15) in (16), and (16) in (17), in such a way that a single expression is obtained as shown in
(18)
X
(
t
1
+
T
)
=
φ
6
(
(
1
-
δ
)
T
2
)
φ
5
(
δ
T
2
-
T
O
L
)
φ
4
(
T
O
L
)
φ
3
×
(
(
1
-
δ
)
T
2
)
φ
2
(
δ
T
2
-
T
O
L
)
φ
1
(
T
O
L
)
X
(
t
1
)
+
[
φ
6
(
(
1
-
δ
)
T
2
)
×
[
φ
5
(
δ
T
2
-
T
O
L
)
×
[
φ
4
(
T
O
L
)
[
φ
3
(
(
1
-
δ
)
T
2
)
×
φ
2
(
δ
T
2
-
T
O
L
)
×
A
1
-
1
[
φ
1
(
T
O
L
)
-
I
d
]
B
1
+
A
2
-
1
[
φ
2
(
δ
T
2
-
T
O
L
)
-
I
d
(
δ
T
2
-
T
O
L
)
]
B
2
(
(
1
-
δ
)
T
2
)
(
(
1
-
δ
)
T
2
)
]
+
A
3
-
1
[
φ
3
(
(
1
-
δ
)
T
2
)
-
I
d
]
B
3
]
+
A
4
-
1
[
φ
4
(
T
O
L
)
-
I
d
]
B
4
(
δ
T
2
-
T
O
L
)
(
δ
T
2
-
T
O
L
)
]
+
A
5
-
1
[
φ
5
(
δ
T
2
-
T
O
L
)
-
I
d
]
B
5
(
(
1
-
δ
)
T
2
)
]
+
A
6
-
1
[
φ
6
(
(
1
-
δ
)
T
2
)
-
I
d
]
B
6
U
.


### 3.3. Half-Cycle Model

The waveformi
L
S of Figure 2 shows that operation modes IV, V, and VI are mirrors of Modes I, II, and III, respectively; therefore, the first three operation modes are sufficient to describe the function of the converter. A particular matrix titled asW may relate the modes I, II, and III with the modes IV, V, and VI, which satisfies the condition W
W
=
I
d, the identity matrix. Therefore, the half-cycle model of the ZVT converter may be obtained replacing the terms A
4, A
5, A
6, B
4, B
5, and B
6 by expressions W
A
1, W
A
2, W
A
3, W
B
1, W
B
2, and W
B
3, respectively, in (18), such that the half-cycle model is
(19)
X
(
t
1
+
T
2
)
=
φ
3
(
(
1
-
δ
)
T
2
)
φ
2
(
δ
T
2
-
T
O
L
)
φ
1
(
T
O
L
)
X
(
t
1
)
+
[
φ
3
(
(
1
-
δ
)
T
2
)
φ
2
φ
3
(
(
1
-
δ
)
T
2
)
φ
2
×
(
δ
T
2
-
T
O
L
)
A
1
-
1
[
φ
1
(
T
O
L
)
-
I
d
]
B
1
+
φ
3
(
(
1
-
δ
)
T
2
)
A
2
-
1
[
φ
2
(
δ
T
2
-
T
O
L
)
-
I
d
]
B
2
+
A
3
-
1
[
φ
3
(
(
1
-
δ
)
T
2
)
-
I
d
]
B
3
]
U
+
W
(
[
φ
3
(
(
1
-
δ
)
T
2
)
-
I
d
]
φ
3
(
(
1
-
δ
)
T
2
)
(
φ
2
(
δ
T
2
-
T
O
L
)
×
W
φ
1
(
T
O
L
)
X
(
t
1
)
+
φ
3
(
(
1
-
δ
)
T
2
)
×
φ
2
(
δ
T
2
-
T
O
L
)
A
1
-
1
×
[
φ
1
(
T
O
L
)
-
I
d
]
B
1
(
δ
T
2
-
T
O
L
)
)
+
φ
3
(
(
1
-
δ
)
T
2
)
A
2
-
1
×
[
φ
2
(
δ
T
2
-
T
O
L
)
-
I
d
]
B
2
+
A
3
-
1
[
φ
3
(
(
1
-
δ
)
T
2
)
-
I
d
]
W
B
3
)
U
(
t
1
)
.The previous equation may be rewritten asX
(
t
1
+
T
/
2
)
=
A
MC
X
(
t
1
)
+
B
MC
U
(
t
1
) for practical purposes.


### 3.4. Sample-Data, Small-Signal Linear Model of the Converter in Open-Loop Conditions

The equationX
(
t
1
+
T
/
2
)
=
A
MC
X
(
t
1
)
+
B
MC
U
(
t
1
) may be used as a half-cycle, discrete model of the ZVT converter, which may be written as
(20)
X
K
+
1
′
=
A
MC
X
K
+
B
MC
U
K
,
where X
K
+
1
′
=
X
(
t
1
+
T
/
2
), X
K
=
X
(
t
1
), and U
K
=
U
(
t
1
)A sample-data, small-signal model may be obtained by using the Taylor series, (21), and using small-signal perturbations as δ
x
K, δ
U
K, δ
T
O
L
k and δ
δ
K. One has
(21)
f
(
x
)
=
f
(
x
0
)
+
J
(
x
-
x
0
)
.Using this equation, the sample-data, small-signal linear model becomes(22)
δ
x
k
+
1
≈
∂
x
k
+
1
∂
x
k
δ
x
k
+
∂
x
k
+
1
∂
U
k
δ
U
k
+
∂
x
k
+
1
∂
δ
δ
δ
k
+
∂
x
k
+
1
∂
T
O
L
δ
T
O
L
k
.
The solution of the partial derivatives is ∂
x
k
+
1
/
∂
x
k
=
A
MC,  ∂
x
k
+
1
/
∂
U
k
=
B
MC,  ∂
x
k
+
1
/
∂
δ
=
C
δ, and ∂
x
k
+
1
/
∂
T
O
L
=
D
T
O
L.  δ
T
O
L
k may be determined utilizing the restriction equation of T
O
L, whereas δ
δ
K is obtained using the restriction equation of δ.


### 3.5. Restriction Equations of the Control Loop

The restriction equations forT
O
L may be obtained analyzing the waveforms i
L
S, i
D
1
,
D
3, and i
sum, which are shown in Figure 2 during the Mode I. The slope of i
sum during Mode I is named g
1 and is determined by the rate of change of i
L
S; that is, g
1
=
V
s
k
/
L
S, while the slopes of i
D
1
,
D
3 during the Mode I are named g
3, which are contrary and of lower amplitude than g
1; that is, g
3
=
-
g
1
/
2
N. The restriction equation of T
O
L may be determined by integrating the waveforms i
D
1
,
D
3 during Mode I:
(23)
i
L
S
k
2
N
+
i
L
f
k
2
+
V
s
k
L
S
T
O
L
k
=
0
.The previous equation is not linear; therefore, it is necessary to use the Taylor series to obtain a linearized model:(24)
δ
T
O
L
k
=
2
N
L
S
V
S
CD
[
-
1
2
N
-
1
2
-
T
O
L
CD
2
N
L
S
]
[
δ
i
L
S
k
δ
i
L
f
k
δ
V
s
k
]
.The restriction equation ofδ may be obtained analyzing the waveforms i
L
S and i
sum with v
i
REF
-
v
SAW during Mode II (Figures 2 and 5). v
SAW is determined by M
(
δ
k
T
/
2
) and the slope of i
sum during Mode II, named g
2, and may be obtained by integrating again i
sumwhen R
s
i
sum
=
v
i
REF
-
v
SAW:
(25)
R
s
(
i
L
S
k
+
g
1
T
O
L
k
+
g
2
(
δ
k
T
2
-
T
O
L
k
)
)
=
V
i
REF
-
M
δ
k
T
2
.The Taylor series is used to linearize the previous equation, and therefore the restriction equation ofδ becomes
(26)
δ
δ
k
=
1
Δ
δ
[
a
δ
1
a
δ
2
a
δ
3
a
δ
4
a
δ
5
]
[
δ
i
L
S
k
δ
i
L
f
k
δ
V
s
k
δ
V
i
REF
k
δ
V
o
k
]
,
where Δ
δ
=
-
(
2
/
T
)
/
(
M
T
/
2
R
S
+
1
/
(
L
S
+
(
1
/
N
2
)
L
f
)
)
(
v
s
CD
-
(
1
/
N
)
v
0
CD
), a
δ
1
=
∂
i
L
S
k
/
∂
i
L
S
k, a
δ
2
=
∂
i
L
S
k
/
∂
i
L
f
k, a
δ
3
=
∂
i
L
S
k
/
∂
V
S
k, a
δ
4
=
∂
i
L
S
k
/
∂
V
i
REF
k, and a
δ
5
=
∂
i
L
S
k
/
∂
V
o
k.


### 3.6. Sample-Data, Small-Signal Linear Model of the Converter in Closed-Loop Conditions

The sample-data, small-signal linear model, may be obtained by substitutingδ
T
O
L
k and δ
δ
K, (24) and (26), respectively, in (22):
(27)
δ
x
k
+
1
=
A
MC
[
δ
i
L
S
k
δ
i
L
f
k
δ
V
s
k
]
+
B
MC
[
δ
V
s
k
δ
I
Z
k
]
+
C
δ
(
1
Δ
δ
[
a
δ
1
a
δ
2
a
δ
3
a
δ
4
a
δ
5
]
[
δ
i
L
S
k
δ
i
L
f
k
δ
V
s
k
δ
V
i
REF
k
δ
V
o
k
]
)
+
D
T
O
L
(
2
N
L
S
V
S
CD
[
-
1
2
N
-
1
2
-
T
O
L
CD
2
N
L
S
]
[
δ
i
L
S
k
δ
i
L
f
k
δ
V
s
k
]
)
,
such that the small-signal model becomes
(28)
δ
x
k
+
1
=
A
c
l
δ
x
k
+
ω
c
l
δ
w
c
l
k
,
where δ
x
k
+
1
=
[
δ
i
L
S
k
′
δ
i
L
f
k
′
δ
V
s
k
′
]
T, δ
x
k
=
[
δ
i
L
S
k
δ
i
L
f
k
δ
V
s
k
]
′, and δ
w
c
l
k
=
[
δ
V
s
k
δ
V
i
REF
k
δ
I
Z
k
]
T.Equation (28) may be solved by using the Z transform, such that δ
x
K becomes
(29)
δ
x
k
=
(
I
d
-
A
c
l
)
-
1
Z
ω
c
l
δ
w
c
l
k
.


### 3.7. Transfer Function

To verify the dynamic characteristics of the converter is necessary to analyze the transfer functions that relatev
o with V
s, v
i
REF, and I
z, which are the throughput input-to-output DC voltage transfer function, H
v
(
z
)
=
v
o
(
z
)
/
v
s
(
z
), the control-to-output transfer function, T
O
L
(
z
)
=
v
o
(
z
)
/
v
i
REF
(
z
), and the output impedance transfer function Z
o
(
z
)
=
v
o
(
z
)
/
I
z
(
z
), respectively.The magnitude and phase of each transfer function may be obtained using a Bode diagram, whereas the root locus technique may be employed to describe the behaviour of the poles and zeros of (30). One has
(30)
H
v
(
z
)
=
z
+
a
1
z
2
+
b
1
z
+
c
1
,
T
O
L
(
z
)
=
a
2
z
2
+
b
2
z
+
c
2
z
2
+
b
1
z
+
c
1
,
Z
o
(
z
)
=
a
3
z
2
+
b
3
z
-
c
3
z
2
+
b
1
z
+
c
1
.


## 3.1. Piece-Wise Linear Model

Equation (2) may be used to develop a piece-wise linear model of the converter of Figure 1 throughout all the modes of operation. The solution of (2) may be expressed as
(10)
X
(
t
n
-
1
+
t
n
)
=
φ
n
(
t
n
)
X
(
t
1
)
+
A
n
-
1
[
φ
n
(
t
n
)
-
I
d
]
B
n
U
,
where
(11)
φ
n
(
t
n
)
=
e
A
n
t
n
,
which defines in the first term of (10) the natural response of the system along the period of time t
n
-
t
n
-
1 with the initial condition X
(
t
n
-
1
) at Moden. The second term of (10) is the steady state response, which is obtained by using the convolution integral. Therefore, using (10) for the time interval of t
1
≤
t
<
t
1
+
T
O
L, together with the matrixes of Mode I, the solution of the state vector for Mode I is obtained as follows:
(12)
X
(
t
1
+
T
O
L
)
=
φ
1
(
T
O
L
)
X
(
t
1
)
+
A
1
-
1
[
φ
1
(
T
O
L
)
-
I
d
]
B
1
U
.In a similar way, the solutions for Modes II to VI at the time intervalst
1
+
T
O
L
≤
t
<
t
1
+
δ
T
/
2,t
1
+
δ
T
/
2
≤
t
<
t
1
+
T
/
2,  t
1
+
T
/
2
≤
t
<
t
1
+
T
/
2
+
T
O
L,  t
1
+
T
/
2
+
T
O
L
≤
t
<
t
1
+
(
1
+
δ
)
T
/
2, and  t
1
+
(
1
+
δ
)
T
/
2
≤
t
<
t
1
+
T become
(13)
X
(
t
1
+
δ
T
2
)
=
φ
2
(
δ
T
2
-
T
O
L
)
X
(
t
1
+
T
O
L
)
+
A
2
-
1
[
φ
2
(
δ
T
2
-
T
O
L
)
-
I
d
]
B
2
U
,
(14)
X
(
t
1
+
T
2
)
=
φ
3
(
T
2
-
δ
T
2
)
X
(
t
1
+
δ
T
2
)
+
A
3
-
1
[
φ
3
(
T
2
-
δ
T
2
)
-
I
d
]
B
3
U
,
(15)
X
(
t
1
+
T
2
+
T
O
L
)
=
φ
4
(
T
O
L
)
X
(
t
1
+
T
2
)
+
A
4
-
1
[
φ
4
(
T
O
L
)
-
I
d
]
B
4
U
,
(16)
X
(
t
1
+
(
1
+
δ
)
T
2
)
=
φ
5
(
δ
T
2
-
T
O
L
)
X
(
t
1
+
T
2
+
T
O
L
)
+
A
5
-
1
[
φ
5
(
δ
T
2
-
T
O
L
)
-
I
d
]
B
5
U
,
(17)
X
(
t
1
+
T
)
=
φ
6
(
(
1
-
δ
)
T
2
)
X
(
t
1
+
(
1
+
δ
)
T
2
)
+
A
6
-
1
[
φ
6
(
(
1
-
δ
)
T
2
)
-
I
d
]
B
6
U
.


## 3.2. Large-Signal Model

The large-signal model of the ZVT converter may be obtained by substituting (12) in (13), (13) in (14), (14) in (15), (15) in (16), and (16) in (17), in such a way that a single expression is obtained as shown in
(18)
X
(
t
1
+
T
)
=
φ
6
(
(
1
-
δ
)
T
2
)
φ
5
(
δ
T
2
-
T
O
L
)
φ
4
(
T
O
L
)
φ
3
×
(
(
1
-
δ
)
T
2
)
φ
2
(
δ
T
2
-
T
O
L
)
φ
1
(
T
O
L
)
X
(
t
1
)
+
[
φ
6
(
(
1
-
δ
)
T
2
)
×
[
φ
5
(
δ
T
2
-
T
O
L
)
×
[
φ
4
(
T
O
L
)
[
φ
3
(
(
1
-
δ
)
T
2
)
×
φ
2
(
δ
T
2
-
T
O
L
)
×
A
1
-
1
[
φ
1
(
T
O
L
)
-
I
d
]
B
1
+
A
2
-
1
[
φ
2
(
δ
T
2
-
T
O
L
)
-
I
d
(
δ
T
2
-
T
O
L
)
]
B
2
(
(
1
-
δ
)
T
2
)
(
(
1
-
δ
)
T
2
)
]
+
A
3
-
1
[
φ
3
(
(
1
-
δ
)
T
2
)
-
I
d
]
B
3
]
+
A
4
-
1
[
φ
4
(
T
O
L
)
-
I
d
]
B
4
(
δ
T
2
-
T
O
L
)
(
δ
T
2
-
T
O
L
)
]
+
A
5
-
1
[
φ
5
(
δ
T
2
-
T
O
L
)
-
I
d
]
B
5
(
(
1
-
δ
)
T
2
)
]
+
A
6
-
1
[
φ
6
(
(
1
-
δ
)
T
2
)
-
I
d
]
B
6
U
.


## 3.3. Half-Cycle Model

The waveformi
L
S of Figure 2 shows that operation modes IV, V, and VI are mirrors of Modes I, II, and III, respectively; therefore, the first three operation modes are sufficient to describe the function of the converter. A particular matrix titled asW may relate the modes I, II, and III with the modes IV, V, and VI, which satisfies the condition W
W
=
I
d, the identity matrix. Therefore, the half-cycle model of the ZVT converter may be obtained replacing the terms A
4, A
5, A
6, B
4, B
5, and B
6 by expressions W
A
1, W
A
2, W
A
3, W
B
1, W
B
2, and W
B
3, respectively, in (18), such that the half-cycle model is
(19)
X
(
t
1
+
T
2
)
=
φ
3
(
(
1
-
δ
)
T
2
)
φ
2
(
δ
T
2
-
T
O
L
)
φ
1
(
T
O
L
)
X
(
t
1
)
+
[
φ
3
(
(
1
-
δ
)
T
2
)
φ
2
φ
3
(
(
1
-
δ
)
T
2
)
φ
2
×
(
δ
T
2
-
T
O
L
)
A
1
-
1
[
φ
1
(
T
O
L
)
-
I
d
]
B
1
+
φ
3
(
(
1
-
δ
)
T
2
)
A
2
-
1
[
φ
2
(
δ
T
2
-
T
O
L
)
-
I
d
]
B
2
+
A
3
-
1
[
φ
3
(
(
1
-
δ
)
T
2
)
-
I
d
]
B
3
]
U
+
W
(
[
φ
3
(
(
1
-
δ
)
T
2
)
-
I
d
]
φ
3
(
(
1
-
δ
)
T
2
)
(
φ
2
(
δ
T
2
-
T
O
L
)
×
W
φ
1
(
T
O
L
)
X
(
t
1
)
+
φ
3
(
(
1
-
δ
)
T
2
)
×
φ
2
(
δ
T
2
-
T
O
L
)
A
1
-
1
×
[
φ
1
(
T
O
L
)
-
I
d
]
B
1
(
δ
T
2
-
T
O
L
)
)
+
φ
3
(
(
1
-
δ
)
T
2
)
A
2
-
1
×
[
φ
2
(
δ
T
2
-
T
O
L
)
-
I
d
]
B
2
+
A
3
-
1
[
φ
3
(
(
1
-
δ
)
T
2
)
-
I
d
]
W
B
3
)
U
(
t
1
)
.The previous equation may be rewritten asX
(
t
1
+
T
/
2
)
=
A
MC
X
(
t
1
)
+
B
MC
U
(
t
1
) for practical purposes.


## 3.4. Sample-Data, Small-Signal Linear Model of the Converter in Open-Loop Conditions

The equationX
(
t
1
+
T
/
2
)
=
A
MC
X
(
t
1
)
+
B
MC
U
(
t
1
) may be used as a half-cycle, discrete model of the ZVT converter, which may be written as
(20)
X
K
+
1
′
=
A
MC
X
K
+
B
MC
U
K
,
where X
K
+
1
′
=
X
(
t
1
+
T
/
2
), X
K
=
X
(
t
1
), and U
K
=
U
(
t
1
)A sample-data, small-signal model may be obtained by using the Taylor series, (21), and using small-signal perturbations as δ
x
K, δ
U
K, δ
T
O
L
k and δ
δ
K. One has
(21)
f
(
x
)
=
f
(
x
0
)
+
J
(
x
-
x
0
)
.Using this equation, the sample-data, small-signal linear model becomes(22)
δ
x
k
+
1
≈
∂
x
k
+
1
∂
x
k
δ
x
k
+
∂
x
k
+
1
∂
U
k
δ
U
k
+
∂
x
k
+
1
∂
δ
δ
δ
k
+
∂
x
k
+
1
∂
T
O
L
δ
T
O
L
k
.
The solution of the partial derivatives is ∂
x
k
+
1
/
∂
x
k
=
A
MC,  ∂
x
k
+
1
/
∂
U
k
=
B
MC,  ∂
x
k
+
1
/
∂
δ
=
C
δ, and ∂
x
k
+
1
/
∂
T
O
L
=
D
T
O
L.  δ
T
O
L
k may be determined utilizing the restriction equation of T
O
L, whereas δ
δ
K is obtained using the restriction equation of δ.


## 3.5. Restriction Equations of the Control Loop

The restriction equations forT
O
L may be obtained analyzing the waveforms i
L
S, i
D
1
,
D
3, and i
sum, which are shown in Figure 2 during the Mode I. The slope of i
sum during Mode I is named g
1 and is determined by the rate of change of i
L
S; that is, g
1
=
V
s
k
/
L
S, while the slopes of i
D
1
,
D
3 during the Mode I are named g
3, which are contrary and of lower amplitude than g
1; that is, g
3
=
-
g
1
/
2
N. The restriction equation of T
O
L may be determined by integrating the waveforms i
D
1
,
D
3 during Mode I:
(23)
i
L
S
k
2
N
+
i
L
f
k
2
+
V
s
k
L
S
T
O
L
k
=
0
.The previous equation is not linear; therefore, it is necessary to use the Taylor series to obtain a linearized model:(24)
δ
T
O
L
k
=
2
N
L
S
V
S
CD
[
-
1
2
N
-
1
2
-
T
O
L
CD
2
N
L
S
]
[
δ
i
L
S
k
δ
i
L
f
k
δ
V
s
k
]
.The restriction equation ofδ may be obtained analyzing the waveforms i
L
S and i
sum with v
i
REF
-
v
SAW during Mode II (Figures 2 and 5). v
SAW is determined by M
(
δ
k
T
/
2
) and the slope of i
sum during Mode II, named g
2, and may be obtained by integrating again i
sumwhen R
s
i
sum
=
v
i
REF
-
v
SAW:
(25)
R
s
(
i
L
S
k
+
g
1
T
O
L
k
+
g
2
(
δ
k
T
2
-
T
O
L
k
)
)
=
V
i
REF
-
M
δ
k
T
2
.The Taylor series is used to linearize the previous equation, and therefore the restriction equation ofδ becomes
(26)
δ
δ
k
=
1
Δ
δ
[
a
δ
1
a
δ
2
a
δ
3
a
δ
4
a
δ
5
]
[
δ
i
L
S
k
δ
i
L
f
k
δ
V
s
k
δ
V
i
REF
k
δ
V
o
k
]
,
where Δ
δ
=
-
(
2
/
T
)
/
(
M
T
/
2
R
S
+
1
/
(
L
S
+
(
1
/
N
2
)
L
f
)
)
(
v
s
CD
-
(
1
/
N
)
v
0
CD
), a
δ
1
=
∂
i
L
S
k
/
∂
i
L
S
k, a
δ
2
=
∂
i
L
S
k
/
∂
i
L
f
k, a
δ
3
=
∂
i
L
S
k
/
∂
V
S
k, a
δ
4
=
∂
i
L
S
k
/
∂
V
i
REF
k, and a
δ
5
=
∂
i
L
S
k
/
∂
V
o
k.


## 3.6. Sample-Data, Small-Signal Linear Model of the Converter in Closed-Loop Conditions

The sample-data, small-signal linear model, may be obtained by substitutingδ
T
O
L
k and δ
δ
K, (24) and (26), respectively, in (22):
(27)
δ
x
k
+
1
=
A
MC
[
δ
i
L
S
k
δ
i
L
f
k
δ
V
s
k
]
+
B
MC
[
δ
V
s
k
δ
I
Z
k
]
+
C
δ
(
1
Δ
δ
[
a
δ
1
a
δ
2
a
δ
3
a
δ
4
a
δ
5
]
[
δ
i
L
S
k
δ
i
L
f
k
δ
V
s
k
δ
V
i
REF
k
δ
V
o
k
]
)
+
D
T
O
L
(
2
N
L
S
V
S
CD
[
-
1
2
N
-
1
2
-
T
O
L
CD
2
N
L
S
]
[
δ
i
L
S
k
δ
i
L
f
k
δ
V
s
k
]
)
,
such that the small-signal model becomes
(28)
δ
x
k
+
1
=
A
c
l
δ
x
k
+
ω
c
l
δ
w
c
l
k
,
where δ
x
k
+
1
=
[
δ
i
L
S
k
′
δ
i
L
f
k
′
δ
V
s
k
′
]
T, δ
x
k
=
[
δ
i
L
S
k
δ
i
L
f
k
δ
V
s
k
]
′, and δ
w
c
l
k
=
[
δ
V
s
k
δ
V
i
REF
k
δ
I
Z
k
]
T.Equation (28) may be solved by using the Z transform, such that δ
x
K becomes
(29)
δ
x
k
=
(
I
d
-
A
c
l
)
-
1
Z
ω
c
l
δ
w
c
l
k
.


## 3.7. Transfer Function

To verify the dynamic characteristics of the converter is necessary to analyze the transfer functions that relatev
o with V
s, v
i
REF, and I
z, which are the throughput input-to-output DC voltage transfer function, H
v
(
z
)
=
v
o
(
z
)
/
v
s
(
z
), the control-to-output transfer function, T
O
L
(
z
)
=
v
o
(
z
)
/
v
i
REF
(
z
), and the output impedance transfer function Z
o
(
z
)
=
v
o
(
z
)
/
I
z
(
z
), respectively.The magnitude and phase of each transfer function may be obtained using a Bode diagram, whereas the root locus technique may be employed to describe the behaviour of the poles and zeros of (30). One has
(30)
H
v
(
z
)
=
z
+
a
1
z
2
+
b
1
z
+
c
1
,
T
O
L
(
z
)
=
a
2
z
2
+
b
2
z
+
c
2
z
2
+
b
1
z
+
c
1
,
Z
o
(
z
)
=
a
3
z
2
+
b
3
z
-
c
3
z
2
+
b
1
z
+
c
1
.


## 4. Verification of the Proposed Model

### 4.1. Prototype Operating Parameters

A 250 W ZVT DC-DC prototype converter was designed under the analysis described in [7] to verify the large-signal model of (14). Table 1 shows the operating parameters of the converter.Table 1
Operating parameters.
Supply voltage
200 V ± 20%
Output voltage
48 V
Maximum power
250 W
Minimum power
50 W
Output voltage ripple
25 mV
Output current ripple
300 mA
Maximum phase
50%
Switching frequency
50 kHzThe steady-state output voltage,V
O, may be calculated as the average of the rectified voltage v
D
D, such that at full load
(31)
V
o
=
δ
max
⁡
N
V
in
-
4
N
2
I
o
(
max
⁡
)
L
S
T
.Taking the assumption shown in (31), the converter component values must comply with the zero-voltage switching phenomena to reduce the transistor switching losses under a certain load range. For instance, L
S should be large enough to keep the converter operation with ZVT under a low load condition, whilst N should be small to maintain regulated output voltage for a maximum input voltage. The list of parameters shown in Table 1, together with (31), defines the component values that may be used to keep the DC-DC converter operating with the ZVT effect within a load range of 50 W to 250 W, and the values shown in Table 2 were decided to be appropriate for the converter design. The output filter components of the rectifier were determined with the output voltage ripple, Δ
V
O, and the filter inductor current ripple, Δ
I
O, which may be calculated by using
(32)
Δ
I
o
=
2
V
o
ω
L
f
{
π
2
sin
⁡
(
cos
⁡
-
1
⁡
(
2
π
)
)
-
cos
⁡
-
1
⁡
(
2
π
)
}
,
Δ
V
o
=
T
Δ
I
o
8
C
.Table 2
Component values used in the 250 W prototype.
Devices
Value
Stray inductance (L
S)
16.35 uH
Filter inductor (L
f)
528 uH
Filter capacitor (C
f)
12.18 uF
Resistive load
9.216Ω
Transformer turns ratioN
0.683


### 4.2. Simulation and Results

The piece-wise linear model, the large-signal model, and the half-cycle model of the converter were verified by iterative program developed in MatLab. The piece-wise model was solved using the Runge-Kutta numerical method and using a small simulation step time, together withT
O
L and δ, to calculate the duration of each operating mode, whereas the large-signal model and half-cycle model were solved by calculating T
O
L and δ with the Newton-Raphson method. Figures 6 to 9 show a comparison of the results obtained with the piece-wise model and simulation results obtained with Micro-Cap. The waveforms plotted on these figures are the transformer primary-side current i
L
S, Figure 6, the filter inductor current i
L
f, Figure 7, the output voltage v
O, Figure 8, and the supply current i
sum together with v
SAW
-
v
i
REF, Figure 9. Tables 3 and 4 show a comparison of the instantaneous values of the state vector obtained at the end of a full cycle in steady state conditions, which verifies the exactitude of the large-signal model, whereas Table 4 shows those of the half-cycle model. Both tables list results together with instantaneous results obtained with Micro-Cap. The value of T
O
L calculated for Modes I and IV is 0.727µswhile δ is 0.3998.Table 3
Verification of the large-signal model.
X
(
t
1
) large-signal model
X
(
t
1
+
T
) large-signal model
X
(
t
1
+
T
) verification
% error
i
L
S
−3.5292
−3.529
−3.5304
0.04%
i
L
f
5.0171
5.017
5.0063
0.2%
V
o
48.035
48.019
48.002
0.4%Table 4
Verification of the half-cycle model.
X
(
t
1
) half-cycle model
X
(
t
1
+
T
/
2
) half-cycle model
X
(
t
1
+
T
/
2
) verification
% error
i
L
S
−3.415
3.47
3.4153
0.016%
i
L
f
4.954
4.957
4.8431
0.023%
V
o
48.53
48.53
47.1245
0.029%Table 5
Definition of matrix for each mode of operation.
Mode I
A
1
[
i
L
S
′
i
L
f
′
V
o
′
]
=
[
0
0
0
0
0
-
1
L
f
0
1
C
f
-
1
R
C
f
]
[
i
L
S
i
L
f
V
o
]
+
[
1
L
S
0
0
0
0
1
C
f
]
[
V
s
I
Z
]
B
1
[
i
sec
i
D
1
i
D
2
i
sum
]
=
[
1
N
0
0
1
2
N
1
2
0
-
1
2
N
1
1
2
0
0
0
]
[
i
L
S
i
L
f
V
o
]
+
[
0
0
0
0
0
0
]
[
V
s
I
Z
]
Mode II
A
2
[
i
L
S
′
i
L
f
′
V
o
′
]
=
[
0
0
-
N
(
N
2
L
S
+
L
f
)
0
0
-
1
(
N
2
L
S
+
L
f
)
0
1
C
f
-
1
R
C
f
]
[
i
L
S
i
L
f
V
o
]
+
[
N
2
(
N
2
L
S
+
L
f
)
0
N
(
N
2
L
S
+
L
f
)
0
0
1
C
f
]
[
V
s
I
Z
]
B
2
[
i
sec
i
D
1
i
D
2
i
sum
]
=
[
0
1
0
0
1
0
0
1
0
N
0
0
]
[
i
L
S
i
L
f
V
o
]
+
[
0
0
0
0
0
0
]
[
V
s
I
Z
]
Mode III
A
3
[
i
L
S
′
i
L
f
′
V
o
′
]
=
[
0
0
-
N
(
N
2
L
S
+
L
f
)
0
0
-
1
(
N
2
L
S
+
L
f
)
0
1
C
f
-
1
R
C
f
]
[
i
L
S
i
L
f
V
o
]
+
[
0
0
0
0
0
1
C
f
]
[
V
s
I
Z
]
B
3
[
i
sec
i
D
1
i
D
2
i
sum
]
=
[
0
1
0
0
1
0
0
0
0
0
0
0
]
[
i
L
S
i
L
f
V
o
]
+
[
0
0
0
0
0
0
]
[
V
s
I
Z
]
Mode IV
A
4
[
i
L
S
′
i
L
f
′
V
o
′
]
=
[
0
0
0
0
0
-
1
L
f
0
1
C
f
-
1
R
C
f
]
[
i
L
S
i
L
f
V
o
]
+
[
-
1
L
S
0
0
0
0
1
C
f
]
[
V
s
I
Z
]
B
4
[
i
sec
i
D
1
i
D
2
i
sum
]
=
[
1
N
0
0
1
2
N
1
2
0
-
1
2
N
-
1
1
2
0
0
0
]
[
i
L
S
i
L
f
V
o
]
+
[
0
0
0
0
0
0
]
[
V
s
I
Z
]
Mode V
A
5
[
i
L
S
′
i
L
f
′
V
o
′
]
=
[
0
0
N
(
N
2
L
S
+
L
f
)
0
0
-
1
(
N
2
L
S
+
L
f
)
0
1
C
f
-
1
R
C
f
]
[
i
L
S
i
L
f
V
o
]
+
[
-
N
2
(
N
2
L
S
+
L
f
)
0
N
(
N
2
L
S
+
L
f
)
0
0
1
C
f
]
[
V
s
I
Z
]
B
5
[
i
sec
i
D
1
i
D
2
i
sum
]
=
[
0
-
1
0
0
0
0
0
-
1
1
N
0
0
]
[
i
L
S
i
L
f
V
o
]
+
[
0
0
0
0
0
0
]
[
V
s
I
Z
]
Mode VI
A
6
[
i
L
S
′
i
L
f
′
V
o
′
]
=
[
0
0
N
(
N
2
L
S
+
L
f
)
0
0
-
1
(
N
2
L
S
+
L
f
)
0
1
C
f
-
1
R
C
f
]
[
i
L
S
i
L
f
V
o
]
+
[
0
0
0
0
0
1
C
f
]
[
V
s
I
Z
]
B
6
[
i
sec
i
D
1
i
D
2
i
sum
]
=
[
0
-
1
0
0
0
0
0
0
1
0
0
0
]
[
i
L
S
i
L
f
V
o
]
+
[
0
0
0
0
0
0
]
[
V
s
I
Z
]Figure 6
i
L
S current waveform obtained with the piece-wise linear model and a Micro-Cap simulation.Figure 7
i
L
f current waveform obtained with the piece-wise linear model and a Micro-Cap simulation.Figure 8
v
o voltage waveform obtained with the piece-wise linear model and a Micro-Cap simulation.Figure 9
Waveforms ofi
sum and v
SAW
-
v
i
REF obtained with the piece-wise linear model and a Micro-Cap simulation.Figures10, 11, and 12 show the bode diagram of the transfer functions H
v
(
z
)
,
T
O
L
(
z
), and Z
o
(
z
) calculated with the symbolic equation tool of MatLab, whilst Figures 13, 14, and 15 show the roots locus of H
v
(
z
)
,
T
O
L
(
z
)
, and Z
o
(
z
).Figure 10
Bode plot ofH
v
(
z
)
.Figure 11
Bode plot ofT
O
L
(
z
)
.Figure 12
Bode plot ofZ
o
(
z
).Figure 13
Root locus ofH
v
(
z
).Figure 14
Root locus ofT
O
L
(
z
).Figure 15
Root locus ofZ
(
z
).The magnitude ofH
v
(
z
) at low frequency converges to the steady-state DC of v
o
-
DC
/
V
s, while the magnitude of T
O
L
(
z
) reveals the gain of the control-to-output under dynamic conditions, and the magnitude of Z
(
z
) converges to small value below and above the resonant frequency determined by 1
/
L
f
+
N
2
L
S
/
C
f.The poles ofH
V
(
z
) are conjugates complex roots, whereas there is a single zero located at −2.75. T
O
L
(
z
) is steady with a gain lower than 0.596 dB, and its poles are conjugates complex roots with two steady zeros. Z
o
(
z
) is steady with a gain lower than 0.0682 dB, and its poles are conjugates complex roots, and there are two zeros located at −3.93 and 0.93.To design a controller is necessary to determine the behaviour of the poles and zeros of the transfer functions with respect to variations ofδ, M, and R
s. Figure 16 shows diverse root locus plots of H
V
(
z
), T
O
L
(
z
), and Z
o
(
z
) by ranging the values of δ
,
M
, and R
s.Figure 16
Root locus plots ofH
v
(
z
), T
O
L
(
z
), and Z
O
(
z
) obtained by ranging of δ, M, and R
s.


## 4.1. Prototype Operating Parameters

A 250 W ZVT DC-DC prototype converter was designed under the analysis described in [7] to verify the large-signal model of (14). Table 1 shows the operating parameters of the converter.Table 1
Operating parameters.
Supply voltage
200 V ± 20%
Output voltage
48 V
Maximum power
250 W
Minimum power
50 W
Output voltage ripple
25 mV
Output current ripple
300 mA
Maximum phase
50%
Switching frequency
50 kHzThe steady-state output voltage,V
O, may be calculated as the average of the rectified voltage v
D
D, such that at full load
(31)
V
o
=
δ
max
⁡
N
V
in
-
4
N
2
I
o
(
max
⁡
)
L
S
T
.Taking the assumption shown in (31), the converter component values must comply with the zero-voltage switching phenomena to reduce the transistor switching losses under a certain load range. For instance, L
S should be large enough to keep the converter operation with ZVT under a low load condition, whilst N should be small to maintain regulated output voltage for a maximum input voltage. The list of parameters shown in Table 1, together with (31), defines the component values that may be used to keep the DC-DC converter operating with the ZVT effect within a load range of 50 W to 250 W, and the values shown in Table 2 were decided to be appropriate for the converter design. The output filter components of the rectifier were determined with the output voltage ripple, Δ
V
O, and the filter inductor current ripple, Δ
I
O, which may be calculated by using
(32)
Δ
I
o
=
2
V
o
ω
L
f
{
π
2
sin
⁡
(
cos
⁡
-
1
⁡
(
2
π
)
)
-
cos
⁡
-
1
⁡
(
2
π
)
}
,
Δ
V
o
=
T
Δ
I
o
8
C
.Table 2
Component values used in the 250 W prototype.
Devices
Value
Stray inductance (L
S)
16.35 uH
Filter inductor (L
f)
528 uH
Filter capacitor (C
f)
12.18 uF
Resistive load
9.216Ω
Transformer turns ratioN
0.683


## 4.2. Simulation and Results

The piece-wise linear model, the large-signal model, and the half-cycle model of the converter were verified by iterative program developed in MatLab. The piece-wise model was solved using the Runge-Kutta numerical method and using a small simulation step time, together withT
O
L and δ, to calculate the duration of each operating mode, whereas the large-signal model and half-cycle model were solved by calculating T
O
L and δ with the Newton-Raphson method. Figures 6 to 9 show a comparison of the results obtained with the piece-wise model and simulation results obtained with Micro-Cap. The waveforms plotted on these figures are the transformer primary-side current i
L
S, Figure 6, the filter inductor current i
L
f, Figure 7, the output voltage v
O, Figure 8, and the supply current i
sum together with v
SAW
-
v
i
REF, Figure 9. Tables 3 and 4 show a comparison of the instantaneous values of the state vector obtained at the end of a full cycle in steady state conditions, which verifies the exactitude of the large-signal model, whereas Table 4 shows those of the half-cycle model. Both tables list results together with instantaneous results obtained with Micro-Cap. The value of T
O
L calculated for Modes I and IV is 0.727µswhile δ is 0.3998.Table 3
Verification of the large-signal model.
X
(
t
1
) large-signal model
X
(
t
1
+
T
) large-signal model
X
(
t
1
+
T
) verification
% error
i
L
S
−3.5292
−3.529
−3.5304
0.04%
i
L
f
5.0171
5.017
5.0063
0.2%
V
o
48.035
48.019
48.002
0.4%Table 4
Verification of the half-cycle model.
X
(
t
1
) half-cycle model
X
(
t
1
+
T
/
2
) half-cycle model
X
(
t
1
+
T
/
2
) verification
% error
i
L
S
−3.415
3.47
3.4153
0.016%
i
L
f
4.954
4.957
4.8431
0.023%
V
o
48.53
48.53
47.1245
0.029%Table 5
Definition of matrix for each mode of operation.
Mode I
A
1
[
i
L
S
′
i
L
f
′
V
o
′
]
=
[
0
0
0
0
0
-
1
L
f
0
1
C
f
-
1
R
C
f
]
[
i
L
S
i
L
f
V
o
]
+
[
1
L
S
0
0
0
0
1
C
f
]
[
V
s
I
Z
]
B
1
[
i
sec
i
D
1
i
D
2
i
sum
]
=
[
1
N
0
0
1
2
N
1
2
0
-
1
2
N
1
1
2
0
0
0
]
[
i
L
S
i
L
f
V
o
]
+
[
0
0
0
0
0
0
]
[
V
s
I
Z
]
Mode II
A
2
[
i
L
S
′
i
L
f
′
V
o
′
]
=
[
0
0
-
N
(
N
2
L
S
+
L
f
)
0
0
-
1
(
N
2
L
S
+
L
f
)
0
1
C
f
-
1
R
C
f
]
[
i
L
S
i
L
f
V
o
]
+
[
N
2
(
N
2
L
S
+
L
f
)
0
N
(
N
2
L
S
+
L
f
)
0
0
1
C
f
]
[
V
s
I
Z
]
B
2
[
i
sec
i
D
1
i
D
2
i
sum
]
=
[
0
1
0
0
1
0
0
1
0
N
0
0
]
[
i
L
S
i
L
f
V
o
]
+
[
0
0
0
0
0
0
]
[
V
s
I
Z
]
Mode III
A
3
[
i
L
S
′
i
L
f
′
V
o
′
]
=
[
0
0
-
N
(
N
2
L
S
+
L
f
)
0
0
-
1
(
N
2
L
S
+
L
f
)
0
1
C
f
-
1
R
C
f
]
[
i
L
S
i
L
f
V
o
]
+
[
0
0
0
0
0
1
C
f
]
[
V
s
I
Z
]
B
3
[
i
sec
i
D
1
i
D
2
i
sum
]
=
[
0
1
0
0
1
0
0
0
0
0
0
0
]
[
i
L
S
i
L
f
V
o
]
+
[
0
0
0
0
0
0
]
[
V
s
I
Z
]
Mode IV
A
4
[
i
L
S
′
i
L
f
′
V
o
′
]
=
[
0
0
0
0
0
-
1
L
f
0
1
C
f
-
1
R
C
f
]
[
i
L
S
i
L
f
V
o
]
+
[
-
1
L
S
0
0
0
0
1
C
f
]
[
V
s
I
Z
]
B
4
[
i
sec
i
D
1
i
D
2
i
sum
]
=
[
1
N
0
0
1
2
N
1
2
0
-
1
2
N
-
1
1
2
0
0
0
]
[
i
L
S
i
L
f
V
o
]
+
[
0
0
0
0
0
0
]
[
V
s
I
Z
]
Mode V
A
5
[
i
L
S
′
i
L
f
′
V
o
′
]
=
[
0
0
N
(
N
2
L
S
+
L
f
)
0
0
-
1
(
N
2
L
S
+
L
f
)
0
1
C
f
-
1
R
C
f
]
[
i
L
S
i
L
f
V
o
]
+
[
-
N
2
(
N
2
L
S
+
L
f
)
0
N
(
N
2
L
S
+
L
f
)
0
0
1
C
f
]
[
V
s
I
Z
]
B
5
[
i
sec
i
D
1
i
D
2
i
sum
]
=
[
0
-
1
0
0
0
0
0
-
1
1
N
0
0
]
[
i
L
S
i
L
f
V
o
]
+
[
0
0
0
0
0
0
]
[
V
s
I
Z
]
Mode VI
A
6
[
i
L
S
′
i
L
f
′
V
o
′
]
=
[
0
0
N
(
N
2
L
S
+
L
f
)
0
0
-
1
(
N
2
L
S
+
L
f
)
0
1
C
f
-
1
R
C
f
]
[
i
L
S
i
L
f
V
o
]
+
[
0
0
0
0
0
1
C
f
]
[
V
s
I
Z
]
B
6
[
i
sec
i
D
1
i
D
2
i
sum
]
=
[
0
-
1
0
0
0
0
0
0
1
0
0
0
]
[
i
L
S
i
L
f
V
o
]
+
[
0
0
0
0
0
0
]
[
V
s
I
Z
]Figure 6
i
L
S current waveform obtained with the piece-wise linear model and a Micro-Cap simulation.Figure 7
i
L
f current waveform obtained with the piece-wise linear model and a Micro-Cap simulation.Figure 8
v
o voltage waveform obtained with the piece-wise linear model and a Micro-Cap simulation.Figure 9
Waveforms ofi
sum and v
SAW
-
v
i
REF obtained with the piece-wise linear model and a Micro-Cap simulation.Figures10, 11, and 12 show the bode diagram of the transfer functions H
v
(
z
)
,
T
O
L
(
z
), and Z
o
(
z
) calculated with the symbolic equation tool of MatLab, whilst Figures 13, 14, and 15 show the roots locus of H
v
(
z
)
,
T
O
L
(
z
)
, and Z
o
(
z
).Figure 10
Bode plot ofH
v
(
z
)
.Figure 11
Bode plot ofT
O
L
(
z
)
.Figure 12
Bode plot ofZ
o
(
z
).Figure 13
Root locus ofH
v
(
z
).Figure 14
Root locus ofT
O
L
(
z
).Figure 15
Root locus ofZ
(
z
).The magnitude ofH
v
(
z
) at low frequency converges to the steady-state DC of v
o
-
DC
/
V
s, while the magnitude of T
O
L
(
z
) reveals the gain of the control-to-output under dynamic conditions, and the magnitude of Z
(
z
) converges to small value below and above the resonant frequency determined by 1
/
L
f
+
N
2
L
S
/
C
f.The poles ofH
V
(
z
) are conjugates complex roots, whereas there is a single zero located at −2.75. T
O
L
(
z
) is steady with a gain lower than 0.596 dB, and its poles are conjugates complex roots with two steady zeros. Z
o
(
z
) is steady with a gain lower than 0.0682 dB, and its poles are conjugates complex roots, and there are two zeros located at −3.93 and 0.93.To design a controller is necessary to determine the behaviour of the poles and zeros of the transfer functions with respect to variations ofδ, M, and R
s. Figure 16 shows diverse root locus plots of H
V
(
z
), T
O
L
(
z
), and Z
o
(
z
) by ranging the values of δ
,
M
, and R
s.Figure 16
Root locus plots ofH
v
(
z
), T
O
L
(
z
), and Z
O
(
z
) obtained by ranging of δ, M, and R
s.


## 5. Conclusion

This paper presented the mathematical derivation of a sample-data, small-signal model for a ZVT DC-DC converter. The method used a piece-wise linear analysis to obtain a large-signal model which was verified with numerical predictions that depend on the integration step size to obtain high accuracy. A sample-data, half-cycle linear model was derived using the large-signal model, such that a dynamic model of the converter was obtained by using a linear approximation. A comparison of the instantaneous values listed in Tables3 and 4 showed that there is close correspondence between the derived models and the circuit simulation, especially with the half-cycle model. Also, Bode diagrams and a root locus analysis showed that the control system may be steady if δ is defined within an interval of 0.3 to 0.6, R
s within 0.9 V/A to 1.2 V/A, andM within 0.044 V/s to 0.1 V/s. Therefore, the half-cycle model is more accurate than the large-signal model, and it is useful to determine a small-signal, sample-data model of the DC-DC converter for dynamic studies. The presented method may help to power electronic practitioners to derive discrete transfer functions of soft switched DC-DC converter and understand the dynamic behaviour of power electronic systems, which serves as a basic principle to design a controller for the converter outer loop.



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*Source: 712360-2014-06-02.xml*