# A 12 dB 0.7 V850μW  CMOS LNA for 866 MHz UHF RFID Reader

Authors: Jie Li; S. M. Rezaul Hasan
Journal: Active and Passive Electronic Components
 (2010)

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## Abstract

The design of a narrow-band cascode CMOS inductive source-degenerated low noise amplifier (LNA) for 866 MHz UHF RFID reader is presented. Compared to other previously reported narrow-band LNA designs, in this paper the finitegds  (=1/r0) effect has been considered to improve the nanometric design,  achieving simultaneous impedance and minimum Fmin noise matching at a very low power drain of 850 μW from a 0.7 V supply voltage. The LNA was fabricated using the IBM 130 nm CMOS process  delivering a forward power gain (S21) of ≈12dB, a reverse  isolation (S12) of  ≈−34dB, an output power reflection (S22 @866 MHz) of  ≈−25dB, and an input power reflection (S11 @866 MHz) of ≈−12dB. It had a minimum pass-band NF of around 2.2 dB and a third-order input referred intercept point (IIP3) of ≈−11.5dBm.


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## Body

## 1. Introduction

RFID (radio-frequency identification) is one of the fastest growing wireless communication technologies for commercial product tracking. As the low noise amplifier (LNA) is the first block in the front-end of the RFID reader which is tuned at a certain transreceiver frequency, it needs to be designed optimally to minimize the noise for the following stages and avoid the distortion of the source signal (requires good linearity). To overcome design trade-off difficulties between gain, power, noise figure(NF) and matching in the optimization of the LNA, the design of the matching circuits at the input and the output are based, respectively, on minimal NF and maximal power transfer. In recent years, considerable research on CMOS LNA design in submicron technologies at 900 MHz have been reported by many authors in    [1–4]. A lower frequency standard for UHF RFID at 866 MHz is also implemented in Europe, Africa, and New Zealand. Low power dissipation at low supply voltage is a significant design criterion for RFID applications synthesized by design trade-off between gain, NF, input and output impedance matching and high linearity. In this paper we discuss the design and the experimental results for a 0.7 V low-power 130 nm CMOS 866 MHz single-ended common-source telescopic cascode LNA using an enhanced power constrained simultaneous noise and impedance matching (PCSNIM [5, 6]) technique.


## 2. Principles and Circuit Design

An inductively source degenerated telescopic cascode topology has been chosen for the 866 MHz RFID LNA design due to its current reuse structure and hence it consumes less bias current than the folded cascode. Figure1 shows the circuit diagram of the proposed RFID LNA. M1 and M2 forms the cascode configuration and their bias currents are driven by M3 and Rref. Ld, Rd, and Cd form the output tank circuit tuned at 866 MHz with an angular frequency bandwidth of 1/(Rd*Cd). Cac denotes ac-coupling capacitor (one at the source input and the other at the output load) while Cb is an ac grounding capacitor at the gate of the cascoding device M2. Ls provides the inductive source degeneration. An improved PCSNIM technique is adopted here for the telescopic cascode LNA structure optimization. Ce is in parallel with Cgs1 of M1 in order to achieve minimum noise figure Fmin with power constraint and higher unity gain frequency ωT. Optimal impedance Zopt for noise match can be derived to achieve the theoretical Fmin [5, 6]. The effect of the finite device conductance gds(=1/r0) due to the deeply scaled short channel length is included in this design optimization. With regard to the input impedance matching at resonance, we can easily derive(1)Zin≅gm1CtLsgm2(gds1+gm2),
where Ct equals Cgs1+Ce, gds1(=1/ro1) is the output conductance of M1, while gm1 and gm2 are the transconductances of the cascode transistors M1 and M2, respectively. Typically Zin at resonance changed by 6%–12% due to the inclusion of gds1 in (1) as indicated by the plot in Figure 2 of the analytical Zin with variation in the ro1 of M1 (being around 450 ohms in this design) from the long channel assumption (ro1→∞). In addition, as shown in Figure 2, the extent of Zin inaccuracy with long channel assumption also varies with the chosen value of Ls, the source inductor. Equation (1) also indicates that for deep nanometric design the finite output conductance of M1 adds an additional trade-off factor in determining the value of the capacitor Ce (in Ct) required for achieving power-constrained input matching. Changing the overdrive and/or the geometry of M2 (and hence gm2) in relation to gds1 provides an additional degree of freedom to reach this value of Ce for input matching. Essentially this trade-off enables a lower value of Ce and hence a higher ωT in achieving input impedance matching for a given gm1. In addition, inclusion of the finite gds effect provides a more accurate power constrained simultaneous optimization of noise and impedance matching for nanometric CMOS (hence it is termed enhanced PCSNIM). The s-domain gain transfer function of the RFID LNA can be determined by first finding the short circuit transconductance (GM1) and then the open circuit output impedance (ZOUTM1) at the drain of M1. Hence, we can deduce the voltage gain as(2)Av(s)=[gm1+((sCt+gm1)(RLs+sLs))/(r01+RLs+sLs)]*(1/(sCd+1/Rd+1/sLd))[1+sCt(Rs+RLg+RLs+Rge+sLg+sLs)+(gm1+sCt)((r01(RLs+sLs))/(r01+RLs+sLs))],where Rs is the source resistance, RLg is the series resistance of the gate inductor, RLs is the series resistance of the source inductor, and Rge is an equivalent gate resistance due to the addition of Ce, which is smaller than the original gate resistance Rg of the transistor M1. The dB magnitude comparison of the theoretical (analytical) gain with the simulated gain is shown in Figure 3 indicating close agreement between the two. A technique based on determining the short circuit output noise current power at the drain of M1 was used for the noise analysis. In this method the output load is shorted compared to the method in [5] where the output noise current is determined with the output load. Since the noise factor is defined as the ratio of the total mean-squared output noise current due to all the noise sources to the input source only, and as the noise factor mostly depends on the front-end noise sources farthest from the output load, almost the same value of noise factor is obtained using this technique without the extra calculation, compared to if the output noise current with load is used in the computation. Hence, the noise factors of the front-end noise sources using this short circuit output noise current method, are added to obtain the overall frequency behavior of the noise factor (N(f)) given by(3)N(f)=1+δ1α15ω2Cgs12Rsgm1{gm1r012Rs-ω2Ls[Ls+gm1r01(Ls+Lg)]}2+ω2r012[Ls(1+gm1Rs)+gm1r01(Lg+Ls)]2ω2Ct2(r012+ω2Ls2)(ωLs+gm1r01/ωCt)2+γ1gm1α1Rsr012{[1-ω2Ct(Lg+Ls)]2+ω2Ct2Rs2}ω2Ct2(ωLs+gm1r01/ωCt)2+2j|c1|ωCgs1r01Rsω2Ct2(ωLs+gm1r01/ωCt)2×δ1γ15𝔄ω2r012[Ls(1+gm1Rs)+gm1r01(Lg+Ls)]2{[1-ω2Ct(Lg+Ls)]2+ω2Ct2Rs2}(r012+ω2Ls2),where 𝔄 denotes {gm1r012Rs-ω2Ls[Ls+gm1r01(Ls+Lg)]}2. It is evident from (3) that inclusion of gds1 (=1/ro1) provides a more detailed expression and hence a more accurate estimate of the noise factor.Figure 1
Proposed narrow-band circuit topology for 866 MHz RFID LNA.Figure 2
Variation of the analyticalZin with finite output impedance (ro1) of M1 for
nanometric CMOS.Figure 3
Analytical and simulated gain-magnitude (AV in dB) of the RFID LNA.


## 3. Simulation and Experimental Results

The LNA (as part T8BTAU) was fabricated using the 130 nm IBM CMOS process available through MOSIS. Figure4 shows the microphotograph of the 0.571 sq.mm die. The outer diameters of the inductors were, respectively, 240 μm for Ld and 140 μm for Ls with 5μm wide trace of top thick aluminum layer MA and underpass contact copper layer E1. The capacitors Ce and Cd were fabricated as MIM (metal-insulator-metal) capacitors, and the resistors were fabricated using p+ poly layer with high-sheet resistance (340 Ω/□). Figure 5 shows the simulated and measured forward power gain, S21 under matched condition [8], indicating reasonably high-Q tuning at 866 MHz with measurement being 4 dB below simulation due to loss along external matching circuit. The measured input reflection coefficient S11 is approximately ≈−12 dB at 866 MHz as shown in Figure 6, while the output reflection coefficient S22 is measured to be ≈−25 dB at 866 MHz as shown in Figure 7. These measurements were carried out using external matching elements and indicates close agreement with the simulation. All measurements include trace and connector losses. Figure 8 shows the comparison of the analytical, simulated and measured NF spectrum which verifies the close approximation provided by (3) due to the inclusion of the finite gds effect. The measured NF was around 2.2 dB. The IIP3 and the 1-dB compression points were determined to be −11.5 dBm and −16.1 dBm, respectively, as shown in Figure 9. Finally, Table 1 shows a summary of performance comparison of the proposed UHF LNA with other UHF LNA designs indicating the low NF achieved at sub-mW power.Table 1
Summary of the 866 MHz UHF RFID LNA performance and comparison with previous UHF LNA designs.
This work[1][2][3][4][5][7]Technology (nm)1302503501803500.25180S11 (dB)−12−11.8−10−29−14−18N/AS21 (dB)127.217.512.5171215S12 (dB)−34−27.4N/A−60−22N/AN/AS22 (dB)−25−20N/A−33N/AN/AN/ANF (dB)2.24.720.73.41.352.9IIP3 (dBm)−11.5−1.8−6−4−5.1−4N/AP1dB (dBm)−16.1−9.3N/A−9−23−15−15Pdiss (mW)0.8519.521.63.91324.32Supply Voltage (V)0.72.52.71.82.31.251.8f0 (MHz)866900900915900900900Figure 4
Microphotograph of the fabricated RFID LNA.Figure 5
Forward gain,S21 (in dB) of the RFID LNA.Figure 6
Input reflection coefficient,S21 (in dB) of the RFID LNA.Figure 7
Output reflection coefficient,S22 (in dB) of the RFID LNA.Figure 8
Noise figure (NF in dB) of the RFID LNA.Figure 9
The IIP3 and 1 dB compression points for the UHF RFID LNA.


## 4. Conclusion

The improved power constrained optimization of an UHF RFID LNA design at 866 MHz considering finitegds effects is presented and measurement results are demonstrated. The design achieves very low NF using only a 0.7 V supply voltage and consuming only 850 μW



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*Source: 702759-2010-06-27.xml*