# Analysis of College Students’ Physical Health Test Data Based on Big Data and Health Promotion Countermeasures

Authors: Ming Li; Fengcai Wang
Journal: Advances in Multimedia
 (2022)

---

## Abstract

In order to improve the data analysis and health promotion effect of college students' physical health test, this paper combines the big data technology to carry out the analysis and health promotion system of college students’ physical health test data. Moreover, this paper analyzes and discusses the overall control strategy of the high-precision time-base calibrator and the time-base phase-locked synchronization method and studies the overall scheme design and system working process of the precision time-base calibrator in combination with the requirements of physical health testing. In addition, this paper conducts mathematical derivation and theoretical simulation analysis on the A/D conversion accuracy, noise source and influence, time-frequency characteristics, and corresponding speed of the second-order generalized integrator and constructs an analysis and health promotion system of college students’ physical health test data. The research results show that the college students’ physical health test data analysis system proposed in this paper has certain reliability, and on this basis, college students' health promotion countermeasures are proposed.


---

## Body

## 1. Introduction

The current era is an era of informatization. With the ever-changing Internet and communication technologies, the era of big data has become prominent in all aspects of our lives, such as the recommendation of hot content from the media and the targeted push of shopping platforms. In such an environment, the data of physical health test will inevitably be further valued to help college students improve their physical health [1]. Due to the unbalanced regional development, colleges and universities in some regions have adopted advanced physical health testing equipment, and the data can be directly collected into the computer system, reducing a lot of manual operations and improving work efficiency. However, in other parts of the country, colleges and universities are still subject to the backward physical health testing environment and equipment, and must manually collect data and manually input it into the computer system. At the same time, no matter whether the equipment is advanced or not, the final data collected by the school for the students' physical health test are only stored, managed, and reported. Schools, teachers, and students all have a deeper understanding and intuitive feeling about the data results of physical health test data that cannot be measured, and they do not care and do not use it. The utilization of physical health test data must be accompanied by the development and construction of soft environments such as data platform systems [2]. Moreover, from a nationwide perspective, the functional modules developed in the data analysis and utilization of the existing physical health test data platforms are very limited and imperfect. At the same time, there is no unified standard for the selection and development of functional modules of college students' physical health test data platform. Therefore, designing and constructing a physical health test data platform for college students is helpful to analyze and summarize the physical health test data in a scientific way. On the one hand, it can provide intuitive analysis results for students and schools from two levels of each student as a whole or each individual student. Moreover, it can accurately and intuitively reflect the specific problems of students' physical quality, so as to formulate specific physical exercise programs to guide college students to participate in sports, and provide a factual basis for the country to promote the healthy development of young people's physical health. On the other hand, it lays a theoretical foundation for the development and construction of the physical health test data platform in colleges and universities across the country [3].The word platform has four meanings: The first meaning refers to the drying platform; the second meaning refers to the workbench setup for the convenience of operation during the production and construction process, and some can be moved and lifted; the third meaning refers to the operating environment of computer hardware or software; and the last meaning generally refers to the environment or conditions required to perform a certain job [4]. College students' physical health test platform refers to the third type, which belongs to the operating environment of computer software, that is, a platform for storage management and statistical analysis of college students' physical health test data. At present, there are different interpretations of the computer data platform. By referring to the interpretation of a large number of relevant documents and the different views of corresponding experts and scholars, combined with the origin and development trend of the computer data platform itself, it can be considered that the computer data platform is a kind of Internet technology that uses information technology, builds an independent server, designs a software client with corresponding functions, realizes data storage, management, statistical analysis, and other functions, and finally realizes a platform for serving professional users and mining the value of data [5]. Continuing on the difference between the data processed by the computer data platform and the service objects, the computer data platform can be further defined in detail. With the advent of advanced Internet technology and the era of big data, the value contained in the physical fitness test data is easier to be tapped and utilized, and the physical fitness test data platform for college students came into being [6]. The college students' physical health test data platform can be understood as a technology through the computer Internet. With the help of more advanced physical health testing instruments and various terminal equipment, based on the physical health test data of college students, the physical health monitoring of students is realized, and the expert system is used to perform statistical analysis on the physical test data to realize the generation of personalized exercise prescriptions for each student, the optimal management of teachers' courses, and a platform to promote the informatization process of school sports work [7].Under the current student physical health test standards, the students' physical health test is relatively low. Many students will have certain health problems in different aspects. The problems of students' health status are mainly manifested in that the students' guided exercise is not in place, the students are not fully exercised, and the students lack a relatively complete exercise plan. Therefore, many students will not be able to successfully test according to the standard in the physical fitness test [8]. In addition, the physical fitness test standards for students are formulated according to the basic age of students, and fully consider the development of students in all aspects. If we want to better promote the improvement of students' physical fitness test standards, we must adopt more effective exercise measures on the basis of the standards so that students can get more complete exercise [9].Different information feedback methods have different corresponding information transmission methods. There are many ways of transmitting information, and the way of transmitting information by comparison is one of them. In the early warning mechanism of college students' physical health, the comparison method can directly reflect the physical status of different college students so that the relevant departments and physical education teachers can pay more attention to the disadvantaged groups, and at the same time, it can also attract students' attention and attention to their own physical health [10]. The construction of the physical health early warning mechanism of college students can apply a new type of three-level early warning. Through different early warning levels, different effects can be produced for different focuses, which can strengthen the educational function of physical health evaluation and achieve the combination of physical health evaluation and physical health monitoring. To urge students to form a benchmark for self-health management and early warning parameters of physical health, the contrast between classmates can make students feel a sense of health crisis, arouse students' intention to consciously improve their physical health status, and promote students' self-care awareness and health risk awareness [11].In the reform of physical education in colleges and universities, students are divided into classes and groups according to the strength of their physique. Using this form of teaching organization, it is necessary to first understand the physical condition of the students, that is, to judge the strength of the students' physique based on the results of the physical fitness assessment, and then group them into groups. According to the physical health status of each group of students, targeted teaching is carried out, which effectively solves the phenomenon of “not enough food” and “can't eat” for some students, and finally promotes the improvement of students’ physical fitness. The quality and ability of students are also a reference for grouping, and the personality differences among students should be minimized as much as possible. Students’ interests and specialties are an important consideration in promoting students’ individuality and ability to fully develop, which is worthy of deep consideration by physical education teachers [12].The network management system of the physical fitness test relies on the functions of the cloud, and is applied to physical education to realize the “flipped classroom”, which also realizes the inquiry and creativity of teaching. The combination of online and offline adds interest and arouses students' strong interest, but in teaching practice, it is necessary to clarify the teaching objects; understand the physical and mental characteristics of students, the basis of learning, and learning needs; and then evaluate and apply physical education methods, clarify the limitations of application, and avoid the unrestrained one [13].The physical health test of college students is formulated by the Ministry of Education and the State Sports General Administration according to the physical quality of domestic college students. All colleges and universities need to strictly implement this regulation. It is necessary to continuously improve the professional quality of college physical education teachers, so as to better guide the physical exercise of college students, thereby improving the pass rate of college students' physical health testing, and at the same time effectively ensuring the scientificity and rationality of college students' physical health testing. [14]. In addition, in the new era, colleges and universities continue to strengthen the individualized development of students' physical strengths. Based on this, colleges and universities need to fully consider the professional quality of physical education teachers in carrying out physical health testing of students, so as to improve physical education teachers' awareness of students' physical health. The importance of the test should not be random because of the low level of attention, which will cause the physical health test of students to be a mere formality, be superficial, and lose its significance and function. In the process of college physical education, the time is only 90 minutes, and it is necessary to guide the students in the course and arrange the content of the examination so that the students' study time will be less and less, which is a measure of the students' physical health. It will also have a certain degree of impact [15].Judging from the actual implementation of the physical health assessment of students, due to the mistakes in the implementation of the colleges and universities, the physical health assessment of students is meaningless. Not only that there will be many unexpected situations in the physical health assessment, mainly manifested as exercise pulling injuries, sprains, etc., but also that some female students cannot participate in the physical health assessment due to special physical conditions, which is unfair and unreasonable for the physical health assessment of students [16].This paper combines the big data technology to analyze the analysis and health promotion system of college students’ physical health test data, and formulate the health promotion countermeasures for college students with the support of the system.


## 2. Design of the College Students' Physical Health Test System

### 2.1. Scheme Design of a High-Precision Time-Base Calibrator

According to the established time-base calibration phase-locked loop control model, combined with the design index requirements, the overall design of the high-precision time-base calibrator is carried out. The time-base calibration synchronization structure is shown in Figure1. The structure consists of a high-precision external time-base source (10 MHz), AD converter, quadrature converter, Park transformer, proportional integrator (PI), VCXO of the calibrated frequency synthesizer, and DDS (direct digital synthesis) sine and cosine signal generation unit. The main body of the high-precision time-base calibrator is a phase-locked loop, the reference signal is quantized by the ADC as the reference clock Vref of the phase-locked loop, and the phase detector adopts a Park transformation structure. Therefore, the quantized signal needs to be orthogonally transformed to obtain the orthogonal signals Vα and Vβ. Orthogonal transformation together with the Park transformation completes the phase relationship verification of the reference clock input signal and the phase-locked loop output signal. The phase relationship verification result Vq is adjusted and fed back to the VCXO voltage control input terminal by the proportional integral unit, and finally, the time-base calibration of the frequency synthesizer is realized. The tuning of the phase-locked loop structure is frequency-dependent. If there is a disturbance in the frequency of the input terminal, the output of the phase-locked frequency will be abnormal, and SOGI is required as an adaptive frequency adjustment unit. When the orthogonal transformation is completed, its frequency response output can be automatically adjusted according to the output frequency of the phase-locked loop. In the process of frequency calibration, SOGI effectively suppresses the high-order harmonics introduced by the disturbance of the sampling clock and relies on the fast frequency response characteristics to make the time-base calibration faster and more accurate.Figure 1
Time-base calibration synchronization structure block diagram.


### 2.2. Structural Design and Working Principle Analysis of the Digital Phase-Locked Loop System

The main components of the digital phase-locked loop include a reference time-base source, A/D conversion module, improved digital phase detector (quadrature transformation and the Park transformation are included), loop filter, proportional integrator, calibrated frequency synthesis device, and DDS frequency synthesis unit.The jitter of the delay unit refers to the time delay (td) of the signal passing through the delay unit, which is the time uncertainty of the delay unit. The variance of voltage random noise is denoted asδ2. Among them, IN is the discharge current of the NMOS, and C is the load capacitance. It is the main source of time uncertainty and jitter. The load capacitance is two uncorrelated white noise sources, that is, the current integrated noise and the initial noise, and the variance can be expressed as follows:(1)δ2=2kTγNCVDDIN2VDD−VtN+kTCIN2,where k is the Boltzmann constant, T is the temperature, VDD is the supply voltage provided, and VtN is the threshold voltage of the NMOS. Obviously, in order to reduce the jitter inside the delay unit, a larger current or a smaller threshold voltage is required. At the same time, the reduced threshold voltage of the transistor will use a larger load capacitance.The output of the time-base source signal in the high-precision time-base calibrator is first undersampled by the sample-and-hold circuit, and then quantized to the digital domain by the ADC. In order to further increase the resolution, an amplifier with high precision, good linearity, and low power consumption is required. An important source of noise in the voltage domain is the capacitance in the sampling circuit. We derive equivalent time uncertainty variance by normalizing the voltage noise to the slope of the input signal.(2)δS2=kT/CVin⋅2π⋅fin,where Vin is the amplitude of the input signal, and fin is the oscillation frequency of the input signal. It can be seen that it is no longer the current that affects the jitter, but the noise on the capacitor. Therefore, a larger capacitance can be used to reduce the noise of the sampling circuit. The noise of the sampling circuit can affect its dynamic range and the effective resolution of the ADC. If the capacitors in the sampling circuit are not optimized, the power consumption of the entire system will also increase. On the contrary, in the time domain, the resolution is improved by adding an amplifying circuit between the time-base reference signal source and the ADC, and the current does not need to be increased.In the case of using the internal reference voltage, when 600 mV and 350 mV ripples are applied to the power supply ports VDD1 and VDD2, respectively, the power supply rejection ratio of VDD1 is greater than 73 dB when the ripple frequency is less than 1 KHz, and the power supply rejection ratio of VDD2 is always maintained at about 85 dB. At room temperature, the internal reference of the AD7626 exhibits a better signal-to-noise ratio and total harmonic distortion than the external reference, as shown in Figure2.Figure 2
Effect of temperature on AD7626 signal-to-noise ratio and total harmonic distortion.The sampling and digitization process of the time-base reference signal is now analyzed in order to reduce the complexity of the digital signal processing by the back-end FPGA, and the digital phase-locked loop mainly focuses on the information such as the phase and the amplitude of the target signal. Therefore, the time-base signal sampling adopts the undersampling mode. The time-base outputs sinusoidal signal frequencyf = 10 MHz, which can be expressed as follows:(3)y=Asin2πft+φ.Among them,φ represents the amplitude, f represents the oscillation frequency, and A represents the initial moment phase. The standard signal is undersampled at the sampling rate of fs, and the sampled digital signal is given by(4)yout=Asin2πffs+φ.According to the Nyquist sampling theorem, for a periodic signal with frequencyf0, the sampling frequency needs to satisfy fs >2 f0. However, under the undersampling condition, there is fs <2 f0. The aliasing that occurs between the sampling frequency and the passband causes the sampling data to be superimposed into harmonic components of multiple frequencies. At this point, the frequency at which the signal is collected is the aliasing frequency. The time-domain state of the acquired signal after undersampling can be determined by calculating the aliasing frequency fout. According to the aliasing mechanism and the calculation formula of the aliasing frequency, the frequency of the output signal after undersampling is determined as follows:(5)fout=N⋅fs−f0.In formula (5), there is N=Intf0/fs+0.5. Int is the rounding operation, fs is the sampling frequency, f0 is the frequency of the sampled signal, and fout is the frequency of the undersampled output signal. The time-base signal of 10 MHz is simulated in MATLAB, and the signal is sampled at a sampling rate of 9 MHz. The entire signal acquisition process is shown in Figure 3.Figure 3
Time-base signal under sampling process simulation.The second-order generalized integral quadrature signal generator can generate the same-phase signal and its quadrature, which mainly contain the fundamental component after filtering. The block diagram of the second-order generalized integrator is shown in Figure4. In the figure, V is the input signal Vref, Vα and Vβ are the in-phase output signal and quadrature output signal of V, respectively, k is the gain coefficient, and ω0 is the resonant frequency of the SOGI system.Figure 4
Second-order generalized integrator.From the block diagram of the second-order generalized integrator, the closed-loop transfer functions of the in-phase and quadrature outputs can be obtained as follows:(6)Hds=VαsVs=kω0ss2+kω0s+ω02,(7)HQs=VβsVs=kω02s2+kω0s+ω02.V(s),Vαs, and Vβs are the s-domain representations of the input signal, in-phase output signal, and quadrature output signal of the SOGI system, respectively. Hds and HQs are the s-domain closed-loop transfer functions for the in-phase and quadrature outputs. The corresponding amplitude-frequency and phase-frequency characteristic expressions are further obtained from the closed-loop transfer function:(8)Hdω=kω0ωkω0ω2+ω2−ω02,(9)φdω=arctanω02−ω2kωω0,(10)HQω=kω02kω0ω2+ω2−ω02,(11)φQω=arctanω02−ω2kωω0−π2In formulas (8)–(11), ω is the frequency of the SOGI input signal V. From the amplitude-frequency characteristics (8) and (10), it is known that SOGI reaches a steady state, that is, when there is Hdω=HQω=1, ω is equal to ω0, which indicates that the two output signals Vα and Vβ of SOGI are of equal amplitude. The phase-frequency characteristics (9) and (11) are compared, and it is known that the system output signals Vα and Vβ have a phase difference of 90 degrees; that is, they are orthogonal to each other.k is the gain coefficient in formulas (6) and (7), and the value of k affects the response speed and frequency characteristics of the quadrature signal generating unit. First, according to the influence of k on the response speed of the system, under the condition of different k values, we simulate the step responses of the closed-loop transfer functions Hds and HQs, and the results are shown in Figure 5. It can be seen from the figure that for Hds, the smaller the k, the slower the system response and the longer the stabilization time. For HQs, the smaller k is, the faster the system responds, but the longer the settling time is.Figure 5
Step response of transfer function for differentk values.k also affects the frequency characteristics of the quadrature signal generating unit. It can be seen from the Bode plot of transfer functionHQs in Figure 6 that when k is greater than 1, the system has a weak amplification of low-frequency noise. The cut-off frequency of the system is 10 MHz, and some frequency components greater than the cut-off frequency can be effectively suppressed, with low-pass filtering performance.Figure 6
Bode plot of transfer functionHQs for different k values.The reference value ofk in the project is 2. In order to make the quadrature signal generation unit achieve the best performance, the response characteristics of the transfer function under different k values and the working stability of the filter algorithm on the FPGA are combined, and the factors such as satisfying the fast response characteristics of the algorithm are comprehensively considered, and the k value is taken as 1.2. Compared with the reference value, under the condition of k = 1.2, the amplifying effect of the system on low-frequency noise can be weakened, and the algorithm application can ensure that the fast response is maintained, and the frequency characteristics are better.The transfer function of SOGI is transformed to the z-domain. According to the principle of bilinear transformation,1/s=TS/21+z−1/1−z−1 can be obtained. It is substituted into (6) and simplified to(12)Hdz=kω02/Tsz−1/z+12/Tsz−1/z+12+kω02/Tsz−1/z+1+ω02.We setx=2kω0TS and y=ω0TS2. Among them, TS is the sampling period of the input terminal to the analog signal V. Formula (12) can be transformed into the standard form:(13)Hdz=x/x+y+4+−x/x+y+4z−21−24−y/x+y+4z−1−x−y−4/x+y+4z−2.We setm0=x/x+y+4m2=−x/x+y+4=−m0, n1=24−y/x+y+4n2=x−y−4/x+y+4, and substitute it into formula (13) to get(14)Hdz=V′zVz=m0+m2z−21−n1z−1−n2z−2.Similarly, the standard form of quadrature output can be obtained:(15)HQz=ky/x+y+4+2ky/x+y+4z−1+ky/x+y+4z−21−24−y/x+y+4z−1−x−y−4/x+y+4z−2.We setQb0=ky/x+y+4, Qb1=2ky/x+y+4, and Qb2=2ky/x+y+4 to get the following:(16)HQz=QV′zVz=Qb0+Qb1z−1+Qb2z−21−a1z−1−a2z−2.The inverse z-transformation of formula (16) is carried out to obtain the time-domain discrete expression of the quadrature output transfer function HQz:(17)QV′z=Qb0⋅Vn+Qb1⋅Vn−1+Qb2⋅Vn−2+QV′n−1+a2⋅QV′n−2.In the same way, the time-domain discrete expression of the in-phase output signal is obtained from formula (14):(18)V′n=m0⋅Vn+m2⋅Vn−2++n1⋅V′n−1+n2⋅V′n−2.In formula (17), Vn is the quantized input data of the SOGI filter, and VQ′n is the calculation output result of the orthogonal transform algorithm. The transfer function is second-order, and the input data Vn is imported by two shift registers (D flip-flops). V(n − 1) and V(n − 2) are the shift output results of the input data after passing through 1 and 2 D flip-flops. VQ′n−1 and VQ′n−2 are the shift output results of the algorithm after one and two D flip-flops after closed-loop feedback.In this paper, the phase detector of the phase-locked loop is designed by theαβ−dq coordinate transformation in the FPGA, and the realization block diagram is shown in Figure 7. Vα and Vβ are the outputs after the phase-locked loop reference clock is orthogonalized, and the phase detection is completed in the phase detector formed by the Park change with the feedback signals sinθ and cosθ introduced by the DDS unit.Figure 7
Digital phase detector based on the Park transformation.Since it is difficult to directly obtain the phase information of the AC signal in the static coordinate system, the phase information is obtained by converting the AC signal (time-base reference signal) into a DC signal (phase detection result) through the Park transformation. As shown in Figure8, Vα and Vβ are two sinusoidal signals that are orthogonal to the stationary coordinate system; that is, the phase difference is 90°. Among them, the a-0-β coordinate system is a stationary coordinate system, and the d-0-q coordinate system is a rotating coordinate system.Figure 8
Park’s transformation process.V is the signal variable. After the Park transformation, the output variables become two variables that are stationary relative to the rotor. These two variables are no longer sinusoidal signals, but DC components. When the rotating coordinate system is not synchronized with the input variable, thenθ is not equal to θo, and the value of Vq is not zero. After the DAC and the attenuation integral link, it is fed back to the VCXO to change the output frequency until the two are synchronized, the Vq output is zero, and the system loop is locked. From Figure 8, it can be deduced that the Park transformation formula is as follows:(19)Vd=Vα⋅cosθ+Vβ⋅cosθ,(20)Vq=Vα⋅sinθ+Vβ⋅sinθ.Among them, there areVα=V⋅cosθ0 and Vβ=V⋅sinθ0, which are substituted into formulas (19) and (20) to obtain the following:(21)Vd=V⋅cosθ0⋅cosθ+V⋅sinθ0⋅sinθ,(22)Vq=−V⋅cosθ0⋅sinθ+V⋅sinθ0⋅cosθ.From formula (22), Vq=V⋅sinθ−θ0 and Vq can be obtained as the algorithm output of the Park transformation, that is, the phase detection output of the digital phase detector. The reference input signals Vα and Vβ and the phase-locked loop feedback signals cosθ and sinθ are phase-locked and synchronized; that is, when the phase difference value θ−θ0 is equal to 0, there is Vq  = 0. Conversely, when there is a phase difference between the two, there is Vq ≠0. This value is captured by the poststage proportional integrator, which then adjusts the frequency output of the voltage-controlled device.Through the DDS (direct digital synthesis) technology, a frequency signal with both high-precision frequency resolution and phase resolution, and low phase noise can be obtained. The DDS structure mainly includes a phase accumulator and a waveform storage unit. With an addressing scheme with an appropriate lookup table, a direct digital frequency synthesizer can form an output of arbitrary frequency sine-cosine waveform samples. In the digital phase-locked loop, the integrated DDS IP core in the FPGA is planned to be used as the DDS sine and cosine signal generation unit to introduce the phase-locked loop feedback frequency output into the phase detector. A simplified diagram of the digital integrated DDS IP core structure is shown in Figure9.Figure 9
Simplified view of digital integrated DDSIP core.The DDS output frequencyfout is determined by the phase increment value Δθ, the phase accumulator bit width Bθn, and the reference clock fclk. The specific algebraic relationship is shown in the following formula:(23)fout=θ2Bθn⋅fclk.When the reference clock is constant, the DDS output frequency resolution is determined by the bit widthBθn of the phase accumulator. DDS achieves the frequency change of the output signal by changing the phase growth rate of the signal. The phase will not change instantaneously, which can ensure that the phase-locked loop system avoids the loss of the phase information of the output signal during frequency agility and keeps it continuous so that the phase detection is more accurate. DDS frequency synthesis is actually a phase control frequency synthesis process, and the stored value of the phase accumulator is the phase value of the output signal.


## 2.1. Scheme Design of a High-Precision Time-Base Calibrator

According to the established time-base calibration phase-locked loop control model, combined with the design index requirements, the overall design of the high-precision time-base calibrator is carried out. The time-base calibration synchronization structure is shown in Figure1. The structure consists of a high-precision external time-base source (10 MHz), AD converter, quadrature converter, Park transformer, proportional integrator (PI), VCXO of the calibrated frequency synthesizer, and DDS (direct digital synthesis) sine and cosine signal generation unit. The main body of the high-precision time-base calibrator is a phase-locked loop, the reference signal is quantized by the ADC as the reference clock Vref of the phase-locked loop, and the phase detector adopts a Park transformation structure. Therefore, the quantized signal needs to be orthogonally transformed to obtain the orthogonal signals Vα and Vβ. Orthogonal transformation together with the Park transformation completes the phase relationship verification of the reference clock input signal and the phase-locked loop output signal. The phase relationship verification result Vq is adjusted and fed back to the VCXO voltage control input terminal by the proportional integral unit, and finally, the time-base calibration of the frequency synthesizer is realized. The tuning of the phase-locked loop structure is frequency-dependent. If there is a disturbance in the frequency of the input terminal, the output of the phase-locked frequency will be abnormal, and SOGI is required as an adaptive frequency adjustment unit. When the orthogonal transformation is completed, its frequency response output can be automatically adjusted according to the output frequency of the phase-locked loop. In the process of frequency calibration, SOGI effectively suppresses the high-order harmonics introduced by the disturbance of the sampling clock and relies on the fast frequency response characteristics to make the time-base calibration faster and more accurate.Figure 1
Time-base calibration synchronization structure block diagram.


## 2.2. Structural Design and Working Principle Analysis of the Digital Phase-Locked Loop System

The main components of the digital phase-locked loop include a reference time-base source, A/D conversion module, improved digital phase detector (quadrature transformation and the Park transformation are included), loop filter, proportional integrator, calibrated frequency synthesis device, and DDS frequency synthesis unit.The jitter of the delay unit refers to the time delay (td) of the signal passing through the delay unit, which is the time uncertainty of the delay unit. The variance of voltage random noise is denoted asδ2. Among them, IN is the discharge current of the NMOS, and C is the load capacitance. It is the main source of time uncertainty and jitter. The load capacitance is two uncorrelated white noise sources, that is, the current integrated noise and the initial noise, and the variance can be expressed as follows:(1)δ2=2kTγNCVDDIN2VDD−VtN+kTCIN2,where k is the Boltzmann constant, T is the temperature, VDD is the supply voltage provided, and VtN is the threshold voltage of the NMOS. Obviously, in order to reduce the jitter inside the delay unit, a larger current or a smaller threshold voltage is required. At the same time, the reduced threshold voltage of the transistor will use a larger load capacitance.The output of the time-base source signal in the high-precision time-base calibrator is first undersampled by the sample-and-hold circuit, and then quantized to the digital domain by the ADC. In order to further increase the resolution, an amplifier with high precision, good linearity, and low power consumption is required. An important source of noise in the voltage domain is the capacitance in the sampling circuit. We derive equivalent time uncertainty variance by normalizing the voltage noise to the slope of the input signal.(2)δS2=kT/CVin⋅2π⋅fin,where Vin is the amplitude of the input signal, and fin is the oscillation frequency of the input signal. It can be seen that it is no longer the current that affects the jitter, but the noise on the capacitor. Therefore, a larger capacitance can be used to reduce the noise of the sampling circuit. The noise of the sampling circuit can affect its dynamic range and the effective resolution of the ADC. If the capacitors in the sampling circuit are not optimized, the power consumption of the entire system will also increase. On the contrary, in the time domain, the resolution is improved by adding an amplifying circuit between the time-base reference signal source and the ADC, and the current does not need to be increased.In the case of using the internal reference voltage, when 600 mV and 350 mV ripples are applied to the power supply ports VDD1 and VDD2, respectively, the power supply rejection ratio of VDD1 is greater than 73 dB when the ripple frequency is less than 1 KHz, and the power supply rejection ratio of VDD2 is always maintained at about 85 dB. At room temperature, the internal reference of the AD7626 exhibits a better signal-to-noise ratio and total harmonic distortion than the external reference, as shown in Figure2.Figure 2
Effect of temperature on AD7626 signal-to-noise ratio and total harmonic distortion.The sampling and digitization process of the time-base reference signal is now analyzed in order to reduce the complexity of the digital signal processing by the back-end FPGA, and the digital phase-locked loop mainly focuses on the information such as the phase and the amplitude of the target signal. Therefore, the time-base signal sampling adopts the undersampling mode. The time-base outputs sinusoidal signal frequencyf = 10 MHz, which can be expressed as follows:(3)y=Asin2πft+φ.Among them,φ represents the amplitude, f represents the oscillation frequency, and A represents the initial moment phase. The standard signal is undersampled at the sampling rate of fs, and the sampled digital signal is given by(4)yout=Asin2πffs+φ.According to the Nyquist sampling theorem, for a periodic signal with frequencyf0, the sampling frequency needs to satisfy fs >2 f0. However, under the undersampling condition, there is fs <2 f0. The aliasing that occurs between the sampling frequency and the passband causes the sampling data to be superimposed into harmonic components of multiple frequencies. At this point, the frequency at which the signal is collected is the aliasing frequency. The time-domain state of the acquired signal after undersampling can be determined by calculating the aliasing frequency fout. According to the aliasing mechanism and the calculation formula of the aliasing frequency, the frequency of the output signal after undersampling is determined as follows:(5)fout=N⋅fs−f0.In formula (5), there is N=Intf0/fs+0.5. Int is the rounding operation, fs is the sampling frequency, f0 is the frequency of the sampled signal, and fout is the frequency of the undersampled output signal. The time-base signal of 10 MHz is simulated in MATLAB, and the signal is sampled at a sampling rate of 9 MHz. The entire signal acquisition process is shown in Figure 3.Figure 3
Time-base signal under sampling process simulation.The second-order generalized integral quadrature signal generator can generate the same-phase signal and its quadrature, which mainly contain the fundamental component after filtering. The block diagram of the second-order generalized integrator is shown in Figure4. In the figure, V is the input signal Vref, Vα and Vβ are the in-phase output signal and quadrature output signal of V, respectively, k is the gain coefficient, and ω0 is the resonant frequency of the SOGI system.Figure 4
Second-order generalized integrator.From the block diagram of the second-order generalized integrator, the closed-loop transfer functions of the in-phase and quadrature outputs can be obtained as follows:(6)Hds=VαsVs=kω0ss2+kω0s+ω02,(7)HQs=VβsVs=kω02s2+kω0s+ω02.V(s),Vαs, and Vβs are the s-domain representations of the input signal, in-phase output signal, and quadrature output signal of the SOGI system, respectively. Hds and HQs are the s-domain closed-loop transfer functions for the in-phase and quadrature outputs. The corresponding amplitude-frequency and phase-frequency characteristic expressions are further obtained from the closed-loop transfer function:(8)Hdω=kω0ωkω0ω2+ω2−ω02,(9)φdω=arctanω02−ω2kωω0,(10)HQω=kω02kω0ω2+ω2−ω02,(11)φQω=arctanω02−ω2kωω0−π2In formulas (8)–(11), ω is the frequency of the SOGI input signal V. From the amplitude-frequency characteristics (8) and (10), it is known that SOGI reaches a steady state, that is, when there is Hdω=HQω=1, ω is equal to ω0, which indicates that the two output signals Vα and Vβ of SOGI are of equal amplitude. The phase-frequency characteristics (9) and (11) are compared, and it is known that the system output signals Vα and Vβ have a phase difference of 90 degrees; that is, they are orthogonal to each other.k is the gain coefficient in formulas (6) and (7), and the value of k affects the response speed and frequency characteristics of the quadrature signal generating unit. First, according to the influence of k on the response speed of the system, under the condition of different k values, we simulate the step responses of the closed-loop transfer functions Hds and HQs, and the results are shown in Figure 5. It can be seen from the figure that for Hds, the smaller the k, the slower the system response and the longer the stabilization time. For HQs, the smaller k is, the faster the system responds, but the longer the settling time is.Figure 5
Step response of transfer function for differentk values.k also affects the frequency characteristics of the quadrature signal generating unit. It can be seen from the Bode plot of transfer functionHQs in Figure 6 that when k is greater than 1, the system has a weak amplification of low-frequency noise. The cut-off frequency of the system is 10 MHz, and some frequency components greater than the cut-off frequency can be effectively suppressed, with low-pass filtering performance.Figure 6
Bode plot of transfer functionHQs for different k values.The reference value ofk in the project is 2. In order to make the quadrature signal generation unit achieve the best performance, the response characteristics of the transfer function under different k values and the working stability of the filter algorithm on the FPGA are combined, and the factors such as satisfying the fast response characteristics of the algorithm are comprehensively considered, and the k value is taken as 1.2. Compared with the reference value, under the condition of k = 1.2, the amplifying effect of the system on low-frequency noise can be weakened, and the algorithm application can ensure that the fast response is maintained, and the frequency characteristics are better.The transfer function of SOGI is transformed to the z-domain. According to the principle of bilinear transformation,1/s=TS/21+z−1/1−z−1 can be obtained. It is substituted into (6) and simplified to(12)Hdz=kω02/Tsz−1/z+12/Tsz−1/z+12+kω02/Tsz−1/z+1+ω02.We setx=2kω0TS and y=ω0TS2. Among them, TS is the sampling period of the input terminal to the analog signal V. Formula (12) can be transformed into the standard form:(13)Hdz=x/x+y+4+−x/x+y+4z−21−24−y/x+y+4z−1−x−y−4/x+y+4z−2.We setm0=x/x+y+4m2=−x/x+y+4=−m0, n1=24−y/x+y+4n2=x−y−4/x+y+4, and substitute it into formula (13) to get(14)Hdz=V′zVz=m0+m2z−21−n1z−1−n2z−2.Similarly, the standard form of quadrature output can be obtained:(15)HQz=ky/x+y+4+2ky/x+y+4z−1+ky/x+y+4z−21−24−y/x+y+4z−1−x−y−4/x+y+4z−2.We setQb0=ky/x+y+4, Qb1=2ky/x+y+4, and Qb2=2ky/x+y+4 to get the following:(16)HQz=QV′zVz=Qb0+Qb1z−1+Qb2z−21−a1z−1−a2z−2.The inverse z-transformation of formula (16) is carried out to obtain the time-domain discrete expression of the quadrature output transfer function HQz:(17)QV′z=Qb0⋅Vn+Qb1⋅Vn−1+Qb2⋅Vn−2+QV′n−1+a2⋅QV′n−2.In the same way, the time-domain discrete expression of the in-phase output signal is obtained from formula (14):(18)V′n=m0⋅Vn+m2⋅Vn−2++n1⋅V′n−1+n2⋅V′n−2.In formula (17), Vn is the quantized input data of the SOGI filter, and VQ′n is the calculation output result of the orthogonal transform algorithm. The transfer function is second-order, and the input data Vn is imported by two shift registers (D flip-flops). V(n − 1) and V(n − 2) are the shift output results of the input data after passing through 1 and 2 D flip-flops. VQ′n−1 and VQ′n−2 are the shift output results of the algorithm after one and two D flip-flops after closed-loop feedback.In this paper, the phase detector of the phase-locked loop is designed by theαβ−dq coordinate transformation in the FPGA, and the realization block diagram is shown in Figure 7. Vα and Vβ are the outputs after the phase-locked loop reference clock is orthogonalized, and the phase detection is completed in the phase detector formed by the Park change with the feedback signals sinθ and cosθ introduced by the DDS unit.Figure 7
Digital phase detector based on the Park transformation.Since it is difficult to directly obtain the phase information of the AC signal in the static coordinate system, the phase information is obtained by converting the AC signal (time-base reference signal) into a DC signal (phase detection result) through the Park transformation. As shown in Figure8, Vα and Vβ are two sinusoidal signals that are orthogonal to the stationary coordinate system; that is, the phase difference is 90°. Among them, the a-0-β coordinate system is a stationary coordinate system, and the d-0-q coordinate system is a rotating coordinate system.Figure 8
Park’s transformation process.V is the signal variable. After the Park transformation, the output variables become two variables that are stationary relative to the rotor. These two variables are no longer sinusoidal signals, but DC components. When the rotating coordinate system is not synchronized with the input variable, thenθ is not equal to θo, and the value of Vq is not zero. After the DAC and the attenuation integral link, it is fed back to the VCXO to change the output frequency until the two are synchronized, the Vq output is zero, and the system loop is locked. From Figure 8, it can be deduced that the Park transformation formula is as follows:(19)Vd=Vα⋅cosθ+Vβ⋅cosθ,(20)Vq=Vα⋅sinθ+Vβ⋅sinθ.Among them, there areVα=V⋅cosθ0 and Vβ=V⋅sinθ0, which are substituted into formulas (19) and (20) to obtain the following:(21)Vd=V⋅cosθ0⋅cosθ+V⋅sinθ0⋅sinθ,(22)Vq=−V⋅cosθ0⋅sinθ+V⋅sinθ0⋅cosθ.From formula (22), Vq=V⋅sinθ−θ0 and Vq can be obtained as the algorithm output of the Park transformation, that is, the phase detection output of the digital phase detector. The reference input signals Vα and Vβ and the phase-locked loop feedback signals cosθ and sinθ are phase-locked and synchronized; that is, when the phase difference value θ−θ0 is equal to 0, there is Vq  = 0. Conversely, when there is a phase difference between the two, there is Vq ≠0. This value is captured by the poststage proportional integrator, which then adjusts the frequency output of the voltage-controlled device.Through the DDS (direct digital synthesis) technology, a frequency signal with both high-precision frequency resolution and phase resolution, and low phase noise can be obtained. The DDS structure mainly includes a phase accumulator and a waveform storage unit. With an addressing scheme with an appropriate lookup table, a direct digital frequency synthesizer can form an output of arbitrary frequency sine-cosine waveform samples. In the digital phase-locked loop, the integrated DDS IP core in the FPGA is planned to be used as the DDS sine and cosine signal generation unit to introduce the phase-locked loop feedback frequency output into the phase detector. A simplified diagram of the digital integrated DDS IP core structure is shown in Figure9.Figure 9
Simplified view of digital integrated DDSIP core.The DDS output frequencyfout is determined by the phase increment value Δθ, the phase accumulator bit width Bθn, and the reference clock fclk. The specific algebraic relationship is shown in the following formula:(23)fout=θ2Bθn⋅fclk.When the reference clock is constant, the DDS output frequency resolution is determined by the bit widthBθn of the phase accumulator. DDS achieves the frequency change of the output signal by changing the phase growth rate of the signal. The phase will not change instantaneously, which can ensure that the phase-locked loop system avoids the loss of the phase information of the output signal during frequency agility and keeps it continuous so that the phase detection is more accurate. DDS frequency synthesis is actually a phase control frequency synthesis process, and the stored value of the phase accumulator is the phase value of the output signal.


## 3. College Students’ Physical Health Test Data Analysis System

Based on the overall design of the system, this paper completes the import of students' basic information based on the big data technology. The functions of this system are mainly divided into data entry, data query, data statistics, and data analysis, as shown in Figure10.Figure 10
System function structure diagram.This paper verifies the effect of the data analysis system for college students' physical health test proposed in this paper, and compares the system proposed in this paper with the manual testing method. Because the method of manual testing is more accurate, it can be used as the basic data to verify the reliability of the system in this paper. After that, the reliability of the system proposed in this paper is verified, and the verification results shown in Table1 are obtained.Table 1
Effect verification of college students' physical health test data analysis system.
No.Reliability test190.020293.044392.178489.418589.744690.723790.402893.954993.2621092.1091192.9781292.4101392.0421492.7831593.5531692.4131791.3411891.1411991.2302093.3232190.6792291.2672389.0792493.9462589.8122689.2262790.3672889.4972989.1413093.9313193.7003291.6403393.8473492.2153592.9773692.8473793.7933892.2723993.5304091.6664193.6784291.0444391.2094489.6204592.6954690.9334789.0384891.7824991.0315093.0835193.402From the above research, we can see that the college students’ physical health test data analysis system proposed in this paper has certain reliability. On this basis, the health promotion countermeasures for college students are put forward, which mainly include the following points:(1)
It is necessary to set up a professional department and attach importance to the physical health testing of students(2)
It is necessary to improve the foundation of physical health testing and realize scientific and standardized testing(3)
It is necessary to establish a physical fitness test center to strengthen the monitoring of students' physical fitness(4)
It is necessary to build a follow-up service network platform to comprehensively track physical fitness data


## 4. Conclusion

There are many students in colleges and universities, and there are tens of thousands of students in all grades. Moreover, the school's teaching tasks are heavy, and teachers' subject teaching is under great pressure. In particular, due to the influence of traditional teaching concepts, the physical education subject itself has not been paid enough attention so that colleges and universities are relatively negligent in the work of physical health testing, and fail to truly recognize the significance of physical health testing. On the contrary, the physical health testing work in colleges and universities is superficial and reduced to a formality. Under the background of quality education, it will play a positive role in promoting the smooth development of students' physical health testing work. However, in the actual implementation and implementation process, it is undeniable that there are still some defects and problems. This paper combines the big data technology to analyze the data of college students' physical health test and build a health promotion system, and formulate college students' health promotion countermeasures with the support of the system. The research shows that the college students’ physical health test data analysis system proposed in this paper has certain reliability, and on this basis, college students' health promotion countermeasures are proposed.



---

*Source: 6879597-2022-08-25.xml*