# Improved Carbon Nanotube Field Effect Transistor for Designing a Hearing Aid Filtering Application

Authors: K. Mohana Sundaram; P. Prakash; D. Karthikeyan; Wubishet Degife Mammo
Journal: Journal of Nanomaterials
 (2021)

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## Abstract

Designing a hearing aid device is one of the challenging applications recently, since it is useful for the people with hearing loss. For this purpose, various circuit designing procedures such as MOSFET and carbon nanotube field effect transistor (CNTFET) are introduced in the existing works. But it mainly lacks the following drawbacks: increased leakage current, not highly efficient, and increased area and power consumption. In order to mitigate these issues, this paper is aimed at designing an improved CNTFET (ECNFET) for hearing aid filtering application. The major objectives of the proposed work are leakage current minimization and the improvements in transconductance and mobility. At first, the layout is designed with 10 layers based on the specific dimensionalities, and different materials are placed in each and every layer. It includes gold, silicon, silicon dioxide, bismuth telluride, and carbon tube. Then, the parameters such as band gap, electron concentration, hole concentration, electron mobility, hole mobility, and insulator breakage voltage are verified to determine the efficiency of the layout. If all the parameters are satisfied, the characteristics such as voltage current, leakage current, mobility, and transconductance are validated. If all measures are satisfied, the library is created for the designed ECNFET layout by using the Comsol tool. Furthermore, the operational amplifier is designed based on the generated library function. After amplification, the hearing aid filter is designed with the use of the proposed ECNFET layout. The experimental validation of the proposed work and comparison with the existing method based on the measures of area consumption, power consumption, speed, and frequency range confirm the effectiveness of ECNTFET in filtering applications.


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## Body

## 1. Introduction

In today’s world, approximately 10% of people suffer due to the hearing loss in which a small amount people use hearing aid devices. The result of wearing this device is highly efficient with minimum noise and distortion. Moreover, a variety of digital signal processing algorithms is required to design the hearing aid device. Traditionally, some of the existing research works are aimed at developing a hearing aid filter by using the VLSI circuit designing technology. But it poses several challenges like increased power and area consumption, when compared to other portable devices. So, the layouts such as MOSFET and CNTFET [1] are developed to design this filtering application. The MOSFET is an integrated circuit that is capable of both voltage gain and signal power gain, in which the MOS capacitor is the main part, and then, the application of gate voltages changes the semiconductor operation from p-type to n-type. Furthermore, it functions based on the deflection mode and the enhancement mode [2]. But it has the major constraints such as process variations, short channel effect, and high leakage current issues. Thus, a CNTFET [3] is developed that is the next generation of MOSFET [4], which uses the carbon nanotube between the source and drain. The major reasons for designing CNTFET are reduced size, high-performance channel material, and mobility enhancement. Normally, the CNT is considered as a rolled-up sheet of graphene, in which the electrical properties are dependent on the chirality of the distortion direction [5]. In CNTFET, the core of integrated circuit is implemented in a single chip that contains four terminal units, namely, source, drain, gate, and body as shown in Figure 1. A CNTFET relates to a FET that uses single or multiple carbon nanotubes as channel being a substitute for bulk silicon found in the conventional MOSFET [6]. Here, the power supply is provided to the source and drain; then the triggering is enabled for the gate. If it is high, the layout goes to on state; otherwise, it goes to off state.Figure 1
Source, drain, and gate of ECNFET layout.


### 1.1. Problem Definition

The procedure of CNTFET [7, 8] is the same as that of MOSFET, in which the source terminal supplies the electrons and it is collected by the drain terminal. The CNTFET is the most widely used technology for the past decades [9]. The dimensional criticality in the silicon material reduced the utilization level for the transistor fabrication [10]. Hence, the research studies focused on the identification of alternatives to improve the density and recital of electronic information system [11]. The gate terminal controls the current intensity [12]. If the transistor is in off stage, there is no gate voltage is supplied [13]. However, it also has some major limitations [14] such as increased area consumption and power consumption, reduced speed and frequency range, and increased leakage current [15]. So, it is highly important to determine whether the hearing aid device is good for the hearing loss patients [16]. To mitigate the issues, this article explores the development of a novel hearing aid filtering application by implementing the CNTFET layout.


### 1.2. Objectives

The objectives modelled from the problem identification are listed as follows:(i)
To reduce the leakage current(ii)
To increase the transconductance(iii)
To increase the electron mobility(iv)
For these objectives, an enhanced CNTFET (ECNFET) layout is designed and implemented in the hearing aid filtering application(v)
The novelty behind the proposed work lies in following cases:(i)
The design of CNTFET-based hearing aid filter in 2 nm technology with the thickness of 0.6 m(ii)
The minimization in layer thickness and the design technology reduce the leakage current compared to the existing models(iii)
The reduction of thickness of the layering initiates the thin material design and increases the operational speed simultaneously


### 1.3. Organization

The article is structured as follows: the existing filtering applications and field effect transistor layouts with its advantages and disadvantages are surveyed in Section2. The detailed description about the proposed ECNFET-hearing aid filtering application is presented in Section 3. The measured results of both available and proposed filtering applications are evaluated in Section 4. Section 5 provides the overall summary and the future enhancement.


## 1.1. Problem Definition

The procedure of CNTFET [7, 8] is the same as that of MOSFET, in which the source terminal supplies the electrons and it is collected by the drain terminal. The CNTFET is the most widely used technology for the past decades [9]. The dimensional criticality in the silicon material reduced the utilization level for the transistor fabrication [10]. Hence, the research studies focused on the identification of alternatives to improve the density and recital of electronic information system [11]. The gate terminal controls the current intensity [12]. If the transistor is in off stage, there is no gate voltage is supplied [13]. However, it also has some major limitations [14] such as increased area consumption and power consumption, reduced speed and frequency range, and increased leakage current [15]. So, it is highly important to determine whether the hearing aid device is good for the hearing loss patients [16]. To mitigate the issues, this article explores the development of a novel hearing aid filtering application by implementing the CNTFET layout.


## 1.2. Objectives

The objectives modelled from the problem identification are listed as follows:(i)
To reduce the leakage current(ii)
To increase the transconductance(iii)
To increase the electron mobility(iv)
For these objectives, an enhanced CNTFET (ECNFET) layout is designed and implemented in the hearing aid filtering application(v)
The novelty behind the proposed work lies in following cases:(i)
The design of CNTFET-based hearing aid filter in 2 nm technology with the thickness of 0.6 m(ii)
The minimization in layer thickness and the design technology reduce the leakage current compared to the existing models(iii)
The reduction of thickness of the layering initiates the thin material design and increases the operational speed simultaneously


## 1.3. Organization

The article is structured as follows: the existing filtering applications and field effect transistor layouts with its advantages and disadvantages are surveyed in Section2. The detailed description about the proposed ECNFET-hearing aid filtering application is presented in Section 3. The measured results of both available and proposed filtering applications are evaluated in Section 4. Section 5 provides the overall summary and the future enhancement.


## 2. Associated Works

The existing available FET layout designs used for hearing aid filters are surveyed with their advantages and disadvantages here. The compensation of hearing loss utilizes the device, namely, hearing-aid system, which contains several processes such as amplification, noise removal, suppressing the feedback, and automatic program switching. The amplification of sounds and transferring such sounds to the human ear are the major operations of hearing-aid system. The adjustments of speech signals were performed through the filter bank-based algorithms. Wei and Wang [17] proposed an adjustable filter bank to achieve wave composition based on hearing loss. The changes in 4-bit control signal provide the adjustments in number of subbands and their location. The size optimizing of filter used in hearing-aid system turned the research studies to make the fast-efficient filter with low-power consumption. Kotha et al. [18] discussed the 4 : 2 compressors for finite impulse response (FIR) design. The realization gate level-17 order filter was illustrated by using Hardware Description Language (HDL). The UMC-90 technology was used to implement the architectures with the integration of Cadence compiler. Recently, the revolution in wireless communications systems changes the people lifestyle and leads to the numerous smart device utilization. Based on the application areas such as environmental monitoring and healthcare monitoring, the frequency ranges were defined. Trivedi et al. [19] pointed out the maximum frequency range for the hearing aid is 6 kHz. Under different biasing conditions, the power dissipation among the components was investigated with the subthreshold operation. In some cases, the degree of hearing loss was worse against the time variations. For the severe hearing loss, the acoustic-based amplification was insufficient to restore the satisfactory result [20]. Based on these operational constraints, the design of hearing aid filter was the next stage of research FET-based models which was employed to design several models. Under the temperature variations, power and delay consumed by the operating phases were high and hence, the reduction mechanisms were required.Nguyen et al. [21] developed a new sensing system, namely, Low cost In-ear Bioelectrical Sensing (LIBS) for providing a solution to healthcare applications. It automatically captured the signal from the ear canal based on the process of data acquisition and signal separation. Also, a Nonnegative Matrix Factorization (NMF) method was introduced to decompose the signal for separation. Yogeshwaran et al. [22] investigated the drain current and delay of the hearing aid device. Here, the relationship between these measures was validated based on the features of ON and OFF. Kuo et al. [23] implemented an ANSI S1.11 filter for designing a digital hearing aid device. The intention of this application was to cancel the echo, reduce the noise, and enhance the speech. The stages involved in this design were filter bank architecture formation, low power optimization, computation reordering, clock gating, and operand isolation. Guo et al. [24] implemented an acoustic feedback cancellation approach for eliminating the probe noise in a hearing aid filter. The intention of this paper was to reduce the convergence rate with the use of probe noise enhancement filters. Here, two different probe noise-based approaches were evaluated for analyzing the suitable approach with increased convergence rate and reduced steady-state error. However, this design strategy failed to reduce the computational complexity.Kalathil and Elias [25] designed a nonuniform cosine-modulated filter, and the aim of this application was to fulfill the requirements of hearing-impaired people with the use of uniform filter and transition filter. The merits observed from this paper were increased flexibility, reduced complexity, and improved performance. Pandey and Matthews [26] implemented a Spectral Gain Shaping Method (SGSM) for hearing loss compensation with dynamic range compression and noise suppression. Also, the unwanted effects of the long and broadband path delays were reduced with the use of hearing aid signal processing algorithms. Moreover, the spectral gain shaping capability of the hearing aid system was analyzed for reducing the delay. Ngo et al. [27] designed an improved prediction error filter for modelling the acoustic feedback and estimating the feedback signal in a hearing aid system. Here, the correlation between the near-end signal and loudspeaker signal was identified with the use of Prediction Error Method (PEM). Moreover, an energy-based voiced and unvoiced detection was performed by using the Zero Crossing Rate (ZCR) feature. Pandey and Mathews [28] employed an adaptive filtering technique to enhance the sound quality of hearing aid device. The aim of this paper was to increase the hearing aid gain and to reduce the perceptual distortion. Here, the amplification process was controlled and the frequency components were automatically identified. The use of CNTFET sensors in biomedical applications is growing at a rapid pace [29–31].


## 3. Suggested Method

The clear description about the proposed hearing aid filtering application using ECNFET layout is provided here. The design of a hearing aid filter with an enhanced CNTFET layout is the major objective of this paper. In this design, the single-walled nanotube is used for providing high current conductivity. It mainly focused to reduce the leakage current and increase the transconductance and electron mobility. For these purposes, an ECNFET layout is designed based on the dimensionalities of length, width, height, CNT thickness, CNT length, and CNT diameter. After designing the circuit, the required materials such as gold, silicon, silicon oxide, bismuth telluride, and carbon are used. Then, the parameters such as band gap, electron concentration, hole concentration, electron mobility, hole mobility, and insulator breakage voltage are considered.After verifying these parameters, the characteristics such as voltage current, mobility, leakage current, and transconductance of the layout are validated. If the characteristics are satisfied, the library is created by using the Comsol tool. Furthermore, the operation amplifier is designed by using the ECNFET layout for increasing the efficiency of filtering application. Finally, the hearing aid filter is designed by implementing this ECNFET layout. To demonstrate the superiority of the suggested application, the evaluation parameters such as area, power, frequency, and speed are considered during the evaluation. ECNFET flow is shown in Figure2.Figure 2
Flow of the ECNFET-based hearing aid filtering.


### 3.1. Physical Design Based on the Dimensionality Analysis

At first, the ECNFET layout is designed based on the specific dimension of each layer. It contains 10 layers, in which different materials are placed in each layer. Layers 1 and 3 are termed as intralayers, and layer 2 is termed as interlayer. Then, layer 5 acts as a source, layer 8 acts as gate, and layer 10 acts as a drain. Also, layers 4, 7, and 9 act as either p-substrates or n-substrates; finally, the CNT is placed in layer 6. The layout design is represented in Figure3, in which the dimensionalities are determined based on rules of circuit designing. The rules specified that the entire layout should contain the minimum width of 2λ and height of 1.5λ, if the layout design does not follow these rules, it is termed as a worst case design. In the proposed design, the height of the ECNFET is 1λ and the width is 2λ. Also, each and every layer should follow some dimensionalities for a good design. The intralayers (i.e., D1 and D3) have the height of 0.2 nm and width of 2 nm, because these dimensions provide an increased doping concentration. Also, it has a minimum opening for allowing the current conductance from electrons to holes and holes to electrons. Then, the inter layer (i.e., D2) has the height of 0.2 nm and width of 2 nm, because it offers an increased conductance and peak doping concentration. The p-type and n-type substrates (i.e., D4, D9, and D7) have the height of 0.2 nm and width of 0.7 nm, because it controls the materials based on the resistance. Moreover, the source, drain, and gate layers (i.e., D5, D8, and D10) have the height of 0.1 nm and width of 0.4 nm, because they offer a high-level implant and energy. Finally, the CNT that is placed in D6 has the height of 0.1 nm, width of 0.6 nm, and diameter of 0.6 nm, which is placed between the source and drain for increasing the conductivity.Figure 3
Layout design with different materials.


### 3.2. Material Selection

After designing the layout, different materials are placed in each and every layer, which includes gold, silicon, quartz, bismuth telluride, and carbon nanotube. The main reasons of using gold are it increases the conductivity of semiconductor and accuracy and improves the movement of electrons to holes and holes to electrons. This material is placed in the layers of D1, D5, D8, and D10. The silicon is considered the second-best material that is placed in D2, which provides little flow electricity when it acts as a semiconductor. Then, the silicon dioxide is placed in D3 and D7, which provides an increased dielectric strength and acts as an excellent insulator. Also, it can function even in high temperature. Bismuth telluride is placed in D4 and D9, which provides low lattice thermal conductivity. Moreover, it acts as a power generation device and is used in both p-type and n-type substrates. Finally, the single-walled thin CNT is placed in D6, which reduces the diameter size by using the single graphite sheet. Due to this, the size of transistor component is reduced to 2 nm.


### 3.3. Parameter Verification

After selecting the materials, the parameters such as band gap, electron concentration, hole concentration, electron mobility, hole mobility, and insulator breakage voltage are validated [32]. As for band gap, the energy band gap of the circuit is highly depending on the materials that are used for circuit designing.The materials or insulators having the energy gap of 1 eV are termed as semiconductors. It is calculated as follows:(1)Eg=Ec−Ev,(2)Eg=1.210−3.60×10−4×TeV,where T indicates the temperature, eV indicates the electron volts, Eg represents the energy band gap, Ec is the conductance band, and Ev is the valence band.


#### 3.3.1. Electron Concentration

The electron concentration is defined as the concentration of electrons in the conduction band. Here, the intrinsic concentration is calculated for both n-type and p-type transistors, which is shown below:(3)ni=NceEF−Ec/kT,where Nc=2πmekT/h23/2.


#### 3.3.2. Hole Concentration

The hole concentration is defined as the concentration of electrons in the valence band, which is calculated as follows:(4)pi=NveEv−EF/kT,whereNv=22πmhkT/h23/2, whereNcis effective density of states in the conduction band, Nv is effective densities of states in the valence band, k is Boltzmann constant, T is temperature, EF is Fermi energy, Ev is valence band level, Ec is conduction band level, mh is effective mass of a hole, me is effective mass of an electron, and h is Planck constant 6.624×10−34Js.


#### 3.3.3. Electron Mobility

The movement of electrons through a semiconductor or metal is characterized by using the electron mobility. It is estimated as follows:(5)vd=μE.


#### 3.3.4. Hole Mobility

Typically, there is an analogous quantity for holes in a semiconductor, which is generally lower than the electron mobility. It is estimated as follows:(6)vd=μH,where μ represents the mobility, E is the electric field, H represents the holes, and vd is the drift velocity.


#### 3.3.5. Insulator Breakage Voltage

This should be minimum, because it causes some portion of an insulator as an electrically conductive. It is calculated as follows:(7)Vbreakdown=B×p×dC+Inp×d,where p is pressure of the gas, d represents the distance between two conducting plats, and B and C are the constants that are determined based on the experiments. Based on these parameters, the effectiveness of the layout is determined; if these measures are fully satisfied, the characteristics of the layout are validated.


### 3.4. Characteristic Validation

After verifying the measures, the major characteristics of the layout is validated; this includes voltage current, mobility, leakage current, and transconductance. The controlling of voltage and flow of current between the source and drain through the proposed ECNFET model reduced leakage current [33].


#### 3.4.1. Voltage Current

It is defined as the amount of current taken for the movement of electrons to holes and holes to electrons. It is calculated as follows:(8)I=μWci×VGS−VTVL,where μ is the mobility and I indicate the current.


#### 3.4.2. Transconductance

The transconductance is also called as mutual conductance, in which the electrical characteristics are related to the output current through the device and the input voltage across the device. Also, the conductance is represented as the reciprocal of the resistance.(9)gm=dIddVGSVDS,where gm is transconductance, Id is drain current, VGS is gate source voltage, and VDS is drain source voltage.


#### 3.4.3. Leakage Current

It is an important conduction of PN junction diode, in which the width of the depletion region is increased, when a diode is reverse biased. This condition is required to restrict the current carrier accumulation. The depletion region acts as an insulator, if the majority of current carriers are primarily negated. It is calculated as follows:(10)I=I0e−Ee/2kT.I0 is the initial current, E defines the electrons, and e is the permittivity. Here and mainly, the leakage current reduction is concentrated, because it leads to the band-to-band tunnelling leakage.


### 3.5. ECNFET Layout Design and Library Creation

After triggering, the transistors are enabled by using the analytic doping model, in which the P, N, and P are substrates in the P-type transistor, and the N, P, and N are substrates in the N-type transistor. In this layout, the semiconductor is placed in between the source and drain under the oxide layer domain. Furthermore, the application of positive and negative voltages on gate terminal switches the operation between n-type and n-type transistors. Here, the holes across the oxide layer are pushed downward to the substrate, when the positive gate voltage is applied. Then, the bound negative charges populate the deflection region with the acceptor atoms. The current flows freely once the voltage is applied between the drain and source; then, the electrons in the channel are controlled by the gate voltage. The hole channel is made under the oxide, when the negative voltage is supplied. The designed ECNFET layout is shown in Figure4, and its 3D representation is shown in Figure 5. After that, the library is generated for both p-type and n-type transistors by using the Comsol tool. Then, the generated libraries are given to the input of filtering for noise removal.Figure 4
ECNFET layout design.Figure 5
3D representation of ECNFET.


### 3.6. Operational Amplifier Design

The ECNFET is a kind of semiconductor device that is mainly used to amplify the signals in the electronic devices. Figure6 shows the operational amplifier [34] with the 7 ECNFETs which are used as a p-type transistor, and 5 ECNFETs are used as an n-type transistor. Also, one capacitor is used to avoid the current loss, which is 0.1 μf. This layout gets the low-level frequency as input and provides an improved frequency as output. In this design, theVdis taken as 10 mw andVgis taken as 2 v.Figure 6
Design of operational amplifier.The op-amp design using the proposed ECNFET operates at the constant common mode voltage close to source voltage. The input to the op-amp stage is simplified with the Miller-compensated simplified voltage supply. The proposed op-amp comprises the cascaded Miller-compensated stage and output stage to minimize the power intake. The input and output waveforms with frequency variations are illustrated in Figure7.Figure 7
Output voltage analysis.With the linear increase of frequencies from 2 kHz to 10 kHz, the voltage variations are graphically depicted in Figure7. The stable operating point for the voltage and current is observed after the frequency range 2 kHz.The major benefits of the ECNFET-hearing aid filter shown in Figure8 are as follows:Figure 8
Hearing and filtering application.It helps to increase the speed of transistor.It avoids the current loss by designing the capacitor with 0.1μf.It efficiently reduces the noise by designing the hearing aid using the ECNFET layout.The output voltage waveform variations with respect to the time period clearly demonstrate the operation of filter design using the ECNFET model. It is shown in Figure9.Figure 9
Filter output.For the minimum time period (50 ns), the output voltage is in maximum state. When the simulation period is linearly increased from the minimum to maximum value (500 ns), the voltage value is decreased to low value due to the reduction in drain current under the constant drain-to-source voltage.


## 3.1. Physical Design Based on the Dimensionality Analysis

At first, the ECNFET layout is designed based on the specific dimension of each layer. It contains 10 layers, in which different materials are placed in each layer. Layers 1 and 3 are termed as intralayers, and layer 2 is termed as interlayer. Then, layer 5 acts as a source, layer 8 acts as gate, and layer 10 acts as a drain. Also, layers 4, 7, and 9 act as either p-substrates or n-substrates; finally, the CNT is placed in layer 6. The layout design is represented in Figure3, in which the dimensionalities are determined based on rules of circuit designing. The rules specified that the entire layout should contain the minimum width of 2λ and height of 1.5λ, if the layout design does not follow these rules, it is termed as a worst case design. In the proposed design, the height of the ECNFET is 1λ and the width is 2λ. Also, each and every layer should follow some dimensionalities for a good design. The intralayers (i.e., D1 and D3) have the height of 0.2 nm and width of 2 nm, because these dimensions provide an increased doping concentration. Also, it has a minimum opening for allowing the current conductance from electrons to holes and holes to electrons. Then, the inter layer (i.e., D2) has the height of 0.2 nm and width of 2 nm, because it offers an increased conductance and peak doping concentration. The p-type and n-type substrates (i.e., D4, D9, and D7) have the height of 0.2 nm and width of 0.7 nm, because it controls the materials based on the resistance. Moreover, the source, drain, and gate layers (i.e., D5, D8, and D10) have the height of 0.1 nm and width of 0.4 nm, because they offer a high-level implant and energy. Finally, the CNT that is placed in D6 has the height of 0.1 nm, width of 0.6 nm, and diameter of 0.6 nm, which is placed between the source and drain for increasing the conductivity.Figure 3
Layout design with different materials.


## 3.2. Material Selection

After designing the layout, different materials are placed in each and every layer, which includes gold, silicon, quartz, bismuth telluride, and carbon nanotube. The main reasons of using gold are it increases the conductivity of semiconductor and accuracy and improves the movement of electrons to holes and holes to electrons. This material is placed in the layers of D1, D5, D8, and D10. The silicon is considered the second-best material that is placed in D2, which provides little flow electricity when it acts as a semiconductor. Then, the silicon dioxide is placed in D3 and D7, which provides an increased dielectric strength and acts as an excellent insulator. Also, it can function even in high temperature. Bismuth telluride is placed in D4 and D9, which provides low lattice thermal conductivity. Moreover, it acts as a power generation device and is used in both p-type and n-type substrates. Finally, the single-walled thin CNT is placed in D6, which reduces the diameter size by using the single graphite sheet. Due to this, the size of transistor component is reduced to 2 nm.


## 3.3. Parameter Verification

After selecting the materials, the parameters such as band gap, electron concentration, hole concentration, electron mobility, hole mobility, and insulator breakage voltage are validated [32]. As for band gap, the energy band gap of the circuit is highly depending on the materials that are used for circuit designing.The materials or insulators having the energy gap of 1 eV are termed as semiconductors. It is calculated as follows:(1)Eg=Ec−Ev,(2)Eg=1.210−3.60×10−4×TeV,where T indicates the temperature, eV indicates the electron volts, Eg represents the energy band gap, Ec is the conductance band, and Ev is the valence band.


### 3.3.1. Electron Concentration

The electron concentration is defined as the concentration of electrons in the conduction band. Here, the intrinsic concentration is calculated for both n-type and p-type transistors, which is shown below:(3)ni=NceEF−Ec/kT,where Nc=2πmekT/h23/2.


### 3.3.2. Hole Concentration

The hole concentration is defined as the concentration of electrons in the valence band, which is calculated as follows:(4)pi=NveEv−EF/kT,whereNv=22πmhkT/h23/2, whereNcis effective density of states in the conduction band, Nv is effective densities of states in the valence band, k is Boltzmann constant, T is temperature, EF is Fermi energy, Ev is valence band level, Ec is conduction band level, mh is effective mass of a hole, me is effective mass of an electron, and h is Planck constant 6.624×10−34Js.


### 3.3.3. Electron Mobility

The movement of electrons through a semiconductor or metal is characterized by using the electron mobility. It is estimated as follows:(5)vd=μE.


### 3.3.4. Hole Mobility

Typically, there is an analogous quantity for holes in a semiconductor, which is generally lower than the electron mobility. It is estimated as follows:(6)vd=μH,where μ represents the mobility, E is the electric field, H represents the holes, and vd is the drift velocity.


### 3.3.5. Insulator Breakage Voltage

This should be minimum, because it causes some portion of an insulator as an electrically conductive. It is calculated as follows:(7)Vbreakdown=B×p×dC+Inp×d,where p is pressure of the gas, d represents the distance between two conducting plats, and B and C are the constants that are determined based on the experiments. Based on these parameters, the effectiveness of the layout is determined; if these measures are fully satisfied, the characteristics of the layout are validated.


## 3.3.1. Electron Concentration

The electron concentration is defined as the concentration of electrons in the conduction band. Here, the intrinsic concentration is calculated for both n-type and p-type transistors, which is shown below:(3)ni=NceEF−Ec/kT,where Nc=2πmekT/h23/2.


## 3.3.2. Hole Concentration

The hole concentration is defined as the concentration of electrons in the valence band, which is calculated as follows:(4)pi=NveEv−EF/kT,whereNv=22πmhkT/h23/2, whereNcis effective density of states in the conduction band, Nv is effective densities of states in the valence band, k is Boltzmann constant, T is temperature, EF is Fermi energy, Ev is valence band level, Ec is conduction band level, mh is effective mass of a hole, me is effective mass of an electron, and h is Planck constant 6.624×10−34Js.


## 3.3.3. Electron Mobility

The movement of electrons through a semiconductor or metal is characterized by using the electron mobility. It is estimated as follows:(5)vd=μE.


## 3.3.4. Hole Mobility

Typically, there is an analogous quantity for holes in a semiconductor, which is generally lower than the electron mobility. It is estimated as follows:(6)vd=μH,where μ represents the mobility, E is the electric field, H represents the holes, and vd is the drift velocity.


## 3.3.5. Insulator Breakage Voltage

This should be minimum, because it causes some portion of an insulator as an electrically conductive. It is calculated as follows:(7)Vbreakdown=B×p×dC+Inp×d,where p is pressure of the gas, d represents the distance between two conducting plats, and B and C are the constants that are determined based on the experiments. Based on these parameters, the effectiveness of the layout is determined; if these measures are fully satisfied, the characteristics of the layout are validated.


## 3.4. Characteristic Validation

After verifying the measures, the major characteristics of the layout is validated; this includes voltage current, mobility, leakage current, and transconductance. The controlling of voltage and flow of current between the source and drain through the proposed ECNFET model reduced leakage current [33].


### 3.4.1. Voltage Current

It is defined as the amount of current taken for the movement of electrons to holes and holes to electrons. It is calculated as follows:(8)I=μWci×VGS−VTVL,where μ is the mobility and I indicate the current.


### 3.4.2. Transconductance

The transconductance is also called as mutual conductance, in which the electrical characteristics are related to the output current through the device and the input voltage across the device. Also, the conductance is represented as the reciprocal of the resistance.(9)gm=dIddVGSVDS,where gm is transconductance, Id is drain current, VGS is gate source voltage, and VDS is drain source voltage.


### 3.4.3. Leakage Current

It is an important conduction of PN junction diode, in which the width of the depletion region is increased, when a diode is reverse biased. This condition is required to restrict the current carrier accumulation. The depletion region acts as an insulator, if the majority of current carriers are primarily negated. It is calculated as follows:(10)I=I0e−Ee/2kT.I0 is the initial current, E defines the electrons, and e is the permittivity. Here and mainly, the leakage current reduction is concentrated, because it leads to the band-to-band tunnelling leakage.


## 3.4.1. Voltage Current

It is defined as the amount of current taken for the movement of electrons to holes and holes to electrons. It is calculated as follows:(8)I=μWci×VGS−VTVL,where μ is the mobility and I indicate the current.


## 3.4.2. Transconductance

The transconductance is also called as mutual conductance, in which the electrical characteristics are related to the output current through the device and the input voltage across the device. Also, the conductance is represented as the reciprocal of the resistance.(9)gm=dIddVGSVDS,where gm is transconductance, Id is drain current, VGS is gate source voltage, and VDS is drain source voltage.


## 3.4.3. Leakage Current

It is an important conduction of PN junction diode, in which the width of the depletion region is increased, when a diode is reverse biased. This condition is required to restrict the current carrier accumulation. The depletion region acts as an insulator, if the majority of current carriers are primarily negated. It is calculated as follows:(10)I=I0e−Ee/2kT.I0 is the initial current, E defines the electrons, and e is the permittivity. Here and mainly, the leakage current reduction is concentrated, because it leads to the band-to-band tunnelling leakage.


## 3.5. ECNFET Layout Design and Library Creation

After triggering, the transistors are enabled by using the analytic doping model, in which the P, N, and P are substrates in the P-type transistor, and the N, P, and N are substrates in the N-type transistor. In this layout, the semiconductor is placed in between the source and drain under the oxide layer domain. Furthermore, the application of positive and negative voltages on gate terminal switches the operation between n-type and n-type transistors. Here, the holes across the oxide layer are pushed downward to the substrate, when the positive gate voltage is applied. Then, the bound negative charges populate the deflection region with the acceptor atoms. The current flows freely once the voltage is applied between the drain and source; then, the electrons in the channel are controlled by the gate voltage. The hole channel is made under the oxide, when the negative voltage is supplied. The designed ECNFET layout is shown in Figure4, and its 3D representation is shown in Figure 5. After that, the library is generated for both p-type and n-type transistors by using the Comsol tool. Then, the generated libraries are given to the input of filtering for noise removal.Figure 4
ECNFET layout design.Figure 5
3D representation of ECNFET.


## 3.6. Operational Amplifier Design

The ECNFET is a kind of semiconductor device that is mainly used to amplify the signals in the electronic devices. Figure6 shows the operational amplifier [34] with the 7 ECNFETs which are used as a p-type transistor, and 5 ECNFETs are used as an n-type transistor. Also, one capacitor is used to avoid the current loss, which is 0.1 μf. This layout gets the low-level frequency as input and provides an improved frequency as output. In this design, theVdis taken as 10 mw andVgis taken as 2 v.Figure 6
Design of operational amplifier.The op-amp design using the proposed ECNFET operates at the constant common mode voltage close to source voltage. The input to the op-amp stage is simplified with the Miller-compensated simplified voltage supply. The proposed op-amp comprises the cascaded Miller-compensated stage and output stage to minimize the power intake. The input and output waveforms with frequency variations are illustrated in Figure7.Figure 7
Output voltage analysis.With the linear increase of frequencies from 2 kHz to 10 kHz, the voltage variations are graphically depicted in Figure7. The stable operating point for the voltage and current is observed after the frequency range 2 kHz.The major benefits of the ECNFET-hearing aid filter shown in Figure8 are as follows:Figure 8
Hearing and filtering application.It helps to increase the speed of transistor.It avoids the current loss by designing the capacitor with 0.1μf.It efficiently reduces the noise by designing the hearing aid using the ECNFET layout.The output voltage waveform variations with respect to the time period clearly demonstrate the operation of filter design using the ECNFET model. It is shown in Figure9.Figure 9
Filter output.For the minimum time period (50 ns), the output voltage is in maximum state. When the simulation period is linearly increased from the minimum to maximum value (500 ns), the voltage value is decreased to low value due to the reduction in drain current under the constant drain-to-source voltage.


## 4. Performance Analysis

The results of both existing and proposed hearing aid filtering applications are measured and equated depending on the measures of leakage current, mobility, transconductance, voltage current, voltage current, area consumption, power consumption, speed, and frequency. The software tools used to implement the proposed work are Comsol 5.0, Electric 9.07, and H-spice J2014. The operating phases of the proposed CNTFET-based hearing aid filter design are layout design, library creation for electric properties, and the performance evaluation. Initially, Comsol 5.0 is used to design the layout with the material specification. In general, there are five materials employed to design the CNTFET such as gold, silicon, graphite, carbon, and SiO2. But, gold and SiO2 are used for our proposed work. Then, the electrical properties are defined as the library which is performed by the software electric tool. The layout is considered as the base for the electric property’s declaration. Once the layout and electric properties are completed, the numerical variations of current, voltage, and the mobility for the design are investigated to state the effectiveness of the proposed work. This is achieved by using the H-spice simulation tool. Hence, the integration of three software tools is the major requirement for our proposed work.


### 4.1. Leakage Current

Figure10 graphically illustrates the leakage current of the proposed ECNFET design with respect to the gate voltage. The leakage current can flow between the source and drain, which is linearly increased with the increase of the gate voltage by minimum leakage current in nanoamps (nA) [33]. In the proposed application, the overall leakage current is reduced to 0.02 nA by using the ECNFET layout.Figure 10
Leakage current.Figure11 represents the drain current variations for the proposed ECNFET. With respect to gate-to-source voltage, there is a linear increase of gate-to-source voltage. The graphical variations of drain current show that it increased to 1.65 mA by using the ECNFET layout. On the basis of the threshold and saturation, the overall peak value of the current is estimated.Figure 11
Voltage current.


### 4.2. Mobility

The mobility defines the movement of electrons and holes from n-substrate to p-substrate, in which the electron conductivity and electron charge carrier are increased, when compared to the holes. The mobility of the proposed ECNFET layout is shown in Figure12. The linear increase in gate voltage from 0 to 2 V increases the mobility values linearly.Figure 12
Mobility graph.


### 4.3. Transconductance

Typically, the transconductance of ECNFET is based on the current of output device and the voltage of input device. Figure13 shows the transconductance of the ECNFET design. From the evaluation, it is observed that the transconductance is improved with respect to the varying gate source voltage and is evaluated in terms of VGS.Figure 13
Transconductance analysis.


### 4.4. Area, Power, Frequency, and Speed

Table1 provides the area consumption, power intake, frequency, and speed of both the existing CNTFET-based filtering design and the proposed ECNFET layout-based filtering design. Here, the amount of area and power required to design the layout is drastically reduced with the increase in the frequency range and speed. In this design, the best materials are used in this circuit design, which reduces the area and power consumption. Also, the operational amplifier improves the frequency range by amplifying the ECNFET layout. Moreover, the hearing aid filter improves the overall efficiency and speed of the system. Based upon the results, it is found that the suggested ECNFET-based hearing aid filtering design provides the better performance, in comparison to the available filtering design.Table 1
Performance analysis of ECNFET.
MeasuresExisting CNTFET filterProposed ECNFET hearing aid filterArea [35]151 components134 componentsPower [36]58.96μw26.03μwFrequency1.9×103 Hz2×103 HzSpeed [37]2.8×109 m/s4×1011 m/sDelay [37]7.4e−126.63e−14


### 4.5. Comparative Analysis

Table2 shows the threshold voltage of existing CNTFET and proposed ECNFET layouts based on varying temperatures. Due to the less heat dissipation mechanism, the heating effect of ECNFET is lower than that of CNTFET, in which the highest value appears in both source and drain, because the heat is nonuniformly distributed. Here, the threshold voltage is calculated with respect to various temperature values, which evaluates the optimized usage of voltage by the proposed layout. Moreover, different temperatures from 27°C to 227°C are taken to analyze the threshold voltage. For minimum temperature values (27°C), the threshold voltage values for CNTFET and ECNFET are 0.210 and 0.205 V, respectively. Similarly, they are 0.164 and 0.160 V for maximum temperature values 227°C, respectively. The comparative analysis between the proposed ECNFET with the CNTFET shows that the proposed model reduces the threshold voltage values by 2.38 and 2.44%, respectively.Table 2
Threshold voltage with respect to temperature.
Temperature (°C)Threshold voltage (V)CNTFETECNFET270.2100.205470.2100.205670.2100.204870.2100.2041070.2020.1981270.1980.1971470.1940.1931670.1910.1861870.1870.1822070.1800.1742270.1640.160Table3 compares the threshold voltage of CNTFET and ECNFET with respect to gold and silicon dioxide materials. The threshold voltage variations on CNTFET and ECNFET corresponding to gold and SiO2 are illustrated in Table 3. In this analysis, various materials are used for estimating the threshold voltage, because each layer has separate voltage. So, selecting an appropriate material for each layer is an important process. For gold material, the threshold voltage values for CNTFET and ECNFET are 0.210 and 0.205 V, respectively. Similarly, they are 0.240 and 0.230 V for SiO2. The proposed design reduces the voltage values by 2.38 and 4.17%, respectively.Table 3
Threshold voltage with respect to different materials.
MaterialsThreshold voltage (V)CNTFETECNFETGold0.2100.205Silicon dioxide (SiO2)0.2400.235Table4 compares the drain voltage of the existing CNFET and proposed ECNFET with respect to varying dielectric constants and drain current. The necessity of the drain voltage is decreased for a specific drain current in an ECNFET device. Here, the electric constant is varied for estimating the current value; based on this, the current consumption of the proposed ECNFET layout is calculated. Also, the voltage consumption is highly depending on the current consumption or resistance, so the current consumption must be reduced. Here, the current consumption is reduced with the increase of electric constant.Table 4
Comparative analysis based on dielectric constant and drain voltage.
Dielectric constantDrain current20 (μA)40 (μA)60 (μA)80 (μA)CNTFETECNFETCNTFETECNFETCNTFETECNFETCNTFETECNFET3.90.300.290.560.540.840.83—0.749.00.150.140.280.280.440.400.560.5315.60.110.100.220.200.330.310.440.4119.00.120.110.180.170.300.270.400.39The reduction of gate layer thickness of 0.6 nm in the proposed layout design reduces the drain voltage further compared to CNTFET models. For the high value of drain current (80μA) and dielectric constant (19), the drain voltage for CNTFET and ECNFET is 0.40 and 0.39 V, respectively. The comparative analysis between the proposed ECNFET with the existing CNTFET models shows that the proposed ECNFET provides the 2.5% reduction compared to the CNTFET model, respectively.


#### 4.5.1. Limitations of CNTFET

(i)
When modelling CNTFETs, a consistent model that is suitable for both analogue and digital applications and capable of mass production must be developed(ii)
The fault tolerance of CNTFET circuits should be investigated(iii)
Scalability of CNTFETs should be thoroughly investigated(iv)
It is necessary to discover new materials for the synthesis and integration of CNTFETs


## 4.1. Leakage Current

Figure10 graphically illustrates the leakage current of the proposed ECNFET design with respect to the gate voltage. The leakage current can flow between the source and drain, which is linearly increased with the increase of the gate voltage by minimum leakage current in nanoamps (nA) [33]. In the proposed application, the overall leakage current is reduced to 0.02 nA by using the ECNFET layout.Figure 10
Leakage current.Figure11 represents the drain current variations for the proposed ECNFET. With respect to gate-to-source voltage, there is a linear increase of gate-to-source voltage. The graphical variations of drain current show that it increased to 1.65 mA by using the ECNFET layout. On the basis of the threshold and saturation, the overall peak value of the current is estimated.Figure 11
Voltage current.


## 4.2. Mobility

The mobility defines the movement of electrons and holes from n-substrate to p-substrate, in which the electron conductivity and electron charge carrier are increased, when compared to the holes. The mobility of the proposed ECNFET layout is shown in Figure12. The linear increase in gate voltage from 0 to 2 V increases the mobility values linearly.Figure 12
Mobility graph.


## 4.3. Transconductance

Typically, the transconductance of ECNFET is based on the current of output device and the voltage of input device. Figure13 shows the transconductance of the ECNFET design. From the evaluation, it is observed that the transconductance is improved with respect to the varying gate source voltage and is evaluated in terms of VGS.Figure 13
Transconductance analysis.


## 4.4. Area, Power, Frequency, and Speed

Table1 provides the area consumption, power intake, frequency, and speed of both the existing CNTFET-based filtering design and the proposed ECNFET layout-based filtering design. Here, the amount of area and power required to design the layout is drastically reduced with the increase in the frequency range and speed. In this design, the best materials are used in this circuit design, which reduces the area and power consumption. Also, the operational amplifier improves the frequency range by amplifying the ECNFET layout. Moreover, the hearing aid filter improves the overall efficiency and speed of the system. Based upon the results, it is found that the suggested ECNFET-based hearing aid filtering design provides the better performance, in comparison to the available filtering design.Table 1
Performance analysis of ECNFET.
MeasuresExisting CNTFET filterProposed ECNFET hearing aid filterArea [35]151 components134 componentsPower [36]58.96μw26.03μwFrequency1.9×103 Hz2×103 HzSpeed [37]2.8×109 m/s4×1011 m/sDelay [37]7.4e−126.63e−14


## 4.5. Comparative Analysis

Table2 shows the threshold voltage of existing CNTFET and proposed ECNFET layouts based on varying temperatures. Due to the less heat dissipation mechanism, the heating effect of ECNFET is lower than that of CNTFET, in which the highest value appears in both source and drain, because the heat is nonuniformly distributed. Here, the threshold voltage is calculated with respect to various temperature values, which evaluates the optimized usage of voltage by the proposed layout. Moreover, different temperatures from 27°C to 227°C are taken to analyze the threshold voltage. For minimum temperature values (27°C), the threshold voltage values for CNTFET and ECNFET are 0.210 and 0.205 V, respectively. Similarly, they are 0.164 and 0.160 V for maximum temperature values 227°C, respectively. The comparative analysis between the proposed ECNFET with the CNTFET shows that the proposed model reduces the threshold voltage values by 2.38 and 2.44%, respectively.Table 2
Threshold voltage with respect to temperature.
Temperature (°C)Threshold voltage (V)CNTFETECNFET270.2100.205470.2100.205670.2100.204870.2100.2041070.2020.1981270.1980.1971470.1940.1931670.1910.1861870.1870.1822070.1800.1742270.1640.160Table3 compares the threshold voltage of CNTFET and ECNFET with respect to gold and silicon dioxide materials. The threshold voltage variations on CNTFET and ECNFET corresponding to gold and SiO2 are illustrated in Table 3. In this analysis, various materials are used for estimating the threshold voltage, because each layer has separate voltage. So, selecting an appropriate material for each layer is an important process. For gold material, the threshold voltage values for CNTFET and ECNFET are 0.210 and 0.205 V, respectively. Similarly, they are 0.240 and 0.230 V for SiO2. The proposed design reduces the voltage values by 2.38 and 4.17%, respectively.Table 3
Threshold voltage with respect to different materials.
MaterialsThreshold voltage (V)CNTFETECNFETGold0.2100.205Silicon dioxide (SiO2)0.2400.235Table4 compares the drain voltage of the existing CNFET and proposed ECNFET with respect to varying dielectric constants and drain current. The necessity of the drain voltage is decreased for a specific drain current in an ECNFET device. Here, the electric constant is varied for estimating the current value; based on this, the current consumption of the proposed ECNFET layout is calculated. Also, the voltage consumption is highly depending on the current consumption or resistance, so the current consumption must be reduced. Here, the current consumption is reduced with the increase of electric constant.Table 4
Comparative analysis based on dielectric constant and drain voltage.
Dielectric constantDrain current20 (μA)40 (μA)60 (μA)80 (μA)CNTFETECNFETCNTFETECNFETCNTFETECNFETCNTFETECNFET3.90.300.290.560.540.840.83—0.749.00.150.140.280.280.440.400.560.5315.60.110.100.220.200.330.310.440.4119.00.120.110.180.170.300.270.400.39The reduction of gate layer thickness of 0.6 nm in the proposed layout design reduces the drain voltage further compared to CNTFET models. For the high value of drain current (80μA) and dielectric constant (19), the drain voltage for CNTFET and ECNFET is 0.40 and 0.39 V, respectively. The comparative analysis between the proposed ECNFET with the existing CNTFET models shows that the proposed ECNFET provides the 2.5% reduction compared to the CNTFET model, respectively.


### 4.5.1. Limitations of CNTFET

(i)
When modelling CNTFETs, a consistent model that is suitable for both analogue and digital applications and capable of mass production must be developed(ii)
The fault tolerance of CNTFET circuits should be investigated(iii)
Scalability of CNTFETs should be thoroughly investigated(iv)
It is necessary to discover new materials for the synthesis and integration of CNTFETs


## 4.5.1. Limitations of CNTFET

(i)
When modelling CNTFETs, a consistent model that is suitable for both analogue and digital applications and capable of mass production must be developed(ii)
The fault tolerance of CNTFET circuits should be investigated(iii)
Scalability of CNTFETs should be thoroughly investigated(iv)
It is necessary to discover new materials for the synthesis and integration of CNTFETs


## 5. Conclusions

This paper designs a new hearing aid filtering application by using an ECNFET layout. Here, five different materials such as gold, silicon, silicon dioxide, bismuth telluride, and single-walled carbon nanotube are placed in the layers, which are selected based on their specific advantages. After selecting these materials, the parameters such as band gap, electron concentration, hole concentration, electron mobility, hole mobility, and insulator breakage voltage are validated. If all the parameters are satisfied, the characteristics of the layout are validated for proving the effectiveness of the proposed design. It includes voltage current, transconductance, mobility, and leakage current, which are all satisfied; the library is created for the corresponding ECNFET layout by using the Comsol tool. After that, the operational amplifier is designed based on the generated library function, which is used to improve the level of frequency. Finally, the hearing aid filter is implemented with the use of ECNFET layout that improves the accuracy of filter by efficiently reducing the noise. The experimental results evaluate the performance of this application based on different performance measures such as area consumption, power consumption, frequency range, and speed. The proposed ECNFET-hearing aid filter provides the better performance in drain voltage, current, threshold voltage, and mobility compared to the existing layout designs.The proposed ECNFET layout can been used to some other applications such as head phone, telephone, and biomedical devices in the future. The parameter estimation of CNTFET could be investigated further using other cutting-edge intelligent optimization algorithms. The most recent materials may be incorporated into the design of a CNTFET in order to identify the one that will yield the longest life of the CNTFET as well as the best performance.



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*Source: 7024032-2021-10-31.xml*