# A New Simple Chaotic Lorenz-Type System and Its Digital Realization Using a TFT Touch-Screen Display Embedded System

Authors: Rodrigo Méndez-Ramírez; Adrian Arellano-Delgado; César Cruz-Hernández; Rigoberto Martínez-Clark
Journal: Complexity
 (2017)

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## Abstract

This paper presents a new three-dimensional autonomous chaotic system. The proposed system generates a chaotic attractor with the variation of two parameters. Analytical and numerical studies of the dynamic properties to generate chaos, for continuous version (CV) and discretized version (DV), for the new chaotic system (NCS) were conducted. The CV of the NCS was implemented by using an electronic circuit with operational amplifiers (OAs). In addition, the presence of chaos for DV of the NCS was proved by using the analytical and numerical degradation tests; the time series was calculated to determine the behavior of Lyapunov exponents (LEs). Finally, the DV of NCS was implemented, in real-time, by using a novel embedded system (ES) Mikromedia Plus for PIC32MX7 that includes one microcontroller PIC32 and one thin film transistor touch-screen display (TFTTSD), together with external digital-to-analog converters (DACs).


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## Body

## 1. Introduction

In recent years, chaotic systems have attracted the attention of the scientific community due to their potential applications in several areas of science and engineering, as an interesting nonlinear phenomenon with different applications in biology, secure communication, complex networks, experimental network synchronization, fingerprint encryption, among others [1–15]. In 1963, Lorenz proposed a three-dimensional system of two scrolls; this is recognized as the first reported chaotic model [16]. Since then, many chaotic systems like Lorenz—and their chaotic behavior—have been reported in the literature, for example, [17–23]. Currently, we can mention some new chaotic systems reported in the literature [24–33].The chaotic systems usually are implemented by using electronic circuits in continuous (CV) and discretized versions (DV). The CVs usually are represented by using OAs [31, 34]. For DVs, Matlab or Labview allows simulating the dynamical behaviors of discretized chaotic systems to desirably obtain the less degradation with respect to CVs, and their implementations are reproduced by using ESs as FPGAs [35], DSPs [36], or microcontrollers [37–39].In this paper, we propose a new simple chaotic system, which is derived from the Lorenz system [16]. The novelty of the proposed chaotic system is the combination of different characteristics that it presents: two critical parameters, only two nonlinearities, low complexity time, low iterations per second, and a larger step size for the discretized version where chaos is preserved, low-cost electronic implementation; also it is flexible and robust with respect to some recent attractors reported in the literature; see, for example, [22, 23]. As a consequence, all these features result in a high ease of implementation that may be of great interest in engineering applications, for example, in cryptography, biometric systems, telemedicine, and secure communications; see, for example, [10, 12, 13, 37]. To the best of our knowledge the electronical implementation in a portable TFTTSD device of DV of chaotic systems, for the reproduction of their nonlinear dynamics in real-time, is new.The paper is organized as follows: Section2 reports basic analytical proof and extensive numerical tests to verify the existence of chaos in the proposed NCS. Section 3 presents two electronic implementations to reproduce the NCS: the first by means of OAs and the second of a novel proposed ES by using one TFTTSD and external DACs. In addition, a degradation study taking into account the preservation of chaos is conducted; a comparison among the NCS and some other chaotic systems reported in the literature is made. In Section 4, we give a complete description of digital implementation process of the DV of NSC with the corresponding robustness diagram to determine regions in which the existence of chaos is guaranteed. Finally, in Section 5 we draw some concluding remarks.


## 2. Basic Analysis and Characterization of NCS

This section presents the state equations of NCS and some numerical and analytical tests to verify the chaos existence in the proposed system. The NCS is built starting from inspecting and modification of Lorenz system [16]. The proposed NCS is described by(1)x˙=-ax-byz,y˙=-x+cy,z˙=d-y2-z.The proposed system has seven terms, two quadratic nonlinearities, and four parametersa,b,c,d∈R+, where b and d are characterized as the bifurcation parameters. The nonlinear NCS (1) is chaotic with a=2, b=2, c=0.5, and d=4.System (1) is symmetrical about the z-axis due to its invariance under the coordinate transformation (x,y,z) → (-x,-y,z). The symmetry is not associated with thea, b, c, andd parameters.The divergence for a 3-dimensional flow of dynamical system is defined by(2)∇V=∂x˙∂x+∂y˙∂y+∂z˙∂z=-a+c-1=-2.5<0.Therefore, the above analysis proves that our system is dissipative. The exponential contraction rate is calculated as follows:(3)dVdt=∇VV⟶V=V0e-2.5t,where each volume containing the system trajectory shrinks to zero as t→∞ at an exponential rate of -2.5t. System orbits are ultimately confined into a specific limit set of zero volume, and the asymptotic motion settles onto an attractor. Thereby, the existence on attractor is proved.The boundness of the chaotic trajectories of system (1) is proved by means of the following theorem. The boundness of a NCS by using similar approach was reported in [40, 41].Theorem 1.
Suppose that the parametersa, b, c, and d of system (1) are positive. Then, the orbits of system (1) including chaotic orbits are confined in a bounded region.Proof.
Consider the candidate Lyapunov function(4)Vx,y,z=12x2+y2+z2,and the time derivative of V(x,y,z) along the trajectories of the NCS (1) is given by(5)V˙x,y,z=xx˙+yy˙+zz˙,V˙x,y,z=-ax2-bxyz+cy2-xy+dz-zy2-z2=-byz2a+ax2+x2c-cy2-x24c-z-d22+d24+byz2a-ayb2-ay2b2.
LetR0 be the sufficiently large region so that for all trajectories (x,y,z) satisfy V(x,y,z) = R for R>R0 with the condition(6)byz2a+ax2+z-d22+ay2b2+x24c>x2c-cy2+byz2a-ayb2+d24.
Consequently on the surface(x,y,z)/Vx,y,z=R. Since R>R0 we can write V˙x,y,z<0, or the set (x,y,z)/Vx,y,z≤R is a confined region for all the trajectories of chaotic system (1).The number of the equilibrium points and their stabilities determine the behavior of system (1); it can be found by setting x˙=y˙=z˙=0 and a,b,c,d>0. The proposed system (1) has five fixed points: P00,0,0, P1,P2,P3,P4±cd+ac/b,±d+ac/b,-ac/b. The Jacobean matrix of CV-system (1) is given by(7)JCV=-a-bz-by-1c00-2y-1,and the characteristic polynomial of (7) is as follows:(8)det⁡λI-J=λ3+a-c+1λ2+a-c-ac-bzλ+2by2-ac-bz=0.Evaluating with parameters a=2,b = 2,c = 0.5, andd = 4 in (8), the stability in the equilibrium points P0,1,2,3,4 was studied. Table 1 shows the stability results of equilibria where all points of NCS are saddle-focus unstable nodes.Table 1
Stability analysis equilibrium points for NCS.
Point
Eigenvalues
Stability
P0
λ
1
=
-
2
λ
1, λ2<0, and λ3>0, unstable saddle point
λ
2
=
-
1
λ
3
=
0.5
P1,P2,P3,P4
λ
1
=
-
3.52387
λ
1
<
0 and the real part of λ2,λ3>0, unstable saddle points
λ
2
=
0.51193
+
2.20134
i
λ
3
=
0.51193
+
2.20134
iThe bifurcation diagram is built to visualize the transitions between periodic and chaotic motions of the proposed system, with the variation of the critical parameterb ord of NCS (1); for more details of the numerical algorithm to obtain the bifurcation diagram see [42]. Figure 1(a) shows the bifurcation diagram of system (1), where the parameters a=2, c=2, and d=4 were fixed, and b is varied. In addition, Figure 1(b) shows the bifurcation diagram of system (1) where the parameters a=2, b=2, and c=0.5 were fixed, andd is varied. From Figure 1 we conclude that system (1) is also robust because it has a large chaotic behavior for parameters b and d to guarantee chaotic behaviors: fixed point, limit cycle, and strange attractor.Figure 1
Bifurcation diagrams of parametersb and d, versus state x using the initial conditions x0=y0=z0 = 1 of system (1): (a) variations of b=[0.5,5] and (b) variations of d=[0.5,5].
(a)
(b)In this numerical study, the parameterb is fixed and the parameter d is choice as bifurcation parameter. The initial conditions x0=y0=z0 = 1 and parameters a=2, b=2, c=0.5, and d=4 were chosen for all numerical and experimental tests.To prove the presence of chaos on the NCS (1), the LEs are calculated using the method reported in [43, 44]. Figure 2 shows the results of the LEs where 10000 time units were considered in the analysis. Figure 2(a) shows the evolution of LEs where the obtained results are L1 = 0.24914, L2 = 0, and L3 = −2.7497. Figure 2(b) shows evolution of LEs considering the variation of bifurcation parameter d = [0.5, 5].Figure 2
LEs of system (1): (a) the bifurcation parameter fixed in d = 4 and (b) variation of bifurcation parameter d=[0.5,5].
(a)
(b)The fractal dimension, commonly known as Kaplan-Yorke dimensionDKY, of this system is(9)DKY=j+1Lj+1∑i=1jLi=2+L1+L2L3=2.0908.The NCS exhibits complex and abundant dynamics behaviors; see Figure3 where chaotic attractors are shown.Figure 3
Chaotic attractors of system (1): (a) phase plane x versus y, (b) phase plane x versus z, (c) phase plane y versus z, and (d) phase space x versus y versus z.
(a)
(b)
(c)
(d)


## 3. Electronic Implementations

This section presents two electronic implementations for system (1): (i) the CV was simulated and implemented with the design of one circuit by using OAs, and (ii) the DV was implemented with design of an ES where one degradation study of NCS is also given.


### 3.1. Electronic Circuit Design for CV of NCS

For the electronic implementation of CV-system (1) the attenuation factor of 20 for each of the state variablesx=20u, y=20v, and z=20w was calculated. Replacing the new variables on system (1), we obtain the following system:(10)u˙=-2u-40vw,v˙=-u+0.5v,w˙=0.2-20v2-w.Replacing the state variablesx=u,  y=v, and  z=w in system (10), the representation of circuit is(11)x˙=1RCl-RRlx-R10Rl0yz,y˙=1RC2-x+RR5y,z˙=1RC3RR9b-R10R8y2-z,where the components are OAs TL084, multipliers AD633, C1=C2=C3=100 pF, R1=500 kΩ, R2=47 kΩ, R=R10=1 MΩ, R3=2 MΩ, R6=100 kΩ, R4=R5=R8=R9=R12=R13=10 kΩ, and R7=5 MΩ, the bifurcation parameter is fixed in d=4 with R11=287 kΩ, and the circuit of Figure 4 is powered with +Vcc=18 V and -Vcc=-18 V. To see a change in the dynamical behavior of system (11), it is recommend to represent the bifurcation parameter d with a variable resistor of R11VAR=1 MΩ; this voltage was referred to as Vd. Figure 4 shows the equivalent circuit of system (11).Figure 4
Schematic diagram of the equivalent circuit of system (11).In order to compare the experimental with numerical results, Figure5 shows the comparison on phase planes of system (11) between Multisim simulation and electronic circuit implementation; we can see that the corresponding attractors are similar with respect to those shown in Figure 3.Figure 5
Comparison on phase planes between simulation and circuit implementation of system (11). Multisim simulation: (a) x versus y, (b) x versus z, and (c) y versus z, and electronic circuit implementation: (d) x versus y, (e) x versus z, and (f) y versus z.
(a)
(b)
(c)
(d)
(e)
(f)


### 3.2. DV of NCS and Its Digital Implementation

It is well known that Euler’s method in order to discretize a continuous system is derived from the expansion of Taylor’s series, when the quadratic and upper order term are truncated. The Euler method to approximate the ordinary differential equations (ODEs),(12)x˙=fx,x0=x0,x∈RN,is given by(13)xn+1=xn+τfxn,where τ is thestep size and n is theiteration number that represent the time in discrete version. Euler’s discretization (13) was considered to obtain the DV of the proposed NCS (1) as follows:(14)xn+1=xn+τ-axn-bynzn,yn+1=yn+τ-xn+cyn,zn+1=zn+τd-yn2-zn.The advantage of Euler’s method is that it is easy to understand and simple to execute as numerical algorithm; in addition it has low time complexity. Even though its low accuracy, this method is widely used for solving (numerically) ODEs; for more details, please see [45].The Matlab simulations of the DV-system (14) were carried out by using τ=0.005 and n=40000. Figure 6 shows the phase space xn versus yn versus zn of DV-system (14).Figure 6
Chaotic attractor of DV-system (14) projected on xn versus yn versus zn.Microchip Technology Inc. is the manufacturer of microcontroller PIC32, their numerical results were represented in floating points 32 bits according to the IEEE-754 Compliant Floating Point Routines [46]. The standard IEEE-754 also is included in Matlab for 32-bit version [45]. The microcontroller PIC32 was programmed by using Mikroc Pro for Pic 32 compiler that includes the standard IEEE-754; this means that the numerical results in simulation by using Matlab to represent the DV-system (14) and implementation by using Mikroc Pro for Pic 32 compiler are equivalents.We use a novel method reported in [37, 38] in order to reproduce the DV of chaotic system (14) by using an PIC32 microcontroller and external DACs connected by the serial peripheral interface (SPI) protocol. The compact ES Mikromedia Plus for PIC32MX7 contains one 32-bit PIC32MX795F512L microcontroller as central part. The Mikromedia Plus for PIC32MX7 ES allows development applications with multimedia contents, and it comes with several internal hardware-devices. We use the internal module TFTTSD (with one screen of 4.3 inches of 480 × 272 resolution) to represent, in real-time, the three phase planes of DV-system (12). TFT touch and LCD controller units are included into TFTTSD. Table 2 shows the hardware and the SPI modes description of the ES, and the schematic circuit diagram is shown in Figure 7. The evolution of discretized states xn, yn, and zn of DV-system (14) were reproduced by using the external DACs U1, U2, and U3, respectively.Table 2
Main hardware description of ES.
Peripheral number
SPI mode, hardware description
U1
Master, TFTTSD Mikromedia Plus for PIC32MX7
U2
Slave 1, DAC MCP4921 showsx(t)
U3
Slave 2, DAC MCP4921 showsy(t)
U4
Slave 3, DAC MCP4921 showsz(t)Figure 7
Schematic circuit design of ES for the implementation of DV-system (14).System (14) describes N=3 dimension. To understand the simulation and implementation, the calculus of time was carried out in the algorithm of U1 to reproduce DV-system (14) on the ES. The time period TTdN was considered as total-decoding-time that the ES requires to process one iteration n. The maximum number of iterations n that the ES generates in 1 second (i.p.s.) was calculated by frequency fTdN, that is, the reciprocal of TTdN; these terms are represented by(15)TTdN=1fTdN=tc+tTgN,where thetime complexitytc defines the time that the algorithm of U1 needs to reproduce one iteration n. The total-graphics-time tTgN is the time that U1 needs to enable the internal device TFTTSD and the DACs U2, U3, and U4 to reproduce in real-time one iteration n; we proposed the calculus of TTdN considering DV-systems for N dimensions, where tTgN was calculated externally of tc. The total time required for each DAC is referred to as tTdacN, and the time required for TFTTSD is referred to as ttft. The total-graphics-time is represented by(16)tTgN=ttft+tdacj+tdacj+1+⋯+tdacN=ttft+∑j=1NtTdacj,j=1,2,…,N.In order to develop the equivalence between simulation and implementation on the ES, we defined the total quantity of iterationsQT as the maximumnumber ofniterations generated in 1 second,(17)QTN=3=τ1TTdN=τfTdN.The time for one specific number of iterations n generated from the DV-system (14) is calculated by using the following expression:(18)tn=ntc+tTgN=ntc+ttft+tTdacN.Figure8 and Table 3 show the implementation of system (14) to exemplify (15)–(18). Finally, we obtained QT = 9.17 considering τ = 0.01; this means that in 1 second we obtained 9.17 time units. Figure 8(d) shows QT = 91.7 for t = 10 s.Table 3
Implementation results of DV-system (14) on the proposed ES.
Parameter
Value
τ
0.01
tTg(3)
27μs
ttft
24μs
fTd(3)
917 i.p.s.
QT(3)
9.17
tc
1063μs
TTd(3)
1090μs
n
917
tTdac(3)
3μs
tn=917
0.99953 sFigure 8
Implementation of DV-system (14) on proposed ES: (a) phase plane xn versus yn, (b) phase plane xn versus zn, (c) phase plane yn versus zn, (d) time evolution of states x(t) and z(t) by using τ = 0.01 and t = 10 s, and (e) representation of phase planes xn versus yn, xn versus zn, and yn versus zn on TFTTSD.
(a)
(b)
(c)
(d)
(e)


### 3.3. Degradation Study for DV of NCS

To prove the presence of chaos on the NCS (1), the LEs for discretized system (14) were calculated by using time series [43, 44]. The result of Jacobean matrix for the discretized system (14) is(19)JDV=1-aτ-bτzn-bτyn-τ1+cτ00-2τyn1-τ,where the step size τ was modified as parameter to prove the chaotic behavior of the DV-system (14); τ is modified by using an increase of step size τ = 0.001 regarding 10000 time units, until the sign of the LEs changes and the discretized system (14) diverges. The LEs and fractal dimension of discretized system (14) are referred to as L1′,L2′,L3′ and DKY′, respectively. Figure 9 and Table 4 show the result of chaos degradation corresponding to DV-system (14) for 2 cases.Table 4
Analysis of chaos degradation for DV-system (14) by using LEs.
Case
τ
LEs
Result
1
(0, 0.085]
L
1
′
=
+
0.050763
Chaotic behavior shown in Figure9(a)
L2′=-0.000064588
L3′=-0.24347
DKY′=2.0996
2
[0.086, +∞)
L
1
′ = no valid
No displayed chaos, see Figure9(b)
L
2
′ = no valid
L
3
′ = no valid
D
K
Y
′ = no validFigure 9
LEs of discretized system (14) for (a) τ = 0.085 and (b) τ = 0.086.
(a)
(b)For case 1, the discretized system (14) conserves the chaotic behavior. This result was compared with the LEs calculated for CV of system (1) where the numerical results of L1 and DKY were similar with respect to L1′ and DKY′. The maximum step size τ=0.085 was found. For case 2, the step size was increased until obtaining τ=0.086, whereby LEs can not be calculated in the DV-system (14). For values of τ≥0.086, the discretized system (14) diverges and the state trajectories xn, yn, and zn can not display chaos.


### 3.4. Comparison of the Proposed NCS with Some Chaotic Systems

In order to compare the performance of the NCS (14) in DV, we studied the chaotic degradation of four 3D Lorenz, Rössler, Chen, and Liu and Chen classical chaotic systems where their DVs were obtained by using the same Euler discretization (13), and the LEs were calculated by using the same method as in [43, 44]. Table 5 shows the results of the step sizes τ intervals of the five Lorenz, Rössler, Chen, and Liu and Chen CSs using the Euler numerical algorithm (13) where the chaotic behavior is conserved in these chaotic systems [16, 17, 22, 23]. According to Table 5, the proposed NCS in DV (14) presents a higher step size with respect to the other four 3D Lorenz, Rössler, Chen, and Liu and Chen chaotic systems in DV. This means that, for implementation, the NCS in DV has more compacts dynamics to digital implementations; then the NCS in DV is a good alternative using ESs where the main part has less processing capacity, for example, 8-bit microcontrollers family. The novelty of the proposed chaotic system is the combination of the different characteristics that it presents, which results in a high ease of implementation for its use in different applications as previously mentioned.Table 5
Comparison of the proposed NCS with some chaotic systems reported in the literature.
Chaotic system
Parameters
Critical parameters
Nonlinearities
Step sizeτ
Total timeμs
Iterations per second
Time unitsQT
Lorenz
σ, b, c
σ
2
≤0.024
1090
917
22
Rössler
a, b, c
c
1
≤0.005
1073
932
4.7
Chen
a, b, c
a
2
≤0.002
1090
917
1.8
Liu and Chen
a, b, c, d1, d2, d3
c
3
≤0.002
1096
912
1.8
Proposed NCS
a, b, c, d
b, d
2
≤0.085
1090
917
78


## 3.1. Electronic Circuit Design for CV of NCS

For the electronic implementation of CV-system (1) the attenuation factor of 20 for each of the state variablesx=20u, y=20v, and z=20w was calculated. Replacing the new variables on system (1), we obtain the following system:(10)u˙=-2u-40vw,v˙=-u+0.5v,w˙=0.2-20v2-w.Replacing the state variablesx=u,  y=v, and  z=w in system (10), the representation of circuit is(11)x˙=1RCl-RRlx-R10Rl0yz,y˙=1RC2-x+RR5y,z˙=1RC3RR9b-R10R8y2-z,where the components are OAs TL084, multipliers AD633, C1=C2=C3=100 pF, R1=500 kΩ, R2=47 kΩ, R=R10=1 MΩ, R3=2 MΩ, R6=100 kΩ, R4=R5=R8=R9=R12=R13=10 kΩ, and R7=5 MΩ, the bifurcation parameter is fixed in d=4 with R11=287 kΩ, and the circuit of Figure 4 is powered with +Vcc=18 V and -Vcc=-18 V. To see a change in the dynamical behavior of system (11), it is recommend to represent the bifurcation parameter d with a variable resistor of R11VAR=1 MΩ; this voltage was referred to as Vd. Figure 4 shows the equivalent circuit of system (11).Figure 4
Schematic diagram of the equivalent circuit of system (11).In order to compare the experimental with numerical results, Figure5 shows the comparison on phase planes of system (11) between Multisim simulation and electronic circuit implementation; we can see that the corresponding attractors are similar with respect to those shown in Figure 3.Figure 5
Comparison on phase planes between simulation and circuit implementation of system (11). Multisim simulation: (a) x versus y, (b) x versus z, and (c) y versus z, and electronic circuit implementation: (d) x versus y, (e) x versus z, and (f) y versus z.
(a)
(b)
(c)
(d)
(e)
(f)


## 3.2. DV of NCS and Its Digital Implementation

It is well known that Euler’s method in order to discretize a continuous system is derived from the expansion of Taylor’s series, when the quadratic and upper order term are truncated. The Euler method to approximate the ordinary differential equations (ODEs),(12)x˙=fx,x0=x0,x∈RN,is given by(13)xn+1=xn+τfxn,where τ is thestep size and n is theiteration number that represent the time in discrete version. Euler’s discretization (13) was considered to obtain the DV of the proposed NCS (1) as follows:(14)xn+1=xn+τ-axn-bynzn,yn+1=yn+τ-xn+cyn,zn+1=zn+τd-yn2-zn.The advantage of Euler’s method is that it is easy to understand and simple to execute as numerical algorithm; in addition it has low time complexity. Even though its low accuracy, this method is widely used for solving (numerically) ODEs; for more details, please see [45].The Matlab simulations of the DV-system (14) were carried out by using τ=0.005 and n=40000. Figure 6 shows the phase space xn versus yn versus zn of DV-system (14).Figure 6
Chaotic attractor of DV-system (14) projected on xn versus yn versus zn.Microchip Technology Inc. is the manufacturer of microcontroller PIC32, their numerical results were represented in floating points 32 bits according to the IEEE-754 Compliant Floating Point Routines [46]. The standard IEEE-754 also is included in Matlab for 32-bit version [45]. The microcontroller PIC32 was programmed by using Mikroc Pro for Pic 32 compiler that includes the standard IEEE-754; this means that the numerical results in simulation by using Matlab to represent the DV-system (14) and implementation by using Mikroc Pro for Pic 32 compiler are equivalents.We use a novel method reported in [37, 38] in order to reproduce the DV of chaotic system (14) by using an PIC32 microcontroller and external DACs connected by the serial peripheral interface (SPI) protocol. The compact ES Mikromedia Plus for PIC32MX7 contains one 32-bit PIC32MX795F512L microcontroller as central part. The Mikromedia Plus for PIC32MX7 ES allows development applications with multimedia contents, and it comes with several internal hardware-devices. We use the internal module TFTTSD (with one screen of 4.3 inches of 480 × 272 resolution) to represent, in real-time, the three phase planes of DV-system (12). TFT touch and LCD controller units are included into TFTTSD. Table 2 shows the hardware and the SPI modes description of the ES, and the schematic circuit diagram is shown in Figure 7. The evolution of discretized states xn, yn, and zn of DV-system (14) were reproduced by using the external DACs U1, U2, and U3, respectively.Table 2
Main hardware description of ES.
Peripheral number
SPI mode, hardware description
U1
Master, TFTTSD Mikromedia Plus for PIC32MX7
U2
Slave 1, DAC MCP4921 showsx(t)
U3
Slave 2, DAC MCP4921 showsy(t)
U4
Slave 3, DAC MCP4921 showsz(t)Figure 7
Schematic circuit design of ES for the implementation of DV-system (14).System (14) describes N=3 dimension. To understand the simulation and implementation, the calculus of time was carried out in the algorithm of U1 to reproduce DV-system (14) on the ES. The time period TTdN was considered as total-decoding-time that the ES requires to process one iteration n. The maximum number of iterations n that the ES generates in 1 second (i.p.s.) was calculated by frequency fTdN, that is, the reciprocal of TTdN; these terms are represented by(15)TTdN=1fTdN=tc+tTgN,where thetime complexitytc defines the time that the algorithm of U1 needs to reproduce one iteration n. The total-graphics-time tTgN is the time that U1 needs to enable the internal device TFTTSD and the DACs U2, U3, and U4 to reproduce in real-time one iteration n; we proposed the calculus of TTdN considering DV-systems for N dimensions, where tTgN was calculated externally of tc. The total time required for each DAC is referred to as tTdacN, and the time required for TFTTSD is referred to as ttft. The total-graphics-time is represented by(16)tTgN=ttft+tdacj+tdacj+1+⋯+tdacN=ttft+∑j=1NtTdacj,j=1,2,…,N.In order to develop the equivalence between simulation and implementation on the ES, we defined the total quantity of iterationsQT as the maximumnumber ofniterations generated in 1 second,(17)QTN=3=τ1TTdN=τfTdN.The time for one specific number of iterations n generated from the DV-system (14) is calculated by using the following expression:(18)tn=ntc+tTgN=ntc+ttft+tTdacN.Figure8 and Table 3 show the implementation of system (14) to exemplify (15)–(18). Finally, we obtained QT = 9.17 considering τ = 0.01; this means that in 1 second we obtained 9.17 time units. Figure 8(d) shows QT = 91.7 for t = 10 s.Table 3
Implementation results of DV-system (14) on the proposed ES.
Parameter
Value
τ
0.01
tTg(3)
27μs
ttft
24μs
fTd(3)
917 i.p.s.
QT(3)
9.17
tc
1063μs
TTd(3)
1090μs
n
917
tTdac(3)
3μs
tn=917
0.99953 sFigure 8
Implementation of DV-system (14) on proposed ES: (a) phase plane xn versus yn, (b) phase plane xn versus zn, (c) phase plane yn versus zn, (d) time evolution of states x(t) and z(t) by using τ = 0.01 and t = 10 s, and (e) representation of phase planes xn versus yn, xn versus zn, and yn versus zn on TFTTSD.
(a)
(b)
(c)
(d)
(e)


## 3.3. Degradation Study for DV of NCS

To prove the presence of chaos on the NCS (1), the LEs for discretized system (14) were calculated by using time series [43, 44]. The result of Jacobean matrix for the discretized system (14) is(19)JDV=1-aτ-bτzn-bτyn-τ1+cτ00-2τyn1-τ,where the step size τ was modified as parameter to prove the chaotic behavior of the DV-system (14); τ is modified by using an increase of step size τ = 0.001 regarding 10000 time units, until the sign of the LEs changes and the discretized system (14) diverges. The LEs and fractal dimension of discretized system (14) are referred to as L1′,L2′,L3′ and DKY′, respectively. Figure 9 and Table 4 show the result of chaos degradation corresponding to DV-system (14) for 2 cases.Table 4
Analysis of chaos degradation for DV-system (14) by using LEs.
Case
τ
LEs
Result
1
(0, 0.085]
L
1
′
=
+
0.050763
Chaotic behavior shown in Figure9(a)
L2′=-0.000064588
L3′=-0.24347
DKY′=2.0996
2
[0.086, +∞)
L
1
′ = no valid
No displayed chaos, see Figure9(b)
L
2
′ = no valid
L
3
′ = no valid
D
K
Y
′ = no validFigure 9
LEs of discretized system (14) for (a) τ = 0.085 and (b) τ = 0.086.
(a)
(b)For case 1, the discretized system (14) conserves the chaotic behavior. This result was compared with the LEs calculated for CV of system (1) where the numerical results of L1 and DKY were similar with respect to L1′ and DKY′. The maximum step size τ=0.085 was found. For case 2, the step size was increased until obtaining τ=0.086, whereby LEs can not be calculated in the DV-system (14). For values of τ≥0.086, the discretized system (14) diverges and the state trajectories xn, yn, and zn can not display chaos.


## 3.4. Comparison of the Proposed NCS with Some Chaotic Systems

In order to compare the performance of the NCS (14) in DV, we studied the chaotic degradation of four 3D Lorenz, Rössler, Chen, and Liu and Chen classical chaotic systems where their DVs were obtained by using the same Euler discretization (13), and the LEs were calculated by using the same method as in [43, 44]. Table 5 shows the results of the step sizes τ intervals of the five Lorenz, Rössler, Chen, and Liu and Chen CSs using the Euler numerical algorithm (13) where the chaotic behavior is conserved in these chaotic systems [16, 17, 22, 23]. According to Table 5, the proposed NCS in DV (14) presents a higher step size with respect to the other four 3D Lorenz, Rössler, Chen, and Liu and Chen chaotic systems in DV. This means that, for implementation, the NCS in DV has more compacts dynamics to digital implementations; then the NCS in DV is a good alternative using ESs where the main part has less processing capacity, for example, 8-bit microcontrollers family. The novelty of the proposed chaotic system is the combination of the different characteristics that it presents, which results in a high ease of implementation for its use in different applications as previously mentioned.Table 5
Comparison of the proposed NCS with some chaotic systems reported in the literature.
Chaotic system
Parameters
Critical parameters
Nonlinearities
Step sizeτ
Total timeμs
Iterations per second
Time unitsQT
Lorenz
σ, b, c
σ
2
≤0.024
1090
917
22
Rössler
a, b, c
c
1
≤0.005
1073
932
4.7
Chen
a, b, c
a
2
≤0.002
1090
917
1.8
Liu and Chen
a, b, c, d1, d2, d3
c
3
≤0.002
1096
912
1.8
Proposed NCS
a, b, c, d
b, d
2
≤0.085
1090
917
78


## 4. Digital Implementation Process

In this section, we present the flow chart and the description of the electronical/digital implementation process that contains the proposed programming algorithm for the implementation of the NSC in DV (14). In addition, we present some aspects of implementation robustness from the point of view of software and hardware, a study regarding the robustness of the critical parameters, and comparative advantages of the implementation for the NSC in DV (14).


### 4.1. Flow Chart Digital Implementation

In Figure10, we illustrate the flow chart of the general electronical/digital implementation process. The description of each step is described below.Figure 10
Flow chart of the general electronical/digital implementation process.Step 1.
Set initial calibration of the TFTTSD U1. The TFTTSD is initialized and an internal program that allows calibrating the internal TFT touch and LCD controllers of the TFTTSD is executed; the four edges of the TFT screen are used.Step 2.
Set graphic environment, variables, and parameters of NCS in DV (14) on PIC32MX795F512L microcontroller. The floating point and decimal-base constants to be used in the programming algorithm of the NSC in DV (14) are defined.Step 3.
Initialization of ports and SPI protocol: the SPI protocol of the main PIC32MX795F512L microcontroller is configured in master mode and the SPI of the external DACs U1, U2, and U3 are configured in slave mode.Step 4.
Set the critical parameters, initial conditionsx0,y0,z0, and step size τ for NCS in DV (14). The critical parametersa = 2,b = 2,c = 0.5, andd = 4, initial conditions x0=y0=z0 = 1, and step size τ = 0.004 corresponding to the initial iteration of the NCS in DV (14) are defined.Step 5.
Definition of the NCS in DV (14) using Euler’s numerical algorithm. The discretized NCS is defined by the Euler’s numerical algorithm. Delay time in this stage is 14 μs.Step 6.
Storing the current values of state variablesxn, yn, and zn: this value corresponds to the next iteration of the NCS in DV (14). Delay time in this stage is 0.2 μs.Step 7.
Rescaling the state variablesxn, yn, and zn in positive scale: Representation of the state variables xn, yn, and zn is rescaled, since the numerical representation in the TFTTSD and the DACs is positive. Delay time in this stage is 1033.7 μs.Step 8.
Rescaling the values of state variablesxn, yn, and zn for the TFTTSD in 480 × 272 resolution: to display images in the TFTTSD, Visual TFT software is used to design a template that displays graphics and text. In our case, the evolution of the phase planes xn versus yn, xn versus zn, and yn versus zn is shown in real-time. In addition, the names of the authors are shown. Delay time in this stage is 7.5 μs.Step 9.
Write the TFTTSD using the TFT library to draw a dot at certain coordinates for each phase plane:xn versus yn in red color, xn versus zn in green color, and yn versus zn in blue color. Once the values are rescaled within the TFTTSD resolution, the “TFT__Dot” library is used to display a point with a different color according to the coordinates indicated by the phase planes of each state variable. Delay time in this stage is 24 μs.Step 10.
Rescaling the values of state variablesxn, yn, and zn in 12 bits for the DACs U2, U3, and U4: for the implementation of the state variables xn, yn, and zn, a positive scale is used with a maximum resolution interval of 12 bits, from 0 to 4095 which is the working range of the DACs and the SPI protocol, resulting in 16 Mbps. Delay time in this stage is 7.6 μs.Step 11.
Write the external DACs U2, U3, and U4 using the SPI protocol to reproduce the state variablesxn, yn, and zn. The microcontroller PIC32MX795F512L configured in master mode is used to enable the select chip and write the DACs U1, U2, and U3 (configured in slave mode), where the state variables xn, yn, and zn are reproduced simultaneously. Delay time in this stage is 3 μs.Finally, a loop from Steps11–5 is performed where the parameter values of the NSC in DV (14) and τ were previously defined according to Table 4.


### 4.2. Robustness in the Implementation of the NCS Digital Version

According to [47], software robustness is the ability of a product to stay in service and function correctly even with the occurrence of errors that are attributable to hardware, software, or even external influences. The implemented software in the TFTTSD is designed from graphical interface tools using the Visual TFT in conjunction with programming code designed in C language that is stored in the PIC32MX795F512L microcontroller flash memory. The accuracy of the programming algorithm calculations depends on the IEEE-754 AN575 standardization of the PIC32MX795F512L microcontroller [46]. With regard to hardware, the TFTTSD has two possible forms of energization: the first is through the USB port connected to a laptop or desktop PC; the second is via an external lithium battery. The possibility that the TFTTSD can be energized through an external battery makes it portable, which allows the autonomy of the equipment.On the other hand, in order to show the robustness of chaos presence in the discretized system (14), a robustness diagram based on the variation of critical parametersb andd was carried out. In this diagram it is possible to determine the regions in which the existence of chaos is guaranteed, considering τ = 0.085. Figure 11 shows the regions of chaos existence forb versusd (intervals of 0.01 are used for both parametersb andd) where each point in the graph represents the maximum Lyapunov exponent (Lmax′). If we have Lmax′>0, that is, if the dynamics are chaotic, the red color is used; otherwise, the blue color is used. From the robustness diagram in Figure 11 it can be seen that the chaotic dynamics are preserved for wide intervals of the parameter valuesb andd.Figure 11
Robustness diagram to determine chaos existence forb versusd at intervals of 0.01 and with τ = 0.085:chaos (red), no chaos (blue).Furthermore, it is easy to note that if a value ofτ less than 0.085 is considered, then the chaos regions increase. Taking into account the fact that the preservation of chaos in the discretized version of the NCS proposed is robust for the parametersb andd, considering the software and hardware characteristics of the proposed ES, and the benefits of digital systems, as the elimination of the typical wear of the analog systems, it is stated that the electronical/digital implementation presented in this work is robust.On the other hand, to the best of our knowledge the electronical implementation in a portable TFTTSD device of DV of chaotic systems, for the reproduction of their nonlinear dynamics in real-time, is new. By having a graphical interface and given certain potential applications in the engineering field, such as biometric systems, telemedicine, cryptography, and secure communications, the proposed digital implementation makes the interaction between the device and the end user very friendly. One of the most relevant advantages of the NSC in DV (14) is the increase in step size compared with other chaotic systems, which allows implementation in slower microcontrollers, for example, in 8-bit low-end microcontrollers; microchip PIC microcontrollers, Motorola M68HC05 microcontrollers, AVR microcontrollers, ATmega328, and 8051 from the manufacturer Atmel. In the same way, there are alternative families of 16-bit mid-range microcontrollers to implement the NSC in DV (14), such as the dsPIC family of manufacturer microchip, MSP430 of Texas Instruments.Finally, we can find the high-end microcontrollers, which are those used in the implementation presented in this work. A microchip PIC32 microcontroller was used which shows great benefits in the use of TFTTSD; along with this microcontroller there are other alternatives such as the STM32 microcontrollers of the manufacturer STMicroelectronics or the FT900 microcontrollers of the manufacturer Future Technology Devices International Limited.


## 4.1. Flow Chart Digital Implementation

In Figure10, we illustrate the flow chart of the general electronical/digital implementation process. The description of each step is described below.Figure 10
Flow chart of the general electronical/digital implementation process.Step 1.
Set initial calibration of the TFTTSD U1. The TFTTSD is initialized and an internal program that allows calibrating the internal TFT touch and LCD controllers of the TFTTSD is executed; the four edges of the TFT screen are used.Step 2.
Set graphic environment, variables, and parameters of NCS in DV (14) on PIC32MX795F512L microcontroller. The floating point and decimal-base constants to be used in the programming algorithm of the NSC in DV (14) are defined.Step 3.
Initialization of ports and SPI protocol: the SPI protocol of the main PIC32MX795F512L microcontroller is configured in master mode and the SPI of the external DACs U1, U2, and U3 are configured in slave mode.Step 4.
Set the critical parameters, initial conditionsx0,y0,z0, and step size τ for NCS in DV (14). The critical parametersa = 2,b = 2,c = 0.5, andd = 4, initial conditions x0=y0=z0 = 1, and step size τ = 0.004 corresponding to the initial iteration of the NCS in DV (14) are defined.Step 5.
Definition of the NCS in DV (14) using Euler’s numerical algorithm. The discretized NCS is defined by the Euler’s numerical algorithm. Delay time in this stage is 14 μs.Step 6.
Storing the current values of state variablesxn, yn, and zn: this value corresponds to the next iteration of the NCS in DV (14). Delay time in this stage is 0.2 μs.Step 7.
Rescaling the state variablesxn, yn, and zn in positive scale: Representation of the state variables xn, yn, and zn is rescaled, since the numerical representation in the TFTTSD and the DACs is positive. Delay time in this stage is 1033.7 μs.Step 8.
Rescaling the values of state variablesxn, yn, and zn for the TFTTSD in 480 × 272 resolution: to display images in the TFTTSD, Visual TFT software is used to design a template that displays graphics and text. In our case, the evolution of the phase planes xn versus yn, xn versus zn, and yn versus zn is shown in real-time. In addition, the names of the authors are shown. Delay time in this stage is 7.5 μs.Step 9.
Write the TFTTSD using the TFT library to draw a dot at certain coordinates for each phase plane:xn versus yn in red color, xn versus zn in green color, and yn versus zn in blue color. Once the values are rescaled within the TFTTSD resolution, the “TFT__Dot” library is used to display a point with a different color according to the coordinates indicated by the phase planes of each state variable. Delay time in this stage is 24 μs.Step 10.
Rescaling the values of state variablesxn, yn, and zn in 12 bits for the DACs U2, U3, and U4: for the implementation of the state variables xn, yn, and zn, a positive scale is used with a maximum resolution interval of 12 bits, from 0 to 4095 which is the working range of the DACs and the SPI protocol, resulting in 16 Mbps. Delay time in this stage is 7.6 μs.Step 11.
Write the external DACs U2, U3, and U4 using the SPI protocol to reproduce the state variablesxn, yn, and zn. The microcontroller PIC32MX795F512L configured in master mode is used to enable the select chip and write the DACs U1, U2, and U3 (configured in slave mode), where the state variables xn, yn, and zn are reproduced simultaneously. Delay time in this stage is 3 μs.Finally, a loop from Steps11–5 is performed where the parameter values of the NSC in DV (14) and τ were previously defined according to Table 4.


## 4.2. Robustness in the Implementation of the NCS Digital Version

According to [47], software robustness is the ability of a product to stay in service and function correctly even with the occurrence of errors that are attributable to hardware, software, or even external influences. The implemented software in the TFTTSD is designed from graphical interface tools using the Visual TFT in conjunction with programming code designed in C language that is stored in the PIC32MX795F512L microcontroller flash memory. The accuracy of the programming algorithm calculations depends on the IEEE-754 AN575 standardization of the PIC32MX795F512L microcontroller [46]. With regard to hardware, the TFTTSD has two possible forms of energization: the first is through the USB port connected to a laptop or desktop PC; the second is via an external lithium battery. The possibility that the TFTTSD can be energized through an external battery makes it portable, which allows the autonomy of the equipment.On the other hand, in order to show the robustness of chaos presence in the discretized system (14), a robustness diagram based on the variation of critical parametersb andd was carried out. In this diagram it is possible to determine the regions in which the existence of chaos is guaranteed, considering τ = 0.085. Figure 11 shows the regions of chaos existence forb versusd (intervals of 0.01 are used for both parametersb andd) where each point in the graph represents the maximum Lyapunov exponent (Lmax′). If we have Lmax′>0, that is, if the dynamics are chaotic, the red color is used; otherwise, the blue color is used. From the robustness diagram in Figure 11 it can be seen that the chaotic dynamics are preserved for wide intervals of the parameter valuesb andd.Figure 11
Robustness diagram to determine chaos existence forb versusd at intervals of 0.01 and with τ = 0.085:chaos (red), no chaos (blue).Furthermore, it is easy to note that if a value ofτ less than 0.085 is considered, then the chaos regions increase. Taking into account the fact that the preservation of chaos in the discretized version of the NCS proposed is robust for the parametersb andd, considering the software and hardware characteristics of the proposed ES, and the benefits of digital systems, as the elimination of the typical wear of the analog systems, it is stated that the electronical/digital implementation presented in this work is robust.On the other hand, to the best of our knowledge the electronical implementation in a portable TFTTSD device of DV of chaotic systems, for the reproduction of their nonlinear dynamics in real-time, is new. By having a graphical interface and given certain potential applications in the engineering field, such as biometric systems, telemedicine, cryptography, and secure communications, the proposed digital implementation makes the interaction between the device and the end user very friendly. One of the most relevant advantages of the NSC in DV (14) is the increase in step size compared with other chaotic systems, which allows implementation in slower microcontrollers, for example, in 8-bit low-end microcontrollers; microchip PIC microcontrollers, Motorola M68HC05 microcontrollers, AVR microcontrollers, ATmega328, and 8051 from the manufacturer Atmel. In the same way, there are alternative families of 16-bit mid-range microcontrollers to implement the NSC in DV (14), such as the dsPIC family of manufacturer microchip, MSP430 of Texas Instruments.Finally, we can find the high-end microcontrollers, which are those used in the implementation presented in this work. A microchip PIC32 microcontroller was used which shows great benefits in the use of TFTTSD; along with this microcontroller there are other alternatives such as the STM32 microcontrollers of the manufacturer STMicroelectronics or the FT900 microcontrollers of the manufacturer Future Technology Devices International Limited.


## 5. Conclusions

We have proposed a new chaotic system (NCS), which generates chaotic dynamics varying two parameters.Analytical and numerical studies to confirm the chaos generation for continuous and discretized version (DV) were presented. Also, a degradation analysis on the discretized version of the NCS was carried out to find the maximum step size. The results showed that the NCS is flexible and robust which allows obtaining different chaotic behaviors.In addition, the NCS was implemented electronically for continuous version with operational amplifiers and for DV we used a novel embedded system that shows dynamical behaviors in real-time.As future work, the authors will concentrate on carrying out a complete analysis of the proposed chaotic system, providing rigorous mathematical proofs, to estimate the ultimate bound and positively invariant set, as is reported in the current literature [11, 48–50], and, in addition, to apply these analytical results to synchronize the proposed chaotic system via approach reported in [51].



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*Source: 6820492-2017-07-26.xml*