# A Low-Power Stable Wideband Current Source for Acupuncture Point Skin Impedance Measurements

Authors: Changpei Qiu; Tianxia Zhao; Qiuping Li; Xin’an Wang; Kanglin Xiao; Bo Wang
Journal: Journal of Healthcare Engineering
 (2021)

---

## Abstract

A low-power stable wideband current source for acupuncture point skin impedance measurements has been designed employing a differential architecture and negative feedback. The circuits extend bandwidth to 1 MHz, reducing harmonic distortion to 0.24% at 1 MHz. The output impedance is 37 MΩ at 100 kHz and 11 MΩ at 1 MHz. The stability of the output current of the current source when connected to different loads is below 0.1% at frequencies up to 500 kHz and increases to 0.74% at 1 MHz. The circuit was manufactured in a 0.13-μm CMOS technology and measured results are presented. The area of the current source is 0.09 mm2 and its consumption is 1.2 mW. It is intended for low-power acupuncture point skin impedance measurements.


---

## Body

## 1. Introduction

Skin impedance measurement has been used for more than 50 years to measure changes in skin impedance at acupuncture points to help diagnose diseases and monitor the effectiveness of treatment [1, 2]. Over the years, researchers have used a wide variety of devices with many measurement modalities to measure skin electrical impedance. However, many interfering factors affect the validity of acupuncture skin impedance measurements. These factors include environmental conditions such as skin moisture, human physiological parameters, as well as the size and angle of the device used to measure skin impedance, the pressure of the measuring electrode, and the contact area with the acupuncture skin impedance [3]. The researchers point out that many of the possible sources of error in skin impedance measurements are related to the stability of skin impedance measurements. There are many methods [4, 5] for measuring skin impedance, including multichannel acquisition systems using concentric probes [6–8], as well as four-electrode and two-electrode probe methods [4, 7, 9]. However, the frequency variation of the injected skin current in these measurement methods and the variation of the system circuitry when intervening in the human skin impedance can affect the results of the skin impedance measurement. Skin impedance measurement typically uses a constant ac current source to inject current into the skin under test and then measure the voltage difference between the two sides of the skin to calculate the skin impedance. The current injection from the current source has to comply with the medical safety limits [10]. Skin impedance measurements can also be performed using an AC voltage source, where an AC voltage is injected into the skin to be measured, and the skin impedance is calculated by measuring the current signal through which it passes. This approach is used in biosensor applications [11–15]. However, voltage output biointerfaces are considered unsafe because when voltage is injected into the skin, the different skin impedances of different people cause different loads to the voltage source, and the resulting current cannot be controlled to a safe range, which can result in a higher risk of damage to different skin tissues [16].In skin impedance measurements, wideband operation is important. The ac current source must have a high accuracy bandwidth to prevent the output current of the current source from having large current errors due to variations in the cortical impedance load. The allowable injected current amplitude must comply with international safety standards [17]. As a result, the current source requires large output impedance in high-frequency broadband, and output current ensures low distortion and meets low-power requirements for acupuncture point skin impedance measurements which is limited in existing integrated current source [18–22]. For current source design studies, most have used the Howland topology circuit architecture, which is designed with discrete electronic component connections [22–25]. Current source design [24] uses a Howland topology to achieve a high output impedance (1.7 MΩ at 50 kHz) for the current source by using a resistor with a precision tolerance of 0.01%. However, in IC design, high precision resistors are difficult to guarantee. There are also current source designs that use a generalized impedance converter circuit to improve the output impedance of the current source by reducing the stray capacitance in the circuit [25]. The integrated current source proposed in [26] uses an active inductive load structure to implement an open-loop operational transduction amplifier (OTA), and its current source can reach an output impedance of 500 kΩ at 500 kHz, but the supply voltage is too high and the bandwidth is less than 1 MHz.In this paper, we propose a low-power stable wideband current source for acupuncture point skin impedance measurements. The designed circuit uses the negative feedback technology formed by differential difference transconductance amplifier and output transconductance amplifier (DDTA-OTA) cascade with the on-chip sense resistors to improve the output impedance which ensures the stability of output current. The current source operates in 1.2 V power supplies and 40μA DC bias reducing power consumption. The paper is organized in the following sections. Section 2 introduces the basic current source circuit and its linear current source architecture. Section 3 focuses on the design of ICs for current sources. In Section 4 we perform performance tests on the current source circuits. In Section 5 we measured acupuncture point skin impedance. Finally, Section 6 concludes.


## 2. Current Source Architecture

Figure1 shows the basic current source circuit. B is the voltage buffer. The low frequency transfer function of the output current is (1)IVin=Gmr0+RL+RS/r0+RSGm,where Gm is the OTA transconductance, RL is the load resistance, Rs is sense resistors, r0 is the small-signal output resistance, I is the load current, and Vin is input AC voltage signal. For r0≫RS+RL, the above expression simplifies to (2)IVin=Gm1+RSGm≈1RS.Figure 1
Basic current source circuit.The current source circuit’s output resistance is given by(3)Rout=r0+Gmr0+1RS.IfGmRS≫1, then Rout≈Gmr0Rs. Therefore, the use of negative feedback increases the output resistance of the circuit.(4)Gm=IbiasVGS−VTH,where VGS is the voltage across gate and source terminals of MOS transistor, VTH is the threshold voltage, and Ibias is the DC bias current. The overdrive voltage of the transistor under SMIC 0.13 μm CMOS technology is approximately 0.3 V. The permissible injection current amplitude must comply with international safety standards. For current frequencies less than 1 kHz where the load magnitude is 10 kΩ, the maximum allowable current flowing through the body is around 100 μA [17], and when DC bias adopts 100 μA and the sense resistor RS is 500 Ω, GmRs is far less than 1, so the effect of negative feedback increasing resistance is not produced.


### 2.1. Proposed Current Source Architecture

The current source structure consisting of preamplifier (DDTA1, DDTA2) and double-ended output transconductance amplifier (Gm1, Gm2) is shown in the block diagram of Figure 2. The AC voltage signal and the DC common-mode voltage are fed through the preamplifier to the next stage of the transimpedance amplifier to produce a stable output current. The output current is induced by the voltage across the integrated resistors and the generating voltage is fed back to the two-terminal input pair of the differential difference transconductance amplifier (DDTA1, DDTA2), thus establishing a negative feedback path.Figure 2
The current source circuit structure block diagram.In the new current source, the voltage difference across the sense resistor is generated at the preamplifier (DDTA1, DDTA2), so there is no need to use a voltage buffer. The output current is generated by two current sources receiving a 180-phase shift differential input voltage signal (Vin, −Vin). Using the differential difference transconductance amplifier (DDTA) as the input stage can eliminate the unnecessary buffer parasitic added by the need for high-frequency operation and also isolate the load from the input signal. This current source structure expands the operating bandwidth and reduces the harmonic distortion of the output current, while also improving the output impedance of the circuit.Assuming that the load is resistanceRL, the low frequency transconductance of a single current source is given by the following equation:(5)Gcurrent=ILVin=1RS+r0+RS+RL/r01/ADDTAGm,where IL is the load current, ADDTA is the small-signal voltage gain of the preamplifier, r0 is the small-signal output resistance, and Gm is the small-signal gain of the transconductor. The current source’s output resistance is given by (6)Rout=r0+ADDTAGmr0+1Rs.The use of preamplifier (DDTA) can meet the condition thatADDTAGmRS≫1 by adjusting the gain of the preamplifier. Thus, Gcurrent≈1/Rs. Hence, Gcurrent can be set according to the value of the sense resistance, independent of the internal parameters of the circuit. The circuit structure of the negative feedback loop can enhance the output resistance of the current source circuit, thus eliminating the need to design a transconductor with a large output resistance. In the structure proposed in this paper, the output resistance of the overall circuit split in half because two current sources were connected in parallel to output current.


## 2.1. Proposed Current Source Architecture

The current source structure consisting of preamplifier (DDTA1, DDTA2) and double-ended output transconductance amplifier (Gm1, Gm2) is shown in the block diagram of Figure 2. The AC voltage signal and the DC common-mode voltage are fed through the preamplifier to the next stage of the transimpedance amplifier to produce a stable output current. The output current is induced by the voltage across the integrated resistors and the generating voltage is fed back to the two-terminal input pair of the differential difference transconductance amplifier (DDTA1, DDTA2), thus establishing a negative feedback path.Figure 2
The current source circuit structure block diagram.In the new current source, the voltage difference across the sense resistor is generated at the preamplifier (DDTA1, DDTA2), so there is no need to use a voltage buffer. The output current is generated by two current sources receiving a 180-phase shift differential input voltage signal (Vin, −Vin). Using the differential difference transconductance amplifier (DDTA) as the input stage can eliminate the unnecessary buffer parasitic added by the need for high-frequency operation and also isolate the load from the input signal. This current source structure expands the operating bandwidth and reduces the harmonic distortion of the output current, while also improving the output impedance of the circuit.Assuming that the load is resistanceRL, the low frequency transconductance of a single current source is given by the following equation:(5)Gcurrent=ILVin=1RS+r0+RS+RL/r01/ADDTAGm,where IL is the load current, ADDTA is the small-signal voltage gain of the preamplifier, r0 is the small-signal output resistance, and Gm is the small-signal gain of the transconductor. The current source’s output resistance is given by (6)Rout=r0+ADDTAGmr0+1Rs.The use of preamplifier (DDTA) can meet the condition thatADDTAGmRS≫1 by adjusting the gain of the preamplifier. Thus, Gcurrent≈1/Rs. Hence, Gcurrent can be set according to the value of the sense resistance, independent of the internal parameters of the circuit. The circuit structure of the negative feedback loop can enhance the output resistance of the current source circuit, thus eliminating the need to design a transconductor with a large output resistance. In the structure proposed in this paper, the output resistance of the overall circuit split in half because two current sources were connected in parallel to output current.


## 3. Current Source Circuit Design and Analysis

### 3.1. Preamplifier (DDTA)

In order to realize the negative feedback function of the whole circuit and further improve the output resistance, we designed a preamplification stage in this paper. Figure3 shows the COMS implementation of preamplifier in which a fully differential cascade to input differential difference pair formed by M1–M4. The M1–M4 transistors, as differential pairs, are connected to the M11–M12 as load diode to form the saturated MOS symmetrical load differential amplifier stage. Current mirrors consisting of transistor pairs M15-16M13-14 form a differential output stage with transistors M19–22.Figure 3
The schematic diagram of the preamplifier stage (DDTA).Common gate transistorsM17-M18 provide active loading to the output differential pair. This circuit topology enhances the output resistance of the circuit and the gain of the differential output. The gate voltage of transistor M10 provides the DC bias for M17-18, which ensures that cascade pairs work in the saturation region. Transistors M23-M24 operate in the triode region and provide common-mode feedback (CMFB); they operate in the triode region. Cascade current mirrors formed by transistors M5–M8 provide the input bias current to the four-input differential difference pairs M1–M4. The advantage of this preamplifier topology is the ability to control the output stage of the circuit without affecting the input transconductance stage. The open-loop voltage gain of this circuit is given by (7)Aov≈GmroutV1−V2−V3−V4,where Gm is the cross conductance in the whole circuit which is the product of the cross conductance of the input transistor and the gain of the current mirror (Gm≈Bgm1).In order to provide sufficient bandwidth for the output current, we should ensure that the predominant pole frequency is large enough. Preamplifier circuit’s internal node 1,2 is the low resistance node, while only output node 3 is the high resistance node. Main pole frequencyfd is the −3 dB cut-off frequency: (8)fd=12πroutCn3+CL,where CL is the parasitic capacitance of the input differential pair transistor of the next stage, Cn3 is the parasitic capacitance of node 3, and rout is the output impedance of node 3. To ensure sufficient phase margin, the nondominant pole must have a high enough frequency. The specific nondominant poles are generated at node 1, 4 and node 2, and the signals of node 4 and node 1 have the same amplitude and opposite phase, which constitute the nondominant poles of the full-differential signal. The frequencies of the nondominant poles generated in the preamplifier circuit are given by (9)fnd1,4≈gm1,42πCn1,4=gm1,42πCgs16+Cgs15+Cgs11,(10)fnd2≈gm72πCn2=gm42πCgs20+Cgs21,where (11)Cgs=23C0xWL,where Cni is the parasitic node capacitance of ith node whereas gmi and Cgsi are transconductance gain and gate to source capacitance of ith MOSFET. Cox is the gate capacitance per unit area and W and L are the channel width and length of the devices.


### 3.2. Transconductance Stage

Figure4 is the schematic of the circuit of the transconductance stage. In order to improve the output impedance of transconductance stage, we adopted the common source common gate cascade technology and added the common gate transistor M11–M18. This circuit only has output node (Vout+/Vout−) which is high resistance node, and other nodes are low resistance nodes. Output impedance is made up of the resistance rout13 looking up from M13 and the resistance Rout17 looking down from M17 in parallel given by (12)rout=rout13//rout17,(13)rout13=rds13gm13rds8,rout17=rds17gm17rds21.Figure 4
The schematic diagram of the transconductance stage.It can be seen that the adoption of the common gate transistorM13 and M17 increases rout13 and rout17 by rds.gm times. Perform the same procedures as before while ensuring adequate PMs and a single dominant pole. The single-ended output node current is the difference between the current supplied by the PMOS and NMOS transistors. The output current can be approximated by I0≈BGmV1−V2 where B is the current mirror gain factor between M5 and M7, M10 (or M6 and M8, M9). The maximum output current amplitude allowed to be injected into the human body impedance must comply with international safety standards [17]. For AC signals injected into the human skin at a frequency of 1 kHz, the maximum allowable injection current amplitude for the human body is 100 μA, and the maximum corresponding load is 10kΩ. In other words, the output voltage compliance is about 2 V. At output current frequencies above 25 kHz, the allowable current amplitude through the body is 2.5 mA, where the load magnitude is reduced to approximately 1 kΩ. We adopted low-supply-voltage (1.2 V) specification and the low-dc bias current (40 μA), which can meet the high biological impedance load (100 kΩ) demand of human body and the maximum allowable load voltage of human body. The output voltage compliance of the OTA is (14)VSS+Vov17+Vov21<Vout<VDD−Vov8−Vov13,where VSS and VDD are negative power supply voltage and positive power supply voltages, Vov17 is the overdrive voltage of transistor M17, and Vovi is the overdrive voltage of ith MOS transistor.To ensure low saturation voltage operation of the output transistors, OTA voltage compliance is designed to be ±1.2 V. When the outputs are short-circuited, the nominal gain of transconductance stage was designed for 144μA/V and the frequency of transconductance stage at a −3 dB bandwidth is approximately 10 MHz.


## 3.1. Preamplifier (DDTA)

In order to realize the negative feedback function of the whole circuit and further improve the output resistance, we designed a preamplification stage in this paper. Figure3 shows the COMS implementation of preamplifier in which a fully differential cascade to input differential difference pair formed by M1–M4. The M1–M4 transistors, as differential pairs, are connected to the M11–M12 as load diode to form the saturated MOS symmetrical load differential amplifier stage. Current mirrors consisting of transistor pairs M15-16M13-14 form a differential output stage with transistors M19–22.Figure 3
The schematic diagram of the preamplifier stage (DDTA).Common gate transistorsM17-M18 provide active loading to the output differential pair. This circuit topology enhances the output resistance of the circuit and the gain of the differential output. The gate voltage of transistor M10 provides the DC bias for M17-18, which ensures that cascade pairs work in the saturation region. Transistors M23-M24 operate in the triode region and provide common-mode feedback (CMFB); they operate in the triode region. Cascade current mirrors formed by transistors M5–M8 provide the input bias current to the four-input differential difference pairs M1–M4. The advantage of this preamplifier topology is the ability to control the output stage of the circuit without affecting the input transconductance stage. The open-loop voltage gain of this circuit is given by (7)Aov≈GmroutV1−V2−V3−V4,where Gm is the cross conductance in the whole circuit which is the product of the cross conductance of the input transistor and the gain of the current mirror (Gm≈Bgm1).In order to provide sufficient bandwidth for the output current, we should ensure that the predominant pole frequency is large enough. Preamplifier circuit’s internal node 1,2 is the low resistance node, while only output node 3 is the high resistance node. Main pole frequencyfd is the −3 dB cut-off frequency: (8)fd=12πroutCn3+CL,where CL is the parasitic capacitance of the input differential pair transistor of the next stage, Cn3 is the parasitic capacitance of node 3, and rout is the output impedance of node 3. To ensure sufficient phase margin, the nondominant pole must have a high enough frequency. The specific nondominant poles are generated at node 1, 4 and node 2, and the signals of node 4 and node 1 have the same amplitude and opposite phase, which constitute the nondominant poles of the full-differential signal. The frequencies of the nondominant poles generated in the preamplifier circuit are given by (9)fnd1,4≈gm1,42πCn1,4=gm1,42πCgs16+Cgs15+Cgs11,(10)fnd2≈gm72πCn2=gm42πCgs20+Cgs21,where (11)Cgs=23C0xWL,where Cni is the parasitic node capacitance of ith node whereas gmi and Cgsi are transconductance gain and gate to source capacitance of ith MOSFET. Cox is the gate capacitance per unit area and W and L are the channel width and length of the devices.


## 3.2. Transconductance Stage

Figure4 is the schematic of the circuit of the transconductance stage. In order to improve the output impedance of transconductance stage, we adopted the common source common gate cascade technology and added the common gate transistor M11–M18. This circuit only has output node (Vout+/Vout−) which is high resistance node, and other nodes are low resistance nodes. Output impedance is made up of the resistance rout13 looking up from M13 and the resistance Rout17 looking down from M17 in parallel given by (12)rout=rout13//rout17,(13)rout13=rds13gm13rds8,rout17=rds17gm17rds21.Figure 4
The schematic diagram of the transconductance stage.It can be seen that the adoption of the common gate transistorM13 and M17 increases rout13 and rout17 by rds.gm times. Perform the same procedures as before while ensuring adequate PMs and a single dominant pole. The single-ended output node current is the difference between the current supplied by the PMOS and NMOS transistors. The output current can be approximated by I0≈BGmV1−V2 where B is the current mirror gain factor between M5 and M7, M10 (or M6 and M8, M9). The maximum output current amplitude allowed to be injected into the human body impedance must comply with international safety standards [17]. For AC signals injected into the human skin at a frequency of 1 kHz, the maximum allowable injection current amplitude for the human body is 100 μA, and the maximum corresponding load is 10kΩ. In other words, the output voltage compliance is about 2 V. At output current frequencies above 25 kHz, the allowable current amplitude through the body is 2.5 mA, where the load magnitude is reduced to approximately 1 kΩ. We adopted low-supply-voltage (1.2 V) specification and the low-dc bias current (40 μA), which can meet the high biological impedance load (100 kΩ) demand of human body and the maximum allowable load voltage of human body. The output voltage compliance of the OTA is (14)VSS+Vov17+Vov21<Vout<VDD−Vov8−Vov13,where VSS and VDD are negative power supply voltage and positive power supply voltages, Vov17 is the overdrive voltage of transistor M17, and Vovi is the overdrive voltage of ith MOS transistor.To ensure low saturation voltage operation of the output transistors, OTA voltage compliance is designed to be ±1.2 V. When the outputs are short-circuited, the nominal gain of transconductance stage was designed for 144μA/V and the frequency of transconductance stage at a −3 dB bandwidth is approximately 10 MHz.


## 4. Current Source Circuit Measured Results

The proposed new current source was manufactured using a SMIC 0.13μm CMOS technology and can operate under 1.2 V power supply. Current source circuit is designed by Cadence software. The microphotograph of proposed circuit is shown in Figure 5. The area of the proposed current source is 0.09 mm2 and its power consumption is 1.2 mW. The on-chip sense resistors were chosen to be 500 Ω.Figure 5
Microphotograph of proposed circuit.In order to eliminate the chance of measuring the performance of a current source circuit, five current source circuit chips were tested, each packaged on a designed pcb test circuit board. Pcb test circuit boards provide the necessary bias current and input/output signals for the current source chips. The chip was tested for the variation of the transconductance stage of the current source over the desired input AC voltage range, the accuracy of the output current of the current source in the frequency range 10 kHz to 1 MHz, and the distortion rate and output impedance of the output current of the current source chip.The THD of the current source was evaluated using an Agilent E4411 B spectrum analyzer at 1 MHz. For three different input voltage amplitudes, corresponding to 50μA, 100 μA, and 200 μA output current amplitudes, the power of the output current harmonic frequency of the current source was measured 10 times at a time to measure the THD results. The measured THD was 0.1% for 50 μA, 0.19% for 100 μA, and 0.24% for 200 μA.Figure6 shows the measurement results of the transconductance of the five current source chips. The result of transconductance of the current source was measured at a load of 10kΩ||5 pF and an input AC voltage signal operating at 1 MHz. The Agilent 33250a signal generator generates the AC voltage signal to provide the input signal to the current source. The maximum input voltage signal measured during normal operation of the chip is ±50 mV, and the maximum output current produced by the current source is 200μAp-p. The average transconductance tested for all five current source chips was 3.95 mA/V, and the standard deviation of the measured transconductance was 0.06 mA/V, where the maximum and minimum transconductance deviations were ±1.51%.Figure 6
Transconductance of current source versus.Figure7 shows the measured results of variation of transconductances of input AC voltage and the accuracy of the output current over frequency with a load of 10 kΩ//5 pF. In the frequency range 1 kHz to 5 MHz the accuracy of current source output is approximately 0.01% for 56 μA, 84 μA, 168 μA, and 200 μA. Between the 500 kHz and 1 MHz the accuracy of current source output is approximately 0.6% for 56.2 μA, 0.63% for 84 μA, 0.63% for 168 μA, and 1.1% for 200 μA. Besides, the measured result of output impedance shown in Figure 8 is at 37MΩ up to 100 kHz and 11 MΩ up to 1 MHz which ensured the stability of output current.Figure 7
Variation of transconductances.Figure 8
Output impedance with frequency.Another important purpose of the chip test is to test and study the stability of the output current of the current source circuit under different loads. Figure9 shows the measured output current of 10 μA, 50 μA, 100 μA, and 200 μA for different load impedance at 1 MHz. In the load impedance rang of 500 Ω to 10 kΩ, the stability of the maximum output current is below 0.1% at 500 kHz increasing to 0.74% at 1 MHz, respectively. The variability of output current in all five chips tested was less than 1%.Figure 9
Output current for different load impedance at 1 MHz.The proposed current source is compared with other publications, as is shown in Table1. In both bandwidth variations, the proposed current source has achieved the highest output impedance and low harmonic distortion. And the power consumption is the lowest in Table 1.Table 1
Measured performance and comparison.
ParameterThis work[27][21][26]Technology130 nm180 nm180 nm350 nmSupply1.2 V1.8 V1.5 V5 VBandwidth>1MHz100 Hz–100 kHz90 kHz10 kHz–1 MHzTHD0.24% at 1 MHz0.2% at 100 kHz1% at 90 kHz0.79%@500μAPower1.2 mW7.08mW2 mW>10mWMax.output current200μAp-p400μΑp-p350μAp-p500μΑp-pOutput impedance11 MΩ at 1 MHz100 kΩ at 100 kHz560 kΩ at 90 kHz500 kΩ at 500 kHzCurrent stability0.74% at 1 MHzNoneNoneNone


## 5. Acupuncture Point Skin Impedance Measurements

Install the current source on impedance measuring device to obtain the impedance characteristics of human meridian acupoints and nonacupoint tissue specimens. This test uses a current source chip to test the electrical impedance of the skin around the human acupuncture point PC4 Ximen and non-acupuncture point PC4 Ximen surrounding area. The test data were used to distinguish the difference in electrical impedance between the skin around PC4 and nonacupoint PC4 area. During the test, subjects were asked to sit in a chair in a resting position and was advised to rest for 5 minutes before the measurement. Before the measurement, we performed an alcohol wipe on the participant’s acupuncture point PC4 Ximen. The participant remained seated in a resting position while the measurement was obtained. Two (1.6 mm in diameter) silver electrodes used to test the skin resistance of the acupuncture points. One end of the electrodes is connected to the chip output port for receiving current from the current source chip and the other end is in contact with the measured acupuncture point.An output current of 20μApp with a variation of current in the frequency range of better than 0.3% amplitude was injected into both sides of the acupuncture points. The output current was varied from 5 Hz to 800 kHz by controlling the input voltage. The voltage values at both ends were measured and recorded. The impedance spectra of the acupuncture points and non-acupuncture points were calculated as shown in Figure 10. It could be seen that the impedance of PC4 Ximen point was obviously different from the impedance of the peripheral non-points. By comparing the data in Figure 10, it is clear that the impedance of the acupuncture points is consistently lower than that of the surrounding area points at all frequencies. This finding is consistent with the results measured at fixed frequencies in previous acupoint impedance studies [28, 29].Figure 10
Impedances of PC4 Ximen acupuncture point and nonacupoint PC4 Ximen surrounding area.


## 6. Conclusion

A low-power stable wideband current source for acupuncture point skin impedance measurements has been proposed. The circuits extend bandwidth to 1 MHz, reducing harmonic distortion to 0.24% at 1 MHz. The output impedance is 37 MΩ at 100 kHz and 11 MΩ at 1 MHz. The stability of the output current of the current source when connected to different loads is below 0.1% at frequencies up to 500 kHz and increases to 0.74% at 1 MHz. More importantly, its power consumption is 1.2 mW which is intended for acupuncture point skin impedance measurements.



---

*Source: 6650651-2021-01-06.xml*