# Efficient Topology for DC-DC Boost Converter Based on Charge Pump Capacitor for Renewable Energy System

Authors: Muhammad Zeeshan Malik; Vineet Tirth; Amjad Ali; Ajmal Farooq; Ali Algahtani; Rajesh Verma; Saiful Islam; Kashif Irshad; Ahmed N. Abdalla
Journal: International Journal of Photoenergy
 (2021)

---

## Abstract

In an attempt to meet the global demand, renewable energy systems (RES) have gained an interest in it due to the availability of the resources, especially solar photovoltaic system that has been an importance since many years because of per watt cost reduction, improvement in efficiency, and abundant availability. Photovoltaic system in remote and rural areas is very useful where a grid supply is unavailable. In this scenario, power electronic converters are an integral part of the renewable energy systems particularly for electronic devices which are operated from renewable energy sources and energy storage system (fuel cell and batteries). In this article, a new topology of charge pump capacitor (CPC) which is based on high voltage gain technique DC-DC boost converter (DCBC) with dynamic modeling is proposed. To testify the efficacy of the introduced topology, a prototype has been developed in a laboratory, where input was given 10VDC and 80VDC output voltage achieved at the load side. Furthermore, the experimental result shows that the voltage stress of MOSFET switches is very less in comparison with the conventional boost converter with the same parameters as the proposed converter.


---

## Body

## 1. Introduction

Solar photovoltaic (PV) that has a tremendous potential to generate electricity directly from the sunlight is considered as a means of powering the future with clean and environment friendly renewable sources [1–3]. However, photovoltaic panels, batteries, and fuel cell output voltage are less. To overcome this issue, DC-DC boost converter is installed to step up the low input voltage to require higher output voltage gain as depicted in Figure 1 [4]. The world surpasses in an approximation of 900 million mobile devices with over 500 million users in 2019. With higher energy demand and increasing prices of conventional electricity, it becomes a challenge for the telecommunication service providers to maintain their existing infrastructure as well as to expand it in many rural locations where access to conventional electricity is not east due to many reasons. Due to technological development in renewable energy technologies specifically solar and wind, this proved as an economical and reliable sources to power the telecom systems in remote locations where conventional grid access is unavailable or difficult to provide, as well as solar power can provide the protection to the defense communication system from any damage or cyberattack as compared to the electric grid as shown in Figure 2 [5]. Therefore, it is significant to use PV technology (off-grid, on-grid, and remote solar power station). In this scenario, a high step-up boost converter has an important part [6, 7]. In literature, many types of boost converter introduced to attain the step-up voltage at the load [8]. These converters are operated with very high duty cycle which caused to increase the converter losses; also, many circuit components occur to reduce the overall system efficiency [9]. In the high PWM signal, MOSFET switches cause the malfunction because of short conduction time [10, 11]. Compared with a classical buck, boost, and buck-boost circuits, transformer-based converters can achieve higher conversion ratios with lower losses [12, 13]. The same feature applies to converters with coupled inductors [14].Figure 1
Renewable energy system [4].Figure 2
Solar remote power station [5].The turn’s proportion of the transformer or the coupled inductors helps realize higher stepping ratios [15, 16].DC to DC boost converter with coupled inductor [17, 18] and active clamp flyback converter in [19], the main limitation of these converters is the problems related to the transformer. The massive turn’s ratio and high-voltage isolation requirements increase the leakage inductance and parasitic capacitance of the winding. At switching instants, the transformer parasitic will result in high voltage spikes across the switches [20]. The voltage and current spikes lead to increased losses and reduced reliability and may damage circuit components [21–23]. A study of some DC-DC converter is discussed in detailed [24]. It described that full-bridge converter can be more efficient. The disadvantage of this design is that the soft switchings are hard to achieve. In this converter, there is no suitable value for the snubber capacitors for the whole operation range. Furthermore, in this converter, it needs an output inductor, which can cause voltage spike at diodes. [25].Finally, DC-DC converter with transformer design is presented in the literature, and the cons of this converter including core losses in the transformer can be significantly high, and the design of winding for transformer is complicated; also, efficiency is low and price is high. Switching semiconductor devices have exacerbated this issue as higher transformer core loss at high switching frequencies make it difficult to size the transformer while simultaneously increasing power density appropriately. Additionally, the inherent mutual coupling effect between adjacent transformer windings makes these topologies less suited to multi-input or multioutput type of applications [26–28]. However, this problem can only be addressed by connecting snubber circuits to the switches or by utilizing the transformer parasitic as a resonant tank and operating these converters as resonant soft-switched converters.


## 2. Related Work

### 2.1. The Principle of Boost Converter Circuits

The popular and generally used converters are the conventional DC-DC boost converters. The fundamental thought of these conventional boost converter circuits governed by splitting the input DC voltage with a precise PWM signal to produce an anticipated voltage at the load side. The PWM signal of conventional boost converters generally kept at a constant rate. Figure3 illustrates the conventional DC-DC boost converter circuit [27]. These circuits are modest in assembly but undergo from some limits avoiding their usage in high-power applications. For the higher DC voltage conversion ratio, conventional converters work with higher duty cycle, which results in increasing the losses in the circuit components and tend to degrade the overall system efficiency [29, 30]. The higher duty cycle may also cause failure in switches due to the short conduction time [31].
(1)M=11−DVs,(2)VS−tress=V0.Figure 3
Conventional boost converter [27].In Eqs. (1), (2) where D is the duty ratio of the active switch, however, the actual conversion ratio is much lower when the effect of inductor equivalent series resistance RL, diode forward voltage drop VD, diode forward resistance Rd, switch on-state resistance Ron is accounted [28]. The effect of all these nonidealities is that the voltage gain from input to output is rarely more than 1.5 to 2.


## 2.1. The Principle of Boost Converter Circuits

The popular and generally used converters are the conventional DC-DC boost converters. The fundamental thought of these conventional boost converter circuits governed by splitting the input DC voltage with a precise PWM signal to produce an anticipated voltage at the load side. The PWM signal of conventional boost converters generally kept at a constant rate. Figure3 illustrates the conventional DC-DC boost converter circuit [27]. These circuits are modest in assembly but undergo from some limits avoiding their usage in high-power applications. For the higher DC voltage conversion ratio, conventional converters work with higher duty cycle, which results in increasing the losses in the circuit components and tend to degrade the overall system efficiency [29, 30]. The higher duty cycle may also cause failure in switches due to the short conduction time [31].
(1)M=11−DVs,(2)VS−tress=V0.Figure 3
Conventional boost converter [27].In Eqs. (1), (2) where D is the duty ratio of the active switch, however, the actual conversion ratio is much lower when the effect of inductor equivalent series resistance RL, diode forward voltage drop VD, diode forward resistance Rd, switch on-state resistance Ron is accounted [28]. The effect of all these nonidealities is that the voltage gain from input to output is rarely more than 1.5 to 2.


## 3. The Proposed Method

### 3.1. The Circuit Description

This paper presents new DC-DC boost converters based on the charge pump capacitor for high voltage gain. The feature combination of CPC-DCBC with voltage multiplier cell (CPC) does not exist in any available high voltage gain topologies of DC-DC converter. The main advantage of the introduced topology is it has the capability to achieve high voltage gain without working at higher duty ratio.The essential features of the proposed converters are proved experimentally in the laboratory with low switching losses and single stage without high-current chopping. Construction of the recommended converter is given in Figure4, where Vs. is an input voltage, four capacitors (C1, C2, C3, and C0), two MOSFET switches (S1 ad S2), inductors (L1, L2, and L3), and diodes (D1, D2, and D3). The presented topology operates in continuous conduction mode (CCM), where all components work in idle condition.Figure 4
Proposed converter.


## 3.1. The Circuit Description

This paper presents new DC-DC boost converters based on the charge pump capacitor for high voltage gain. The feature combination of CPC-DCBC with voltage multiplier cell (CPC) does not exist in any available high voltage gain topologies of DC-DC converter. The main advantage of the introduced topology is it has the capability to achieve high voltage gain without working at higher duty ratio.The essential features of the proposed converters are proved experimentally in the laboratory with low switching losses and single stage without high-current chopping. Construction of the recommended converter is given in Figure4, where Vs. is an input voltage, four capacitors (C1, C2, C3, and C0), two MOSFET switches (S1 ad S2), inductors (L1, L2, and L3), and diodes (D1, D2, and D3). The presented topology operates in continuous conduction mode (CCM), where all components work in idle condition.Figure 4
Proposed converter.


## 4. The Operating Principle

### 4.1. State I (t0-t1)

In this state, as depicted in Figure5, when switches S1 and S2 are on, diode D1 works in forward biased, and diodes D2 and D3 work in reverse biased, respectively. Inductor L1 increase by input voltage and inductor current increases linearly at the same time (Vs) established across the inductor L2 and the inductor current increases linearly, respectively. In this state, capacitors VC1 and VC2 work in series resultant capacitor voltage of VC1+VC2=2VC2 inductor L3 decrease by 2VC2−V0 and their current decrease in this state. This state is derived in Eqs. (3)-(8).
(3)V1=Vs,(4)iL1=iL1−t0+VsL1t,(5)iL2=iL2−t0+VsL2t(6)iL3=iL3−t0+2Vc2−V0L3t,(7)iQ1,2=iL1+iL2+iL3,(8)iin=iQ−iL3.Figure 5
State I.


### 4.2. State II (t1-t2)

In this state, as depicted in Figure6, when both the semiconductor switches S1 and S2 are turned off, diode D1 is reverse biased. The current across the inductor L1 discharged to the load by 2Vs−Vc2.In the same time inductor, L2 also released to load the same as inductor L1 and the voltage across inductor L3 charged to load by VC2−V0. In this state, inductors iL1 and iL2 decrease linearly and iL3 increases respectfully; this state is derived Eqs. (9)-(13).
(9)iL1=iL1−t12Vs−Vc2L1t,(10)iL2=iL2−t12Vs−Vc2L2t,(11)iL3=iL3−t1Vc2−V0L3t,(12)iQ=0,(13)iin=iL2.Figure 6
State II.


## 4.1. State I (t0-t1)

In this state, as depicted in Figure5, when switches S1 and S2 are on, diode D1 works in forward biased, and diodes D2 and D3 work in reverse biased, respectively. Inductor L1 increase by input voltage and inductor current increases linearly at the same time (Vs) established across the inductor L2 and the inductor current increases linearly, respectively. In this state, capacitors VC1 and VC2 work in series resultant capacitor voltage of VC1+VC2=2VC2 inductor L3 decrease by 2VC2−V0 and their current decrease in this state. This state is derived in Eqs. (3)-(8).
(3)V1=Vs,(4)iL1=iL1−t0+VsL1t,(5)iL2=iL2−t0+VsL2t(6)iL3=iL3−t0+2Vc2−V0L3t,(7)iQ1,2=iL1+iL2+iL3,(8)iin=iQ−iL3.Figure 5
State I.


## 4.2. State II (t1-t2)

In this state, as depicted in Figure6, when both the semiconductor switches S1 and S2 are turned off, diode D1 is reverse biased. The current across the inductor L1 discharged to the load by 2Vs−Vc2.In the same time inductor, L2 also released to load the same as inductor L1 and the voltage across inductor L3 charged to load by VC2−V0. In this state, inductors iL1 and iL2 decrease linearly and iL3 increases respectfully; this state is derived Eqs. (9)-(13).
(9)iL1=iL1−t12Vs−Vc2L1t,(10)iL2=iL2−t12Vs−Vc2L2t,(11)iL3=iL3−t1Vc2−V0L3t,(12)iQ=0,(13)iin=iL2.Figure 6
State II.


## 5. Proposed Converter Voltage Conversion Ratio

At the proposed converter inductorsL1, L2, and L3, applying volt second balance method in each state, the connection between the proposed converters is given below in Eqs. (14)-(20). Steady-state behavior of inductor voltage and their currents are depicted in above Figure 7.
(14)VL1=Vs,(15)VL2=Vs,(16)VL3=2Vc2−V0,(17)VL1=2Vs−Vc1,(18)VL2=2Vs−Vc2,(19)VL3=Vc2−V0,(20)G=V0Vs=21+D1−D.Figure 7
Steady state.Voltage stress across the MOSFET switch in Eqs. (21)-(24)
(21)VS1,2=13.2V0,(22)VD1stress=V1=−Vc1=−Vs,(23)VD2stress=V2=−Vc2=−2Vs1−D,(24)VD3stress=V3=−Vc3=−2Vs1−D.


### 5.1. Proposed Converter Power Loss Analysis

Total power loss in converter is equal to losses in each component of converter Table1.
(25)Ploss=PL1+PL2+PL3+PC1+PC2+PC3+PC0+PD1+PD2+PD3+PS1+PS2+PS′1+PS′2.(26)PL1=IL1rms2.RL1,PL2=IL2rms2.RL2,PL3=IL3rms2.RL3,PC1=IC1rms2.RC1,PC2=IC2rms2.RC2,PC3=IC3rms2.RC3,PC0=IC0rms2.RC0,PD1=ID1rms2.RD1,PD1=ID1rms2.RD1,PD2=ID2rms2.RD2,PD3=ID3rms2.RD3,PS1=Is1rms2.RDson1,PS2=Is2rms2.RDson2,PS′1=12VS1max.IS1max.fs.tr+tf,PS′2=12VS2max.IS2max.fs.tr+tf,Table 1
Power/component.
Power (W)ComponentsPL1L1PL2L2PL3L3PC1C1PC2C2PC3C3PC0C0PD1D1PD2D2PD3D3PS1S1PS2S2PS′1S1′PS′2S2′VS1max=maximumvoltagestressofS1, IS1max=maximumcurrentstressofS1, fs=switchingfrequency, tr=risetimeofMOSFETswitch, and tf=falltimeofMOSFETswitch.
(27)IL1rms=IL1avg2+∆IL1/232.Similarly, forIL2rms and IL3rms,
(28)Ic1rms=IC1max3=∆IL1/23,Ic2rms=IC3rms=∆IL2/23,Ic0rms=∆IL3/23,ID1rms=DIs−IL1,ID2rms=ID3rms=1−D.IL1,Is1rms=D.IL1,Is2rms=D.IL2.


### 5.2. DCM Analysis of Proposed Converter

Discontinuous conduction mode (DCM) occurs in switching ripples in inductor current is too large which causes reverse current to flow in the diodes. As we know, didoes can conduct in reverse current so converter goes in DCM mode.DCM mode commonly occurs in converter which has a single quadrant switch. The condition for CCM operation is that average value of conductor should be greater than half of the peak to peak ripples. Converter can go into DCM as given below.For CCM mode,(29)ILavg>∆IL2=>2ILavg>∆IL.For DCM mode,(30)ILavg<∆IL2=>2ILavg<∆IL.In between the above two conditions is the boundary B/W CCM and DCM which is given by(31)ILavg=∆IL2=>2ILavg=∆IL,In proposed converter, we have three inductors. For CCM inductors, value can be obtained for CCM mode below.(32)L1min=L2min=DVs2fsILavg,L3min=D2Vc2−V02fsIL3avg.As the energy release path from inductorL3 is discharged by switches S1 and S2, these switches are bidirectional, so there is no DCM mode in inductor L3 due to ripples in current. In simple word, ripples increase in IL3 do not cause DCM because MOSFET switches S1 and S2 conduct the reverse current. However, value of inductor L3 should be greater enough to avoid the current reversal problem.An increase of ripple current theory in inductorsL2 and L2 causes DCM mode as the freewheeling diodes D2 and D3 cannot conduct the reverse current. Hence, for DCM, there is a 3rd stage in proposed converter which D2 and D3 also of along with other switching components as shown in below Figure 8.Figure 8
D1Ts−>TsSo in DCM operation of proposed converter, there are three switching states in each switching period. State I and state II are the same as CCM mode, and state III is given below when all switches are off.(33)IL1=IL2=0,VL1=VL2=0,VL3=V3−V0−VD2.As we know,V3 = V2 and Vs = V1, so
(34)VL3=2V2−2Vs−V0.Current through inductorsL1 and L2 is given below steady state Figure 9.Figure 9
Steady state.In DCM mode, DC conversion ratio is given by(35)M=V0Vs=fD.D1=fD.ILavg.L.Ts.After applying voltage second balance law on all inductors, we get(36)V2=V3=2D1D1−DVs,M=V0Vs=2D1D+2−D1−2D1−2D1−DD1−D,D1=2L1−DDVs.Ts.


### 5.3. Dynamic Modeling for the Presented Converter

For dynamic modeling, ripples of inductor current and voltage ripples of capacitor are assume very less. The equivalent circuit of presented converter is shown below in Figure10 derived from Figure 5.Figure 10
Average equivalent circuit.Subsequently, applying circuit theory in Figure7, this derived in Eq. (37).
(37)iL1̇iL2̇iL3̇Vc1̇Vc2̇Vc3̇Vc4̇=0001−uC10000000uC2−uC300000−1C2−1C30−1−uL10000000uL2uL3000−uC40−uL2−1L3000−1C400−1L3000−1RLC4iL1iL2iL3Vc1Vc2Vc3Vc4+uL11+uL2−1L30000et.Equation (37) can be written as Eq. (38) without considering losses.
(38)ẋt=Auxt+Buet,wherext=iL1,iL2,iL3,Vc1,Vc2,Vc3,Vc4T∈R7 is the normal value of state vector, Au is a matrix in R7×7, and Bu is a vector in R7;Vs∈R=inputvoltage, whereas resistive load is RL and u is a function of switch S with the binary value, which is [0, 1]. This means that when the switch value is [0], the switch is off, and when the value is [1], the switch is on. The above equation is based on nonlinear, and matrix Au,Bu is based on control signal ofut∈R. The linearisation process method obtained the proposed converter behavior to small perturbations around an operation point. Therefore, the nominal steady-state operating system of the proposed converter can be written by setting (8),AX+BE=0 and can be written as shown in Eqs. (49)-(55).The voltage across the capacitor is(39)Vc1=Vs,(40)Vc2=21−DVs,(41)Vc3=21−DVs,(42)Vc4=21+D1−DVs,Current across the inductor is(43)iL1=Vs1−D4RL,(44)iL2=Vs1−D4RL,(45)iL3=Vs1−D2RL,whereVs=DCinputvoltage and D=dutycycleoftheswitchS, u~=small−signalperturbationstothenominaldustycycleD, and e~=tothenominalinputvoltageVs to the nominal input voltage, so we can write the relationship between voltage and duty cycle as below (46), (47).
(46)et=E+e~,(47)ut=U+u~,wheree~<<E and u~<<D, so we can also write as (48), (49).
(48)Xt=X+x~,(49)V0t=V0+v~0.After substituting Eqs. (39)-(45) and (46), (47) into Eq. (40), we can derive linear mode after assuming that the perturbations are less enough and nonlinear terms can be avoided so that we can write Eq. (50).
(50)iL1̇~iL2̇~iL3̇~Vc1̇~Vc2̇~Vc3̇~Vc4̇~=0001−uC10000000uC2−uC300000−1C2−1C30−1−uL10000000uL2uL3000−uC40−uL2−1L3000−1C400−1L3000−1RLC4iL1~iL2~iL3~Vc1~Vc2~Vc3~Vc4~+Vs21−DL2Vs21−DL2Vs21+D1−DL3VsVs1−D4RLc1Vs1−D4RLc2Vs1−D2RLc3uL11+uL2−1L30000u~e~.Equation (50) can be written as Eq. (51).
(51)ẋt=Axt+Bvt,wherext∈R7 is the state vector,A∈R7×7 and B are constant matrix inR7×2, R2 is vector of input voltage, andVt=u~e~. When the perturbation input voltage is neglected e~=0,so matrix B can be removed and written as (62).
(52)iL1̇~iL2̇~iL3̇~Vc1̇~Vc2̇~Vc3̇~Vc4̇~=0001−uC10000000uC2−uC300000−1C2−1C30−1−uL10000000uL2uL3000−uC40−uL2−1L3000−1C400−1L3000−1RLC4iL1~iL2~iL3~Vc1~Vc2~Vc3~Vc4~+Vs21−DL2Vs21−DL2Vs21+D1−DL3VsVs1−D4RLc1Vs1−D4RLc2Vs1−D2RLc3u~.


## 5.1. Proposed Converter Power Loss Analysis

Total power loss in converter is equal to losses in each component of converter Table1.
(25)Ploss=PL1+PL2+PL3+PC1+PC2+PC3+PC0+PD1+PD2+PD3+PS1+PS2+PS′1+PS′2.(26)PL1=IL1rms2.RL1,PL2=IL2rms2.RL2,PL3=IL3rms2.RL3,PC1=IC1rms2.RC1,PC2=IC2rms2.RC2,PC3=IC3rms2.RC3,PC0=IC0rms2.RC0,PD1=ID1rms2.RD1,PD1=ID1rms2.RD1,PD2=ID2rms2.RD2,PD3=ID3rms2.RD3,PS1=Is1rms2.RDson1,PS2=Is2rms2.RDson2,PS′1=12VS1max.IS1max.fs.tr+tf,PS′2=12VS2max.IS2max.fs.tr+tf,Table 1
Power/component.
Power (W)ComponentsPL1L1PL2L2PL3L3PC1C1PC2C2PC3C3PC0C0PD1D1PD2D2PD3D3PS1S1PS2S2PS′1S1′PS′2S2′VS1max=maximumvoltagestressofS1, IS1max=maximumcurrentstressofS1, fs=switchingfrequency, tr=risetimeofMOSFETswitch, and tf=falltimeofMOSFETswitch.
(27)IL1rms=IL1avg2+∆IL1/232.Similarly, forIL2rms and IL3rms,
(28)Ic1rms=IC1max3=∆IL1/23,Ic2rms=IC3rms=∆IL2/23,Ic0rms=∆IL3/23,ID1rms=DIs−IL1,ID2rms=ID3rms=1−D.IL1,Is1rms=D.IL1,Is2rms=D.IL2.


## 5.2. DCM Analysis of Proposed Converter

Discontinuous conduction mode (DCM) occurs in switching ripples in inductor current is too large which causes reverse current to flow in the diodes. As we know, didoes can conduct in reverse current so converter goes in DCM mode.DCM mode commonly occurs in converter which has a single quadrant switch. The condition for CCM operation is that average value of conductor should be greater than half of the peak to peak ripples. Converter can go into DCM as given below.For CCM mode,(29)ILavg>∆IL2=>2ILavg>∆IL.For DCM mode,(30)ILavg<∆IL2=>2ILavg<∆IL.In between the above two conditions is the boundary B/W CCM and DCM which is given by(31)ILavg=∆IL2=>2ILavg=∆IL,In proposed converter, we have three inductors. For CCM inductors, value can be obtained for CCM mode below.(32)L1min=L2min=DVs2fsILavg,L3min=D2Vc2−V02fsIL3avg.As the energy release path from inductorL3 is discharged by switches S1 and S2, these switches are bidirectional, so there is no DCM mode in inductor L3 due to ripples in current. In simple word, ripples increase in IL3 do not cause DCM because MOSFET switches S1 and S2 conduct the reverse current. However, value of inductor L3 should be greater enough to avoid the current reversal problem.An increase of ripple current theory in inductorsL2 and L2 causes DCM mode as the freewheeling diodes D2 and D3 cannot conduct the reverse current. Hence, for DCM, there is a 3rd stage in proposed converter which D2 and D3 also of along with other switching components as shown in below Figure 8.Figure 8
D1Ts−>TsSo in DCM operation of proposed converter, there are three switching states in each switching period. State I and state II are the same as CCM mode, and state III is given below when all switches are off.(33)IL1=IL2=0,VL1=VL2=0,VL3=V3−V0−VD2.As we know,V3 = V2 and Vs = V1, so
(34)VL3=2V2−2Vs−V0.Current through inductorsL1 and L2 is given below steady state Figure 9.Figure 9
Steady state.In DCM mode, DC conversion ratio is given by(35)M=V0Vs=fD.D1=fD.ILavg.L.Ts.After applying voltage second balance law on all inductors, we get(36)V2=V3=2D1D1−DVs,M=V0Vs=2D1D+2−D1−2D1−2D1−DD1−D,D1=2L1−DDVs.Ts.


## 5.3. Dynamic Modeling for the Presented Converter

For dynamic modeling, ripples of inductor current and voltage ripples of capacitor are assume very less. The equivalent circuit of presented converter is shown below in Figure10 derived from Figure 5.Figure 10
Average equivalent circuit.Subsequently, applying circuit theory in Figure7, this derived in Eq. (37).
(37)iL1̇iL2̇iL3̇Vc1̇Vc2̇Vc3̇Vc4̇=0001−uC10000000uC2−uC300000−1C2−1C30−1−uL10000000uL2uL3000−uC40−uL2−1L3000−1C400−1L3000−1RLC4iL1iL2iL3Vc1Vc2Vc3Vc4+uL11+uL2−1L30000et.Equation (37) can be written as Eq. (38) without considering losses.
(38)ẋt=Auxt+Buet,wherext=iL1,iL2,iL3,Vc1,Vc2,Vc3,Vc4T∈R7 is the normal value of state vector, Au is a matrix in R7×7, and Bu is a vector in R7;Vs∈R=inputvoltage, whereas resistive load is RL and u is a function of switch S with the binary value, which is [0, 1]. This means that when the switch value is [0], the switch is off, and when the value is [1], the switch is on. The above equation is based on nonlinear, and matrix Au,Bu is based on control signal ofut∈R. The linearisation process method obtained the proposed converter behavior to small perturbations around an operation point. Therefore, the nominal steady-state operating system of the proposed converter can be written by setting (8),AX+BE=0 and can be written as shown in Eqs. (49)-(55).The voltage across the capacitor is(39)Vc1=Vs,(40)Vc2=21−DVs,(41)Vc3=21−DVs,(42)Vc4=21+D1−DVs,Current across the inductor is(43)iL1=Vs1−D4RL,(44)iL2=Vs1−D4RL,(45)iL3=Vs1−D2RL,whereVs=DCinputvoltage and D=dutycycleoftheswitchS, u~=small−signalperturbationstothenominaldustycycleD, and e~=tothenominalinputvoltageVs to the nominal input voltage, so we can write the relationship between voltage and duty cycle as below (46), (47).
(46)et=E+e~,(47)ut=U+u~,wheree~<<E and u~<<D, so we can also write as (48), (49).
(48)Xt=X+x~,(49)V0t=V0+v~0.After substituting Eqs. (39)-(45) and (46), (47) into Eq. (40), we can derive linear mode after assuming that the perturbations are less enough and nonlinear terms can be avoided so that we can write Eq. (50).
(50)iL1̇~iL2̇~iL3̇~Vc1̇~Vc2̇~Vc3̇~Vc4̇~=0001−uC10000000uC2−uC300000−1C2−1C30−1−uL10000000uL2uL3000−uC40−uL2−1L3000−1C400−1L3000−1RLC4iL1~iL2~iL3~Vc1~Vc2~Vc3~Vc4~+Vs21−DL2Vs21−DL2Vs21+D1−DL3VsVs1−D4RLc1Vs1−D4RLc2Vs1−D2RLc3uL11+uL2−1L30000u~e~.Equation (50) can be written as Eq. (51).
(51)ẋt=Axt+Bvt,wherext∈R7 is the state vector,A∈R7×7 and B are constant matrix inR7×2, R2 is vector of input voltage, andVt=u~e~. When the perturbation input voltage is neglected e~=0,so matrix B can be removed and written as (62).
(52)iL1̇~iL2̇~iL3̇~Vc1̇~Vc2̇~Vc3̇~Vc4̇~=0001−uC10000000uC2−uC300000−1C2−1C30−1−uL10000000uL2uL3000−uC40−uL2−1L3000−1C400−1L3000−1RLC4iL1~iL2~iL3~Vc1~Vc2~Vc3~Vc4~+Vs21−DL2Vs21−DL2Vs21+D1−DL3VsVs1−D4RLc1Vs1−D4RLc2Vs1−D2RLc3u~.


## 6. Results and Discussions

### 6.1. Simulation Results and Discussion

Figures11(a) and 11(b) presented simulation results of proposed topology and conventional boost converter. These simulation results performed in Matlab Simulink at the same parameters, as shown. Figure 11(a) shows the simulation results of both the conventional boost converter and proposed CPC converter, where input voltage given to both the converters is the same 10 V, and it can be seen that the output voltage of the proposed converter is higher as compared to conventional converter, which is 80 V as compared to 25 V output voltage of conventional boost converter, which is very low. In Figure 11(b), we can see that the voltage stress of the traditional boost converter is the same as output voltage, as mentioned in Eq. (2). Still, the voltage stress of the recommended converter CPC topology is very less. From simulation results, it is very clear that the presented converter contains many pros as compared to conventional converter, such as high voltage gains and lower semiconductor switching stress, as shown in Figure 11(b). In traditional boost converter, if we give 10 V as an input voltage to achieve the output voltage according to proposed topology from the conventional boost converter, it shall be operated at higher of duty ratio, which will result in increasing the component losses connected with the circuit and will degrade the overall system efficiency. The higher duty cycle could cause failure or malfunctioning of the switches because of the short conduction time.Figure 11
Proposed converter simulation results.
(a)(b)


### 6.2. Experimental Results and Discussion

To validate the operation principle and investigate the efficacy of the recommended CPC converter topology, a lab-scale prototype was developed with the circuit parameters:VS=10 V; V0=80 V; switchingfrequency=100 kHz; L1,L2,andL3=220 μH; load=200 Ω; C1,C2,C3,andC0=440μF,840μF,840μF,and420μF, respectively, as shown in Figure 12, and proposed converter component types and cost are presented in Table 2. The experimental results of the recommended CPC converter are depicted in Figure 13, where the duty cycle of the suggested CPC topology is set at D=0.6, and it works in CCM mode. Figure 13(a) depicted switching signals of the anticipated converter, and Figure 13(b) depicted input voltage Vs. Figure 13(c) depicted where we can observe that the output voltage V0 presented converter is around 78 V, which is very close to the voltage gain equation of the recommended converter. From output voltage, it is vibrant that the recommended converter CPC topology has achieved high voltage gain without higher duty ratio.Figure 12
Experimental prototype of presented converter.Table 2
Component type and cost.
ComponentsSymbolComponent typeCost ($)Model numberInductors (L1,2,3)LPassive0.15/pieceCapacitor (C1,2,3,4)CPassive$0.20-$1/pieceResistorRPassive$14-$20/pieceMOSFET (S1,2)SActive$0.22-$0.24/pieceIRFZ46NDiodes (D1,2,3)DActive$0.21-$0.24/pieceMUR860Figure 13
Proposed converter experimental results.Figures13(d) and 13(e) show the waveform of capacitor voltage VC2 and VC3 which is 49 V, respectively, which are also very close to the capacitors of Eqs. (40), (41). Figure 13(f) depicted voltage across the capacitor VC1 which is 10 V, which is equal to the input voltage. Furthermore, Figures 13(g) and 13(h) depicted voltage stress across the MOSFET switches S1 and S2 which are 25 V of each. So, it is testified that the recommended CPC converter topology can get high voltage gain at the load side with monomer switching stress.The proposed converter efficiency vs. the traditional boost converter were observed at different load at input and output terminals in which input voltage and current and output voltage current were measured with a tool, and supported handling data by following the Eq. (53) were performed in Matlab Simulink.
(53)η=V0∗I0Vin∗Iin.The proposed converter efficiency graph is portrayed in Figure14, and it can be observed that the maximum efficiency achieved by the proposed CPC topology is 95.68% at 25 W input power and 85.98% minimum efficiency at 5 W input. Thus, it is clear that the recommended CPC topology has shown an excellent efficiency with high voltage gain. Figure 15 shows the output voltages at altered duty cycles, where it can be simply observed that at any duty cycle, recommended converter achieved high voltage at the output in response to the conventional converter. Furthermore, in Figure 16, the switching stress and output voltage across the MOSFETs of recommended CPC converter and traditional boost converter are illustrated, where we can witness that at 0.4, 0.5, and 0.6 duty ratio levels, voltage gain of the proposed converter is very high and switching stress is low as compared to traditional boost converter, and the voltage gain is equal to voltage stress across the MOSFET switch.Figure 14
Efficiency graph.Figure 15
Voltage gain graph.Figure 16
Switching stress graph.


## 6.1. Simulation Results and Discussion

Figures11(a) and 11(b) presented simulation results of proposed topology and conventional boost converter. These simulation results performed in Matlab Simulink at the same parameters, as shown. Figure 11(a) shows the simulation results of both the conventional boost converter and proposed CPC converter, where input voltage given to both the converters is the same 10 V, and it can be seen that the output voltage of the proposed converter is higher as compared to conventional converter, which is 80 V as compared to 25 V output voltage of conventional boost converter, which is very low. In Figure 11(b), we can see that the voltage stress of the traditional boost converter is the same as output voltage, as mentioned in Eq. (2). Still, the voltage stress of the recommended converter CPC topology is very less. From simulation results, it is very clear that the presented converter contains many pros as compared to conventional converter, such as high voltage gains and lower semiconductor switching stress, as shown in Figure 11(b). In traditional boost converter, if we give 10 V as an input voltage to achieve the output voltage according to proposed topology from the conventional boost converter, it shall be operated at higher of duty ratio, which will result in increasing the component losses connected with the circuit and will degrade the overall system efficiency. The higher duty cycle could cause failure or malfunctioning of the switches because of the short conduction time.Figure 11
Proposed converter simulation results.
(a)(b)


## 6.2. Experimental Results and Discussion

To validate the operation principle and investigate the efficacy of the recommended CPC converter topology, a lab-scale prototype was developed with the circuit parameters:VS=10 V; V0=80 V; switchingfrequency=100 kHz; L1,L2,andL3=220 μH; load=200 Ω; C1,C2,C3,andC0=440μF,840μF,840μF,and420μF, respectively, as shown in Figure 12, and proposed converter component types and cost are presented in Table 2. The experimental results of the recommended CPC converter are depicted in Figure 13, where the duty cycle of the suggested CPC topology is set at D=0.6, and it works in CCM mode. Figure 13(a) depicted switching signals of the anticipated converter, and Figure 13(b) depicted input voltage Vs. Figure 13(c) depicted where we can observe that the output voltage V0 presented converter is around 78 V, which is very close to the voltage gain equation of the recommended converter. From output voltage, it is vibrant that the recommended converter CPC topology has achieved high voltage gain without higher duty ratio.Figure 12
Experimental prototype of presented converter.Table 2
Component type and cost.
ComponentsSymbolComponent typeCost ($)Model numberInductors (L1,2,3)LPassive0.15/pieceCapacitor (C1,2,3,4)CPassive$0.20-$1/pieceResistorRPassive$14-$20/pieceMOSFET (S1,2)SActive$0.22-$0.24/pieceIRFZ46NDiodes (D1,2,3)DActive$0.21-$0.24/pieceMUR860Figure 13
Proposed converter experimental results.Figures13(d) and 13(e) show the waveform of capacitor voltage VC2 and VC3 which is 49 V, respectively, which are also very close to the capacitors of Eqs. (40), (41). Figure 13(f) depicted voltage across the capacitor VC1 which is 10 V, which is equal to the input voltage. Furthermore, Figures 13(g) and 13(h) depicted voltage stress across the MOSFET switches S1 and S2 which are 25 V of each. So, it is testified that the recommended CPC converter topology can get high voltage gain at the load side with monomer switching stress.The proposed converter efficiency vs. the traditional boost converter were observed at different load at input and output terminals in which input voltage and current and output voltage current were measured with a tool, and supported handling data by following the Eq. (53) were performed in Matlab Simulink.
(53)η=V0∗I0Vin∗Iin.The proposed converter efficiency graph is portrayed in Figure14, and it can be observed that the maximum efficiency achieved by the proposed CPC topology is 95.68% at 25 W input power and 85.98% minimum efficiency at 5 W input. Thus, it is clear that the recommended CPC topology has shown an excellent efficiency with high voltage gain. Figure 15 shows the output voltages at altered duty cycles, where it can be simply observed that at any duty cycle, recommended converter achieved high voltage at the output in response to the conventional converter. Furthermore, in Figure 16, the switching stress and output voltage across the MOSFETs of recommended CPC converter and traditional boost converter are illustrated, where we can witness that at 0.4, 0.5, and 0.6 duty ratio levels, voltage gain of the proposed converter is very high and switching stress is low as compared to traditional boost converter, and the voltage gain is equal to voltage stress across the MOSFET switch.Figure 14
Efficiency graph.Figure 15
Voltage gain graph.Figure 16
Switching stress graph.


## 7. Conclusions

Renewable energy systems are needed in order to meet the increasing demand of the global energy consumption, and power electronic converters are an important module in such systems. This paper presents new DC-DC boost converters based on the charge pump capacitor (CPC). The feature combination of CPC-DCBC with voltage multiplier cell attains high output voltage gain with lesser switching stress. After simulation and experimental results, it is evidenced that the CPC-DCBC proposed topology could achieve high output voltage without working at an extremely duty cycle with excellent efficiency. The presented converter topology is applicable where a grid supply is unavailable and the source appliances generally run at high current with low input voltage, whereas their output load requirement is low current with high output voltage. for example, remote telecommunication system, off-grid solar system, and defense communication system. It also has the following advantages over traditional DC-DC boost converter:(i)
It operates at a lower duty cycle, which reduces the losses linked with the components installed in circuit and improves its efficiency(ii)
Less number of components, which reduce the risk of malfunctioning across the components and can, therefore, achieve higher voltage gain with very less voltage stress(iii)
Fewer switch utilization because of low voltage stress across them, which tends to reduce the active switch cost(iv)
Smaller inductor size because of less energy volume, which reduces the cost and size of the converter



---

*Source: 6675720-2021-02-15.xml*