# Dynamic Sliding Mode Evolution PWM Controller for a Novel High-Gain Interleaved DC-DC Converter in PV System

Authors: Taizhou Bei; Ping Wang; Liu Yang; Zhe Zhou
Journal: Journal of Applied Mathematics
 (2014)

---

## Abstract

Considering the disadvantages of the traditional high-gain DC-DC converter such as big size, high voltage stress of switches, and large input current ripple, a novel high-gain interleaved boost converter with coupled-inductor and switched-capacitor was proposed correspondingly and the operation principle together with the steady-state analysis of this converter was also described. Besides, a new control approach-dynamic sliding mode evolution PWM controller (DSME PWM) for the novel topological converter based on both dynamic evolution and sliding mode control was also presented. From the simulation results and experimental validation the proposed converter can fulfill high-gain boost, low ripple of both the input current and the output voltage. Furthermore, MPPT technique can be also achieved in a short time by simulation. The efficiency and stability of the converter proposed in this paper can be improved.


---

## Body

## 1. Introduction

Photovoltaic (PV) generation has an increasing influence on alleviating the energy crisis and reducing the environmental pollution. Researchers around the world have devoted themselves to the performance of PV system such as stability, efficiency, and the cost as a consequence (as discussed by [1–3]). Generally, the outputting voltage of the PV arrays ranges from 30 V to 60 V. High-gain and high-efficiency DC-DC converters are required to boost the low PV voltage to a high voltage, such as 380 V for the full-bridge inverter or 760 V for the half-bridge inverter in the 220 V AC grid-connected power system.The good performances of any high-gain DC-DC converter in PV system greatly depend on the employed topology and the corresponding control strategy. So when designing this kind of converters, one should pay more attention to these two aspects and ensure that the designed converter can minimize the current ripple and reduce the numbers of the electrolytic capacitors, which can reduce the circuit cost and easily achieve MPPT algorithms (as discussed by [4, 5]). Besides, power losses that existed in the converters in high-output-voltage applications should be decreased to improve system efficiency (as discussed by [6]). This paper will devote itself to a novel scheme that can meet the requirement above.The traditional boost converters can achieve any high-gain transform by adjusting the duty cycle theoretically; however the actual voltage gain is often limited by the parasitic parameters of inductances, capacitances, and switch devices (as discussed by [7]). Furthermore, in high-gain applications, as the duty cycle increases, the input current ripple, voltage or current stress of the devices, and the switching loss are all increasing as well as the diodes’ reverse recovery loss, decreasing the efficiency of the converters. Meanwhile electromagnetic interference (EMI) is further severe due to the excess of dv/dt. Boost converter can enhance its voltage gain via adding coupled inductances (as discussed by [8–10]). However, voltage spike will occur when turning off the switches due to the leakage inductances, which can result in voltage stress increasing, efficiency lowering, and severe EMI. The aforementioned problems can be relieved by active or passive clamping methods. Undoubtedly, it will make the main circuit, control strategy and drive mode more complicated (as discussed by [11, 12]). Another way to improve the voltage gain of conversion is to employ nonisolated cascade boost converters (as discussed by [13]). However there are many disadvantages, such as low reliability, high costs, and complexity of main circuit as well as control strategy and drive methods; besides, the outputting diodes’ reverse recovery problem is still serious in high-gain applications. Isolated boost converters can also achieve high-gain transform by designing the ratio of transformers (as discussed by [12, 14]), but the leakage inductances will cause many problems such as voltage overshoot of switches, big voltage stress, and EMI problems. Meanwhile the loss of transformers will result in lower efficiency, higher costs, and complexity of main circuit, control strategy, drive methods, and isolation design. The topology-combining boost converters and fly-back converters can be employed in the high-step-up transform (as discussed by [15, 16]), whose topology and control method are fairly simple; however the voltage balance of the capacitors exists in this system due to series connection.The reverse-recovery loss of the output diode is one of the main reasons why the efficiency is limited in the high step-up applications. When the boost converter works on discontinuous current mode (DCM) or critical current mode (CRM), the reverse-recovery loss can be reduced, but it will increase both current stress and input current ripple. Therefore it is not suitable for the high-power applications due to the bulky filter circuit.Interleaved boost converters can not only develop both power level and power density but also average the thermal stress distribution and reduce the input current ripple (as discussed by [17–19]), which can even be eliminated when the duty cycle is equal to 0.5 theoretically. However, there are some weaknesses to apply interleaved boost converter into PV grid-connected system directly (as discussed by [7, 18]). The step-up ratio is not increased efficiently comparing with the traditional single-stage boost converter, as well as the voltage stress of switches. Besides, it is very sensitive for ordinary interleaved boost converters to mismatch the duty cycle.In allusion to all the problems mentioned above, a novel high-gain interleaved converter with coupled inductance and switched capacitor (hereinafter referred to as the new converter) is proposed. High-gain transform can be realized by designing the main circuit parameters reasonably. Furthermore, the topology as well as its control method is relatively simple. Compared with conventional interleaved boost converters, the new one can boost voltage on the great scale, while reducing the voltage stress of the switch devices significantly under the same duty cycle. Moreover, the volume of magnetic elements and the current ripple of the inductance can be reduced by introducing coupled inductance (as discussed by [8, 9, 14]).Control strategy of the proposed converter can easily achieve the MPPT algorithms and minimize the current ripple to reduce the coupled inductance losses and to improve system efficiency and stability. Moreover, less computation should also be under the consideration to ease the computational complexity. It is worth noting that, in the literature, some examples of high-gain DC-DC converters are presented, but they only concern the topologies, while few papers are devoted to the controller design for such kind of converter, although not referring to PV applications.Sliding mode control (SMC) has a high robustness against plant uncertainty and external disturbances, including those due to the environmental conditions in PV applications. Many SM-based MPPT algorithms operated in different applications or different topologies have been proposed in published papers, but most of those mainly focus on the SMC used in conventional boost converter. Nevertheless, such an approach has never been used in analyzing a class of interleaved boost converters for PV applications controlled by the SM-MPPT technique.The controller of the proposed new converter is required to extract the maximum energy from the PV panels and output the stable expectant voltage without errors. Dynamic evolution control (DEC) as a new control technique has been utilized in power electronics converters (not in PV applications). DEC can ensure that the error state goes to zero in increase of time, thereby improving the dynamic characteristic of system.A new control approach based on both SM-MPPT and DEC is proposed in this paper. Since the outputting voltage and current of PV cell together with the outputting voltage of converter are involved in calculation of duty cycle, all the variation above can be compensated in the dynamic evolution.This paper is organized as follows. Section2 describes the characteristic of PV cells. Section 3 gives the working principle and performance analysis of the new converter. Section 4 is devoted to the controller design on basis of SM-MPPT and DEC. Sections 5 and 6 afford the simulation results and experimental validation, respectively. In the conclusion, the main results are finally summarized.


## 2. Characteristic of PV Cells

Formulas of the outputting current and power for the PV cells can be seen from (1) (as discussed by [3]) and Figure 1 shows the output characteristics of PV cells:
(1)ipv=Iph-Isat⁡[exp⁡(qVpvAKT)-1],Ppv=VpvIph-VpvIsat⁡[exp⁡(qVpvAKT)-1],
where ipv, Vpv are the outputting current and voltage of PV cells, Iph is the photocurrent of a single solar module, Isat⁡ is the reverse saturation current, K is Boltzmann constant, q is electric charge, T is operating temperature, and A is P-N junction ideal factor.The output characteristics of PV cells.
(a)
V-P curve when temp. = 25°C, different irradiance
(b)
V-P curve when irradiance = 1 kW/m2, different temp.When the output of the equivalent circuit of PV cells is shorted, if neglecting the reverse leakage current of the diodes, we can make an approximation thatIph≈Isc (Isc is the short-cut current), which will be used in part V for analyzing the inputting current in dynamic mode.


## 3. Principle and Steady-State Analysis

### 3.1. Principle of the New Converter

The new converter with PV panels is shown in Figure2. Capacitors C1, C2 and diode VD1 are employed to further enlarge the boost voltage under the same duty cycle compared with any other topology.Figure 2
The new converter.The inductancesL1 and L2 are closely coupled and with the same winding orientation. The coupled inductances can be represented as a mutual inductance M, two equivalent leakage inductances L1′ and L2′. The equivalent circuit is shown in Figure 3.Figure 3
Equivalent circuit of the new converter.The relationships of the inductances are related by the following equations:(2)L1′=L1-M,L2′=L2-M,M=kL1L2,
where k is coupled coefficient.In order to simplify the circuit analysis of the proposed converter, several necessary assumptions should be made as follows.(1)
All components including power switches, magnetic components, and diodes are ideal; the on-state resistanceRDS(ON) and all parasitic capacitances of the switches are neglected, as are the forward voltage drops of diodes VD1~VD3.(2)
The ESR of capacitorsC0~C2 and the parasitic resistance of coupled inductances are neglected.(3)
L1=L2=L.(4)
S1 and S2 work by turn and both are driven by PWM signals.Referring to the equivalent circuits for four different switching states of a switching period shown in Figure4 and the waveforms in Figure 5, the operation of the converter can be explained as follows.Operation states and current paths of the converter.
(a)
Mode 1:S1-on; S2-off; VD1-off; VD2-on; VD3-on
(b)
Mode 2:S1-on; S2-off; VD1-off; VD2-off; VD3-off
(c)
Mode 3:S1-off; S2-on; VD1-on; VD2-off; VD3-on
(d)
Mode 4:S1-off; S2-on; VD1-off; VD2-off; VD3-offFigure 5
Main waveforms of the new converter.Mode 1 (Figure 4(a)). At time t0, S1 is on while S2 is off; the current in the inductance L1′ starts to rise linearly while L2′ continues to discharge (the current in L2′ was acquired in the last switching period). Capacitor C2 discharges, leading to its voltage falling. But the voltage of capacitor C1 rises because C1 is charged; besides, capacitor C0 is charged by input voltage and inductor in this mode. The rates of change of iL1 and iL2 are approximately given by
(3)diL1dt=Vo-vC1L1′,diL2dt=-Vo-vC2L2′.Mode 2 (Figure 4(b)). At time t1, iL2 falls to zero. iL1 continues to rise linearly. R is charged by capacitor C0. The rate of change of iL1 is
(4)diL1dt=VpvL1,
where L1=L1′+M.Mode 3 (Figure 4(c)). At time t2, S1 is off while S2 is on. iL2 starts to rise linearly from zero and L1 starts to discharge. Besides, C1 discharges too while C2 starts to charge. Moreover, C0 is charged by input voltage and inductor. The rates of change of iL1 and iL2 are approximately given by
(5)diL1dt=-Vo-vC1L1′,(6)diL2dt=Vo-vC2L2′,(7)vC1+vC2=Vo.Mode 4 (Figure 4(d)). At time t3, S1 is off while S2 is on, iL1 falls to zero. iL2 continues to rise linearly. R is charged by capacitor C0. The rate of change of iL2 is
(8)diL2dt=VpvL2,
where L2=L2′+M.The switching period will be repeated whenS1 is on again at time t4.


### 3.2. Steady-State Analysis

Assume that the current waveforms shown in Figure5 have reached a steady state. From the waveform iL1 as shown in Figure 5, it can be found that
(9)Vo-vC1L1′α11T+VpvL1(α1-α11)T=Vo-vC1L1′(α2-α21)T.
From the waveform iL2 as shown in Figure 5, it can be found that:
(10)Vo-vC2L2′(α2-α21)T+VpvL2α21T=Vo-vC2L2′α11T.
Also from Figure 5, the average values of iL1 and iL2, denoted as I1 and I2, respectively, are found as
(11)I1=1T{12Vo-vC1L1′·(α11T)2+12Vo-vC1L1′·[(α2-α21)T]2+12(α1-α11)T·[2(Vo-vC1)L1′·α11T+VpvL1(α1-α11)T]},I2=1T{12Vo-vC2L2′·(α11T)2+12Vo-vC2L2′·[(α2-α21)T]2+12α21T·[2(Vo-vC2)L2′·(α2-α21)T+VpvL2α21T]}.
Assume that the converter is lossless; that is, the input power Pi is equal to the output power Po. Consider
(12)Vpv(I1+I2)=Vo2R,
where R is the load resistance.In principle, (7) and (9)–(12) can be solved to find Vo. However, to simplify the calculation, it is assumed that α1=α, α2=1-α, L1=L2=L, and L1′=L2′=(1-k)L. According to some algebraic manipulations and solving a quadratic equation derived from (12), the approximate values of VC1,VC2, and Vo can be referred as follows:
(13)VC1=31-αVpv=34Vo,VC2=11-αVpv=14Vo,(14)Vo=41-αVpv.
The effect of R on the calculation is very little; thus it is neglected when getting the approximate values, as shown in (13) and (14).A careful study of the waveforms shown in Figure5 will reveal the following interesting facts.(1)
As far as the input currentiin is concerned, the converter appears to operate in CCM (because iin is continuous). Thus, the peak current stress of the inductances and the input current ripple can be maintained relatively low.(2)
However, sinceiL1 and iL2 are discontinuous, the new converter is actually operating in DCM. Also, since the rectifier diodes VD1~VD3 turn off before S1/S2 turns on, the reverse-recovery loss of the rectifiers is eliminated.(3)
Besides, the current of inductanceiL1/iL2 has fallen to zero before S1/S2 turns on. ZCS soft switching operation during the whole switching transition is achieved.Furthermore, when considering the parasitic resistances of switches and capacitances (rs and rc), the switching loss due to capacitances in the course of charging can be defined as (15) in an independent converter which contains n capacitances:
(15)Ws=nC2·1+e-αT/τ1-e-αT/τ(ΔVo)2,
where C is the value of capacitances and τ=(rs+rc)C.From (15), Ws do exist even under the ideal conditions, mainly depending on ΔVo. Thus, in order to reduce Ws, the difference between the maximum and the minimum of voltage in the course of charging for all capacitances should be decreased.


## 3.1. Principle of the New Converter

The new converter with PV panels is shown in Figure2. Capacitors C1, C2 and diode VD1 are employed to further enlarge the boost voltage under the same duty cycle compared with any other topology.Figure 2
The new converter.The inductancesL1 and L2 are closely coupled and with the same winding orientation. The coupled inductances can be represented as a mutual inductance M, two equivalent leakage inductances L1′ and L2′. The equivalent circuit is shown in Figure 3.Figure 3
Equivalent circuit of the new converter.The relationships of the inductances are related by the following equations:(2)L1′=L1-M,L2′=L2-M,M=kL1L2,
where k is coupled coefficient.In order to simplify the circuit analysis of the proposed converter, several necessary assumptions should be made as follows.(1)
All components including power switches, magnetic components, and diodes are ideal; the on-state resistanceRDS(ON) and all parasitic capacitances of the switches are neglected, as are the forward voltage drops of diodes VD1~VD3.(2)
The ESR of capacitorsC0~C2 and the parasitic resistance of coupled inductances are neglected.(3)
L1=L2=L.(4)
S1 and S2 work by turn and both are driven by PWM signals.Referring to the equivalent circuits for four different switching states of a switching period shown in Figure4 and the waveforms in Figure 5, the operation of the converter can be explained as follows.Operation states and current paths of the converter.
(a)
Mode 1:S1-on; S2-off; VD1-off; VD2-on; VD3-on
(b)
Mode 2:S1-on; S2-off; VD1-off; VD2-off; VD3-off
(c)
Mode 3:S1-off; S2-on; VD1-on; VD2-off; VD3-on
(d)
Mode 4:S1-off; S2-on; VD1-off; VD2-off; VD3-offFigure 5
Main waveforms of the new converter.Mode 1 (Figure 4(a)). At time t0, S1 is on while S2 is off; the current in the inductance L1′ starts to rise linearly while L2′ continues to discharge (the current in L2′ was acquired in the last switching period). Capacitor C2 discharges, leading to its voltage falling. But the voltage of capacitor C1 rises because C1 is charged; besides, capacitor C0 is charged by input voltage and inductor in this mode. The rates of change of iL1 and iL2 are approximately given by
(3)diL1dt=Vo-vC1L1′,diL2dt=-Vo-vC2L2′.Mode 2 (Figure 4(b)). At time t1, iL2 falls to zero. iL1 continues to rise linearly. R is charged by capacitor C0. The rate of change of iL1 is
(4)diL1dt=VpvL1,
where L1=L1′+M.Mode 3 (Figure 4(c)). At time t2, S1 is off while S2 is on. iL2 starts to rise linearly from zero and L1 starts to discharge. Besides, C1 discharges too while C2 starts to charge. Moreover, C0 is charged by input voltage and inductor. The rates of change of iL1 and iL2 are approximately given by
(5)diL1dt=-Vo-vC1L1′,(6)diL2dt=Vo-vC2L2′,(7)vC1+vC2=Vo.Mode 4 (Figure 4(d)). At time t3, S1 is off while S2 is on, iL1 falls to zero. iL2 continues to rise linearly. R is charged by capacitor C0. The rate of change of iL2 is
(8)diL2dt=VpvL2,
where L2=L2′+M.The switching period will be repeated whenS1 is on again at time t4.


## 3.2. Steady-State Analysis

Assume that the current waveforms shown in Figure5 have reached a steady state. From the waveform iL1 as shown in Figure 5, it can be found that
(9)Vo-vC1L1′α11T+VpvL1(α1-α11)T=Vo-vC1L1′(α2-α21)T.
From the waveform iL2 as shown in Figure 5, it can be found that:
(10)Vo-vC2L2′(α2-α21)T+VpvL2α21T=Vo-vC2L2′α11T.
Also from Figure 5, the average values of iL1 and iL2, denoted as I1 and I2, respectively, are found as
(11)I1=1T{12Vo-vC1L1′·(α11T)2+12Vo-vC1L1′·[(α2-α21)T]2+12(α1-α11)T·[2(Vo-vC1)L1′·α11T+VpvL1(α1-α11)T]},I2=1T{12Vo-vC2L2′·(α11T)2+12Vo-vC2L2′·[(α2-α21)T]2+12α21T·[2(Vo-vC2)L2′·(α2-α21)T+VpvL2α21T]}.
Assume that the converter is lossless; that is, the input power Pi is equal to the output power Po. Consider
(12)Vpv(I1+I2)=Vo2R,
where R is the load resistance.In principle, (7) and (9)–(12) can be solved to find Vo. However, to simplify the calculation, it is assumed that α1=α, α2=1-α, L1=L2=L, and L1′=L2′=(1-k)L. According to some algebraic manipulations and solving a quadratic equation derived from (12), the approximate values of VC1,VC2, and Vo can be referred as follows:
(13)VC1=31-αVpv=34Vo,VC2=11-αVpv=14Vo,(14)Vo=41-αVpv.
The effect of R on the calculation is very little; thus it is neglected when getting the approximate values, as shown in (13) and (14).A careful study of the waveforms shown in Figure5 will reveal the following interesting facts.(1)
As far as the input currentiin is concerned, the converter appears to operate in CCM (because iin is continuous). Thus, the peak current stress of the inductances and the input current ripple can be maintained relatively low.(2)
However, sinceiL1 and iL2 are discontinuous, the new converter is actually operating in DCM. Also, since the rectifier diodes VD1~VD3 turn off before S1/S2 turns on, the reverse-recovery loss of the rectifiers is eliminated.(3)
Besides, the current of inductanceiL1/iL2 has fallen to zero before S1/S2 turns on. ZCS soft switching operation during the whole switching transition is achieved.Furthermore, when considering the parasitic resistances of switches and capacitances (rs and rc), the switching loss due to capacitances in the course of charging can be defined as (15) in an independent converter which contains n capacitances:
(15)Ws=nC2·1+e-αT/τ1-e-αT/τ(ΔVo)2,
where C is the value of capacitances and τ=(rs+rc)C.From (15), Ws do exist even under the ideal conditions, mainly depending on ΔVo. Thus, in order to reduce Ws, the difference between the maximum and the minimum of voltage in the course of charging for all capacitances should be decreased.


## 4. DSME PWM Controller

The original intention of the DSME control is to achieve MPPT as well as high-gain boost, also to reduce the error state by forcing the error state to follow the specific path, which ensures the error state goes to zero in increase of time (as discussed by [19, 20]). The control flow chart of dynamic sliding mode evolution PWM Controller can be seen in Figure 6.Figure 6
The control flow chart of DSME PWM controller.The modulating signal of PWM generationVm1 is produced by the formula δ, combing the sliding mode theory with the dynamic evolution algorithm. The specific design process of the DSME controller can be described as follows.


### 4.1. MPPT by Sliding Mode Control

When the PV cells run at the point of maximum power(16)dPpvdVpv=ipv+VpvdipvdVpv=0.
In SMC, the state space is divided into s>0 and s<0 by sliding manifold (s=0). The movement on s=0 can be called sliding mode dynamics. Considering dPpv/dVpv=0, the sliding manifold can be chosen as (as discussed by [21, 22])
(17)s=dPpvdVpv=ipv+VpvdipvdVpv.
Reconsidering the mathematical model of PV cell,
(18)ipv=Iph-Isat⁡[exp⁡(qVpvAKT)-1].
Directly substituting ipv from (18) into (17),
(19)s=dPpvdVpv=ipv+VpvdipvdVpv=-Isat⁡[exp⁡(qAKTVpv)·qAKTVpv]+Iph-Isat⁡[exp⁡(qAKTVpv)-1]=-Isat⁡(qAKTVpv+1)·exp⁡(qAKTVpv)+(Iph+Isat⁡).
The differential form of s is
(20)s˙=-Isat⁡qAKT·dVpvdtexp⁡(qAKT)-Isat⁡(qVpvAKT+1)·exp⁡(qVpvAKT)qAKTdVpvdt=-Isat⁡qAKT·dVpvdtexp⁡(qVpvAKT)(qVpvAKT+2).
According to ss˙<0, if s>0, then s˙<0, dVpv/dt>0, Vpv will increase when s tends to sliding manifold, and if s<0, then s˙>0, dVpv/dt<0, Vpv will decrease when s tends to sliding manifold. The dynamic accommodation of Vpv can be seen in Figure 7.Figure 7
The dynamic accommodation ofVpv.Considering that the new converter is composed of two paralleled boost converters, the purpose of the additional switched capacitor and coupled inductance is to increase the voltage gain. Thus, the drive signals for the switches can be designed, respectively. From the state space model of the single boost converter, when the switch is on,Vpv increases and when the switch is off, Vpv decreases (as discussed by [23]).Rearranging (17),
(21)s=dPpvdVpv=ipv+VpvdipvdVpv=Vpv(ipvVpv+dipvdVpv).
The differential form approximates to
(22)ΔipvΔVpv≈dipvdVpv.
Thus,
(23)s=Vpv(ipvVpv+ΔipvΔVpv).
Theoretically, in the case of low requirement, both (17) and (24) can be chosen as the sliding surface:
(24)s=ΔVpv·ipv+Δipv·Vpv.
The corresponding control law is
(25)u=12[1+sign⁡(ΔVpv·ipv+Δipv·Vpv)].


### 4.2. Evolution Path Selection

The principle of determining the evolution path is to ensure that the error state can go to zero at any increase of time (as discussed by [24, 25]). In this research, the evolution path is an exponential function as shown in Figure 8.Figure 8
Exponential evolution path.With this exponential evolution path, the value of the dynamic characteristic of the converter will decrease exponentially to zero by(26)H=H0l-λt,
where H is the dynamic characteristic of system, H0 is the initial value of H, and λ is a dynamic evolution factor. The derivative of H is
(27)dHdt=-λH0l-λt=-λH,dHdt+λH=0.


### 4.3. Analysis of Duty Cycle

In order to synthesize the control law of the dynamic evolution controller, the dynamic equation of converter system has to be established and analyzed. On basis of the state space average model, when the converter works on DCM, the voltage and current dynamics of the converter are given by(28)Vpv=Ldiindt+Vo4(1-α),
where L is the inductance, Vpv is the input voltage, iin is the input current, Vo is the output voltage, and α is the duty cycle, respectively.i
in
≈
i
pv, rearranging (28), the output voltage of converter can be written as
(29)Vpv=Ldipvdt+Vo4(1-α),(30)Vo=4Vpv+αVo-4Ldipvdt.
Define a linear voltage error function as shown below
(31)E=kev=k(Vref-Vo),
where k>0.Substituting (27) into (31), yields
(32)kdevdt+λkev=0.
Combining (31) with (32)
(33)kdevdt+(λk-1)ev+Vref=Vo.
Directly substituting the converter output voltage Vo from (30) into (33)
(34)kdevdt+(λk-1)ev+Vref=4Vpv+αVo-4Ldipvdt.
The obtained duty cycle formula is given by
(35)α=Vref-4VpvVo+(λk-1)evVo+kVodevdt+4LVodipvdt.
Formula (35) forces the state error function E to satisfy the dynamic evolution function (27). Consequently, the state error function E is forced to make evolution by following equation (35) and decrease to zero (E=0) with a decrease rate λ. The outputting voltage of converter converges to the converters steady state:
(36)Vo=Vref.From the synthesis procedure, it is clear that the dynamic evolution controller works on the full nonlinear system and does not need any linearization or simplification on the system model at all and it is interesting to note that the control law in (35) consists of four distinct parts. The first part is the feed-forward term which is calculated based on the duty cycle at the previous sampling instant. This term compensates for variations in the input voltages. The second and third terms consist of proportional and derivative terms of the perturbations in the output voltage, respectively. The last term consists of the derivative terms of the inductance current. Since the inputting and outputting voltages and inductance current are involved in calculation of duty cycle, it can compensate all the variation of them in the dynamic evolution.It should be noted that bothVpv and ipv are not the voltage and current at the MPP in (35). Consequently, we expect that the controller can achieve MPPT and high-gain boost; thus considering the logic relationship of control signals, the final control law can be described as follows combing (25) with (35):
(37)δ=12[1+sign⁡(ΔVpv·ipv+Δipv·Vpv)]·(Vref-4VpvVo+(λk-1)evVo+kVodevdt+4LVodipvdt).


### 4.4. PWM Generation

The PWM signals are generated by comparing a control signal with a constant peak repetitive triangle signal (Vcs). The frequency of the repetitive triangle signal establishes the constant switching frequency.Figure9 shows the PWM signals generation technique. PWM1 is produced when the control signal Vm1 is greater than Vcs while PWM2 is produced when Vm1 is less than Vcs.Figure 9
PWM generator.The values of the desired duty cycleα can be gotten from (37). PWM signals are generated by (39):
(38)Vm1=δ,(39)PWM1={1Vm1>Vcs0Vm1<Vcs,PWM2={1Vm1<Vcs0Vm1>Vcs.


## 4.1. MPPT by Sliding Mode Control

When the PV cells run at the point of maximum power(16)dPpvdVpv=ipv+VpvdipvdVpv=0.
In SMC, the state space is divided into s>0 and s<0 by sliding manifold (s=0). The movement on s=0 can be called sliding mode dynamics. Considering dPpv/dVpv=0, the sliding manifold can be chosen as (as discussed by [21, 22])
(17)s=dPpvdVpv=ipv+VpvdipvdVpv.
Reconsidering the mathematical model of PV cell,
(18)ipv=Iph-Isat⁡[exp⁡(qVpvAKT)-1].
Directly substituting ipv from (18) into (17),
(19)s=dPpvdVpv=ipv+VpvdipvdVpv=-Isat⁡[exp⁡(qAKTVpv)·qAKTVpv]+Iph-Isat⁡[exp⁡(qAKTVpv)-1]=-Isat⁡(qAKTVpv+1)·exp⁡(qAKTVpv)+(Iph+Isat⁡).
The differential form of s is
(20)s˙=-Isat⁡qAKT·dVpvdtexp⁡(qAKT)-Isat⁡(qVpvAKT+1)·exp⁡(qVpvAKT)qAKTdVpvdt=-Isat⁡qAKT·dVpvdtexp⁡(qVpvAKT)(qVpvAKT+2).
According to ss˙<0, if s>0, then s˙<0, dVpv/dt>0, Vpv will increase when s tends to sliding manifold, and if s<0, then s˙>0, dVpv/dt<0, Vpv will decrease when s tends to sliding manifold. The dynamic accommodation of Vpv can be seen in Figure 7.Figure 7
The dynamic accommodation ofVpv.Considering that the new converter is composed of two paralleled boost converters, the purpose of the additional switched capacitor and coupled inductance is to increase the voltage gain. Thus, the drive signals for the switches can be designed, respectively. From the state space model of the single boost converter, when the switch is on,Vpv increases and when the switch is off, Vpv decreases (as discussed by [23]).Rearranging (17),
(21)s=dPpvdVpv=ipv+VpvdipvdVpv=Vpv(ipvVpv+dipvdVpv).
The differential form approximates to
(22)ΔipvΔVpv≈dipvdVpv.
Thus,
(23)s=Vpv(ipvVpv+ΔipvΔVpv).
Theoretically, in the case of low requirement, both (17) and (24) can be chosen as the sliding surface:
(24)s=ΔVpv·ipv+Δipv·Vpv.
The corresponding control law is
(25)u=12[1+sign⁡(ΔVpv·ipv+Δipv·Vpv)].


## 4.2. Evolution Path Selection

The principle of determining the evolution path is to ensure that the error state can go to zero at any increase of time (as discussed by [24, 25]). In this research, the evolution path is an exponential function as shown in Figure 8.Figure 8
Exponential evolution path.With this exponential evolution path, the value of the dynamic characteristic of the converter will decrease exponentially to zero by(26)H=H0l-λt,
where H is the dynamic characteristic of system, H0 is the initial value of H, and λ is a dynamic evolution factor. The derivative of H is
(27)dHdt=-λH0l-λt=-λH,dHdt+λH=0.


## 4.3. Analysis of Duty Cycle

In order to synthesize the control law of the dynamic evolution controller, the dynamic equation of converter system has to be established and analyzed. On basis of the state space average model, when the converter works on DCM, the voltage and current dynamics of the converter are given by(28)Vpv=Ldiindt+Vo4(1-α),
where L is the inductance, Vpv is the input voltage, iin is the input current, Vo is the output voltage, and α is the duty cycle, respectively.i
in
≈
i
pv, rearranging (28), the output voltage of converter can be written as
(29)Vpv=Ldipvdt+Vo4(1-α),(30)Vo=4Vpv+αVo-4Ldipvdt.
Define a linear voltage error function as shown below
(31)E=kev=k(Vref-Vo),
where k>0.Substituting (27) into (31), yields
(32)kdevdt+λkev=0.
Combining (31) with (32)
(33)kdevdt+(λk-1)ev+Vref=Vo.
Directly substituting the converter output voltage Vo from (30) into (33)
(34)kdevdt+(λk-1)ev+Vref=4Vpv+αVo-4Ldipvdt.
The obtained duty cycle formula is given by
(35)α=Vref-4VpvVo+(λk-1)evVo+kVodevdt+4LVodipvdt.
Formula (35) forces the state error function E to satisfy the dynamic evolution function (27). Consequently, the state error function E is forced to make evolution by following equation (35) and decrease to zero (E=0) with a decrease rate λ. The outputting voltage of converter converges to the converters steady state:
(36)Vo=Vref.From the synthesis procedure, it is clear that the dynamic evolution controller works on the full nonlinear system and does not need any linearization or simplification on the system model at all and it is interesting to note that the control law in (35) consists of four distinct parts. The first part is the feed-forward term which is calculated based on the duty cycle at the previous sampling instant. This term compensates for variations in the input voltages. The second and third terms consist of proportional and derivative terms of the perturbations in the output voltage, respectively. The last term consists of the derivative terms of the inductance current. Since the inputting and outputting voltages and inductance current are involved in calculation of duty cycle, it can compensate all the variation of them in the dynamic evolution.It should be noted that bothVpv and ipv are not the voltage and current at the MPP in (35). Consequently, we expect that the controller can achieve MPPT and high-gain boost; thus considering the logic relationship of control signals, the final control law can be described as follows combing (25) with (35):
(37)δ=12[1+sign⁡(ΔVpv·ipv+Δipv·Vpv)]·(Vref-4VpvVo+(λk-1)evVo+kVodevdt+4LVodipvdt).


## 4.4. PWM Generation

The PWM signals are generated by comparing a control signal with a constant peak repetitive triangle signal (Vcs). The frequency of the repetitive triangle signal establishes the constant switching frequency.Figure9 shows the PWM signals generation technique. PWM1 is produced when the control signal Vm1 is greater than Vcs while PWM2 is produced when Vm1 is less than Vcs.Figure 9
PWM generator.The values of the desired duty cycleα can be gotten from (37). PWM signals are generated by (39):
(38)Vm1=δ,(39)PWM1={1Vm1>Vcs0Vm1<Vcs,PWM2={1Vm1<Vcs0Vm1>Vcs.


## 5. Simulation

Some simulation has been done in order to verify the performance of the topology and the main parameters can be referred to in Table1.Table 1
The main parameters.
Parameters
Values
V
oc/V
44.3
I
sc/A
7.7
V
mp at MPP/V
36
I
mp at MPP/A
7.2
Coupling coefficient
0.9
L
1 and L2/mH
0.4
C
1/μF
10
C
2/μF
100
C
0/μF
22
R/kΩ
1
Switching frequency/kHz
50The portion of the simulation results is given in Figure10.Simulation results.
(a)
Driving signals forS1 & S2
(b)
The output voltage and power of PV cell in process of MPPT
(c)
The output voltage wave
(d)
The current ofL1 and L2 and iin
(e)
The voltage wave of switched capacitorC1 and C2Figure10(a) shows the driving signals for S1 and S2, which are generated by the control law δ. The outputting voltage and power of PV cell in process of MPPT can be seen in Figure 10(b). From the simulation, one may get the conclusion that the DSME PWM controller can ensure that the PV cell runs at the maximum power point in a short time. Although the overshoot with a little range occurs in the process of power adjustment, it will be eliminated soon and the stable outputting power of 260 W is achieved. During the dynamic adjustment, there is a stable and fleet performance without oscillation.In Figure10(c), the dynamic response of the novel topology is the curve labeled overall trend. This curse shows that the converter can raise the voltage from 36 V to 400 V steadily without a long time. The curve labeled partial enlargement shows that the outputting voltage has a low voltage ripple when it is in stable state. Considering the whole PV grid-connected system, a DC-link high voltage with low ripple is convenient to choice and maintaining of the DC-link capacitor.As mentioned before, the converter can run under four modes in every switching period. The tendencies ofiL1 and iL2 as well as iin in every mode have been discussed in part III and it is also easy to get the conclusion about iin=iL1+iL2 based on Kirchhoff’s current law, so the tendency of iin can be obtained by the sum of iL1 and iL2. The first and second one of Figure 10(d) describe the stable current of iL1 and iL2 and iin, respectively, over the same period in stable mode. Figure 10(d) shows that the current iin has little ripple, which can reduce the coupled inductance losses and improve system efficiency.Figure10(e) shows the voltage waves of switched capacitors C1 and C2. The voltage of C1 is three times as much as the one of C2, close to three quarters of Vo; this simulation verifies the formula (13).


## 6. Experiments

Experiments have been finished in our laboratory just in order to verify the validity of theoretical analysis above and the performance of the new converter proposed in this paper.Experimental waveforms of the new converter are shown in Figure11. The driving signals of S1 and S2 from DSP on basis of the algorithm in this paper are given in Figure 11(a). Obviously, the new converter can raise the voltage from 36 V to 400 V when the duty cycle equals 0.64 (calculated from Figure 11(a)). The output voltage wave (after 10 times attenuation) is shown in Figure 11(b). Moreover, the ripple of the output voltage shown in Figure 11(b) can be limited in 8 V, which can decrease the loss of switched capacitors as shown in (15). Figure 11(c) shows the wave of the input current. The little input current ripple can reduce both the loss and the volume of the coupled inductance. Figures 11(d) and 11(e) show the voltage waveform of switched capacitors C1 and C2, respectively (after 10 times attenuation). The voltage of C1, about 300 V~306 V, is three times as much as the one of C2, about 92 V~100 V, which is consistent with both the analysis and the simulation results above; besides, the difference between the maximum and the minimum of voltage in the course of charging for each capacitance can be limited to a fairly small range, which can decrease the loss of switched capacitors.Experimental validation.
(a)
Driving signals forS1 and S2 from DSP
(b)
The outputting voltage wave (X10)
(c)
The wave of input current
(d)
The voltage wave of switched capacitorC1 (X10)
(e)
The voltage wave of switched capacitorC2 (X10)Burrs existing in experimental waveform mainly stem from the effect of EMI in the experiment.


## 7. Conclusion

This paper proposed a new high-gain interleaved converter with coupled inductances and switched capacitors network which are suited for PV application. After explaining its operating principle and analyzing its steady-state performance, then a control strategy for it on basis of SM-MPPT and DEC theory was designed. Both simulation analysis and experimental results showed that the proposed system had the following good performance.(1)
Achieving MPPT and producing a high-gain voltage in an extremely short time.(2)
Decreasing the ripple of the outputting voltage, as well as the inputting current and improving power density.(3)
Reducing the volume of magnetic components and cutting the cost of system.



---

*Source: 658674-2014-05-21.xml*