# Active Realization of Fractional-Order Integrators and Their Application in Multiscroll Chaotic Systems

Authors: Jesus M. Munoz-Pacheco; Luis Carlos Lujano-Hernández; Carlos Muñiz-Montero; Akif Akgül; Luis A. Sánchez-Gaspariano; Chun-Biao Li; Mustafa Çaǧri Kutlu
Journal: Complexity
 (2021)

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## Abstract

This paper presents the design, simulation, and experimental verification of the fractional-order multiscroll Lü chaotic system. We base them on op-amp-based approximations of fractional-order integrators and saturated series of nonlinear functions. The integrators are first-order active realizations tuned to reduce the inaccuracy of the frequency response. By an exponential curve fitting, we got a convenient design equation for realizing fractional-order integrators of orders from 0.1 to 0.95. The results include simulations in SPICE of the mathematical description and the electronic implementation and experimental measurements that confirm them. Monte Carlo and sensitivity tests revealed a robust realization. Contrary to its passive counterparts, the suggested realizations significantly reduce design and implementation efforts by favoring resistors and capacitors with commercial values and reducing hardware requirements.


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## Body

## 1. Introduction

Fractional calculus has been known since 1695 when L’Hôpital and Leibniz interchange letters about the noninteger order of the derivative. The fractional calculus is considered as a generalization of the integer-order version. Fractional-order derivatives are characterized by their memory properties providing an excellent approach for describing the physical phenomena elegantly with improved accuracy [1, 2]. As a result, the researchers have proposed novel mathematical models with applications in various fields, such as biology, economics, chaos theory, botany, hidden dynamics, digital circuits, cryptography, control, image processing, wind turbines, viscoelastic studies, and ferroelectric materials [3–15].Regarding chaos, there has been recently an increased number of works reporting fractional-order chaotic systems because fractional order provides an extra degree of freedom, which can be useful for generating diverse dynamics such as self-excited attractors, hidden attractors, multistability, and extreme stability [16–20]. In particular, the multiscroll chaotic attractors present plenty of complex topological structures contrary to single- or double-scroll attractors. One of the most typical applications is secure communications, e.g., in random number generators, cryptosystems in wireless networks, and image encryption [21–23]. Therefore, it is a subject of increasing interest [24–30].The physical realization of chaotic systems is a well-accepted technique to observe the chaotic behaviors and therefore validates the theoretical findings. From an engineering point of view, the challenge consists of implementing the fractional-order multiscroll chaotic systems physically since there is not a fabricated fractional-order capacitor yet commercially available [31, 32]. Hence, in the literature, we can find two approaches for implementing fractional-order differential equations that describe the chaotic systems. On the one side, the embedded methodology uses FPGAs or DSPs to describe the fractional-order dynamical system by implementing a numerical method to solve computationally the system rather than an electronic circuit [33]. Nevertheless, this approach has been demonstrated that induces degradation effects corrupting the chaos generation. On the other side, the analog method employs essential circuit elements for obtaining the fractional-order integrators. The basic idea consists of representing the fractional order with an integer-order transfer function of high degree. As a result, the electronic realization of the fractional integrator depends on a tree-like passive network formed with resistors and capacitors. However, the resulting passive emulator circuits nor contain commercial values neither a suitable design equation between elements (ratio of values), provoking a complexity for a proper tuning of the fractional order for observing chaos behavior. Therefore, the works focused on the physical implementation of fractional-order chaotic systems generating multiscrolls are limited and only found with implementations using passive networks [24–28].The question arising is how to obtain a straightforward approach for implementing fractional-order multiscroll chaotic systems with analog topologies? This paper will give a positive answer to this question. A first response is to use fractional-order integrators derived from an active circuit topology, which can be designed with circuit elements of commercial values or using an appropriate ratio of values. In this regard, some first results were proposed in refs. [31, 32], which reported active realization using integrated circuit technology. However, that approach has not been proved in either single-scroll or multiscroll chaotic systems. Therefore, the main contributions of this paper are as follows: (i) an optimized design methodology is proposed based on continued fraction expansion to obtain an active fractional integrator which can be related in a quick way to the fractional order of the chaotic systems; (ii) to the best knowledge of authors, the first experimental validation of a fractional-order multiscroll chaotic system is proposed based on active circuit topologies; and (iii) additionally, we perform an exhaustive study to demonstrate that the proposed design methodology is robust to statistical variations of element values and insensible to changes in the circuit elements.The electrical circuits to realize fractional-order integrators are based on “fractances,” electrical elements with fractional-order impedance. These elements produce a magnitude frequency response with roll-off±20α dB/dec and constant-phase response of ±90α degrees [34]. Unfortunately, the nonexistence of circuit elements with fractional response challenges carries out fractional-order transfer functions. The alternative is the approaching of fractances in a desired bandwidth with rational functions by means of methods of approximation such as Muir, Matsuda, Newton, Carlson, Oustaloup, power series (PSE), and continuous fraction expansion (CFE) [34–36]. The larger the order of the approximation, the larger the bandwidth where it is valid. Once got the rational function, the synthesis is possible using ladder networks of Cauer or Foster [36], tree structures, or transmission lines [35, 36]. The disadvantage of these realizations is the difficulty to approximate the required elements with commercially available resistances, capacitors, inductors, and even negative impedance converters, which results in bulky realizations [36–39]. For instance, Figure 1 shows a third-order realization using the Charef approach for a fractional-order passive fractance with α=0.95, an error of 1 dB, and a bandwidth from 0.1 rad/s to 1000 rad/s [40]. The circuit requires three resistors and three capacitors of disperse and not available values. To avoid this drawback in this paper, we present two proposals of implementation of s−α with active elements based on algebraic manipulation of a first-order CFE approximation. Despite its inaccuracy, in this work, we explore the use of a compact first-order approximation with α∈0,1 obtained by the CFE approach, but tuned to reduce error in the magnitude’s slope response. It has the form [34](1)1sα≈1−αs+1+α1+αs+1−α=s+AAs+1,A=1+α1−α.Figure 1
Approximation of a fractional-order passive fractance withα=0.95 and error of 1 dB.This article is organized as follows. Section2 provides a brief survey of fractional calculus, approximation of fractances, and op-amp-based building blocks. Section 3 depicts the circuit realization of the fractional-order integrator and presents Monte Carlo and sensitivity tests. Section 4 offers simulation and experimental results of the Lü chaotic oscillator and discusses the advantages of the proposed realization. We draw the conclusion in Section 5.


## 2. Theoretical Background

This section describes theoretical background such as fractional-order calculus, the Laplace transform of a fractional derivative, and op-amp-based building blocks for implementing fractional-order integrators and chaotic oscillators.


### 2.1. Fractional Derivative and Fractional Laplacian Operator

The Riemann–Liouville definition for calculation of fractional derivatives and integrals of a functionft establishes [41, 42](2)Dtαft=1Γm−αddtm∫0tfτdτt−τα−m+1,where α∈ℝ is the fractional order, m−1<α<m, m∈ℕ, and Γ⋅ is the gamma function. For α>0, α<0, and α=0, one gets the fractional derivative, fractional integral, and identity function. The Laplace transform of (2) with zero initial conditions becomes [41](3)ℒDtαft=sαFs,where Fs stands for Laplace transform of ft and sα is the fractional Laplacian operator given by(4)sα=jωα=ωαcosαπ2+jsinαπ2.


### 2.2. Op-Amp-Based Building Blocks

The circuits of Figure2 are the analog electronic blocks used in this paper to realize fractional-order integrators and chaotic oscillators. The selection of Rg, Rs, Ry, Cx, and Ω as degrees of freedom will allow reducing the number of passive elements with disperse or not commercially available values.Figure 2
Basic building blocks. (a) Weighted differential amplifier (WDA). (b) Two-input weighted adder amplifier (WAA). (c) Inverting integrator (IInv). (d) Inverting amplifier (Inv). (e) Four-input inverting weighted adder amplifier (IWAA). (f) SNLF for generating two and four scrolls. (g) Circuit realization of SNLF to generate two and four scrolls. (h) Lead/lag phase network.
(a)(b)(c)(d)(e)(f)(g)(h)


#### 2.2.1. Weighted Differential Amplifier (WDA)

The op-amp-based amplifier of Figure2(a) amplifies the weighted difference between two voltages V1A and V2A with pondering factors depending on Rg1 and Rg2. By nodal analysis, the output voltage Vout,A can be calculated as(5)Vout,A=RgRg1V1A−RgRg2V2A.


#### 2.2.2. Weighted Adder Amplifier (WAA)

The amplifier of Figure2(b) provides the weighted sum of two voltages V1B and V2B given by(6)Vout,B=RgRh1V1B+RgRh2V2B,where Rh1 and Rh2 control the pondering factors. Note that since this circuit is a noninverter adder based on a voltage series feedback amplifier, it presents a negative feedback loop which adds up stability to the weighted coefficients of V1B and V2B, which in turn are the pondering factors Rg/Rh1 and Rg/Rh2.


#### 2.2.3. Inverting Integrator (IInv)

The circuit of Figure2(c) uses capacitive feedback to integrate the voltage V1C through(7)Vout,CV1C=−1RxCxs=−1s,Rx=1Cx.A capacitorC can replace Cx to translate the frequency response by a factor Ω, where(8)C=CxΩ.In the time domain, expression (7) is rearranged to be written as(9)Vout,C=−1RxCx∫0tV1Cdt.


#### 2.2.4. Inverting Amplifier (Inv)

The circuit of Figure2(d) provides a negative voltage gain given by(10)Vout,DV1D=−RbRa.This negative gain is indicative of an inverting amplifier with a180° phase shift between V1D and Vout,D. The gain can be greater than, less than, or equal to 1 depending on the values of Ra and Rb.


#### 2.2.5. Inverting Weighted Adder Amplifier (IWAA)

The amplifier of Figure2(e) provides a weighted negative sum of four input voltages V1E, V2E, V3E, and V4E with pondering factors a, b, c, and d. By nodal analysis, the output voltage Vout,E can be calculated as(11)Vout,E=aV1E+bV2E+cV3E+dV4E.


#### 2.2.6. PWL Function Emulator (PWL)

Multiscroll chaotic oscillator circuits use saturated nonlinear functions (SNLFs) approximated by piecewise linear (PWL) functions [43, 44]. Figure 2(f) shows the SNLF for generating two and four scrolls. The number of scrolls achieved is the number of saturated levels, in this case with amplitudes E1, E2, E3, and E4. The breakpoints of the SNLF are e1, e2, and e3. Figure 2(g) represents the corresponding electronic realization. To generate two scrolls, the circuit requires two op-amps with two saturated levels at E1 and E2 and a shifted voltage (breakpoint) at e1. To make four scrolls, it requires four op-amps with four saturated levels at E1, E2, E3, and E4 and three shifted voltages at e1, e2, and e3.


#### 2.2.7. Lead/Lag Phase Network (LL)

The circuit of Figure2(h) is a particular case of a lead/lag phase network with transfer function(12)Vout,GV1G=Gs+AAs+1,A=1+α1−α,where we can use (8) to translate the frequencies of the zero ωz=A and the pole ωp=1/A by a factor Ω. It is important to remark that the circuit of Figure 2(h) is an op-amp-based lead compensator, and for the element values as they are labeled in the network, the transfer function becomes (12), which is a scaled version of the approximation in (1).


## 2.1. Fractional Derivative and Fractional Laplacian Operator

The Riemann–Liouville definition for calculation of fractional derivatives and integrals of a functionft establishes [41, 42](2)Dtαft=1Γm−αddtm∫0tfτdτt−τα−m+1,where α∈ℝ is the fractional order, m−1<α<m, m∈ℕ, and Γ⋅ is the gamma function. For α>0, α<0, and α=0, one gets the fractional derivative, fractional integral, and identity function. The Laplace transform of (2) with zero initial conditions becomes [41](3)ℒDtαft=sαFs,where Fs stands for Laplace transform of ft and sα is the fractional Laplacian operator given by(4)sα=jωα=ωαcosαπ2+jsinαπ2.


## 2.2. Op-Amp-Based Building Blocks

The circuits of Figure2 are the analog electronic blocks used in this paper to realize fractional-order integrators and chaotic oscillators. The selection of Rg, Rs, Ry, Cx, and Ω as degrees of freedom will allow reducing the number of passive elements with disperse or not commercially available values.Figure 2
Basic building blocks. (a) Weighted differential amplifier (WDA). (b) Two-input weighted adder amplifier (WAA). (c) Inverting integrator (IInv). (d) Inverting amplifier (Inv). (e) Four-input inverting weighted adder amplifier (IWAA). (f) SNLF for generating two and four scrolls. (g) Circuit realization of SNLF to generate two and four scrolls. (h) Lead/lag phase network.
(a)(b)(c)(d)(e)(f)(g)(h)


### 2.2.1. Weighted Differential Amplifier (WDA)

The op-amp-based amplifier of Figure2(a) amplifies the weighted difference between two voltages V1A and V2A with pondering factors depending on Rg1 and Rg2. By nodal analysis, the output voltage Vout,A can be calculated as(5)Vout,A=RgRg1V1A−RgRg2V2A.


### 2.2.2. Weighted Adder Amplifier (WAA)

The amplifier of Figure2(b) provides the weighted sum of two voltages V1B and V2B given by(6)Vout,B=RgRh1V1B+RgRh2V2B,where Rh1 and Rh2 control the pondering factors. Note that since this circuit is a noninverter adder based on a voltage series feedback amplifier, it presents a negative feedback loop which adds up stability to the weighted coefficients of V1B and V2B, which in turn are the pondering factors Rg/Rh1 and Rg/Rh2.


### 2.2.3. Inverting Integrator (IInv)

The circuit of Figure2(c) uses capacitive feedback to integrate the voltage V1C through(7)Vout,CV1C=−1RxCxs=−1s,Rx=1Cx.A capacitorC can replace Cx to translate the frequency response by a factor Ω, where(8)C=CxΩ.In the time domain, expression (7) is rearranged to be written as(9)Vout,C=−1RxCx∫0tV1Cdt.


### 2.2.4. Inverting Amplifier (Inv)

The circuit of Figure2(d) provides a negative voltage gain given by(10)Vout,DV1D=−RbRa.This negative gain is indicative of an inverting amplifier with a180° phase shift between V1D and Vout,D. The gain can be greater than, less than, or equal to 1 depending on the values of Ra and Rb.


### 2.2.5. Inverting Weighted Adder Amplifier (IWAA)

The amplifier of Figure2(e) provides a weighted negative sum of four input voltages V1E, V2E, V3E, and V4E with pondering factors a, b, c, and d. By nodal analysis, the output voltage Vout,E can be calculated as(11)Vout,E=aV1E+bV2E+cV3E+dV4E.


### 2.2.6. PWL Function Emulator (PWL)

Multiscroll chaotic oscillator circuits use saturated nonlinear functions (SNLFs) approximated by piecewise linear (PWL) functions [43, 44]. Figure 2(f) shows the SNLF for generating two and four scrolls. The number of scrolls achieved is the number of saturated levels, in this case with amplitudes E1, E2, E3, and E4. The breakpoints of the SNLF are e1, e2, and e3. Figure 2(g) represents the corresponding electronic realization. To generate two scrolls, the circuit requires two op-amps with two saturated levels at E1 and E2 and a shifted voltage (breakpoint) at e1. To make four scrolls, it requires four op-amps with four saturated levels at E1, E2, E3, and E4 and three shifted voltages at e1, e2, and e3.


### 2.2.7. Lead/Lag Phase Network (LL)

The circuit of Figure2(h) is a particular case of a lead/lag phase network with transfer function(12)Vout,GV1G=Gs+AAs+1,A=1+α1−α,where we can use (8) to translate the frequencies of the zero ωz=A and the pole ωp=1/A by a factor Ω. It is important to remark that the circuit of Figure 2(h) is an op-amp-based lead compensator, and for the element values as they are labeled in the network, the transfer function becomes (12), which is a scaled version of the approximation in (1).


## 2.2.1. Weighted Differential Amplifier (WDA)

The op-amp-based amplifier of Figure2(a) amplifies the weighted difference between two voltages V1A and V2A with pondering factors depending on Rg1 and Rg2. By nodal analysis, the output voltage Vout,A can be calculated as(5)Vout,A=RgRg1V1A−RgRg2V2A.


## 2.2.2. Weighted Adder Amplifier (WAA)

The amplifier of Figure2(b) provides the weighted sum of two voltages V1B and V2B given by(6)Vout,B=RgRh1V1B+RgRh2V2B,where Rh1 and Rh2 control the pondering factors. Note that since this circuit is a noninverter adder based on a voltage series feedback amplifier, it presents a negative feedback loop which adds up stability to the weighted coefficients of V1B and V2B, which in turn are the pondering factors Rg/Rh1 and Rg/Rh2.


## 2.2.3. Inverting Integrator (IInv)

The circuit of Figure2(c) uses capacitive feedback to integrate the voltage V1C through(7)Vout,CV1C=−1RxCxs=−1s,Rx=1Cx.A capacitorC can replace Cx to translate the frequency response by a factor Ω, where(8)C=CxΩ.In the time domain, expression (7) is rearranged to be written as(9)Vout,C=−1RxCx∫0tV1Cdt.


## 2.2.4. Inverting Amplifier (Inv)

The circuit of Figure2(d) provides a negative voltage gain given by(10)Vout,DV1D=−RbRa.This negative gain is indicative of an inverting amplifier with a180° phase shift between V1D and Vout,D. The gain can be greater than, less than, or equal to 1 depending on the values of Ra and Rb.


## 2.2.5. Inverting Weighted Adder Amplifier (IWAA)

The amplifier of Figure2(e) provides a weighted negative sum of four input voltages V1E, V2E, V3E, and V4E with pondering factors a, b, c, and d. By nodal analysis, the output voltage Vout,E can be calculated as(11)Vout,E=aV1E+bV2E+cV3E+dV4E.


## 2.2.6. PWL Function Emulator (PWL)

Multiscroll chaotic oscillator circuits use saturated nonlinear functions (SNLFs) approximated by piecewise linear (PWL) functions [43, 44]. Figure 2(f) shows the SNLF for generating two and four scrolls. The number of scrolls achieved is the number of saturated levels, in this case with amplitudes E1, E2, E3, and E4. The breakpoints of the SNLF are e1, e2, and e3. Figure 2(g) represents the corresponding electronic realization. To generate two scrolls, the circuit requires two op-amps with two saturated levels at E1 and E2 and a shifted voltage (breakpoint) at e1. To make four scrolls, it requires four op-amps with four saturated levels at E1, E2, E3, and E4 and three shifted voltages at e1, e2, and e3.


## 2.2.7. Lead/Lag Phase Network (LL)

The circuit of Figure2(h) is a particular case of a lead/lag phase network with transfer function(12)Vout,GV1G=Gs+AAs+1,A=1+α1−α,where we can use (8) to translate the frequencies of the zero ωz=A and the pole ωp=1/A by a factor Ω. It is important to remark that the circuit of Figure 2(h) is an op-amp-based lead compensator, and for the element values as they are labeled in the network, the transfer function becomes (12), which is a scaled version of the approximation in (1).


## 3. Fractional-Order Integrators

This section presents two realizations of fractional integrators using the blocks of Figure2. We will carry out Monte Carlo and sensitivity analyses in them to study how the uncertainty in the output voltage is allocated to the tolerances of the circuit elements. In addition, we will tune some circuit elements to diminish the slope error in the magnitude frequency response caused by the first-order CFE approximation.


### 3.1. Circuit Implementation

In order to achieve a circuit implementation of the first-order CFE approximation of the fractional integrator given by (1), consider a transfer function in frequency-domain, V0s/Vis, expressed in the same form, i.e.,(13)Fs=VosVis=s+AAs+1,where Vis and Vos are input and output voltages. An algebraic manipulation on (13) leads to(14)VosAs+1=Viss+A,sAVos=sVis+AVis−Vos,and dividing both sides of (14) by As and collecting similar terms, we get(15)Vos=VisA+−1s︸IInv blockVosA−Vis︸WDA block︸WAA block.Figures3(a) and 3(b) illustrate the corresponding block diagram and electronic realization using circuits WDA, IInv, and WAA. A comparison of (15) with (5) and (6) results in(16)Rg1=Rh2=ARg,Rg2=Rh1=Rg.Figure 3
Fractional-order integrator. (a) Block diagram. (b) First implementation. (c) Second implementation.
(a)(b)(c)To determineC and Rx, we apply (7) and (8) after designating the degrees of freedom Cx and Ω. Later, once chosen the degree of freedom Rg, for the order α required and using (1), we calculate Rg1=Rh2=ARg (circuit elements are denoted in blue in Figure 3(b)). The rest of resistances have a value of Rg. As an example, after adopting the degrees of freedom Rg=100Ω, Cx=0.1mF, and Ω=1E5, the resistances Rg1=Rh2 shown in the table of Figure 3(b) result for each order α=0.1,0.2,0.3,0.4,0.5,0.6,0.7,0.8,0.85,0.9,0.95.Other alternative of implementation is with the circuit of Figure2(h) which corresponds to the transfer function (12). To determine C, we apply (8) after designating the degrees of freedom Cx and Ω. Later, once chosen the degrees of freedom Ry and G, for the order α required and under A=1+α/1−α, we calculate 1/ACx, A/Cx, and GRy/A (circuit elements are denoted in blue in Figure 3(c)).


### 3.2. Experimental Validation and Slope Adjustment

We simulated the fractional integrator of Figure3(b) in HSPICE and breadboarded it with op-amps TL081 (gain bandwidth product = 100 kHz, dc gain = 200 V/V, and supply voltage = ±15 V). The input was a sinusoidal voltage with 0.1 V in amplitude and frequency ranged from 1 kHz to 100 kHz. An NI ELVIS II + laboratory platform provided this signal and bias potentials of ±15 V for the op-amps. Figure 4(a) shows the measured frequency responses for α=0.1,0.2,0.3,0.4,0.5,0.6,0.7,0.8,0.85,0.9,0.95. These plots presented a satisfactory agreement with the results in HSPICE and with numerical simulations of (1) in Matlab. In consequence, the first-order CFE approximation of the fractional integrator causes the slope errors of the frequency responses reported in Table 1, with negligible influence of the circuit elements and no idealities of the op-amps. In agreement with Table 1, these errors are considerable (except for α=0.1, α=0.9, and α=0.95), extending from 0.09 dB to 4.73 dB. This performance is prohibitive to carry out chaotic oscillators, which are susceptible to their parameters and initial conditions. To reduce these errors, for each value of α, we did an experimental tuning of Rg1=Rh2=ARg (see the table of Figure 3(b)). This is equivalent to adjusting α through A, getting the frequency responses of Figure 4(b). From this figure and according to Table 1, the adjustment reduces the slope errors to values in the range from −0.09 dB to 0.6 dB, which produces values of α closer to the theoretical ones. The corresponding curve fitting of Figure 5 brings us a design equation to calculate A respect to α, resulting in(17)Aα=1.014e1.241α+0.002697e7.48α,(18)1sα≈s+1.014e1.241α+0.002697e7.48α1.014e1.241α+0.002697e7.48αs+1.Figure 4
Experimental results of the fractional-order integrator: (a) without adjustment and (b) with adjustment.
(a)(b)Table 1
A adjustment for each order α=0.1,0.2,0.3,0.4,0.5,0.6,0.7,0.8,0.85,0.9,0.95.
Theoretical valueExperimental data without adjustmentExperimental data with adjustmentαSlope (dB/dec)AARgkΩSlope (dB/dec)Error (dB)AARgkΩSlope (dB/dec)Error (dB)Phase error (%)Equivalentα0.1021.200.1202.9600.961.10.112.1400.14−1.120.10700.2041.500.1506.3002.301.30.134.1700.17−2.570.20850.3061.850.1858.9002.901.60.166.6000.60−3.160.33000.4082.330.23311.843.841.70.177.910−0.09−2.790.39550.50103.000.30014.534.532.00.2010.140.14−2.480.50700.60124.000.40016.734.732.40.2412.400.40−2.950.62000.70145.660.56618.384.382.80.2813.94−0.06−2.540.69700.80169.000.90020.004.003.90.3916.460.46−2.270.82300.851712.31.23020.243.244.50.4517.010.01−3.320.85050.901819.01.90019.151.155.30.5318.100.10−0.570.90500.951939.03.90019.090.096.60.6619.020.02−0.070.9510Figure 5
Approximation ofA as an exponential function of α.For the circuit of Figure3(c) and using the adjusted values of A of Table 1, for Ry=1kΩ, Cx=0.1μF, and Ω=1E5, the resistances of values 1/ACx, A/Cx, and GRy/A shown in the table of Figure 3(c) are obtained. Here, α=0.9,0.95 and G=3,3.5. Although there are other alternatives for implementing fractional-order integrators, as discussed in Section 1, the first-order CFE implementation used in this work is very compact and does not require circuit elements with noncommercial values. Therefore, to the best of the authors’ knowledge, this is the first experimental validation of a multiscroll chaotic system based on active fractional-order circuits, and thus, there are not any other works where either simulated or experimental results are reported, and consequently, those cannot be compared with our proposal. In fact, other fractional-order multiscroll chaotic systems based on passive ladder networks as reported in [43, 44] require more hardware, including resistors and capacitors with noncommercial values.


### 3.3. Monte Carlo Analysis

To verify that the circuit of Figure3(b) is robust to tolerances, we carried out a Monte Carlo analysis in SPICE. We dealt with tolerances of ±5% and ±20% in the resistors and capacitors using a normal distribution with N = 100. The variable to examine is the slope of the magnitude response for each value α=0.1,0.2,0.3,0.4,0.5,0.6,0.7,0.8,0.85,0.9,0.95. To simplify, Figure 6 depicts only the histograms corresponding to the adjusted circuit with α=0.9 and α=0.95. We observe distributions similar to a normal distribution. Table 2 outlines the obtained results for each value of α and for both cases, with and without adjustment. The resulting standard deviations are small, in the range from 0.027 dB/dec to 0.23 dB/dec, and comparable in both cases. Figure 7(a) illustrates the mean slope obtained for each order. Without tuning, these values move away from the line that describes the theoretical slopes. Figure 7(b) depicts the largest and smallest values that the slope gets without tuning. The maximum error is in the range from 0.5 dB to 4.5 dB. No one order (except α=0.1) encloses the curve of the ideal slope. From Figure 7(c), we observe that the greatest and smallest values of the slope with tuning are closer to the ideal line, enclosing it. The maximum error is in the range of 0.6 dB. This way, the error in the first-order CFE approximation without adjustment influences the slope more than the tolerances.Figure 6
Histograms (Monte Carlo analysis): (a)α=0.9 and (b) α=0.95.
(a)(b)Table 2
Monte Carlo analysis.
Without adjustmentWith adjustmentαMean slope (dB/dec)Std. dev. (dB/dec)Min. (dB/dec)Max. (dB/dec)Mean slope (dB/dec)Std. dev. (dB/dec) (m)Min. (dB/dec)Max. (dB/dec)0.10−2.54200.62−3.04−1.94−1.90189.72−2.35−1.410.20−5.77177.18−6.12−5.30−3.77197.33−4.24−3.330.30−8.65204.31−9.18−8.23−6.73177.47−7.13−6.240.40−11.45167.15−11.92−11.03−7.57175.89−7.95−7.090.50−14.00213.91−14.55−13.53−9.65187.33−10.10−9.110.60−16.29153.06−16.56−15.86−11.8159.39−12.28−11.430.70−18.1390.907−18.28−17.76−13.39151.61−13.74−13.000.80−19.17167.37−19.54−18.64−15.91238.89−16.49v15.300.85−18.50167.71−18.92−18.08−16.89180.43−17.16−16.440.90−19.3097.381−19.50−18.97−17.75153.82−18.00−17.260.95−19.8327.705−19.89−19.73−18.60129.53−18.85−18.17Figure 7
Monte Carlo analysis: (a) mean values of slope with and without adjustment. (b) Maximum and minimum values of slope without adjustment. (c) Maximum and minimum values of slope with adjustment.
(a)(b)(c)


### 3.4. Sensitivity Analysis

In assessing the sensitivity of the output voltage of the fractional-order integrator of Figure8 regarding its resistive elements, by performing a normalized sensitivity simulation, the results reported in Table 3 are achieved. Note that only four of the thirteen resistors of the circuit are in Table 3 since these are those who exhibit a “major” impact on the integrator’s sensitivity. As appreciated, different scenarios may occur depending on the value of α, but in general terms sensitivity is a little less when the adjustment has been applied. Without loss of generality, we can say that the larger the value of α is, the larger the sensitivity becomes. Still, sensitivity is highly acceptable. Let us take the worst case when α=0.95 and a 1% variation of the nominal value of RG02 produces a deviation of ≈2.3mV in the output voltage of the circuit. Even though this value is low, a lesser variation can be attained if a high-precision resistor (with a tolerance <1%) is used for RG02. We can apply the same criteria for the rest of the resistors in terms of tolerances; however, there is a trade-off between sensitivity and realization cost, and high-precision resistors are also more expensive. It is important to emphasize that the sensitivity of the output voltage at a frequency of 0 Hz ω=0rad/s, i.e., at DC regime, and Vin=1V is equivalent to determine the sensitivity of the transfer function, Fs, when s=jω=0, i.e., for F0=A. And thus, we are evaluating A variation as a function of the resistive elements.Figure 8
Fractional-order integrator: notation for the sensitivity analysis.Table 3
Sensitivity analysis.
OrderSensitivity without adjustmentSensitivity with adjustmentαRG02 (mV/%)RG11 (mV/%)RG20 (mV/%)RH10 (mV/%)RG02 (mV/%)RG11 (mV/%)RG20 (mV/%)RH10 (mV/%)0.10—8.47−7.77——7.56−7.22—0.20—11.3−9.38——9.39−8.31—0.30—14.6−11.2——12.2−9.91—0.40—19.2−13.7——13.1−10.4—0.5011.48.562.6e−136.422.95e−416.0−12.0−1.96e−40.6013.18.38−7.75e−58.374.08e−419.9−14.1−2.88e−40.7015.27.74−1.28e−410.95.4e−423.8−16.1−3.98e−40.8017.86.40—14.313.08.41—8.190.8519.45.37—16.413.88.21—9.220.9021.24.00—18.814.87.89—10.40.9523.322.3—21.416.17.34—12.1To evaluate the sensitivity of the fractional-order integrator regarding capacitorCx, Figure 9 depicts the behavior of the normalized sensitivity of Fs for both with and without adjustment of parameter A. We define the normalized sensitivity as(19)SCxFs=CxFsdFsdCx,with nominal values Cx=1nF and s=2π15.91kHzj, and with Fs given by (13). As illustrated, the tendency is rising towards the 1% of Fs variation as Cx changes 1% of its nominal value along with the α increment.Figure 9
Normalized sensitivity ofFs regarding Cx.According to the results reported above, we can conclude that the proposed fractional-order integrator exhibits a low sensitivity regarding variations of the values of its passive elements.


## 3.1. Circuit Implementation

In order to achieve a circuit implementation of the first-order CFE approximation of the fractional integrator given by (1), consider a transfer function in frequency-domain, V0s/Vis, expressed in the same form, i.e.,(13)Fs=VosVis=s+AAs+1,where Vis and Vos are input and output voltages. An algebraic manipulation on (13) leads to(14)VosAs+1=Viss+A,sAVos=sVis+AVis−Vos,and dividing both sides of (14) by As and collecting similar terms, we get(15)Vos=VisA+−1s︸IInv blockVosA−Vis︸WDA block︸WAA block.Figures3(a) and 3(b) illustrate the corresponding block diagram and electronic realization using circuits WDA, IInv, and WAA. A comparison of (15) with (5) and (6) results in(16)Rg1=Rh2=ARg,Rg2=Rh1=Rg.Figure 3
Fractional-order integrator. (a) Block diagram. (b) First implementation. (c) Second implementation.
(a)(b)(c)To determineC and Rx, we apply (7) and (8) after designating the degrees of freedom Cx and Ω. Later, once chosen the degree of freedom Rg, for the order α required and using (1), we calculate Rg1=Rh2=ARg (circuit elements are denoted in blue in Figure 3(b)). The rest of resistances have a value of Rg. As an example, after adopting the degrees of freedom Rg=100Ω, Cx=0.1mF, and Ω=1E5, the resistances Rg1=Rh2 shown in the table of Figure 3(b) result for each order α=0.1,0.2,0.3,0.4,0.5,0.6,0.7,0.8,0.85,0.9,0.95.Other alternative of implementation is with the circuit of Figure2(h) which corresponds to the transfer function (12). To determine C, we apply (8) after designating the degrees of freedom Cx and Ω. Later, once chosen the degrees of freedom Ry and G, for the order α required and under A=1+α/1−α, we calculate 1/ACx, A/Cx, and GRy/A (circuit elements are denoted in blue in Figure 3(c)).


## 3.2. Experimental Validation and Slope Adjustment

We simulated the fractional integrator of Figure3(b) in HSPICE and breadboarded it with op-amps TL081 (gain bandwidth product = 100 kHz, dc gain = 200 V/V, and supply voltage = ±15 V). The input was a sinusoidal voltage with 0.1 V in amplitude and frequency ranged from 1 kHz to 100 kHz. An NI ELVIS II + laboratory platform provided this signal and bias potentials of ±15 V for the op-amps. Figure 4(a) shows the measured frequency responses for α=0.1,0.2,0.3,0.4,0.5,0.6,0.7,0.8,0.85,0.9,0.95. These plots presented a satisfactory agreement with the results in HSPICE and with numerical simulations of (1) in Matlab. In consequence, the first-order CFE approximation of the fractional integrator causes the slope errors of the frequency responses reported in Table 1, with negligible influence of the circuit elements and no idealities of the op-amps. In agreement with Table 1, these errors are considerable (except for α=0.1, α=0.9, and α=0.95), extending from 0.09 dB to 4.73 dB. This performance is prohibitive to carry out chaotic oscillators, which are susceptible to their parameters and initial conditions. To reduce these errors, for each value of α, we did an experimental tuning of Rg1=Rh2=ARg (see the table of Figure 3(b)). This is equivalent to adjusting α through A, getting the frequency responses of Figure 4(b). From this figure and according to Table 1, the adjustment reduces the slope errors to values in the range from −0.09 dB to 0.6 dB, which produces values of α closer to the theoretical ones. The corresponding curve fitting of Figure 5 brings us a design equation to calculate A respect to α, resulting in(17)Aα=1.014e1.241α+0.002697e7.48α,(18)1sα≈s+1.014e1.241α+0.002697e7.48α1.014e1.241α+0.002697e7.48αs+1.Figure 4
Experimental results of the fractional-order integrator: (a) without adjustment and (b) with adjustment.
(a)(b)Table 1
A adjustment for each order α=0.1,0.2,0.3,0.4,0.5,0.6,0.7,0.8,0.85,0.9,0.95.
Theoretical valueExperimental data without adjustmentExperimental data with adjustmentαSlope (dB/dec)AARgkΩSlope (dB/dec)Error (dB)AARgkΩSlope (dB/dec)Error (dB)Phase error (%)Equivalentα0.1021.200.1202.9600.961.10.112.1400.14−1.120.10700.2041.500.1506.3002.301.30.134.1700.17−2.570.20850.3061.850.1858.9002.901.60.166.6000.60−3.160.33000.4082.330.23311.843.841.70.177.910−0.09−2.790.39550.50103.000.30014.534.532.00.2010.140.14−2.480.50700.60124.000.40016.734.732.40.2412.400.40−2.950.62000.70145.660.56618.384.382.80.2813.94−0.06−2.540.69700.80169.000.90020.004.003.90.3916.460.46−2.270.82300.851712.31.23020.243.244.50.4517.010.01−3.320.85050.901819.01.90019.151.155.30.5318.100.10−0.570.90500.951939.03.90019.090.096.60.6619.020.02−0.070.9510Figure 5
Approximation ofA as an exponential function of α.For the circuit of Figure3(c) and using the adjusted values of A of Table 1, for Ry=1kΩ, Cx=0.1μF, and Ω=1E5, the resistances of values 1/ACx, A/Cx, and GRy/A shown in the table of Figure 3(c) are obtained. Here, α=0.9,0.95 and G=3,3.5. Although there are other alternatives for implementing fractional-order integrators, as discussed in Section 1, the first-order CFE implementation used in this work is very compact and does not require circuit elements with noncommercial values. Therefore, to the best of the authors’ knowledge, this is the first experimental validation of a multiscroll chaotic system based on active fractional-order circuits, and thus, there are not any other works where either simulated or experimental results are reported, and consequently, those cannot be compared with our proposal. In fact, other fractional-order multiscroll chaotic systems based on passive ladder networks as reported in [43, 44] require more hardware, including resistors and capacitors with noncommercial values.


## 3.3. Monte Carlo Analysis

To verify that the circuit of Figure3(b) is robust to tolerances, we carried out a Monte Carlo analysis in SPICE. We dealt with tolerances of ±5% and ±20% in the resistors and capacitors using a normal distribution with N = 100. The variable to examine is the slope of the magnitude response for each value α=0.1,0.2,0.3,0.4,0.5,0.6,0.7,0.8,0.85,0.9,0.95. To simplify, Figure 6 depicts only the histograms corresponding to the adjusted circuit with α=0.9 and α=0.95. We observe distributions similar to a normal distribution. Table 2 outlines the obtained results for each value of α and for both cases, with and without adjustment. The resulting standard deviations are small, in the range from 0.027 dB/dec to 0.23 dB/dec, and comparable in both cases. Figure 7(a) illustrates the mean slope obtained for each order. Without tuning, these values move away from the line that describes the theoretical slopes. Figure 7(b) depicts the largest and smallest values that the slope gets without tuning. The maximum error is in the range from 0.5 dB to 4.5 dB. No one order (except α=0.1) encloses the curve of the ideal slope. From Figure 7(c), we observe that the greatest and smallest values of the slope with tuning are closer to the ideal line, enclosing it. The maximum error is in the range of 0.6 dB. This way, the error in the first-order CFE approximation without adjustment influences the slope more than the tolerances.Figure 6
Histograms (Monte Carlo analysis): (a)α=0.9 and (b) α=0.95.
(a)(b)Table 2
Monte Carlo analysis.
Without adjustmentWith adjustmentαMean slope (dB/dec)Std. dev. (dB/dec)Min. (dB/dec)Max. (dB/dec)Mean slope (dB/dec)Std. dev. (dB/dec) (m)Min. (dB/dec)Max. (dB/dec)0.10−2.54200.62−3.04−1.94−1.90189.72−2.35−1.410.20−5.77177.18−6.12−5.30−3.77197.33−4.24−3.330.30−8.65204.31−9.18−8.23−6.73177.47−7.13−6.240.40−11.45167.15−11.92−11.03−7.57175.89−7.95−7.090.50−14.00213.91−14.55−13.53−9.65187.33−10.10−9.110.60−16.29153.06−16.56−15.86−11.8159.39−12.28−11.430.70−18.1390.907−18.28−17.76−13.39151.61−13.74−13.000.80−19.17167.37−19.54−18.64−15.91238.89−16.49v15.300.85−18.50167.71−18.92−18.08−16.89180.43−17.16−16.440.90−19.3097.381−19.50−18.97−17.75153.82−18.00−17.260.95−19.8327.705−19.89−19.73−18.60129.53−18.85−18.17Figure 7
Monte Carlo analysis: (a) mean values of slope with and without adjustment. (b) Maximum and minimum values of slope without adjustment. (c) Maximum and minimum values of slope with adjustment.
(a)(b)(c)


## 3.4. Sensitivity Analysis

In assessing the sensitivity of the output voltage of the fractional-order integrator of Figure8 regarding its resistive elements, by performing a normalized sensitivity simulation, the results reported in Table 3 are achieved. Note that only four of the thirteen resistors of the circuit are in Table 3 since these are those who exhibit a “major” impact on the integrator’s sensitivity. As appreciated, different scenarios may occur depending on the value of α, but in general terms sensitivity is a little less when the adjustment has been applied. Without loss of generality, we can say that the larger the value of α is, the larger the sensitivity becomes. Still, sensitivity is highly acceptable. Let us take the worst case when α=0.95 and a 1% variation of the nominal value of RG02 produces a deviation of ≈2.3mV in the output voltage of the circuit. Even though this value is low, a lesser variation can be attained if a high-precision resistor (with a tolerance <1%) is used for RG02. We can apply the same criteria for the rest of the resistors in terms of tolerances; however, there is a trade-off between sensitivity and realization cost, and high-precision resistors are also more expensive. It is important to emphasize that the sensitivity of the output voltage at a frequency of 0 Hz ω=0rad/s, i.e., at DC regime, and Vin=1V is equivalent to determine the sensitivity of the transfer function, Fs, when s=jω=0, i.e., for F0=A. And thus, we are evaluating A variation as a function of the resistive elements.Figure 8
Fractional-order integrator: notation for the sensitivity analysis.Table 3
Sensitivity analysis.
OrderSensitivity without adjustmentSensitivity with adjustmentαRG02 (mV/%)RG11 (mV/%)RG20 (mV/%)RH10 (mV/%)RG02 (mV/%)RG11 (mV/%)RG20 (mV/%)RH10 (mV/%)0.10—8.47−7.77——7.56−7.22—0.20—11.3−9.38——9.39−8.31—0.30—14.6−11.2——12.2−9.91—0.40—19.2−13.7——13.1−10.4—0.5011.48.562.6e−136.422.95e−416.0−12.0−1.96e−40.6013.18.38−7.75e−58.374.08e−419.9−14.1−2.88e−40.7015.27.74−1.28e−410.95.4e−423.8−16.1−3.98e−40.8017.86.40—14.313.08.41—8.190.8519.45.37—16.413.88.21—9.220.9021.24.00—18.814.87.89—10.40.9523.322.3—21.416.17.34—12.1To evaluate the sensitivity of the fractional-order integrator regarding capacitorCx, Figure 9 depicts the behavior of the normalized sensitivity of Fs for both with and without adjustment of parameter A. We define the normalized sensitivity as(19)SCxFs=CxFsdFsdCx,with nominal values Cx=1nF and s=2π15.91kHzj, and with Fs given by (13). As illustrated, the tendency is rising towards the 1% of Fs variation as Cx changes 1% of its nominal value along with the α increment.Figure 9
Normalized sensitivity ofFs regarding Cx.According to the results reported above, we can conclude that the proposed fractional-order integrator exhibits a low sensitivity regarding variations of the values of its passive elements.


## 4. Fractional-Order Multiscroll Lü Chaotic System

In this section, we design electronic circuits based on the building blocks of Figure2 and the fractional integrators of Figure 3 to realize commensurate fractional-order Lü chaotic system, i.e., system with equal fractional order for integrators. A commensurate realization is acceptable to test the functionality and benefits of using the active fractional-order integrators of Figure 3, but incommensurate fractional-order oscillators, as those reported in [45–47] or [48] can also be realized with the proposed approach without increasing hardware requirements. In fact, the proposed approach is an attractive alternative for the design of incommensurate fractional-order oscillators because it is necessary to calculate the parameter A using (17) instead of designing ladder networks.The fractional-order Lü chaotic system is a realization that represents the transition from the Lorenz to the Chen attractor [49, 50]. The Lü system displays the following system of equations:(20)Dαx=y,Dαy=z,Dαz=−ax−by−cz+d1fx︸PWL,where x, y, and z are state variables, a, b, c, and d are positive real constants, α∈0,1 is the fractional order, and fx is a SNLF similar to that represented in Figure 2(f). In [43, 49], the authors determine, for a Lü chaotic oscillator, the suitable incommensurate fractional order to preserve the chaotic behavior with a,b,c,d=2,1,0.6,2, getting α1=0.8, α2=0.9, and α3=0.95 and Lyapunov exponents LE1=0.3226, LE2=0, and LE3=−1.2203. Taking as reference that design, we will design our 2-scroll and 4-scroll commensurate realizations with the same parameters a, b, c, and d, and with α=0.9 and α=0.95. The stability can be verified by using the method reported in [51].Figure10 depicts the block diagram and design details of the commensurate fractional-order system in (20). Figure 11 shows the corresponding experimental setup with fractional integrators as those depicted in Figure 3(b) and all the circuits realized using TL081 op-amps. The setup comprises a Keysight DSOX3054A oscilloscope, two DC power supplies RIGOL DP832 and BK precision 1550, and the PCB realized with the software Altium Designer 19. The design details of the PWL block for a 4-scroll chaotic attractor are presented in this figure for a saturation voltage Vsat=13.5V. VCC and VEE are the bias voltages of the op-amps TL081, while V+ and V− are the voltages required by the block fx. The 2-scroll chaotic attractor can be obtained with this circuit, as is illustrated in Figure 2(g). The four-input IWAA is designed with the degree of freedom Rg=1kΩ and the desired values for a, b, c, and d. We incorporated a gain G to the first and second approximations of the fractional integrator to add tuning capacity. The parameter A was calculated using (17) and the degrees of freedom for the first approximation were Rg=100Ω, Cx=0.1mF, Ω=1E5, C=1nF, and Rx=5kΩ. For the second approximation, we used Ry=1kΩ, Cx=0.1μF, Ω=1E5, and C=1pF. Values of G=3 and G=3.5 were used for α=0.9 and α=0.95 to approximate the frequency response of the integrators to the response of equivalent passive realizations. We can observe that, with the first approximation, the chaotic oscillator requires for implementation 54 resistors, 3 capacitors, and 14 op-amps. With the second approximation, the circuit comprises 27 resistors, 6 capacitors, and 11 op-amps. Figures 12(a) and 12(b) show the SPICE simulation and experimental measurement of the 2-scroll chaotic attractor projected onto xy-plane (phase space portrait) for α=0.9. Figures 12(c) and 12(d) show the SPICE simulation and experimental measurement of the same projection for α=0.95. We can observe an agreement between simulation, theoretical, and experimental results. Figures 13(a) and 13(b) show the SPICE simulation and experimental measurement of the projection of the 4-scroll chaotic attractor onto xy-plane for α=0.9. Figures 13(c) and 13(d) show the SPICE simulation and experimental measurement of the same projection for α=0.95. Again we observe agreement between simulation and experimental results.Figure 10
Block diagram and circuit synthesis to realize the fractional-order multiscroll PWL Lü chaotic system in (20) with α=0.9 and α=0.95.Figure 11
Experimental setup.Figure 12
Projection of the 2-scroll chaotic attractor ontoxy-plane (phase space portrait): (a) simulation result with α=0.9 (SPICE); (b) experimental result with α=0.9 (oscilloscope scale = 0.5 V per division); (c) simulation result with α=0.95 (SPICE); (d) experimental result with α=0.95 (oscilloscope scale = 0.3 V per division).
(a)(b)(c)(d)Figure 13
Projection of the 4-scroll chaotic attractor ontoxy-plane (phase space portrait): (a) simulation result with α=0.9 (SPICE); (b) experimental result with α=0.9 (oscilloscope scale = 1 V per division); (c) simulation result with α=0.95 (SPICE); (d) experimental result with α=0.95 (oscilloscope scale = 1 V per division).
(a)(b)(c)(d)Table4 shows a comparison of the hardware requirements of the two proposed realization and the fractional-order oscillators reported in [43, 44]. Despite the active realization of the fractional integrators, we observe that the two proposed implementations reduce the number of required op-amps (reducing power consumption), do not require noncommercial capacitors, and have a comparable number of noncommercial resistors. Unlike the resistors used in [43, 44], the values of the noncommercial resistors of the proposed realizations are easy to approximate with combinations of commercially available resistors, avoiding bulky realizations difficult to redesign. Another advantage is the easy design of the fractional-order integrators using (17) instead of calculating the elements of ladder networks.Table 4
Comparison of hardware requirements of implemented Lü fractional-order chaotic oscillators.
RealizationNumber of resistorsNumber of capacitorsOp-ampsCommercialNoncommercialTotalCommercialNoncommercialTotal[43]3311440111115[44]161733099151st approximation421254303142nd approximation1892760611


## 5. Conclusion

This paper presented the design and electronic implementation of a commensurate fractional-order multiscroll chaotic oscillator with ordersα=0.9 and α=0.95. The fractional-order integrators realized with tuned first-order active realizations are robust to tolerances in the passive elements and favor the use of resistors and capacitors with commercial values, reducing hardware requirements and design and implementation efforts. The easy design of the fractional-order integrators with improved accuracy using (17) instead of calculating ladder networks could favor the practical realization of other types of systems, such as incommensurate chaotic oscillators, fractional-order filters, fractional-order controllers, and fractional-order memristors.Finally, the physical realization of fractional-order chaotic systems with hidden dynamics (attractors without equilibrium points, multistability, extreme multistability, etc.) along with their synchronization schemes using the proposed approach will be conducted in future works to explore secure communications based on fractional chaos.



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