# Fowler-Nordheim Tunneling Characterization on Poly1-Poly2 Capacitors for the Implementation of Analog Memories in CMOS 0.5μm Technology

Authors: Enrique J. Tinajero-Perez; Jesus Ezequiel Molinar-Solis; Rodolfo Z. Garcia-Lozano; Pedro Rosales-Quintero; Jose M. Rocha-Perez; Alejandro Diaz-Sanchez; Arturo Morales-Acevedo
Journal: Advances in Condensed Matter Physics
 (2014)

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## Abstract

The experimental results of the Fowler-Nordheim characterization using poly1-poly2 capacitors on CMOS ON Semi 0.5μm technology are presented. This characterization allows the development, design, and characterization of a new current-mode analog nonvolatile memory. Experimental results of the memory cell architecture are presented and demonstrate the usefulness of the proposed architecture.


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## Body

## 1. Introduction

For decades, the floating gate MOS transistors (FG-MOS) have been used as an important element for analog and digital circuit design. Over the years, a wide spectrum of floating gate devices has been proposed for analog applications. Some of them are related to the development of analog nonvolatile memories [1], where the storage of charge in a floating gate (FG) cell is later used as information in voltage-mode or current-mode. This kind of devices is very useful for trimming in analog circuits and information storage for artificial neural networks. Several methods have been used for injecting or removing charge onto a floating gate: the hot electron injection (HEI), Fowler-Nordheim tunneling (F-N) [2], and UV conductances [3]. Over the time, many analog nonvolatile cells have been proposed; Fujita and Amemiya [4] present a structure that has two floating gates connected through a high resistance ~1 GΩ. Though it is a compact cell, it is not achievable in standard CMOS processes, since the integration of such high resistances is not possible.In the paper [5], Harrison et al. present an on-chip nonvolatile analog memory array. The design uses NMOS transistors with N-well layer as drain in order to address high voltages on chip. Thus, this high voltage is used to allow F-N for programming a specific cell in the whole array. However, the design of an NMOS with this feature violates a design rule related to “active to well edge” in standard CMOS technology.Figueroa Toro [6] proposes a negative feedback floating gate configuration with two transistors, one capacitor and one inverter amplifier. In this case it is necessary to include an on-chip charge pump, which is used to induce the F-N mechanism. Hence, the design area is augmented by the need of special circuitry.Moreover, Diorio et al. [7] presents a structure with two PMOS transistors. One transistor has a thin gate oxide that tunnels at much lower voltages. The other transistor uses high drain voltages to induce the HEI mechanism in order to increase the electron charge onto the floating gate. Nevertheless, the thin oxide layer tends to degrade with the use of the cell. Thus, the lifetime of the cell is reduced notably.In this paper, the F-N characterization and the design of a current-mode analog nonvolatile memory are presented. The key element avoids the use of internal high voltages devices (>10 V) on-chip for addressing the F-N programming mechanism. The cell design uses a single floating gate, a poly1-poly2 injector, and a control gate. Thus, F-N tunneling is used to charge and discharge the floating gate. The sections of this paper are organized as follows: the next section will explain the characterization of the F-N current in poly1-poly2 capacitors. Section3 gives an overview of the cell design. Section 4 reviews the simulations and the experimental results are presented. Finally, the conclusions are presented in Section 5.


## 2. F-N Characterization on Poly1-Poly2 Capacitors

Depending on the thickness of silicon oxide, there are several electron-transport mechanisms. The F-N tunneling is the dominant mechanism when the oxide thickness is greater than a few tens of nanometers and electrical fields (Eox) greater than 6 × 106 V/cm [2]. The current density (JFN) caused by the F-N tunneling through a SOS (silicon-oxide-silicon) capacitor of area A can be described by the following classical equation:
(1)JFN=CFNEox2exp⁡[-432mox*qℏ(qϕB)3/2Eox],
where CFN is a constant, Eox is the electrical field, mox* is the effective electron mass in the oxide, q is the electron charge, ℏ is the normalized Planck constant, and ϕB is the barrier height between conductor and isolator layer, in this particular case, highly doped polysilicon. As depicted in Figure 1, the I-Eox curves from 5 capacitors fabricated over 5 different chips are shown. When electrical field is less than 6.3 MV/cm, the current is negligible. Moreover, as electrical field increases, electrical current also increases; this suggests that F-N tunneling could be the dominant mechanism. To prove that the transport mechanism is F-N tunneling, it is necessary plot log (JFN/Eox2) versus 1/Eox to obtain a straight line as shown in Figure 2.Figure 1
Measured tunneling current from five different capacitorsI versus E.Figure 2
F-N plotJ/E2 versus 1/E.The proposed floating gate transistor has a tunneling injector and a control gate (Figure3). In this device, considering negligible parasitic capacitances, the floating gate potential VFG (potential at FG node with respect to substrate) is approximately given by [8]
(2)VFG=C1CTVC+C2CTVtun,
where VC is the control gate voltage through C1 capacitor; Vtun is the voltage at the charge injector that couples to the floating gate through capacitor C2, and CT is the total capacitance of the floating gate.Topological design of an FGMOS transistor with a tunneling injector: top view and side view.
(a)
(b)For this case, the cell is designed with the conditionC1≫C2; thus, ratio C1/CT≈1. Hence, floating gate potential VFG is practically defined by control gate potential VC; that is, VFG≈VC.The F-N mechanism allows injecting or extracting electrons from the floating gate. As the potential difference between the floating gate and the charge injector is enough to achieve a critical electrical field, a current is established. The current density is theoretically characterized by the Fowler-Nordheim equation [2]:
(3)J=αE2exp⁡(-βE),
where J is the current density, E is the electrical field in the oxide, and α and β are technological constants. For simplicity, we assume that charge injector-floating gate structure is a parallel plate capacitor of area A separated by a distance d. Thus, the electric field in the injector is given by
(4)E=Voxd,
where Vox=Vtun-VFG. Considering that current tunneling is achieved through all the charge injector area, we can express (3) as follows:
(5)IFN=Aα(Voxd)2exp⁡(-βdVox),
where α and β are fit parameters which must be extracted experimentally from CMOS technology.In order to obtainα and β from experimental data, (5) must be linearized. Therefore, using natural logarithm in both sides, (5) is transformed to
(6)ln⁡(IFNVox2)=ln⁡(Ad2α)-βdVox.
This has the linear form
(7)y=k-βdx,
where
(8)y=ln⁡(IFNVox2),k=ln⁡(Ad2α),x=1Vox.
Thus, through the I-V characterization of poly1-poly2 injector, α and β can be extracted using linear fitting.


### 2.1. Parameter Extraction

Several testing poly1-poly2 capacitors were designed and fabricated on CMOS 0.5μm technology; these capacitors have an area A = 180 μm × 210 μm and d = 38.4 nm (Figure 4). The I-V curves from 40 capacitors were obtained using Keithley 2400 sourcemeters. The extracting methodology was accomplished with the arithmetic average of the I-V curves. The following values for α=86.51×10-12 A/V2 and β = 150.56 MV/cm were obtained; consequently, the F-N current expression is
(9)IFN=86.51×10-12(AV2)A(Voxd)2×exp⁡(-150.56×106(V/cm)dVox).
This expression brings a close approximation for the F-N current for a given poly1-poly2 tunneling injector with area A and distance d between plates.(a) Capacitor microphotograph. (b) Measuring equipment and testing structure.
(a)
(b)Only fiveI-V curves from different capacitors are shown for clarity in Figure 5; the average curve and the IFN model for the capacitors are also shown in the same plot. A good fitting among I-V measurements, average, and the proposed IFN model can be noticed.Figure 5
Five structures with F-N tunneling current, average curve, and F-N model using technological parameters.


## 2.1. Parameter Extraction

Several testing poly1-poly2 capacitors were designed and fabricated on CMOS 0.5μm technology; these capacitors have an area A = 180 μm × 210 μm and d = 38.4 nm (Figure 4). The I-V curves from 40 capacitors were obtained using Keithley 2400 sourcemeters. The extracting methodology was accomplished with the arithmetic average of the I-V curves. The following values for α=86.51×10-12 A/V2 and β = 150.56 MV/cm were obtained; consequently, the F-N current expression is
(9)IFN=86.51×10-12(AV2)A(Voxd)2×exp⁡(-150.56×106(V/cm)dVox).
This expression brings a close approximation for the F-N current for a given poly1-poly2 tunneling injector with area A and distance d between plates.(a) Capacitor microphotograph. (b) Measuring equipment and testing structure.
(a)
(b)Only fiveI-V curves from different capacitors are shown for clarity in Figure 5; the average curve and the IFN model for the capacitors are also shown in the same plot. A good fitting among I-V measurements, average, and the proposed IFN model can be noticed.Figure 5
Five structures with F-N tunneling current, average curve, and F-N model using technological parameters.


## 3. Memory Cell Design

The current-mode analog memory cell proposed in this paper stores charge onto the floating gate of MFG1 and MFG2 transistors in order to set a given current Imfg and Iout, (Figure 6). This current is stored permanently and results from the copy of an input current Iin by using a feedback loop. Thus, the stored charge can be read out as an analogue current from MFG2. Some important electrical characteristics of the cell are presented in Table 1.Table 1
Electrical values for the memory cell.
Electrical parameter
Value
V
DD1
3.3 V
V
DD2
8 V
C
1
1 pF
C
2
3 fF
C
par
360 fF
R
1, R2
1E99 Ω
MFG1,2
6μm/3 μm
M
1, M2, M4, M5
6μm/3 μm
M
3
30μm/1.5 μm
M
6, M9
12μm/6 μm
M
7, M8
30μm/6 μm
M
10
12μm/6 μ
M
11
60μm/6 μm
M
12
100μm/1.5 μm
I
bias
50μA
V
ref
1.5 V
V
b
1
3.3 V
V
read
0–3.3 VFigure 6
Analog current-mode memory cell.The operation of the storage cell is explained in three stages as follows.


### 3.1. Initialization

The capacitorC2 is set to an initial potential of Vtun = −25 V and transistor M12 must be turned on in order to lead Vc to ground. This condition Vc = 0 V sets VFG = 0 V through capacitor C1. As a result, Vox = −25 V enabling F-N tunneling current through poly1-poly2 capacitor C2. Consequently, electrons are injected to the FG causing a potential drop of VFG relative to ground, increasing the current Imfg from MFG1 transistor. This memory has been verified to store analogue current values in the range of 30 μA < Iout < 70 μA; therefore, the initial current condition must fulfill Imfg > 70 μA for a proper operation of the cell feedback loop.


### 3.2. Programming

The programming stage starts setting an input current valueIin, which will be stored in the cell permanently. A potential of Vtun= 25 V must be also established on C2 and transistor M12 must be turned off. The current to be stored is introduced by the current source Iin, where transistors M1, M2, and M3 act as a cascode current mirror with high output impedance at node “x.” Thus, node “x” will have high gain and since Imfg > Iin, the potential in this node will be close to VDD1. The comparator allows even a higher gain from node “x” and was considered in order to reduce the error of Iout/Iin. Moreover, this comparator allows an adjustable reference through Vref. The push-pull inverter brings a rail-to-rail output from the comparator output; indeed, this inverter has a VDD2 = 8 V whose output Vc is induced to the FG through capacitor C1.Thus, when voltage at node “x” is close toVDD1, the inverter brings Vc = 0 V which sets the FG also to 0 V, as mentioned above. This voltage difference between Vtun and VFG is greater than 24 V (Vox > 24 V); then, electron tunneling is achieved, which extracts electrons from the FG causing an increase on VFG. As a result, the current Imfg is decreased. Consequently, potential VFG rises until node “x” reaches Iin≈Imfg by the use of the feedback loop. When Iin is slightly greater than Imfg, the potential at node “x” drops to a value near ground; this causes a “high” output from the inverter, Vc = 8 V. This 8 V output of the circuit applied to C1 capacitor stops tunneling since now Vox < 24 V. This control loop makes this cell a novel design since only 8 V on-chip is necessary in order to stop tunneling with the feedback loop.Finally,Imfg current of MFG transistor will be equal to  Iin current, which is permanently stored by means of the stored charge in the FG.


### 3.3. Reading

Cell reading is performed under the following conditions:Vtun = 0 V and Vc = 0 V. For this purpose, transistor M12 must be turned on in order to lead Vc to ground. The output current Iout is a copy of Imfg and is obtained from the drain of transistor M4.


## 3.1. Initialization

The capacitorC2 is set to an initial potential of Vtun = −25 V and transistor M12 must be turned on in order to lead Vc to ground. This condition Vc = 0 V sets VFG = 0 V through capacitor C1. As a result, Vox = −25 V enabling F-N tunneling current through poly1-poly2 capacitor C2. Consequently, electrons are injected to the FG causing a potential drop of VFG relative to ground, increasing the current Imfg from MFG1 transistor. This memory has been verified to store analogue current values in the range of 30 μA < Iout < 70 μA; therefore, the initial current condition must fulfill Imfg > 70 μA for a proper operation of the cell feedback loop.


## 3.2. Programming

The programming stage starts setting an input current valueIin, which will be stored in the cell permanently. A potential of Vtun= 25 V must be also established on C2 and transistor M12 must be turned off. The current to be stored is introduced by the current source Iin, where transistors M1, M2, and M3 act as a cascode current mirror with high output impedance at node “x.” Thus, node “x” will have high gain and since Imfg > Iin, the potential in this node will be close to VDD1. The comparator allows even a higher gain from node “x” and was considered in order to reduce the error of Iout/Iin. Moreover, this comparator allows an adjustable reference through Vref. The push-pull inverter brings a rail-to-rail output from the comparator output; indeed, this inverter has a VDD2 = 8 V whose output Vc is induced to the FG through capacitor C1.Thus, when voltage at node “x” is close toVDD1, the inverter brings Vc = 0 V which sets the FG also to 0 V, as mentioned above. This voltage difference between Vtun and VFG is greater than 24 V (Vox > 24 V); then, electron tunneling is achieved, which extracts electrons from the FG causing an increase on VFG. As a result, the current Imfg is decreased. Consequently, potential VFG rises until node “x” reaches Iin≈Imfg by the use of the feedback loop. When Iin is slightly greater than Imfg, the potential at node “x” drops to a value near ground; this causes a “high” output from the inverter, Vc = 8 V. This 8 V output of the circuit applied to C1 capacitor stops tunneling since now Vox < 24 V. This control loop makes this cell a novel design since only 8 V on-chip is necessary in order to stop tunneling with the feedback loop.Finally,Imfg current of MFG transistor will be equal to  Iin current, which is permanently stored by means of the stored charge in the FG.


## 3.3. Reading

Cell reading is performed under the following conditions:Vtun = 0 V and Vc = 0 V. For this purpose, transistor M12 must be turned on in order to lead Vc to ground. The output current Iout is a copy of Imfg and is obtained from the drain of transistor M4.


## 4. PSpice Simulations and Experimental Results

### 4.1. Macromodel forItun Electrical Simulation

Spice is a world standard program for electrical circuit simulation. A macromodel is a combination of Spice models used for a special purpose device. Since F-N tunneling current is not modeled in Spice, the F-N expression is implemented as a macromodel with the use of a voltage-controlled current source (VCCS); that is,(10)G112VALUE={15[V(1)-V(2)]190.1e-9*[V(1)-V(2)]2*EXP{-578.15[V(1)-V(2)]}}R1121e99,
where “G” is associated with a voltage controlled current source and 1 and 2 are the nodes where the current source is connected. Node 1 represents external applied voltage Vtun which is ground referenced and node 2 represents the VFG. The “VALUE” parameter allows the implementation of (9) including the injector area of C2; in this case A = 1.8 μm × 1.8 μm and distance d = 38.4 nm. Additionally, a resistor R1 is included with a high value in order to improve simulation convergence. The VCCS G1 and R1 are shown in dashed line in Figure 6.


### 4.2.  Spice Electrical Cell Simulation

An electrical cell simulation using PSpice is shown in Figure7. The cell also includes resistor R2, which is used for improving convergence and helps the simulator to set the DC operation point at the floating gate. Furthermore, capacitor Cpar models the FG-substrate parasitic capacitor. In this case this capacitor can be calculated using the layer capacitance parameters given by the foundry and the injector area, in this case, has a value of Cpar = 360 fF. When an input current Iin = 70 μA is established on the cell, the initial output current is Imfg = 160 μA and after 40 s this output current drops to ~70 μA. At this point, VC rises to 8 V and F-N tunneling is stopped. Afterwards, at 50 s, the Vtun is removed and transistor M14 is turned on; this enables the readout current, Iout = 70.1 μA. The cell worked properly at the range 70 μA < Iout < 30 μA. The highest error, error = |Iout-Iin|, is obtained when current values are near 30 μA. It is important to notice that although a deviation in (9) could be present, only the cell convergence time to reach Iin≈Imfg would be affected by several seconds. A microphotograph of a chip is shown in Figure 8.Figure 7
Transient simulation of the analog memory cell for a 70μA input current.Memory cell microphotograph and layout.
(a)
(b)The measured relative error percentages for several programming input current values are shown in Figure9. The error calculation was considered using
(11)error%=|Iout-IinIin|×100.
From experimental data, the error is less than 5% in the range 70 μA < Iout < 50 μA. Therefore this is considered the working range of the cell. In Figure 10, the plot shows a set of five cells supplying currents between Iout = 60 μA to 65 μA over a long period of time. The charge retention of the floating gate has been confirmed by the measurements of the cells over 1000 minutes. In submicron technologies, gate leakage is well known [9]; thus, a constant measurement of the cell could show a change in the charge trend. Nevertheless, a further statistical analysis of this situation should be considered for periods ≫ 1000 min, since this could give important information about the usefulness of the cell, that is, reliability and refreshing cycles.Figure 9
Error percentage from output currentIout for several input current values Iin.Figure 10
Output currentIout in a time span of 1000 minutes.In Figure11, the graph shows ambient temperature measurement at the same time span. A correlational fluctuation of the current value is observed and caused by the ambient temperature. Considering ΔIout from Figure 10 and ΔT from Figure 11, the storage cell presents a temperature dependence of −221 nA/°C. Therefore, the stored charge onto the floating gate does not present a significant change at the same period of time.Figure 11
Ambient temperature variation.


## 4.1. Macromodel forItun Electrical Simulation

Spice is a world standard program for electrical circuit simulation. A macromodel is a combination of Spice models used for a special purpose device. Since F-N tunneling current is not modeled in Spice, the F-N expression is implemented as a macromodel with the use of a voltage-controlled current source (VCCS); that is,(10)G112VALUE={15[V(1)-V(2)]190.1e-9*[V(1)-V(2)]2*EXP{-578.15[V(1)-V(2)]}}R1121e99,
where “G” is associated with a voltage controlled current source and 1 and 2 are the nodes where the current source is connected. Node 1 represents external applied voltage Vtun which is ground referenced and node 2 represents the VFG. The “VALUE” parameter allows the implementation of (9) including the injector area of C2; in this case A = 1.8 μm × 1.8 μm and distance d = 38.4 nm. Additionally, a resistor R1 is included with a high value in order to improve simulation convergence. The VCCS G1 and R1 are shown in dashed line in Figure 6.


## 4.2.  Spice Electrical Cell Simulation

An electrical cell simulation using PSpice is shown in Figure7. The cell also includes resistor R2, which is used for improving convergence and helps the simulator to set the DC operation point at the floating gate. Furthermore, capacitor Cpar models the FG-substrate parasitic capacitor. In this case this capacitor can be calculated using the layer capacitance parameters given by the foundry and the injector area, in this case, has a value of Cpar = 360 fF. When an input current Iin = 70 μA is established on the cell, the initial output current is Imfg = 160 μA and after 40 s this output current drops to ~70 μA. At this point, VC rises to 8 V and F-N tunneling is stopped. Afterwards, at 50 s, the Vtun is removed and transistor M14 is turned on; this enables the readout current, Iout = 70.1 μA. The cell worked properly at the range 70 μA < Iout < 30 μA. The highest error, error = |Iout-Iin|, is obtained when current values are near 30 μA. It is important to notice that although a deviation in (9) could be present, only the cell convergence time to reach Iin≈Imfg would be affected by several seconds. A microphotograph of a chip is shown in Figure 8.Figure 7
Transient simulation of the analog memory cell for a 70μA input current.Memory cell microphotograph and layout.
(a)
(b)The measured relative error percentages for several programming input current values are shown in Figure9. The error calculation was considered using
(11)error%=|Iout-IinIin|×100.
From experimental data, the error is less than 5% in the range 70 μA < Iout < 50 μA. Therefore this is considered the working range of the cell. In Figure 10, the plot shows a set of five cells supplying currents between Iout = 60 μA to 65 μA over a long period of time. The charge retention of the floating gate has been confirmed by the measurements of the cells over 1000 minutes. In submicron technologies, gate leakage is well known [9]; thus, a constant measurement of the cell could show a change in the charge trend. Nevertheless, a further statistical analysis of this situation should be considered for periods ≫ 1000 min, since this could give important information about the usefulness of the cell, that is, reliability and refreshing cycles.Figure 9
Error percentage from output currentIout for several input current values Iin.Figure 10
Output currentIout in a time span of 1000 minutes.In Figure11, the graph shows ambient temperature measurement at the same time span. A correlational fluctuation of the current value is observed and caused by the ambient temperature. Considering ΔIout from Figure 10 and ΔT from Figure 11, the storage cell presents a temperature dependence of −221 nA/°C. Therefore, the stored charge onto the floating gate does not present a significant change at the same period of time.Figure 11
Ambient temperature variation.


## 5. Conclusions

In this work, a novel nonvolatile current-mode analog memory cell architecture is presented. A control loop is used with only 8V to stop F-N tunneling. This is a new approach that allows the use of standard circuitry internally in order to program nonvolatile analog cells on chip. Experimental results show that the cell presents a useful range of values with a maximum error of 5%. The functionality of the cell was analyzed through a long period of time (1000 min) and also temperature performance was analyzed.



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*Source: 632785-2014-02-23.xml*