# Six-Port-Based Architecture for Phase Noise Measurement in the UWB Band

Authors: J. M. Ávila-Ruiz; A. Moscoso-Mártir; E. Durán-Valdeiglesias; L. Moreno-Pozas; J. de-Oliva-Rubio; I. Molina-Fernández
Journal: Journal of Electrical and Computer Engineering
 (2014)

---

## Abstract

A six-port-based frequency discriminator for phase noise measurement is proposed. This circuit makes use of a delay line discriminator configuration, thus not requiring reference oscillator. Furthermore, the use of a six-port network allows an extremely simple and completely passive solution well suited for low power oscillator measurement. A detailed study of the architecture is performed including the system noise sources. Besides, a prototype of the proposed six-port based delay line frequency discriminator is evaluated. Phase noise measurements of a commercial RF VCO are performed and compared with the results obtained with commercial metrology equipment with good agreement.


---

## Body

## 1. Introduction

The high data rate transmission requirements of current radiofrequency standards demand efficient and robust modulation techniques. One of these modulation techniques is Orthogonal Frequency Division Multiplexing (OFDM), which is widely used in wireless communications due to its good performance against noise and multipath effects. On the other hand, OFDM receivers are very sensitive to local oscillator phase noise, which produces adjacent channel crosstalk due to reciprocal mixing [1, 2]. This adjacent channel crosstalk increases bit error rate (BER) [3, 4]. Phase noise effects in radiofrequency communications are the reason why feedback systems, such as phase locked loops (PLL), have been used for phase noise reduction for 80 years [5, 6]. Moreover, a great amount of new on chip low noise oscillators designs are carried out every year [7, 8].An outstanding issue, as important as the design of low phase noise oscillators, is the accurate measurement of their phase noise. Modern oscillators with low phase noise level require metrology systems with even more demanding specifications as well as measurement methods to compensate their limitations [2, 9]. Several methods have been defined for phase noise measurement, depending on the characteristics of the system to be measured. As a main distinction, these methods can be first classified depending on whether they require a reference oscillator or not. This differentiation is important, since reference oscillator phase noise will increase the noise floor of the measurement system. In order to increase the instrument sensitivity, ultralow phase noise reference oscillators are needed. Therefore, high performance systems that rely on reference oscillators are more expensive than other instrument systems.The group of phase noise measurement techniques that make use of a reference oscillator comprises the direct spectrum measurement and the PLL techniques. The direct spectrum measurement is the most straightforward method (Figure1(a)). The spectrum of the oscillator under test, from now on the device under test (DUT), can be directly measured with a spectrum analyzer or previously down-converted to an intermediate frequency (IF) using a reference oscillator and a mixer. The PLL method makes use of a mixer as a phase detector (Figure 1(b)). Then, the output of the phase detector is low-pass-filtered to eliminate the higher frequency terms, retaining only the baseband component. The phase noise of the DUT is extracted from the spectrum of the low-pass filtered output. In this method, a PLL is needed to lock the reference oscillator to the oscillator under test.Phase noise measurement methods with reference oscillator. (a) Direct downconversion method and (b) PLL method.
(a)
(b)The need of a reference oscillator is removed by the second group of phase noise measurement methods, which make use of a frequency discriminator. The most used one is the delay line frequency discriminator. A typical phase noise measurement system based on a delay line discriminator is shown in Figure2. This method makes use of a mixer-based phase detector, as in the aforementioned PLL method. However, in this architecture, the RF signal from the oscillator under test is compared in the phase detector with a delayed version of itself. A phase shifter must be included in order to keep the quadrature condition between both signals at the phase detector inputs [10]. Even though this method gets rid of the reference oscillator, it has an important drawback: the complex circuitry needed to control the phase shifter and keep the system into the quadrature condition.Figure 2
Delay line frequency discriminator method.Recently, a new architecture for phase noise measurement based on delay line discriminator has been proposed [11]. In this circuit, a dual phase detector architecture and a 90-degree hybrid allow the detection of the phase noise from the in-phase and quadrature (
I
/
Q
) signal components without quadrature adjustment. Even though this architecture needs neither reference oscillator nor quadrature adjustment circuitry, it has an important disadvantage: its input-referred phase noise floor considerably increases at lower input power levels [11]. A good solution to improve the phase noise measurement of this new architecture is the utilization of a six-port demodulator (see Figure 3). Six-port demodulators can work with low input power levels and their calibration has been widely studied [12]. The six-port architecture has been previously implemented in [13], for W-band phase noise measurements, but using a reference oscillator, obtaining good accuracy in phase noise measurement of one-port and two-port systems.Figure 3
Equivalence between [11] mixer architecture and classical six-port.The architecture proposed in this work makes use of the idea of dualI
/
Q phase noise detection based on a delay line discriminator [11] and the six-port architecture used in [13] in order to implement a compact phase noise measurement system. This architecture uses neither reference oscillator nor a phase shifter for quadrature adjustments. Moreover, the existence of powerful calibration strategies for six-port demodulators [12] and their good performance for low input power levels make the use of this structure advantageous against traditional mixers.The rest of this paper is organized as follows. In Section2, the six-port-based delay line discriminator architecture is described. In Section 3, the noise contributions and their effects are detailed. In Section 4, measurement setup and results are discussed. Finally, Section 5 is devoted to conclusions.


## 2. The Six-Port-Based Delay Line Discriminator

The proposed phase noise measurement architecture unifies the delay line method with the use of a six-port demodulator as a phase detector to measure the phase noise from the in-phase and quadrature signal components. The block diagram of the six-port-based delay line discriminator is shown in Figure4. This figure includes the noise sources, n
2
-, referred to the detector output, which will only be used in the noise analysis carried out in Section 3.Figure 4
Six-port-based delay line discriminator architecture.In order to analyze the system response in the phase noise detection, a RF input signal is considered. The time-domain signal is(1)
v
i
n
(
t
)
=
V
0
(
1
+
r
(
t
)
)
·
cos
(
ω
0
t
+
ϕ
(
t
)
)
,
where ϕ
(
t
) is the phase noise, r
(
t
) is the amplitude noise, V
0 is the rms voltage, and ω
0 is the microwave carrier frequency. Using phasor nomenclature, the rms complex envelope from (1) is
(2)
v
i
n
~
(
t
)
=
V
0
(
1
+
r
(
t
)
)
·
e
j
ϕ
(
t
)
.The relation between the time-domain signal and the complex envelope is(3)
v
i
n
(
t
)
=
ℛ
e
{
v
i
n
~
(
t
)
·
e
j
ω
0
t
}
.Assuming thatϕ
(
t
) and r
(
t
) are ergodic noise signals, and knowing that r
(
t
) is very small compared with V
0, the power of the RF signal is
(4)
P
i
n
=
v
i
n
~
(
t
)
v
i
n
~
*
(
t
)
=
|
v
i
n
~
(
t
)
|
2
=
|
V
0
|
2
.Now that the input signal has been defined, the six-port based delay line discriminator will be analyzed. In Figure4, it can be seen that the input RF signal is equally split in two halves. One half travels through a delay line before being fed in one of the inputs of the six-port receiver and the other one is directly sent to the second input of the receiver. If an ideal 3 dB power splitter and a lossless delay line are assumed, the time-domain complex envelopes at the six-port inputs are
(5)
v
A
~
(
t
)
=
v
i
n
~
(
t
)
2
,
v
B
~
(
t
)
=
v
i
n
~
(
t
-
τ
)
·
e
-
j
ω
0
τ
2
,
where τ is the delay of the line. For the sake of simplicity, the product ω
0
τ is defined as ϕ
0. This phase shift depends on the carrier frequency and is constant as long as ω
0 keeps constant. As the carrier frequency changes, this phase shift will change with a period of 1
/
τ Hertz.For the six-port block, an ideal passive network with four 90-degree hybrids and a 90-degree phase shift is used [14]. Therefore, insertion loss of 6 dB per path is considered and all S
i
j are balanced in amplitude and phase. With these assumptions, the signals at the six-port outputs are
(6)
v
1
~
(
t
)
=
1
2
·
(
v
A
~
(
t
)
+
v
B
~
(
t
)
)
,
(7)
v
2
~
(
t
)
=
1
2
·
(
v
A
~
(
t
)
-
v
B
~
(
t
)
)
,
(8)
v
3
~
(
t
)
=
1
2
·
(
v
A
~
(
t
)
+
j
·
v
B
~
(
t
)
)
,
(9)
v
4
~
(
t
)
=
1
2
·
(
v
A
~
(
t
)
-
j
·
v
B
~
(
t
)
)
.Using the concept of centers of the six-port architecture,q
i
=
-
S
i
2
/
S
i
1 [15], all expressions, (6) to (9), can be written together as
(10)
v
i
~
(
t
)
=
1
2
·
(
v
A
~
(
t
)
-
q
i
·
v
B
~
(
t
)
)
,
for
i
=
1
⋯
4
,
where the centres are q
1
=
1, q
2
=
-
1, q
3
=
j and q
4
=
-
j.The instantaneous voltage of each output is obtained from a diode power detector. Assuming square law detectors, the voltage at each power detector output is(11)
v
o
i
(
t
)
=
β
·
P
i
=
β
·
|
v
i
~
(
t
)
|
2
=
1
4
·
|
v
A
~
(
t
)
-
q
i
·
v
B
~
(
t
)
|
2
,
for
i
=
1
⋯
4
,
where β is the power detector sensitivity and P
i is the instantaneous power at the input of the detector i. It is supposed that the four detectors are identical; hence the same β is assumed for all of them. Equation (11) can be rewritten as
(12)
v
o
i
(
t
)
=
|
v
B
~
(
t
)
|
2
4
·
β
·
|
Γ
~
(
t
)
-
q
i
|
2
,
for
i
=
1
⋯
4
,
where Γ
~
(
t
) is a complex variable that relates the two input signals of the six-port, analogous to the received symbol in classical six-port based I
/
Q receivers [16]. This variable has the phase noise information in its phase as it can be seen in the following definition of Γ
~
(
t
):
(13)
Γ
~
(
t
)
=
v
A
~
(
t
)
v
B
~
(
t
)
=
1
+
r
(
t
)
1
+
r
(
t
-
τ
)
·
e
j
(
ψ
(
t
)
+
ϕ
0
)
,
where ψ
(
t
) is the instantaneous phase of  Γ
~
(
t
). For very small τ, ψ
(
t
) is proportional to the derivative of the input phase noise:
(14)
ψ
(
t
)
=
ϕ
(
t
)
-
ϕ
(
t
-
τ
)
≈
d
ϕ
(
t
)
d
t
τ
.If (12) is operated, knowing that |
q
i
|
2
=
1 for all i, the expression of the four outputs of the power divider is obtained:
(15)
v
o
1
(
t
)
=
|
v
B
~
(
t
)
|
2
4
·
β
·
(
1
+
|
Γ
~
(
t
)
|
2
+
2
·
ℛ
e
{
Γ
~
(
t
)
}
)
,
v
o
2
(
t
)
=
|
v
B
~
(
t
)
|
2
4
·
β
·
(
1
+
|
Γ
~
(
t
)
|
2
-
2
·
ℛ
e
{
Γ
~
(
t
)
}
)
,
v
o
3
(
t
)
=
|
v
B
~
(
t
)
|
2
4
·
β
·
(
1
+
|
Γ
~
(
t
)
|
2
-
2
·
ℐ
m
{
Γ
~
(
t
)
}
)
,
v
o
4
(
t
)
=
|
v
B
~
(
t
)
|
2
4
·
β
·
(
1
+
|
Γ
~
(
t
)
|
2
+
2
·
ℐ
m
{
Γ
~
(
t
)
}
)
.These outputs must be combined in order to obtain scaled versions of the in-phase and quadrature components ofΓ
~
(
t
):
(16)
I
(
t
)
=
v
o
1
(
t
)
-
v
o
2
(
t
)
=
|
v
B
~
(
t
)
|
2
·
β
·
ℛ
e
{
Γ
~
(
t
)
}
=
P
i
n
2
·
β
·
ℛ
e
{
Γ
~
(
t
)
}
,
(17)
Q
(
t
)
=
v
o
4
(
t
)
-
v
o
3
(
t
)
=
|
v
B
~
(
t
)
|
2
·
β
·
ℐ
m
{
Γ
~
(
t
)
}
=
P
i
n
2
·
β
·
ℐ
m
{
Γ
~
(
t
)
}
,
(18)
η
~
(
t
)
=
I
(
t
)
+
j
·
Q
(
t
)
=
P
i
n
2
·
β
·
Γ
~
(
t
)
,
where η
~
(
t
) is a complex variable proportional to Γ
~
(
t
) depicted in the complex plane in Figure 5. As the phase noise is measured from the phase shift of η
~
(
t
) and the amplitude noise only affects the module of this variable, as seen in (13), the phase noise measurement is independent of the AM noise of the DUT.Figure 5
Complex plane representation of the complex variableη
~
(
t
).The phase in both complex variables,η
~
(
t
) and Γ
~
(
t
), is the same, as shown in (18). Thus, it is straightforward to obtain the phase noise information from the phase of η
~
(
t
):
(19)
∢
η
~
(
t
)
=
ψ
(
t
)
+
ϕ
0
=
ϕ
(
t
)
-
ϕ
(
t
-
τ
)
+
ϕ
0
.If the DC component of (19), ϕ
0, is eliminated, a time variant phase signal is measured. This phase signal is proportional to the frequency fluctuations at the system input and can be represented in the frequency domain as a power spectral density:
(20)
S
ψ
ψ
(
f
)
=
PSD
(
ψ
(
t
)
)
.From (14), a relation between the power spectral density of ψ
(
t
) and the power spectral density of the phase noise, ϕ
(
t
), is obtained:
(21)
S
ϕ
ϕ
(
f
)
=
S
ψ
ψ
(
f
)
|
1
-
e
-
j
ω
τ
|
2
,
where ω is the angular frequency deviation from the RF carrier frequency and S
ϕ
ϕ
(
f
) is the power spectral density of the phase fluctuations, ϕ
(
t
). This relation can be simplified for ω
τ
≪
1. In this case, the exponential in (21) can be approximated by the first Taylor series expansion term; that is, e
-
j
ω
τ
≅
1
-
j
ω
τ, becoming
(22)
S
ϕ
ϕ
(
f
)
=
S
ψ
ψ
(
f
)
|
2
π
f
τ
|
2
.As can be seen in (22), the RF frequency variations in the system input can be detected in the six-port delay line discriminator output. In fact, the time-domain variation of the detected phase signal (∢
η
~
(
t
)) is proportional to the time-domain frequency variations of the RF oscillator under test. Thanks to the relation between phase and frequency, it is easy to obtain the phase fluctuations at the input from these frequency variations. The previous analysis has been carried out assuming lossless blocks. However, following [16], it can be shown that, assuming well balanced couplers and dividers, element losses do not affect the phase of η
~
(
t
). A more detailed analysis must be done if the imbalances of the different elements in the discriminator architecture are considered. Moreover, as it will be shown in Section 3, the losses of the system increase the noise floor of the system, partially degrading the sensitivity of this measurement method.


## 3. Noise Analysis

Although in the previous section the effects of the internal noise sources of the measurement setup have not been considered, this noise is an important factor to take into account. The internal noise limits the measurement system noise floor. The measurement system is passive, with the exception of the amplifiers used after the power detection and the digital processing circuitry. Therefore, two different noise sources are included in the analysis, depending on the noise origin: (i) the noise from the power detector (diode plus detection circuitry) and (ii) the noise generated in the data acquisition system. The rest of the noise sources (i.e., thermal noise due to losses in couplers and dividers) are negligible because at these components signal level is well over its thermal noise floor. All the noise sources are referred to the power detector output, as seen in Figure4, and their spectral power density is measured in V
2
/
Hz. Since both internal noises are uncorrelated, the total internal noise at each detector output is
(23)
n
T
,
i
2
-
=
n
DAQ
,
i
2
-
+
n
PD
,
i
2
-
,
for
i
=
1
⋯
4
,
where n
DAQ
,
i
2
- is the noise from each data acquisition channel and n
PD
,
i
2
- is the noise from each detection block. So, if the internal noise is included in the analysis, the signals at the detectors outputs are
(24)
v
o
i
(
t
)
=
P
i
n
8
·
β
·
(
1
+
|
Γ
~
(
t
)
|
2
-
2
·
ℛ
e
{
q
i
*
·
Γ
~
(
t
)
}
)
+
n
T
,
i
(
t
)
,
for
i
=
1
⋯
4
,
with q
i
=
1
,
-
1
,
j
,
-
j for i
=
1
⋯
4, respectively. It is assumed that the noise signals at every detector output are identical and uncorrelated; that is, n
T
,
i
2
-
=
n
2
- for all i. The in-phase and quadrature components of η
~
(
t
) defined in (16) and (17) are rewritten as
(25)
I
(
t
)
=
P
i
n
2
·
β
·
ℛ
e
{
Γ
~
(
t
)
}
+
2
·
n
(
t
)
,
Q
(
t
)
=
P
i
n
2
·
β
·
ℐ
m
{
Γ
~
(
t
)
}
+
2
·
n
(
t
)
.The noisy complex variableη
~
n
(
t
) is depicted in Figure 6. It can be seen how the aforementioned internal voltage noise sources, n
(
t
), generate a phase fluctuation ψ
n
(
t
) in the phase of η
~
n
(
t
). With the assumption of small angle, the arc of the angle ψ
n
(
t
) in the circumference of radius ρ can be approximated as 2
·
n
(
t
). Finally, the phase shift introduced by the internal noise is obtained calculating the angle of the arc as(26)
ψ
n
(
t
)
=
∢
η
~
n
(
t
)
=
2
·
n
(
t
)
(
β
·
P
i
n
)
/
2
.Figure 6
Influence of the internal noise inη
~
n
(
t
) degradation.Equation (26) can be expressed in power spectral densities as follows:
(27)
S
ψ
n
ψ
n
(
f
)
=
S
n
n
(
f
)
8
|
β
·
P
i
n
|
2
,
where S
ψ
n
ψ
n
(
f
) is the power spectral density of the phase fluctuations of η
~
n
(
t
) due to the internal noise and S
n
n
(
f
) is the power spectral density of the internal voltage noise referred to the power detector output.It can be seen from (27) that the noise contribution of the system depends on the input power and the sensitivity of the power detectors. Therefore, for higher input power level, the influence of the internal noise decreases.In order to know the limitations of the measurement method, it is necessary to obtain the minimum discernible value of phase noise at the system input, that is, the phase noise floor. This noise floor can be calculated by referring the power spectral density of the internal voltage noise,S
n
n
(
f
), which is usually referred at the detector output (as seen in Figure 4), to the system input. From (27), the relation between the power spectral density of the voltage noise at the detector output and the power spectral density of the phase fluctuations, S
ψ
n
ψ
n
(
f
), can be obtained. Then, with the help of (22), the phase noise floor can be calculated as
(28)
S
ϕ
n
ϕ
n
(
f
)
=
S
ψ
n
ψ
n
(
f
)
1
|
2
π
f
τ
|
2
=
S
n
n
(
f
)
8
|
β
·
P
i
n
|
2
·
1
|
2
π
f
τ
|
2
,
where S
ϕ
n
ϕ
n
(
f
) is the power spectral density of the input-referred phase noise floor, ϕ
n
(
t
).As shown in (28), the phase noise floor at the measurement system input can be improved in three ways: (i) increasing the gain of the system by using a larger delay line, with higher τ; (ii) increasing the input power and the sensitivity of the power detectors; and (iii) directly reducing the internal noise. The following subsection will be devoted to discussing the third option.


### 3.1. Internal Noise Reduction

As it is shown in (23), there are two important sources of internal noise. On the one hand, the noise generated in the data acquisition system depends on the number of quantification bits, the internal electronics, and the input voltage range. These characteristics are determined for each digital acquisition system. On the other hand, the noise generated by the power detection and baseband circuitry can be minimized if a deep analysis and a careful design and implementation of these blocks are performed. The schematic of the power detection and baseband circuitry used in this work is depicted in Figure 7.Figure 7
Power detection and baseband circuitry schematic.The resistancesR
f and R
s are the resistances of the amplifier and they set the amplifier gain, G. They are related as R
f
=
R
s
·
(
G
-
1
). For low frequencies, the matching network at the power detector input, with a shorted stub, works as a short circuit. Therefore, applying the operational amplifiers topologies noise analysis [17], the voltage noise at the output is
(29)
n
PD
2
-
=
4
K
T
0
(
R
f
+
R
V
G
)
G
+
i
n
2
(
(
R
V
G
)
2
+
R
f
2
)
+
(
e
n
G
)
2
,
where K is the Boltzmann constant, T
0 is the temperature (in Kelvin), R
V is the video resistance of the diode, and  i
n
2 and e
n
2 are the equivalent input current noise and the equivalent input voltage noise of the amplifier, respectively. If the approximation R
f
≪
R
V
G is fulfilled, (29) simplifies to
(30)
n
PD
2
-
≅
G
2
·
(
4
K
T
0
R
V
+
(
i
n
R
V
)
2
+
e
n
2
)
.From (30), it can be concluded that there are two important noise sources in this circuit (n
PD
2
-): the diode detector and the operational amplifier. The election of a diode with a lower video resistance (R
V) and the operational amplifiers with low equivalent current and voltage noise is one of the keys to minimize internal noise and, therefore, to reduce the noise floor of the measurement setup.


## 3.1. Internal Noise Reduction

As it is shown in (23), there are two important sources of internal noise. On the one hand, the noise generated in the data acquisition system depends on the number of quantification bits, the internal electronics, and the input voltage range. These characteristics are determined for each digital acquisition system. On the other hand, the noise generated by the power detection and baseband circuitry can be minimized if a deep analysis and a careful design and implementation of these blocks are performed. The schematic of the power detection and baseband circuitry used in this work is depicted in Figure 7.Figure 7
Power detection and baseband circuitry schematic.The resistancesR
f and R
s are the resistances of the amplifier and they set the amplifier gain, G. They are related as R
f
=
R
s
·
(
G
-
1
). For low frequencies, the matching network at the power detector input, with a shorted stub, works as a short circuit. Therefore, applying the operational amplifiers topologies noise analysis [17], the voltage noise at the output is
(29)
n
PD
2
-
=
4
K
T
0
(
R
f
+
R
V
G
)
G
+
i
n
2
(
(
R
V
G
)
2
+
R
f
2
)
+
(
e
n
G
)
2
,
where K is the Boltzmann constant, T
0 is the temperature (in Kelvin), R
V is the video resistance of the diode, and  i
n
2 and e
n
2 are the equivalent input current noise and the equivalent input voltage noise of the amplifier, respectively. If the approximation R
f
≪
R
V
G is fulfilled, (29) simplifies to
(30)
n
PD
2
-
≅
G
2
·
(
4
K
T
0
R
V
+
(
i
n
R
V
)
2
+
e
n
2
)
.From (30), it can be concluded that there are two important noise sources in this circuit (n
PD
2
-): the diode detector and the operational amplifier. The election of a diode with a lower video resistance (R
V) and the operational amplifiers with low equivalent current and voltage noise is one of the keys to minimize internal noise and, therefore, to reduce the noise floor of the measurement setup.


## 4. Simulation and Measurement Results

Simulations with the design environment Advanced Design System (ADS) from Agilent Technologies have been done. For these simulations, each functional block has been modeled depending on their nature. The power divider and the six-port have been characterized by full-vectorial 3D electromagnetic simulation using Ansys HFSS. In doing so, theirS parameters have been calculated. Then, they have been used to model both devices as multiport S parameters defined components into ADS circuit schematic. A 15 ns delay line (LabFlex290 coaxial cable) has been modeled from the manufacturer S parameters. These three blocks are passive and linear so they are fully defined from their S parameters. For the rest of the blocks, diodes and amplifiers, ADS models based on the manufacturer specifications have been used. The diode model is based on HSCH-9161 zero bias diode from Avago Tech. and the amplifier has been modeled from the specifications of LMH6622 amplifier from Texas Instrument.A prototype has been fabricated in order to assess the simulated results, which is shown in Figure8. The prototype comprises a Wilkinson power splitter with 3.4 dB insertion loss at 5 GHz, a 3.779 m LabFlex290 delay line from EMC-RFLabs with a delay of 15 ns and 1.5 dB insertion loss at 5 GHz, an ultrawideband six-port circuit with state-of-the-art characteristics in amplitude and phase imbalance [14], four power detector blocks that use a zero bias diode HSCH-9161 from Avago Technologies, and an operational amplifier LMH6622 from Texas Instruments. The gain of the amplifiers is set to 20 dB (10 V/V). The output of each power detector is sampled and digitalized with a data acquisition board NI-6115 from National Instruments.Figure 8
Six-port-based delay line frequency discriminator prototype.After the digitalization, the signals from the power detectors are processed with MatLab in order to obtain the phase noise spectrum. A simplified diagram of the mathematical process is shown in Figure9. To take advantage of the full dynamic range of the data acquisition board, two measurements are done, with DC and AC coupling, in order to get the DC component and the time-varying part of the I (16) and Q (17) signals. From these two measurements, the complete I
/
Q signals are built and the subsequent complex variable η
~
(
t
) is obtained from (18). From the phase of η
~
(
t
), the power spectral density is calculated with (20) and the phase noise power spectral density at the input is obtained applying the FFT, as described in (22). The applied FFT uses a rectangular window of 200 ms and a frequency rate of 10 MHz. These parameters are enough for the measurement of phase noise between 100 Hz and 1 MHz from the RF carrier. As the six-port junction imbalances are very low [14], no calibration is required and the I
/
Q signals are directly obtained by subtracting the corresponding power readings, as seen in (16) and (17).Figure 9
Phase noise power spectral density calculation algorithm.In this section, four measurements are shown. They are compared with simulation, theoretical calculations, and measurements using commercial instrumentation. The measurements are (i) the static response of the system, (ii) the internal noise, (iii) the dynamic response to a RF input signal with a frequency modulation, and (iv) phase noise measurement of a commercial RF oscillator.


### 4.1. Static Response

To characterize the static response, a slow carrier frequency sweep, between 5 and 5.2 GHz, is done. This sweep is repeated for input powers between −10 dBm and −4 dBm. The results of theI
/
Q diagrams are shown in Figure 10, for simulation and measurements. In both graphics and for a concrete input power, an amplitude difference between I and Q components that flatten the I
/
Q diagram can be seen. Besides, the module of the circle is not constant for different cycles. Both effects are because the system has not been calibrated.I
/
Q diagram for carrier frequency = [5, 5.2] GHz and Pin = [−10, −4]  dBm; (a) simulations and (b) measurements.
(a)
(b)


### 4.2. Internal Noise

The mathematical estimation of the internal noise has been separated in two parts, one for the power detector circuitry and one for the data acquisition system. The noise of the data acquisition board depends on the minimum voltage step,Δ
V, and this minimum step depends at the same time on the quantification bits and the voltage range of the board. The data acquisition board NI-6115 uses 12 bits of quantification and its minimum input voltage range is ±200 mV, so
(31)
Δ
V
=
0.4
2
12
=
97.7
μ
V
.The specified noise spectral density in the sampling board datasheet is(
1.3
·
Δ
V
)
2
/
f
s, where f
s is the sampling frequency. For NI-6115, f
s
=
10
MHz. Therefore, the board noise level is −147.9 dBV/Hz.The power detector circuitry noise is calculated from (30). For this block, R
f = 680 Ω and R
s = 33 Ω resistances have been used in the amplifier in order to achieve a 20 dB gain. The diode HSCH-9161 video resistance is R
V
=
3
k
Ω. The internal noise sources of the amplifier are e
n
=
1.6
nV
/
Hz and i
n
=
1.5
pA
/
Hz. From (30), the amplifier expected added noise is −136.5 dBV/Hz. Thus, noise limit is set by the power detector circuitry and can be estimated with (23) to a value of −136.5 dBV/Hz approximately.As it can be seen in Figure11, the measured total noise, at one data acquisition channel input, is 5 dB higher at 1 kHz (due to the effect of flicker noise) and 1 dB lower than the theoretically expected for frequency offsets higher than 100 kHz. The measured internal noise is approximately −137.5 dBV/Hz for the four channels.Figure 11
Internal noise, calculated and measured.


### 4.3. FM Demodulation

The dynamic characterization of the system is done by the detection of a frequency modulated RF signal. Using the N5181A vector signal generator from Agilent Technologies, a carrier of 5 GHz and −6 dBm is modulated with a frequency modulation,f
m, of 30 kHz and frequency deviation, Δ
f, of 100 kHz. This modulated RF signal is introduced in the six-port delay line discriminator. Since the main function of the system is the frequency fluctuations detection, a phase shift signal, ψ
(
t
), proportional to the baseband signal is expected. This phase shift signal is shown in Figure 12. It has a time period of 33 μs, so its frequency is 30 kHz as expected and its maximum phase deviation, Δ
ψ, is ±9.7 mrad. The proportionality factor of the system is
(32)
2
π
τ
=
94.25
rad
/
GHz
.Figure 12
FM demodulation of a signal withf
m
=
30
kHz and Δ
f
=
100
kHz.The calculation of the frequency deviation is as follows:(33)
Δ
f
(
MHz
)
=
Δ
ψ
(
2
π
τ
)
=
Δ
ψ
·
10.61
,
where Δ
ψ is the maximum phase deviation of η
~
(
t
). Therefore, for a Δ
ψ value of 9.7 mrad, the measured frequency deviation is 102.9 kHz, very close to the original 100 kHz.


### 4.4. Phase Noise Measurement

For the phase noise measurement, a voltage controlled oscillator (VCO) from HITTITE (HMC587LC4B) has been chosen as the device under test. This VCO features 4 dBm output power and it has an output carrier frequency range from 5 GHz to 10 GHz. Its phase noise is −95 dBc/Hz and −118 dBc/Hz for offset frequencies of 100 kHz and 1 MHz, respectively.Two different phase noise measurements have been performed for two different VCO output power levels. Hence, 6 dB and 10 dB attenuators have been used at the VCO output to change the VCO output power, obtaining −2 dBm and −6.6 dBm, respectively. The VCO output frequency has been set at 5 GHz. For both setups, the VCO phase noise has been measured with the prototype shown in Figure8 and with the signal source analyzer E5052B from Agilent technologies. The E5052B measurements have been performed using the internal PLL of the E5052B (that the E5052B uses in order to phase noise measure); an averaging factor of 20 and an IF gain of 50 dB have been used. For the measurements with the prototype, no PLL has been used (free running oscillator) and an averaging factor of 20 has been used.The results of the measurements for both configurations are depicted in Figures13 and 14. In each figure, the input-referred phase noise floor of the measurement system (voltage noise at the diode outputs referred to the input with (28)) is also plotted for comparison. The measurements results with the six-port delay line discriminator architecture (without calibration) are in very good agreement with the measurement results of commercial systems. Moreover, the proposed method is able to measure phase noise from sources with low carrier power without preamplification as well. Although the measurement system noise floor appears to be very high, as it can be seen in (28), it can be reduced using a longer delay line as it was done in [11].Figure 13
Phase noise measurements of a VCO from HITTITE-HMC587LC4B (P
i
n
=
-
6.6
dBm).Figure 14
Phase noise measurements of a VCO from HITTITE-HMC587LC4B (P
i
n
=
-
2
dBm).


## 4.1. Static Response

To characterize the static response, a slow carrier frequency sweep, between 5 and 5.2 GHz, is done. This sweep is repeated for input powers between −10 dBm and −4 dBm. The results of theI
/
Q diagrams are shown in Figure 10, for simulation and measurements. In both graphics and for a concrete input power, an amplitude difference between I and Q components that flatten the I
/
Q diagram can be seen. Besides, the module of the circle is not constant for different cycles. Both effects are because the system has not been calibrated.I
/
Q diagram for carrier frequency = [5, 5.2] GHz and Pin = [−10, −4]  dBm; (a) simulations and (b) measurements.
(a)
(b)


## 4.2. Internal Noise

The mathematical estimation of the internal noise has been separated in two parts, one for the power detector circuitry and one for the data acquisition system. The noise of the data acquisition board depends on the minimum voltage step,Δ
V, and this minimum step depends at the same time on the quantification bits and the voltage range of the board. The data acquisition board NI-6115 uses 12 bits of quantification and its minimum input voltage range is ±200 mV, so
(31)
Δ
V
=
0.4
2
12
=
97.7
μ
V
.The specified noise spectral density in the sampling board datasheet is(
1.3
·
Δ
V
)
2
/
f
s, where f
s is the sampling frequency. For NI-6115, f
s
=
10
MHz. Therefore, the board noise level is −147.9 dBV/Hz.The power detector circuitry noise is calculated from (30). For this block, R
f = 680 Ω and R
s = 33 Ω resistances have been used in the amplifier in order to achieve a 20 dB gain. The diode HSCH-9161 video resistance is R
V
=
3
k
Ω. The internal noise sources of the amplifier are e
n
=
1.6
nV
/
Hz and i
n
=
1.5
pA
/
Hz. From (30), the amplifier expected added noise is −136.5 dBV/Hz. Thus, noise limit is set by the power detector circuitry and can be estimated with (23) to a value of −136.5 dBV/Hz approximately.As it can be seen in Figure11, the measured total noise, at one data acquisition channel input, is 5 dB higher at 1 kHz (due to the effect of flicker noise) and 1 dB lower than the theoretically expected for frequency offsets higher than 100 kHz. The measured internal noise is approximately −137.5 dBV/Hz for the four channels.Figure 11
Internal noise, calculated and measured.


## 4.3. FM Demodulation

The dynamic characterization of the system is done by the detection of a frequency modulated RF signal. Using the N5181A vector signal generator from Agilent Technologies, a carrier of 5 GHz and −6 dBm is modulated with a frequency modulation,f
m, of 30 kHz and frequency deviation, Δ
f, of 100 kHz. This modulated RF signal is introduced in the six-port delay line discriminator. Since the main function of the system is the frequency fluctuations detection, a phase shift signal, ψ
(
t
), proportional to the baseband signal is expected. This phase shift signal is shown in Figure 12. It has a time period of 33 μs, so its frequency is 30 kHz as expected and its maximum phase deviation, Δ
ψ, is ±9.7 mrad. The proportionality factor of the system is
(32)
2
π
τ
=
94.25
rad
/
GHz
.Figure 12
FM demodulation of a signal withf
m
=
30
kHz and Δ
f
=
100
kHz.The calculation of the frequency deviation is as follows:(33)
Δ
f
(
MHz
)
=
Δ
ψ
(
2
π
τ
)
=
Δ
ψ
·
10.61
,
where Δ
ψ is the maximum phase deviation of η
~
(
t
). Therefore, for a Δ
ψ value of 9.7 mrad, the measured frequency deviation is 102.9 kHz, very close to the original 100 kHz.


## 4.4. Phase Noise Measurement

For the phase noise measurement, a voltage controlled oscillator (VCO) from HITTITE (HMC587LC4B) has been chosen as the device under test. This VCO features 4 dBm output power and it has an output carrier frequency range from 5 GHz to 10 GHz. Its phase noise is −95 dBc/Hz and −118 dBc/Hz for offset frequencies of 100 kHz and 1 MHz, respectively.Two different phase noise measurements have been performed for two different VCO output power levels. Hence, 6 dB and 10 dB attenuators have been used at the VCO output to change the VCO output power, obtaining −2 dBm and −6.6 dBm, respectively. The VCO output frequency has been set at 5 GHz. For both setups, the VCO phase noise has been measured with the prototype shown in Figure8 and with the signal source analyzer E5052B from Agilent technologies. The E5052B measurements have been performed using the internal PLL of the E5052B (that the E5052B uses in order to phase noise measure); an averaging factor of 20 and an IF gain of 50 dB have been used. For the measurements with the prototype, no PLL has been used (free running oscillator) and an averaging factor of 20 has been used.The results of the measurements for both configurations are depicted in Figures13 and 14. In each figure, the input-referred phase noise floor of the measurement system (voltage noise at the diode outputs referred to the input with (28)) is also plotted for comparison. The measurements results with the six-port delay line discriminator architecture (without calibration) are in very good agreement with the measurement results of commercial systems. Moreover, the proposed method is able to measure phase noise from sources with low carrier power without preamplification as well. Although the measurement system noise floor appears to be very high, as it can be seen in (28), it can be reduced using a longer delay line as it was done in [11].Figure 13
Phase noise measurements of a VCO from HITTITE-HMC587LC4B (P
i
n
=
-
6.6
dBm).Figure 14
Phase noise measurements of a VCO from HITTITE-HMC587LC4B (P
i
n
=
-
2
dBm).


## 5. Conclusions

In this work, a new phase noise measurement architecture has been proposed. This architecture makes use of a six-port frequency discriminator. This circuit is based on a delay line discriminator configuration, thus not needing a reference oscillator. Most of the elements of the proposed architecture are passive (only the baseband operational amplifiers need DC supply), highly reducing its power consumption. The use of a six-port in spite of RF mixers allows phase noise measurement of low power oscillators without RF amplification.A detailed study of the architecture has been performed including the system noise sources. Besides, the gain and sensitivity of the system have been calculated. In order to assess the proposed architecture, a prototype of the proposed six-port-based delay-line frequency discriminator has been fabricated. Several tests have been carried out to evaluate its performance. The phase noise of a commercial RF VCO has been measured and compared with the results obtained with a commercial phase noise measurement system. Even though no calibration algorithms have been used, the measured results of the proposed architecture are in good agreement with the commercial system ones, which show the validity of the proposed architecture for the characterization of RF VCOs.



---

*Source: 646738-2014-01-02.xml*