# Carrier-Based PWM Method to Reduce Common-Mode Voltage of Three-to-Five-Phase Indirect Matrix Converter

Authors: Rutian Wang; Xingjun Mu; Zhiqiang Wu; Lihui Zhu; Qiufeng Chen; Xue Wang
Journal: Mathematical Problems in Engineering
 (2016)

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## Abstract

In order to reduce the common-mode voltage (CMV) for three-to-five-phase indirect matrix converter (IMC), the CMV with the conventional modulation strategy is analyzed. A novel carrier-based PWM (CBPWM) method is proposed in this paper. The zero vectors in the inverter stage are assigned to the rectifier stage, equivalently, which are not considered in the inverter stage. The zero vectors are selected appropriately to ensure that the dc-link is connected to an input phase with the minimum absolute value, so that the larger CMV can be avoided. Then, the modulation signals are derived by the duty ratios, which are used to compare with the only one carrier signal and generate the gate pulses of switches. With the proposed method, the CMV is reduced effectively compared with the conventional modulation strategy. This method is analyzed and researched with a simulation model established by Matlab/Simulink. Simulation results are provided in detail to verify the feasibility and validity of the proposed method.


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## Body

## 1. Introduction

With the rapid development of the power electronic converter, the drive system gradually gets rid of the bound of the phase number. Multiphase drive system has received more and more attention [1–5], so that the multiphase matrix converter (MC) has been widely studied [6–11]. The three-to-five-phase direct matrix converter (DMC) was proposed in [7], and there are fifteen bidirectional switches connected in series; each output phase can connect with each input phase. However, this topology requires many power switches, multistep commutation, and complicated overvoltage protection circuits [12]. To avoid the above problems, a three-to-five-phase indirect matrix converter (IMC) topology, illustrated in Figure 1, has been researched to implement the AC-AC power converter. The benefits of three-to-five-phase IMC are similar to those of a three-to-five-phase DMC, such as no required large energy storage components, compact structure, bidirectional energy flow, unrestricted output frequency, a controllable input power factor, and a maximum voltage transfer ratio (VTR) of 0.7886 [7]. Moreover, it has additional advantages such as zero current safer commutation and less switching losses in the rectifier stage and less total number of power switches [11].Figure 1
The topology of three-to-five-phase IMC.However, the CMV between the motor neutral point and the ground is caused inevitably when the SVPWM strategy is applied to MC. Due to the switches operating at high switching frequencies, the CMV, with a high value ofdu/dt, will produce a strong impact action on the motor drive system. Meanwhile, it will excite stray capacitance and parasitic coupling capacitance to generate high-frequency leakage current. This leakage current will produce a strong electromagnetic interference (EMI) [13–15]. Meanwhile, the CMV may cause shaft voltage between the shaft and the bearing seat through the distributed capacitance existing in the gap between stator, rotor, air, and ground, so that the normal operation of motor devices will be affected. Therefore, it is particularly important to reduce the negative effects of CMV.At present, the research on control strategy to reduce CMV of the three-to-three-phase MC is relatively mature [14, 16–19], which is based on the mechanism of CMV. According to the amplitude-frequency characteristic of CMV, the low-pass filter with much smaller cut-off frequency than the switching frequency is applied in [16], so that the CMV is reduced. The high value of du/dt is suppressed in [17] by improving the topology of matrix converter, and the output voltage is not mutation. Instead of zero vectors, a pair of opposing active vectors is chosen in [18] to reduce CMV. The two smaller line voltages are selected in [14] to synthesize the dc-link voltage. The CMV and switching losses of IMC are both reduced, but the maximum VTR is limited to 0.5. Using three active vectors to synthesize the desired output voltage vector is proposed in [19]. Although the CMV of IMC is reduced, the maximum VTR is only 0.577.However, the research on CMV of the multiphase MC is relatively few. The zero vectors in the inverter stage are reselected based on SVPWM strategy in [20]. But it requires a complex sector combination and lookup tables.In view of the above problems, a carrier-based PWM (CBPWM) method is proposed in this paper to reduce the CMV of three-to-five-phase IMC. This method focuses on the reasonable distribution of the zero vectors in both stages, so that the value of CMV is reduced. And the switching losses of the inverter stage are decreased.


## 2. Topology and Modulation Principles of Three-to-Five-Phase IMC

### 2.1. Topology of Three-to-Five-Phase IMC

The topology of three-to-five-phase IMC is shown in Figure1. It consists of a rectifier stage with six bidirectional switches and a five-leg inverter stage with ten unidirectional switches. ua, ub, and uc and ia, ib, and ic are three-phase input voltages and input currents, respectively; uA, uB, uC, uD, and uE and iA, iB, iC, iD, and iE are five-phase output voltages and currents respectively. upn and ipn are the dc-link voltage and current, respectively. Lf and Cf are inductor and capacitor of input filter. The switches of the rectifier stage are denoted by using Skw (k∈a,b,c; w∈p,n), and those of the inverter stage are denoted by using Sjw (j∈A,B,C,D,E).


### 2.2. The Basic Principle of Conventional Modulation Strategy

For the rectifier stage, suppose the three input voltages are described by(1)ua=Uimcos⁡ωitub=Uimcos⁡ωit-2π3uc=Uimcos⁡ωit+2π3,where Uim and ωi are the amplitude and angular frequency of the input phase voltage, respectively. One period of input phase voltages is divided into twelve segments, as shown in Figure 2.Figure 2
Segment partition for input voltages.
(a)
Input three-phase voltages (b)
Input three line voltagesIn each segment, to obtain the maximum dc-link voltageupn, only two larger and positive line voltages are selected to synthesize upn [21]. Taking the input voltages in segment 1 as an example, then, the voltages uab and uac are selected, as shown in Figure 2(b). Thus, the average value of the dc-link voltage Upn can be expressed as(2)Upn=dδ·uab+dγ·uac,where dδ and dγ are duty ratios of voltages uab and uac, respectively, and satisfy the following constraints:(3)dδ+dγ=10≤dδ≤10≤dγ≤1.The local-averaged input currents are expressed as(4)iaibic=dδ+dγ-dδ-dγIpn,where Ipn is the local-averaged dc-link current of ipn. Combining (2), (3), and (4) with the condition of unit input power factor, the duty ratios are obtained by(5)dδ=TδTs=-ubuadγ=TγTs=-ucua,where Ts is the sampling period. Tδ and Tγ are action times of voltages uab and uac.Combining (2) and (5), the average value of the dc-link voltage is(6)Upn=3Uim22ua.Thus,Upn varies in each input segment. The respective minimum and maximum values of the average dc-link voltage are(7)Upnmin⁡=1.5UimUpnmax⁡=3Uim.According to the above analysis, the switching states in each segment and the corresponding duty ratios are shown in Table1.Table 1
The switching state and corresponding duty ratio in each segment.
Segment ON switch ⁢Modulated switches and duty ratios d δ d γ 1, 12 S a p S b n - u b / u a S c n - u c / u a 2, 3 S c n S b p - u b / u c S a p - u a / u c 4, 5 S b p S a n - u a / u b S c n - u c / u b 6, 7 S a n S c p - u c / u a S b p - u b / u a 8, 9 S c p S b n - u b / u c S a n - u a / u c 10, 11 S b n S a p - u a / u b S c p - u c / u bFor the five-leg inverter stage, assume the expected output voltages are described by(8)uA=Uomcos⁡ωotuB=Uomcos⁡ωot-2π5uC=Uomcos⁡ωot-4π5uD=Uomcos⁡ωot-6π5uE=Uomcos⁡ωot-8π5,where Uom and ωo are the amplitude and angular frequency of the output phase voltage, respectively.The distribution of output voltage space vector is shown in Figure3(a), which includes thirty active vectors and two zero vectors (U0(00000) and U31(11111), not shown in Figure 3(a)). Each vector is represented by the set (SA, SB, SC, SD, and SE), where Sk (k=A,B,C,D,E) is defined as(9)Sk=1,the upper switch of legkis ON state0,the lower switch of legkis ON state.Figure 3
Distribution and Generation of output voltage space vector.
(a)
Distribution of output voltage space vector (b)
Generation of output reference voltageThere are six adjacent vectors in each sector that can be used to synthesize the reference output voltage vector. However, in order to obtain the maximum output reference voltage, only two adjacent maximum vectorsUαL and UβL, and two medium vectors UαM and UβM, and zero vector U0 are selected [22], as shown in Figure 3(b).The reference output voltage vectorUref can be described by(10)Uref=dαLUαL+dαMUαM+dβLUβL+dβMUβM+d0U0,where(11)dαL=TαLTs=1sin⁡4π/5minvη·M+Lsin⁡π5-θvdαM=TαMTs=η·dαLdβL=TβLTs=1sin⁡4π/5minvη·M+Lsin⁡θvdβM=TβMTs=η·dβLd0v=T0vTs=1-dαL+dαM+dβL+dβM,where minv is the modulation index of the five-leg inverter stage, minv=Uom/Upn. θv is the angle between the vector Uref and the vector UαL. M=0.4. L=0.8cos⁡(π/5). TαL, TαM, TβL, and TβM and dαL, dαM, dβL, and dβM are action times and duty ratios of corresponding vector. η is the ratio of the medium and maximum vector in the same direction. In order to ensure the output voltage is sinusoidal waveform, the value of η should be equal to 1/2cos⁡(π/5).Suppose the output voltage is in sector I (θv=ωot, 0≤θv≤π/5), from (11), the sum of the duty ratios of the active vectors must be satisfied(12)dαL+dαM+dβL+dβM≤1.From (11) and (12), the following inequality can be obtained:(13)2sin⁡2/5π·Uom·cos⁡ωot-π/10Upn≤1.On the left of (13), when the numerator takes the maximum value and the denominator takes the minimum value, (13) should also be established. That is,(14)2sin⁡2/5π·UomUpnmin⁡≤1.From (7) and (14), the voltage transfer ratio (VTR) of the three-to-five-phase IMC is calculated as(15)VTR=UomUim≤0.7886.To obtain the sinusoidal input and output waveforms, the switching pattern should produce an effective combination of the rectifier and inverter switching states. The input voltages in segment 1 and output voltages in sector I are taken as an example; the duty ratios of switching states within one sampling period are obtained by (5) and (11):(16)dδαM=dδ·dαM;dδαL=dδ·dαLdδβM=dδ·dβM;dδβL=dδ·dβLdδ0v=dδ·d0vdγαM=dγ·dαM;dγαL=dγ·dαLdγβM=dγ·dβM;dγβL=dγ·dβLdγ0v=dγ·d0v.According to Figure3(b), for the first half of the switching period, the vectors of the five-leg inverter stage are switched by U0a→UβM→UαL→UβL→UαM→U0b, and in reverse for the second half for the symmetrical scheme. The switching sequence of the two stages is shown in Figure 4. The selection principle of zero vectors, U0a and U0b, is to ensure the least switching number in each sampling period. U0a,U0b∈U0,U31. According to (16), the action time of each switching state is t01=0.25dδ0vTs, t1=0.5dδβMTs, t2=0.5dδαLTs, t3=0.5dδβLTs, t4=0.5dδαMTs, t02=0.25d0vTs, t5=0.5dγαMTs, t6=0.5dγβLTs, t7=0.5dδαLTs, t8=0.5dγβMTs, and t03=0.5dγ0vTs. From Figure 4, the zero dc-link current commutation is achieved in the rectifier stage [21].Figure 4
The switching sequence of conventional modulation strategy.


### 2.3. Sector Transition Problem

The principle of the transition from one segment to the other adjacent segment is to ensure the least switching number.In the rectifier stage, The states of six switches in rectifier stage are represented by the set (Sap, San, Sbp, Sbn, Scp, and Scn), and Skw = 1 denotes that the switch Skw is ON state, and Skw = 0 denotes that the switch Skw is OFF state, where k∈a,b,c; w∈p,n. The switching sequence in segment 1 is uab(100100)→uac(100001)→uab(100100). In case of transit to segment 2, the switching sequence is uac(100001)→ubc(001001)→uac(100001). So, during the transition, the switch switches only once. From Figure 2(b), in case of transit from segment 2 to segment 3, the switch state remains unchanged. It is similar in other segments.In the inverter stage, the switching sequence in sector I isU31(11111)→U29(11101)→U25(11001)→U24(11000)→U16(10000)→U0(00000)→U16(10000)→  U24(11000)→U25(11001)→U29(11101)→U31(11111). In case of the transit to the sector II, the switching sequence is U31(11111)→U29(11101)→U28(11100)→U24(11000)→U8(01000)→U0(00000)→U8(01000)→  U24(11000)→U28(11100)→U29(11101)→U31(11111). The switching sequence in other sectors is similar to that described above.


## 2.1. Topology of Three-to-Five-Phase IMC

The topology of three-to-five-phase IMC is shown in Figure1. It consists of a rectifier stage with six bidirectional switches and a five-leg inverter stage with ten unidirectional switches. ua, ub, and uc and ia, ib, and ic are three-phase input voltages and input currents, respectively; uA, uB, uC, uD, and uE and iA, iB, iC, iD, and iE are five-phase output voltages and currents respectively. upn and ipn are the dc-link voltage and current, respectively. Lf and Cf are inductor and capacitor of input filter. The switches of the rectifier stage are denoted by using Skw (k∈a,b,c; w∈p,n), and those of the inverter stage are denoted by using Sjw (j∈A,B,C,D,E).


## 2.2. The Basic Principle of Conventional Modulation Strategy

For the rectifier stage, suppose the three input voltages are described by(1)ua=Uimcos⁡ωitub=Uimcos⁡ωit-2π3uc=Uimcos⁡ωit+2π3,where Uim and ωi are the amplitude and angular frequency of the input phase voltage, respectively. One period of input phase voltages is divided into twelve segments, as shown in Figure 2.Figure 2
Segment partition for input voltages.
(a)
Input three-phase voltages (b)
Input three line voltagesIn each segment, to obtain the maximum dc-link voltageupn, only two larger and positive line voltages are selected to synthesize upn [21]. Taking the input voltages in segment 1 as an example, then, the voltages uab and uac are selected, as shown in Figure 2(b). Thus, the average value of the dc-link voltage Upn can be expressed as(2)Upn=dδ·uab+dγ·uac,where dδ and dγ are duty ratios of voltages uab and uac, respectively, and satisfy the following constraints:(3)dδ+dγ=10≤dδ≤10≤dγ≤1.The local-averaged input currents are expressed as(4)iaibic=dδ+dγ-dδ-dγIpn,where Ipn is the local-averaged dc-link current of ipn. Combining (2), (3), and (4) with the condition of unit input power factor, the duty ratios are obtained by(5)dδ=TδTs=-ubuadγ=TγTs=-ucua,where Ts is the sampling period. Tδ and Tγ are action times of voltages uab and uac.Combining (2) and (5), the average value of the dc-link voltage is(6)Upn=3Uim22ua.Thus,Upn varies in each input segment. The respective minimum and maximum values of the average dc-link voltage are(7)Upnmin⁡=1.5UimUpnmax⁡=3Uim.According to the above analysis, the switching states in each segment and the corresponding duty ratios are shown in Table1.Table 1
The switching state and corresponding duty ratio in each segment.
Segment ON switch ⁢Modulated switches and duty ratios d δ d γ 1, 12 S a p S b n - u b / u a S c n - u c / u a 2, 3 S c n S b p - u b / u c S a p - u a / u c 4, 5 S b p S a n - u a / u b S c n - u c / u b 6, 7 S a n S c p - u c / u a S b p - u b / u a 8, 9 S c p S b n - u b / u c S a n - u a / u c 10, 11 S b n S a p - u a / u b S c p - u c / u bFor the five-leg inverter stage, assume the expected output voltages are described by(8)uA=Uomcos⁡ωotuB=Uomcos⁡ωot-2π5uC=Uomcos⁡ωot-4π5uD=Uomcos⁡ωot-6π5uE=Uomcos⁡ωot-8π5,where Uom and ωo are the amplitude and angular frequency of the output phase voltage, respectively.The distribution of output voltage space vector is shown in Figure3(a), which includes thirty active vectors and two zero vectors (U0(00000) and U31(11111), not shown in Figure 3(a)). Each vector is represented by the set (SA, SB, SC, SD, and SE), where Sk (k=A,B,C,D,E) is defined as(9)Sk=1,the upper switch of legkis ON state0,the lower switch of legkis ON state.Figure 3
Distribution and Generation of output voltage space vector.
(a)
Distribution of output voltage space vector (b)
Generation of output reference voltageThere are six adjacent vectors in each sector that can be used to synthesize the reference output voltage vector. However, in order to obtain the maximum output reference voltage, only two adjacent maximum vectorsUαL and UβL, and two medium vectors UαM and UβM, and zero vector U0 are selected [22], as shown in Figure 3(b).The reference output voltage vectorUref can be described by(10)Uref=dαLUαL+dαMUαM+dβLUβL+dβMUβM+d0U0,where(11)dαL=TαLTs=1sin⁡4π/5minvη·M+Lsin⁡π5-θvdαM=TαMTs=η·dαLdβL=TβLTs=1sin⁡4π/5minvη·M+Lsin⁡θvdβM=TβMTs=η·dβLd0v=T0vTs=1-dαL+dαM+dβL+dβM,where minv is the modulation index of the five-leg inverter stage, minv=Uom/Upn. θv is the angle between the vector Uref and the vector UαL. M=0.4. L=0.8cos⁡(π/5). TαL, TαM, TβL, and TβM and dαL, dαM, dβL, and dβM are action times and duty ratios of corresponding vector. η is the ratio of the medium and maximum vector in the same direction. In order to ensure the output voltage is sinusoidal waveform, the value of η should be equal to 1/2cos⁡(π/5).Suppose the output voltage is in sector I (θv=ωot, 0≤θv≤π/5), from (11), the sum of the duty ratios of the active vectors must be satisfied(12)dαL+dαM+dβL+dβM≤1.From (11) and (12), the following inequality can be obtained:(13)2sin⁡2/5π·Uom·cos⁡ωot-π/10Upn≤1.On the left of (13), when the numerator takes the maximum value and the denominator takes the minimum value, (13) should also be established. That is,(14)2sin⁡2/5π·UomUpnmin⁡≤1.From (7) and (14), the voltage transfer ratio (VTR) of the three-to-five-phase IMC is calculated as(15)VTR=UomUim≤0.7886.To obtain the sinusoidal input and output waveforms, the switching pattern should produce an effective combination of the rectifier and inverter switching states. The input voltages in segment 1 and output voltages in sector I are taken as an example; the duty ratios of switching states within one sampling period are obtained by (5) and (11):(16)dδαM=dδ·dαM;dδαL=dδ·dαLdδβM=dδ·dβM;dδβL=dδ·dβLdδ0v=dδ·d0vdγαM=dγ·dαM;dγαL=dγ·dαLdγβM=dγ·dβM;dγβL=dγ·dβLdγ0v=dγ·d0v.According to Figure3(b), for the first half of the switching period, the vectors of the five-leg inverter stage are switched by U0a→UβM→UαL→UβL→UαM→U0b, and in reverse for the second half for the symmetrical scheme. The switching sequence of the two stages is shown in Figure 4. The selection principle of zero vectors, U0a and U0b, is to ensure the least switching number in each sampling period. U0a,U0b∈U0,U31. According to (16), the action time of each switching state is t01=0.25dδ0vTs, t1=0.5dδβMTs, t2=0.5dδαLTs, t3=0.5dδβLTs, t4=0.5dδαMTs, t02=0.25d0vTs, t5=0.5dγαMTs, t6=0.5dγβLTs, t7=0.5dδαLTs, t8=0.5dγβMTs, and t03=0.5dγ0vTs. From Figure 4, the zero dc-link current commutation is achieved in the rectifier stage [21].Figure 4
The switching sequence of conventional modulation strategy.


## 2.3. Sector Transition Problem

The principle of the transition from one segment to the other adjacent segment is to ensure the least switching number.In the rectifier stage, The states of six switches in rectifier stage are represented by the set (Sap, San, Sbp, Sbn, Scp, and Scn), and Skw = 1 denotes that the switch Skw is ON state, and Skw = 0 denotes that the switch Skw is OFF state, where k∈a,b,c; w∈p,n. The switching sequence in segment 1 is uab(100100)→uac(100001)→uab(100100). In case of transit to segment 2, the switching sequence is uac(100001)→ubc(001001)→uac(100001). So, during the transition, the switch switches only once. From Figure 2(b), in case of transit from segment 2 to segment 3, the switch state remains unchanged. It is similar in other segments.In the inverter stage, the switching sequence in sector I isU31(11111)→U29(11101)→U25(11001)→U24(11000)→U16(10000)→U0(00000)→U16(10000)→  U24(11000)→U25(11001)→U29(11101)→U31(11111). In case of the transit to the sector II, the switching sequence is U31(11111)→U29(11101)→U28(11100)→U24(11000)→U8(01000)→U0(00000)→U8(01000)→  U24(11000)→U28(11100)→U29(11101)→U31(11111). The switching sequence in other sectors is similar to that described above.


## 3. CMV Analysis in Three-to-Five-Phase IMC

The principle of CMV when a five-phase AC motor is driven by the three-to-five-phase IMC is shown in Figure5. ZNO is the leakage impedance between the load neutral point and the ground. The paths of CMV and leakage current are represented by the dashed line in Figure 5. Then, the equations can be obtained by KVL:(17)uAO-uNO=RiA+LdiA/dtuBO-uNO=RiB+LdiB/dtuCO-uNO=RiC+LdiC/dtuDO-uNO=RiD+LdiD/dtuEO-uNO=RiE+LdiE/dt,where uAO, uBO, uCO, uDO, and uEO are voltages between output phases and the ground. R and L are the equivalent resistance and inductance of the AC motor. Under the condition of sinusoidal and symmetrical output waveforms, the sum of output currents is equal to zero iA+iB+iC+iD+iE=0. From (17), The CMV uNO can be expressed as(18)uNO=uAO+uBO+uCO+uDO+uEO5.According to the above analysis, it can be seen that the CMV is generated inevitably between the motor neutral point and the ground, when the motor is driven by five-phase converter. Different peak value of CMV is generated due to the different switching combinations, when the conventional modulation strategies in [11, 22] are applied. According to the basic principle of the conventional modulation strategy, taking the input voltage in segment 1 and the reference output voltage vector in sector I as an example, when the dc-link voltage is uab and the vector U25(11001) is used in the five-leg inverter stage, the output phases “A,” “B,” and “E” are connected to “p” pole of dc-side (input phase “a”); “C” and “D” are connected to “n” pole of dc-side (input phase “b”). Combining (18), The CMV generated at this time is calculated by uNO=(3ua+2ub)/5, the value range of which is [3Uim/10, 33Uim/10]. Thus, the peak value of CMV is 33/10 times of the amplitude of input phase voltage. Other cases are similar to the above. The distribution of CMV at each switching combination is shown in Table 2. Similarly, the same method can be used to analyze the CMV of other sector combinations.Table 2
Distribution and variation of the CMV.
udc Vector u N O Ranges Peak value ofuNO uab U 0(00000) u b [-3Uim/2,0] 3 U i m / 2 U 16(10000) (ua+4ub)/5 [-33Uim/10,3Uim/10] 3 3 U i m / 10 U 24(11000) (2ua+3ub)/5 [-3Uim/10,3Uim/5] 3 U i m / 5 U 25(11001) (3ua+2ub)/5 [3Uim/10,33Uim/10] 3 3 U i m / 10 U 29(11101) (4ua+ub)/5 [33Uim/10,13Uim/5] 13 U i m / 5 U 31(11111) u a [3Uim/2,Uim] U i m  uac U 0(00000) u c [-3Uim/2,0] 3 U i m / 2 U 16(10000) (ua+4uc)/5 [-33Uim/10,3Uim/10] 3 3 U i m / 10 U 24(11000) (2ua+3uc)/5 [-3Uim/10,3Uim/5] 3 U i m / 5 U 25(11001) (3ua+2uc)/5 [3Uim/10,33Uim/10] 3 3 U i m / 10 U 29(11101) (4ua+uc)/5 [33Uim/10,13Uim/5] 13 U i m / 5 U 31(11111) u a [3Uim/2,Uim] U i mFigure 5
Generation of CMV and leakage current.From Table2, the peak value of CMV is the amplitude of input phase voltage when the zero vector U31 is used in the five-leg inverter stage. Then, the dc-link is connected to an input phase with the maximum absolute value. The CMV, the peak value of which is equal to Uim, is generated.


## 4. The CBPWM Method with CMV Reduction

By analyzing the switching sequence in Figure4, the zero vectors in the inverter stage are assigned to the rectifier stage, equivalently, which are not considered in the inverter stage. Thus, the dc-link voltage is synthesized by two larger line voltages and a zero voltage, which can be selected according to the absolute value of the input phase voltage. When the input voltage is in segments 1, 2, 7, and 8, the zero voltage ubb is selected; the voltage uaa is used in segments 3, 4, 9, and 10; and in segments 5, 6, 11, and 12, ucc is used. The input voltage in segment 1 and the reference output voltage vector in sector I are taken as an example; the switching sequence is shown in Figures 6(a) and 6(b).Figure 6
The switching sequence and generation of gate pulses by using the improved modulation strategy.In terms of the change rate of CMV, the CMV is changed 16 times within one sampling period by using the improved modulation strategy. While it is 22 times and 18 times when using two zero vectors and one zero vector, respectively, under conventional modulation strategies.According to (16), the action time of each switching state in Figure 6 is t1=0.5dδβMTs, t2=0.5dδαLTs, t3=0.5dδβLTs, t4=0.5dδαMTs, t5=0.5dγαMTs, t6=0.5dγβLTs, t7=0.5dγαLTs, t8=0.5dγβMTs, and t0=0.5d0vTs.In the rectifier stage, when the switching states are switched, the active vectors are used in the inverter stage. Thus, the commutation mode should be applied appropriately to ensure the safe commutation of switches in the rectifier stage.According to the above analysis and Table2, the peak value of CMV is not more than 13Uim/5, so that it can be reduced to 13/5 of the amplitude of the input phase voltage.The modulation strategy is realized by complex division and combination of sectors, which is similar to the SVPWM strategy. In order to simplify the process, only one symmetrical triangular carrier signal is applied in this paper, which is described as(19)uc=4Tst-1,0≤t≤Ts2,where uc is the instantaneous value of the carrier signal.


### 4.1. Rectifier Stage Control

Figure6(d) shows the principle to generate gate pulses for the rectifier stage. The two modulation signals u1 and u2 in Figure 6(c) are used to generate the gate pulses for rectifier stage. The two pulses S1 and S2 in Figure 6(d) are obtained by comparing two modulation signals to the carrier signal. The gate pulses for switches Sap, Sbp, Sbn, and Scn are calculated by(20)Sap=S2Sbp=S-2Sbn=S-1Scn=S1.The gate pulses for other switches are San=0 and Scp=0. The switching sequence for the rectifier stage, shown in Figure 6(a), is obtained by (20) and Figure 6(d).From Figures6(a) and 6(c), the durations T1 and T2 can be derived as(21)T1=dαM+dβL+dαL+dβM·dδ·Ts2T2=dαM+dβL+dαL+dβM·Ts2.Combining (19) and (21), two modulation signals are obtained by(22)u1=2dδuA-uDUpn-1u2=2uA-uDUpn-1.In other segments, the two modulation signals are similar to (22). In different input segments, they can be written as(23)ur1=2dδumax-uminUpn-1ur2=2umax-uminUpn-1,where ur1 and ur2 are two modulation signals for the rectifier stage. umax=max⁡(uA,uB,uC,uD,uE) and umin=min⁡(uA,uB,uC,uD,uE).


### 4.2. Inverter Stage Control

In Figure6(b), because the zero vectors are not considered in the inverter stage, the switches SAp and SDn keep ON state, while SAn and SDp keep OFF state within each sampling period in sector I, so that the switches of phases “B,” “C,” and “E” are modulated. In order to generate the gate pulse for the upper switch of each phase, two modulation signals are needed. Figure 6(e) shows the principle to generate the gate pulse for switch SE when the CBPWM method is used in the inverter stage. The two modulation signals, urE1 and urE2, are used to generate the gate pulse for the upper switch of phase “E,” which is shown in Figure 6(c). The pulses SE1 and SE2 are obtained by comparing two modulation signals, urE1 and urE2, respectively, with the symmetrical triangular signal uc. Then, the pulse SE for switch SEp is shown in Figure 6(e). It is obtained by XOR function:(24)SE=SE1·SE2+S-E1·S-E2.The switching sequence for output phase “E” is obtained by (24) and Figure 6(e).From Figures6(b) and 6(c), the durations TE1 and TE2 can be derived as(25)TE1=dβM+dαL·dδ·Ts2TE2=dβM+dαL+dβL+dαM·dδ+dαM+dβL·dγ·Ts2.Combining (19) and (25), two modulation signals are obtained by(26)urE1=2dδuE-uDUpn-1urE2=2uA-uDUpn-uE-uDUpndγ-1.The two modulation signals of other phases are similar to (22) as well as in other sectors. Generally, the double modulation signals to generate gate pulse for the upper switch of phase “X” (X∈A,B,C,D,E) in the inverter stage are given by(27)urX1=2dδuX-uminUpn-1urX2=2umax-uminUpn-uX-uminUpndγ-1,where urX1 and urX2 are two modulation signals of phase “X” and uX is output voltage of phase “X”.In the inverter stage, the gate pulse of the lower switch of each phase has a complementary relationship with that of the upper switch. However, in the different sectors, the switches which keep ON state or OFF state continuously are different. Thus, the different modulation signals are needed, as shown in Table3.Table 3
Switching states and modulation signals in each sector.
Sector ON state switches OFF state switches Modulation signals I S A p, SDn S A n, SDp u B 1, uB2, uC1, uC2, uE1, uE2 II S B p, SDn S B n, SDp u A 1, uA2, uC1, uC2, uE1, uE2 III S B p, SEn S B n, SEp u A 1, uA2, uC1, uC2, uD1, uD2 IV S C p, SEn S C n, SEp u A 1, uA2, uB1, uB2, uD1, uD2 V S C p, SAn S C n, SAp u B 1, uB2, uD1, uD2, uE1, uE2 VI S D p, SAn S D n, SAp u B 1, uB2, uC1, uC2, uE1, uE2 VII S D p, SBn S D n, SBp u A 1, uA2, uC1, uC2, uE1, uE2 VIII S E p, SBn S E n, SBp u A 1, uA2, uC1, uC2, uD1, uD2 IX S E p, SCn S E n, SCp u A 1, uA2, uB1, uB2, uD1, uD2 X S A p, SCn S A n, SCp u B 1, uB2, uD1, uD2, uE1, uE2


## 4.1. Rectifier Stage Control

Figure6(d) shows the principle to generate gate pulses for the rectifier stage. The two modulation signals u1 and u2 in Figure 6(c) are used to generate the gate pulses for rectifier stage. The two pulses S1 and S2 in Figure 6(d) are obtained by comparing two modulation signals to the carrier signal. The gate pulses for switches Sap, Sbp, Sbn, and Scn are calculated by(20)Sap=S2Sbp=S-2Sbn=S-1Scn=S1.The gate pulses for other switches are San=0 and Scp=0. The switching sequence for the rectifier stage, shown in Figure 6(a), is obtained by (20) and Figure 6(d).From Figures6(a) and 6(c), the durations T1 and T2 can be derived as(21)T1=dαM+dβL+dαL+dβM·dδ·Ts2T2=dαM+dβL+dαL+dβM·Ts2.Combining (19) and (21), two modulation signals are obtained by(22)u1=2dδuA-uDUpn-1u2=2uA-uDUpn-1.In other segments, the two modulation signals are similar to (22). In different input segments, they can be written as(23)ur1=2dδumax-uminUpn-1ur2=2umax-uminUpn-1,where ur1 and ur2 are two modulation signals for the rectifier stage. umax=max⁡(uA,uB,uC,uD,uE) and umin=min⁡(uA,uB,uC,uD,uE).


## 4.2. Inverter Stage Control

In Figure6(b), because the zero vectors are not considered in the inverter stage, the switches SAp and SDn keep ON state, while SAn and SDp keep OFF state within each sampling period in sector I, so that the switches of phases “B,” “C,” and “E” are modulated. In order to generate the gate pulse for the upper switch of each phase, two modulation signals are needed. Figure 6(e) shows the principle to generate the gate pulse for switch SE when the CBPWM method is used in the inverter stage. The two modulation signals, urE1 and urE2, are used to generate the gate pulse for the upper switch of phase “E,” which is shown in Figure 6(c). The pulses SE1 and SE2 are obtained by comparing two modulation signals, urE1 and urE2, respectively, with the symmetrical triangular signal uc. Then, the pulse SE for switch SEp is shown in Figure 6(e). It is obtained by XOR function:(24)SE=SE1·SE2+S-E1·S-E2.The switching sequence for output phase “E” is obtained by (24) and Figure 6(e).From Figures6(b) and 6(c), the durations TE1 and TE2 can be derived as(25)TE1=dβM+dαL·dδ·Ts2TE2=dβM+dαL+dβL+dαM·dδ+dαM+dβL·dγ·Ts2.Combining (19) and (25), two modulation signals are obtained by(26)urE1=2dδuE-uDUpn-1urE2=2uA-uDUpn-uE-uDUpndγ-1.The two modulation signals of other phases are similar to (22) as well as in other sectors. Generally, the double modulation signals to generate gate pulse for the upper switch of phase “X” (X∈A,B,C,D,E) in the inverter stage are given by(27)urX1=2dδuX-uminUpn-1urX2=2umax-uminUpn-uX-uminUpndγ-1,where urX1 and urX2 are two modulation signals of phase “X” and uX is output voltage of phase “X”.In the inverter stage, the gate pulse of the lower switch of each phase has a complementary relationship with that of the upper switch. However, in the different sectors, the switches which keep ON state or OFF state continuously are different. Thus, the different modulation signals are needed, as shown in Table3.Table 3
Switching states and modulation signals in each sector.
Sector ON state switches OFF state switches Modulation signals I S A p, SDn S A n, SDp u B 1, uB2, uC1, uC2, uE1, uE2 II S B p, SDn S B n, SDp u A 1, uA2, uC1, uC2, uE1, uE2 III S B p, SEn S B n, SEp u A 1, uA2, uC1, uC2, uD1, uD2 IV S C p, SEn S C n, SEp u A 1, uA2, uB1, uB2, uD1, uD2 V S C p, SAn S C n, SAp u B 1, uB2, uD1, uD2, uE1, uE2 VI S D p, SAn S D n, SAp u B 1, uB2, uC1, uC2, uE1, uE2 VII S D p, SBn S D n, SBp u A 1, uA2, uC1, uC2, uE1, uE2 VIII S E p, SBn S E n, SBp u A 1, uA2, uC1, uC2, uD1, uD2 IX S E p, SCn S E n, SCp u A 1, uA2, uB1, uB2, uD1, uD2 X S A p, SCn S A n, SCp u B 1, uB2, uD1, uD2, uE1, uE2


## 5. Simulation Results

In order to verify the feasibility of the proposed CBPWM method, the simulation model of three-to-five-phase IMC is established based on Matlab/Simulink. The parameters of the simulation model are shown in Table4. The simulation results are shown in Figures 7 and 8.Table 4
The simulation parameters for the simulation model.
Parameters Value Input voltage (line-to-line RMS) 2203 V Input frequency 50 Hz Input filter R f = 0.2 Ω, Lf=0.2 mH, Cf=30 μF Switching frequency 10 kHz (Ts=1×10-4 s) Output frequency 25 Hz Voltage transfer ratio VTR = 0.75 Five-phaseR-L load R = 20 Ω, L=30 mHFigure 7
Input and output waveforms and FFT analysis.
(a)
Input voltage and current of phase “a” (b)
Output adjacent line-to-line voltageuAB (c)
FFT analysis ofuAB (d)
Output five-phase currentFigure 8
Waveforms of CMV.
(a)
The CMV of conventional modulation strategy (b)
The CMV of the proposed CBPWM methodFigure7 contains the simulation waveforms of the input voltage ua and input current ia, output line-to-line voltage uAB, FFT analysis of uAB, and five-phase output current. From Figure 7(a), the input current ia becomes almost sinusoidal waveform due to theLC filter. However, theLC filter causes the displacement angle between the input voltage and current at the power supply. From Figures 7(b) and 7(c), the output line-to-line voltage does not contain the low-order harmonic, and the output currents are sinusoidal waveforms in Figure 7(d). It can be confirmed that the sinusoidal output voltages and input currents are obtained by using proposed CBPWM method.Figure8 shows the CMV waveforms with the conventional modulation strategies, proposed in [11, 22], and the proposed CBPWM method, respectively. Obviously, the peak value of CMV in Figure 8(a) is 311 V which is equal to the amplitude of input phase voltage. And the peak value of CMV in Figure 8(b) is equal to about 224 V, which is 72% (about 13/5) of the amplitude of input phase voltage. In other words, by using the proposed CBPWM method, the CMV is reduced by 28%. It is consistent with the theoretic analysis above.


## 6. Conclusion

In this paper, a CBPWM method to reduce CMV of three-to-five-phase IMC is proposed. To ensure the dc-link is connected to an input phase with the minimum absolute value, the zero vectors are selected and arranged reasonably. Thus, the peak value of CMV can be reduced effectively, which is13/5 times of the amplitude of input phase voltage. The method is implemented by using only one symmetrical triangular carrier signal, which is simple and avoids the complexity of sector combination and lookup tables. Due to the zero vector is assigned to the rectifier stage, the switching times as well as the switching losses are reduced. The correctness of the theoretical analysis is verified by simulation.



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*Source: 6086497-2016-11-29.xml*