# Intermediate Frequency Digital Receiver Based on Multi-FPGA System

Authors: Chengchang Zhang; Lihong Zhang
Journal: Journal of Electrical and Computer Engineering
 (2016)

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## Abstract

Aiming at high-cost, large-size, and inflexibility problems of traditional analog intermediate frequency receiver in the aerospace telemetry, tracking, and command (TTC) system, we have proposed a new intermediate frequency (IF) digital receiver based on Multi-FPGA system in this paper. Digital beam forming (DBF) is realized by coordinated rotation digital computer (CORDIC) algorithm. An experimental prototype has been developed on a compact Multi-FPGA system with three FPGAs to receive 16 channels of IF digital signals. Our experimental results show that our proposed scheme is able to provide a great convenience for the design of IF digital receiver, which offers a valuable reference for real-time, low power, high density, and small size receiver design.


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## Body

## 1. Introduction

In the field of aerospace TTC system, a ground station is mostly used to capture and track aerial vehicles with the aid of a large high gain narrow beam. Such a searching and tracking process works when the angle error detector of an antenna servo system can detect the angle error (including azimuth error and pitch error) between laser gyroscope inertial axis and antenna axis. After amplification and certain operations, this angle error signal can drive a servo motor to make the electric antenna axis aim at the laser gyroscope inertial axis so as to realize automatic tracking to the aircraft [1, 2]. This traditional method is mainly based on analog devices and technologies, which lead to some major disadvantages, for example, expensive laser gyroscope and large-size turntable antenna.With the advancement of digital devices and digital signal processing technology, a new concept of digital array radar (DAR), which can perfectly combine digital technology and antenna technology, emerges to adopt DBF to replace the traditional analog beam forming in both transmitting and receiving mode [3–5]. The key techniques of DAR mainly include digital transmitter and receiver (T/R) module, multichannel digital receiving, high speed and large capacity data transmission, wide band DBF, and high performance software signal processing. Multichannel digital receiver is the core of DAR because of its high hardware/software complexity, high integration, and high performance index.Taking into account the strict requirements for DAR regarding correct identification of amplitude and phase between multiple receivers, DBF receiver adopts the thought of software defined radio (SDR) [6–8]. The central idea of SDR is to construct an open, standardized, and modular platform, which will use software to accomplish modulation and demodulation functions. And the bandwidth of the high speed broadband analog to digital converter (A/D) is highly close to the receiver or even to the antenna. The basic structures of SDR can be roughly divided into three types: radio frequency (RF) low pass sampling, RF band pass sampling, and IF band pass sampling.In order to improve the selectivity, suppress out-band interferences, and reduce the processing rate of the subsequent signal processor, radars usually adopt the IF band pass sampling, which is an IF digital receiver usually adopting super heterodyne system [9]. Since the sampling takes place directly in intermediate frequency, the subsequent processing can all be handled in the digital form. This will overcome the shortcomings of the traditional receivers that are based on analog devices and analog signal processing technique, such as gain variation, DC temperature drift, and nonorthogonality between I and Q. Therefore, the stability and consistency can be significantly improved.With the development and application of wideband high resolution radar, the bandwidth of digital receivers gets increasingly wider, and the sampling rate is increasingly higher. The design of wideband IF digital receivers is more complicated than that of the narrow band IF digital receivers [10–13], which are mainly reflected in the following aspects:(1)
With the increase of sampling data rate, the follow-up signal processing speed cannot be kept up with. In addition, the high data rate also leads to the problems of high speed data transmission and data synchronization.(2)
Combinational frequency interference within a receiver is greatly increased. Therefore, an optimized design considering a variety of factors (e.g., the working frequency, low phase noise, low spurious frequency source, and electromagnetic compatibility) is highly essential.(3)
RF front-end analog circuits of a receiver inevitably have amplitude and phase discordance, especially for the wideband receivers. In addition, there is inconsistency of the channel frequency response, which would affect the side lobe level, the output signal to noise ratio (SNR), or zero depth of adaptive beam forming. Therefore, the channel equalizer [14, 15] must be adopted for correction.It can be seen that the multiple channel digital receivers based on DBF are much more complex than the traditional ones. As a matter of fact, a DBF receiver may include many channels, even up to thousands of channels. However, there exist some stringent requirements for the receiver size and weight of airborne radar, space borne radar, or other radars.To resolve the abovementioned problems, in this paper we propose a DAR receiver based on Multi-FPGA system [16], which can provide a large number of digital I/O to meet the need of digital receivers for digital interface. The high speed parallel processing capability based on Multi-FPGA hardware, mature IP cores, and digital processing technology can greatly facilitate the design of our digital receiver, making it feasible for real-time application with the features of low power consumption, high density, and physical size miniaturization.Our contributions of this work lie in the following aspects:(1)
We propose that the multichannel ADC output digital signal is directly connected to FPGA, and the multichannel digital down conversion (DDC) is also realized in FPGA. This method is simpler, cheaper, and more flexible compared to using the programmable digital down converter ASIC chip, such as GC4016 or AD6654. This improvement is especially significant for digital array receivers with hundreds of channels.(2)
Based on the principle and analysis of digital beam forming, we propose and implement CORDIC algorithm scheme for digital beam forming in FPGA.(3)
We realize our digital receiver scheme of circular array with 16 channels in a Multi-FPGA system. This Multi-FPGA system comprises 3 pieces of FPGA: two FPGAs are directly connected with the digital signal output from ADC, while the third FPGA is to implement DBF and terminal display driver.


## 2. Analysis for Array Antenna

Array antenna is a synthetic antenna composed of a plurality of radiating elements, which generates a strong direction radiation. Antenna array has two forms, one is a line array [17] where all the elements of the array are arranged in a straight line; the other is a planar array [18] where all the array elements are arranged on a plane. An array element might be a simple weak directional antenna, such as dipole, half wave dipole, and waveguide slot, or might be a more complex antenna, such as parabolic antenna and Yaga antenna. The array antenna forms narrow directivity beam, whose performance is determined by position, amplitude, and phase of the radiating elements. Figure 1 shows the geometric relationship of array antenna elements.Figure 1
Geometry of array antenna.Let us assume an element is located atP1(x1,y1,z1) and the phase reference point is O(0,0,0). The electric field strength measured at the far field point P is(1)Eθ,ϕ=I0e-jkR1R1fθ,ϕ,where I0 is the complex amplitude, k is the wave number that equals 2π/λ, and f(θ,ϕ) is the radiation pattern.Considering that the radiation source is composed of a number of array elements, the coordinate of any elementPi is (xi,yi,zi) and the vector from point O to Pi is(2)ri=a→xxi+a→yyi+a→zzi,where a→x, a→y, and a→z are unit vectors of axes x, y, and z, respectively.The far field component of the total electric field is(3)Eiθ,ϕ=Iie-jkRiRifθi,ϕi,where Ii is the complex amplitude and f(θi,ϕi) is the radiation pattern. Ri can be represented as follows:(4)Ri=x-xi2+y-yi2+z-zi2=r1+xi2+yi2+zi2r2-2xxi+yyi+zzir2,where x=rsin⁡θcos⁡ϕ, y=rsin⁡θsin⁡ϕ, z=rcos⁡θ, and (5)xi2+yi2+zi2r2=ri2r2≪1.Based on binomial expansion, a better estimate for (4) is obtained using(6)Ri=r-rxisin⁡θcos⁡ϕ+yisin⁡θsin⁡ϕ+zicos⁡θ.Relative to the reference point, the phase contribution ofPi in the far field is(7)e-jkRi=e-jkrejkxisin⁡θcos⁡ϕ+yisin⁡θsin⁡ϕ+zicos⁡θ.The unit vector along the directionr is r0 as shown in the following equation:(8)r0=a→xsin⁡θcos⁡ϕ+a→ysin⁡θsin⁡ϕ+a→zcos⁡θ.Thus, (7) can be rewritten as(9)e-jkRi=e-jkrejkri·r0=e-jkrejψiθ,ϕ.For an equal amplitude excitation array, the radiation pattern of each array element is isotropic. Without loss of generality, we can assumef(θ,ϕ)=1. Thus, the total electric field is(10)Eθ,ϕ=∑i=1NIiejψiθ,ϕ.This is called the matrix factor expression. Iff(θ,ϕ) is equal to another value, only the coefficient of the expression changes, and the amplitude of the composed beam is changed to another value. However, this will not affect the shape and direction of the beam.


## 3. CORDIC-Based DBF

### 3.1. Model of DBF

Although each element pattern of antenna array is omnidirectional, the array’s direction gain can be gathered in the direction of the desired signal by weighting the sampled data of each channel, which is equivalent to forming a high gain beam in the desired direction. The principle of selecting the weighting coefficients is to make the output signal maximal.As shown in Figure2, DBF for an array of M elements is achieved by adjusting the weighting coefficient of each element, the output of the array is the weighted sum of each component from the received signal vector x(n). Let the weighting vector be W=[W1,…,WM]T; the output can be written as(11)yn=WHxn=∑m=1MWM∗XMn,where superscript ∗ represents complex conjugate.Figure 2
Structure of DBF.Under narrowband model, the signal amplitude of each element at any instant is the same. Equation (11) can be realized only by adjusting weighting coefficient of phase shifter, which is only for signal phase, without a need for changing signal amplitude. If there is only one signal from direction θk and guidance vector is a(θk), then y(n)=aH(θk)a(θk)=M when weighting vector w is equal to a(θk). This is the largest, which is used to achieve the role of oriented positioning. At this time, the weights of the various signals are for the same phase superposition, which is also for the spatial matching filter.


### 3.2. DBF Module Based on CORDIC Algorithm [19]

Let the signal received by theith array element be(12)Xi=xIi+jxQi.The complex weighting coefficient is(13)wi=wIi+jwQi=exp⁡jαi.The output after complex weighted is(14)Xi′=xIi′+jxQi′=xIi+jxQi∗exp⁡-jαi,where(15)αi=2πrλsin⁡θcos⁡ϕ-φi=12πcosπ2-θ+ϕ-φi+cosπ2-θ-ϕ+φi,φi=2i-1πN,i=1,2,…,N.Through the conversion above, it can be seen that the complex weighting operation for each channel can be implemented by using three CORDIC algorithm modules: two cosine operations and one rotating module. Figure3 depicts a single channel complex weighting module schematic.Figure 3
Single complex weighting module.In order to track target, we need to do parallel addition operation forI and Q signals, get total output XΣ′=xIΣ′+jxQΣ′, and then use the vector mode of CORDIC algorithm to obtain XΣ′ as shown in Figure 4.Figure 4
DBF module.The operations above can be implemented by configuring CORDIC IP core in FPGA.


### 3.3. IF Digital Receiver in FPGA

Based on the realization scheme for DBF on top of CORDIC algorithm, we can construct the IF digital array radar receiver by combining it with A/D conversion and digital down conversion (DDC) [20]. A simplified block diagram of IF digital array radar receiver is shown in Figure 5.Figure 5
Block diagram of IF digital receiver.


## 3.1. Model of DBF

Although each element pattern of antenna array is omnidirectional, the array’s direction gain can be gathered in the direction of the desired signal by weighting the sampled data of each channel, which is equivalent to forming a high gain beam in the desired direction. The principle of selecting the weighting coefficients is to make the output signal maximal.As shown in Figure2, DBF for an array of M elements is achieved by adjusting the weighting coefficient of each element, the output of the array is the weighted sum of each component from the received signal vector x(n). Let the weighting vector be W=[W1,…,WM]T; the output can be written as(11)yn=WHxn=∑m=1MWM∗XMn,where superscript ∗ represents complex conjugate.Figure 2
Structure of DBF.Under narrowband model, the signal amplitude of each element at any instant is the same. Equation (11) can be realized only by adjusting weighting coefficient of phase shifter, which is only for signal phase, without a need for changing signal amplitude. If there is only one signal from direction θk and guidance vector is a(θk), then y(n)=aH(θk)a(θk)=M when weighting vector w is equal to a(θk). This is the largest, which is used to achieve the role of oriented positioning. At this time, the weights of the various signals are for the same phase superposition, which is also for the spatial matching filter.


## 3.2. DBF Module Based on CORDIC Algorithm [19]

Let the signal received by theith array element be(12)Xi=xIi+jxQi.The complex weighting coefficient is(13)wi=wIi+jwQi=exp⁡jαi.The output after complex weighted is(14)Xi′=xIi′+jxQi′=xIi+jxQi∗exp⁡-jαi,where(15)αi=2πrλsin⁡θcos⁡ϕ-φi=12πcosπ2-θ+ϕ-φi+cosπ2-θ-ϕ+φi,φi=2i-1πN,i=1,2,…,N.Through the conversion above, it can be seen that the complex weighting operation for each channel can be implemented by using three CORDIC algorithm modules: two cosine operations and one rotating module. Figure3 depicts a single channel complex weighting module schematic.Figure 3
Single complex weighting module.In order to track target, we need to do parallel addition operation forI and Q signals, get total output XΣ′=xIΣ′+jxQΣ′, and then use the vector mode of CORDIC algorithm to obtain XΣ′ as shown in Figure 4.Figure 4
DBF module.The operations above can be implemented by configuring CORDIC IP core in FPGA.


## 3.3. IF Digital Receiver in FPGA

Based on the realization scheme for DBF on top of CORDIC algorithm, we can construct the IF digital array radar receiver by combining it with A/D conversion and digital down conversion (DDC) [20]. A simplified block diagram of IF digital array radar receiver is shown in Figure 5.Figure 5
Block diagram of IF digital receiver.


## 4. Simulation for 16-Element Circular Array DBF

As shown in Figure6, in thex-o-y plane, N isotropic radiation elements are evenly distributed on the circle with radius of R, N=16.Figure 6
Illustration of circular array.Here(16)ϕn=2πNn,n=1,2,…,16.The coordinates ofnth elements are(17)xn=Rcos⁡ϕn,yn=Rsin⁡ϕn,zn=0.So,(18)krn·r0=ψn=kRsin⁡θcos⁡ϕcos⁡ϕn+Rsin⁡θsin⁡ϕsin⁡ϕn+0=Rksin⁡θcos⁡ϕcos⁡ϕn+sin⁡ϕsin⁡ϕn=Rksin⁡θcos⁡ϕn-ϕ.According to (10),(19)Eθ,ϕ=∑n=1NInexp⁡j2πλRsin⁡θcos⁡ϕn-ϕ,where In is the complex current of nth element. For equal amplitude excitation, we have In=1. When the array main beam points at (θ0,ϕ0), (19) can be expressed as follows:(20)Eθ,ϕ=∑n=1NInexp⁡j2πλRsin⁡θcos⁡ϕn-ϕ-sin⁡θ0cos⁡ϕn-ϕ0.According to (20), circular pattern can scan in both θ and ϕ directions. For convenient observation and analysis, we make θ and ϕ constant separately. We first letθ be a constant;θ=45°, θ0=60°, and R/λ = 1 : 1; the simulation results are shown in Figure 7. The solid lines represent the pattern of ϕ0=30°, and the dashed lines represent the pattern of ϕ0=45°.Figure 7
Pattern of 16-element circular array. (a) Normalized Cartesian coordinates. (b) Normalized polar diagram. (θ=45°, θ0=60°, R/λ = 1 : 1, and ϕ0 = 30°(—)/45°(- - -)).
(a) (b)Then we letϕ be a constant; ϕ=45°, ϕ0=30°, and R/λ = 1 : 1. Figure 8 shows the array pattern from our simulation.Figure 8
Pattern of 16-element circular array. (a) Normalized Cartesian coordinates. (b) Normalized polar diagram. (ϕ=45°, ϕ0=30°, R/λ = 1 : 1, and θ0 = 30°(- - -)/45°(—)).
(a) (b)The following can be observed from (20) and our simulation results:(1)
The beam of circular array can point at the specified direction in two dimensions, which can be used to distinguish the direction of a target, that is, the circular array has resolution with two dimensions, which can also distinguish the elevation and azimuth.(2)
Sinceθ is a constant in Figure 7, with the increase of ϕ, the beam width remains unchanged. That is to say, in the range of 0°≤ϕ≤360°, the resolution capability of the circular array is the same. Therefore, the circular array beam can be scanned in one direction, and the amplitude of the signal is the same.(3)
From Figure8 where ϕ is a constant, the larger the value of θ is, the wider the width of the beam gets. This means that the ability for the circular array to distinguish a target will be reduced.


## 5. Experimental Verification

### 5.1. Multi-FPGA System Structure

The hardware design of the IF digital array radar receiver includes circuit board design and multiple FPGAs configuration control program design. OrCAD and PADS are used in printed circuit board (PCB) design, while ISE is used in our control program design.Our developed Multi-FPGA system consists of three Spartan 3 FPGAXC3S2000FGG456, one CPLD XC9572, and one Prom XCF32p. XC3S2000 is a high density and low cost FPGA with 2 M logic gates, up to 326 MHz clock frequency, embedded by forty18×18 multipliers. The system structure is shown in Figure 9.Figure 9
The diagram of Multi-FPGA system.The interconnection between three FPGAs is 8-way topology [16], where the interconnection pin numbers are 24 between FPGA1 and FPGA2, 50 between FPGA1 and FPGA3, and 50 between FPGA2 and FPGA3. There are 20 receiving IF branches, among which 16 are used to receive 16 channels sampling signal and the remaining 4 channels are spare. FPGA1 receives the first to the eighth channel IF sampling digital signals, while FPGA2 receives the ninth to the sixteenth channel IF sampling digital signals. The eight IF signals’ DDC is realized in FPGA1 in parallel and the digital baseband signal is sent to FPGA3. Similarly, FPGA2 completes another 8 parallel IF signals’ digital down conversion and the digital baseband signal is also sent to FPGA3. The operation of DBF is completed in FPGA3, which also operates display driver program and handles DBF result display on screen. The XC9572 plus XCF32p architecture is to complete the three FPGAs configuration. XCF32p is a 32 M flash memory, which can be divided into four 8 M segments for configuring four FPGAs in order to reduce the number of used flash memory chips. The chip configuration control program is stored in CPLD XC9572. All of the FPGA, flash memory, and CPLD chips are products from XILINX, which can simplify our system design thanks to the use of the same JTAG interface and software.


### 5.2. Layer Division Scheme of PCB

In order to minimize the adverse effects of circuit design on the performance of the system and to ensure the requirements of high frequency and high speed, the electronic components in our PCB design were manually placed and routed, with a thorough consideration of electromagnetic compatibility. Our developed PCB has 8 layers, whose arrangement is listed in Table1. The PCB board is illustrated in Figure 10.Table 1
The layer assignment of PCB.
Symbol Description (1) Top Element layer (2) GND/CLK Analog ground/clock (3) S2 Signal layer (4) P1 Power layer (5) SGND Digital ground (6) S3 Signal layer (7) P2 Power layer (8) Bottom Element layerFigure 10
The snapshot of our developed PCB.


### 5.3. Field Experiments and Results

We conducted field experiments with our developed IF digital receiver. The receiving antenna array was a circular array, which included 16 array elements. The beacon was a monopole antenna, which spread signals. The antenna array searched the target, determined the target’s range, and formed a strong beam in the direction of the target. One terminal screen displayed the beam to thereby complete the target searching and locating.Test conditions and parameters are listed in Table2. As a good trade-off between experimental effects and prototyping cost, the receiver antenna array was determined to be a 16-element circular array with the array element of monopole antenna.Table 2
Test description.
Description Value Array form Circular array Sum of array elements 16 Array element Monopole antenna RF frequency 1032 MHz IF frequency 70 MHzSinglecarrier Sampling frequency 66 MHz Beamforming direction ϕThe received radio frequency (RF) for antenna array was 1032 MHz, which is in L band. IF signal frequency after RF-analog conversion was 70 MHz, and the sampling frequency of IF signal was 66 MHz. The size of the verification site in our field experiment was about 200 meters × 200 meters.Antenna array, analog conversion channel, and the receiving circuit board were placed in the middle of the experiment site, which is shown in Figure11(a). The beacon was placed at the edge of the site, which is shown in Figure 11(b). Due to the high position of the antenna array and the fixed beacon, θ is a fixed value. The radio frequency signal was transmitted by the beacon, and the receiver received the signal, formed the DBF beam, and pointed to the direction of the beacon, which is shown in Figure 11(c). When moving the position of the beacon during our experiments, which is equivalent to changing ϕ, the direction of the DBF beam was also moving along with the beacon. These field experiments have confirmed a great success for our developed algorithmic scheme and the implemented prototype.Figure 11
Experiment results. (a) Verification platform. (b) The beacon. (c) The formed beam.
(a) (b) (c)In this work, we are only focused on the circular array digital receiver scheme. If the antenna is arranged as a linear array, the digital receiver DBF waveform shall point to the target in a specific direction with a certainθ or ϕ value. But the entire design would become much simpler.


## 5.1. Multi-FPGA System Structure

The hardware design of the IF digital array radar receiver includes circuit board design and multiple FPGAs configuration control program design. OrCAD and PADS are used in printed circuit board (PCB) design, while ISE is used in our control program design.Our developed Multi-FPGA system consists of three Spartan 3 FPGAXC3S2000FGG456, one CPLD XC9572, and one Prom XCF32p. XC3S2000 is a high density and low cost FPGA with 2 M logic gates, up to 326 MHz clock frequency, embedded by forty18×18 multipliers. The system structure is shown in Figure 9.Figure 9
The diagram of Multi-FPGA system.The interconnection between three FPGAs is 8-way topology [16], where the interconnection pin numbers are 24 between FPGA1 and FPGA2, 50 between FPGA1 and FPGA3, and 50 between FPGA2 and FPGA3. There are 20 receiving IF branches, among which 16 are used to receive 16 channels sampling signal and the remaining 4 channels are spare. FPGA1 receives the first to the eighth channel IF sampling digital signals, while FPGA2 receives the ninth to the sixteenth channel IF sampling digital signals. The eight IF signals’ DDC is realized in FPGA1 in parallel and the digital baseband signal is sent to FPGA3. Similarly, FPGA2 completes another 8 parallel IF signals’ digital down conversion and the digital baseband signal is also sent to FPGA3. The operation of DBF is completed in FPGA3, which also operates display driver program and handles DBF result display on screen. The XC9572 plus XCF32p architecture is to complete the three FPGAs configuration. XCF32p is a 32 M flash memory, which can be divided into four 8 M segments for configuring four FPGAs in order to reduce the number of used flash memory chips. The chip configuration control program is stored in CPLD XC9572. All of the FPGA, flash memory, and CPLD chips are products from XILINX, which can simplify our system design thanks to the use of the same JTAG interface and software.


## 5.2. Layer Division Scheme of PCB

In order to minimize the adverse effects of circuit design on the performance of the system and to ensure the requirements of high frequency and high speed, the electronic components in our PCB design were manually placed and routed, with a thorough consideration of electromagnetic compatibility. Our developed PCB has 8 layers, whose arrangement is listed in Table1. The PCB board is illustrated in Figure 10.Table 1
The layer assignment of PCB.
Symbol Description (1) Top Element layer (2) GND/CLK Analog ground/clock (3) S2 Signal layer (4) P1 Power layer (5) SGND Digital ground (6) S3 Signal layer (7) P2 Power layer (8) Bottom Element layerFigure 10
The snapshot of our developed PCB.


## 5.3. Field Experiments and Results

We conducted field experiments with our developed IF digital receiver. The receiving antenna array was a circular array, which included 16 array elements. The beacon was a monopole antenna, which spread signals. The antenna array searched the target, determined the target’s range, and formed a strong beam in the direction of the target. One terminal screen displayed the beam to thereby complete the target searching and locating.Test conditions and parameters are listed in Table2. As a good trade-off between experimental effects and prototyping cost, the receiver antenna array was determined to be a 16-element circular array with the array element of monopole antenna.Table 2
Test description.
Description Value Array form Circular array Sum of array elements 16 Array element Monopole antenna RF frequency 1032 MHz IF frequency 70 MHzSinglecarrier Sampling frequency 66 MHz Beamforming direction ϕThe received radio frequency (RF) for antenna array was 1032 MHz, which is in L band. IF signal frequency after RF-analog conversion was 70 MHz, and the sampling frequency of IF signal was 66 MHz. The size of the verification site in our field experiment was about 200 meters × 200 meters.Antenna array, analog conversion channel, and the receiving circuit board were placed in the middle of the experiment site, which is shown in Figure11(a). The beacon was placed at the edge of the site, which is shown in Figure 11(b). Due to the high position of the antenna array and the fixed beacon, θ is a fixed value. The radio frequency signal was transmitted by the beacon, and the receiver received the signal, formed the DBF beam, and pointed to the direction of the beacon, which is shown in Figure 11(c). When moving the position of the beacon during our experiments, which is equivalent to changing ϕ, the direction of the DBF beam was also moving along with the beacon. These field experiments have confirmed a great success for our developed algorithmic scheme and the implemented prototype.Figure 11
Experiment results. (a) Verification platform. (b) The beacon. (c) The formed beam.
(a) (b) (c)In this work, we are only focused on the circular array digital receiver scheme. If the antenna is arranged as a linear array, the digital receiver DBF waveform shall point to the target in a specific direction with a certainθ or ϕ value. But the entire design would become much simpler.


## 6. Conclusions

In the field of aerospace measurement and control, the ground station signal receiving equipment based on analog technology is usually expensive, large in size, and inflexible. In this paper we proposed a scheme based on Multi-FPGA system to realize intermediate frequency digital receivers. The digital beam forming (DBF) was achieved by CORDIC algorithm and an experimental prototype was developed. Our field experiments show that the developed prototype worked perfectly. The power consumption of the IF receiver circuit was only 6 watts; the consuming capacity of FPGAs was about 60%. IF sampling and digital down conversion for 16 channels are developed in parallel, and process of programs in FPGA is hard wired circuit, so, our proposed scheme can provide a great convenience to the design of IF digital receivers, which provide a valuable reference for real-time application with strong features of low power consumption, high density, and compact utilization of FPGA logic gates.



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