# Mathematical Modeling and Fault Tolerance Control for a Three-Phase Soft-Switching Mode Rectifier

Authors: Kuei-Hsiang Chao; Chin-Tsang Hsieh
Journal: Mathematical Problems in Engineering
 (2013)

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## Abstract

This study primarily focuses on the design of an intelligent three-phase soft-switching mode rectifier (SSMR). Firstly, the small-signal dynamic model of a single-phase SSMR is derived together with the design of its controller. Then, the developed single-phase SSMR is connected to form an intelligent three-phase SSMR. When any of the phase modules in the proposed intelligent three-phase SSMR experiences a fault, it can continue to supply power automatically under reduced load capacity while still maintaining good power quality characteristics. Finally, some simulation results were used to demonstrate the effectiveness of the proposed intelligent three-phase SSMR design.


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## Body

## 1. Introduction

Traditional rectifiers contain a large amount of harmonic currents, which reduce the power factor of input AC side and greatly deteriorate the power quality. To enhance power quality, a switching-mode rectifier (SMR) with power factor regulation [1] is used to make the rectifier-induced current form a sine wave with the power factor near to 1. A traditional hard-switch mode SMR comes with reduced power conversion efficiency due to a larger switching loss and possesses greater switching stress and electromagnetic interference (EMI). It uses the auxiliary resonant branches connected to the original power circuit on the hard-switching mode SMR and the modified switching control signals of the pulse-width modulation (PWM) to complete the soft-switching mode rectifier (SSMR) operation [2]. In general, large electrical equipments are fed with a three-phase power. A considerable variety of three-phase circuit configurations have been derived from single-phase switching rectifier circuits. Among them, the circuit architecture of a boost converter [3–5] is the simplest in form, easiest to control, and superior in performance; these are the primary reasons for its wide use. To date, a variety of circuit configurations and control technologies for the single-stage three-phase boost AC/DC converter have been proposed. Some of these configurations use a single active switch [6, 7], while others use six active switches [8, 9]. Single active switch-based three-phase boost AC/DC converters have a very simple architecture but contain a large amount of low older harmonics. Six active switch-based three-phase boost AC/DC converters can obtain a better power factor and harmonic control characteristics but involve a more complex control strategy.Some three-phase SMRs constructed using three or two separate single-phase SMR modules were presented in [10–13]. Though the three connected single-phase modules in a three-phase Δ-connected SMR [12] can directly apply the power factor control and soft-switching technology of a single-phase module, when one of the three-phase modules fails, Δ-connected can change to V-connected. It can continue to provide power under a reduced load condition, which translates into improved system reliability, but it is done at the expense of power quality [12]. In [13], the authors proposed a modified T-connected three-phase SMR, which is constructed using two single-phase SMRs and one center-tapped autotransformer. The three-phase line drawn currents are made balanced by applying unbalanced two-phase voltages to power the two-single SMRs. However, as any module is randomly disabled, this three-phase SMR cannot online detect the fault occurrence and continuously perform the three-phase SMR operation through automatic switch connection arrangement. To overcome these problems, this study proposes that single-phase SSMR modules should be connected together to form an intelligent three-phase SSMR that not only has a simple connection structure but also possesses automatic online fault detection functions. In the case of a module experiencing a fault, the intelligent three-phase SSMR can continue to maintain the three-phase balance of high power quality electricity supply without having to shut down for fault module maintenance, thus greatly enhancing the quality and reliability of the power supplied by the system.


## 2. Single-Phase SSMR

Figure1 shows the power circuit of the single-phase boost SSMR adopted in this study. The proposed zero-voltage transition (ZVT) SSMR system design adopts the current switch control method that uses ramp-comparison pulse-width modulation under the continuous current conduction mode (CCM).Figure 1
Circuit configuration of the proposed ZVT SSMR.


### 2.1. Scheme of Control Loop

The control block diagram of the proposed SSMR, as shown in Figure2, contains both inner and outer control loops. The inner loop is the current control loop, and the outer loop is the voltage control loop. The role of the current control loop is to raise the power factor, and the role of the voltage control loop is to provide stability control for the output DC voltage.Figure 2
Block diagram of the control structure of the proposed ZVT SSMR.According to the on- and off-states of circuit switches and diodes in Figure1, a switching period can be divided into seven operating modes. Their main waveform variables are as shown in Figure 3.Figure 3
Voltage and current waveforms of the main components of ZVT SSMR.


### 2.2. Design of a Current Control Loop Controller

The state average method can be used to derive the current loop gain transfer function [10]. If the current controller Gci(s) chooses to use a proportional-integrated (PI) controller, then the general rule of the crossover frequency of current control loop gain should be less than the switching frequency 1/2 (i.e., fc<0.5fs) and should be applied for the design of the current controller [10], which obtains
(1)Gci(s)=KPis+KIis=16.5s+10000s.


### 2.3. Deriving the Converter Model

The ZVT SSMR circuit configuration in Figure1 was divided into a slow-variable subsystem and a fast-variable subsystem [14]. The slow subsystem consisted of main storage (filter) components for input and output, while the fast subsystem consisted of resonant components with a state variable filter (slow system variables) as iLm(t) and vCo(t) and resonant state variables (fast system variables) as iLr(t) and vCr(t). From the fast subsystem perspective, the slow state variables in the entire switching period Ts could be considered as constants. In contrast, from the slow subsystem perspective, only the average effect of fast resonant state variables could be seen. Therefore, when deriving the mathematical model for the converter, the moving average function of the fast variables should be calculated first and then substituted into the slow variables to obtain the averaging model for the slow variables. Finally, the average power method was used to derive the small-signal model of the converter [15]. From the circuit configuration in Figure 1, the slow filter perspective could be used to depict the average equivalent circuit of the slow system that was shown in Figure 4. The dashed-line portion indicates the average effect of fast variables on the slow variables system. Additionally, rLm is the serial equivalent resistance of the boost inductor Lm.Figure 4
Average equivalent circuit from a slow speed perspective.Then, the voltagevCr of the resonant capacitor Cr and the moving average function of the sum iDL=iD+iDa of the currents iD and iDa flowing through both the diode D and the auxiliary diode Da were separately obtained. The seven operation modes [10] in Figure 3 were used to obtain vCr, iD, and iDa under various mode solutions, listed in Table 1. The results listed in Table 1 could be used to separately obtain the moving average function of vCr and iDL.(a)
Obtain moving average functionv-Cr of vCr as
(2)v-Cr(t)=〈vCr(t)〉Ts=1Ts∑i=06∫titi+1vCr(τ)dτ.(b)
Obtain moving average functioni-DL of iDL(t) as
(3)i-DL(t)=〈iDL(t)〉Ts=1Ts∑i=06∫titi+1[iD(t)+iDa(t)]dτ.Table 1
v
C
r
(
t
), iD(t), and iDa(t) solutions for SSMR in the seven operation modes.
Time period
Variable
v
C
r
(
t
)
i
D
(
t
)
i
D
a
(
t
)
T
1
:
[
t
0~t1]
v
C
o
(
t
)
i
L
m
(
t
)
-
[
v
C
o
(
t
)
/
L
r
]
(
t
-
t
0
)
0
T
2
:
[
t
1~t2]
v
C
o
(
t
)
cos
ω
o
(
t
-
t
1
)
0
0
T
3
:
[
t
2~t3]
0
0
0
T
4
:
[
t
3~t4]
0
0
i
L
m
(
t
)
+
v
C
o
(
t
)
/
Z
o
+
[
v
C
o
(
t
)
/
L
r
]
(
t
-
t
3
)
T
5
:
[
t
4~t5]
0
0
0
T
6
:
[
t
5~t6]
[
i
L
m
(
t
)
/
C
r
]
(
t
-
t
5
)
0
0
T
7
:
[
t
6~t0]
v
C
o
(
t
)
i
L
m
(
t
)
0Since the system in Figure1 shows a very small loss to be negligible, the averaged equivalent circuit of the slow system shown in Figure 4 can be plotted like Figure 5. Its average value of i-DL(t) during the input voltage period TL is
(4)〈i¯DL(t)〉TL≜〈〈iDL(t)〉Ts〉TL=K12π2Lri^Lm2vd(rms)28Tsvo+K1Lri^Lmvd(rms)TsZo+K1πi^Lmvd(rms)222vo-Crvo2Ts,
where K1=22K/π, and K is the proportional constant of the rectifier.Figure 5
Slow speed perspective average model equivalent circuit during the periodTL of input voltage vd.At the DC operating point of〈iLm〉TL=ILm, vd(rms)=Vd(rms), i^Lm=I^Lm, 〈i-DL(t)〉TL=IDL, and vo=Vo, after experiencing a small-signal disturbance and ignoring high-order terms of AC, the system can obtain the following.(a)
The AC component of the input current〈iLm〉TL is
(5)ΔiLm(t)=K1Vd(rms)Δi^Lm(t)+K1I^LmΔvd(rms)(t)≜gfΔi^Lm(t)+1rfΔvd(rms)(t),wheregf≜K1vd(rms), and rf≜1/(K1I^Lm).(b)
AC component of output current〈i-DL(t)〉TL is
(6)ΔiDL(t)=gb1Δi^Lm(t)+gb2Δvd(rms)(t)-[1rb1+1rb2+1rb3]Δvo(t),where(7)gb1≜K1πVd(rms)222Vo+K12π2Lri^LmVd(rms)24TsVo+K1LrVd(rms)TsZo,gb2≜K1πI^LmVd(rms)2vo+K12π2LrI^Lm2Vd(rms)4TsVo+K1LrI^LmTsZo,rb1≜22Vo2K1πI^LmVd(rms)2=22Vo2πILmVd(rms),rb2≜8TsVo2K12π2LrI^Lm2Vd(rms)2=8TsVo2π2LrILm2,rb3≜2TsCr.Equations (5) and (6) can be used to draw the small-signal equivalent circuit model of the converter, as shown in Figure 6. The transfer function of Δi^Lm to Δvo  when Δvd(rms)=0 can be derived from Figure 6 as follows:
(8)Δvo(s)Δi^Lm(s)|(Δvd(rms)=0)=gb1×(RL/(1+sRLCo))1+[(1/(rb1//rb2//rb3))×(RL/(1+sRLCo))]=gb1RLsRLCo+(RL/(rb1//rb2//rb3))+1.Figure 6
Small-signal equivalent circuit model of the converter.


## 2.1. Scheme of Control Loop

The control block diagram of the proposed SSMR, as shown in Figure2, contains both inner and outer control loops. The inner loop is the current control loop, and the outer loop is the voltage control loop. The role of the current control loop is to raise the power factor, and the role of the voltage control loop is to provide stability control for the output DC voltage.Figure 2
Block diagram of the control structure of the proposed ZVT SSMR.According to the on- and off-states of circuit switches and diodes in Figure1, a switching period can be divided into seven operating modes. Their main waveform variables are as shown in Figure 3.Figure 3
Voltage and current waveforms of the main components of ZVT SSMR.


## 2.2. Design of a Current Control Loop Controller

The state average method can be used to derive the current loop gain transfer function [10]. If the current controller Gci(s) chooses to use a proportional-integrated (PI) controller, then the general rule of the crossover frequency of current control loop gain should be less than the switching frequency 1/2 (i.e., fc<0.5fs) and should be applied for the design of the current controller [10], which obtains
(1)Gci(s)=KPis+KIis=16.5s+10000s.


## 2.3. Deriving the Converter Model

The ZVT SSMR circuit configuration in Figure1 was divided into a slow-variable subsystem and a fast-variable subsystem [14]. The slow subsystem consisted of main storage (filter) components for input and output, while the fast subsystem consisted of resonant components with a state variable filter (slow system variables) as iLm(t) and vCo(t) and resonant state variables (fast system variables) as iLr(t) and vCr(t). From the fast subsystem perspective, the slow state variables in the entire switching period Ts could be considered as constants. In contrast, from the slow subsystem perspective, only the average effect of fast resonant state variables could be seen. Therefore, when deriving the mathematical model for the converter, the moving average function of the fast variables should be calculated first and then substituted into the slow variables to obtain the averaging model for the slow variables. Finally, the average power method was used to derive the small-signal model of the converter [15]. From the circuit configuration in Figure 1, the slow filter perspective could be used to depict the average equivalent circuit of the slow system that was shown in Figure 4. The dashed-line portion indicates the average effect of fast variables on the slow variables system. Additionally, rLm is the serial equivalent resistance of the boost inductor Lm.Figure 4
Average equivalent circuit from a slow speed perspective.Then, the voltagevCr of the resonant capacitor Cr and the moving average function of the sum iDL=iD+iDa of the currents iD and iDa flowing through both the diode D and the auxiliary diode Da were separately obtained. The seven operation modes [10] in Figure 3 were used to obtain vCr, iD, and iDa under various mode solutions, listed in Table 1. The results listed in Table 1 could be used to separately obtain the moving average function of vCr and iDL.(a)
Obtain moving average functionv-Cr of vCr as
(2)v-Cr(t)=〈vCr(t)〉Ts=1Ts∑i=06∫titi+1vCr(τ)dτ.(b)
Obtain moving average functioni-DL of iDL(t) as
(3)i-DL(t)=〈iDL(t)〉Ts=1Ts∑i=06∫titi+1[iD(t)+iDa(t)]dτ.Table 1
v
C
r
(
t
), iD(t), and iDa(t) solutions for SSMR in the seven operation modes.
Time period
Variable
v
C
r
(
t
)
i
D
(
t
)
i
D
a
(
t
)
T
1
:
[
t
0~t1]
v
C
o
(
t
)
i
L
m
(
t
)
-
[
v
C
o
(
t
)
/
L
r
]
(
t
-
t
0
)
0
T
2
:
[
t
1~t2]
v
C
o
(
t
)
cos
ω
o
(
t
-
t
1
)
0
0
T
3
:
[
t
2~t3]
0
0
0
T
4
:
[
t
3~t4]
0
0
i
L
m
(
t
)
+
v
C
o
(
t
)
/
Z
o
+
[
v
C
o
(
t
)
/
L
r
]
(
t
-
t
3
)
T
5
:
[
t
4~t5]
0
0
0
T
6
:
[
t
5~t6]
[
i
L
m
(
t
)
/
C
r
]
(
t
-
t
5
)
0
0
T
7
:
[
t
6~t0]
v
C
o
(
t
)
i
L
m
(
t
)
0Since the system in Figure1 shows a very small loss to be negligible, the averaged equivalent circuit of the slow system shown in Figure 4 can be plotted like Figure 5. Its average value of i-DL(t) during the input voltage period TL is
(4)〈i¯DL(t)〉TL≜〈〈iDL(t)〉Ts〉TL=K12π2Lri^Lm2vd(rms)28Tsvo+K1Lri^Lmvd(rms)TsZo+K1πi^Lmvd(rms)222vo-Crvo2Ts,
where K1=22K/π, and K is the proportional constant of the rectifier.Figure 5
Slow speed perspective average model equivalent circuit during the periodTL of input voltage vd.At the DC operating point of〈iLm〉TL=ILm, vd(rms)=Vd(rms), i^Lm=I^Lm, 〈i-DL(t)〉TL=IDL, and vo=Vo, after experiencing a small-signal disturbance and ignoring high-order terms of AC, the system can obtain the following.(a)
The AC component of the input current〈iLm〉TL is
(5)ΔiLm(t)=K1Vd(rms)Δi^Lm(t)+K1I^LmΔvd(rms)(t)≜gfΔi^Lm(t)+1rfΔvd(rms)(t),wheregf≜K1vd(rms), and rf≜1/(K1I^Lm).(b)
AC component of output current〈i-DL(t)〉TL is
(6)ΔiDL(t)=gb1Δi^Lm(t)+gb2Δvd(rms)(t)-[1rb1+1rb2+1rb3]Δvo(t),where(7)gb1≜K1πVd(rms)222Vo+K12π2Lri^LmVd(rms)24TsVo+K1LrVd(rms)TsZo,gb2≜K1πI^LmVd(rms)2vo+K12π2LrI^Lm2Vd(rms)4TsVo+K1LrI^LmTsZo,rb1≜22Vo2K1πI^LmVd(rms)2=22Vo2πILmVd(rms),rb2≜8TsVo2K12π2LrI^Lm2Vd(rms)2=8TsVo2π2LrILm2,rb3≜2TsCr.Equations (5) and (6) can be used to draw the small-signal equivalent circuit model of the converter, as shown in Figure 6. The transfer function of Δi^Lm to Δvo  when Δvd(rms)=0 can be derived from Figure 6 as follows:
(8)Δvo(s)Δi^Lm(s)|(Δvd(rms)=0)=gb1×(RL/(1+sRLCo))1+[(1/(rb1//rb2//rb3))×(RL/(1+sRLCo))]=gb1RLsRLCo+(RL/(rb1//rb2//rb3))+1.Figure 6
Small-signal equivalent circuit model of the converter.


## 3. Proposed Intelligent Three-Phase SSMR

The three-phase rectifier circuit system possesses advantages such as higher capacity, higher output voltage ripple frequency, and smaller ripple amplitude. Therefore, to increase the system capacity and the quality of the power supply, the single-phase SSMR in this study is connected to form a three-phase SSMR for the power supply. When any of the phase modules experiences a fault, the three-phase SSMR system can continue to maintain the three-phase balanced power supply under a reduced load capacity while still maintaining excellent power quality characteristics.


### 3.1. Proposed Circuit Configuration of a Single-Phase SSMR Module Connected to Form a Three-Phase SSMR

The proposed circuit configuration and control structure of the intelligent three-phase SSMR has two more center-tapped autotransformers and three more toggle switches than a traditional three-phaseΔ-connected SSMR system, as shown in Figures 7(a) and 7(b) [13, 16]. The control structure of the intelligent three-phase SSMR in Figure 7(b) has added current distributing factors w1~w3, fault diagnosis, and troubleshooting logic components. The fault diagnosis and troubleshooting logic unit controlled the switching of the proposed intelligent three-phase SSMR toggle switches SW1~SW3 and the selection of current distribution factors w1~w3. SW1~SW3 in each module switche to theⓐpoint shown in Figure 7(a) under normal operation, with the selection of current distribution factors w1~w3 as 1. When each module of the proposed intelligent three-phase SSMR is operating under normal conditions, its circuit configuration is complete the same as the three-phase Δ-connected SSMR. Therefore, the total capacity and the phasor diagram of voltage and current of the intelligent three-phase SSMR are similar to those of a traditional three-phase Δ-connected SSMR.The proposed intelligent three-phase SSMR: (a) circuit configuration; (b) control structure.
(a)
(b)


### 3.2. Design of a Voltage Control Loop Controller

Under good current tracking characteristics, the proposed voltage control loop of a three-phase SSMR can be reasonably expressed as in the block diagram of Figure8, where Kpv is the conversion coefficient of a load power disturbance on the voltage, Kv is the expressed voltage sensing conversion factor, which is set as Kv=0.02(V/V), and Gp(s) is the transfer function of the converter. Based on the ease of implementation consideration, the voltage controller Gcv(s) uses a PI controller.Figure 8
Voltage control loop block diagram of the proposed three-phase SSMR.The proposed small-signal equivalent circuit model for the three-phase SSMR converter is plotted in Figure9 based on the single-phase SSMR determined in Section 2.3. The transfer function of Δi^Lm to Δvo during Δvd(rms)=0 that can be obtained from Figure 9 is
(9)Δvo(s)Δi^Lm(s)|(Δvd(rms)=0)=3gb1×(RL/(1+sRLCo))1+[(3/(rb1//rb2//rb3))×(RL/(1+sRLCo))]=3gb1RLsRLCo+(3RL/(rb1//rb2//rb3))+1.Figure 9
Small-signal equivalent circuit model of the proposed three-phase SSMR converter.When the module load in each phase reachesPo=300.4 W, the voltage controller will first use a simple proportional controller (P-controller) Gcv(s)=Kp=5 and set vo* to 8 V (the actual command value is 8V/0.02=400V). In cases where the input inductor current iLm(t) is able to completely track the command current, the current amplitude command signal I^Lm is measured to be 6.4 A, with an actual output voltage of 360 V at the specific moment. The rest of the parameters required for seeking the transfer function of the converter are listed in Table 2. By substituting the parameters listed in Table 2 into (9), the converter transfer function can be obtained as
(10)Gp(s)=bs+a=851.38s+20.16.Table 2
Parameters required for finding the transfer function of the converter.
Input voltageVd(rms)
220 V
Maximum output powerPo
600 W
Boost inductorLm
450μH
Output filter capacitorCo
2000μF
Load resistorRL
150 Ω
Resonant inductorLr
20μH
Resonant capacitorCr
870 PF
Switching periodTs
10μs
Resonant impedanceZo
151.62 Ω
Ratio constantKr
5 V/220 VIf the system is to achieve high performance load regulation characteristics, the step load dynamic response is generally required to possess characteristics such as zero steady-state error, zero overshoot, smallest possible maximum voltage dip, and quickest possible restore time. The output voltage specification requirements on the step response are(i)
steady-state error = 0;(ii)
overshoot = 0;(iii)
output voltage dip caused by a unit-step load  changeΔPo=600 W is set to Δvo,max=8V;(iv)
voltage dip restore time:tr=0.8 sec.The voltage controller parameters that can be obtained using voltage controller quantitative design steps [15] are Kp=1.3 and KI=9.46.


### 3.3. Power Supply Situation during Any Phase Fault in the Proposed Intelligent Three-Phase SSMR

The circuit configuration and the phasor diagram of the associated voltage and current of the proposed intelligent three-phase SSMR duringu phase module failure are shown in Figure 10. Assume that when the u phase SSMR module is experiencing a fault, the position of SW3 will be switched toⓑ, and at that specific moment, the output power values of SSMR v and SSMR w are Pv and Pw. Their circuit configuration and the phasor diagram of related voltages and currents are plotted in Figure 10, and the obtained Pv and Pw are
(11)Pv=|Vv||Iv|=(3|Vun|)(K3|Vun|i^Lmw2),Pw=|Vw||Iw|=(32|Vun|)(K32|Vun|i^Lmw3),
where K is the proportionality constant of the rectifier, and w2 and w3 are current distribution factors of SSMR v and SSMR w, respectively. In (11), the purported  Pv=Pw condition must be met by satisfying
(12)w2:w3=0.75:1.
At the moment when |Vv|=V, |Iv|=(3/2)I, |VW|=(3/2)V, and |IW|=I, the total capacity of the proposed modified T-connected SSMR during a fault in SSMR u is
(13)VAT=PT=|Vv||Iv|+|VW||IW|=3VI=13PΔ.Figure 10
The circuit configuration and the phasor diagram of related voltages and currents of the proposed intelligent three-phase SSMR duringu phase fault.When a fault occurs in thev phase SSMR module, the output power values of SSMR u and SSMR w are Pu and Pw.The circuit configuration and the phasor diagram of the related voltages and currents are plotted in Figure11, and the obtained Pu and Pw are
(14)Pu=|Vu||Iu|=(3|Vun|)(K3|Vun|i^Lmw1),Pw=|Vw||Iw|=(32|Vun|)(K32|Vun|i^Lmw3),
where K is the proportionality constant of the rectifier, and w1 and w3 are current distribution factors of SSMR u and SSMR w, respectively. In (14), the purported Pu=Pw condition must be met by satisfying
(15)w1:w3=0.75:1.
At the moment when |Vu|=V, |Iu|=(3/2)I, |VW|=(3/2)V, and |IW|=I, the total capacity of the proposed modified T-connected SSMR during a fault in SSMR v is
(16)VAT=PT=|Vu||Iu|+|VW||IW|=3VI=13PΔ.Figure 11
The circuit configuration and the phasor diagram of related voltages and currents of the proposed intelligent three-phase SSMR duringv phase fault.When a fault occurs in aw phase SSMR module, the output power values of SSMR u and SSMR v are Pu and Pv. The circuit configuration and the phasor diagram of the correlated voltages and currents are plotted in Figure 12, and the obtained Pu and Pv are
(17)Pu=|Vu||Iu|=(3|Vun|)(K3|Vun|i^Lmw1),Pv=|Vv||Iv|=(32|Vun|)(K32|Vun|i^Lmw2),
where K is the proportionality constant of the rectifier, and w1  and  w2 are current distribution factors of SSMR u and SSMR v, respectively. In (17), the purported Pu=Pv condition must be met by satisfying
(18)w1:w2=0.75:1.
At the moment when |Vu|=V, |Iu|=(3/2)I, |Vv|=(3/2)V, and |Iv|=I, the total capacity of the proposed modified T-connected SSMR during a fault in SSMR w is
(19)VAT=PT=|Vu||Iu|+|Vv||Iv|=3VI=13PΔ.Figure 12
The circuit configuration and the phasor diagram of related voltages and currents of the proposed intelligent three-phase SSMR duringw phase fault.Based on the previous analysis, when a fault occurs in any phase module of the proposed intelligent three-phase SSMR, the total capacity is reduced to1/3 that of normal operation. When a fault occurs to any phase module and during normal three-phase module operation, the switch state of toggle switches SW1~SW3 and the current distribution factors used in each module are as shown in Tables 3 and 4. During normal operation, current flowing through the module can be detected; therefore, the logic level of that module during normal operation is set to high. In contrast, when a module experiences a fault, the logic level is set to low. In Table 3, when the switch is placed at theⓐpoint, the logic level is set to high. When it is at theⓑpoint, it is set to low. In Table 4, when the current distribution factor is 1, the logic level is set to high; when the current distribution factor is 0.75, the logic level is set to low. The logic levels demonstrated by the previous results are summarized in a logic control circuit truth-value table in Table 5. The truth-value table listed in Table 5 has been simplified using Karnaugh map, and its logic control circuit can be realized using the logic circuit in Figure 13. The logic circuit in Figure 13 can be used to control the position of the toggle switches SW1~SW3 and the selection of a current distribution factor in Figures 10 to 12. When a fault occurs in any phase module of the proposed three-phase modified T-connected SSMR system, the detected faulty module can again perform a no-fault module current distribution factor selection and can automatically toggle the position of switches SW1~SW3 to change the circuit configuration. The three-phase balanced power supply is continuously maintained under a reduced load capacity, allowing it to still regulate the input voltage and current into almost the same phase. This achieves an excellent supply quality of almost 1.0 in the power factor.Table 3
Positions of toggle switches SW1~SW3 under various operating conditions.
Operating condition
Switch
SW1
SW2
SW3
Normal operation
ⓐ
ⓐ
ⓐ
SSMRu fault
ⓐ
ⓐ
ⓑ
SSMRv fault
ⓑ
ⓐ
ⓐ
SSMRw fault
ⓐ
ⓑ
ⓐTable 4
Current distribution factors used under various operating conditions.
Operating condition
Current distribution factor
w
1
w
2
w
3
Normal operation
1
1
1
SSMRu fault
×
0.75
1
SSMRv fault
0.75
×
1
SSMRw fault
0.75
1
×
Note: × indicates not taking into consideration.Table 5
Truth-value table of a logic control circuit of the proposed intelligent three-phase SSMR.
|
i
u
|
|
i
v
|
|
i
w
|
w
1
w
2
w
3
SW1
SW2
SW3
L
L
L
×
×
×
×
×
×
L
L
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
L
H
H
×
L
H
H
H
L
H
L
L
H
H
H
H
H
H
H
L
H
L
×
H
L
H
H
H
H
L
L
H
×
H
L
H
H
H
H
H
H
H
H
H
HFigure 13
Logic control circuit of the proposed intelligent three-phase SSMR.


## 3.1. Proposed Circuit Configuration of a Single-Phase SSMR Module Connected to Form a Three-Phase SSMR

The proposed circuit configuration and control structure of the intelligent three-phase SSMR has two more center-tapped autotransformers and three more toggle switches than a traditional three-phaseΔ-connected SSMR system, as shown in Figures 7(a) and 7(b) [13, 16]. The control structure of the intelligent three-phase SSMR in Figure 7(b) has added current distributing factors w1~w3, fault diagnosis, and troubleshooting logic components. The fault diagnosis and troubleshooting logic unit controlled the switching of the proposed intelligent three-phase SSMR toggle switches SW1~SW3 and the selection of current distribution factors w1~w3. SW1~SW3 in each module switche to theⓐpoint shown in Figure 7(a) under normal operation, with the selection of current distribution factors w1~w3 as 1. When each module of the proposed intelligent three-phase SSMR is operating under normal conditions, its circuit configuration is complete the same as the three-phase Δ-connected SSMR. Therefore, the total capacity and the phasor diagram of voltage and current of the intelligent three-phase SSMR are similar to those of a traditional three-phase Δ-connected SSMR.The proposed intelligent three-phase SSMR: (a) circuit configuration; (b) control structure.
(a)
(b)


## 3.2. Design of a Voltage Control Loop Controller

Under good current tracking characteristics, the proposed voltage control loop of a three-phase SSMR can be reasonably expressed as in the block diagram of Figure8, where Kpv is the conversion coefficient of a load power disturbance on the voltage, Kv is the expressed voltage sensing conversion factor, which is set as Kv=0.02(V/V), and Gp(s) is the transfer function of the converter. Based on the ease of implementation consideration, the voltage controller Gcv(s) uses a PI controller.Figure 8
Voltage control loop block diagram of the proposed three-phase SSMR.The proposed small-signal equivalent circuit model for the three-phase SSMR converter is plotted in Figure9 based on the single-phase SSMR determined in Section 2.3. The transfer function of Δi^Lm to Δvo during Δvd(rms)=0 that can be obtained from Figure 9 is
(9)Δvo(s)Δi^Lm(s)|(Δvd(rms)=0)=3gb1×(RL/(1+sRLCo))1+[(3/(rb1//rb2//rb3))×(RL/(1+sRLCo))]=3gb1RLsRLCo+(3RL/(rb1//rb2//rb3))+1.Figure 9
Small-signal equivalent circuit model of the proposed three-phase SSMR converter.When the module load in each phase reachesPo=300.4 W, the voltage controller will first use a simple proportional controller (P-controller) Gcv(s)=Kp=5 and set vo* to 8 V (the actual command value is 8V/0.02=400V). In cases where the input inductor current iLm(t) is able to completely track the command current, the current amplitude command signal I^Lm is measured to be 6.4 A, with an actual output voltage of 360 V at the specific moment. The rest of the parameters required for seeking the transfer function of the converter are listed in Table 2. By substituting the parameters listed in Table 2 into (9), the converter transfer function can be obtained as
(10)Gp(s)=bs+a=851.38s+20.16.Table 2
Parameters required for finding the transfer function of the converter.
Input voltageVd(rms)
220 V
Maximum output powerPo
600 W
Boost inductorLm
450μH
Output filter capacitorCo
2000μF
Load resistorRL
150 Ω
Resonant inductorLr
20μH
Resonant capacitorCr
870 PF
Switching periodTs
10μs
Resonant impedanceZo
151.62 Ω
Ratio constantKr
5 V/220 VIf the system is to achieve high performance load regulation characteristics, the step load dynamic response is generally required to possess characteristics such as zero steady-state error, zero overshoot, smallest possible maximum voltage dip, and quickest possible restore time. The output voltage specification requirements on the step response are(i)
steady-state error = 0;(ii)
overshoot = 0;(iii)
output voltage dip caused by a unit-step load  changeΔPo=600 W is set to Δvo,max=8V;(iv)
voltage dip restore time:tr=0.8 sec.The voltage controller parameters that can be obtained using voltage controller quantitative design steps [15] are Kp=1.3 and KI=9.46.


## 3.3. Power Supply Situation during Any Phase Fault in the Proposed Intelligent Three-Phase SSMR

The circuit configuration and the phasor diagram of the associated voltage and current of the proposed intelligent three-phase SSMR duringu phase module failure are shown in Figure 10. Assume that when the u phase SSMR module is experiencing a fault, the position of SW3 will be switched toⓑ, and at that specific moment, the output power values of SSMR v and SSMR w are Pv and Pw. Their circuit configuration and the phasor diagram of related voltages and currents are plotted in Figure 10, and the obtained Pv and Pw are
(11)Pv=|Vv||Iv|=(3|Vun|)(K3|Vun|i^Lmw2),Pw=|Vw||Iw|=(32|Vun|)(K32|Vun|i^Lmw3),
where K is the proportionality constant of the rectifier, and w2 and w3 are current distribution factors of SSMR v and SSMR w, respectively. In (11), the purported  Pv=Pw condition must be met by satisfying
(12)w2:w3=0.75:1.
At the moment when |Vv|=V, |Iv|=(3/2)I, |VW|=(3/2)V, and |IW|=I, the total capacity of the proposed modified T-connected SSMR during a fault in SSMR u is
(13)VAT=PT=|Vv||Iv|+|VW||IW|=3VI=13PΔ.Figure 10
The circuit configuration and the phasor diagram of related voltages and currents of the proposed intelligent three-phase SSMR duringu phase fault.When a fault occurs in thev phase SSMR module, the output power values of SSMR u and SSMR w are Pu and Pw.The circuit configuration and the phasor diagram of the related voltages and currents are plotted in Figure11, and the obtained Pu and Pw are
(14)Pu=|Vu||Iu|=(3|Vun|)(K3|Vun|i^Lmw1),Pw=|Vw||Iw|=(32|Vun|)(K32|Vun|i^Lmw3),
where K is the proportionality constant of the rectifier, and w1 and w3 are current distribution factors of SSMR u and SSMR w, respectively. In (14), the purported Pu=Pw condition must be met by satisfying
(15)w1:w3=0.75:1.
At the moment when |Vu|=V, |Iu|=(3/2)I, |VW|=(3/2)V, and |IW|=I, the total capacity of the proposed modified T-connected SSMR during a fault in SSMR v is
(16)VAT=PT=|Vu||Iu|+|VW||IW|=3VI=13PΔ.Figure 11
The circuit configuration and the phasor diagram of related voltages and currents of the proposed intelligent three-phase SSMR duringv phase fault.When a fault occurs in aw phase SSMR module, the output power values of SSMR u and SSMR v are Pu and Pv. The circuit configuration and the phasor diagram of the correlated voltages and currents are plotted in Figure 12, and the obtained Pu and Pv are
(17)Pu=|Vu||Iu|=(3|Vun|)(K3|Vun|i^Lmw1),Pv=|Vv||Iv|=(32|Vun|)(K32|Vun|i^Lmw2),
where K is the proportionality constant of the rectifier, and w1  and  w2 are current distribution factors of SSMR u and SSMR v, respectively. In (17), the purported Pu=Pv condition must be met by satisfying
(18)w1:w2=0.75:1.
At the moment when |Vu|=V, |Iu|=(3/2)I, |Vv|=(3/2)V, and |Iv|=I, the total capacity of the proposed modified T-connected SSMR during a fault in SSMR w is
(19)VAT=PT=|Vu||Iu|+|Vv||Iv|=3VI=13PΔ.Figure 12
The circuit configuration and the phasor diagram of related voltages and currents of the proposed intelligent three-phase SSMR duringw phase fault.Based on the previous analysis, when a fault occurs in any phase module of the proposed intelligent three-phase SSMR, the total capacity is reduced to1/3 that of normal operation. When a fault occurs to any phase module and during normal three-phase module operation, the switch state of toggle switches SW1~SW3 and the current distribution factors used in each module are as shown in Tables 3 and 4. During normal operation, current flowing through the module can be detected; therefore, the logic level of that module during normal operation is set to high. In contrast, when a module experiences a fault, the logic level is set to low. In Table 3, when the switch is placed at theⓐpoint, the logic level is set to high. When it is at theⓑpoint, it is set to low. In Table 4, when the current distribution factor is 1, the logic level is set to high; when the current distribution factor is 0.75, the logic level is set to low. The logic levels demonstrated by the previous results are summarized in a logic control circuit truth-value table in Table 5. The truth-value table listed in Table 5 has been simplified using Karnaugh map, and its logic control circuit can be realized using the logic circuit in Figure 13. The logic circuit in Figure 13 can be used to control the position of the toggle switches SW1~SW3 and the selection of a current distribution factor in Figures 10 to 12. When a fault occurs in any phase module of the proposed three-phase modified T-connected SSMR system, the detected faulty module can again perform a no-fault module current distribution factor selection and can automatically toggle the position of switches SW1~SW3 to change the circuit configuration. The three-phase balanced power supply is continuously maintained under a reduced load capacity, allowing it to still regulate the input voltage and current into almost the same phase. This achieves an excellent supply quality of almost 1.0 in the power factor.Table 3
Positions of toggle switches SW1~SW3 under various operating conditions.
Operating condition
Switch
SW1
SW2
SW3
Normal operation
ⓐ
ⓐ
ⓐ
SSMRu fault
ⓐ
ⓐ
ⓑ
SSMRv fault
ⓑ
ⓐ
ⓐ
SSMRw fault
ⓐ
ⓑ
ⓐTable 4
Current distribution factors used under various operating conditions.
Operating condition
Current distribution factor
w
1
w
2
w
3
Normal operation
1
1
1
SSMRu fault
×
0.75
1
SSMRv fault
0.75
×
1
SSMRw fault
0.75
1
×
Note: × indicates not taking into consideration.Table 5
Truth-value table of a logic control circuit of the proposed intelligent three-phase SSMR.
|
i
u
|
|
i
v
|
|
i
w
|
w
1
w
2
w
3
SW1
SW2
SW3
L
L
L
×
×
×
×
×
×
L
L
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
L
H
H
×
L
H
H
H
L
H
L
L
H
H
H
H
H
H
H
L
H
L
×
H
L
H
H
H
H
L
L
H
×
H
L
H
H
H
H
H
H
H
H
H
HFigure 13
Logic control circuit of the proposed intelligent three-phase SSMR.


## 4. Simulation Results of the Proposed Intelligent Three-Phase SMR

Since each single module of the proposed intelligent three-phase SSMR system is rated at 600 W, the total power is 1800 W. Therefore, when a fault occurs in any module in this system, if the load capacity is greater than1800/3 W, then the system reduces the load to continue providing power. This ensures that no-fault modules would not be burnt down by a power overload. Figures 14, 15, and 16 are the PSIM software generated waveforms representing relevant restored voltages and currents after the troubleshooting of faults from a sudden failure of any of the SSMR u, SSMR v, and SSMR w modules under a reduced power load when the proposed SSMR supply load is 1800 W. As is evident from the intelligent three-phase SSMR shown in the figures, when each module is operating normally, the three-phase input line voltage and current are nearly in phase to produce a three-phase balance power supply. When one module fails, the input line voltage and current of the three-phase can maintain in phase and supply the three-phase balance power, while the amplitude of the input voltage and current and phasor diagram of each no-fault module is also consistent with positions that are in phase. Therefore, it has a good power factor and low harmonic characteristics. The output DC voltage during the dynamic response to a module fault and the post fault troubleshooting power restoration can also use the designed voltage controller to retain a high regulation performance.Simulated results of a continuous power supply when the load drops from 1800 W to1800/3 W during a failure of a SSMR u module in the proposed intelligent three-phase SSMR: (a) simulated waveforms of output DC voltages and input voltages and currents for each phase; (b) simulated waveforms of input voltages and currents of various modules.
(a)
(b)Simulated results of a continuous power supply when the load drops from 1800 W to1800/3 W during a failure of a SSMR v module in the proposed intelligent three-phase SSMR: (a) simulated waveforms of output DC voltages and input voltages and currents for each phase; (b) simulated waveforms of input voltages and currents of various modules.
(a)
(b)Simulated results of a continuous power supply when the load drops from 1800 W to1800/3 W during a failure of SSMR w module in the proposed intelligent three-phase SSMR: (a) simulated waveforms of output DC voltages and input voltages and currents for each phase; (b) simulated waveforms of input voltages and currents of various modules.
(a)
(b)The comparisons of circuit structure, switching characteristics, power quality, fault tolerance, and reliability of the power supply between the proposed three-phase SSMR and some of the existing ones are made in Table6. It shows that the proposed three-phase SSMR possesses the advantages of flexibility, reliability, superior power quality, and on-line fault detection tolerance.Table 6
Characteristics comparison between different three-phase switching mode rectifiers (SMRs).
Items
Topologies
TSP PFC SMR in [13]
PFC SSMR in [12]
Proposed SSMR
Circuit structure
Medium
Simple
Medium
Switching characteristics
Hard-switching
Soft-switching
Soft-switching
Power quality
Superior
Inferior
Superior
Fault tolerance
Inferior
Inferior
Superior
Reliability of the power supply
Inferior
Inferior
Superior


## 5. Conclusions

For the application of a three-phase power feeding in large-capacity power electronic equipment, this study adopted single-phase single module SSMR to assemble an intelligent three-phase SSMR system power supply.  When any module in this three-phase SSMR module experiences a fault, the proposed intelligent three-phase SSMR system can use intelligent online fault diagnosis and a fault troubleshooting strategy to immediately reduce the load capacity online to continue maintaining the three-phase balanced power supply, keeping the three-phase SSMR system from shutting down for rerouting. This greatly enhances the reliability of the power supply, while the three-phase input voltage and current are still almost in phase; so, the power supply side can still possess the characteristics of good power factor and low harmonics.



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*Source: 598130-2013-02-28.xml*