# Analytical Model of Subthreshold Drain Current Characteristics of Ballistic Silicon Nanowire Transistors

Authors: Wanjie Xu; Hei Wong; Hiroshi Iwai
Journal: Advances in Condensed Matter Physics
 (2015)

---

## Abstract

A physically based subthreshold current model for silicon nanowire transistors working in the ballistic regime is developed. Based on the electric potential distribution obtained from a 2D Poisson equation and by performing some perturbation approximations for subband energy levels, an analytical model for the subthreshold drain current is obtained. The model is further used for predicting the subthreshold slopes and threshold voltages of the transistors. Our results agree well with TCAD simulation with different geometries and under different biasing conditions.


---

## Body

## 1. Introduction

Performance improvement of metal-oxide-semiconductor field-effect transistors (MOSFETs) based on downsizing has now reached the bottleneck because of the severe short channel effects (SCE) and extremely large leakage current in ultrasmall scales. Several alternate structures other than the conventional planar MOSFET have been proposed [1–3]. It was shown that silicon nanowire transistor (SNT) with a surrounding gate architecture has excellent SCE immunity and is now considered to be one of the most promising candidates for future generations of nanoscale MOS technology.Due to the superior gate control capability, the channel region of SNT needs not to be heavily doped and the penetration of source and drain electric field into the channel are still minimal. In addition, mobility degradation due to the impurity scattering of carriers in the channel can be greatly reduced also. Ultrashort channel structures further enable ballistic transport [4, 5]. Transistor working in the ballistic regime is considered to have the best electrical performance. However, subthreshold leakage is still the big concern for these devices. It will be more convenient for process and device engineers to estimate these effects by using a simple compact model as it did in the conventional device structure. The conventional drift-diffusion-based subthreshold current model will no longer be valid for the ultrashort SNTs [6, 7] as the ballistic transport has become the dominating mechanism and that makes the analytical modeling extremely difficult [8, 9]. In [10], a model for subthreshold characteristics of ballistic surrounding gate MOSFET is proposed. However, the boundary electric potential was extracted from numerical simulation without comprehensive analysis. This work aims at the development of an analytical model for the subthreshold drain current of SNT by taking the ballistic effect into account. The boundary potential is analyzed from the electron statistics point of view.Our model is developed by firstly solving the two-dimensional Poisson equation to determine the potential distribution; subband energy levels are then obtained by using the first-order perturbation based on the available electric potentials. Finally drain current is obtained according to the Landauer theory by taking several major subband levels into consideration. The model is validated by comparing the results with TCAD simulation with Nonequilibrium Green Function (NEGF) model [11]. NEGF approach has been widely used to characterize quantum confinement and ballistic transport in the ultrascale devices [10–14]. The organization of this paper is as follows. The modeling of electric potential in the channel from solving Poisson’s equation is presented in Section 2. In Section 3, the electrical characteristics of SNT, such as electric potential distribution, subthreshold current, subthreshold slope, and threshold voltage roll-off, are presented along with the comparison with TCAD simulations. Finally, the major results are summed up in Section 4.


## 2. Modeling of Potential Distribution

The structures of the SNT and the coordinate system used in this work are shown in Figure1. For the sake of simplicity, heavily doped source and drain regions are considered as ideal reservoirs. The channel region is undoped. It was found experimentally that ballisticity occurs in SNT with radius of 4 nm and channel length of about 20 nm [15]. This model uses the similar device dimensions. Typical values of device parameters used in the calculation and simulation are listed in Table 1. Considering angular symmetry, polar coordinates r and θ were used. With the surrounding gate structure, the electric potential in the channel is predominately governed by the gate bias. While for very short channel, the influence of source and drain on electric potential cannot be neglected. To obtain the channel potential distribution, we solve the 2D Poisson equation in the undoped channel as follows:(1)1r∂∂rr∂ϕ∂r+∂2ϕ∂z2=qniϵSieqϕ-V/kBT,where ϕ(r,z) is the electric potential, q is the magnitude of electron charge, and ϵSi is the silicon permittivity. ni is the intrinsic electron concentration of silicon; V is quasi-Fermi potential whose value depends on position in the channel. It equals zero at source and drain-to-source voltage (VDS) at the drain side. Since the subthreshold drain current is mainly governed by the electrostatic near the source region, we evaluate the case when V=0V. Comparison made between numerical simulations also confirms the validity of this assumption in the subthreshold regime.Table 1
Typical device parameters used in the simulation and model calculation.
Parameters
Typical values
Source doping density,NS (cm−3)
1020
Drain doping density,ND (cm−3)
1020
Gate length,L (nm)
20
Gate oxide thickness,tox (nm)
1
Radius of nanowire,R (nm)
4Figure 1
Schematic of structure of ann-type SNT. (a) Cross section view and (b) cut plane along the channel. R and L are the radius and the length of nanowire, respectively. tox is the gate oxide thickness.
(a)
(b)The boundary conditions for electric potential are(2)CoxVGS-VFB-ϕR,z=ϵSi∂ϕ∂rr=R(3)ϕr,0=VS,ϕr,L=VD,where VGS is the gate-to-source voltage and VFB is the flatband voltage which equals the difference between the workfunctions of gate material and silicon. Cox is the oxide capacitance per unit area. VS and VD are potentials in source and drain region, respectively. The difference of VS and VD is drain bias; that is, VD=VS+VDS.V
S needs to be specified to obtain the electric potential distribution. In the conventional models of SNT, VS is fixed as built-in voltage of source junction Vbi. For the device considered in this model, Vbi=Eg/2, where Eg is the bandgap of silicon. In thin nanowires, electrons are confined to discrete subbands which are well above conduction band edge. In order to maintain the charge neutrality condition in the source region, these subband levels should be further pulled down to be occupied by more electrons. The difference of the subband levels from conduction band edge is approximated by energy levels in a cylindrical quantum well; that is,(4)Em,nυ=jmn2ℏ22mυrR2,where ℏ is the reduced Plank constant and jmn is the nth root of mth-order first-kind Bessel function Jm(x). υ represents the valley in which subbands reside. mυr is the radical effective mass for the valley concerned. Electron density is the statistics of each subband from Landauer theory [16]. Suppose the doping concentration in the source region is ND; equation of charge neutrality is(5)∑υ,m,ngυ2mυdkBTπℏ21/2F-1/2EFS-Em,nυ-qVSkBT=πR2ND,where all subband levels are assumed to be lowered by the source potential. gυ and mυd are the degeneracy and the z-direction effective mass of the valley, respectively. EFS is the source Fermi level; F-1/2(x) is the Fermi-Dirac integral. Here we used analytical approximation [17] for the integral to reduce the cost of computation. VS can be obtained by solving (5) numerically and the result is a function of nanowire radius. The biasing conditions do not have significant influence on VS. Figure 2(a) shows the dependence of VS on the nanowire radius. It is observed that, for larger radius, VS is smaller due to lower subband energy levels.Figure 2
(a) Dependence of source potential on the nanowire radius for the source doping density shown in Table1. (b) Dependence of maximum central electric potential on the nanowire radius. The results can be fitted empirically with a rational function.
(a)
(b)Figure3 shows the central potential distribution along the channel obtained from TCAD simulation. In the source region, the electric potential is very close to the value calculated from (5). However, the electric potential starts to drop at some distances from interface between the source and the channel. This also occurs at the drain end of the channel. This is equivalent to an increase of channel length and is treated as a fitting parameter in the model. The increment of channel length is 1.4 nm and this value is used for other channel-length-dependent results also.Figure 3
Central electric potential at different positions along the channel obtained from TCAD simulation forR = 4 nm and L = 10 nm; source and drain length are both 10 nm; VGS = 0.1 V, VDS = 0.05 V. The horizontal axis is distance from source electrode. Interfaces between channel and source and channel and drain are depicted by dashed lines.Using the proposition method given in [18], (1) can be solved by dividing electric potential into two parts which can be solved separately:(6)ϕr,z=ϕ0r+ϕ1r,z,where ϕ0r is the part obtained by gradual channel approximation; that is [19],(7)ϕ0r=ϕc-2kBTqln⁡1-r2R2eqϕc-ϕcm/kBT,where ϕc is the electric potential at the center of nanowire. ϕcm is the maximum central potential that can be reached by increasing the gate voltage. In thin SNT with strong confinement, central potential also tends to be saturated when the gate voltage is very high. Because of the quantum confinement, the electron density in the channel is smaller; the maximum central potential is larger than that in the classic model [20]. Since ϕ0r in (7) is based on the gradual channel approximation which is independent of both the drain bias and the channel length, ϕcm is determined by the gate oxide thickness and the nanowire radius. Figure 2(b) shows the dependence of ϕcm on the radius of the nanowire for different gate oxide thicknesses obtained from simulation. It is obvious that the influence of gate oxide thickness on ϕcm is very small; that is, ϕcm is fairly governed by the radius of the nanowire only. An empirical fitting of the simulation result, as given below, is used to model this dependence:(8)ϕcm=aR+bR+c,where the values of the fitting parameters are a=0.484V,  b=0.092V·nm, and c=-0.466nm.The central potentialϕc can be obtained precisely by considering the boundary condition for ϕ0r. Here we use an asymptotic approximation, instead, to simplify the equation evaluation [19]:(9)ϕc=12ϕca+ϕcm-ϕca-ϕcm2+δϕcaϕcm,where ϕca=VGS-VFB is the central potential when the gate voltage is far below the threshold. δ is an empirical smoothing parameter and its value is approximated as 0.011+ln⁡1+tox/R.ϕ
1
r
,
z in (6) is obtained by solving the residual 2D Poisson equation as an expansion of Fourier-Bessel series [18]:(10)ϕ1r,z=∑m=1∞C0meλmz/R+C1me-λmz/RJ0λmrRand the eigenvalue λm is the mth solution of the equation(11)ϵoxϵSiln⁡1+tox/R=λJ1λJ0λ,where ϵox is the permittivity of oxide. Coefficients C0m and C1m are obtained by expanding the boundary conditions (3) in the Fourier-Bessel series. Since the gate length L is usually much larger than nanowire radius R, the expressions for C0m and C1m can be further simplified as(12)C0m=2e-λmL/RJ02λm+J12λmJ1λmλmVD-VmC1m=2J02λm+J12λmJ1λmλmVS-Vm,where Vm is the expansion coefficient of ϕ0r in the Fourier-Bessel series:(13)Vm=1R2∫0Rϕ0rJ0λmrRrdr.The integral in (13) can be simplified further. Considering the expression of ϕ0r in (7), in the subthreshold regime, q(ϕc-ϕcm)/kBT is small; ϕ0r can be simplified as(14)ϕ0r≈ϕc+2kBTr2qR2eqϕc-ϕcm/kBT.Taking these approximations into account, the integral in (14) can be analytically derived and the result is(15)Vm=J1λmλmϕc+2J2λm-λmJ3λmλm22kBTqeqϕc-ϕcm/kBT.Figure4 compares the central potential distribution along the channel obtained from the model and the simulations for various gate lengths. The results of model agree well with simulation ones, especially in the region near the source dominating the drain current characteristics. It is clearly shown that as gate length shrinks, the influence of the source and drain regions on the electric potential in the channel becomes more prominent; the central potential in the channel increases as a result. In the case of gate length of 10 nm, the central potential is even larger than the gate voltage. It indicates a serious SCE in such short gate length. Larger potential in the channel results in a larger electron concentration and therefore a larger subthreshold leakage current in a shorter SNT. For a device with a larger gate length, the gate controllability on the channel potential is stronger; the variation of potential near the source still remains small as the drain voltage increases. However, for gate length of 10 nm, the control of gate becomes much weaker and the increase of drain voltage would cause a substantial variation on the potential distribution in the whole channel (see Figure 4).Figure 4
Central electric potential along the channel obtained from the model and TCAD simulation for different gate lengths. Nanowire radius is (a) 4 nm; (b) 3 nm. The other device parameters are obtained from Table1. The solid lines and symbols are for drain bias of 0.05 V; the dashed lines and open symbols are for drain bias of 0.5 V.
(a)
(b)


## 3. Subthreshold Current Characteristics

Electronic transportation was determined at the subband barrier located at the position with minimum electric potential along the channel. Within each subband, electrons injected from source or drain have to transmit across the barrier. The transmission probability is either one or zero depending on whether the electron energy is larger or smaller than barrier energy or not. Drain current was then calculated with Landauer’s theory [16]: (16)IDS=qkBTπℏ∑υ,m,ngυln⁡1+eEFS-Em,nυ/kBT1+eEFD-Em,nυ/kBT,where EFD=EFS-qVDS is Fermi level of drain region.Note that the subband levels in (16) are the most important parameter for determining the drain current. In the flatband condition, the subband levels are characterized by (4). For larger gate bias, it is difficult to get an analytical expression for the subband levels and drain current. Here we revised the subband levels by taking perturbation integrals at the subband barrier:(17)ΔEm,nυ=-q∫0Rψm,nr2ϕr,zmin⁡rdr,where ψm,nr=Jm(jmnr/R)/Nmn is the corresponding wavefunction of the subband. The wavefunctions of the corresponding subbands in the two valleys are the same. Nmn is a normalization factor, and zmin⁡ is the position of subband barrier along channel and is determined by (∂ϕ1r,z/∂z)zmin⁡=0. Only the first term in (10) is considered when deriving zmin⁡ because the magnitude of other high-order terms is much smaller; hence, zmin⁡=(R/2λ1)ln⁡C11/C01. From (10) and (14), variation of subband levels can be analytically obtained at various bias conditions and drain current can be readily computed by putting subband levels into (16).Figure5 shows the transfer characteristics calculated from the model and TCAD simulation. In the subthreshold region, drain current shows an exponential dependence on the gate voltage and that agrees with simulation very well. Results of different gate lengths are compared and deteriorated subthreshold characteristics in shorter channels are observed. Not only does the leakage current increase significantly, but also the drain current changes slower with the gate voltage. It indicates that the switching performance gets worse in short channel devices. Drain current characteristics for different drain biases are also shown. For devices with large channel lengths, the influence of the potential near the subband barrier by the drain bias is small (see Figure 4). Hence, the subband energy levels do not change much at different drain bias. The slight increase on the drain current for a larger drain bias is mainly due to the reduction of drain Fermi level which reduces the electron flux injecting from drain. However, for short channel device, for example, L = 10 nm, a larger drain bias leads to the increase of the potential near subband barrier and then the reduction of subband energy levels. As a consequence, the drain current increases significantly as the drain voltage increases from 0.05 V to 0.5 V (see Figures 5(a) and 5(b)). Figure 6 shows the transfer characteristics calculated from our model together with TCAD simulation results for transistors with different values of nanowire radius and gate oxide thicknesses. The agreement is quite good. It indicates that the present model can accurately predict subthreshold characteristics for different device parameters.Figure 5
Subthreshold transfer characteristics obtained from the model and TCAD simulation for different gate lengths. The other device parameters are obtained from Table1. Drain bias is (a) 0.05 V; (b) 0.5 V.
(a)
(b)Figure 6
Subthreshold transfer characteristics obtained from the model and TCAD simulation for different gate lengths. Drain bias is 0.05 V. (a) Radius is 3 nm; (b) oxide thickness is 2 nm. The other device parameters are obtained from Table1.
(a)
(b)Subthreshold slope (SS) is used to describe the steepness ofIDS-VGS characteristics. It is defined as reduction of gate voltage required to reduce drain current by one decade; that is,(18)SS=∂VGS∂log⁡IDS.Figure7(a) plots the SS, extracted from IDS-VGS curve, as a function of channel length. The newly developed model is in good agreement with the TCAD simulation. As shown in the figure SCE is still obvious in the concerned channel length range. At shorter channel lengths, the SS values are larger as a result of degraded gate control over the channel. Reducing the radius of nanowire can suppress the SS degradation for the same channel length. As the channel length increases, SS reduces closer to its lowest limit of 60 mV/dec.Figure 7
Dependence of (a) subthreshold slope and (b) threshold voltage roll-off on the gate length for different nanowire radii calculated from compact model and TCAD simulation. Drain bias is 0.05 V. Device parameters, except gate length, are listed in Table1.
(a)
(b)Threshold voltageVth is another important parameter in circuit design and is also influenced by SCE. Figure 7(b) plots the threshold voltage roll-off as a function of channel length. Here the threshold voltages were extracted from the calculated IDS-VGS characteristics. Our compact model agrees well with TCAD simulation. Threshold voltage roll-off is defined as the decrease of threshold voltage in a short channel SNT as compared with a long channel SNT. The Vth is defined as the gate voltage at which a specific drain current (Ith) is obtained [21]. In considering the different nanowire radii and the volume inversion effect of the thin nanowires [22], Ith should be proportional to the cross-sectional area of the nanowire. Here we fitted the threshold current density per unit area at 0.02 μA/nm2. As shown in Figures 5 and 6, in short SNTs, Vth is smaller and this leads to larger leakage current. As shown in Figure 7(b), the threshold voltage roll-off is larger for shorter gate length and smaller nanowire radii, representing severer SCE in these cases. As gate length gets larger, Vth tends to be independent of gate length.


## 4. Conclusion

An analytical model for the subthreshold behaviors of ballistic silicon nanowire transistors (SNTs) was developed. In this model, the electric potential was determined by solving the 2D Poisson equation with some proper approximations. Subband levels and the drain current in subthreshold regime were calculated analytically. We further extracted the threshold voltage roll-off and subthreshold swing (SS) degradation characteristics from the computed current characteristics and the trends were studied in detail. These results were validated with TCAD simulations also.



---

*Source: 605987-2015-05-31.xml*