# Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process

Authors: Avi Karsenty; Avraham Chelly
Journal: Active and Passive Electronic Components
 (2015)

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## Abstract

Nanoscale Gate-Recessed Channel (GRC) Fully Depleted- (FD-) SOI MOSFET device with a silicon channel thickness (tSi) as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K) for I-V characterizations. In spite of its FD-SOI nanoscale thickness and long channel feature, the device has surprisingly exhibited a Drain-Induced Barrier Lowering (DIBL) effect at RT. However, this effect was suppressed at 77 K. If the apparition of such anomalous effect can be explained by a parasitic short channel transistor located at the edges of the channel, its suppression is explained by the decrease of the potential barrier between the drain and the channel when lowering the temperature.


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## Body

## 1. Introduction

The Drain-Induced Barrier Lowering (DIBL) effect is a well-known phenomenon, which was reported in different types of nanoscale devices, such as in classical short-channel MOSFET devices [1] and recently in long-channel Carbon Nano Tubes (CNT) devices [2].The DIBL effect was mainly reported in short channel structures. The classical described root cause is that the channel formation is not entirely done by the gate, but now the drain and source also affect the channel formation. As the channel length decreases, the depletion regions of the source and drain come closer together and make the threshold voltage (VT) a function of the length of the channel. This is called VT roll-off. VT also becomes function of drain to source voltage VDS. As we increase VDS, the depletion regions increase in size and a considerable amount of charge is depleted by VDS. The gate voltage required to form the channel is then lowered, and thus, VT decreases with an increase in VDS. This effect is called Drain-Induced Barrier Lowering.In this paper, we report the evidence of an anomalous DIBL effect in nanoscale n-type FD-SOI MOSFET with a Gate-Recessed Channel (GRC) thickness of 2.2 nm and a long channelW/L ratio of 80/3 [μm]. Moreover, if the effect was anomalously observed at room temperature (RT) of 300 K, it completely disappeared at low temperature (LT) of 77 K. A COMSOL Multiphysics simulation picture of the device channel is shown in Figure 1. Further details about such kind of devices can be found in previous published work [3]. The initial SOI thickness before gate recess processing of the gate was 50 nm. The buried oxide (BOX) thickness is 70 nm. The gate oxide (GOX) thickness is 26 nm.Figure 1
COMSOL 3D view of the GRC device is presented, showing a channel thickness of 2.2 nm. ScaleX : Y ratio is 100 : 1.


## 2. Experimental Results and Analysis

### 2.1. Room Temperature Measurements

The transfer (IDS-VGS) characteristics of the n-type FD-SOI MOSFET were measured at room temperature (300 K) and shown in Figure 2 in a semilog scale for several VDS voltages (1, 2, 3, and 4 V).Figure 2
Transfer characteristicsIDS versus VGS for GRC device with specifications: tSi = 2.2 nm and W/L = 80 μm/3 μm, T = 300 K.For eachVDS value, the threshold voltage is extracted from the end of the weak inversion domain of the transfer characteristic for a given threshold current fixed here at 1 μA. The extracted values range stands between −1 V and −0.5 V and is linearly decreasing (in relative value) with VDS, indicating Drain-Induced Barrier Lowering (DIBL) effect as shown in Figure 3.Figure 3
Linear variation ofVT extracted from Figure 2 as a function of VDS showing the DIBL effect at 300 K.The intercept value at zeroVDS is 0.02 V, indicating that the device is almost depletion type (normally on). The DIBL coefficient σ as extracted from the slope of a linear fit of the Figure 3 is −104 mV/V. Such a DIBL effect is at a first glance surprising here since the length of the channel is relatively high (L = 3 μm) and the channel is ultrathin (tSi = 2.2 nm) with a relatively small gate oxide thickness (tox = 26 nm). Indeed, these conditions should prevent such effect as expected for FD-SOI MOSFETs [4, 5]. Indeed, the design rule for the channel length to avoid Short Channel Effects (SCE) like DIBL in a planar SOI-MOSFET is given by the following equation:(1)L≫λ=εSiεoxtSitox=13nm.For a FD-SOI MOSFET [6], a correction factor should be applied to the previous equation which turns to(2)λFD=λCfbbηCbox,where(3)1Cfbb=1Cbox+1Cfox+1CbCbox is the buried oxide capacitance (εox/tbox), Cb is the channel body capacitance (εSi/tSi), and Cfox is the front gate capacitance (εox/tox). η is the factor which depends on the substrate doping value and silicon thickness and is taken as 1 for very thin body channel [7]. According to our device’s parameters λFD is now 11 nm which is not a significant change relatively to the planar SOI MOSFET.


### 2.2. Low Temperature (77 K) Measurements

The same transfer characteristicsIDS-VGS for several VDS voltages (1, 2, 3, and 4 V) were measured at 77 K and are shown in Figure 4 in a semilog scale. The drain current is reduced to about 60 times relatively to RT.Figure 4
Transfer characteristicsIDS versus VGS for GRC device with following specifications: tSi = 2.2 nm and W/L = 80 μm/3 μm, T = 77 K.The extracted threshold voltage (VT) for a threshold current of 10 nA is now almost independent of VDS and is fixed to about −0.1 V +/− 0.1 V, meaning that the DIBL effect is suppressed by lowering the temperature. It turns also out that VT is weakly decreased by lowering the temperature from 300 K to 77 K. This result is also surprising since it is expected that VT is increased, like the Fermi potential should, by lowering the temperature for n-FD-SOI MOSFET according to [5].By confining the channel to very thin silicon, we should expect a quantization of the threshold voltage. Indeed, when the channel becomes very thin,VT will increase due to the quantum shift of the ground state energy which is inversely proportional to the square of the Si thickness like a 1D quantum well. It has been shown [8] that the uncertainty of the threshold voltage (σVT) due to quantum fluctuations is given by(4)σVT=-ħ2π2em∗tSi3σtSi,where σtSiis the channel thickness uncertainty (taken as 10% of tSi, i.e., 0.2 nm), e is the elementary charge, and m∗ is the effective mass of the first subband. In our case, σVT is found to be as low as 15 mV which is well below the experimental error.


## 2.1. Room Temperature Measurements

The transfer (IDS-VGS) characteristics of the n-type FD-SOI MOSFET were measured at room temperature (300 K) and shown in Figure 2 in a semilog scale for several VDS voltages (1, 2, 3, and 4 V).Figure 2
Transfer characteristicsIDS versus VGS for GRC device with specifications: tSi = 2.2 nm and W/L = 80 μm/3 μm, T = 300 K.For eachVDS value, the threshold voltage is extracted from the end of the weak inversion domain of the transfer characteristic for a given threshold current fixed here at 1 μA. The extracted values range stands between −1 V and −0.5 V and is linearly decreasing (in relative value) with VDS, indicating Drain-Induced Barrier Lowering (DIBL) effect as shown in Figure 3.Figure 3
Linear variation ofVT extracted from Figure 2 as a function of VDS showing the DIBL effect at 300 K.The intercept value at zeroVDS is 0.02 V, indicating that the device is almost depletion type (normally on). The DIBL coefficient σ as extracted from the slope of a linear fit of the Figure 3 is −104 mV/V. Such a DIBL effect is at a first glance surprising here since the length of the channel is relatively high (L = 3 μm) and the channel is ultrathin (tSi = 2.2 nm) with a relatively small gate oxide thickness (tox = 26 nm). Indeed, these conditions should prevent such effect as expected for FD-SOI MOSFETs [4, 5]. Indeed, the design rule for the channel length to avoid Short Channel Effects (SCE) like DIBL in a planar SOI-MOSFET is given by the following equation:(1)L≫λ=εSiεoxtSitox=13nm.For a FD-SOI MOSFET [6], a correction factor should be applied to the previous equation which turns to(2)λFD=λCfbbηCbox,where(3)1Cfbb=1Cbox+1Cfox+1CbCbox is the buried oxide capacitance (εox/tbox), Cb is the channel body capacitance (εSi/tSi), and Cfox is the front gate capacitance (εox/tox). η is the factor which depends on the substrate doping value and silicon thickness and is taken as 1 for very thin body channel [7]. According to our device’s parameters λFD is now 11 nm which is not a significant change relatively to the planar SOI MOSFET.


## 2.2. Low Temperature (77 K) Measurements

The same transfer characteristicsIDS-VGS for several VDS voltages (1, 2, 3, and 4 V) were measured at 77 K and are shown in Figure 4 in a semilog scale. The drain current is reduced to about 60 times relatively to RT.Figure 4
Transfer characteristicsIDS versus VGS for GRC device with following specifications: tSi = 2.2 nm and W/L = 80 μm/3 μm, T = 77 K.The extracted threshold voltage (VT) for a threshold current of 10 nA is now almost independent of VDS and is fixed to about −0.1 V +/− 0.1 V, meaning that the DIBL effect is suppressed by lowering the temperature. It turns also out that VT is weakly decreased by lowering the temperature from 300 K to 77 K. This result is also surprising since it is expected that VT is increased, like the Fermi potential should, by lowering the temperature for n-FD-SOI MOSFET according to [5].By confining the channel to very thin silicon, we should expect a quantization of the threshold voltage. Indeed, when the channel becomes very thin,VT will increase due to the quantum shift of the ground state energy which is inversely proportional to the square of the Si thickness like a 1D quantum well. It has been shown [8] that the uncertainty of the threshold voltage (σVT) due to quantum fluctuations is given by(4)σVT=-ħ2π2em∗tSi3σtSi,where σtSiis the channel thickness uncertainty (taken as 10% of tSi, i.e., 0.2 nm), e is the elementary charge, and m∗ is the effective mass of the first subband. In our case, σVT is found to be as low as 15 mV which is well below the experimental error.


## 3. Interpretation

We propose to interpret the previous experimental observations at 300 K and 77 K as follows.


### 3.1. Room Temperature

For a FD SOI MOSFET device the DIBL coefficientσ can be modeled by the following equation [6, 7]:(5)σ=dVTdVDS=CbbCfbbe-Leff/2λFD+2e-Leff/2λFDwith (6)1Cbb=1Cbox+1Cb.According to our device’s parameters, Cbb/Cfbb=1.37 and by solving the previous equation numerically, we can compute the value of the effective channel length (Leff = 81 nm) of the device corresponding to the extracted value of (σ = 104 mV/V).Since the field can penetrate the channel from drain and source through the buried oxide (BOX) and substrate, another term should be added to the DIBL coefficientσ defined in (5). This is called drain-induced virtual substrate biasing (DIVSB) [7] and is given by(7)DIVSB=CBD0CbCfoxCBD0+Cb,where CDB(0) is the drain to body capacitance taken at the middle of the channel. Since the body channel is very thin (2.2 nm) the Cb term is dominating such that the DIVSB is close to the CDB(0)/Cfox ratio. CDB(0) is given by the following [7]: (8)CBD0=εoxtoxeπL/2tbox-1.If we take into account the additional DIVSB term to calculate the new effective channel length, we would get a value of 83 nm which is not a significant change relatively to the former value of 81 nm. Indeed, for our long channel device, L/tbox = 3000/70, so CDB(0)~0 and then DIVSB~0.We can conclude that this device behaves like a SOI-MOSFET sharing an effective channel length of about 80 nm. This can be described like a parasitic transistor located in the vicinity of the channel edges below the gate which overwhelms the behavior of the expected long channel SOI-MOSFET device.


### 3.2. Low Temperature

On one hand, the decrease of the current at low temperature may be due to a freezing effect of the doping charge that in turn increases the series resistances located at the drain and source to channel contacts as reported in a similar device [3].On the other hand, it is well known that operating at low temperatures reduces SCE like DIBL does [9]. Indeed, in order to sustain a given subthreshold current level, which is proportional to e-qΔφ/kT, the potential barrier Δφ between the source and the surface channel is lowered by decreasing the temperature. The potential barrier will then be less sensitive to the lateral electric field into the channel, and charge sharing effects near the surface will be reduced at low temperature. Moreover, this may explain our experimental decreasing of VT by lowering the temperature.Finally, if we consider the influence of quantum confinement, as well as the temperature dependence of the effective density of states for channel thickness thinner than 10 nm [10], it has been shown that SCE should be enhanced at low temperature in opposition to the classic behavior mentioned above. So, this may confirm that the observed SCE is not connected to the quantum well confinement of the channel but rather to a classic short channel parasitic n-SOI MOSFET having at least 10 nm thickness.


## 3.1. Room Temperature

For a FD SOI MOSFET device the DIBL coefficientσ can be modeled by the following equation [6, 7]:(5)σ=dVTdVDS=CbbCfbbe-Leff/2λFD+2e-Leff/2λFDwith (6)1Cbb=1Cbox+1Cb.According to our device’s parameters, Cbb/Cfbb=1.37 and by solving the previous equation numerically, we can compute the value of the effective channel length (Leff = 81 nm) of the device corresponding to the extracted value of (σ = 104 mV/V).Since the field can penetrate the channel from drain and source through the buried oxide (BOX) and substrate, another term should be added to the DIBL coefficientσ defined in (5). This is called drain-induced virtual substrate biasing (DIVSB) [7] and is given by(7)DIVSB=CBD0CbCfoxCBD0+Cb,where CDB(0) is the drain to body capacitance taken at the middle of the channel. Since the body channel is very thin (2.2 nm) the Cb term is dominating such that the DIVSB is close to the CDB(0)/Cfox ratio. CDB(0) is given by the following [7]: (8)CBD0=εoxtoxeπL/2tbox-1.If we take into account the additional DIVSB term to calculate the new effective channel length, we would get a value of 83 nm which is not a significant change relatively to the former value of 81 nm. Indeed, for our long channel device, L/tbox = 3000/70, so CDB(0)~0 and then DIVSB~0.We can conclude that this device behaves like a SOI-MOSFET sharing an effective channel length of about 80 nm. This can be described like a parasitic transistor located in the vicinity of the channel edges below the gate which overwhelms the behavior of the expected long channel SOI-MOSFET device.


## 3.2. Low Temperature

On one hand, the decrease of the current at low temperature may be due to a freezing effect of the doping charge that in turn increases the series resistances located at the drain and source to channel contacts as reported in a similar device [3].On the other hand, it is well known that operating at low temperatures reduces SCE like DIBL does [9]. Indeed, in order to sustain a given subthreshold current level, which is proportional to e-qΔφ/kT, the potential barrier Δφ between the source and the surface channel is lowered by decreasing the temperature. The potential barrier will then be less sensitive to the lateral electric field into the channel, and charge sharing effects near the surface will be reduced at low temperature. Moreover, this may explain our experimental decreasing of VT by lowering the temperature.Finally, if we consider the influence of quantum confinement, as well as the temperature dependence of the effective density of states for channel thickness thinner than 10 nm [10], it has been shown that SCE should be enhanced at low temperature in opposition to the classic behavior mentioned above. So, this may confirm that the observed SCE is not connected to the quantum well confinement of the channel but rather to a classic short channel parasitic n-SOI MOSFET having at least 10 nm thickness.


## 4. Conclusion

Anomalous DIBL effect at 300 K and its suppression at 77 K are observed for ultrathinned Fully-Depleted Silicon-On-Insulator (FD-SOI) MOSFETs fabricated by GRC process. These trade-off phenomena are interpreted by the apparition of a dominating short channel transistor near the edges of the recessed channel and by the lowering of the potential barrier when decreasing the temperature. Such phenomena may occur in other low dimensional devices where source and drain contacts are separated from the channel by an extension region at both sides.



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*Source: 609828-2015-10-28.xml*