# Single Magnetic Element-Based High Step-Up Converter for Energy Storage and Photovoltaic System with Reduced Device Count

Authors: Muhammad Arif; Mohsin Shahzad; Qianmu Li; Jawad Saleem; Muhammad Shamrooz Aslam; Abdul Majid
Journal: Complexity
 (2020)

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## Abstract

The multiport DC-DC power converter is a prominent area of research in power electronics due to its highly dense design, reduced device count, and high energy efficiency. In this paper, a nonisolated single magnetic element-based high step-up three-port converter for an energy storage system is presented. The proposed converter has two input ports and one output port. The coupled inductor with switched capacitor is used to achieve high voltage gain. The key features of the proposed converter are high conversion gain, low voltage stress, zero voltage switching (ZVS), and zero current switching (ZCS). The detailed theoretical analysis and operation of the converter are elaborated. The energy efficiency of the proposed converter is calculated and compared with the other counterparts. Ansys Maxwell is used for the coupled inductor finite element modeling. To verify the applicability and functionality of proposed converter, a100W converter with two inputs (48V and 96V) and one output 360V at 100kHz is tested in the laboratory.


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## Body

## 1. Introduction

The photovoltaic (PV) power generation, owing to its high availability and cleanliness, is rapidly increasing with a total global capacity of627GW at the end of year 2019 [1]. The PV generation system can be operated in islanded and grid-connected mode. The islanded PV system is an optimal choice for the remote area electricity generation and distribution. However, the unpredictability of the solar energy and the electric load demand pose a challenge for the broad level exploitation of solar energy. Therefore, the PV framework needs a battery to remunerate these challenges. On the contrary, to produce 220V AC, the inverter requires input voltage of 380–400V on its DC link. As the voltage generated by the PV system is less than 50V, a step-up converter is required to keep DC link voltage constant. To address the aforementioned challenges, the power electronic converters provide best solution and efficient interface to PV source [2]. Conventionally, a separate unidirectional converter for PV is used along with a battery connected to either side of converter using bidirectional DC-DC converter. This configuration of separate converters for each source increases the system volume and cost at lower system efficiency. Therefore, various multiport converter topologies are reported in literature [3]. A multiport converter is a converter with central controls, inputs/outputs, and bidirectional ports [4]. Using multiport converter instead of standard single converters builds the system proficiency, improves components execution, and diminishes the volume and cost [2–4].A special type of multiport converter is the three-port converter (TPC) including a unidirectional port for power source, a bidirectional port for battery system, and the output port. Recent advances and topologies used for the integration of renewable sources are discussed in [5]. There are some challenges that need to be addressed in TPC such as minimum device count, high voltage gain, optimal control for power sharing, and smooth transition between operating modes. As an optimal design of the TPC, it is always desired that the converter should have minimum device count and high conversion gain. In traditional step-up converters, duty cycle is increased to achieve large step-up ratio. Increasing duty cycle beyond certain limit results in increased switching loss. The coupled inductors, transformers, multipliers, and switched capacitors are some of the various techniques used to achieve high voltage gain [5, 6].Three-port converter topologies are classified as fully isolated [7–11], partly isolated where one of the ports is isolated [12–18], and nonisolated [19–33]. The isolated structures are suitable for the high power and low frequency applications, but efficiency of these structures is usually low. The partly isolated structures are good with prominent features of high power density and efficiency. The nonisolated three-port converter topologies are preferred because of reduced size, cost, and high power density [5]. The nonisolated topologies are more suitable for standalone PV and low voltage distribution and storage system [3–5]. Recent advancements in nonisolated structures are presented in [19–33]. In [19], a series-parallel connection based on the H-bridge nonisolated converter has been proposed. A 10kW converter having input of 300V and output of 600V at a frequency of 20kHz is discussed. The converter topology can be modified by increasing its gain and reducing the device count. A nonisolated TPC converter using two inductors and switched capacitors and diodes has been proposed in [20]. The converter has comparatively high conversion gain and low voltage stress on the main operating switch. However, the converter has too many components and inductive elements leading to reduced system efficiency. A three-port high gain converter for the HEV’s applications has been addressed in [22]. To accomplish high gain, a coupled inductor along with series of the capacitors has been used. However, the topology can further be optimized by reducing the number of device count. In [23], a high gain converter using a Cockcroft–Walton multiplier method has been proposed. The converter has bigger size due to many passive components. In [24], a coupled inductor-based high step-up TPC with high conversion gain for PV integration has been proposed. However, the use of two coupled inductors results in increased size and cost. A soft switching high gain TPC with the merits of soft switching and demerits of high component count and two coupled inductors is discussed in [25]. A very simple topology of TPC based on the coupled inductor for PV system is given in [26]. The topology used only coupled inductor, and its gain depends on the turn ratio of the coupled inductor. In [27–29], the authors presented modeling and control of a three-port converter for various applications.To attain high conversion gain, one coupled inductor is used in nonisolated converter topology [30, 31]. A coupled inductor-based high gain converter is better than isolation transformer due to simpler winding structures and lower conduction losses [6]. In [30], a three-port high gain converter using a coupled inductor is introduced. The converter has the merit of high conversion gain, reduced voltage stress on the main operating switch, and soft switching. However, the converter has a coupled inductor and single inductor which increases its size. A coupled inductor with series capacitor-based high gain TPC with comparatively reduced device count and only one magnetic element has been proposed in [31]. This topology can be further improved by minimizing the device count and better design of the magnetic element. Most of the topologies reported in the literature are switched at less than 100kHz. The switching frequency of theses converter topologies can be increased and control schemes can be improved.In this paper, a three-port bidirectional converter using one coupled inductor and switched capacitor is proposed. The switching frequency is increased up to100kHz in order to shrink the size, increase power compactness, and improve the dynamic response of the converter. The proposed converter has high conversion gain and soft switching capability for the main operating switches. The analysis of the converter is performed in continuous conduction mode (CCM). The operating principle and corresponding theoretical analyses of the proposed converter in different modes are discussed in detail. The presented work is based on [32, 33], with the following vital modifications and extensions:(1)
Novel converter topology with reduced device count(2)
Reduction in size and cost by increasing switching frequency up to100kHz(3)
Finite element modeling of coupled inductor in order to improve the design(4)
Operation of converter in different modes(5)
Loss and efficiency analyses(6)
Development of lab prototype and presentation of measured resultsThe introduction and comprehensive summary of various converter topologies are presented inSection 1, followed by the operation and analysis of the proposed converter in Section 2. The detailed proposed design and the control scheme are elaborated in Section 3 and 4, respectively. The experimental results, loss and efficiency analyses, and comparison are given in Section 5. Lastly, the overall work is concluded in Section 6.


## 2. Operation and Analysis of the Proposed Topology

The proposed converter, comprised of one unidirectional port for PV and two bidirectional ports, is presented in Figure1. The proposed converter comprises four active switches S1, S2, S3, and S4 and four diodes Dpv, Db, Dc2, and Dc. The proposed converter has three capacitors: clamp capacitor C1, switch capacitor C2, and output capacitor Cm. The proposed converter structure has only one coupled inductor. The coupled inductor along with switch capacitor C2 is used to achieve high voltage conversion gain at output port. In order to diminish the voltage stress on the fundamental switch S1, the active clamp circuit is used. The primary winding of the coupled inductor is common between the inputs, i.e., battery and PV system. The proposed converter has the bidirectional power flow ability along with intersource power-sharing. The switch S1 is the main operating switch and remains active most of the time. The switches S2 and S3 are used for boost and buck operations, respectively. The switch S4 is used to control power between the PV and battery system. The converter operation is discussed for single-input single-output (SISO), double-input single-output (DISO), and single-input double-output (SIDO) modes. Large value capacitors are used to maintain constant voltage. The detailed operation of the converter in different operating modes is explained in the following sections.Figure 1
Proposed three-port converter.


### 2.1. Converter Operation in SISO Mode

In SISO mode, there are two modes of operation; buck and boost. In boost operation, the battery/PV provides power to the load, whereas in buck operation, the battery is charged from the DC link capacitor.


#### 2.1.1. Boost Operation

In this mode, the power is transferred to the load either by the battery or from the PV. For a single switching cycle, the converter has five operating states. The theoretical switching waveform and current flow paths in CCM are presented in Figure2(a). The detailed operation of the converter in five states is illustrated.Figure 2
Steady-state theoretical waveform. (a) SISO mode (boost operation). (b) SISO mode (buck operation). (c) DISO mode. (d) SIDO mode.
(a)(b)(c)(d)Figure 3
Steady-state equivalent circuits and current flow of the converter in SISO mode (boost operation). (a)t0∼t1. (b) t1∼t2. (c) t2∼t3. (d) t3∼t4. (e) t4∼t5.
(a)(b)(c)(d)(e)State-I [t0∼t1] (Figure 3(a)): this is a very short interval; the switch S1 is turned on at t0, S2 is on, and the switches S3 and S4 are off. The current ilk increases linearly and it is equal to the magnetizing inductance current ilm at time t1. The net current passing through the primary side is ilm−ilk. The secondary side current iLS is equal to n×ilm−ilk which decreases linearly and is equal to zero at time t1. The diodes D3, Db, and Dpv are reverse biased.State-II [t1∼t2] (Figure 3(b)): in this interval, both the switches S1 and S2 are on. The current ilm is increasing linearly. The current iLS is also increasing linearly but in opposite direction. As the current direction and voltage polarity are reversed on both sides of the coupled inductor, the capacitor C1 is charging the switched capacitor C2 through the diode Dc2. The current idc2 increases until it equals iLS at time t2.State-III [t2∼t3] (Figure 3(c)): at time t2, the switch S1 is turned off. The leakage inductance energy is transferred to the capacitor C1. The voltage over the switch S1 is clamped to Vds1. The currents idc and idc2 through the diodes Dc and Dc2 decrease. As this is a very short interval, the current direction and voltage polarities over the coupled inductor remain unchanged.State-IV [t3∼t4] (Figure 3(d)): for this interval, the switch S2 is on and the switch S1 is off. The current direction and the voltage polarities change over the coupled inductor. The diode Dc is forward biased and current idc decreases. At time t4, the current idc become zero, and the diode Dc is reverse biased.State-V [t4∼t5] (Figure 3(e)): the switch S1 is off, whereas switch S2 is still on. At time t4, the diode Dc is turned off. The current direction is the same in both primary and secondary windings of the coupled inductor. The magnetizing current ilm is decreasing. The energy from the battery, magnetizing inductor Lm, and the leakage inductor Llk along with the capacitor C2 is delivered to the load.


#### 2.1.2. Buck Operation

In SISO mode, the input is main DC link capacitor and the output is battery. The large value DC link capacitor is used. In this mode, the main operating switch isS3. The theoretical waveforms for this mode are presented in Figure 2(b). For one complete cycle, the operation the converter is explained for the following time intervals.State-I [t0∼t1]: this is a very short interval; the switch S3 is turned on. The magnetizing current ilm and leakage current ilk are decreasing and the switch S3 is turned on at almost zero current flowing through it.State-II [t1∼t2] (Figure 4(a)): in this interval, the switch S3 is on. The coupled inductor magnetizing current ilm is increasing in opposite direction. The current ilm is charging the inductor Lm. The interval ends at time t2.State-III [t2∼t3] (Figure 4(b)): at the end of time t2, the switch S3 is turned off. Initially, current idc increases abruptly and then becomes zero at time t3. This interval ends at t3.State-IV [t3∼t4] (Figure 4(c)): at time t3, the diode Dc2 conducts and switch S3 is off. The current idc2 increases and becomes zero at time t2.State-V [t4∼t5] (Figure 4(d)): in this interval, the switch S3 is still off. The magnetizing current ilm charges the battery through the body diode D1. This interval ends at time t5.Figure 4
Steady-state equivalent circuits and current flow of the converter in SISO mode (buck operation). (a)t1∼t2. (b) t2∼t3. (c) t3∼t4. (d) t4∼t5.
(a)(b)(c)(d)


### 2.2. Converter Operation in DISO Mode

During this mode, the PV power is not enough to fulfill the load requirement. The additional power is supplied to the load from the battery by controlling the switchS3. During this dual-input single-output (DISO) mode, both PV and battery provide power to load. The theoretical waveforms and current flow paths are presented in Figures 2(c) and 5, respectively. The operation of the converter during this mode is explained in six states.State-I [t0∼t1] (Figure 5(a)): at time t0, switches S1 and S2 are turned on. The leakage current iLk is almost zero, and the current iLS is changing its direction. The switches S1, and S2 are turned on under almost zero current. This state is similar to state-1 of the SISO mode. All the relationships and equations are same for this state.State-II [t1∼t2] (Figure 5(b)): this state is similar to state-II of the SISO mode. All the relationships and equations are same for this state.State-III [t2∼t3] (Figure 5(c)): the switch S1 is still on while at the end of time t3, the switch S2 is turned off. The diode Dpv is forward biased, and the current ipv increases. The current ib decreases linearly and is zero at time t3. The primary voltage of the coupled inductor has been decreased from its previous value.State-IV [t3∼t4] (Figure 5(d)): in this state, inductor Lm is charged through by the PV source. The switch S4 is still on and the current ilm increases linearly with a slope of Vpv/Lm.State-V [t4∼t5] (Figure 5(e)): at the end of time t4, the switch S1 is turned off and the diode Dc is forward biased. The voltage Vds1 over the switch S1 clamps to the voltage Vc1.State-VI [t6∼t7] (Figure 5(f)): all the switches are off, PV is delivering power to the load, and voltage Vpv is boosted to V0. This state is similar to state-V of the SISO mode except the switch S2 is off and diode Dpv is turned on.Figure 5
Steady-state equivalent circuits and current flow of the converter in DISO mode. (a)t0∼t1. (b) t1∼t2. (c) t2∼t3. (d) t3∼t4. (e) t4∼t5. (f) t5∼t6.
(a)(b)(c)(d)(e)(f)


### 2.3. Converter Operation in SIDO Mode

In this mode, the PV generation is greater than the load requirement and excess energy is used to charge the battery. The theoretical switching characteristics are presented in Figure2(d). The switches S1 and S4 are active in this mode. The operation of the converter in different states is discussed as follows.State-I [t0∼t1] (Figure 6(a)): at time t0, the switches S1 and S4 are turned on. The current ilk decreases linearly and tends to reach zero, consequently turning on both S1 and S4 at ZCS. The operation of the converter in this state is similar to its operation in state-1 of SISO mode.State-II [t1∼t2] (Figure 6(b)): in this state, the operation of the converter is similar to the operation of state-1 of SISO mode except the source. All relationships and equations are valid for this state.State-III [t2∼t3] (Figure 6(c)): at time t2, the switch S1 is turned off while the switch S4 is still on. The current ilk and the magnetizing current ilm decrease linearly. At time t3, the current iLS becomes zero.State-IV [t3∼t4] (Figure 6(d)): at time t3, the switch S4 is still on. The leakage ilk and magnetizing ilm currents are equal while the secondary current ils is zero. The magnetizing current ilm is used to charge the battery through the diode Db and switch S4. The battery charge current ich is controlled by the duty cycle D4. The slope of ilm is equal to Vbat−Vpv/Lm. The state ends at time t4 when the switch S4 is turned off.State-V [t4∼t5] (Figure 6(e)): the switches S1 and S4 are turned off. The diode Dc conducts, transferring the leakage inductance Llk energy to the clamping capacitor C1. This state ends at time t5.State-VI [t5∼t6] (Figure 6(f)): all switches are off. The operation of the converter in this state is similar to state-V of the SISO mode. The only difference is that the diode Dpv conducts and the source is PV. All the relationships and equations are similar to state-V of SISO mode for this state.Figure 6
Steady-state equivalent circuits and current flow of the converter in SIDO mode. (a)t0∼t1. (b) t1∼t2. (c) t2∼t3. (d) t3∼t4. (e) t4∼t5. (f) t5∼t6.
(a)(b)(c)(d)(e)(f)


## 2.1. Converter Operation in SISO Mode

In SISO mode, there are two modes of operation; buck and boost. In boost operation, the battery/PV provides power to the load, whereas in buck operation, the battery is charged from the DC link capacitor.


### 2.1.1. Boost Operation

In this mode, the power is transferred to the load either by the battery or from the PV. For a single switching cycle, the converter has five operating states. The theoretical switching waveform and current flow paths in CCM are presented in Figure2(a). The detailed operation of the converter in five states is illustrated.Figure 2
Steady-state theoretical waveform. (a) SISO mode (boost operation). (b) SISO mode (buck operation). (c) DISO mode. (d) SIDO mode.
(a)(b)(c)(d)Figure 3
Steady-state equivalent circuits and current flow of the converter in SISO mode (boost operation). (a)t0∼t1. (b) t1∼t2. (c) t2∼t3. (d) t3∼t4. (e) t4∼t5.
(a)(b)(c)(d)(e)State-I [t0∼t1] (Figure 3(a)): this is a very short interval; the switch S1 is turned on at t0, S2 is on, and the switches S3 and S4 are off. The current ilk increases linearly and it is equal to the magnetizing inductance current ilm at time t1. The net current passing through the primary side is ilm−ilk. The secondary side current iLS is equal to n×ilm−ilk which decreases linearly and is equal to zero at time t1. The diodes D3, Db, and Dpv are reverse biased.State-II [t1∼t2] (Figure 3(b)): in this interval, both the switches S1 and S2 are on. The current ilm is increasing linearly. The current iLS is also increasing linearly but in opposite direction. As the current direction and voltage polarity are reversed on both sides of the coupled inductor, the capacitor C1 is charging the switched capacitor C2 through the diode Dc2. The current idc2 increases until it equals iLS at time t2.State-III [t2∼t3] (Figure 3(c)): at time t2, the switch S1 is turned off. The leakage inductance energy is transferred to the capacitor C1. The voltage over the switch S1 is clamped to Vds1. The currents idc and idc2 through the diodes Dc and Dc2 decrease. As this is a very short interval, the current direction and voltage polarities over the coupled inductor remain unchanged.State-IV [t3∼t4] (Figure 3(d)): for this interval, the switch S2 is on and the switch S1 is off. The current direction and the voltage polarities change over the coupled inductor. The diode Dc is forward biased and current idc decreases. At time t4, the current idc become zero, and the diode Dc is reverse biased.State-V [t4∼t5] (Figure 3(e)): the switch S1 is off, whereas switch S2 is still on. At time t4, the diode Dc is turned off. The current direction is the same in both primary and secondary windings of the coupled inductor. The magnetizing current ilm is decreasing. The energy from the battery, magnetizing inductor Lm, and the leakage inductor Llk along with the capacitor C2 is delivered to the load.


### 2.1.2. Buck Operation

In SISO mode, the input is main DC link capacitor and the output is battery. The large value DC link capacitor is used. In this mode, the main operating switch isS3. The theoretical waveforms for this mode are presented in Figure 2(b). For one complete cycle, the operation the converter is explained for the following time intervals.State-I [t0∼t1]: this is a very short interval; the switch S3 is turned on. The magnetizing current ilm and leakage current ilk are decreasing and the switch S3 is turned on at almost zero current flowing through it.State-II [t1∼t2] (Figure 4(a)): in this interval, the switch S3 is on. The coupled inductor magnetizing current ilm is increasing in opposite direction. The current ilm is charging the inductor Lm. The interval ends at time t2.State-III [t2∼t3] (Figure 4(b)): at the end of time t2, the switch S3 is turned off. Initially, current idc increases abruptly and then becomes zero at time t3. This interval ends at t3.State-IV [t3∼t4] (Figure 4(c)): at time t3, the diode Dc2 conducts and switch S3 is off. The current idc2 increases and becomes zero at time t2.State-V [t4∼t5] (Figure 4(d)): in this interval, the switch S3 is still off. The magnetizing current ilm charges the battery through the body diode D1. This interval ends at time t5.Figure 4
Steady-state equivalent circuits and current flow of the converter in SISO mode (buck operation). (a)t1∼t2. (b) t2∼t3. (c) t3∼t4. (d) t4∼t5.
(a)(b)(c)(d)


## 2.1.1. Boost Operation

In this mode, the power is transferred to the load either by the battery or from the PV. For a single switching cycle, the converter has five operating states. The theoretical switching waveform and current flow paths in CCM are presented in Figure2(a). The detailed operation of the converter in five states is illustrated.Figure 2
Steady-state theoretical waveform. (a) SISO mode (boost operation). (b) SISO mode (buck operation). (c) DISO mode. (d) SIDO mode.
(a)(b)(c)(d)Figure 3
Steady-state equivalent circuits and current flow of the converter in SISO mode (boost operation). (a)t0∼t1. (b) t1∼t2. (c) t2∼t3. (d) t3∼t4. (e) t4∼t5.
(a)(b)(c)(d)(e)State-I [t0∼t1] (Figure 3(a)): this is a very short interval; the switch S1 is turned on at t0, S2 is on, and the switches S3 and S4 are off. The current ilk increases linearly and it is equal to the magnetizing inductance current ilm at time t1. The net current passing through the primary side is ilm−ilk. The secondary side current iLS is equal to n×ilm−ilk which decreases linearly and is equal to zero at time t1. The diodes D3, Db, and Dpv are reverse biased.State-II [t1∼t2] (Figure 3(b)): in this interval, both the switches S1 and S2 are on. The current ilm is increasing linearly. The current iLS is also increasing linearly but in opposite direction. As the current direction and voltage polarity are reversed on both sides of the coupled inductor, the capacitor C1 is charging the switched capacitor C2 through the diode Dc2. The current idc2 increases until it equals iLS at time t2.State-III [t2∼t3] (Figure 3(c)): at time t2, the switch S1 is turned off. The leakage inductance energy is transferred to the capacitor C1. The voltage over the switch S1 is clamped to Vds1. The currents idc and idc2 through the diodes Dc and Dc2 decrease. As this is a very short interval, the current direction and voltage polarities over the coupled inductor remain unchanged.State-IV [t3∼t4] (Figure 3(d)): for this interval, the switch S2 is on and the switch S1 is off. The current direction and the voltage polarities change over the coupled inductor. The diode Dc is forward biased and current idc decreases. At time t4, the current idc become zero, and the diode Dc is reverse biased.State-V [t4∼t5] (Figure 3(e)): the switch S1 is off, whereas switch S2 is still on. At time t4, the diode Dc is turned off. The current direction is the same in both primary and secondary windings of the coupled inductor. The magnetizing current ilm is decreasing. The energy from the battery, magnetizing inductor Lm, and the leakage inductor Llk along with the capacitor C2 is delivered to the load.


## 2.1.2. Buck Operation

In SISO mode, the input is main DC link capacitor and the output is battery. The large value DC link capacitor is used. In this mode, the main operating switch isS3. The theoretical waveforms for this mode are presented in Figure 2(b). For one complete cycle, the operation the converter is explained for the following time intervals.State-I [t0∼t1]: this is a very short interval; the switch S3 is turned on. The magnetizing current ilm and leakage current ilk are decreasing and the switch S3 is turned on at almost zero current flowing through it.State-II [t1∼t2] (Figure 4(a)): in this interval, the switch S3 is on. The coupled inductor magnetizing current ilm is increasing in opposite direction. The current ilm is charging the inductor Lm. The interval ends at time t2.State-III [t2∼t3] (Figure 4(b)): at the end of time t2, the switch S3 is turned off. Initially, current idc increases abruptly and then becomes zero at time t3. This interval ends at t3.State-IV [t3∼t4] (Figure 4(c)): at time t3, the diode Dc2 conducts and switch S3 is off. The current idc2 increases and becomes zero at time t2.State-V [t4∼t5] (Figure 4(d)): in this interval, the switch S3 is still off. The magnetizing current ilm charges the battery through the body diode D1. This interval ends at time t5.Figure 4
Steady-state equivalent circuits and current flow of the converter in SISO mode (buck operation). (a)t1∼t2. (b) t2∼t3. (c) t3∼t4. (d) t4∼t5.
(a)(b)(c)(d)


## 2.2. Converter Operation in DISO Mode

During this mode, the PV power is not enough to fulfill the load requirement. The additional power is supplied to the load from the battery by controlling the switchS3. During this dual-input single-output (DISO) mode, both PV and battery provide power to load. The theoretical waveforms and current flow paths are presented in Figures 2(c) and 5, respectively. The operation of the converter during this mode is explained in six states.State-I [t0∼t1] (Figure 5(a)): at time t0, switches S1 and S2 are turned on. The leakage current iLk is almost zero, and the current iLS is changing its direction. The switches S1, and S2 are turned on under almost zero current. This state is similar to state-1 of the SISO mode. All the relationships and equations are same for this state.State-II [t1∼t2] (Figure 5(b)): this state is similar to state-II of the SISO mode. All the relationships and equations are same for this state.State-III [t2∼t3] (Figure 5(c)): the switch S1 is still on while at the end of time t3, the switch S2 is turned off. The diode Dpv is forward biased, and the current ipv increases. The current ib decreases linearly and is zero at time t3. The primary voltage of the coupled inductor has been decreased from its previous value.State-IV [t3∼t4] (Figure 5(d)): in this state, inductor Lm is charged through by the PV source. The switch S4 is still on and the current ilm increases linearly with a slope of Vpv/Lm.State-V [t4∼t5] (Figure 5(e)): at the end of time t4, the switch S1 is turned off and the diode Dc is forward biased. The voltage Vds1 over the switch S1 clamps to the voltage Vc1.State-VI [t6∼t7] (Figure 5(f)): all the switches are off, PV is delivering power to the load, and voltage Vpv is boosted to V0. This state is similar to state-V of the SISO mode except the switch S2 is off and diode Dpv is turned on.Figure 5
Steady-state equivalent circuits and current flow of the converter in DISO mode. (a)t0∼t1. (b) t1∼t2. (c) t2∼t3. (d) t3∼t4. (e) t4∼t5. (f) t5∼t6.
(a)(b)(c)(d)(e)(f)


## 2.3. Converter Operation in SIDO Mode

In this mode, the PV generation is greater than the load requirement and excess energy is used to charge the battery. The theoretical switching characteristics are presented in Figure2(d). The switches S1 and S4 are active in this mode. The operation of the converter in different states is discussed as follows.State-I [t0∼t1] (Figure 6(a)): at time t0, the switches S1 and S4 are turned on. The current ilk decreases linearly and tends to reach zero, consequently turning on both S1 and S4 at ZCS. The operation of the converter in this state is similar to its operation in state-1 of SISO mode.State-II [t1∼t2] (Figure 6(b)): in this state, the operation of the converter is similar to the operation of state-1 of SISO mode except the source. All relationships and equations are valid for this state.State-III [t2∼t3] (Figure 6(c)): at time t2, the switch S1 is turned off while the switch S4 is still on. The current ilk and the magnetizing current ilm decrease linearly. At time t3, the current iLS becomes zero.State-IV [t3∼t4] (Figure 6(d)): at time t3, the switch S4 is still on. The leakage ilk and magnetizing ilm currents are equal while the secondary current ils is zero. The magnetizing current ilm is used to charge the battery through the diode Db and switch S4. The battery charge current ich is controlled by the duty cycle D4. The slope of ilm is equal to Vbat−Vpv/Lm. The state ends at time t4 when the switch S4 is turned off.State-V [t4∼t5] (Figure 6(e)): the switches S1 and S4 are turned off. The diode Dc conducts, transferring the leakage inductance Llk energy to the clamping capacitor C1. This state ends at time t5.State-VI [t5∼t6] (Figure 6(f)): all switches are off. The operation of the converter in this state is similar to state-V of the SISO mode. The only difference is that the diode Dpv conducts and the source is PV. All the relationships and equations are similar to state-V of SISO mode for this state.Figure 6
Steady-state equivalent circuits and current flow of the converter in SIDO mode. (a)t0∼t1. (b) t1∼t2. (c) t2∼t3. (d) t3∼t4. (e) t4∼t5. (f) t5∼t6.
(a)(b)(c)(d)(e)(f)


## 3. Steady-State Analysis and Design Considerations

Averaging of the converter in each mode is performed by applying voltage-second balance on magnetizing currentilm equations, whereas the ampere-second method is used on all capacitors’ voltage equations. The steady-state analysis results for each mode are elaborated in SISO, DISO, and SIDO modes.


### 3.1. SISO Mode

#### 3.1.1. Boost Operation

By applying the voltage-second balance on the magnetizing inductanceLm, the voltage over the magnetizing inductor is calculated according to the following equation:(1)Vlm=d1×Vbat1−d1.The voltages across the capacitorsC1 and C2 are computed according to equations (2) and (3), respectively.(2)VC1=Vbat1−d1,(3)VC2=n+2×Vbat1−d1.The steady-state voltage across the capacitorCm is computed by using the following equation:(4)Vcm=Vbat+VLm+nVLm+Vc2.The output voltageV0 across the load is computed by using the following equation:(5)V0=Vbat×2+n+d11+n1−d1.The converter gain increases significantly by increasing the duty cycle and the turn ratio “n” of the coupled inductor. Change in the output voltage V0 with the change in duty cycle d1 in SISO mode is presented in Figure 7(a). The comparison of output voltage and the input voltage at various values of the turn ratio “n” is presented in Figure 7(b). This shows that the output voltage increases linearly with the input voltage. The proposed converter has the gain of 8.Figure 7
(a) Converter output vs duty cycle (d1) in SISO mode. (b) Output vs input voltage in SISO mode with different values of “n.”
(a)(b)From the analysis, it is observed that for both the inputs (PV and battery), the voltage across the load will remain the same. The switchS1 is used to control the output voltage for both the inputs PV and battery.


#### 3.1.2. Buck Operation

In this mode, the battery is charged from the main DC link capacitor. The main operating switch is S3. For the steady-state operation in this mode, the voltage-second balance on the magnetizing currentilm is applied. The steady-state voltage, when the battery is charged from the DC link capacitor, is given in the following equation:(6)Vbat=Vcm×d3n+2,where Vcm=V0.


### 3.2. DISO Mode

For this mode, the voltage-second balance on the magnetizing inductance is applied. The voltage across the magnetizing inductance is computed by using the following equation:(7)Vlm=Vpv×d1−d2+Vbat×d21−d1.The voltageVC1 across the capacitor C1 is computed by the following equation:(8)Vc1=Vpv−d2×Vpv+d2×Vbat1−d1.The voltageVC2 across the capacitor C2 is determined by the following equation:(9)Vc2=Vpv×1+nd1−d3n+2+Vch1−d1,where Vch=Vbatd2n+1+n1−d1.The output voltageV0 across the capacitor Cm is computed by using the following equation:(10)V0=Vpvnew×Vpvd1−d2+Vbat×d31−d1,where Vpvnew=2Vpv+n×Vbat+2n+2.


### 3.3. SIDO Mode

For the calculation of conversion ratio, we are applying voltage-second balance. In this mode, the only input is PV. To calculate the conversion ratio, voltage-second balance is applied on the magnetizing inductanceLm. The voltage across Lm is calculated by using the following equation:(11)Vlm=Vpv×d4−Vbatd4−d11−d2.The voltage across the capacitorsC1, C2, and Cm is calculated by using equations (12)–(14), respectively.(12)Vc1=Vpv−Vbatd4−d11−d4,(13)Vc2=n+2Vpv−Vbatd4−d11−d4.The output voltage over the capacitorCm is calculated by using the following equation:(14)V0=n3+d4Vpv−3n+2d4−d1Vbat1−d4.


### 3.4. Design Consideration

The design specifications of the proposed converter are given in Table1. The main components used in the converter design are coupled inductor, power MOSFETs, capacitors, and diodes. The appropriate selection of coupled inductor, capacitors, and power semiconductor devices is very crucial for the desired operation of the converter.Table 1
Parameters’ symbols and values/components used for prototype and simulation.
ParametersSymbolsValuesInput source-1Vpv48VBattery voltageVbat96VOutput voltageV0380VPrimary inductor (DCM)Lp5.01uHSecondary inductor (DCM)Ls20.043uHPrimary inductor (CCM)Lp25uHSecondary inductor (CCM)Ls100.043uHPeak primary inductor currentILp16ALoad currentILoad0.263AClamp capacitorC15uF, 250 VSeries capacitorC22uF, 250 VSeries capacitorC2uF, 250 VMain DC link capacitorCm300uFLoad resistorRload680ΩMOSFETsS1,S2, S3FQA34N20MOSFETsS4G32N500DiodeDcMBR20200CTDiodeDc2MUR840DiodeDb, DPVMBR4060PTSwitching frequencyfreq100kHzOutput powerP0100W


#### 3.4.1. Coupled Inductor Design

The required parameters of the coupled inductor used in the converter topology are given in Table1. The equivalent inductance is Leq=Lp+Ls+2M, where M is the mutual inductance. The number of turns for the required inductance value of the Lp is calculated by using equation (15). The required peak inductor current is 6.165A, and the duty cycle d1=0.6. For 100W, the core ETD-39 and wire AWG-14 are selected. The peak ILpk primary inductor current is calculated using equation (16). The peak to peak primary inductor current is 2ILP . The peak current IDpk through diode D3 is calculated by using equation (17). The relationship between ILpk and Iout is expressed in equation (18). The required values of the coupled inductor are Lp=5uH and Ls=20uH for DCM operation. For the CCM operation, inductor values are Lp=25uH and Ls=100uH.(15)Bmax=Ueff⋅U0⋅N12⋅ImaxLe,where N67 material is used which has the following properties: Ueff=1590, Ae=97.1mm2, Le=78.8mm, and Bmax = maximum flux density.(16)ILpk=VpvLP×d1T,(17)IDpk=V0−Vpv×2+n−Vc2Leq×1−D1T,(18)ILpk=Iout×2+n+d11+n1−d1,(19)Iout=IDpk1−d12.The primary inductance value and its losses are calculated by using equations (20) and (21), respectively. The magnetizing inductance can be calculated by using equation (22).(20)Lp=Vpv2+n2×Iout×d11−d1T,(21)LPloss=RESR×n+11−d1×Iout2,(22)Lm=n×d1×Vpvfs×Δilp.The secondary inductor value is calculated by using the relationshipLs=n2⋅Lp, where n=N1/N2=L1/L2. Here, N1 is the number of turns on the primary side and N2 is the number of turns on the secondary side. The coupling coefficient between the primary and secondary inductors is calculated by using equation (23), where as the power loss in secondary inductor is calculated by equation (24).(23)k=MLp×Ls,(24)LSloss=RESR×n+11−d1×Iout2.The leakage inductance value on the primary side can be calculated by equation (25), where fr is the resonance frequency and the Couts1 is the output capacitance of the switch S1.(25)Llk=12⋅πfr2⋅Couts1.The finite element model of the coupled inductor is developed in Ansys Maxwell 3D by using PExprt tool. The coupled inductor’s Ansys analysis report for both the DCM and CCM operations is given in Tables2 and 3, respectively. In Table 2, the coupled inductor performance results are shown for the DCM mode. The results show the primary and secondary inductance (Lp and Ls) values of 5uH and 20uH, respectively, with turn ratio n=2. The current density is found to be 13.39A/mm2 for Lp and 3.58A/mm2 for Ls with the losses of 2.4W and 438.5mW for Lp and Ls, respectively. The value of Rdc is found to be 7.85Ω and 20.14Ω for Lp and Ls, respectively. The total losses for DCM mode are 4.455W, and window filling is 36.74% and 73.1% for Lp and Ls, respectively. Similarly, the coupled inductor performance results for CCM mode are shown in Table 3. The values of the current density, coupled inductor, losses in primary and secondary windings are shown. The DC resistance value of the used wire is Rdc = 3.353mΩ. Moreover, the losses in the core and winding are expressed as 971.142mW and 200.684mW, respectively. Furthermore, the window occupancy for both primary and secondary winding is obtained as 31.09% and 55.72%, respectively.Table 2
Ansys Maxwell analysis report: coupled inductor performance results (DCM).
Primary inductor (Lp)Secondary inductor (Ls)Current density13.39A/mm23.579A/mm2Inductance5.01uH20.043uHLosses2.405W438.504mWRdc7.857Ω20.144mΩLossesLosses (winding)3.360WLosses (core)95.104mWTotal losses4.455WWindow occupancyWindow filling (%)36.7473.10Table 3
Ansys Maxwell analysis report: coupled inductor performance results (CCM).
Primary inductor (Lp)Secondary inductor (Ls)Current density2.88A/mm21.22A/mm2Inductance25.00uH100.043uHLosses815.77mW119.917mWRdc3.353mΩ29.379mΩLossesLosses (winding)200.684mWLosses (core)971.142mWTotal losses1.172WWindow occupancyWindow filling (%)31.0955.72The finite element model (FEM) of coupled inductor for magnetic flux density is presented in Figure8(a), whereas the FEM for the magnetic flux lines is presented in Figure 8(b).Figure 8
FEM. (a) Magnetic flux density. (b) Magnetic flux lines.
(a)(b)


#### 3.4.2. Capacitor Selection

Three capacitors used in this topology are the clamping capacitorC1, the switched capacitor C2, and DC link capacitor Cm. Equation (26) gives the relationship between the clamp capacitor C1 and the input voltage Vbat.(26)Vc1=Vbat1−d1.The blocking voltage over the switchS1 is expressed in the following equation:(27)VDS1=Vbat1−d1.The minimum value of the capacitorsC1 and C2 is calculated by using equations (28) and (29), where as the value of the output capacitor Cm is determined by equation (30). The voltage across the capacitor C2 is determined by equation (31).(28)C1min≥Vbat×d1⋅T2×Rdson1×ΔVc1,(29)C2min≥Vc1×d1⋅T2×Rdson1×ΔVc2,(30)Cm≥Vpv×d1×T2×Rload×ΔVcm,(31)Vc2=Vpv×−1+2⋅d1+2+n1+n1−d11−d1.


#### 3.4.3. Selection of Switches and Diodes

The switchesS1, S2, and S4 have low voltage blocking capability while switch S3 has high voltage blocking capability. The maximum voltage stress across the main switch S1 and the diode Dc is calculated by the following equation:(32)Vds1=Vin1−d1,where Vin is the input voltage at PV or battery port. The switch S3 and the diode Dc2 bear maximum voltage stress, and it can be expressed as follows:(33)Vds3=Vin×2+n+d11+n1−d1.The voltage stress across the switchS2 and the diode Dpv is expressed as follows:(34)Vds2=Vbat−1+nVlp+Vc2+V0,whereas the voltage stress across the switch S4 and the diode D6 is given as follows:(35)Vds4=Vbat−Vd6+Vc1.The maximum current stress across the switches and diodes of the proposed converter occurs if only one source is serving the load. The current stress on the switchesS1 and S2 and the diodes Dpv and Dc is equal to ILpk as expressed in equation (18). The current stress on the switch S3 is equal to IDpk and is express in equation (20). The peak current through the diode Dc2 is Idp = IDpk/n, where IDpk is expressed in equation (17).A fast recovery diode is selected forDc, and an ultrafast recovery diode is chosen for Dc2, whereas the ordinary rectifier diodes with required current and voltage blocking capability are selected for Dpv and Db. The ratings of components used in simulation or prototype are given in Table 1.


## 3.1. SISO Mode

### 3.1.1. Boost Operation

By applying the voltage-second balance on the magnetizing inductanceLm, the voltage over the magnetizing inductor is calculated according to the following equation:(1)Vlm=d1×Vbat1−d1.The voltages across the capacitorsC1 and C2 are computed according to equations (2) and (3), respectively.(2)VC1=Vbat1−d1,(3)VC2=n+2×Vbat1−d1.The steady-state voltage across the capacitorCm is computed by using the following equation:(4)Vcm=Vbat+VLm+nVLm+Vc2.The output voltageV0 across the load is computed by using the following equation:(5)V0=Vbat×2+n+d11+n1−d1.The converter gain increases significantly by increasing the duty cycle and the turn ratio “n” of the coupled inductor. Change in the output voltage V0 with the change in duty cycle d1 in SISO mode is presented in Figure 7(a). The comparison of output voltage and the input voltage at various values of the turn ratio “n” is presented in Figure 7(b). This shows that the output voltage increases linearly with the input voltage. The proposed converter has the gain of 8.Figure 7
(a) Converter output vs duty cycle (d1) in SISO mode. (b) Output vs input voltage in SISO mode with different values of “n.”
(a)(b)From the analysis, it is observed that for both the inputs (PV and battery), the voltage across the load will remain the same. The switchS1 is used to control the output voltage for both the inputs PV and battery.


### 3.1.2. Buck Operation

In this mode, the battery is charged from the main DC link capacitor. The main operating switch is S3. For the steady-state operation in this mode, the voltage-second balance on the magnetizing currentilm is applied. The steady-state voltage, when the battery is charged from the DC link capacitor, is given in the following equation:(6)Vbat=Vcm×d3n+2,where Vcm=V0.


## 3.1.1. Boost Operation

By applying the voltage-second balance on the magnetizing inductanceLm, the voltage over the magnetizing inductor is calculated according to the following equation:(1)Vlm=d1×Vbat1−d1.The voltages across the capacitorsC1 and C2 are computed according to equations (2) and (3), respectively.(2)VC1=Vbat1−d1,(3)VC2=n+2×Vbat1−d1.The steady-state voltage across the capacitorCm is computed by using the following equation:(4)Vcm=Vbat+VLm+nVLm+Vc2.The output voltageV0 across the load is computed by using the following equation:(5)V0=Vbat×2+n+d11+n1−d1.The converter gain increases significantly by increasing the duty cycle and the turn ratio “n” of the coupled inductor. Change in the output voltage V0 with the change in duty cycle d1 in SISO mode is presented in Figure 7(a). The comparison of output voltage and the input voltage at various values of the turn ratio “n” is presented in Figure 7(b). This shows that the output voltage increases linearly with the input voltage. The proposed converter has the gain of 8.Figure 7
(a) Converter output vs duty cycle (d1) in SISO mode. (b) Output vs input voltage in SISO mode with different values of “n.”
(a)(b)From the analysis, it is observed that for both the inputs (PV and battery), the voltage across the load will remain the same. The switchS1 is used to control the output voltage for both the inputs PV and battery.


## 3.1.2. Buck Operation

In this mode, the battery is charged from the main DC link capacitor. The main operating switch is S3. For the steady-state operation in this mode, the voltage-second balance on the magnetizing currentilm is applied. The steady-state voltage, when the battery is charged from the DC link capacitor, is given in the following equation:(6)Vbat=Vcm×d3n+2,where Vcm=V0.


## 3.2. DISO Mode

For this mode, the voltage-second balance on the magnetizing inductance is applied. The voltage across the magnetizing inductance is computed by using the following equation:(7)Vlm=Vpv×d1−d2+Vbat×d21−d1.The voltageVC1 across the capacitor C1 is computed by the following equation:(8)Vc1=Vpv−d2×Vpv+d2×Vbat1−d1.The voltageVC2 across the capacitor C2 is determined by the following equation:(9)Vc2=Vpv×1+nd1−d3n+2+Vch1−d1,where Vch=Vbatd2n+1+n1−d1.The output voltageV0 across the capacitor Cm is computed by using the following equation:(10)V0=Vpvnew×Vpvd1−d2+Vbat×d31−d1,where Vpvnew=2Vpv+n×Vbat+2n+2.


## 3.3. SIDO Mode

For the calculation of conversion ratio, we are applying voltage-second balance. In this mode, the only input is PV. To calculate the conversion ratio, voltage-second balance is applied on the magnetizing inductanceLm. The voltage across Lm is calculated by using the following equation:(11)Vlm=Vpv×d4−Vbatd4−d11−d2.The voltage across the capacitorsC1, C2, and Cm is calculated by using equations (12)–(14), respectively.(12)Vc1=Vpv−Vbatd4−d11−d4,(13)Vc2=n+2Vpv−Vbatd4−d11−d4.The output voltage over the capacitorCm is calculated by using the following equation:(14)V0=n3+d4Vpv−3n+2d4−d1Vbat1−d4.


## 3.4. Design Consideration

The design specifications of the proposed converter are given in Table1. The main components used in the converter design are coupled inductor, power MOSFETs, capacitors, and diodes. The appropriate selection of coupled inductor, capacitors, and power semiconductor devices is very crucial for the desired operation of the converter.Table 1
Parameters’ symbols and values/components used for prototype and simulation.
ParametersSymbolsValuesInput source-1Vpv48VBattery voltageVbat96VOutput voltageV0380VPrimary inductor (DCM)Lp5.01uHSecondary inductor (DCM)Ls20.043uHPrimary inductor (CCM)Lp25uHSecondary inductor (CCM)Ls100.043uHPeak primary inductor currentILp16ALoad currentILoad0.263AClamp capacitorC15uF, 250 VSeries capacitorC22uF, 250 VSeries capacitorC2uF, 250 VMain DC link capacitorCm300uFLoad resistorRload680ΩMOSFETsS1,S2, S3FQA34N20MOSFETsS4G32N500DiodeDcMBR20200CTDiodeDc2MUR840DiodeDb, DPVMBR4060PTSwitching frequencyfreq100kHzOutput powerP0100W


### 3.4.1. Coupled Inductor Design

The required parameters of the coupled inductor used in the converter topology are given in Table1. The equivalent inductance is Leq=Lp+Ls+2M, where M is the mutual inductance. The number of turns for the required inductance value of the Lp is calculated by using equation (15). The required peak inductor current is 6.165A, and the duty cycle d1=0.6. For 100W, the core ETD-39 and wire AWG-14 are selected. The peak ILpk primary inductor current is calculated using equation (16). The peak to peak primary inductor current is 2ILP . The peak current IDpk through diode D3 is calculated by using equation (17). The relationship between ILpk and Iout is expressed in equation (18). The required values of the coupled inductor are Lp=5uH and Ls=20uH for DCM operation. For the CCM operation, inductor values are Lp=25uH and Ls=100uH.(15)Bmax=Ueff⋅U0⋅N12⋅ImaxLe,where N67 material is used which has the following properties: Ueff=1590, Ae=97.1mm2, Le=78.8mm, and Bmax = maximum flux density.(16)ILpk=VpvLP×d1T,(17)IDpk=V0−Vpv×2+n−Vc2Leq×1−D1T,(18)ILpk=Iout×2+n+d11+n1−d1,(19)Iout=IDpk1−d12.The primary inductance value and its losses are calculated by using equations (20) and (21), respectively. The magnetizing inductance can be calculated by using equation (22).(20)Lp=Vpv2+n2×Iout×d11−d1T,(21)LPloss=RESR×n+11−d1×Iout2,(22)Lm=n×d1×Vpvfs×Δilp.The secondary inductor value is calculated by using the relationshipLs=n2⋅Lp, where n=N1/N2=L1/L2. Here, N1 is the number of turns on the primary side and N2 is the number of turns on the secondary side. The coupling coefficient between the primary and secondary inductors is calculated by using equation (23), where as the power loss in secondary inductor is calculated by equation (24).(23)k=MLp×Ls,(24)LSloss=RESR×n+11−d1×Iout2.The leakage inductance value on the primary side can be calculated by equation (25), where fr is the resonance frequency and the Couts1 is the output capacitance of the switch S1.(25)Llk=12⋅πfr2⋅Couts1.The finite element model of the coupled inductor is developed in Ansys Maxwell 3D by using PExprt tool. The coupled inductor’s Ansys analysis report for both the DCM and CCM operations is given in Tables2 and 3, respectively. In Table 2, the coupled inductor performance results are shown for the DCM mode. The results show the primary and secondary inductance (Lp and Ls) values of 5uH and 20uH, respectively, with turn ratio n=2. The current density is found to be 13.39A/mm2 for Lp and 3.58A/mm2 for Ls with the losses of 2.4W and 438.5mW for Lp and Ls, respectively. The value of Rdc is found to be 7.85Ω and 20.14Ω for Lp and Ls, respectively. The total losses for DCM mode are 4.455W, and window filling is 36.74% and 73.1% for Lp and Ls, respectively. Similarly, the coupled inductor performance results for CCM mode are shown in Table 3. The values of the current density, coupled inductor, losses in primary and secondary windings are shown. The DC resistance value of the used wire is Rdc = 3.353mΩ. Moreover, the losses in the core and winding are expressed as 971.142mW and 200.684mW, respectively. Furthermore, the window occupancy for both primary and secondary winding is obtained as 31.09% and 55.72%, respectively.Table 2
Ansys Maxwell analysis report: coupled inductor performance results (DCM).
Primary inductor (Lp)Secondary inductor (Ls)Current density13.39A/mm23.579A/mm2Inductance5.01uH20.043uHLosses2.405W438.504mWRdc7.857Ω20.144mΩLossesLosses (winding)3.360WLosses (core)95.104mWTotal losses4.455WWindow occupancyWindow filling (%)36.7473.10Table 3
Ansys Maxwell analysis report: coupled inductor performance results (CCM).
Primary inductor (Lp)Secondary inductor (Ls)Current density2.88A/mm21.22A/mm2Inductance25.00uH100.043uHLosses815.77mW119.917mWRdc3.353mΩ29.379mΩLossesLosses (winding)200.684mWLosses (core)971.142mWTotal losses1.172WWindow occupancyWindow filling (%)31.0955.72The finite element model (FEM) of coupled inductor for magnetic flux density is presented in Figure8(a), whereas the FEM for the magnetic flux lines is presented in Figure 8(b).Figure 8
FEM. (a) Magnetic flux density. (b) Magnetic flux lines.
(a)(b)


### 3.4.2. Capacitor Selection

Three capacitors used in this topology are the clamping capacitorC1, the switched capacitor C2, and DC link capacitor Cm. Equation (26) gives the relationship between the clamp capacitor C1 and the input voltage Vbat.(26)Vc1=Vbat1−d1.The blocking voltage over the switchS1 is expressed in the following equation:(27)VDS1=Vbat1−d1.The minimum value of the capacitorsC1 and C2 is calculated by using equations (28) and (29), where as the value of the output capacitor Cm is determined by equation (30). The voltage across the capacitor C2 is determined by equation (31).(28)C1min≥Vbat×d1⋅T2×Rdson1×ΔVc1,(29)C2min≥Vc1×d1⋅T2×Rdson1×ΔVc2,(30)Cm≥Vpv×d1×T2×Rload×ΔVcm,(31)Vc2=Vpv×−1+2⋅d1+2+n1+n1−d11−d1.


### 3.4.3. Selection of Switches and Diodes

The switchesS1, S2, and S4 have low voltage blocking capability while switch S3 has high voltage blocking capability. The maximum voltage stress across the main switch S1 and the diode Dc is calculated by the following equation:(32)Vds1=Vin1−d1,where Vin is the input voltage at PV or battery port. The switch S3 and the diode Dc2 bear maximum voltage stress, and it can be expressed as follows:(33)Vds3=Vin×2+n+d11+n1−d1.The voltage stress across the switchS2 and the diode Dpv is expressed as follows:(34)Vds2=Vbat−1+nVlp+Vc2+V0,whereas the voltage stress across the switch S4 and the diode D6 is given as follows:(35)Vds4=Vbat−Vd6+Vc1.The maximum current stress across the switches and diodes of the proposed converter occurs if only one source is serving the load. The current stress on the switchesS1 and S2 and the diodes Dpv and Dc is equal to ILpk as expressed in equation (18). The current stress on the switch S3 is equal to IDpk and is express in equation (20). The peak current through the diode Dc2 is Idp = IDpk/n, where IDpk is expressed in equation (17).A fast recovery diode is selected forDc, and an ultrafast recovery diode is chosen for Dc2, whereas the ordinary rectifier diodes with required current and voltage blocking capability are selected for Dpv and Db. The ratings of components used in simulation or prototype are given in Table 1.


## 3.4.1. Coupled Inductor Design

The required parameters of the coupled inductor used in the converter topology are given in Table1. The equivalent inductance is Leq=Lp+Ls+2M, where M is the mutual inductance. The number of turns for the required inductance value of the Lp is calculated by using equation (15). The required peak inductor current is 6.165A, and the duty cycle d1=0.6. For 100W, the core ETD-39 and wire AWG-14 are selected. The peak ILpk primary inductor current is calculated using equation (16). The peak to peak primary inductor current is 2ILP . The peak current IDpk through diode D3 is calculated by using equation (17). The relationship between ILpk and Iout is expressed in equation (18). The required values of the coupled inductor are Lp=5uH and Ls=20uH for DCM operation. For the CCM operation, inductor values are Lp=25uH and Ls=100uH.(15)Bmax=Ueff⋅U0⋅N12⋅ImaxLe,where N67 material is used which has the following properties: Ueff=1590, Ae=97.1mm2, Le=78.8mm, and Bmax = maximum flux density.(16)ILpk=VpvLP×d1T,(17)IDpk=V0−Vpv×2+n−Vc2Leq×1−D1T,(18)ILpk=Iout×2+n+d11+n1−d1,(19)Iout=IDpk1−d12.The primary inductance value and its losses are calculated by using equations (20) and (21), respectively. The magnetizing inductance can be calculated by using equation (22).(20)Lp=Vpv2+n2×Iout×d11−d1T,(21)LPloss=RESR×n+11−d1×Iout2,(22)Lm=n×d1×Vpvfs×Δilp.The secondary inductor value is calculated by using the relationshipLs=n2⋅Lp, where n=N1/N2=L1/L2. Here, N1 is the number of turns on the primary side and N2 is the number of turns on the secondary side. The coupling coefficient between the primary and secondary inductors is calculated by using equation (23), where as the power loss in secondary inductor is calculated by equation (24).(23)k=MLp×Ls,(24)LSloss=RESR×n+11−d1×Iout2.The leakage inductance value on the primary side can be calculated by equation (25), where fr is the resonance frequency and the Couts1 is the output capacitance of the switch S1.(25)Llk=12⋅πfr2⋅Couts1.The finite element model of the coupled inductor is developed in Ansys Maxwell 3D by using PExprt tool. The coupled inductor’s Ansys analysis report for both the DCM and CCM operations is given in Tables2 and 3, respectively. In Table 2, the coupled inductor performance results are shown for the DCM mode. The results show the primary and secondary inductance (Lp and Ls) values of 5uH and 20uH, respectively, with turn ratio n=2. The current density is found to be 13.39A/mm2 for Lp and 3.58A/mm2 for Ls with the losses of 2.4W and 438.5mW for Lp and Ls, respectively. The value of Rdc is found to be 7.85Ω and 20.14Ω for Lp and Ls, respectively. The total losses for DCM mode are 4.455W, and window filling is 36.74% and 73.1% for Lp and Ls, respectively. Similarly, the coupled inductor performance results for CCM mode are shown in Table 3. The values of the current density, coupled inductor, losses in primary and secondary windings are shown. The DC resistance value of the used wire is Rdc = 3.353mΩ. Moreover, the losses in the core and winding are expressed as 971.142mW and 200.684mW, respectively. Furthermore, the window occupancy for both primary and secondary winding is obtained as 31.09% and 55.72%, respectively.Table 2
Ansys Maxwell analysis report: coupled inductor performance results (DCM).
Primary inductor (Lp)Secondary inductor (Ls)Current density13.39A/mm23.579A/mm2Inductance5.01uH20.043uHLosses2.405W438.504mWRdc7.857Ω20.144mΩLossesLosses (winding)3.360WLosses (core)95.104mWTotal losses4.455WWindow occupancyWindow filling (%)36.7473.10Table 3
Ansys Maxwell analysis report: coupled inductor performance results (CCM).
Primary inductor (Lp)Secondary inductor (Ls)Current density2.88A/mm21.22A/mm2Inductance25.00uH100.043uHLosses815.77mW119.917mWRdc3.353mΩ29.379mΩLossesLosses (winding)200.684mWLosses (core)971.142mWTotal losses1.172WWindow occupancyWindow filling (%)31.0955.72The finite element model (FEM) of coupled inductor for magnetic flux density is presented in Figure8(a), whereas the FEM for the magnetic flux lines is presented in Figure 8(b).Figure 8
FEM. (a) Magnetic flux density. (b) Magnetic flux lines.
(a)(b)


## 3.4.2. Capacitor Selection

Three capacitors used in this topology are the clamping capacitorC1, the switched capacitor C2, and DC link capacitor Cm. Equation (26) gives the relationship between the clamp capacitor C1 and the input voltage Vbat.(26)Vc1=Vbat1−d1.The blocking voltage over the switchS1 is expressed in the following equation:(27)VDS1=Vbat1−d1.The minimum value of the capacitorsC1 and C2 is calculated by using equations (28) and (29), where as the value of the output capacitor Cm is determined by equation (30). The voltage across the capacitor C2 is determined by equation (31).(28)C1min≥Vbat×d1⋅T2×Rdson1×ΔVc1,(29)C2min≥Vc1×d1⋅T2×Rdson1×ΔVc2,(30)Cm≥Vpv×d1×T2×Rload×ΔVcm,(31)Vc2=Vpv×−1+2⋅d1+2+n1+n1−d11−d1.


## 3.4.3. Selection of Switches and Diodes

The switchesS1, S2, and S4 have low voltage blocking capability while switch S3 has high voltage blocking capability. The maximum voltage stress across the main switch S1 and the diode Dc is calculated by the following equation:(32)Vds1=Vin1−d1,where Vin is the input voltage at PV or battery port. The switch S3 and the diode Dc2 bear maximum voltage stress, and it can be expressed as follows:(33)Vds3=Vin×2+n+d11+n1−d1.The voltage stress across the switchS2 and the diode Dpv is expressed as follows:(34)Vds2=Vbat−1+nVlp+Vc2+V0,whereas the voltage stress across the switch S4 and the diode D6 is given as follows:(35)Vds4=Vbat−Vd6+Vc1.The maximum current stress across the switches and diodes of the proposed converter occurs if only one source is serving the load. The current stress on the switchesS1 and S2 and the diodes Dpv and Dc is equal to ILpk as expressed in equation (18). The current stress on the switch S3 is equal to IDpk and is express in equation (20). The peak current through the diode Dc2 is Idp = IDpk/n, where IDpk is expressed in equation (17).A fast recovery diode is selected forDc, and an ultrafast recovery diode is chosen for Dc2, whereas the ordinary rectifier diodes with required current and voltage blocking capability are selected for Dpv and Db. The ratings of components used in simulation or prototype are given in Table 1.


## 4. Control Scheme and Operational Mode Selection

Generally, output of the converter is regulated to satisfy the load requirement and also for the constant input to the inverter. The objective of the control scheme is to regulate the main DC link capacitorCm voltage V0 in SISO (boost operation) and DISO modes. In SIDO mode, the voltage V0 over the main DC link capacitor Cm is regulated at constant value. The charging and discharging battery is also regulated in this mode. In SISO (buck operation), the objective is to direct the battery voltage Vbat and control the charging current ib. The charging and discharging battery is also regulated in this mode. The mode selection and pulse width modulation (PWM) block is presented in Figure 9(a). The flow diagram explains the power flow and conditions for the transition in different modes. In this figure, VGS1, VGS2, VGS3, and VGS4 are the gate driving/control signals for switches S1, S2, S3, and S4, respectively. The control signal VGS1 is the main control signal applied to switch S1 in all modes. There are separate control loops for the input and output voltage ports. The comp-1 regulator keeps the PV system power at the maximum value while comp-2 regulates the output voltage at Vref. The activity mode is resolved by present working conditions, for example, load power, battery condition of charge, and accessible PV power. The control algorithm which determines the operational mode is presented in Figure 9(b). Initially, values of all terminal variables, i.e., Vpv, Vbat, V0, and R0, are acquired. If the battery is fully charged and PV power is not available, then the converter will operate in SISO (boost) mode. The converter operates in SISO (buck) mode when the PV power is not available and there is light load.Figure 9
(a) Control system block diagram. (b) Control flow diagram.
(a)(b)If both the PV power and load are available, the converter will operate in DISO Mode. As the converter is developed for the standalone PV system, the equationPpv+Pbat=Pload is always true, and hence the intermittence in PV power is always compensated by the battery system. Moreover, the converter is operated in SIDO mode; otherwise, the battery charge protection is active. The switch S4 is used to control the battery power. The transition between modes is very smooth. For example, in SIDO mode, if Ppv>P0 with constant load, VGS4 is used to control the battery power until Ppv=P0. The converter operates in SISO mode (buck) and battery is charged from the main DC link capacitor Cm, and the control signal is VGS3. This ensures smooth and soft transition between the ports.


## 5. Results and Discussion

In order to examine the exhibition of proposed topology and hypothetical investigation, a100W converter is tested in the laboratory. The proposed converter has high gain in SISO, DISO, and SIDO modes. The complete analytical and experimental results for SISO, DISO, and SIDO modes are presented. Main parts of the converter are common to all the ports. The parameters of different parts utilized in this model are given in Table 1. There are only minor changes in the values of parameters; however, shapes of the current and voltage waveforms remain the same. Design and selection of the components is performed by considering the possible maximum rating values. As the converter has only one coupled inductor, n can be expanded by keeping the duty cycle constant in order to increase the gain of the converter.


### 5.1. Experimental Results

A hardware prototype is developed and tested to prove the operational concepts of the proposed converter. The photographs of laboratory workstation and converter topology are presented in Figures10(a) and 10(b), respectively. A four-layer PCB is developed by using Altium Designer, with one power plan and one segmented ground plan. In the design of PCB, the number of controlled interfaces is reduced. This reduces the common mode voltage between the interface ports so that there is less coupling from the cables into or out of the system. In order to minimize the return current path impedance, the return current path is kept closer to the signal path. “Moats” in PCB ground plan are avoided. All power and ground rails are carefully checked to ensure they do not offer common impedance routes within or outside the unit. The parameters and particulars of different segments utilized in equipment model are expressed in Table 1. For the generation of control signals, TI Launchpad-F28379D is used. The instruments used for measurements are GDS-810C, a measuring module (USM-3IV), an oscilloscope, and a multimeter.Figure 10
(a) Workstation photograph. (b) Hardware prototype.
(a)(b)The measured waveforms of the converter for SISO boost operating modes are presented in Figure11. The magnetizing current ilm and gate driving signal (VGS1) are presented in Figure 11(a). The duty cycle d1 for the switch S1 is 0.6. The peak to peak voltage VGS1 is 12V. The gate driving signal (VGS1) vs coupled inductor leakage current ilk is presented in Figure 11(b), whereas the gate driving signal (VGS1) and coupled inductor secondary current iLS is presented in Figure 11(c).Figure 11
SISO (boost) mode results (scale: 5 V/DIV, 2 A/DIV, and 2.5 us/DIV). (a) Gate signalVGS1 and magnetizing current ilm waveforms. (b) Gate signal VGS1 and leakage current ilk waveforms. (c) Gate signal VGS1 and secondary current iLS waveforms. (d) Gate signal VGS1 and diode Dc current idc waveforms. (e) Gate signal VGS1 and diode Dc2 current idc2 waveforms. (f) Gate signal VGS1 and output voltage V0 waveforms.
(a)(b)(c)(d)(e)(f)Because of the leakage inductance of coupled inductor, the switchS1 is operated under ZCS. The leakage inductance is calculated according to equation (26). The measured series resonance inductance which is combination of leakage inductance and stray inductance is 0.98uH. The equivalent capacitance obtained from the output capacitance of primary and synchronous switches is 100pF. The switch S1 is also operated under almost ZVS condition without using the external inductors and capacitors. There are some ripples in the measurement of the current due to the low sensitivity of the measuring module. The measured gate signal of switch S1 and currents IDc are presented in Figure 11(d), whereas the VGS1 vs IDc2 curves are plotted in Figure 11(e) which are in close similarity with the theoretical results plotted in Figure 2(a).The gate signal of switchS1 and corresponding drain source voltage are plotted in Figure 12. It is obvious from the results that drain source voltage of S1 becomes zero before application of gate signal. In this case, almost ZVS is achieved by the series resonance tank Llk-Couts1 tank circuit. The tank circuit consists of the primary side leakage inductance of the coupled inductor and the output capacitance Couts1 of the switch S1. During the off time of the signal VGS1, the Llk-Couts1 circuit resonates. As the output capacitance of the switch S1 has been discharged by the series resonant circuit, this results in power savings and improvement in the energy efficiency of the converter.Figure 12
VDS1 and VGS1 during ZVS.The measured results for the SISO mode (buck operation) are presented in Figure13. The duty cycle d3 is equal to 0.3. The gate signal VGS3 and magnetizing current ilm are presented in Figure 13(a). There are some ripples in the current due to the measuring setup and coupled inductor leakage inductance. The gate signal VGS3 of switch S3 and corresponding drain source voltages VDS3 are presented in Figure 13(b). It is obvious from the figure that switch S3 is operated under almost ZVS. In Figure 13, switching gate signal VGS3 and inductor’s secondary current iLS are presented. During the turn on of the switch S3, both currents ilm and iLS are same.Figure 13
SISO mode results (buck operation) (scale: 5 V/DIV, 2 A/DIV, and 2.5 us/DIV). (a) Gate signalsVGS3 and magnetizing current ilm. (b) Gate signals VGS3 and blocking voltage VGS3 of switch S3. (c) Gate signals VGS3 and secondary current iLS.
(a)(b)(c)The measured results of converter in DISO mode are presented in Figure14. The duty cycle of switch S1 is 0.6, and the duty cycle of switch S2 is 0.5. The gate signals VGS1 and VGS2 and the current ib are presented in Figure 14(a). Battery supplies power to the load as long as the switch S2 is on. As the battery voltage drops below the threshold voltage, the switch S2 is turned off and power is supplied to the load by the source Vpv. Due to this, all of the results are same as those of the SISO (boost operation) mode. In Figure 14(b), the gate signals VGS1 and VGS2 and magnetizing current ilm are presented. The secondary current iLS and gate signals VGS1 and VGS1 are presented in Figure 14(c). It is observed that the only voltage rating and polarity of C1 and C2 affect the performance of the converter.Figure 14
DISO mode results (scale: 5 V/DIV, 2 A/DIV, and 2.5 us/DIV). (a) Gate signalsVGS1 and VGS2 and current ib of switch S2. (b) Gate signals VGS1 and VGS2 and magnetizing current ilm. (c) Gate signals VGS1 and VGS2 and secondary current iLS.
(a)(b)(c)The measured results of converter in SIDO mode are plotted in Figure15. The duty cycle of switch S1 is 0.6, and the duty cycle of the switch S4 is 0.68. The control signals VGS1 and VGS4 and the magnetizing current ilm are presented in Figure 15(a). The switch S4 is used to control the battery current ich. The excess energy generated by PV is used to charge the battery. The control signals VGS1 and VGS4 and drain source voltage VDS4 are presented in Figure 15(b). The gate signals VGS1 and VGS4 and secondary current iLS are expressed in Figure 15(c). The diode Dc is used to transfer the voltage stress of the switch S1. The gate signals VGS4 and VGS1 and the current idc are presented in Figure 15(d). The current ich control signals VGS1 and VGS4 are presented in Figure 15(e). The control signals VGS1 and VGS4 and current idc2 are presented in Figure. 15(f)Figure 15
SIDO mode results (scale: 5 V/DIV, 2 A/DIV, and 2.5 us/DIV). (a) Gate signalsVGS1 and VGS4 and magnetizing current ilm. (b) Gate signals VGS1 and VGS2 and blocking voltage VDS4 of switch S4ib. (c) Gate signals VGS1 and VGS4 and secondary current iLS. (d) Gate signals VGS1 and VGS4 and current idcof diode Dc. (e) Gate signals VGS1 and VGS4 and current ich of diode Dch. (f) Gate signals VGS1 and VGS4 and current idc2 of diode Dc2.
(a)(b)(c)(d)(e)(f)


### 5.2. Loss and Efficiency Analysis

The loss and efficiency of the proposed converter are analyzed in each operating mode. The SISO boost mode of operation is the main operating mode. For this mode, the efficiency of the converter as a function of output power is depicted in Figure16(a). The converter has maximum efficiency of 96% at the power of 240W with Vbat=96V in SISO mode. For input Vpv=48V, the converter has maximum efficiency of 95.5%. The converter efficiency is calculated by using equation (36). Table 4 shows the measured values of the input (rms) current, output current, resistive load, and efficiency values. The converter efficiency increases with the output power up to 240W. Beyond this point, the energy efficiency remains constant. Under these conditions, the losses in the converter are estimated and illustrated in the pie diagram in Figure 16(b). At the output power of 100W, the efficiency of the converter is 93% with input voltage Vpv and 94.5% with the input voltage Vbat. The maximum contribution in the loss is due to the main operating switch S1, i.e., FQA34N20 with RDSON=75mΩ . The switch loss can be calculated by using equation (37). The coupled inductor has the second highest losses with the exact value of 1.172W . The series capacitor contributes about 15% and input diode has the share of 10% in the total losses. Rest of the components have relatively low loss contribution.Figure 16
(a) Efficiency vs output power. (b) Measurement results: loss distribution on the main components of the converter at100W power. (c) SISO mode comparison of the proposed converter with other converters with n = 2. (d) Efficiency comparison of the converters.
(a)(b)(c)(d)Table 4
Power results in mode 1 withVpv=48V, V0=260V,andVbat=96V.
IinrmsAIoutARloadΩ%Peff11.21.31428893.269.991.230095.028.91.0634094.287.950.9540094.670.84445095.56.130.72950094.145.20.675091.344.980.58785093.3140.46995092.823.50.4100090.47(36)%Peff=1+n×Iout1−d1×Vpv×Iinrms×100,(37)Ploss−sw=Rdson×d1×1+n1−d1.For the DISO mode of operation, the main power loss is the same as that of the SISO mode, but there is additional power loss due to the diodeDpv and the switch S2. The losses due to diode Dpv and switch S2 are calculated by using equation (38) and equation (39), respectively.(38)Ploss−Dpv=Vf×If∗d1,(39)Ploss−S2=Rds2onf×Ib2,where Idb2 is the discharging current of the battery.The power loss in the SIDO mode is investigated by considering the loss of the diodesDpv and Db and the switch S4. The conduction losses for the diodes Dpv and Db are computed by using equation (38) and equation (40), respectively. The switch S4 conduction loss can be computed by using equation (41).(40)Ploss−S2=Vf×If,(41)Ploss−S2=Ich2×Rds4on.


### 5.3. Comparison Study

The proposed converter is compared with several similar converters suitable for standalone PV system in Table5. The comparison of proposed converter with [24, 30, 31] is performed. The proposed converter has higher switching frequency and uses less number of components to construct more useful features such as bidirectional power flow ports.Table 5
Comparative analysis of proposed converter with latest benchmarks converters.
[24][30][31]Proposed converterCoupled inductor2111MOSFETs5334Inductors2100Capacitors5332Diodes5662Soft switchingZVS turn onAlmost ZCS turn onAlmost ZCS turn onAlmost ZVS turn onVoltage stressVIN×n+1/1−d11−d1+d1×Vpv/1−d12n+1+nd/1−dVIN/1−d1Voltage gain (SISO)n×d+1/1−d2+n×d/1−d12n+1+n+×d/1−d12+n+d11+n/1−dThe proposed converter has only one conversion stage with common coupled inductor for both inputs. It has only one magnetic element, i.e., coupled inductor, four MOSFETs, two capacitors, and two diodes, whereas the converter in [24] has two coupled inductors, two inductors, and five switches. Similarly, the converter in [30] has one coupled inductor and one inductor along with three MOSFETs, six diodes, and three capacitors. The size of the converter is relatively small. The converter proposed in [31] has one coupled inductor, three MOSFETs and capacitors each, and six diodes. The converter has no extra inductor.The conversion gain in SISO mode is presented in Figure16(c). The gain of the proposed converter is almost equal to the converter explained in [31], but with minimum number of device count and size. In terms of device count, operational modes, and efficiency, the proposed converter outperforms its competitors. The operational comparison of the converters in terms of the efficiency in different operating modes is presented in Figure 16(d). In comparison with other counterparts by considering the input voltage 48V, the proposed converter has the maximum efficiency of 96% which is the same as that of [24, 31], but the proposed converter is operated at 100kHz while others are operated at 20kHz.A topological comparison of the proposed converter along with its other recent counterparts is presented in Table6. The advantages and disadvantages of the various recent structures are given. In [8], the converter provides good galvanic isolation, ZVS operation, and high conversion gain. The converter has large size, and this makes the converter costly with lower efficiency. The converter is good for the AC/DC integrated DC microgrid applications. In [10], the proposed converter has single conversion stage for each port which makes the control scheme simpler. It also has the ZVS and ZCS operation for all the switches. However, the large size and low efficiency limit the converter applications. In [12], the converter has the merits of high conversion gain and flexible operation between different modes. However, the converter has large size leading to the low efficiency. Merits and demerits of some other converters [13–15, 18] are summarized in Table 6.Table 6
Topological comparison of the proposed converter with other benchmarks: advantages, disadvantages, and applications.
ConvertersTopologyAdvantagesDisadvantages[8]Full bridge fully isolatedGalvanic isolationLarge sizeSimultaneous power managementCost inefficientZVS operation of the switchesLow efficiencyHigh gain[10]Interleaved-boost-full-bridgeUncoupled controlLarge sizeZVS and ZCS operationLess efficient[12]Flyback forward topologyHigh gainComplex controlGalvanic isolationLarge sizeMultiple operating modesLess efficient[13]Full bridge partly isolatedHigh gainLarge sizeSimple structure and controlLess efficientGalvanic isolationNot suitable for MPPT[14]Transformer with LCLHigh gainLess efficiencySimultaneous power flowComplex controlGood for MPPT[15]Fully isolated-interleaved boostHigh gainLarge sizeZVS and ZCSComplex controlReduced voltage stressSmooth transition[18]Partly isolated using boost-flyback forward converter and voltage doublerSimple structureLow gainZCSNot efficientLarge size[24]Nonisolated coupled inductorHigh gainLarge sizeSimple control strategyLess efficient[30]Coupled inductorHigh gainLarge sizeSimple structureComplex controlLow efficiency[31]Coupled inductorHigh gainComplex controlHigh efficiencyLimited power sharingLow voltage stressAlmost ZVS operationProposed converterCoupled inductorHigh gainShared controlReduced device countAlmost ZVS and ZCSIncreased efficiencyThe coupled inductor-based topologies are discussed in [24, 30, 31]. Brief overview of these topologies is given in Table 6, whereas detailed comparative analysis is given in Table 5. These topologies are preferred for the renewable energy integration with DC microgrid.The proposed converter has the merits of high gain, simple structure, low voltage stress on the main switches, and high efficiency. The only challenging part is the need of decoupling control as most of the components are common in the structure which can be overcome with suitable control scheme.


## 5.1. Experimental Results

A hardware prototype is developed and tested to prove the operational concepts of the proposed converter. The photographs of laboratory workstation and converter topology are presented in Figures10(a) and 10(b), respectively. A four-layer PCB is developed by using Altium Designer, with one power plan and one segmented ground plan. In the design of PCB, the number of controlled interfaces is reduced. This reduces the common mode voltage between the interface ports so that there is less coupling from the cables into or out of the system. In order to minimize the return current path impedance, the return current path is kept closer to the signal path. “Moats” in PCB ground plan are avoided. All power and ground rails are carefully checked to ensure they do not offer common impedance routes within or outside the unit. The parameters and particulars of different segments utilized in equipment model are expressed in Table 1. For the generation of control signals, TI Launchpad-F28379D is used. The instruments used for measurements are GDS-810C, a measuring module (USM-3IV), an oscilloscope, and a multimeter.Figure 10
(a) Workstation photograph. (b) Hardware prototype.
(a)(b)The measured waveforms of the converter for SISO boost operating modes are presented in Figure11. The magnetizing current ilm and gate driving signal (VGS1) are presented in Figure 11(a). The duty cycle d1 for the switch S1 is 0.6. The peak to peak voltage VGS1 is 12V. The gate driving signal (VGS1) vs coupled inductor leakage current ilk is presented in Figure 11(b), whereas the gate driving signal (VGS1) and coupled inductor secondary current iLS is presented in Figure 11(c).Figure 11
SISO (boost) mode results (scale: 5 V/DIV, 2 A/DIV, and 2.5 us/DIV). (a) Gate signalVGS1 and magnetizing current ilm waveforms. (b) Gate signal VGS1 and leakage current ilk waveforms. (c) Gate signal VGS1 and secondary current iLS waveforms. (d) Gate signal VGS1 and diode Dc current idc waveforms. (e) Gate signal VGS1 and diode Dc2 current idc2 waveforms. (f) Gate signal VGS1 and output voltage V0 waveforms.
(a)(b)(c)(d)(e)(f)Because of the leakage inductance of coupled inductor, the switchS1 is operated under ZCS. The leakage inductance is calculated according to equation (26). The measured series resonance inductance which is combination of leakage inductance and stray inductance is 0.98uH. The equivalent capacitance obtained from the output capacitance of primary and synchronous switches is 100pF. The switch S1 is also operated under almost ZVS condition without using the external inductors and capacitors. There are some ripples in the measurement of the current due to the low sensitivity of the measuring module. The measured gate signal of switch S1 and currents IDc are presented in Figure 11(d), whereas the VGS1 vs IDc2 curves are plotted in Figure 11(e) which are in close similarity with the theoretical results plotted in Figure 2(a).The gate signal of switchS1 and corresponding drain source voltage are plotted in Figure 12. It is obvious from the results that drain source voltage of S1 becomes zero before application of gate signal. In this case, almost ZVS is achieved by the series resonance tank Llk-Couts1 tank circuit. The tank circuit consists of the primary side leakage inductance of the coupled inductor and the output capacitance Couts1 of the switch S1. During the off time of the signal VGS1, the Llk-Couts1 circuit resonates. As the output capacitance of the switch S1 has been discharged by the series resonant circuit, this results in power savings and improvement in the energy efficiency of the converter.Figure 12
VDS1 and VGS1 during ZVS.The measured results for the SISO mode (buck operation) are presented in Figure13. The duty cycle d3 is equal to 0.3. The gate signal VGS3 and magnetizing current ilm are presented in Figure 13(a). There are some ripples in the current due to the measuring setup and coupled inductor leakage inductance. The gate signal VGS3 of switch S3 and corresponding drain source voltages VDS3 are presented in Figure 13(b). It is obvious from the figure that switch S3 is operated under almost ZVS. In Figure 13, switching gate signal VGS3 and inductor’s secondary current iLS are presented. During the turn on of the switch S3, both currents ilm and iLS are same.Figure 13
SISO mode results (buck operation) (scale: 5 V/DIV, 2 A/DIV, and 2.5 us/DIV). (a) Gate signalsVGS3 and magnetizing current ilm. (b) Gate signals VGS3 and blocking voltage VGS3 of switch S3. (c) Gate signals VGS3 and secondary current iLS.
(a)(b)(c)The measured results of converter in DISO mode are presented in Figure14. The duty cycle of switch S1 is 0.6, and the duty cycle of switch S2 is 0.5. The gate signals VGS1 and VGS2 and the current ib are presented in Figure 14(a). Battery supplies power to the load as long as the switch S2 is on. As the battery voltage drops below the threshold voltage, the switch S2 is turned off and power is supplied to the load by the source Vpv. Due to this, all of the results are same as those of the SISO (boost operation) mode. In Figure 14(b), the gate signals VGS1 and VGS2 and magnetizing current ilm are presented. The secondary current iLS and gate signals VGS1 and VGS1 are presented in Figure 14(c). It is observed that the only voltage rating and polarity of C1 and C2 affect the performance of the converter.Figure 14
DISO mode results (scale: 5 V/DIV, 2 A/DIV, and 2.5 us/DIV). (a) Gate signalsVGS1 and VGS2 and current ib of switch S2. (b) Gate signals VGS1 and VGS2 and magnetizing current ilm. (c) Gate signals VGS1 and VGS2 and secondary current iLS.
(a)(b)(c)The measured results of converter in SIDO mode are plotted in Figure15. The duty cycle of switch S1 is 0.6, and the duty cycle of the switch S4 is 0.68. The control signals VGS1 and VGS4 and the magnetizing current ilm are presented in Figure 15(a). The switch S4 is used to control the battery current ich. The excess energy generated by PV is used to charge the battery. The control signals VGS1 and VGS4 and drain source voltage VDS4 are presented in Figure 15(b). The gate signals VGS1 and VGS4 and secondary current iLS are expressed in Figure 15(c). The diode Dc is used to transfer the voltage stress of the switch S1. The gate signals VGS4 and VGS1 and the current idc are presented in Figure 15(d). The current ich control signals VGS1 and VGS4 are presented in Figure 15(e). The control signals VGS1 and VGS4 and current idc2 are presented in Figure. 15(f)Figure 15
SIDO mode results (scale: 5 V/DIV, 2 A/DIV, and 2.5 us/DIV). (a) Gate signalsVGS1 and VGS4 and magnetizing current ilm. (b) Gate signals VGS1 and VGS2 and blocking voltage VDS4 of switch S4ib. (c) Gate signals VGS1 and VGS4 and secondary current iLS. (d) Gate signals VGS1 and VGS4 and current idcof diode Dc. (e) Gate signals VGS1 and VGS4 and current ich of diode Dch. (f) Gate signals VGS1 and VGS4 and current idc2 of diode Dc2.
(a)(b)(c)(d)(e)(f)


## 5.2. Loss and Efficiency Analysis

The loss and efficiency of the proposed converter are analyzed in each operating mode. The SISO boost mode of operation is the main operating mode. For this mode, the efficiency of the converter as a function of output power is depicted in Figure16(a). The converter has maximum efficiency of 96% at the power of 240W with Vbat=96V in SISO mode. For input Vpv=48V, the converter has maximum efficiency of 95.5%. The converter efficiency is calculated by using equation (36). Table 4 shows the measured values of the input (rms) current, output current, resistive load, and efficiency values. The converter efficiency increases with the output power up to 240W. Beyond this point, the energy efficiency remains constant. Under these conditions, the losses in the converter are estimated and illustrated in the pie diagram in Figure 16(b). At the output power of 100W, the efficiency of the converter is 93% with input voltage Vpv and 94.5% with the input voltage Vbat. The maximum contribution in the loss is due to the main operating switch S1, i.e., FQA34N20 with RDSON=75mΩ . The switch loss can be calculated by using equation (37). The coupled inductor has the second highest losses with the exact value of 1.172W . The series capacitor contributes about 15% and input diode has the share of 10% in the total losses. Rest of the components have relatively low loss contribution.Figure 16
(a) Efficiency vs output power. (b) Measurement results: loss distribution on the main components of the converter at100W power. (c) SISO mode comparison of the proposed converter with other converters with n = 2. (d) Efficiency comparison of the converters.
(a)(b)(c)(d)Table 4
Power results in mode 1 withVpv=48V, V0=260V,andVbat=96V.
IinrmsAIoutARloadΩ%Peff11.21.31428893.269.991.230095.028.91.0634094.287.950.9540094.670.84445095.56.130.72950094.145.20.675091.344.980.58785093.3140.46995092.823.50.4100090.47(36)%Peff=1+n×Iout1−d1×Vpv×Iinrms×100,(37)Ploss−sw=Rdson×d1×1+n1−d1.For the DISO mode of operation, the main power loss is the same as that of the SISO mode, but there is additional power loss due to the diodeDpv and the switch S2. The losses due to diode Dpv and switch S2 are calculated by using equation (38) and equation (39), respectively.(38)Ploss−Dpv=Vf×If∗d1,(39)Ploss−S2=Rds2onf×Ib2,where Idb2 is the discharging current of the battery.The power loss in the SIDO mode is investigated by considering the loss of the diodesDpv and Db and the switch S4. The conduction losses for the diodes Dpv and Db are computed by using equation (38) and equation (40), respectively. The switch S4 conduction loss can be computed by using equation (41).(40)Ploss−S2=Vf×If,(41)Ploss−S2=Ich2×Rds4on.


## 5.3. Comparison Study

The proposed converter is compared with several similar converters suitable for standalone PV system in Table5. The comparison of proposed converter with [24, 30, 31] is performed. The proposed converter has higher switching frequency and uses less number of components to construct more useful features such as bidirectional power flow ports.Table 5
Comparative analysis of proposed converter with latest benchmarks converters.
[24][30][31]Proposed converterCoupled inductor2111MOSFETs5334Inductors2100Capacitors5332Diodes5662Soft switchingZVS turn onAlmost ZCS turn onAlmost ZCS turn onAlmost ZVS turn onVoltage stressVIN×n+1/1−d11−d1+d1×Vpv/1−d12n+1+nd/1−dVIN/1−d1Voltage gain (SISO)n×d+1/1−d2+n×d/1−d12n+1+n+×d/1−d12+n+d11+n/1−dThe proposed converter has only one conversion stage with common coupled inductor for both inputs. It has only one magnetic element, i.e., coupled inductor, four MOSFETs, two capacitors, and two diodes, whereas the converter in [24] has two coupled inductors, two inductors, and five switches. Similarly, the converter in [30] has one coupled inductor and one inductor along with three MOSFETs, six diodes, and three capacitors. The size of the converter is relatively small. The converter proposed in [31] has one coupled inductor, three MOSFETs and capacitors each, and six diodes. The converter has no extra inductor.The conversion gain in SISO mode is presented in Figure16(c). The gain of the proposed converter is almost equal to the converter explained in [31], but with minimum number of device count and size. In terms of device count, operational modes, and efficiency, the proposed converter outperforms its competitors. The operational comparison of the converters in terms of the efficiency in different operating modes is presented in Figure 16(d). In comparison with other counterparts by considering the input voltage 48V, the proposed converter has the maximum efficiency of 96% which is the same as that of [24, 31], but the proposed converter is operated at 100kHz while others are operated at 20kHz.A topological comparison of the proposed converter along with its other recent counterparts is presented in Table6. The advantages and disadvantages of the various recent structures are given. In [8], the converter provides good galvanic isolation, ZVS operation, and high conversion gain. The converter has large size, and this makes the converter costly with lower efficiency. The converter is good for the AC/DC integrated DC microgrid applications. In [10], the proposed converter has single conversion stage for each port which makes the control scheme simpler. It also has the ZVS and ZCS operation for all the switches. However, the large size and low efficiency limit the converter applications. In [12], the converter has the merits of high conversion gain and flexible operation between different modes. However, the converter has large size leading to the low efficiency. Merits and demerits of some other converters [13–15, 18] are summarized in Table 6.Table 6
Topological comparison of the proposed converter with other benchmarks: advantages, disadvantages, and applications.
ConvertersTopologyAdvantagesDisadvantages[8]Full bridge fully isolatedGalvanic isolationLarge sizeSimultaneous power managementCost inefficientZVS operation of the switchesLow efficiencyHigh gain[10]Interleaved-boost-full-bridgeUncoupled controlLarge sizeZVS and ZCS operationLess efficient[12]Flyback forward topologyHigh gainComplex controlGalvanic isolationLarge sizeMultiple operating modesLess efficient[13]Full bridge partly isolatedHigh gainLarge sizeSimple structure and controlLess efficientGalvanic isolationNot suitable for MPPT[14]Transformer with LCLHigh gainLess efficiencySimultaneous power flowComplex controlGood for MPPT[15]Fully isolated-interleaved boostHigh gainLarge sizeZVS and ZCSComplex controlReduced voltage stressSmooth transition[18]Partly isolated using boost-flyback forward converter and voltage doublerSimple structureLow gainZCSNot efficientLarge size[24]Nonisolated coupled inductorHigh gainLarge sizeSimple control strategyLess efficient[30]Coupled inductorHigh gainLarge sizeSimple structureComplex controlLow efficiency[31]Coupled inductorHigh gainComplex controlHigh efficiencyLimited power sharingLow voltage stressAlmost ZVS operationProposed converterCoupled inductorHigh gainShared controlReduced device countAlmost ZVS and ZCSIncreased efficiencyThe coupled inductor-based topologies are discussed in [24, 30, 31]. Brief overview of these topologies is given in Table 6, whereas detailed comparative analysis is given in Table 5. These topologies are preferred for the renewable energy integration with DC microgrid.The proposed converter has the merits of high gain, simple structure, low voltage stress on the main switches, and high efficiency. The only challenging part is the need of decoupling control as most of the components are common in the structure which can be overcome with suitable control scheme.


## 6. Conclusions

A three-port bidirectional power converter using a coupled inductor and a switched capacitor is proposed. Size of the converter is reduced by increasing the switching frequency. Higher voltage gain is achieved by using active clamp and switch capacitor technique. Operation of the converter is illustrated in three distinct modes, i.e., SISO, DISO, and SIDO. The converter has high gain in all operational modes. The use of the clamp circuit results in the reduction of voltage stress on the switches. All the main operating switches are operated under ZVS and ZCS. The converter efficiency is calculated and loss analysis is performed using analytic, simulated, and experimental models. The proposed converter has96% efficiency in SISO mode. A prototype of a 100 W converter is developed by using 48V and 96V inputs and 380V output voltage. The measured results of the converter are in close comparison with simulation results.



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*Source: 5892190-2020-10-24.xml*