# An Inductorless Cascaded Phase-Locked Loop with Pulse Injection Locking Technique in 90nm CMOS

Authors: Sang-yeop Lee; Hiroyuki Ito; Shuhei Amakawa; Noboru Ishihara; Kazuya Masu
Journal: International Journal of Microwave Science and Technology
 (2013)

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## Abstract

An inductorless phase-locked loop with subharmonic pulse injection locking was realized (PLL
area: 0.11 mm2) by adopting 90 nm Si CMOS technology. The proposed circuit is configured with two cascaded PLLs; one of them is a reference PLL that generates reference signals to the other one from low-frequency external reference signals. The other is a main PLL that generates high-frequency output signals. A high-frequency half-integral subharmonic locking technique was used to decrease the phase noise characteristics. For a 50 MHz input reference signal, without injection locking, the 1 MHz offset phase noise was −88 dBc/Hz at a PLL output frequency of 7.2 GHz (= 144 × 50 MHz); with injection locking, the noise was −101 dBc/Hz (spur level: −31 dBc; power consumption from a 1.0 V power supply: 25 mW).


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## Body

## 1. Introduction

Conventional multistandard wireless mobile terminals contain multiple RFICs. To reduce production costs, one-chip wideband RF LSI systems are desired. A great effort is being made to develop wideband and/or multiband RF solutions using highly scaled advanced CMOS processes. The use of such processes is beneficial toA/D and D/A converters and digital baseband circuits. However, it is very difficult to reduce the scale of RF/analog circuit blocks, especially power amplifiers and oscillator circuits, including voltage-controlled oscillators (VCOs) and phase-locked loops (PLLs), because of the presence of inductors that do not scale with advancements in technology.In designing VCOs which generate signals in RF systems, ring-type VCOs (ring VCOs) are more attractive than LC-resonant-type VCOs (LC VCOs) in terms of their small area and wide frequency tuning range since they do not use large passive devices. However, they have poor phase noise with relatively high power consumption. Nevertheless, low-phase-noise ring VCO is still a possibility if some noise-suppression mechanism is applied. One of available options would be injection locking.In the early days, Adler [1] and many other authors studied the behavior of VCOs with injection locking. Also, there are numerous papers published in reference to VCOs with injection locking in order to achieve phase locking and high performances. Moreover, recently, PLLs with an injection-locked frequency divider and frequency multiplier, and a clock and data recovery circuit (CDR) were presented.This paper describes a study on a ring-VCO-based PLL with pulse injection locking as a potential solution to realize a scalable inductorless PLL, which can generate wideband frequency signal with low supply voltage. Usually, the frequency range utilized consumer RF applications, such as wireless LAN a/b/g/n, Bluetooth, and digital TV (DTV), is very wide and spreading from 400 MHz to 6 GHz. Table1 shows target performance of the proposed PLL. Generally, in RF systems using high transmitting power, a frequency synthesizer should generate higher-frequency signals up to 12 GHz to avoid injection pulling from a power amplifier. Then, some methods, such as using frequency dividers and mixers, are applied to widen frequency range [2, 3].Table 1
Target performance.
VCO
Ring
Frequency range
6–12 GHz
Phase noise at 1 MHz offset
−100 dBc/Hz
CMOS process
90 nm
Supply voltage
1.0 VIn addition, the proposed PLL is augmented with high-frequency half-integral subharmonic locking in order to improve its phase-noise performance. In Section2, brief features of the proposed PLL are explained. In Section 2.1, high-frequency half-integral subharmonic locking is shown as a method of reducing phase noise. Also, the proposed cascaded PLL (CPLL) that can achieve injection locking at high frequencies from low-frequency reference is presented. Detailed circuit designs, such as a VCO and a charge pump which are able to realize wide-band operation, and the measurement results obtained from an implementation in 90 nm CMOS process are presented in Sections 3 and 4, respectively. Finally, we conclude this work in Section 5.


## 2. Injection Locking in Frequency Synthesizers

Figure1 shows an injection-locked PLL (ILPLL). The PLL is based on a ring VCO that is able to generate high-frequency outputs across wide frequency range, as well as I/Q outputs. The PLL also consists of a phase frequency detector (PFD), a charge pump (CP), a loop filter (LF), a variable delay unit (ΔT), and a pulser.Figure 1
Injection-locked PLL with pulse injection.PLLs that use ring type VCOs are required to have a wide loop bandwidth of the phase-locked loop for lowering their poor phase noise characteristics. However, there is a trade-off between the loop bandwidth and the stability of PLLs. In general, the loop bandwidth (ω-3dB) must be narrower than ωref/20~ωref/10, where ωref is the reference-signal frequency [4]. Consequently, there is a limitation on lowering the phase noise in ring-VCO-based charge-pump PLLs (CP PLLs). Figure 2 shows phase noise characteristics of the PLL. In this case, the charge-pump noise of the PLL is assumed to be small enough and can be neglected. In Figure 2, phase noise is suppressed up to the loop bandwidth (ω-3dB) by the noise filtering of the loop. On the other hand, pulse injection locking is effective to reduce phase noise of ring VCOs since ring VCOs have a wider lock range with injection locking than that of LC VCOs because of their low quality factors. In designing subharmonically injection-locked oscillators (ILOs), N times frequency-multiplied signals as to the reference frequency can be achieved. The lock range is decided by the power of Nth superharmonics of the reference signal as follows [1, 5]:(1)ωL=ωout2Q·PinjNP0,
where Q represents the open-loop quality factor of an oscillator (calculated by using the open-loop transfer function of the oscillator [6]), ωout is the output frequency of the oscillator under injection locked condition, PinjN is the Nth harmonic power of the reference signal, and P0 is the free-running output power of the oscillator. PinjN is approximately given by
(2)PinjN∝{A·Dsin(πD·N)πD·N}2,
where A is the pulse amplitude, D is the duty cycle of pulses (D=ΔT/T, ΔT: pulse width, T: period of pulses). From (1) and (2), the lock range ωL can be rewritten as follows:
(3)ωL∝ωinj2Q·|sin(πD·N)|P0,
where ωinj (=ω0/N) is the injection-signal frequency [7].Figure 2
Phase-noise reduction with a charge-pump PLL and injection locking.The overall ILO output phase noise is obtained by adding the noise contributions in an ILO. Assuming thatSILO(ω), SREF(ω), and SVCO(ω) are phase noise power functions of an injection-locked VCO, a reference signal, and a free-running VCO, respectively, the phase noise of an ILO, SILO(ω), simply can be expressed as
(4)SILO(ω)=SREF,M(ω)·|HLPF(jω)|2+SVCO(ω)·|HHPF(jω)|2=M2·SREF(ω)·11+(ω/ωL)2+SVCO(ω)·(ω/ωL)21+(ω/ωL)2,
where SREF,M is the normalized phase noise power function with respect to the output frequency of fout, and M means the ratio between the output frequency (fout) and the input frequency (finj). HLPF(jω) and HHPF(jω) are low-pass and high-pass transfer functions, respectively [8]. Supposed that HHPF(jω) and HLPF(jω) have the first-order transfer functions and they have the same cutoff frequency of ωL, the simple equation of (4) would be achieved [5, 9, 10].In the proposed PLL, there are two kinds of phase locking mechanism: one is a phase-locked loop, and the other is pulse injection locking. In general, either of them is enough for phase locking. However, those two mechanisms are combined to get a wide frequency range operation with a low-phase-noise performance. The phase-locked loop, which uses a charge pump for controlling the oscillation frequency, is implemented to ensure correct frequency locking over the entire VCO tuning range. The final phase locking is done by injection locking to reference signal [11–13].


### 2.1. High-Frequency Half-Integral Subharmonic Locking Topology for Noise Reduction

A paper on half-integral subharmonic injection locking based on the use of a ring VCO has been presented [8]. A differential VCO can be easily designed to lock to half-integral subharmonics by giving its necessary symmetry properties. Suppose that a VCO consists of differential circuits and has a certain symmetry. As a method to achieve injection locking, a direct injection technique is applied, which uses nMOS switches that short the differential outputs for phase corrections. Figure 3 shows differential waveforms (Vd1, Vd2) of the VCO in the case of both integral (f0=finj) and half-integral subharmonic locking (f0=1.5finj). The two output nodes are shorted when the injection signal (Vinj1, Vinj2) is input into the nMOS switches. Phase corrections may occur at the time and the jitter is reduced. Generally, there are two points of time during the period of the output signal when two output nodes can be shorted because of topological symmetry as shown in Figure 3. Consequently, the differential VCO is capable of both integral and also half-integral subharmonic locking.Voltage and current waveforms at differential output nodes of a VCO; (a) integral subharmonic locking (f0=finj), (b) half-integral subharmonic locking (f0=1.5finj).
(a)
(b)One advantage of using half-integral subharmonic locking is to be able to use high-frequency reference signal and can make the locking range of injection locking,ωL wide as shown in (1). Figure 2 and Equation (4) also show that the phase noise of the reference signal mainly affects the output phase noise at low offset frequencies and that the phase noise of the PLL becomes dominant as the offset frequency approaches the edge of the locking range [11]. Therefore, it will improve phase noise characteristics to the edge of the locking range to use high-frequency reference signals.


### 2.2.   High-Frequency Signal Generation with Cascaded ILOs

As shown in (3), the lock range is proportional to the input frequency of ωinj. However, narrower pulses are required to achieve smaller D with increasing the multiplication ratio (N). Unfortunately, it is difficult to achieve sufficiently narrow pulses even with the use of nm-scale CMOS processes since the reference inputs also have certain jitter and parasitic components of the pulser limit the pulse width. In other words, there is limitation to generate high-frequency (over 5 GHz) injection-locked signals with low-frequency reference such as XTALs.One solution is to employ cascaded oscillators [11], which make each multiplication ratio (N) smaller by using two multiplication processes. Figure 4 shows the concept of the cascaded ILOs. Firstly, the input signal, which has sufficiently high-power superharmonics, is injected into VCO1. Then, M1 multiplied frequency signal (fout1=M1·finj) of the reference frequency can be achieved by tuning the VCO1 oscillation frequency properly. In this case, the output phase noise of VCO1 with injection locking can be expressed as follows:
(5)SILO1(ω)=M12·SREF(ω)·11+(ω/ωL1)2+SVCO1(ω)·(ω/ωL1)21+(ω/ωL1)2,
where ωL1 is the lock range that is proportional to the input frequency (finj) and can be calculated from (3).Figure 4
Concept of the cascaded ILOs.The output signal of VCO1 is injected into VCO2 and locked to the output of VCO2 with the same process occurred in VCO1. Also, the output phase noise of VCO2 with injection locking can be expressed as follows:(6)SILO2(ω)=M22·SILO1(ω)·11+(ω/ωL2)2+SVCO2(ω)·(ω/ωL2)21+(ω/ωL2)2(7)≈M22·11+(ω/ωL2)2·SILO1(ω),
where M2 is the ratio between the output frequency of VCO2 (fout2) and input frequency (fout1) and ωL2 is the lock range of VCO2. When the offset frequency of ω is sufficiently lower than ωL2 (i.e.,  ω≪ωL2), (7) is held. In other words, sufficiently wide lock range makes it possible to neglect the secondary VCO phase noise up to the lock range in cascaded ILOs.


## 2.1. High-Frequency Half-Integral Subharmonic Locking Topology for Noise Reduction

A paper on half-integral subharmonic injection locking based on the use of a ring VCO has been presented [8]. A differential VCO can be easily designed to lock to half-integral subharmonics by giving its necessary symmetry properties. Suppose that a VCO consists of differential circuits and has a certain symmetry. As a method to achieve injection locking, a direct injection technique is applied, which uses nMOS switches that short the differential outputs for phase corrections. Figure 3 shows differential waveforms (Vd1, Vd2) of the VCO in the case of both integral (f0=finj) and half-integral subharmonic locking (f0=1.5finj). The two output nodes are shorted when the injection signal (Vinj1, Vinj2) is input into the nMOS switches. Phase corrections may occur at the time and the jitter is reduced. Generally, there are two points of time during the period of the output signal when two output nodes can be shorted because of topological symmetry as shown in Figure 3. Consequently, the differential VCO is capable of both integral and also half-integral subharmonic locking.Voltage and current waveforms at differential output nodes of a VCO; (a) integral subharmonic locking (f0=finj), (b) half-integral subharmonic locking (f0=1.5finj).
(a)
(b)One advantage of using half-integral subharmonic locking is to be able to use high-frequency reference signal and can make the locking range of injection locking,ωL wide as shown in (1). Figure 2 and Equation (4) also show that the phase noise of the reference signal mainly affects the output phase noise at low offset frequencies and that the phase noise of the PLL becomes dominant as the offset frequency approaches the edge of the locking range [11]. Therefore, it will improve phase noise characteristics to the edge of the locking range to use high-frequency reference signals.


## 2.2.   High-Frequency Signal Generation with Cascaded ILOs

As shown in (3), the lock range is proportional to the input frequency of ωinj. However, narrower pulses are required to achieve smaller D with increasing the multiplication ratio (N). Unfortunately, it is difficult to achieve sufficiently narrow pulses even with the use of nm-scale CMOS processes since the reference inputs also have certain jitter and parasitic components of the pulser limit the pulse width. In other words, there is limitation to generate high-frequency (over 5 GHz) injection-locked signals with low-frequency reference such as XTALs.One solution is to employ cascaded oscillators [11], which make each multiplication ratio (N) smaller by using two multiplication processes. Figure 4 shows the concept of the cascaded ILOs. Firstly, the input signal, which has sufficiently high-power superharmonics, is injected into VCO1. Then, M1 multiplied frequency signal (fout1=M1·finj) of the reference frequency can be achieved by tuning the VCO1 oscillation frequency properly. In this case, the output phase noise of VCO1 with injection locking can be expressed as follows:
(5)SILO1(ω)=M12·SREF(ω)·11+(ω/ωL1)2+SVCO1(ω)·(ω/ωL1)21+(ω/ωL1)2,
where ωL1 is the lock range that is proportional to the input frequency (finj) and can be calculated from (3).Figure 4
Concept of the cascaded ILOs.The output signal of VCO1 is injected into VCO2 and locked to the output of VCO2 with the same process occurred in VCO1. Also, the output phase noise of VCO2 with injection locking can be expressed as follows:(6)SILO2(ω)=M22·SILO1(ω)·11+(ω/ωL2)2+SVCO2(ω)·(ω/ωL2)21+(ω/ωL2)2(7)≈M22·11+(ω/ωL2)2·SILO1(ω),
where M2 is the ratio between the output frequency of VCO2 (fout2) and input frequency (fout1) and ωL2 is the lock range of VCO2. When the offset frequency of ω is sufficiently lower than ωL2 (i.e.,  ω≪ωL2), (7) is held. In other words, sufficiently wide lock range makes it possible to neglect the secondary VCO phase noise up to the lock range in cascaded ILOs.


## 3. Proposed Injection-Locked PLL Topology

Figure5 shows the configuration of the proposed PLL that enables the use of half-integral subharmonic locking, which was proposed in our previous work [13]. The proposed PLL consists of two injection-locked PLLs. A reference PLL, namely, RPLL generates reference signals to a main PLL, namely, MPLL from low-frequency external reference signals. In this topology, when we choose divider ratios (Table 2), respectively as, N2=36, N3=1, and N4=8, the ratio between the reference signal to MPLL and the output frequency of MPLL may be 4.5 and high-frequency half-integral subharmonic locking can be applied. Variable time delay cells ΔTs are implemented to control the time when injection signals are input because phase corrections can occur easily when differential output nodes are shorted in the direct injection locking scheme (Figure 3).Table 2
Dividers ratio in Figure5.
N
1
N
2
N
3
N
4
32
24, 36
1, 8
4, 8Figure 5
Proposed cascaded injection-locked PLL (CPLL) with pulse injection.


### 3.1. Main PLL

Figure6(a) shows the topology of the proposed delay cell that composes a ring VCO [13]. The delay cell contains an inverter latch as a negative conductance circuit that generates delay by positive feedback in order to satisfy the oscillation condition [14]. To tune the VCO output frequency widely, variable pMOS resistive loads are used. However, in the commonly used delay cells with pMOS resistive loads, the range of control voltage is limited from 0 V to the pMOS threshold voltage. In the proposed delay cell, a pMOS transistor is added into which the subcontrol voltage (Vbn) is input in order to make the range of sensitive voltages identical to the rail-to-rail voltage range (0 V to VDD). For this purpose, the bias level shifted by about VDD/2, Vbn, is input to the added pMOS transistor. As a result, the total equivalent resistance of the two pMOS transistors in parallel changes almost linearly versus the main control voltage, Vb. Consequently, the VCO output frequency can be tuned linearly across the wide tuning range [12, 13]. An nMOS switches are connected at the nodes between the differential nodes to achieve injection locking [15].(a) Proposed differential delay cell, (b) two-stage differential VCO of MPLL with a bias-level-shift circuit.
(a)
(b)The proposed ring VCO is shown in Figure6(b). It is based on a two-stage pseudo differential ring oscillator. Pulses which are generated by the on-chip pulser are injected into the left delay cell in the form of rail-to-rail pulses for injection locking. To maintain topological symmetry, an nMOS switch biased to 0 V is also applied in the right-side delay cell. We achieved the VCO tuning range of 6.02 GHz to 11.1 GHz across the rail-to-rail control voltage from the postlayout simulation of the VCO core with output buffers (90 nm CMOS process, VDD=1.0V).A tristate phase/frequency detector (PFD) is implemented, which consists of two D-flip flops, delay-path inverters, and an AND logic. The PFD detects phase and frequency difference between the reference signal and the divided VCO output and generates output pulses ofVUP and VDN which are input into the charge pump to reduce the difference.Figure7 shows an implemented current mirror circuit to generate stable constant current from the charge pump. Usually, stacked current mirrors design can obtain better DC headroom and linearity with longer channel lengths as shown in the left side of Figure 7. In this case, DC headroom of the output voltage (Vout) is expressed as 2(Δov+Vthn), where Δov is the overdrive voltage of MOS transistors (M3, M4), and Vthn is an nMOS threshold voltage. In the case of Sooch cascode current mirror as shown in the right side of Figure 7, the MOS transistor, M5, is forced to operate in the triode region. The DC headroom can be reduced as 2Δov since MOS transistors operate in the saturation region except for M5 [16]. Consequently, low voltage operation can be achieved.Figure 7
Sooch cascode current mirror circuit.Proposed current switching charge pump (CP) that employs Sooch cascode current mirror is shown in Figure8. Dummy switches are also implemented to maintain the balance between PFD outputs. Two external current sources ranged from  10 μA to 150 μA are used.Figure 8
Proposed charge-pump (CP) circuit and loop filter (LF).Figure9 shows postlayout simulation results of the proposed charge pump, when ICP=20 μA (90 nm CMOS process, 1.0 V supply). It shows that the charge pump can generate quite constant output current across the wide range of the output voltage (Vb). When VUP=1 V and  VDN=0 V, the result shows current mismatch between the up and down output currents as a function of the output voltage (Vb). The percentage mismatch error for 0.48 V≤Vb≤0.81V is less than 2% and increases to less than 5% for 0.21 V≤Vb≤0.85V.Figure 9
Charge-pump output current versus the control voltage (Vb), when ICP=20 μA.A second-order lag-lead filter that consists of a register and two capacitors is implemented as a loop filter (LF) of the loop to suppress the charge-pump ripple. (R=16 kΩ, C1=41 pF, C2=12 pF). In this case, on-chip MIM capacitors were used.The frequency divider consists of differential pseudo-nMOS latches to minimize chip area and achieve low power consumption [17]. The frequency divider chain consists of three divide-by-2 circuits and one divide-by-2/3 circuit. As a result, it can divide by 24 and 36 in the loop (i.e., divider ratio N1=24,36).The loop dynamic characteristics are designed to have the unity-gain bandwidth of 2.8 MHz and phase margin of 16° (VCO gain: 5 GHz/V,ICP=20 μA, divider ratio N1=24). When the divider ratio N1 equals to 36, the unity-gain bandwidth of 2.2 MHz and phase margin of 19° are achieved. The PLL has poor phase margin that is related to the low damping factor and the slow settling time, because final phase locking is done not only by the phase-locked loop but also by injection locking. Injection locking that is applied into a phase-locked loop helps the phase margin to be improved [21]. In this case, large capacitance of C2 is required to suppress the reference spur level due to the control voltage ripple. A loop bandwidth of the PLL is designed to be small enough compared to the lock range of injection locking to avoid the interference between two phase locking but can still achieve frequency locking.To achieve subharmonic locking, an AND-based pulser is used, which is able to tune the pulse width below 40 ps by the analog control. Also, a variable time-delay unit (ΔT) which consists of inverters and tristate inverters was applied to match the zero-crossing points of differential VCO outputs to the pulses for effective injection locking.


### 3.2. Reference PLL

The proposed ring VCO used in RPLL is based on a four-stage pseudo differential ring oscillator. The same delay cell shown in MPLL (Figure6(a)) is applied to widen frequency tuning range linearly. Also, long-gate channel MOS transistors are equipped in the delay cell to decrease VCO oscillation frequencies and reduce flicker noise characteristics as a reference signal into MPLL. Pulses which are generated by the on-chip pulser are injected into the left delay cell in the form of rail-to-rail pulses for injection locking. To maintain topological symmetry, an nMOS switch biased to 0 V is also applied in the other delay cells. We achieved the VCO tuning range of 0.805 GHz to 2.85 GHz across the rail-to-rail control voltage from the postlayout simulation of the VCO core with output buffers (90 nm CMOS process, VDD=1.0V).The tristate PFD and CP presented in Figure8 are implemented in RPLL. With postlayout simulation results of the charge pump (90 nm CMOS process, 1.0 V supply), the percentage mismatch error (ICP=100μA) for 0.32 V≤Vb≤0.70V is less than 2% and increases to less than 5% for 0.24 V≤Vb≤0.76V (VUP=1 V, VDN=0 V).As a loop filter (LF), a second-order lag-lead filter is implemented. The filter consists of a register (R=16 kΩ), and two on-chip capacitors (C1=41 pF, C2=1 pF). The frequency divider chain in RPLL consists of five divide-by-2 circuits. As a result, it can divide by 32 (i.e., divider ratio N2=32). Finally, the AND-based pulser and the variable time-delay unit (ΔT) were implemented for effective injection locking. In RPLL, an injection frequency of finj1 is same to a reference frequency of fref.


## 3.1. Main PLL

Figure6(a) shows the topology of the proposed delay cell that composes a ring VCO [13]. The delay cell contains an inverter latch as a negative conductance circuit that generates delay by positive feedback in order to satisfy the oscillation condition [14]. To tune the VCO output frequency widely, variable pMOS resistive loads are used. However, in the commonly used delay cells with pMOS resistive loads, the range of control voltage is limited from 0 V to the pMOS threshold voltage. In the proposed delay cell, a pMOS transistor is added into which the subcontrol voltage (Vbn) is input in order to make the range of sensitive voltages identical to the rail-to-rail voltage range (0 V to VDD). For this purpose, the bias level shifted by about VDD/2, Vbn, is input to the added pMOS transistor. As a result, the total equivalent resistance of the two pMOS transistors in parallel changes almost linearly versus the main control voltage, Vb. Consequently, the VCO output frequency can be tuned linearly across the wide tuning range [12, 13]. An nMOS switches are connected at the nodes between the differential nodes to achieve injection locking [15].(a) Proposed differential delay cell, (b) two-stage differential VCO of MPLL with a bias-level-shift circuit.
(a)
(b)The proposed ring VCO is shown in Figure6(b). It is based on a two-stage pseudo differential ring oscillator. Pulses which are generated by the on-chip pulser are injected into the left delay cell in the form of rail-to-rail pulses for injection locking. To maintain topological symmetry, an nMOS switch biased to 0 V is also applied in the right-side delay cell. We achieved the VCO tuning range of 6.02 GHz to 11.1 GHz across the rail-to-rail control voltage from the postlayout simulation of the VCO core with output buffers (90 nm CMOS process, VDD=1.0V).A tristate phase/frequency detector (PFD) is implemented, which consists of two D-flip flops, delay-path inverters, and an AND logic. The PFD detects phase and frequency difference between the reference signal and the divided VCO output and generates output pulses ofVUP and VDN which are input into the charge pump to reduce the difference.Figure7 shows an implemented current mirror circuit to generate stable constant current from the charge pump. Usually, stacked current mirrors design can obtain better DC headroom and linearity with longer channel lengths as shown in the left side of Figure 7. In this case, DC headroom of the output voltage (Vout) is expressed as 2(Δov+Vthn), where Δov is the overdrive voltage of MOS transistors (M3, M4), and Vthn is an nMOS threshold voltage. In the case of Sooch cascode current mirror as shown in the right side of Figure 7, the MOS transistor, M5, is forced to operate in the triode region. The DC headroom can be reduced as 2Δov since MOS transistors operate in the saturation region except for M5 [16]. Consequently, low voltage operation can be achieved.Figure 7
Sooch cascode current mirror circuit.Proposed current switching charge pump (CP) that employs Sooch cascode current mirror is shown in Figure8. Dummy switches are also implemented to maintain the balance between PFD outputs. Two external current sources ranged from  10 μA to 150 μA are used.Figure 8
Proposed charge-pump (CP) circuit and loop filter (LF).Figure9 shows postlayout simulation results of the proposed charge pump, when ICP=20 μA (90 nm CMOS process, 1.0 V supply). It shows that the charge pump can generate quite constant output current across the wide range of the output voltage (Vb). When VUP=1 V and  VDN=0 V, the result shows current mismatch between the up and down output currents as a function of the output voltage (Vb). The percentage mismatch error for 0.48 V≤Vb≤0.81V is less than 2% and increases to less than 5% for 0.21 V≤Vb≤0.85V.Figure 9
Charge-pump output current versus the control voltage (Vb), when ICP=20 μA.A second-order lag-lead filter that consists of a register and two capacitors is implemented as a loop filter (LF) of the loop to suppress the charge-pump ripple. (R=16 kΩ, C1=41 pF, C2=12 pF). In this case, on-chip MIM capacitors were used.The frequency divider consists of differential pseudo-nMOS latches to minimize chip area and achieve low power consumption [17]. The frequency divider chain consists of three divide-by-2 circuits and one divide-by-2/3 circuit. As a result, it can divide by 24 and 36 in the loop (i.e., divider ratio N1=24,36).The loop dynamic characteristics are designed to have the unity-gain bandwidth of 2.8 MHz and phase margin of 16° (VCO gain: 5 GHz/V,ICP=20 μA, divider ratio N1=24). When the divider ratio N1 equals to 36, the unity-gain bandwidth of 2.2 MHz and phase margin of 19° are achieved. The PLL has poor phase margin that is related to the low damping factor and the slow settling time, because final phase locking is done not only by the phase-locked loop but also by injection locking. Injection locking that is applied into a phase-locked loop helps the phase margin to be improved [21]. In this case, large capacitance of C2 is required to suppress the reference spur level due to the control voltage ripple. A loop bandwidth of the PLL is designed to be small enough compared to the lock range of injection locking to avoid the interference between two phase locking but can still achieve frequency locking.To achieve subharmonic locking, an AND-based pulser is used, which is able to tune the pulse width below 40 ps by the analog control. Also, a variable time-delay unit (ΔT) which consists of inverters and tristate inverters was applied to match the zero-crossing points of differential VCO outputs to the pulses for effective injection locking.


## 3.2. Reference PLL

The proposed ring VCO used in RPLL is based on a four-stage pseudo differential ring oscillator. The same delay cell shown in MPLL (Figure6(a)) is applied to widen frequency tuning range linearly. Also, long-gate channel MOS transistors are equipped in the delay cell to decrease VCO oscillation frequencies and reduce flicker noise characteristics as a reference signal into MPLL. Pulses which are generated by the on-chip pulser are injected into the left delay cell in the form of rail-to-rail pulses for injection locking. To maintain topological symmetry, an nMOS switch biased to 0 V is also applied in the other delay cells. We achieved the VCO tuning range of 0.805 GHz to 2.85 GHz across the rail-to-rail control voltage from the postlayout simulation of the VCO core with output buffers (90 nm CMOS process, VDD=1.0V).The tristate PFD and CP presented in Figure8 are implemented in RPLL. With postlayout simulation results of the charge pump (90 nm CMOS process, 1.0 V supply), the percentage mismatch error (ICP=100μA) for 0.32 V≤Vb≤0.70V is less than 2% and increases to less than 5% for 0.24 V≤Vb≤0.76V (VUP=1 V, VDN=0 V).As a loop filter (LF), a second-order lag-lead filter is implemented. The filter consists of a register (R=16 kΩ), and two on-chip capacitors (C1=41 pF, C2=1 pF). The frequency divider chain in RPLL consists of five divide-by-2 circuits. As a result, it can divide by 32 (i.e., divider ratio N2=32). Finally, the AND-based pulser and the variable time-delay unit (ΔT) were implemented for effective injection locking. In RPLL, an injection frequency of finj1 is same to a reference frequency of fref.


## 4. Measurement Results

### 4.1. Main PLL (MPLL)

Figures10(a) and 10(b) show chip micrograph of the differential ring VCO and a PLL, respectively. To clear the effectiveness of the proposed PLL, the VCO cell used in the PLL was also fabricated. They were fabricated by a 90 nm Si CMOS process. The area of the ring VCO core is 0.030 × 0.045 mm2 including the bias-level-shift circuit and the pulser. The PLL circuit occupies an area of 0.38 × 0.21 mm2. They were measured in 1.0 V supply condition. Also, the PLL circuit was measured using 20 μA-current-sources (ICP) into the charge pump.Chip micrographs; (a) proposed VCO and (b) proposed PLL.
(a)
(b)During free-running operation, the frequency tuning range of the VCO was from 6.35 GHz to 11.5 GHz as shown in Figure11. It was measured by using an Agilent Technologies E5052B signal source analyzer. It also shows that the VCO output frequency could be tuned quite linearly versus the rail-to-rail control voltage (Vb) due to the bias-level-shift circuit. When the VCO output frequency (f0) is 7.18 GHz, the total power consumption of the VCO (with the bias-level-shift circuit and pulser) was 8.4 mW.Figure 11
Measured frequency tuning range of the VCO.Phase noise characteristics of the VCO and PLL atf0≃fout=7.2 GHz without and with injection locking are shown in Figure 12 as measured by the signal source analyzer. In addition to them, phase noise characteristics of the 300 MHz reference signal are shown in Figures 12 and 14. A 1 MHz-offset phase noise of -75.8 dBc/Hz  was generated in the free-running VCO. With injection locking, a 1 MHz offset phase noise of -108 dBc/Hz was generated, which was improved by 32 dB compared to the former. On the other hand, a 1 MHz-offset phase noise of -91.3 dBc/Hz  was generated in the PLL when the PLL was only locked by the phase-locked loop. Due to the poor phase margin, gain peaking at the offset frequency of about 3 MHz was observed. With injection locking, a 1 MHz offset phase noise of -107 dBc/Hz was generated, which was improved by 16 dB compared to the former.Figure 12
Measured phase noise characteristics at 7.2 GHz from the VCO and PLL output without and with injection locking.Figure13 shows calculated phase noise characteristics by using (4) and the measurement phase noise of the free-running VCO and the reference signal as shown in Figure 12. The results show that wider lock range makes lower phase noise characteristics within the lock range. From the calculated result of fL=ωL/2π=40 MHz, (4) is well matched to the measurement results except the offset-frequency region up to about 30 kHz. It is because that flicker noise model as expressed in [5] is not included for simplicity and certain spurs occurred at the offset frequency of about 10 KHz were measured.Figure 13
Calculated phase noise by using (4) and measure phase noise characteristics as shown in Figure 12.Figure 14
Measured phase noise characteristics at 10.8 GHz from the VCO and PLL output without injection locking.Phase noise characteristics of the VCO and PLL atf0≃fout=10.8 GHz are shown in Figure 14. A 1MHzoffset phase noise of -79.5 dBc/Hz and -83.7 dBc/Hz were generated in the free-running VCO and the PLL, respectively. Phase noise reduction with injection locking could not be achieved since it was difficult to generate effective injection pulses with sufficient power for achieving the injection-locked condition at that high output frequency.


### 4.2. Cascaded PLL

Figure15 shows a chip micrograph of the proposed CPLL. It was fabricated by a 90 nm Si CMOS process. It includes both RPLL and MPLL that occupy an area of  0.11 mm2. It was measured in 1.0 V supply condition. Also, the PLL circuit was measured using 100 μA current sources into RPLL charge pump and 20 μA current-sources into MPLL charge pump. RPLL was locked to reference signals of 50 MHz which were generated by the pulse pattern generator.Figure 15
A chip micrograph of the proposed cascaded PLL.Figure16 shows the phase noise characteristics at frout=1.6 GHz (= 32 × 50 MHz) as measured by an Agilent Technologies E5052A signal source analyzer. Without injection locking, a 1 MHz-offset phase noise of -100 dBc/Hz  was generated in RPLL. Due to the poor phase margin, gain peaking at the offset frequency of about 4 MHz was observed. With injection locking, the measured phase noise was -116 dBc/Hz at an offset of 1 MHz. It shows a 16 dB phase-noise reduction with injection locking. Also, phase noise characteristics of the external reference signal are shown Figure 16. At 10 KHz and 1 MHz offset, the phase noise of the reference signal were -117 and -155 dBc/Hz, respectively.Figure 16
Measured phase noise characteristics of RPLL output at 1.6 GHz.Figure17 shows the phase noise characteristics at fmout=7.2 GHz (= 144 × 50 MHz). 0.2 GHz injection signals were injected when N2, N3, and N4 are corresponding to 36, 8, and 8, respectively. Also, 1.6 GHz injection signals were injected when N2, N3, and N4 are corresponding to 36, 1, and 8, respectively. Without injection into MPLL, a 1 MHz offset phase noise of -88 dBc/Hz was generated in the PLL. With integral subharmonic injection locking (fmout=36×finj2, finj2=0.2 GHz), the measured phase noise was -99 dBc/Hz at an offset of 1 MHz. With high-frequency half-integral subharmonic locking (fmout=4.5×finj2, finj2=1.6 GHz), we successfully achieved 2 dB lower phase noise at 1 MHz offset than the former. A 4 MHz offset phase noise was improved by 4 dB in the latter case, compared with the former. The results show that high-frequency reference injections can widen the injection lock range. However, there was a spur around the offset frequency of 25 MHz owing to the RPLL spur level, and the spur limited the lock range widening with high-frequency signal injections.Figure 17
Measured phase noise characteristics of CPLL output at 7.2 GHz.Usually, spurs are induced by periodic phase shift due to injection locking. The spur level can be expressed as follows:(8)Pspur,ωinjP0≈ω02Qωinj·PinjNPosc=ωLωinj,
where Pspur,ωinj represents the spur levels occurred by the reference signal at f0±finj, and  P0 is the injection-locked output power of the oscillator [22]. As shown in this equation, the spur level would be reduced lowering the lock range with the same reference frequency, however, which is undesirable to reduce phase noise characteristics.Calculated phase noise characteristics by using (6) and measure phase noise characteristics, as shown in Figures 12 and 16, are shown in Figure 18. In this case, the lock range was supposed to be proportional to the input frequency and the coefficient was 0.14, which was expected in Figure 13. In the results, phase noise characteristics especially at the offset frequency of 500 kHz, 700 kHz, and lower than 5 kHz due to the secondary VCO (VCO2) would be reduced by using high-frequency injection signals (finj=1.6 GHz, fL=224 MHz). In Figure 18, measured phase noise characteristics from the offset frequency of 30 kHz to 1 MHz were degraded compared with calculated results due to induced noise from the MPLL loop.Figure 18
Calculated phase noise by using (6) and measuring phase noise characteristics as shown in Figures 12 and 16.Figure19 shows the phase noise characteristics at fmout=9.6 GHz (= 192 × 50 MHz). In these cases, N2, N3, and N4 are corresponding to 24, 8, and 8, respectively. Without injection into MPLL, a 1 MHz offset phase noise of -85 dBc/Hz was generated in the PLL. With integral subharmonic injection locking (fmout=48×finj2, finj2=0.2 GHz), the measured phase noise was -93 dBc/Hz at an offset of 1 MHz. In Figure 19, spur levels around the offset frequency of 25 MHz were decreased, because the phase-locking effect of injection locking was decreased.Figure 19
Measured phase noise characteristics of CPLL output at 9.6 GHz.The PLL generated reference spurs of lower than-31 dBc at the output frequency of 7.2 GHz with 1.6 GHz injections, as shown in Figure 20(a). At the output frequency of 9.6 GHz with 0.2 GHz injections, reference spurs of lower than -27 dBc were measured as shown in Figure 20(b).Measured frequency spectra of CPLL output (a) at 7.2 GHz and (b) at 9.6 GHz.
(a)
(b)A performance summary at the output frequency of 7.2 GHz of the fabricated chips are given in Table3, when injection locking was established. It shows that high-frequency injections are effective to reduce the phase noise because a wide injection lock range can be achieved.Table 3
Performance summary atfout=7.2 GHz.
This work
MPLL VCO
MPLL
CPLL
f
out [GHz]
7.2
f
ref [MHz]
—
300
50
f
inj [MHz]
300
300
200
1600
f
out
/
f
inj
24
24
36
4.5
L
(
Δ
f
)
|
Δ
f
=
1
MHz [dBc/Hz]
-
108
-
107
-
99
-
101
Power consumption [mW]
8.4
14
25
Area [mm2]
0.0014
0.080
0.11A performance comparison of the PLL with other PLLs that were designed using various kinds of phase-locking methods is given in Table4. Unfortunately, the proposed PLL cannot cover wide frequency range from 6 GHz to 12 GHz as shown in Table 1, due to the VCO tuning range and limitation of tunable divider ratio. To make a fair in-band phase noise comparison between various kinds of PLL designs, the dependency of in-band phase noise on fref and N should be normalized out [23]. Therefore, normalized in-band phase noise Lnormalized was applied for comparison. The proposed PLL shows a relatively good Lnormalized value. Also its area and power consumption are small and comparable to that of other circuits.Table 4
Performance comparison of PLLs.
Reference
CMOS Technology
f
0 [GHz]
N
=
f
0
/
f
ref
L
in-band [dBc/Hz]
L
normalized
* [dBc/Hz2]
Power [mW]
Area [mm2]
VCO
This work
90 nm
1.6
32
-
116
-
223
11 (sim.)
0.031
Ring
7.2
144
-
101
-
221
25
0.11
9.6
192
-
93
-
216
27
[11]
90 nm
20
20
-
113
-
229
38
0.46
LC
[18]
90 nm
9.24
35
-
97
-
212
56
0.09
Ring
[19]
0.18μm
8.98
17
-
110
-
222
58
0.77
LC
[20]
0.18μm
8.45
32
-
98
-
212
117
5.5
LC
*Normalized in-band phase noise = Lin-band – 20log N – 10log fref.


## 4.1. Main PLL (MPLL)

Figures10(a) and 10(b) show chip micrograph of the differential ring VCO and a PLL, respectively. To clear the effectiveness of the proposed PLL, the VCO cell used in the PLL was also fabricated. They were fabricated by a 90 nm Si CMOS process. The area of the ring VCO core is 0.030 × 0.045 mm2 including the bias-level-shift circuit and the pulser. The PLL circuit occupies an area of 0.38 × 0.21 mm2. They were measured in 1.0 V supply condition. Also, the PLL circuit was measured using 20 μA-current-sources (ICP) into the charge pump.Chip micrographs; (a) proposed VCO and (b) proposed PLL.
(a)
(b)During free-running operation, the frequency tuning range of the VCO was from 6.35 GHz to 11.5 GHz as shown in Figure11. It was measured by using an Agilent Technologies E5052B signal source analyzer. It also shows that the VCO output frequency could be tuned quite linearly versus the rail-to-rail control voltage (Vb) due to the bias-level-shift circuit. When the VCO output frequency (f0) is 7.18 GHz, the total power consumption of the VCO (with the bias-level-shift circuit and pulser) was 8.4 mW.Figure 11
Measured frequency tuning range of the VCO.Phase noise characteristics of the VCO and PLL atf0≃fout=7.2 GHz without and with injection locking are shown in Figure 12 as measured by the signal source analyzer. In addition to them, phase noise characteristics of the 300 MHz reference signal are shown in Figures 12 and 14. A 1 MHz-offset phase noise of -75.8 dBc/Hz  was generated in the free-running VCO. With injection locking, a 1 MHz offset phase noise of -108 dBc/Hz was generated, which was improved by 32 dB compared to the former. On the other hand, a 1 MHz-offset phase noise of -91.3 dBc/Hz  was generated in the PLL when the PLL was only locked by the phase-locked loop. Due to the poor phase margin, gain peaking at the offset frequency of about 3 MHz was observed. With injection locking, a 1 MHz offset phase noise of -107 dBc/Hz was generated, which was improved by 16 dB compared to the former.Figure 12
Measured phase noise characteristics at 7.2 GHz from the VCO and PLL output without and with injection locking.Figure13 shows calculated phase noise characteristics by using (4) and the measurement phase noise of the free-running VCO and the reference signal as shown in Figure 12. The results show that wider lock range makes lower phase noise characteristics within the lock range. From the calculated result of fL=ωL/2π=40 MHz, (4) is well matched to the measurement results except the offset-frequency region up to about 30 kHz. It is because that flicker noise model as expressed in [5] is not included for simplicity and certain spurs occurred at the offset frequency of about 10 KHz were measured.Figure 13
Calculated phase noise by using (4) and measure phase noise characteristics as shown in Figure 12.Figure 14
Measured phase noise characteristics at 10.8 GHz from the VCO and PLL output without injection locking.Phase noise characteristics of the VCO and PLL atf0≃fout=10.8 GHz are shown in Figure 14. A 1MHzoffset phase noise of -79.5 dBc/Hz and -83.7 dBc/Hz were generated in the free-running VCO and the PLL, respectively. Phase noise reduction with injection locking could not be achieved since it was difficult to generate effective injection pulses with sufficient power for achieving the injection-locked condition at that high output frequency.


## 4.2. Cascaded PLL

Figure15 shows a chip micrograph of the proposed CPLL. It was fabricated by a 90 nm Si CMOS process. It includes both RPLL and MPLL that occupy an area of  0.11 mm2. It was measured in 1.0 V supply condition. Also, the PLL circuit was measured using 100 μA current sources into RPLL charge pump and 20 μA current-sources into MPLL charge pump. RPLL was locked to reference signals of 50 MHz which were generated by the pulse pattern generator.Figure 15
A chip micrograph of the proposed cascaded PLL.Figure16 shows the phase noise characteristics at frout=1.6 GHz (= 32 × 50 MHz) as measured by an Agilent Technologies E5052A signal source analyzer. Without injection locking, a 1 MHz-offset phase noise of -100 dBc/Hz  was generated in RPLL. Due to the poor phase margin, gain peaking at the offset frequency of about 4 MHz was observed. With injection locking, the measured phase noise was -116 dBc/Hz at an offset of 1 MHz. It shows a 16 dB phase-noise reduction with injection locking. Also, phase noise characteristics of the external reference signal are shown Figure 16. At 10 KHz and 1 MHz offset, the phase noise of the reference signal were -117 and -155 dBc/Hz, respectively.Figure 16
Measured phase noise characteristics of RPLL output at 1.6 GHz.Figure17 shows the phase noise characteristics at fmout=7.2 GHz (= 144 × 50 MHz). 0.2 GHz injection signals were injected when N2, N3, and N4 are corresponding to 36, 8, and 8, respectively. Also, 1.6 GHz injection signals were injected when N2, N3, and N4 are corresponding to 36, 1, and 8, respectively. Without injection into MPLL, a 1 MHz offset phase noise of -88 dBc/Hz was generated in the PLL. With integral subharmonic injection locking (fmout=36×finj2, finj2=0.2 GHz), the measured phase noise was -99 dBc/Hz at an offset of 1 MHz. With high-frequency half-integral subharmonic locking (fmout=4.5×finj2, finj2=1.6 GHz), we successfully achieved 2 dB lower phase noise at 1 MHz offset than the former. A 4 MHz offset phase noise was improved by 4 dB in the latter case, compared with the former. The results show that high-frequency reference injections can widen the injection lock range. However, there was a spur around the offset frequency of 25 MHz owing to the RPLL spur level, and the spur limited the lock range widening with high-frequency signal injections.Figure 17
Measured phase noise characteristics of CPLL output at 7.2 GHz.Usually, spurs are induced by periodic phase shift due to injection locking. The spur level can be expressed as follows:(8)Pspur,ωinjP0≈ω02Qωinj·PinjNPosc=ωLωinj,
where Pspur,ωinj represents the spur levels occurred by the reference signal at f0±finj, and  P0 is the injection-locked output power of the oscillator [22]. As shown in this equation, the spur level would be reduced lowering the lock range with the same reference frequency, however, which is undesirable to reduce phase noise characteristics.Calculated phase noise characteristics by using (6) and measure phase noise characteristics, as shown in Figures 12 and 16, are shown in Figure 18. In this case, the lock range was supposed to be proportional to the input frequency and the coefficient was 0.14, which was expected in Figure 13. In the results, phase noise characteristics especially at the offset frequency of 500 kHz, 700 kHz, and lower than 5 kHz due to the secondary VCO (VCO2) would be reduced by using high-frequency injection signals (finj=1.6 GHz, fL=224 MHz). In Figure 18, measured phase noise characteristics from the offset frequency of 30 kHz to 1 MHz were degraded compared with calculated results due to induced noise from the MPLL loop.Figure 18
Calculated phase noise by using (6) and measuring phase noise characteristics as shown in Figures 12 and 16.Figure19 shows the phase noise characteristics at fmout=9.6 GHz (= 192 × 50 MHz). In these cases, N2, N3, and N4 are corresponding to 24, 8, and 8, respectively. Without injection into MPLL, a 1 MHz offset phase noise of -85 dBc/Hz was generated in the PLL. With integral subharmonic injection locking (fmout=48×finj2, finj2=0.2 GHz), the measured phase noise was -93 dBc/Hz at an offset of 1 MHz. In Figure 19, spur levels around the offset frequency of 25 MHz were decreased, because the phase-locking effect of injection locking was decreased.Figure 19
Measured phase noise characteristics of CPLL output at 9.6 GHz.The PLL generated reference spurs of lower than-31 dBc at the output frequency of 7.2 GHz with 1.6 GHz injections, as shown in Figure 20(a). At the output frequency of 9.6 GHz with 0.2 GHz injections, reference spurs of lower than -27 dBc were measured as shown in Figure 20(b).Measured frequency spectra of CPLL output (a) at 7.2 GHz and (b) at 9.6 GHz.
(a)
(b)A performance summary at the output frequency of 7.2 GHz of the fabricated chips are given in Table3, when injection locking was established. It shows that high-frequency injections are effective to reduce the phase noise because a wide injection lock range can be achieved.Table 3
Performance summary atfout=7.2 GHz.
This work
MPLL VCO
MPLL
CPLL
f
out [GHz]
7.2
f
ref [MHz]
—
300
50
f
inj [MHz]
300
300
200
1600
f
out
/
f
inj
24
24
36
4.5
L
(
Δ
f
)
|
Δ
f
=
1
MHz [dBc/Hz]
-
108
-
107
-
99
-
101
Power consumption [mW]
8.4
14
25
Area [mm2]
0.0014
0.080
0.11A performance comparison of the PLL with other PLLs that were designed using various kinds of phase-locking methods is given in Table4. Unfortunately, the proposed PLL cannot cover wide frequency range from 6 GHz to 12 GHz as shown in Table 1, due to the VCO tuning range and limitation of tunable divider ratio. To make a fair in-band phase noise comparison between various kinds of PLL designs, the dependency of in-band phase noise on fref and N should be normalized out [23]. Therefore, normalized in-band phase noise Lnormalized was applied for comparison. The proposed PLL shows a relatively good Lnormalized value. Also its area and power consumption are small and comparable to that of other circuits.Table 4
Performance comparison of PLLs.
Reference
CMOS Technology
f
0 [GHz]
N
=
f
0
/
f
ref
L
in-band [dBc/Hz]
L
normalized
* [dBc/Hz2]
Power [mW]
Area [mm2]
VCO
This work
90 nm
1.6
32
-
116
-
223
11 (sim.)
0.031
Ring
7.2
144
-
101
-
221
25
0.11
9.6
192
-
93
-
216
27
[11]
90 nm
20
20
-
113
-
229
38
0.46
LC
[18]
90 nm
9.24
35
-
97
-
212
56
0.09
Ring
[19]
0.18μm
8.98
17
-
110
-
222
58
0.77
LC
[20]
0.18μm
8.45
32
-
98
-
212
117
5.5
LC
*Normalized in-band phase noise = Lin-band – 20log N – 10log fref.


## 5. Conclusion

An inductorless PLL architecture, using the combination of a phase-locked loop, and injection locking with a ring VCO was proposed. The proposed CPLL that consists of two PLLs was designed in order to generate high-frequency output signals with low-frequency external reference signals. High-frequency half-integral subharmonic injection locking to improve the phase noise characteristics of the inductorless PLL was implemented.The injection-locked PLL was fabricated by adopting 90 nm Si CMOS technology. A 1 MHz-offset phase noise of-101 dBc/Hz  was achieved at an output frequency of 7.2 GHz, which was improved by 25 dB compared with that of the free-running VCO. The area of this inductorless PLL was as small as  0.11 mm2 with low power consumption of 25 mW.



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*Source: 584341-2013-03-04.xml*