# Single-Stage Coupled-Inductor Sepic-Type HB-LED Driver with Soft Switching for Universal Line Input

Authors: Chih-Lung Shen; Kuo-Kuang Chen
Journal: Mathematical Problems in Engineering
 (2012)

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## Abstract

This paper proposes a single-stage Sepic-type high brightness LED driver for universal line input to perform power factor correcting and LED dimming. In the driver, a coupled inductor is introduced to replace with two separate inductors to lower volume and cost. A soft-switching cell is embedded into the driver to obtain zero-voltage switching (ZVS) feature so as to furthermore improve driver efficiency. Mathematical derivation and detailed discussion is presented. A prototype is designed, analyzed and implemented, which demonstrates the feasibility of the driver and verifies the theoretical analysis.


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## Body

## 1. Introduction

Power electronic devices with front-end rectifier are widely used in industry, commerce, and transportation, which generate current harmonics, produce power pollution, and result in low power factor. Therefore, there are international harmonic standards (such as IEC-1000 and IEC-555) to confine power pollution. In order to meet the requirements of the standards, the input current waveform of a device has to be shaped by a power factor corrector (PFC) to eliminate current harmonics and improve power factor.The PFCs can be briefly classified into two types. One is passive and the other is active. Passive-type PFC is mainly constructed by inductors and capacitors. Low efficiency, heavy weight, and large volume are its major disadvantages. Besides, in general power factor merely is improved to around 0.8. For active type, active switch, diode and energy-stored component are used to achieve near unity power factor, of which topologies have Buck, Boost, Buck-Boost, ′Cuk, Zeta, Sepic, and Flyback. Conventional Buck-type PFC can obtain an output voltage smaller than ac input voltage. However, only a power factor of 0.95 is met [1]. The Boost structure attains better power factor correction feature but its output voltage is higher than ac-side voltage, and power components withstand high voltage stresses [2, 3]. The Buck-Boost PFC can obtain an output voltage magnitude either larger or smaller than the input. Nevertheless, there is a polarity reversal on the output, and an isolation driver for active switch is required [4, 5]. The ′Cuk, Zeta, Sepic, and Flyback topologies can resolve the problems caused from the Buck-Boost. Among them the Sepic type possesses better performance in total harmonics distortion (THD), efficiency, and power factor correction [6–13]. However, the Sepic PFC needs two separate inductors like ′Cuk and Zeta.In this paper a dsPIC-based coupled-inductor Sepic-type converter for high-brightness light-emitting-diode  (HB LED) lighting applications is presented, which can not only step down input voltage directly but also perform power factor correcting, drive LED panel, and complete dimming function. A soft-switching cell is proposed to reduce switching losses, improving efficiency. In addition, a bypass circuit in parallel with each LED is also proposed, which is cost-effective and suitable for IC process. A dual-loop control approach, which contains inner control loop and outer control loop to shape input current and to regulate output voltage, is also presented. In LED panel, the current of each LED string is sensed and controlled to accomplish current sharing and dimming feature. A 100 W prototype is designed, analyzed, and implemented. Simulations and practical results have demonstrated the feasibility of the single-stage Sepic-type LED driver and verified the aforementioned functions.


## 2. Power Stage Configuration

For high mains voltage or in low output voltage application, in general a Boost-type PFC is cascaded with a full-wave rectifier in the input and a step-down dc/dc converter in the output, as shown in Figure1. The PFC stage shapes a high-crest-factor current caused by the full-wave rectifier into a purely sinusoidal waveform in phase with line voltage. However, the input voltage also is boosted. Therefore, it is required that a dc/dc converter is adopted to drop voltage for dc load. Power is processed by two stages, a PFC and a dc/dc converter, lowering overall efficiency and increasing cost. To release the mentioned drawbacks, a single-stage step-down PFC is adopted to simplify the structure of power-conversion stage, as shown in Figure 2, in which the PFC stage performs power factor correcting as well as steps down its input voltage to a desired level. In this paper, a dsPIC-based Sepic-type configuration is presented to serve as the single-stage step-down PFC for HB-LED driving, as shown in Figure 3. Figure 4 shows the corresponding main-stage schematic, in which the diodes D5 and D6 are introduced to prevent opposite current from flowing through inductors L1 and L2, respectively. In Figure 4, the two separate inductors L1 and L2 can be coupled magnetically. In addition, a proposed soft-switching cell, including an active switch Q2, an inductor Lr,  and a capacitor Cr, to achieve zero-voltage switching (ZVS) feature, is embedded into the power stage to reduce switching loss. Figure 5 is the derived single-stage coupled-inductor soft-switching Sepic-type HB-LED driver.Figure 1
A PFC stage cascaded with a full-wave rectifier in the input and a step-down dc/dc converter in the output.Figure 2
A block diagram representing single-stage step-down PFC.Figure 3
A block diagram representing that Sepic-type converter serves as PFC for LED lighting application.Figure 4
The main-stage schematic of a Sepic-type PFC.Figure 5
The proposed single-stage coupled-inductor soft-switching Sepic-type HB-LED driver.


## 3. Operation Principle of Power Stage

In Figure5, while the soft-switching Sepic-type HB-LED driver operates in boundary conduction mode and with peak current control, a high power factor can readily be achieved. As a result, the envelope of the input current will follow the shape of line voltage to be sinusoidal, leading to unity power factor. As the resonant frequency of the soft-switching cell is much higher than switching frequency of main power circuit, over a switching cycle the operation of the driver can be divided into eight modes. Figure 6 is the corresponding circuits, and the related conceptual key waveforms are shown in Figure 7. The eight operation modes during a switching period are discussed as follows.Equivalent circuits corresponding to the eight operation modes: (a) mode 1, (b) mode 2, (c) mode 3, (d) mode 4, (e) mode 5, (f) mode 6, (g) mode 7, and (h) mode 8.
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)Figure 7
The related conceptual key waveforms.(1) Mode 1 (t0≤t<t1, Figure 6(a))
During this time interval, switchQ1 is on and Q2 off. The inductor currents of iL1 and iLr are linearly built, and the capacitor C2 dumps energy to inductor L2 by the way of Lr, Q1, and D6. At the same time, the capacitor C3 supplies power for load. The time constant determined by capacitance of C3 and load resistance is much larger than switching period so that output voltage vo can be regarded as a constant. At time t=t1, this mode is ended and Q2 is turned off. In mode 1, the voltage across the resonant inductor, vLr can be calculated by
(3.1)vLr=(vC1-VD5-VDS1,on)⋅LrL1+Lr,
in which vC1 expresses rectified half sine wave, VD5 is the cut-in voltage of diode D5, and VDS1,on stands for the turn-on voltage across switch Q1. Then, inductor current iLr is determined as follows:
(3.2)iLr(t)=iLr(0)+∫0tvC1(t′)-VD5-VDS1,onLr+L1dt′.
In (3.2), the initial value of inductor current iLr(0) is found by the end of mode 8.(2) Mode 2 (t1≤t<t2, Figure 6(b))
The switchQ1  is turned off at t1. The inductor L1 discharges through the path of D5, resonant inductor Lr, and parasitical capacitor Cb1. Meanwhile, the capacitor C2 still dumps energy to L2, and dc load draws power from C3. Since typical value of Cb1 is far smaller than the capacitance of C2, the voltage vDS1 across Cb1 increases rapidly. Applying KVL to the loop, C2-Lr-Q1-D6-L2, one can obtain the following equivalent:
(3.3)vC2-LrdiLrdt-vDS1-VD6-L2diLrdt=0,
in which VD6 is the cut-in voltage of diode D6. Rearranging (3.3) yields
(3.4)iLr(t)=iLr(t1)+1Lr+L2∫t1t(vC2(t′)-vDS1-VD6)dt′.
The iLr(t1) is the initial value of iLr at mode 2, which can be found by (3.2). At t=t2, the voltage vDS1 reaches vC2+vo and this mode is terminated.(3) Mode 3 (t2≤t<t3, Figure 6(c))
During this time interval, inductorsL1 and Lr still discharge energy, and voltage vDS1 increases. The diode D7 starts conducting, and the voltage across L2 is equal to output voltage vo. Therefore, L2 dumps energy to the output, and the inductor current iL2 is expressed by
(3.5)iL2(t)=-vOL2(t-t2)+iL2(t2).
The capacitor Cb1 will be charged to Vstress  1, which is also the voltage stress of Q1. That is,
(3.6)Vstress  1=[vCr+vC1-vL1]t=t3.(4) Mode 4 (t3≤t<t4, Figure 6(d))
Both inductorsL1 and L2 release energy continuously but capacitor C2 charges. The parasitical capacitor of switch Q2 starts dumping energy by the way of Cr and Lr until vDS2 drops to zero. The resonant frequency of the loop Lr-Cb2-Cr and the voltage across Q2 can be found as follows, respectively:
(3.7)fr,mode   4=12πCb2+CrLr⋅Cb2⋅Cr,vDS2(t)=vCb2(t3)cos⁡⁡(2πfr,mode  4(t-t3))+iLr(t3)Lr⋅Cb2⋅CrCb2+Crsin⁡(2πfr,mode  4(t-t3)).(5) Mode 5 (t4≤t<t5, Figure 6(e))
The body diode ofQ2 conducts, and inductor Lr resonates with Cr. The resonant frequency in the soft-switching cell during this mode is
(3.8)fr,mode  5=12πLr⋅Cr,
In addition, the following relationship holds:
(3.9)LrdiLrdt=-1Cr∫t4tiLr(t′)dt′-vCr(t4)-VDb2.
The VDb2 is the voltage drop on the body diode Db2. According to (3.9), resonant inductor current iLr can be obtained by:
(3.10)iLr(t)=iLr(t5)cos⁡⁡(t-t5)Lr⋅Cr-VCr(t5)CrLrsin⁡⁡(t-t5)Lr⋅Cr.
During this time interval, switchQ2 is tuned on with ZVS. Operation of the driver enters into next mode as the current iLr decreases to zero.(6) Mode 6 (t5≤t<t6, Figure 6(f))
The energy stored in resonant capacitorCr is dumped to Lr via Q2. As a result, the current iLr increases negatively. In this time period, inductors L1 and L2 release energy but C2 charges. At t=t6, Q2 is turned off and this mode is terminated.(7) Mode 7 (t6≤t<t7, Figure 6(g))
SwitchesQ1 and Q2 are off. The stored energy in the parasitical capacitor Cb1 is drawn by inductor Lr and vDS1 decreases. This mode ends when vDS1 drops to zero. In this mode, the inductor Lr resonates with Cb1 under the frequency of
(3.11)fr,mode  7=12πLr⋅Cb1.(8) Mode 8 (t7≤t<t8, Figure 6(h))
The energy stored inLr is discharge by the way of C2, D7, C3, and Db1. In this time interval, switch Q1 is triggered. This mode is terminated while iL1 equals zero. A complete switching cycle is ended at t=t8, at which switch Q1 has been turned on again.


## 4. Control of Driver

The proposed HB-LED driver not only steps down input voltage but also performs power factor correcting and functions as dimming feature. Dual-loop control and average-current control are adopted to achieve power factor correction and to regulate HB-LED current, respectively.


### 4.1. Control of Power Factor Correction

Figure8 shows the block diagram of the dual-loop control. Zero-crossing point of the line voltage is detected by the zero-crossing detector, and, then, the sine-wave generator produces a unity sine wave in phase with the line voltage. In the dual-loop control, output voltage is fed back and compared with reference Vref for determining the amplitude of current command. Meanwhile, input current is sensed and compared with current command for the determination of appropriate control signals driving Q1 and Q2. With the dual-loop control, input current shaping and output voltage regulating are readily accomplished over universal line-voltage range.Figure 8
A block diagram to represent the control of power factor correction.The driver operates in boundary conduction mode to perform power factor correcting. Therefore, on-time intervalTon of the main switch Q1 within one switching cycle can be represented as
(4.1)Ton=iL1,peakvC1⋅(L1+Lr).
The iL1,peak stands for peak value of inductor current through L1 and is obtained from
(4.2)iL1,peak=2IPK|sin⁡⁡(2πfLt)|.
In (4.2), fL is the line frequency and IPK expresses the amplitude of line current. In addition, off-time interval Toff of the main switch Q1 within one switching cycle is found by
(4.3)Toff=iL1,peakvC2+vo-vC1⋅L1.
Suppose that voltage drop on the input diodes can be neglected. Thus, vC1 can be expressed as
(4.4)vC1=VP|sin⁡⁡(2πfst)|,
where VP is the amplitude of line voltage. From (4.1)–(4.4), determination for Ton and Toff of a control signal can be further derived and becomes
(4.5)Ton=2IPKVP⋅(L1+Lr),Toff=2IPK|sin⁡⁡(2πfLt)|vC2+vo-VP|sin⁡(2πfLt)|⋅L1.
Since the switching frequency of the driver, fsw, is
(4.6)fsw=1Ton+Toff,
with the relationships of (4.5), expression for fsw is rewritten as
(4.7)fsw=VP(vC2+vo-VP|sin⁡⁡(2πfLt)|)2IPK((vC2+vo)(L1+Lr)-(L1+Lr-1)(VP|sin⁡⁡(2πfLt)|)).


### 4.2. Dimming Control of HB-LED Panel

Each string current of HB-LED panel is controlled by current regulator to achieve current sharing and dimming feature. The current regulator mainly includes an active switch and a current sensor, as shown in Figure9. String current is sensed, and, then, according to its average value the duty ratio of the active switch is determined so as to accomplish 400 Hz burst-mode current control. Consequently, string current can be controlled to achieve luminance balance and dimming feature. The associated average-current calculation and dimming signal determination are all-digital implementation, of which control block diagram is illustrated in Figure 10.Figure 9
The HB-LED panel with current regulators and by-pass circuits.Figure 10
A block diagram to represent the control for LED panel.In Figure9, duty ratio of the active switch in the jth LED string, Ddim,j, can be expressed as
(4.8)Ddim,j=Tdim,on,jTdim,
where Tdim denotes the period of dimming signal and Tdim,on,j is the on-state time interval of the active switch in the jth LED string.  In Figure 10, average value of the jth-string sensed current is calculated by
(4.9)Is,j=1Tdim∫0Tdim,on,jis,j(t)dt.
Additionally, while the jth active switch is closed, a corresponding current through the jth LED string has to be
(4.10)ILED,on,j=vO-Nj⋅Vf,LEDNj⋅Rd.
In (4.10), Nj is the total number of LEDs in the jth string; Vf,LED and Rd are the forward voltage and equivalent series resistance of LED, respectively. Since Is,j can be also evaluated by
(4.11)Is,j=Ddim,j⋅ILED,on,j,
then, from (4.9)-(4.11) the following equivalent holds:
(4.12)Ddim,j=Nj⋅RdTdim(vo-Nj⋅Vf,LED)∫0Tdim,on,jis,j(t)dt.
Based on (4.12), to determine Ddim,j, the values of Rf and Vf,LED should be given in advance, which leads to the determination error caused from the aging effect of LED. To avoid the drawback, the difference between the average sensed current Is,j and a reference current Iref is amplified and then compared with a triangular waveform so as to fulfill pulse-width-modulation (PWM) current control, as shown in Figure 10. The corresponding control law can be expressed as follows:
(4.13)Ddim,j=Vtri,peak/2+Kp(Iref-Is,j)Vtri,peak,
where Vtri,peak is the peak value of the triangular waveform and Kp stands for a constant. The Ddim,j is in the range of 0-1.In this paper, a by-pass circuit is also presented, which is in parallel with LED, as shown in Figure9. While LED being out of order, it is triggered and provides an alternative path to continue string current. As the presented by-pass circuit conducts, voltage drop across its terminals is about 1 V. Compared with conventional single-zener-diode by-pass circuit, of which conduction voltage drop is larger than 3.3 V, the power dissipation of the presented by-pass circuit is much smaller than that of the conventional one.


## 4.1. Control of Power Factor Correction

Figure8 shows the block diagram of the dual-loop control. Zero-crossing point of the line voltage is detected by the zero-crossing detector, and, then, the sine-wave generator produces a unity sine wave in phase with the line voltage. In the dual-loop control, output voltage is fed back and compared with reference Vref for determining the amplitude of current command. Meanwhile, input current is sensed and compared with current command for the determination of appropriate control signals driving Q1 and Q2. With the dual-loop control, input current shaping and output voltage regulating are readily accomplished over universal line-voltage range.Figure 8
A block diagram to represent the control of power factor correction.The driver operates in boundary conduction mode to perform power factor correcting. Therefore, on-time intervalTon of the main switch Q1 within one switching cycle can be represented as
(4.1)Ton=iL1,peakvC1⋅(L1+Lr).
The iL1,peak stands for peak value of inductor current through L1 and is obtained from
(4.2)iL1,peak=2IPK|sin⁡⁡(2πfLt)|.
In (4.2), fL is the line frequency and IPK expresses the amplitude of line current. In addition, off-time interval Toff of the main switch Q1 within one switching cycle is found by
(4.3)Toff=iL1,peakvC2+vo-vC1⋅L1.
Suppose that voltage drop on the input diodes can be neglected. Thus, vC1 can be expressed as
(4.4)vC1=VP|sin⁡⁡(2πfst)|,
where VP is the amplitude of line voltage. From (4.1)–(4.4), determination for Ton and Toff of a control signal can be further derived and becomes
(4.5)Ton=2IPKVP⋅(L1+Lr),Toff=2IPK|sin⁡⁡(2πfLt)|vC2+vo-VP|sin⁡(2πfLt)|⋅L1.
Since the switching frequency of the driver, fsw, is
(4.6)fsw=1Ton+Toff,
with the relationships of (4.5), expression for fsw is rewritten as
(4.7)fsw=VP(vC2+vo-VP|sin⁡⁡(2πfLt)|)2IPK((vC2+vo)(L1+Lr)-(L1+Lr-1)(VP|sin⁡⁡(2πfLt)|)).


## 4.2. Dimming Control of HB-LED Panel

Each string current of HB-LED panel is controlled by current regulator to achieve current sharing and dimming feature. The current regulator mainly includes an active switch and a current sensor, as shown in Figure9. String current is sensed, and, then, according to its average value the duty ratio of the active switch is determined so as to accomplish 400 Hz burst-mode current control. Consequently, string current can be controlled to achieve luminance balance and dimming feature. The associated average-current calculation and dimming signal determination are all-digital implementation, of which control block diagram is illustrated in Figure 10.Figure 9
The HB-LED panel with current regulators and by-pass circuits.Figure 10
A block diagram to represent the control for LED panel.In Figure9, duty ratio of the active switch in the jth LED string, Ddim,j, can be expressed as
(4.8)Ddim,j=Tdim,on,jTdim,
where Tdim denotes the period of dimming signal and Tdim,on,j is the on-state time interval of the active switch in the jth LED string.  In Figure 10, average value of the jth-string sensed current is calculated by
(4.9)Is,j=1Tdim∫0Tdim,on,jis,j(t)dt.
Additionally, while the jth active switch is closed, a corresponding current through the jth LED string has to be
(4.10)ILED,on,j=vO-Nj⋅Vf,LEDNj⋅Rd.
In (4.10), Nj is the total number of LEDs in the jth string; Vf,LED and Rd are the forward voltage and equivalent series resistance of LED, respectively. Since Is,j can be also evaluated by
(4.11)Is,j=Ddim,j⋅ILED,on,j,
then, from (4.9)-(4.11) the following equivalent holds:
(4.12)Ddim,j=Nj⋅RdTdim(vo-Nj⋅Vf,LED)∫0Tdim,on,jis,j(t)dt.
Based on (4.12), to determine Ddim,j, the values of Rf and Vf,LED should be given in advance, which leads to the determination error caused from the aging effect of LED. To avoid the drawback, the difference between the average sensed current Is,j and a reference current Iref is amplified and then compared with a triangular waveform so as to fulfill pulse-width-modulation (PWM) current control, as shown in Figure 10. The corresponding control law can be expressed as follows:
(4.13)Ddim,j=Vtri,peak/2+Kp(Iref-Is,j)Vtri,peak,
where Vtri,peak is the peak value of the triangular waveform and Kp stands for a constant. The Ddim,j is in the range of 0-1.In this paper, a by-pass circuit is also presented, which is in parallel with LED, as shown in Figure9. While LED being out of order, it is triggered and provides an alternative path to continue string current. As the presented by-pass circuit conducts, voltage drop across its terminals is about 1 V. Compared with conventional single-zener-diode by-pass circuit, of which conduction voltage drop is larger than 3.3 V, the power dissipation of the presented by-pass circuit is much smaller than that of the conventional one.


## 5. Design Considerations

The inductances and capacitances,L1, L2, C2, and C3, influence the performances of the single-stage driver significantly. Determinations for L1 and L2 are presented as follows:(5.1)L1=Ll1Ll2+LmLl1+n2LmLl2Ll2-(n-1)Lm,L2=Ll1Ll2+LmLl1+n2LmLl2Ll1+n(n-1)Lm,
in which n is the turns ratio of the coupled inductors, Lm denotes the magnetizing inductance, and Ll1 and Ll2 stand for leakage inductances of winding 1 and winding 2, respectively. In addition, the capacitances C2 and C3 are obtained by
(5.2)C2=LeΔVC1(max⁡)⋅IPK22⋅1(Vo+2VAC⁡(min⁡)),C3=Io2⋅π⋅fL⋅ΔVo,
where Le equals Ll1//Ll2, Vo and ΔVo represent dc-bus voltage and its ripple component, in turn, and VAC(min) expresses the rms value of the minimum line voltage. The peak value of the inductor current iL1 can also be expressed as follows:
(5.3)iL1,peak(t)=VPTon|sin⁡⁡(2fLπt)|L1.
Then, the filtered input current is determined by
(5.4)|is,filtered(t)|=2Ts∫0Ts/2iL1(t)dt=2VpTonTs⋅(L1+Lr)(fL⋅π).
In addition, the power drawn from line voltage can be computed in the following:
(5.5)Pin=2Ts∫0Ts/2vs(t)⋅is,filtered(t)dt=2Vp2Ton+Ts(L1+Lr)Ts⋅(L1+Lr)(fL⋅π).In Figure8, the output voltage vo is divided by the two resistors, Rm and Rs, with 1% accuracy such that the voltage vRs can be described as
(5.6)vRs=voRs(1±1%)Rs(1±1%)+Rm(1±1%).
Suppose that a 10-bit analog-to-digital converter (ADC) is used. Therefore, the ADC resolution is calculated as
(5.7)Resolution=SupplyVoltage10-bitADC=5210≅0.00488(V).
Thus, the maximum deviation of vRs after analog-to-digital conversion is
(5.8)vRs,con|max=vRs±0.0048.
Accordingly, the deviation on the output voltage, Δvo,  can be found by
(5.9)Δvo=±0.0048Rs(1±1%)+Rm(1±1%)Rs(1±1%).


## 6. Simulations and Hardware Measurements

A prototype of the proposed HB-LED driver is built to demonstrate the theoretical analysis and to verify the feasibility, of which controller is implemented on a 16-bit disPIC-30F4011 chip. The adopted microcontroller comprises a 10-bit ADC with conversion rate up to 500 Ksps, 9 input channels, 6 PWM outputs, and 5 16-bit timers. It fulfills the controlling of power factor correction, current sharing, and dimming. The driver has been designed according to the following specifications:input voltage:85~265 V,output power: 100 W,output current: 1.75 A,output voltage: 58 V,LED: LUMILEDS 1.2 W/3.42 V/0.35 A,LED panel: 5 strings, 17 pieces in series for each string.Component values and important parameters are determined as:Q2: IRF730 (400 V/5.5 A),Q1: 17N80C3 (800 V/17 A),L1 = 1.2 mH, L2= 0.77 mH, Lr = 0.1 mH,C1 = 0.1 μF, C2 = 0.25 μF, C3 = 100 μF, and Cr = 0.05 μF.Figure 11 is the waveforms of voltage and current of the main switch Q1, while Figure 12 shows the waveforms of Q2 in the soft-switching cell. From Figures 11 and 12, it can be observed that zero-voltage switching (ZVS) feature is achieved by the both switches Q1 and Q2. Figure 13 is the simulated waveform of the current iL1. Figure 14 shows the simulated line voltage and input current when mains voltage is 110 V. For 220 V mains input, the simulated line voltage and input current are shown in Figure 15. Figure 16 shows the hardware measurement of line voltage and input current while mains voltage is 110 V. From Figures 13–16, it can be found that a unity power factor is achieved by the single-stage HB-LED driver. Figure 17 shows the harmonics of the input current measured by PM3000 and then compared with IEC6100-3-2 class C. From Figure 17, it can be observed that the line current harmonics are much less than the requirements of the standard. Power factor and efficiency measurements are shown in Figures 18 and 19, in turn, illustrating that high power factor and efficiency can be achieved by the single-stage HB-LED driver.Figure 11
Voltage and current waveforms of switchQ1.Figure 12
Voltage and current waveforms of switchQ2.Figure 13
The current waveform of the inductorL1.Figure 14
Line voltage and input current when mains voltage is 110 V.Figure 15
Line voltage and input current when mains voltage is 220 V.Figure 16
Practical results of line voltage and input current.Figure 17
Measured input current harmonics.Figure 18
Power factor measurement over universal-line input range.Figure 19
Measured efficiency over universal-line input range.


## 7. Conclusion

This paper has proposed a single-stage Sepic-type soft-switching HB-LED driver with coupled inductor for universal line input. The proposed driver not only can perform power factor correcting but also achieve zero-voltage switching feature and step down input voltage directly. Consequently, a unity power factor is obtained and efficiency is improved. In the driver, its output voltage can be much smaller than the ac-side voltage, reducing component stresses significantly. Therefore, the driver is suitable for the applications of high-line voltage and/or low output voltage. To drive LED panel, an all-digital controller is also presented for power factor correcting, dc-bus voltage regulating, current sharing, and LED dimming, which is implemented on a 16-bit disPIC chip. A prototype of the designed single-stage driver to ballast 100 W 58 V HB-LED panel has been built. The simulations and practical measurements have verified the feasibility and features of the single-stage HB-LED driver.



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*Source: 593568-2012-07-26.xml*