# Extra-High-Voltage DC-DC Boost Converters Topology with Simple Control Strategy

Authors: P. Sanjeevikumar; K. Rajambal
Journal: Modelling and Simulation in Engineering
 (2008)

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## Abstract

This paper presents the topology of operating DC-DC buck converter in boost mode for extra-high-voltage applications. Traditional DC-DC boost converters are used in high-voltage applications, but they are not economical due to the limited output voltage, efficiency and they require two sensors with complex control algorithm. Moreover, due to the effect of parasitic elements the output voltage and power transfer efficiency of DC-DC converters are limited. These limitations are overcome by using the voltage lift technique, opens a good way to improve the performance characteristics of DC-DC converter. The technique is applied to DC-DC converter and a simplified control algorithm in this paper. The performance of the controller is studied for both line and load disturbances. These converters perform positive DC-DC voltage increasing conversion with high power density, high efficiency, low cost in simple structure, small ripples, and wide range of control.  Simulation results along theoretical analysis  are provided to verify its performance.


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## Body

## 1. Introducton

Proceeding
to the paper work [1], other two topologies are developed for extra-high-voltage
applications. Traditional DC‐DC boost converters are used in extra-high-voltage
applications. But they are not economical due to the limited output voltage,
efficiency, and they require two sensors with complex control algorithm. Because of
the effect of parasitic elements, the output voltage and
transfer efficiency of DC‐DC converters are limited. Voltage lift technique is
a popular method widely applied in electronic circuit design. It
has been successfully employed in DC‐DC converter [1–5] applications in
recent years, and opened a way to design high-voltage gain converters. The output voltage increases stage-by-stage along the geometric progression. So to overcome these limitations and
to make the DC‐DC converter with a simple control loop, a new technique called
voltage lift technique is used [6–11].In this paper, a
new series ofDC‐DC converter topologies is analyzed which is different from classical
boost converter. This paper
introduces positive output boost converters employed with voltage lift
technique that implements the output voltage increase in a simple geometric
progression. They also effectively enhance the voltage transfer gain as per
power-law terms. The performance of this DC‐DC converter is superior to classical
DC‐DC with reduced control scheme. The performance of this
DC‐DC converter is superior to classical DC‐DC with the following advantages.
(i)
It performs similar
to classicalDC‐DC boost converter with comparatively high-voltage transfer
ratio.(ii)
Wide
range of control with smooth ripple at the output voltage is an added advantage
of this proposed converter.(iii)
High
power density with high efficiency than classical boost converter.(iv)
Closed-loop
controller requires only one sensor.
In this paper, the operation and mathematical
analysis of the proposed converters I and II are presented. An algorithm is
developed to generate PWM pulses for the N-channel MOSFET. The simulation model of the converter is
developed in MATLAB7 using simulink toolbox.
Simulation is carried out to study the performance of the converter under
line and load disturbances. The
simulation results are presented and they closely match with the theoretical
results. The effectiveness of the converter is shown by comparing the
performance with the classical boost converter.


## 2. Boost Converter Circuits

### 2.1. Topology-I

The
proposed topology of new series of boost converter is derived from theDC‐DC
boost
converter circuit. Topology-I
is a boost converter circuit with the voltage lift components, that is, additional three stages of inductor and capacitor along with the basic circuit
are shown in Figure 1. In this topology, the switch S is N-channel power
MOSFET device (NMOS) and it is driven by a pulse-width-modulated (PWM) switching signal with variable frequency f and conduction duty k. For this
circuit, the load is usually resistive, R=V0/I0.Figure 1
Topology-I ofDC‐DC boost converter.The basic principle of this circuit in
boosting up the output voltage is charging and discharging reactive elements into a load,
controlling the levels of charge, and consequently the output voltage by
switching theDC supply in and out of the circuit at very high
frequencies. They include a freewheeling diode to protect the switch from the
inductors high reverse currents, and this also ensures that the generated
inductor energy is applied to the load. Capacitors are connected in parallel
with the load to filter output ripple and maintain a constant output voltage.It consists of passive components: one static
switchS, diodes, four inductors L,L0,L1,L2, and capacitors C,C0,C1,C2,andC3. Capacitors C2andC3 perform the characteristics to lift the capacitor voltage VC. The directions of all voltages and currents
are defined and shown in Figure 1. We will assume that all the
components are ideal and the capacitors are large enough. We also assume that
the circuits operate in continuous conduction mode. The output voltage and
current are V0 and I0 the input voltage and current are V1 and I1.


### 2.2. Analysis of Topology-I

When switchS is turned ON, its equivalent
circuit is shown in Figure 2. The source  instantaneous current is equal to iL1+iL0+iC2+iL2+iC3+iL.
The load current flows from the addition of two voltages. That is, the
source voltage V1 and the voltage across the capacitor C
during ON period. Also the capacitors C2 and C3 are
charged to the input voltage under switch-ON condition. All the inductor
current rises during switch-ON period. When switch S is turned OFF, source
current is equal to zero. The stored energy in the inductors L1,L2,andL and the capacitors C2 and C3 discharges and charge  the capacitor C
with the direction as shown in Figure 3. Simultaneously, current iL0 flows through the load, which is sustained by the inductor L0.
Currents iL,iL1,andiL2 decrease during
switch-OFF period.Figure 2
Topology-I (switch-ON equivalent circuit).Figure 3
Topology-I (switch-OFF equivalent circuit).In steady state, the average inductor voltages
over a period are zero. Thus(1)VC0=V0.The inductor currentiL increases in the
switch-on period and  decreases in the switch-off period. The corresponding
voltages across LareV1, and −VL‐OFF.Therefore,(2)kTV1=(1−k)TVL‐OFF,VL‐OFF=[k1−k]V1.Similarly,(3)VL1‐OFF=[k1−k]V1,VL2‐OFF=[k1−k]V1.During switch-on period, the voltage
across capacitorC1is equal to the source voltage plus the voltage across C. Since we assume that C and C1 are
sufficiently large, during switch-on period,(4)VC0=V1+VC1.
Therefore, from
switch-off period equivalent circuit,(5)VC=VC‐OFF=VL‐OFF+VL1‐OFF+VL2‐OFF+VC2+VC3,VC=(k1−k)V1+(k1−k)V1+(k1−k)V1+V1+V1,VC=3k1−kV1+2V1,V0=VC+V1,V0=[31−k]V1.The voltage transfer gain of
continuous conduction mode (CCM) is(6)M=V0V1=31−k.The output voltage, current, and the
voltage transfer gain are summarized as follows:(7)V0=[31−k]V1,i0=[1−k3]i1,M=31−k.Average voltages are(8)VC=[2+k1−k]V1,VC1=V0,VC2=VC3=V1.Average currents are(9)iL0=i0,iL1=iL2=iL=[11−k]i0.


### 2.3. Topology-II

Topology-II of theDC‐DC boost converter is
derived from topology-I.
Topology-II is the same as topology-I
circuit with the additional voltage lift components, that is, capacitor and
inductors in addition to that of the topology-I circuit. The output voltage and current of this
converter are smooth. The output voltage
of this converter is four times that of the input source voltage. It consists
of a static switch S, diodes D,D1,D2,D3,D4,D10,D11,D12,andD13, inductors L,L0,L1,L2,andL3 capacitors C,C1,C2,C3,andC4,
and the output capacitor C0. It can be seen that there are one
capacitor C4, one inductor L3, and two diodes D4andD13 added
into the circuit. Capacitors C1,C2,C3,andC4 perform
characteristics to lift the capacitor voltage Vc by four times that of source
voltage VS. The directions of all voltages and currents are
defined and shown in the Figure 4.Figure 4
Topology-II ofDC‐DC boost converter.It is assumed that all the components are ideal
and the capacitors are large enough. It is also assumed that the circuits
operate in continuous conduction mode. The output voltage and current areV0
and I0, while the input voltage and current are VI and I1. Topology-II performs a positive-to-positive DC‐DC step-up
voltage conversion with high efficiency, high power density and cheap topology
in a simple structure.


### 2.4. Analysis of Topology-II

When switchS is turned ON, the equivalent
circuit is shown in Figure 5. The source instantaneous current is equal to iL1+iL0+iC2+iL2+iC3+iL+iC4+iL3.
The load current flows from the addition of two voltages, That is, the source
voltage V1 and the voltage across the capacitor C during switch-ON period. Also
the capacitors C2,C3,andC4 are charged to
the input voltage under switch-ON condition. All the inductor current rises
during switch-ON period. When
switch S turned OFF, source current is equal to zero and equivalent circuit is
shown in Figure 6. The stored energy in the inductors L1,L2,L3,andL and the capacitors C2,C3,andC4 discharges and charges the capacitor C with the direction as
shown in Figure 6. Simultaneously, current iL0 flows through
the load, which is sustained by the inductor L0.
All the inductor currents decrease during the switch-OFF period.Figure 5
Topology-II (switch-ON equivalent circuit).Figure 6
Topology-II (switch-OFF equivalent circuit).Under steady state, the average inductor voltages
over a period are zero. Thus(10)VC0=V0.During switch-on period,(11)VC2=VC3=VC4=V1.Also(12)V0=VC1=VC+V1.The inductor currentIL increases in the switch-on
period and decreases in the switch-off period. The corresponding voltages
across LareV1 and −VL‐OFF.Therefore,(13)kTV1=(1−k)TVL‐OFF,VL‐OFF=[k1−k]V1.Similarly, forL1,L2,andL3,(14)VL1‐OFF=[k1−k]V1,VL2‐OFF=[k1−k]V1,VL3‐OFF=[k1−k]V1.From switch-off period
equivalent circuit,(15)VC=VC‐OFF=VL‐OFF+VL1‐OFF+VL2‐OFF+VL3‐OFF+VC2+VC3+VC4,VC=4k1−kV1+3V1,V0=VC+V1,V0=[4k1−k]V1.The output voltage, current, and voltage transfer
gain are summarized below(16)V0=[41−k]V1,i0=[1−k4]i1,M0=41−k.Average voltages are(17)VC=[3+k1−k]V1,VC1=V0,VC2=VC3=VC4=V1.Average currents are(18)iL0=i0,iL=[k1−k]i0,iL1=iL2=iL3=iL+iL0=[11−k]i0.Table1 illustrates the comparison between the analyzed DC‐DC converters with the classical
boost converter. From the table, it is
clear that the proposed converter topology produces higher output DC voltage.Table 1
Performance comparison of the proposedDC‐DC boost converter with classical boost converter.
DC‐DC convertersOutput voltage (V0)
(volts)Output current (i0)
(amps)Classical boost
converterV0=[k/(1−k)]V1i0=[(1−k)/k]i1Boost converter topology-IV0=[3/(1−k)]V1i0=[(1−k)/3]i1Boost converter topology-IIV0=[4/(1−k)]V1i0=[(1−k)/4]i1


## 2.1. Topology-I

The
proposed topology of new series of boost converter is derived from theDC‐DC
boost
converter circuit. Topology-I
is a boost converter circuit with the voltage lift components, that is, additional three stages of inductor and capacitor along with the basic circuit
are shown in Figure 1. In this topology, the switch S is N-channel power
MOSFET device (NMOS) and it is driven by a pulse-width-modulated (PWM) switching signal with variable frequency f and conduction duty k. For this
circuit, the load is usually resistive, R=V0/I0.Figure 1
Topology-I ofDC‐DC boost converter.The basic principle of this circuit in
boosting up the output voltage is charging and discharging reactive elements into a load,
controlling the levels of charge, and consequently the output voltage by
switching theDC supply in and out of the circuit at very high
frequencies. They include a freewheeling diode to protect the switch from the
inductors high reverse currents, and this also ensures that the generated
inductor energy is applied to the load. Capacitors are connected in parallel
with the load to filter output ripple and maintain a constant output voltage.It consists of passive components: one static
switchS, diodes, four inductors L,L0,L1,L2, and capacitors C,C0,C1,C2,andC3. Capacitors C2andC3 perform the characteristics to lift the capacitor voltage VC. The directions of all voltages and currents
are defined and shown in Figure 1. We will assume that all the
components are ideal and the capacitors are large enough. We also assume that
the circuits operate in continuous conduction mode. The output voltage and
current are V0 and I0 the input voltage and current are V1 and I1.


## 2.2. Analysis of Topology-I

When switchS is turned ON, its equivalent
circuit is shown in Figure 2. The source  instantaneous current is equal to iL1+iL0+iC2+iL2+iC3+iL.
The load current flows from the addition of two voltages. That is, the
source voltage V1 and the voltage across the capacitor C
during ON period. Also the capacitors C2 and C3 are
charged to the input voltage under switch-ON condition. All the inductor
current rises during switch-ON period. When switch S is turned OFF, source
current is equal to zero. The stored energy in the inductors L1,L2,andL and the capacitors C2 and C3 discharges and charge  the capacitor C
with the direction as shown in Figure 3. Simultaneously, current iL0 flows through the load, which is sustained by the inductor L0.
Currents iL,iL1,andiL2 decrease during
switch-OFF period.Figure 2
Topology-I (switch-ON equivalent circuit).Figure 3
Topology-I (switch-OFF equivalent circuit).In steady state, the average inductor voltages
over a period are zero. Thus(1)VC0=V0.The inductor currentiL increases in the
switch-on period and  decreases in the switch-off period. The corresponding
voltages across LareV1, and −VL‐OFF.Therefore,(2)kTV1=(1−k)TVL‐OFF,VL‐OFF=[k1−k]V1.Similarly,(3)VL1‐OFF=[k1−k]V1,VL2‐OFF=[k1−k]V1.During switch-on period, the voltage
across capacitorC1is equal to the source voltage plus the voltage across C. Since we assume that C and C1 are
sufficiently large, during switch-on period,(4)VC0=V1+VC1.
Therefore, from
switch-off period equivalent circuit,(5)VC=VC‐OFF=VL‐OFF+VL1‐OFF+VL2‐OFF+VC2+VC3,VC=(k1−k)V1+(k1−k)V1+(k1−k)V1+V1+V1,VC=3k1−kV1+2V1,V0=VC+V1,V0=[31−k]V1.The voltage transfer gain of
continuous conduction mode (CCM) is(6)M=V0V1=31−k.The output voltage, current, and the
voltage transfer gain are summarized as follows:(7)V0=[31−k]V1,i0=[1−k3]i1,M=31−k.Average voltages are(8)VC=[2+k1−k]V1,VC1=V0,VC2=VC3=V1.Average currents are(9)iL0=i0,iL1=iL2=iL=[11−k]i0.


## 2.3. Topology-II

Topology-II of theDC‐DC boost converter is
derived from topology-I.
Topology-II is the same as topology-I
circuit with the additional voltage lift components, that is, capacitor and
inductors in addition to that of the topology-I circuit. The output voltage and current of this
converter are smooth. The output voltage
of this converter is four times that of the input source voltage. It consists
of a static switch S, diodes D,D1,D2,D3,D4,D10,D11,D12,andD13, inductors L,L0,L1,L2,andL3 capacitors C,C1,C2,C3,andC4,
and the output capacitor C0. It can be seen that there are one
capacitor C4, one inductor L3, and two diodes D4andD13 added
into the circuit. Capacitors C1,C2,C3,andC4 perform
characteristics to lift the capacitor voltage Vc by four times that of source
voltage VS. The directions of all voltages and currents are
defined and shown in the Figure 4.Figure 4
Topology-II ofDC‐DC boost converter.It is assumed that all the components are ideal
and the capacitors are large enough. It is also assumed that the circuits
operate in continuous conduction mode. The output voltage and current areV0
and I0, while the input voltage and current are VI and I1. Topology-II performs a positive-to-positive DC‐DC step-up
voltage conversion with high efficiency, high power density and cheap topology
in a simple structure.


## 2.4. Analysis of Topology-II

When switchS is turned ON, the equivalent
circuit is shown in Figure 5. The source instantaneous current is equal to iL1+iL0+iC2+iL2+iC3+iL+iC4+iL3.
The load current flows from the addition of two voltages, That is, the source
voltage V1 and the voltage across the capacitor C during switch-ON period. Also
the capacitors C2,C3,andC4 are charged to
the input voltage under switch-ON condition. All the inductor current rises
during switch-ON period. When
switch S turned OFF, source current is equal to zero and equivalent circuit is
shown in Figure 6. The stored energy in the inductors L1,L2,L3,andL and the capacitors C2,C3,andC4 discharges and charges the capacitor C with the direction as
shown in Figure 6. Simultaneously, current iL0 flows through
the load, which is sustained by the inductor L0.
All the inductor currents decrease during the switch-OFF period.Figure 5
Topology-II (switch-ON equivalent circuit).Figure 6
Topology-II (switch-OFF equivalent circuit).Under steady state, the average inductor voltages
over a period are zero. Thus(10)VC0=V0.During switch-on period,(11)VC2=VC3=VC4=V1.Also(12)V0=VC1=VC+V1.The inductor currentIL increases in the switch-on
period and decreases in the switch-off period. The corresponding voltages
across LareV1 and −VL‐OFF.Therefore,(13)kTV1=(1−k)TVL‐OFF,VL‐OFF=[k1−k]V1.Similarly, forL1,L2,andL3,(14)VL1‐OFF=[k1−k]V1,VL2‐OFF=[k1−k]V1,VL3‐OFF=[k1−k]V1.From switch-off period
equivalent circuit,(15)VC=VC‐OFF=VL‐OFF+VL1‐OFF+VL2‐OFF+VL3‐OFF+VC2+VC3+VC4,VC=4k1−kV1+3V1,V0=VC+V1,V0=[4k1−k]V1.The output voltage, current, and voltage transfer
gain are summarized below(16)V0=[41−k]V1,i0=[1−k4]i1,M0=41−k.Average voltages are(17)VC=[3+k1−k]V1,VC1=V0,VC2=VC3=VC4=V1.Average currents are(18)iL0=i0,iL=[k1−k]i0,iL1=iL2=iL3=iL+iL0=[11−k]i0.Table1 illustrates the comparison between the analyzed DC‐DC converters with the classical
boost converter. From the table, it is
clear that the proposed converter topology produces higher output DC voltage.Table 1
Performance comparison of the proposedDC‐DC boost converter with classical boost converter.
DC‐DC convertersOutput voltage (V0)
(volts)Output current (i0)
(amps)Classical boost
converterV0=[k/(1−k)]V1i0=[(1−k)/k]i1Boost converter topology-IV0=[3/(1−k)]V1i0=[(1−k)/3]i1Boost converter topology-IIV0=[4/(1−k)]V1i0=[(1−k)/4]i1


## 3. Closed-Loop Controller for Proposed Boost Converter

Closed-loop control scheme for the proposedDC‐DC boost converter topology is shown in Figures 7 and 8.
The control scheme essentially consists of only one voltage sensor with simple control structure when compared with classical DC‐DC boost converter
which requires both voltage and current sensors. DC voltage of the load is fed
back and compared with Vdc reference voltage and the error is given
to the PI controller to stabilize the error and the signal obtained from the
controller is the modulating signal for the PWM scheme. Signal from the PI
controller is compared with high frequency ramp signal to produce required
pulse for the N-channel MOSFET switch to obtain the reference DC voltage at the
load. In this paper, for
the above model of the converter [12, 13] using the Ziegler-Nichols method 1
is (S-shaped curve technique) applied to design the PI controller.Figure 7
Closed-loop controller for topology-IDC‐DC boost converter.Figure 8
Closed-loop
controller for topology-II DC-DC boost converter.Step input is applied to the plant model and
the response is theS shaped curve. By drawing the tangent to the S-shaped
curve at its inflection point with reference to X-axis, the time delay L and
time constant T are
calculated. Using [12] Ziegler-Nichols chart, the value of the Kp and
Ti is calculated.
The PI controller designed by the above method is tested under different
disturbance conditions and results are provided for the feasibility. Closed
control schemes for both
topologies are the same and tuning parameters Kp and Ki are different.


## 4. Simulation Results

Simulation results
of the proposedDC‐DC boost converter topologies with simplified controller
scheme are presented and discussed further. Design of inductance and capacitance
is based on 5% ripple at the output [14] and the values are the same for both load
and lift part of the circuit.Simulation
parameters taken for analysis areInput voltageV1 = 10 volts,Inductance = 100μH,Capacitance = 5μF,Load resistance = 44 ohms,Duty ratiok = 0.6666,Switching frequency = 50 KHz.PI controller
transfer function:(19)Topology‐I:G(s)=0.065684(S+5500.2)S,Topology‐II:G(s)=0.065011(S+9000)S.Figure9 depicts the output voltage of the
converter at rated condition, maintaining 90 volts at 44 ohms load resistance, and
the corresponding output current of 2.045 amperes is shown in Figure 10. Figure
11 shows the line voltage variation applied to topology-I, initially 10 volts is
maintained and introduced a change to 9 volts at 0.03 second, for analyzing the
line disturbance performance. Figure 12 shows the load resistance variation
applied to topology-I, initially 48 ohms are maintained and introduced a change
to 44 ohms at 0.05 second, for analyzing the load disturbance performance. Figure
13 illustrates the output voltage for topology-I under both line and load
disturbances, the output voltage stabilized in 0.005 second for both distortion
conditions by the closed-loop controller. Figure 14 illustrates the output
current for topology-I under line and load disturbances, as load resistance
decreases from 48 ohms to 44 ohms at 0.05 second the load current increases
from 1.875 amperes to 2.045 amperes.Figure 9
Output voltage at rated condition for topology-I.Figure 10
Output current at rated condition for topology-I.Figure 11
Line disturbance at 0.03 second for the topology-I.Figure 12
Load disturbance at 0.06 second for the topology-I.Figure 13
Output voltage of the topology-I
for line and load disturbances.Figure 14
Output current of the topology-I under line and load disturbances.Figure15 depicts the output voltage of the
converter at rated condition, maintaining 120 volts at 44 ohms load resistance and
the corresponding output current of 2.7272 amperes is shown in Figure 16. Figure
17 shows the line voltage variation applied to topology-I, initially 10 volts are maintained and
introduced a change to 9 volts at 0.02 second, for analyzing the line
disturbance performance. Figure 18 shows the load resistance variation applied
to topology-I, initially 48 ohms are maintained and introduced a change to 44 ohms
at 0.04 second, for analyzing the load disturbance performance. Figure 19 illustrates
the output voltage for topology-I under both line and load disturbances, the
output voltage stabilized in 0.005 second for both distortion conditions by the
closed-loop controller. Figure 20 illustrates the output current for topology-I
under line and load disturbances, as load resistance decreases from 48 ohms to
44 ohms at 0.05 second the load current increases from 2.5 amperes to 2.7272 amperes.Figure 15
Output voltage at rated condition for topology-II.Figure 16
Output current at rated condition for topology-II.Figure 17
Line disturbance at 0.02 second for topology-II.Figure 18
Load disturbance at 0.04 second for topology-II.Figure 19
Output voltage of the topology-II
for line and load disturbances.Figure 20
Output current of topology-II
under line and load disturbances.


## 5. Effectiveness of the Proposed Converter

The effectiveness of the proposed converter
topologies is shown in Table2 by comparing  the simulation results with classical
boost converter. It is seen from Table 2 that the output voltage varies from
33.33 volts to 300 volts for topology-I and 44.44 volts to 400 volts for
topology-II, respectively, for a duty ratio of 0.1 to 0.9. However, the
classical converter produces only a maximum of 90 volts. This shows that the proposed
converter provides higher output voltage.Table 2
Comparison of simulation result of
the proposed converters with classical converter at steady state condition for
rated load.
Duty ratio (k)Output voltage (V0) classical
converterOutput voltage (V0) proposed topology-IOutput voltage (V0) proposed topology-II0.11.1133.3344.440.22.537.5500.34.2842.8557.140.46.665066.660.51060800.615751000.723.33100133.330.8401502000.990300400


## 6. Conclusions

A new series ofDC‐DC boost
converter topologies are proposed. The topologies use voltage lift technique to obtain higher output voltage than the classical boost converter for the same
duty ratio. The technique also overcomes
the effect of parasitic elements and minimizes the ripple in the output voltage. A simplified controller with
one sensor is designed to maintain the output voltage at the required level for
the load and line disturbances.
Simulation results validate the theoretical analysis. The proposed converter topologies find
application in computer peripheral circuits, medical equipments, and industrial
applications which require higher DC  voltages.



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*Source: 593042-2009-01-21.xml*