# An Enhanced Space Vector PWM Strategies for Three Phase Asymmetric Multilevel Inverter

Authors: B. Hemanth Kumar; K. Janardhan; R. Seshu Kumar; J. Ramesh Rahul; Arvind R. Singh; Raj Naidoo; Ramesh C. Bansal
Journal: International Transactions on Electrical Energy Systems
 (2023)

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## Abstract

This work presents the two space vector pulse width modulation (SVPWM-I and SVPWM-II) strategies for eleven-level (11L) asymmetric cascaded H-bridge (CHB) multilevel inverter (MLI). Depending on the isolated structure and nonappearance of capacitor voltage balancing issues, the CHB MLI structure is favoured. These days, the SVPWM control method is accomplished superior consideration among the diverse PWM methods. In common, the SVPWM strategy is realized based on deteriorating higher-level hexagons into a lower level hexagon (2-level). Compared to the classical SVPWM strategy, the proposed SVPWM-I strategy decreases the memory and mathematical burden necessity included within the demonstration of eleven-level SVPWM devoid of losing the inverter output voltage (AC) contour by diminution the number of two-level hexagons. Also, the SVPWM-II strategy is presented, which incredibly diminishes the mathematical endeavours. The presented two SVPWM methods performed on an eleven-level asymmetric CHB multilevel inverter (MLI) by utilizing SIMULINK/MATLAB program tool and are compared with conventional sinusoidal PWM and Third harmonic injection (THI) PWM methods to confirm the proposed SVPWM methods. The proposed SVPWM methods give higher AC RMS voltage and lower harmonic distortion when compared to SPWM and THIPWM methods. To validate the presented two SVPWM control schemes, hardware results are taken on asymmetric eleven-level CHB MLI.


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## Body

## 1. Introduction

In a basic two-level inverter, a lower harmonic in output voltage is obtained by rising the switching frequency, which leads to higher voltage stresses and switching losses upon that switches are the result of a reduction in the step count in the output voltage. The disadvantages in two-level inverter motivate the intrigued on the multilevel inverters (MLIs). In 1991, MLI was presented and its development is quick over a long time [1].MLIs find widespread use across a variety of sectors today, particularly for high-power and medium-voltage applications [2, 3]. MLIs make use of a greater amount of DC sources and switches to generate a staircase waveform that is more similar to a sinusoidal signal and has a lower level of harmonic distortion [4]. MLIs provide several advantages over classical two-level inverters, including a higher basic output voltage, a lower common mode voltage and switching loss, a reduction in EMI, and a reduction in THD [5]. As a result of these benefits, MLIs may be utilized in a diverse collection of contexts, such as in HVDC, FACTS, electric cars, and solar power systems [6–8]. The CHB inverter, which was discovered by Peng and Lai [9] the flying capacitor (FC) inverter, which was discovered by Meynard and Foch [10] and the neutral point clamped (NPC) inverter, which was discovered by Nabae et al. [11] are the three established MLI topologies that are used the most frequently. The only difference between NPC and FC topologies is that NPC uses diodes in a ladder configuration while FC uses capacitors in a ladder configuration. To produce higher inverter levels, NPC, and FC both need a greater number of power components, and they both struggle with voltage imbalance [12, 13]. H-bridge cells are connected in series in the CHB topology, and the modular topology is created by the requirement that each cell has its own DC source. Both three-phase and single-phase power conversion can benefit from this CHB topology. CHB MLIs are one of the three fundamental MLI topologies and are ideal for PV applications [14, 15]. In this work, CHB inverter topology is considered and is operated in an asymmetric mode to realize an eleven-level inverter. Figure 1 depicts the three-phase asymmetric CHB 11L inverter. Table 1 depicts the switching logic of an asymmetric CHB eleven-level inverter.Figure 1
Three phase asymmetric 11L CHB inverter configuration.Table 1
Switching states of eleven-level CHB inverter.
Voltage levelS1S2S3S4S5S6S7S8S9S10S11S12+5E110011001100+4E101011001100+3E110011001010+2E101010101100+E1100101010100101010101010−E0′10110101010−2E10100′1011010−3E0′1010′1011010−4E10100′1010′101−5E0′1010′1010′101The SVPWM [16] and the level-shifted multicarrier SPWM [17] are the two inverter modulation methods that are used the most often for MLIs. To identify the switching states of an MLI in SPWM, a sinusoidal signal of the appropriate phase is compared to a high-frequency triangular carrier waveform. To create gate pulses in an 11-L inverter, ten carrier waveforms are compared with a single modulating signal. If a sinusoidal signal with a frequency three times that of the modulating signal is added to the modulating signal in the SPWM method, it is referred to as a third harmonic injection (THI) PWM. The THI signal’s magnitude is determined by the modulating signal’s amplitude. If k is the amplitude of the modulating signal, then k/4 or k/6 is the magnitude of the common mode signal for better results. The magnitude of the reference signal (k) is changed to 1.154k in THIPWM to achieve high DC bus usage. Both SPWM and THIPWM schemes lack redundancy switching states, which are particularly helpful for a variety of applications [17].The SVPWM approach, on the other hand, provides greater DC source utilization, reduced THD, and common mode voltage (CMV) [18–20]. In addition, it enables the balancing of capacitor voltage concerns through the assistance of a redundant switching state [21]. And also, the reliability of the MLIs can be improved with the use of redundancy switching states in the SVPWM technique [22]. SPWM technique is also simpler to implement for various applications [23]. SVPWM implementation via digital means is simpler. SVPWM is therefore the preferred PWM method for industrial applications [24, 25]. Finding the sector in which the reference voltage (Vref) is located is the first step in implementing the SVPWM [26], which is then followed by choosing a triangle within that sector based on the location of Vref, computing dwell times and choosing the best switching times to generate gate signals for power switches in an MLI. SVPWM implementation for an MLI is challenging for the reason that complexity rises as inverter levels rise [27].Article [28] presents an SVPWM method for a 3L (level) inverter in which they split the 3L hexagon into six 2L hexagons. To implement 3L SVM similarly to the 2L SVM approach, the center of the 3L hexagon is moved to the corresponding 2L hexagon. Euclidean vector approach is used in [29] to implement generalised SVM for an N-level inverter. According to [30], a fractal concept related SVPWM approach for MLI involves knowing the triangle where the Vref tip lies using a triangularization procedure. In [31], the initial 5L space vector diagram (SVD) was broken up into six 3L hexagons, and then each of those was split into six 2L hexagons prior to the standard procedure was used to acquire SVPWM for five-level inverters.In [32], the 7L SVPWM was first disintegrated into six 4L hexagons, and the 4L hexagon was then divided into 2L hexagons. The usual conventional process was then used to realise the seven-level SVPWM. In [33], the nine-level SVPWM was first disintegrated into six 5L hexagons, and the 5L hexagon was then divided into 2L hexagons. Then, the conventional process was then used to realise the nine-level SVPWM. MLI output phase voltage levels range from + P5 (equivalent + ve peak level) to −N5 (equivalent -ve peak level) as shown in Figure 2, according to the SVD for eleven-level inverters. The switching instants for an N-level inverter is typically N3. 3N2 − 3N + 1 are independent switching possibilities out of N3, and the left behind switching instants are redundant switching possibilities. It consists of (N − 1)3 triangles and (N − 1) layers in N-level SVD. As a result, an inverter has 113 = 1331 switching instants available for 11-level inverters. There are 331 independent switching instants and 1000 redundant switching instants out of the total 1331 switching instants. The space vector diagram contains 1000 triangles and has 10 layers.Figure 2
11L SVD with reference vector mapping and its disintegration to 6L SVDs.In this work, presents the two SVPWM techniques, namely, SVPWM-I and SVPWM-II strategies for eleven-level asymmetric cascaded H-bridge MLI. Without sacrificing the AC voltage profile at the MLI output, the proposed two SVPWM technique drastically lessens the computational load associated with the SVPWM for an 11-level inverter. Reduced from 1331 to 222 counts, the number of 2L hexagons needed for an eleven-level inverter. It is also shown in the SVPWM-II technique, which significantly reduces computation time by switching from 222 to 1862-level hexagons. The proposed SVPWM methods that have been proposed are tested on an eleven-level inverter and evaluated against the widely used SPWM and THIPWM techniques. The proposed SVPWM schemes have undergone an experimental setup for validation.


## 2. Proposed SVPWM-I Technique

The lower level SVD is disintegrated into 2L hexagons as part of the SVPWM-I technique. Figure2 displays the 11L SVD. As shown in Figure 2, the 11L SVD is first divided into six 6L hexagons. Hexagon-I is the first six-level hexagon, and its midpoint is by the side of the 0°axis. The midpoint of every subsequent 6L hexagon is then 60°off. To prevent overlap between adjacent hexagons, the appropriate hexagon is chosen by considering the Vref angle’s value. Depending on the angle of the Vref, Table 2 displays the selection of 6L hexagons from 11L SVD.Table 2
Selection of 6L hexagons from 11L SVD.
Hexagon NoRange ofθI330° to 30°II30° to 90°III90° to 150°IV150° to 210°V210° to 270°VI270° to 330°Once a six-level hexagon is chosen, a new reference vector,Vref6, that originates from the centre of the chosen six-level hexagon is needed to align the vector tips of Vref and Vref6. Take as an illustration that the tip of Vref is located in Hexagon-I shown in Figure 2. Here, as shown in Figure 2, the reference signal Vref and the mapped reference vector Vref6 from Hexagon-I are coincident with their tips. Precisely, the imaginary(β-axis)and real (α-axis) components of mapped vector Vref can be derived from Vref as follows:(1)V6α=V11α−5E,V6β=V11β.Here, the components ofVref6 and Vref along the α-axis and β-axis, correspondingly, are V6α and V6β, and V11α and V11β. The reference vector (Vref) mapping to other six-level hexagons can be examined similarly, as shown in Table 3. By calculating the Vref6 vector, the 11L SVPWM problem is reduced to a 6L SVPWM problem.Table 3
Mapping ofVref6 from Vref11.
Hexagon NoV6αV6βIV11α − 5EV11βIIV11α − 5Ecos (π/3)V11β − 5Esin (π/3)IIIV11α − 5Ecos (2π/3)V11β − 5Esin (2π/3)IVV11α + 5EV11βVV11α − 5Ecos (4π/3)V11β − 5Esin (4π/3)VIV11α − 5Ecos (5π/3)V11β − 5Esin (5π/3)The 6L is then disintegrated into 2L hexagons as the next step. Figure3 illustrates how a 6L hexagon can be reduced to a two-level one by having an inner 4L hexagon with thirteen 2L hexagons and an outer one with 24 two-level hexagons. Thus, there are thirty-seven 2L hexagons in total for each 6L hexagon. Depending on the angle and magnitude of Vref6, outer and inner 2L hexagons are chosen. Assume that outer 2L hexagons are chosen if the magnitude value of the vector Vref6 is greater than magnitude 3E, and inner 2L hexagons are chosen if the magnitude value of the vector Vref6 falls below the value of 3E. The 6L SVD is then disintegrated into 2L hexagons as the next step. Table 4 displays the selection of the outer twenty-four 2L hexagons in a 6L SVD.Figure 3
Disintegration of 6L SVD to lower-level hexagons.Table 4
Selection of outer 2L hexagons from 6L SVD and mapping ofVref2O from Vref6.
Hexagon NoRange ofθV2αoV2βoOH1348° to 12°V6α−4EV6βOH212° to 24°V6α − 3.6Ecos (π/12)V6β − 3.6Esin (π/12)OH324° to 36°V6α − 3.46Ecos (2π/12)V6β − 3.46Esin (2π/12)OH436° to 48°V6α − 3.6Ecos (3π/12)V6β − 3.6Esin (3π/12)OH548° to 72°V6α − 4Ecos (4π/12)V6β − 4Esin (4π/12)OH672° to 84°V6α − 3.6Ecos (5π/12)V6β − 3.6Esin (5π/12)OH784° to 96°V6α − 3.46Ecos (6π/12)V6β − 3.46Esin (6π/12)OH896° to 108°V6α − 3.6Ecos (7π/12)V6β − 3.6Esin (7π/12)OH9108° to 132°V6α − 4Ecos (8π/12)V6β − 4Esin (8π/12)OH10132° to 144°V6α − 3.6Ecos (9π/12)V6β − 3.6Esin (9π/12)OH11144° to 156°V6α − 3.46Ecos (10π/12)V6β − 3.46Esin (10π/12)OH12156° to 168°V6α − 3.6Ecos (11π/12)V6β − 3.6Esin (11π/12)OH13168° to 192°V6α + 4EV6βOH14192° to 204°V6α − 3.6Ecos (13π/3)V6β − 3.6Esin (13π/12)OH15204° to 216°V6α − 3.46Ecos (14π/12)V6α − 3.46Esin (14π/12)OH16216° to 228°V6α − 3.6Ecos (15π/12)V6β − 3.6Esin (15π/12)OH17228° to 252°V6α − 4Ecos (16π/12)V6β − 4Esin (16π/12)OH18252° to 264°V6α − 3.6Ecos (17π/12)V6β − 3.6Esin (17π/12)OH19264° to 278°V6α − 3.46Ecos (18π/12)V6β − 3.46Esin (18π/12)OH20278° to 290°V6α − 3.6Ecos (19π/12)V6β − 3.6Esin (19π/12)OH21290° to 314°V6α − 4Ecos (20π/12)V6β − 4Esin (20π/12)OH22314° to 326°V6α − 3.6Ecos (21π/12)V6β − 3.6Esin (21π/12)OH23326° to 337°V6α − 3.46Ecos (22π/12)V6β − 3.46Esin (22π/12)OH24337° to 348°V6α − 3.6Ecos (23π/12)V6β − 3.6Esin (23π/12)A new reference vector, let us call itVref2O, that comes from the centre of the chosen outer 2L hexagons is needed if any outer 2L hexagons is chosen. Here, the Vref6 and Vref2O tips are in sync. Take the tip of Vref as an example; it is located in the outer 2L hexagon-3 (i.e., OH3) in Figure 4. The following diagram shows how to calculate the vector Vref2O mathematically from Vref6.(2)V2αO=v6α−3.46Ecosπ6,V2βO=v6αβ−3.46Ecosπ6.Figure 4
Mapping of Vref6 in outer 2L hexagon.Here, the components ofVref6 and Vref2 along the α-axis and β- axis, correspondingly, are V6α and V6β, and V2αO and V2βO, respectively. Consecutively, the mapping of Vref6 to the remaining twenty-three outer 2L hexagons in a 6L SVD can be analysed similarly, as given in Table 4. The 6L hexagon-I is depicted in Figure 5 along with all potential switching instants. Figure 5 illustrates how the number of space vector redundancies rises beginning from the outer layer to the centre. The eleven-level SVD’s centre has the most space vectors, ten of which are redundant.Figure 5
Switching states of 6L hexagon-I.A new reference vector, let us call itVref2i, that comes from the centre of the chosen inner 2L hexagons is needed if inner four-level hexagons, which are a grouping of thirteen 2L hexagons, are chosen. Here, the Vref6 and Vref2i tips are identical is shown in Figure 6. Table 5 illustrates how a four-level hexagon’s inner 2L hexagons are chosen depending on the magnitude of Vref6. Consider the tip of Vref6 as an example, which is located in the inner 2L hexagon-1 in Figure 6. The following diagram shows how to calculate the vector Vref2i mathematically from Vref6.(3)V2αi=V6α−2E,V2βi=V6β.Figure 6
Disintegration of 4L SVD to 2L hexagons.Table 5
Selection of 2L hexagons from 4L SVD and mapping ofVref2 from Vref4.
Hexagon NoMagnitude ofVref4Range ofθV2αiV2βiIH≤E———OH1>E340° to 20°V4α − 2EV4βOH220° to 40°V4α − 1.73E cos (π/6)V4β − 1.73E sin (π/6)OH340° to 80°V4α − 2E cos (2π/6)V4β − 2E sin (2π/6)OH480° to 100°V4αV4β − 1.73 EOH5100° to 140°V4α − 2E cos (4π/6)V4β − 2E sin (4π/6)OH6140° to 160°V4α − 1.73Ecos (5π/6)V4β − 1.73Esin (5π/6)OH7160° to 200°V4α + 2EV4βOH8200° to 220°V4α − 1.73Ecos (7π/6)V4β − 1.73E sin (7π/6)OH9220° to 260°V4α − 2Ecos (8π/6)V4β − 2E sin (8π/6)OH10260° to 280°V4α − 1.73Ecos (9π/6)V4β − 1.73Esin (9π/6)OH11280° to 320°V4α − 2Ecos (10π/6)V4β − 2E sin (10π/6)OH12320° to 340°V4α − 1.73Ecos (11π/6)V4β − 1.73E sin (11π/6)Here, the components ofVref6 and Vref2i along the α-axis and β- axis, correspondingly, are V6α and V6β, and V2α and V2β, respectively. Consecutively in a 4-level SVD of a six-level SVD, Vref6 mapping to the other 13 inner two-level hexagons can be analysed similarly is shown in Table 5. Thus, by locating the Vref2 vector, the 11L SVM problem is reduced to a 2LSVM.


### 2.1. Calculation of Switching Sequence and Dwell times

The switching times and dwell times are derived in a manner akin to the classical 2L hexagon. Every one of the six sectors in a two-level hexagon can be realised with a reference vector (Vref) using one of the three switching states that are available. Based on the volt-sec-balancing method, the time spent in each switching state is determined. Consider the mapped reference vector Vref2O, which is depicted in Figure 7 as being located in the outermost 2L hexagon (OH3) of the 6L hexagon-I.Figure 7
Outer 2L hexagon-3 with switching states.Figure7 shows P5N3N5 as the active switching state (V1), P5N2N5 as the active switching state (V2), and P5N2N4 or P4N3N5 as the zero switching states (V0). For switching between states V1, V2, and V0, the dwell times are T1, T2, and T0, correspondingly.The terms to derive the dwell times meant forV1, V2, and V0 are as follows:(4)T1=TsxMxsin60−θ,T2=TsxMxsin60,T0=Ts−T1−T2.HereM stands for modulation index, and it is given as follows:(5)M=3VrefE.Here,M value ranges from 0 to unity. Designing the switching time sequence using a single zero switching state and 2 active switching states is another crucial step. This technique switches between seven segments. When changing from one switching instant to another instant, there should be no more than individual leg change in the switching sequence.The seven instants of segment switching through switching times sector-I is chosen if theVref2O vector is present.(6)P4N3N5∗T04,P5N3N5∗T12,P5N2N5∗T22,P5N2N4∗T02,P5N3N5∗T12,P5N2N5∗T22,P3N4N4∗T04.Furthermore, if theVref2 vector lies within, sector-IV is chosen as(7)P4N3N5∗T04,P4N3N4∗T12,P4N2N4∗T22,P4N3N5∗T02,P4N3N4∗T12,P4N2N4∗T22,P4N3N5∗T04.


## 2.1. Calculation of Switching Sequence and Dwell times

The switching times and dwell times are derived in a manner akin to the classical 2L hexagon. Every one of the six sectors in a two-level hexagon can be realised with a reference vector (Vref) using one of the three switching states that are available. Based on the volt-sec-balancing method, the time spent in each switching state is determined. Consider the mapped reference vector Vref2O, which is depicted in Figure 7 as being located in the outermost 2L hexagon (OH3) of the 6L hexagon-I.Figure 7
Outer 2L hexagon-3 with switching states.Figure7 shows P5N3N5 as the active switching state (V1), P5N2N5 as the active switching state (V2), and P5N2N4 or P4N3N5 as the zero switching states (V0). For switching between states V1, V2, and V0, the dwell times are T1, T2, and T0, correspondingly.The terms to derive the dwell times meant forV1, V2, and V0 are as follows:(4)T1=TsxMxsin60−θ,T2=TsxMxsin60,T0=Ts−T1−T2.HereM stands for modulation index, and it is given as follows:(5)M=3VrefE.Here,M value ranges from 0 to unity. Designing the switching time sequence using a single zero switching state and 2 active switching states is another crucial step. This technique switches between seven segments. When changing from one switching instant to another instant, there should be no more than individual leg change in the switching sequence.The seven instants of segment switching through switching times sector-I is chosen if theVref2O vector is present.(6)P4N3N5∗T04,P5N3N5∗T12,P5N2N5∗T22,P5N2N4∗T02,P5N3N5∗T12,P5N2N5∗T22,P3N4N4∗T04.Furthermore, if theVref2 vector lies within, sector-IV is chosen as(7)P4N3N5∗T04,P4N3N4∗T12,P4N2N4∗T22,P4N3N5∗T02,P4N3N4∗T12,P4N2N4∗T22,P4N3N5∗T04.


## 3. Proposed SVPWM-II Technique

For the SVPWMM of a nine-level inverter, the SVPWM-II scheme is also suggested. The number of 2L hexagons required to realise the eleven-level SVD is once again reduced by this scheme. As in the SVPWM-II technique, the 9L SVD is first resolved into six 4L hexagons in this scheme, and each of those is then divided into thirty-one 2L hexagons. As a result, for eleven-level SVM, the number of 2L hexagons to be considered drops from 222 to 186. The largest circle that is encircled by a hexagon has a radius that corresponds to the value ofM is 1.0. Figure 8 displays the 6L SVD with a circle. Only 18 of the outer hexagons in the eleven-level SVD’s darkly shaded region are excluded, even for the unity modulation index (M).Figure 8
6L SVD with inscribed circle at 1.0M.As a result, for the SVM of an eleven-level inverter, the number of 2L hexagons considered is diminished to 186. Consider selecting the adjacent outer hexagon depends onVref2O and angle θ2 if the Vref vector is in the dark-shaded area. According to the value of Vref6 and angle θ6, the outer eighteen 2L hexagons of a 6L SVD are chosen as shown in Table 6, and the inner 2L hexagons are chosen using the same criteria as in the SVPWM-I method (Table 5). When the M value is greater than 0.91, the THD is slightly increased, which results in a reduction in complexity compared to the SVPWM-I scheme. Both SVPWM-I and SVPWM-II produce the same results if the value of M is less than or equal to 0.92.Table 6
Selection of 2L hexagons from 6L SVD.
Hexagon NoRange ofθOH20° to 24°OH324° to 36°OH436° to 60°OH660° to 84°OH784° to 96°OH896° to 120°OH10120° to 144°OH11144° to 156°OH12156° to 180°OH14180° to 204°OH15204° to 216°OH16216° to 240°OH18240° to 264°OH19264° to 276°OH20276° to 300°OH22300° to 324°OH23324° to 336°OH24336° to 360°


## 4. Simulation Results

Using the MATLAB/SIMULINK software tool, the SVPWM-I and SVPWM-II schemes are both applied to an 11L asymmetric CHB MLI. The three-phase CHB MLI is associated to a three-phase RL-load that is star connected. The inverter neutral and load neutral are not isolated to each other. With the SPWM and THIPWM techniques, simulation results for the presented two SVPWM schemes are validated. IPD multicarrier scheme is employed in the SPWM method. In the SPWM technique, the carrier frequency is 2.5 KHz. Table7 displays the simulation’s input parameters.Table 7
Simulation parameters.
ParameterValueOutput frequency50 HzDC source (E)100 VInductive load110 mH/phResistive load100Ω/phSampling time (TS)2100 sFigure9 displays the output phase voltage of an 11L inverter for various control schemes (SPWM, THIPWM, SVPWM-I, and SVPWM-II) when the dynamic variation of M is from 0.2 to 1.0. Figure 10 displays the eleven-level inverter AC line voltage waveform for various modulation indices ranging from 0.2 to unity.Figure 9
11L CHB inverter phase output voltage for dynamic values of M. (a) SPWM. (b) THIPWM. (c) SVPWM-I. (d) SVPWM-II.
(a)(b)(c)(d)Figure 10
11L CHB inverter line voltage for dynamic values ofM. (a) SPWM. (b) THIPWM. (c) SVPWM-I. (d) SVPWM-II.
(a)(b)(c)(d)Table8 displays the line voltage THD for various values of M and modulation techniques. The RMS voltage for various modulation strategies at various values of M is shown in Table 9. Figure 11 depicts the 11L inverter load current waveforms at dynamic value of M for various modulation techniques by using SPWM, THIPWM, SVPWM-I, and SVPWM-II schemes. The load voltage along with the load current for 1.0 as M value is shown in Figure 12 by using the SVPWM-I technique. The three-phase line voltage of an 11L inverter for various control schemes (SPWM, THIPWM, SVPWM-I, and SVPWM-II) when the dynamic variation of M from 0.2 to 1.0 is shown in Figure 13. The load voltage waveform for the dynamic variation of M from 0.2 to 1.0 is shown in Figure 14 by using SVPWM-I and SVPWM-II techniques. The microscopic view of the 11L inverter line voltage waveform for 1.0 as M value by using SVPWM-I and SVPWM-II is shown in Figure 15. From Figure 15, it is clear that the line voltage waveform has 21 levels. Table 10 shows the 11L inverter line output voltage levels for different modulation indices. The THD is calculated in MATLAB by considering the harmonic order of infinity; i.e., all the frequency components are considered in FFT analysis. The line voltage FFT at M value of 1.0 by using SVPWM-I and SVPWM-II is shown in Figure 16. Similarly, the load current harmonic spectra at M = 1.0 by using SVPWM-I and SVPWM-II is shown in Figure 17. The line voltage FFT and load current FFT at M value of 0.9 by using SVPWM-I are shown in Figure 18. The two SVPWM techniques that have been suggested perform well at various modulation indices and are comparable to traditional SPWM and THIPWM schemes. Switching losses are computed for various modulation schemes by adding IGBT parameters from the datasheet [34] into the IGBT thermal model. At M = 1.0, Table 11 displays the switching losses for SPWM, MSVPWM, and FMSVPWM approaches. Because the switching sequence pattern is built in such a manner that there is only one leg change from one switching instant to the next, the switching frequency is reduced, which results in a decrease in switching losses. Table 11 shows that the suggested SVPWM strategies yield smaller switching losses than the SPWM method.Table 8
Line voltage THD at various values ofM.
M valueLine voltage THD (%)SPWMTHIPWMSVPWM-ISVPWM-II1.06.756.696.066.120.97.888.066.176.170.88.238.826.786.780.610.49.218.658.650.417.412.6912.4812.480.233.2227.1425.5525.55Table 9
AC line voltage value at various values ofM.
M valueAC line voltage (V)SPWMTHIPWMSVPWM-ISVPWM-II1.0305.4334.3353.1343.20.9274.7315.4317.8317.80.8245283.7284.8284.80.6183.2212.4212.5212.50.4121.9141142.6142.60.262.0270.1771.5271.52Figure 11
11L CHB inverter load current for dynamic values ofM. (a) SPWM. (b) THIPWM. (c) SVPWM-I. (d) SVPWM-II.
(a)(b)(c)(d)Figure 12
11L CHB inverter load voltage and current atM = 1.0. (a) SPWM. (b) THIPWM. (c) SVPWM-I.
(a)(b)(c)Figure 13
11L CHB inverter three phase line voltage for dynamic values ofM. (a) SPWM. (b) THIPWM. (c) SVPWM-I. (d) SVPWM-II.
(a)(b)(c)(d)Figure 14
11L CHB inverter load voltage for dynamic values ofM. (a) SVPWM-I. (b) SVPWM-II.
(a)(b)Figure 15
Microscopic view of line voltage atM = 1.0. (a) SVPWM-I. (b) SVPWM-II.
(a)(b)Table 10
Line output voltage levels for different modulation indices.
Modulation indexLine output voltage levels0.130.250.370.490.5110.6130.7150.8170.9191.021Figure 16
FFT spectra of line voltage atM = 1.0. (a) SVPWM-I. (b) SVPWM-II.
(a)(b)Figure 17
FFT spectra of load current atM = 1.0. (a) SVPWM-I. (b) SVPWM-II.
(a)(b)Figure 18
FFT spectra atM = 0.9 by using SVPWM-I technique. (a) Line Voltage. (b) Load Current.
(a)(b)Table 11
Switching losses for three different modulation schemes.
Modulation schemeSwitching losses (W)SPWM8.57SVPWM-I6.89SVPWM-II7.56


## 5. Hardware Results

Figure19 depicts the practical setup for a 3 − θ, eleven-level CHB MLI to verify the suggested two SVPWM schemes. The same simulation’s parameters were taken out for analysis. Texas DSP processor is used to implement the suggested SVPWM techniques.Figure 19
Hardware prototype.Figures20(a) and 20(b) respectively show the eleven-level output phase voltage at different modulation indices (0.2, 0.4, 0.6, 0.8, and 1.0) by using the SVPWM-I and SVPWM-II technique, respectively. The eleven-level output line voltage by different M values using the SVPWM-I and SVPWM-II technique is shown in Figures 21(a) and 21(b) correspondingly. Figures 22(a) and 22(b) show the load current waveforms at dynamic modulation indices by using the SVPWM-I and SVPWM-II techniques correspondingly. Similarly, the load voltage waveforms at dynamic modulation indices by using the SVPWM-I and SVPWM-II techniques are shown in Figures 23(a) and 23(b) correspondingly.Figure 20
Experimental 11L CHB inverter phase voltage for dynamic values ofM. (a) SVPWM-I. (b) SVPWM-II.
(a)(b)Figure 21
Experimental 11L CHB inverter line voltage for dynamic values ofM. (a) SVPWM-I. (b) SVPWM-II.
(a)(b)Figure 22
Experimental 11L CHB inverter load current for dynamic values ofM. (a) SVPWM-I. (b) SVPWM-II.
(a)(b)Figure 23
Experimental 11L CHB inverter load voltage for dynamic values ofM. (a) SVPWM-I. (b) SVPWM-II.
(a)(b)Figures24(a) and 24(b) display the frequency spectrum for the 11L phase voltage at 1.0 as M by using the SVPWM-I and SVPWM-II techniques. Whereas the frequency spectrum for the load current at M = 1.0 by using the SVPWM-I and SVPWM-II techniques is shown in Figures 25(a) and 25(b). Table 12 shows the experimental line voltage THD for different modulation indices for both SVPWM techniques. It is seen that the experimental THD value in lower when compared to THD obtained in simulation because the harmonic order of 100 is considered in digital storage oscilloscopes when calculating frequency spectra of any quantity, whereas during the simulation the entire frequency harmonic orders are contemplated in FFT analysis.Figure 24
Experimental FFT of line voltage atM = 1.0. (a) SVPWM-I. (b) SVPWM-II.
(a)(b)Figure 25
Experimental FFT of load current atM = 1.0. (a) SVPWM-I. (b) SVPWM-II.
(a)(b)Table 12
Experimental line voltage THD for different modulation indices.
Modulation index (M)Harmonic distortion (%)SVPWM-ISVPWM-II1.03.733.780.94.074.070.84.194.190.66.586.580.48.658.650.216.6416.64


## 6. Conclusion

By reducing the number of 2L hexagons that must have been considered from 1331 to 222 in order to realise the space vector PWM of the 11L inverter, the proposed SVPWM-I schemes significantly diminish the mathematical burden and the system memory requirements. This method can be generalised for any inverter level and is applicable to any inverter topology. Also presented is the SVPWM-II scheme, which diminishes the number of 2L hexagons so as to be considered to realise a nine-level SVM from 222 to 186. Eleven-level CHB inverter simulation analyses at various modulation indices are compared through SPWM and THIPWM techniques. Reduced harmonic distortion and greater DC bus utilisation are provided by the presented SVPWM schemes. To support the suggested SVPWM control strategies, experimental results are also provided. Thus, by simplifying the process of realising SVPWM for MLIS, the suggested two SVPWM-I and SVPWM-II techniques yield satisfactory results.



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*Source: 5548828-2023-02-20.xml*