# Hall Effect Devices with Three Terminals: Their Magnetic Sensitivity and Offset Cancellation Scheme

Authors: Udo Ausserlechner
Journal: Journal of Sensors
 (2016)

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## Abstract

This paper discusses properties of Hall effect sensors with only three terminals and compares them to conventional four-terminal devices. It covers both Horizontal and Vertical Hall effect devices. Their Hall-geometry factor is computed analytically. Several modes of operation are proposed and their signal-to-noise ratio is compared. A six-phase offset cancellation scheme is developed. All theoretical results are checked by measurements. The residual offset of Vertical Hall effect devices with three contacts is found to be smaller than the offset of conventional Vertical Hall effect devices with five contacts.


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## Body

## 1. Introduction

Traditionally, Hall plates have four contacts and two orthogonal planes of mirror symmetry: two opposite contacts are used to supply the device with electrical energy while the other two opposite contacts are used to tap the output signal. The Hall plate can be supplied by a voltage or a current source and the output signal can be sensed by a voltmeter or an amperemeter. The combination of these possibilities gives four operating modes. For such devices spinning current schemes are known: they swap the two pairs of contacts—inputs and outputs—in consecutive operating phases. Combining the outputs of so-called orthogonal phases cancels out offset errors while keeping the magnetic sensitivity high. The output in each phase has a raw or initial offset, whereas the combination of phases according to the spinning scheme gives a much smaller offset, which is called residual offset. Offset error is stochastic so that one has to measure its standard deviation in order to quantify it. The standard deviation of a Gaussian distributed quantity is equal to its root mean square value, which we denote by rms. Moreover, if we compare different technologies and different types of devices, it is pretty meaningless to specify the offset in microvolts. Instead one should divide the output signal by the magnetic sensitivity in order to get the so-called equivalent offset in microtesla. In silicon technology the raw offset of state-of-the-art packaged Hall plates is roughly 7.5 mTrms and the residual offset of a good spinning current circuit may be as low as 15μTrms. This is a drastic improvement of the offset error by a factor of 500. Thereby low residual offset is achieved only if either (i) constant current is forced during all spinning current phases into the device while voltage is tapped at the outputs or (ii) constant voltage is forced during all phases across the input terminals of the device while the short-circuit output current is sensed between the output terminals [1]. We call the latter procedure “spinning voltage scheme” to discriminate it against the first one, the “spinning current scheme.” If we refer to both schemes, we simply say “spinning scheme” or “dynamic offset cancellation.” So it is commonly believed that (i) the current needs to spin around in space during this dynamic offset cancellation procedure, that (ii) both input and output terminals need to be swapped in order to get best suppression of offset errors, and that (iii) the Hall plate must have 90° symmetry for the spinning scheme to work. However, none of these requirements is obligatory, as we will see in the sequel.With the advent of Vertical Hall effect devices the spatial spinning of current during the “spinning” scheme became obsolete; however, up to now all published dynamic offset cancellation schemes still seem to work with exactly two inputs and two outputs, which are continuously swapped. We call Vertical Hall effect devices VHalls in contrast to Hall plates, which we also call Horizontal Hall effect devices or HHalls. The terms “horizontal” and “vertical” denote the orientation of the plate-like geometry of the devices with respect to the main surface of the semiconductor die. It is a misconception that VHalls need to have current flowing in vertical direction into the depth of the die. In fact the predecessors of VHalls withoutput contacts only on a single side of the device used a current purely parallel to that side [2] (Figure 1). Of course devices withinput contacts on the top side of the Hall effect region need some vertical and some horizontal current flow. As a general rule, they tend to have the highest magnetic sensitivity when the share of vertical to horizontal current flow is about 50%.Figure 1
A Hall plate with five contacts after [2]. The two small sense contacts are only on one single side of the Hall effect regions. (a) shows the geometry. (b) shows the potential and the current streamlines as obtained by a numerical calculation for a Hall angle of 45°. For small Hall angle the current streamlines become parallel to the long edge of the device.
(a)
(b)We specify the number of contact diffusions per Hall effect region: for example, the well known original VHall device of [3] is termed 5C-VHall (see Figure 2). It has five contact diffusions in the Hall effect region, which we label C1,C2,…,C5 from left to right. The outmost two of them (C1 and C5) are shorted, so that the device offers a total of four terminals T1,T2,T3,T4; therefore a more precise name for it is 5C-4T-VHall. Recently, a similar device was published, where the contacts C2 and C4 are shorted instead of C1 and C5, but the number of terminals is still four [4].Figure 2
A Vertical Hall effect device with five contacts and four terminals in BiCMOS technology with deep trench isolation. The contacts comprise shallown+S/D-diffusions and slightly deepernCMOS-wells. The bottom of the Hall effect region is shorted by a highly conductiven-buried layer at floating potential.
(a)
(b)


## 2. The Role of Symmetry

Obviously, the degree of symmetry in VHalls is smaller than that in HHalls, because the accessible contacts of VHalls are only on the top face of the Hall effect region, whereas the contacts of HHalls can be arranged symmetrically along the entire perimeter of the Hall plate. Thus, there must be two outmost contacts as long as the Hall effect region has the shape of a straight tub, and these outmost contacts break the symmetry. This might also contribute to the roughly ten times larger equivalent residual offset error of VHalls compared to HHalls. So several people have tried to improve the symmetry. Here we name just a few:(1)
One may apply the principle of forced symmetrization as it is used by HHalls since the 1980s: instead of a single device with four terminals one uses four devices and connects each terminal to a different contact of a different device as shown in Figure3 [5].No matter how asymmetric a single device was, the complete network of four devices is symmetric in an electric sense: the resistance between terminalsT1→T2 is equal to the resistance between terminals T2→T3, or T3→T4, or T4→T1 and the output signal between T1→T3 is equal to the output signal between T2→T4. For traditional Hall plates this was used to average out systematic offset errors caused by mask misalignment or mechanical stress. In VHalls it averages out junction field effects and charge modulation effects, too. Such a kind of symmetrization facilitates the task for the Hall biasing and signal conditioning circuits, yet it does not solve the problem for each single device: it is still asymmetric and the forced symmetrization circuit only adjusts the amount of current through it to counterbalance its asymmetry.(2)
One can avoid the two ends of the Hall tub by using a ring-shaped Hall effect region with eight or more contacts [6]. Not all of these contacts are used simultaneously: in [7] one uses five consecutive contacts during a first phase like in the 5C-VHall device, and during subsequent operating phases the group of five contacts is shifted (counter)clockwise. In some technologies like those with deep trench isolation it is not possible to make ring-shaped Hall effect regions, because the boundaries of the trenches must be parallel to the edges of the die. Moreover the large number of MOS-switches needed to route current through so many contacts requires considerable chip space. Besides, there is no theoretical proof yet that the spinning principles applied to these structures cancel out offset in a strict sense: with each new phase at least one further MOS-switch adds its on-resistance to the residual offset. The reported offsets achieved in practice may result simply from the statistical average of the large number of partial devices used.(3)
Another strategy is to use several disjunct Hall tubs and connect them with wires in a ring topology like in Figure4 [8, 9]. This arrangement is perfectly symmetric; however, the price we pay is that the voltage drop in these two tubs, which have the supply terminals, does not contribute to the Hall effect. So the power efficiency of the device is suboptimal. However, one may connect a large number of devices in a ring circuit. Then the percentage of the two devices with supply contacts is small and the efficiency of the device is higher; however a complete spinning scheme over all devices takes longer and this limits the bandwidth. The residual offset is low because the voltage per device (and thus the nonlinearity caused by the electric field) is low and the large number of devices results in better statistical averaging. The magnetic sensitivity is low, but the SNR is high.Figure 3
Four 5C-VHalls connected in a forced symmetrization pattern.Figure 4
Examples of VHalls comprising several disjunct Hall tubs.In fact, electrical symmetry is not the main problem for spinning schemes. Even if a four-terminal device would lack any kind of electrical symmetry the spinning scheme would cancel out the offset error perfectly well, as long as the device has linear electrical properties and if we disregard thermoelectric effects [1]. Electrical linearity means that its equivalent resistor circuit is made up of resistors with fixed values which do not depend on applied potential. In practice the active Hall effect region is isolated against its surroundings by reverse biased pn-junctions, whose depletion region widths depend on the potentials, and this voltage dependence changes the shape of the Hall effect region depending on the applied potentials finally leading to electrical nonlinearity. Even if the side-walls of the Hall tub are isolated by trench isolation with thin dielectric layers charge modulation along the perimeter of the Hall effect region will be caused by varying potentials analogous to the channel region of PMOS transistor. Moreover, for small devices the electric field exceeds 100 kV/m which gives rise to velocity saturation in low dopedn-type silicon, and this is another source of electrical nonlinearity. For HHalls this is no problem, since one can scale the lateral size of the device until the electric field is low enough. For VHalls one cannot scale the thickness into the depth of the substrate; it is given by the technology: for BiCMOS technologies one may use the epitaxial layer with a thickness around 5 μm, for HV-CMOS technologies one may use a CMOS well of a high-voltage transistor with around 3 μm thickness, and for plain CMOS one has to cope with the logic CMOSn-well of only 1.5 μm thickness. The size and spacing of the contacts on the surface of the Hall tub relate to the thickness of the tub: if the thickness is small also the sizes of the contacts and their spacing need to be small in order to have a reasonably strong Hall output signal. In practice the size of the contacts as well as their minimum distance is limited by layout design rules of the specific technology. And smaller distances between contacts lead to larger electric field, which causes mobility degradation, electrical nonlinearity, and inhomogeneous temperature distribution in the Hall device. All these effects give large residual offset. This leads us to the idea that a device with a minimum number of contacts should have the least problems with contact size and spacing and therefore we hoped that devices with only three contacts may have advantages over traditional ones with more contacts.It is known for a while that large contacts reduce the Hall output signal, because on the one hand the output contacts draw current away from the Hall effect region (current likes to flow over the low ohmic contacts instead of flowing through the high ohmic Hall effect region) so that it is not available for the Hall effect any more, and on the other hand the input contacts short a part of the Hall electric field. For these reasons one is inclined to use as few contacts as possible, namely, three.VHalls in BiCMOS technologies can benefit from the lown-doped epitaxial layer and its relatively large thickness. However, the bottom of then-epi layer is not isolated by ap-doped region; instead there is a highly conductiven-buried layer, which acts like a contact at the bottom side of the Hall effect region (Figure 2). Yet, it is difficult to connect thisn-buried layer contact to a terminal. So it is a floating contact that shorts some portion of the Hall output signal but which cannot be tapped by the circuit to use it as an output signal. In other words, such a device may have, for example, three diffusion contacts at the top of the Hall effect region plus one floating contact at the bottom of the Hall effect region. Obviously, one is trying to reduce the number of additional contacts on the top surface in order to keep the electric field reasonably low. This was the motivation that led us to a closer investigation into Hall effect devices with only three terminals.In the following we start with Hall plates having only three contacts, derive their equivalent circuit diagram, and discuss various operating modes and their signal-to-noise ratios (SNR). Then we derive a linear theory on spinning schemes for Hall effect devices with three contacts. In the measurement sections we check our theories with 3C-HHall and 3C-VHall and compare them to 4C-HHalls and 5C-VHalls.


## 3. Magnetic Sensitivity in Various Operating Modes

Figure5 shows 3C-HHall, 3C-VHall, and their equivalent resistor network at vanishing magnetic field. The 3C-HHall has a 120° symmetry so that it does not change its shape when rotated by ±120°. Therefore the resistors R1=R2=R3 are nominally equal for the 3C-HHall. Conversely, the 3C-VHall has only mirror symmetry with respect to its center contact C2, so that the resistors R1=R2<R3. The shapes of Hall effect regions for the devices in Figure 5 are merely examples; particularly for VHalls there is a large variety of possible geometries: with or without buried layers, all contacts in a row or not, and several disjunct Hall effect regions connected in a ring circuit or not. In the following we discuss the magnetic sensitivity of devices with one or two Hall effect regions.Figure 5
A symmetrical 3C-HHall device (a), an asymmetrical 3C-VHall device (b), and an equivalent circuit diagram for general 3C-Hall devices (c).
(a)
(b)
(c)If current flows between two supply contacts, the potential at the third sense contact depends on the symmetry: in the symmetric case it is close to half of the supply voltage at zero magnetic field; in the asymmetric case it is somewhat closer to that supply potential, whose contact is nearer. When a magnetic field is applied perpendicularly to the plate the potential at the third contact rises or decreases, depending on whether the contact is left or right to the current streamlines. This holds also for asymmetric operation: for example, if current flows from left to center contact of the VHall in Figure5 the right contact is to the right of the current flow and so its potential decreases when magnetic field pointing out of the drawing plane is applied. With this simple rule, one can figure out easily the sign of the Hall output signals for unconventional Hall effect devices.Figures6(a)–6(e) show various modes of operation of a 3C-device. For the sake of simplicity, we choose a symmetric device, but the same principles apply to asymmetric HHalls or VHalls. First we discuss how these devices can be biased and how one can extract an output signal. The underlying motivation is to find one arrangement with optimum magnetic sensitivity, minimum noise, and maximum power efficiency.Figure 6
Differential operating mode (a) and equivalent circuit model of its left half. (b) Operating mode (b) and equivalent circuit model. (c) Operating mode (c) has inverted current flow polarities of operating mode (b). (d) Operating mode (d) and its equivalent circuit diagram. (e) Operating mode (e) has inverted polarity of supply current from operating mode (d).
(a)
(b)
(c)
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(e)Figure6(a) shows a differential operation, where two devices are supplied with currents flowing through their first two contacts whereby the output signal is tapped between their third contacts. One device has its sense contact to the left hand side of the current path while the other one has its sense contact to the right of the current path. Therefore, the potential on the sense contact of one device rises while it falls on the sense contact of the other device. The output voltage is tapped between the sense contacts of both devices. Each of the two devices has two supply contacts and a single sense contact.A numerical simulation assumed a conductivity tensorσ__=σ01-μHBzμHBz1 with σ0=62.5S/m and a Hall-mobility of μH=0.13038T-1. The Hall effect region is derived from an equilateral triangle with 40 μm long edges, where the corners are cut off by circles with 10 μm radius and the resulting curved boundaries are used as contacts. The thickness of the plate was tH=1μm. A current of Iina/2=40.1μA was injected into contact C2 of each device. This gave a potential of Vina=1.0V on C2. At zero magnetic field the potential at C3 is exactly half of this value and it rises by 1.66 mV if a magnetic field of Bz=50mT is applied to the left device. So the input resistance of the complete device is Rina=Vina/Iina=12457.2Ω. The sheet resistance is RS=1/tHσ0=16000Ω and this gives the effective number of squares L/Wina=Rina/RS=0.779. The output voltage is given by Vouta=SiBzIina with the current related magnetic sensitivity (1)Si=12μHσ0GH03CtH,whereby GH03C is the Hall-geometry factor at low magnetic field and factor 1/2 accounts for the fact that the 3C-Hall has only a single output terminal. By splitting apart factors 1/2 and GH03C we make sure that the Hall-geometry factor GH03C accounts only for the short circuiting effects of contacts of finite size; if all contacts become point-sized it holds that GH03C→1 just like it was originally defined with traditional four-contact Hall plates [10]. A strict derivation of (1) is given in Appendix A.For the device in Figure6(a) we get GH03C=0.79228 which gives Si=826.4V/A/T. The voltage related magnetic sensitivity is defined as Sua=Vouta/BzVina=Si/Rina. For the device in Figure 6(a) we get Sua=0.0663V/V/T. The value for Sua is even 8% larger than the maximum Su for conventional 4C-HHalls with 90° symmetry, which is max⁡Su4C=μH2/3=0.0615V/V/T [11]. With Appendix C one finds max⁡Sua≅0.539×μH for 3C-Halls with 120° symmetry, which is 1.14 times larger than max⁡Su4C.However, magnetic sensitivity is less important than signal-to-noise ratio, which we derive next. The equivalent resistor network in Figure6(a) gives Rina=Req/3 and Routa=4Req/3, so the output resistance is four times the input resistance. The numbers are Routa=49828.8Ω and Req=37371.6Ω. The output number of squares is defined as L/Wouta=Routa/RS. From the equivalent circuit it follows that L/Wouta=4L/Wina. Thus, the thermal noise at the output is Vna=4kbTRSL/WoutaΔf with Boltzmann’s constant kb, the absolute temperature T, and the effective noise bandwidth Δf. 1/f-noise is irrelevant, because it is chopped out by the spinning scheme [12]. But in practice the Hall effect device should be optimized to have maximum signal-to-noise ratio, SNR, but at the same time neither the current drain nor the necessary input voltage should be too large. So we do not want to maximize SNR/Iin or SNR/Vin, but we need maximum SNR while keeping Rin constant. In fact at the start of a new sensor system development the circuit design engineers choose the impedance level Rin at which they want the circuit to operate, because this defines the current drain and the size of the noise critical transistors of the signal conditioning circuits. To this end we express the signal-to-noise ratio in operating mode (a) in the following way: (2)SNRa=12μHBz4kbTΔfGH03CL/WinaL/WoutaVinaRinafrom which it is evident that we need to maximize the Hall-mobility and the term GH03C/L/WinaL/Wouta, which depends only on the lateral geometry of the device. The same result is obtained if we maximize the SNR over the square-root of the power dissipated in the Hall effect device SNRa/VinaIina=μHBzGH03C/4kbTL/WinaL/WoutaΔf. In practice, saving power in a Hall effect device pays only, if the input resistance of the device is such that the total available supply voltage drops over the device and not over a pass transistor in its bias circuit, and this brings us back to the intuition of the circuit design engineer who chooses the optimum impedance level at the start of the circuit design.For the device in Figure6(a) we get GH03C/L/WinaL/Wouta=0.509. How does it relate to conventional 4C-Hall plates? Appendix B shows that they have a maximum GH04C/L/Win4CL/Wout4C≤2/3=0.471, which is achieved for L/Win4C=L/Wout4C=2. However, in the SNR of the 3C-Hall effect device (in (2)) we had to add the extra factor 1/2, so that the SNR of the device in Figure 6(a) is 0.471/0.509/2=1.85 times smaller than the optimum SNR of 4C-Hall. In Appendix C we investigate the SNR of the symmetrical 3C-Hall for various contact sizes and there we will see that even for optimum symmetrical 3C-Halls the SNRa is ~1.75 times smaller than the SNR for optimum 4C-Halls (under the boundary condition of equal input resistance, see (C.1)). So this is bad news for symmetrical 3C-HHalls and 3C-VHalls in operating mode (a): at the same input resistance they have ~1.75 times smaller SNR; for the same SNR we need to spend ~3.06 times more current. However, in the case of single tub 4C-VHalls it seems impossible to achieve an optimum device, which can be mapped by a conformal transformation onto a 180°-symmetrical 4C-HHall and therefore the single tub 3C-VHalls may still be a viable compromise.Figure6(a) also shows an equivalent circuit diagram for the 3C-HHall, which models the output signal at small magnetic field. It holds if the third contact is grounded and it accounts for the symmetry between contacts C2 and C3. In the following we show that it may also be used to describe the output signals in other operating modes.Figure6(b) shows an operation of a single device, where equal currents are injected into contacts C2 and C3, while the third contact C1 is at ground potential. The output voltage is tapped between the two current input contacts. In this case all three contacts of the device are supply contacts, whereby the two current input contacts also act as sense contacts.With the parameters from above a numerical simulation gives a voltage difference ofVoutb=2.21mV at currents of Iinb/2=53.5μA in both contacts C2, C3, and at Bz = 50 mT. At zero magnetic field the potential at contacts C2 and C3 is 1.0 V. Thus, the voltage related magnetic sensitivity is Sub=44.2mV/V/T, which is 1.5 times smaller than Sua in Figure 6(a). The equivalent circuit diagram gives Voutb=SiBzIinb which agrees with this result of the numerical simulation. The input resistance Rinb=Req/2 is 1.5 times larger than that in Figure 6(a). The output resistance Routb=2Req/3 is only half of the output resistance of Figure 6(a). Hence, according to (2) for equal devices at constant supply voltage the SNR of Figure 6(b) is reduced by factor 2/3/2≅0.943 compared to Figure 6(a). However, the supply current is also reduced by factor 1.5 so that the SNR/Iin in Figure 6(b) is 2≅1.414 times larger than that in Figure 6(a). And what is the maximum SNR of Figure 6(b) for a given input resistance? To this end we increase the thickness of the device in operating mode (b) 1.5 times. Then the input resistance of the original thin device in operating mode (a) is equal to the input resistance of the new thick device in operating mode (b). The change of the thickness has no effect on GH03C/L/WinbL/Woutb, but it decreases the input resistance of mode (b) 1.5 times and so it increases its SNR by 3/2. Thus, the SNR of the thick device in mode (b) is factor 2/3/2=2/3≅1.155 times larger than the SNR of the thin device in mode (a) with identical input resistance. In other words(3)max⁡SNRb=23max⁡SNRafor  equal  input  resistanceRina=Rinb.Hence, for a given input voltage and for a given input resistance the operating mode (b) can achieve 15.5% higher SNR than operating mode (a). Compared to optimum 4C-HHalls with L/Win4C=L/Wout4C=2 the maximum SNR of Figure 6(b) at equal input resistance is still ~1.51 times smaller (see Appendices B and C, (B.2), and (C.2)). To make up for this, one has to reduce the input resistance 2.28 times and this increases the current drain by the same factor.Figure6(c) shows a current polarity inversion of the operation of Figure 6(b), where current is forced to flow out of two contacts at low potential while the third contact is at high potential.Figure6(d) shows the same device being supplied with identical potential at two contacts C2 and C3, while the third one is at ground potential. For Vind=1V the numerical simulation gives I3-I2=0.177μA at Bz = 50 mT. Here the output signal is the difference in currents flowing into both C2 and C3. The sum of both currents is Iind=53.52μA. With the equivalent circuit diagram in Figure 6(d) we obtain I3d-I2d=6VindSiBz/Req2+Si2Bz2≅3IindSiBz/Req which matches the result of the numerical simulation. Current consumption and input and output resistance are identical to Figure 6(b). Figure 6(e) shows the polarity inversion of this operation, where the identical potentials at C2 and C3 are lower than the supply potential.


## 4. Iv-Biasing Six-Phase Offset Cancellation Scheme

In this section we discuss an offset cancellation scheme for 3C-Halls: Iv-biasing. Thereby, the device is supplied withthe same input current in six operating phases and the output voltages of all phases are sensed and processed. For the sake of brevity we explain the principle with asymmetric 3C-VHalls. Obviously, the same procedure may be applied to symmetrical devices and to HHalls, too. In Figures 7(a)–7(f) the left ones show a physical cross section of the device and the circuit parts connected to the device, whereas the right figures show simplified linearized equivalent circuit diagrams to estimate the output signals at zero magnetic field. If a label “+B” is written to a contact this means that the signal at this contact increases with increasing magnetic field whereas “−B” means that it decreases with increasing magnetic field. The magnetic field is supposed to point outside of the drawing plane. In the equivalent circuit diagram R1 is roughly equal to R2 due to the symmetry of the device, yet due to tolerances, mechanical stress, and electric nonlinearity of the device there is a mismatch between R1 and R2 in the order of 0.1%⋯5%. The contacts are labeled 1, 2, and 3 from left to right. Operating phases are labeled 1,2,…,6.Figure 7
(a) Operating phase 1 of Iv-biasing scheme of differential operating mode according to Figure6(a). (b) Operating phase 3 of Iv-biasing scheme of differential operating mode according to Figure 6(a). (c) Operating phase 2 of Iv-biasing scheme of differential operating mode according to Figure 6(a). (d) Operating phase 4 of Iv-biasing scheme of differential operating mode according to Figure 6(a). (e) Operating phase 5 of Iv-biasing scheme of differential operating mode according to Figure 6(a). (f) Operating phase 6 of Iv-biasing scheme of differential operating mode according to Figure 6(a).
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(b)
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(f)The Iv-biasing scheme applies to the differential operating mode of Figure6(a). All quantities of the right device are primed whereas the quantities of the left device are unprimed. Two operating phases are shown in Figures 7(a) and 7(b). In phase 1 currents are injected into the left contact of the left device and into the right contact of the right device so that Iina=I0+I0′. Preferably both currents are identical, yet in practice one has to account for inevitable mismatches between I0 and I0′. The center contacts of both devices are grounded and the output voltage Vph1 is tapped between the right contact of the left device and the left contact of the right device. In the left device contact C3 is at the right hand side of the current flow and so its potential decreases with growing magnetic field (“−B”). Conversely, in the right device contact C1′ is at the left hand side of the current flow and so its potential increases with growing magnetic field (“+B”). Thereby it is irrelevant if the magnetic sensitivity of both devices is identical or not; only the sign counts, because eventually we aim at adding up all output voltages of all phases constructively in order to have a large overall magnetic sensitivity. We denote this by adding the term S1B to the output voltage, whereby 1 denotes phase 1 and S1B is supposed to be a positive number. The output signal of phase 1 is the sum of raw offset plus a magnetic field term:(4)Vph1=I0′R1′R2′R1′+R2′+R3′-I0R1R2R1+R2+R3+S1B.The raw offset is also called electric raw offset, because it is described by the equivalent electric circuit. This is in contrast to thermoelectric offset terms, which are also present in a real device and which are not described by the equivalent electric circuit. We will come back to thermoelectric offset later.Figure7(b) shows operating phase 3 where the roles of current input contacts and voltage output contacts are swapped, whereas the center contacts remain grounded. If the device is asymmetric, the magnetic sensitivity may be different. Therefore we add the positive term S3B to the output voltage: (5)Vph3=I0R1R2R1+R2+R3-I0′R1′R2′R1′+R2′+R3′+S3B.If the magnetic field vanishes, the output voltages of phases 1 and 3 have equal magnitude but opposite sign! Consequently if we add them up the electric raw offsets of phases 1 and 3 cancel out while the magnetic sensitivities add up: Vph1+Vph3=S1+S3B. We call these two phasesorthogonal phases in analogy to conventional 4C-HHalls, where the electric raw offsets of two orthogonal current directions also cancel out. Note that the offset is canceled out even if I0 and I0′ are not equal! In practice, each terminal of the Hall devices is connected to MOS-switches, which have a small but nonnegligible on-resistance. In this case we have to add R2′ds,onI0′-R2ds,onI0 to Vph1, which comes from the on-resistance of the switch that connects contacts C2 and C2′ to ground. However, the same switch is active in phase 3 and so its contribution is canceled out in the sum of Vph1+Vph3. The on-resistance of the switches at the current inputs and voltage outputs is irrelevant.Basically, the two phases 1 and 3 are enough to cancel out the offset, if the origins of offset were fully described by the equivalent circuit. However, in reality offset also comes from thermoelectric voltages: the output voltage is tapped at a contact, where then-doped silicon region is in contact with the metal interconnect layer. This pair of different materials adds a small thermoelectric voltage, which depends on the temperature of the contact region and on the difference in Seebeck-coefficients of the involved material partners. Usually, these thermoelectric errors are cancelled out by reversing the polarity of the supply current: if the device is symmetric with respect to the supply current path a polarity inversion does not change the temperature in the device and so it does not change the thermoelectric voltage at the contacts. However, it changes the sign of the magnetic sensitivity. Thus, if we subtract two output signals from phases with different polarity of supply current, we cancel out thermoelectric voltages and add up the magnetic sensitivities of both phases. Therefore, an efficient offset cancellation scheme must comprise pairs of phases with opposite polarity of supply current. We call the phases of such a pairinverse phases. Our phases 1 and 3 were orthogonal, yet they were not inverse! So, we look for additional operating phases, which are inverse to phases 1 and 3. Finally, the complete spinning scheme must consist of a number of phases, where each phase has exactly one orthogonal phase and where each phase has exactly one inverse phase.Figure7(c) shows phase 2, which is inverse to phase 3, because it merely reverses the polarity of the supply current. Moreover, Figure 7(d) shows phase 4, which is inverse to phase 1 due to its opposite supply current polarity: (6)Vph2=I0′R1′R3′R1′+R2′+R3′-I0R2R3R1+R2+R3+S2B,Vph4=I0R1R3R1+R2+R3-I0′R2′R3′R1′+R2′+R3′+S4B.Unfortunately, phases 2 and 4 are not orthogonal; their electric offsets do not cancel out, if we add the output signals Vph2+Vph4. So we have to find two phases, which are orthogonal to phases 2 and 4 and at the same time they must be inverse to each other, because phases 1 and 4 are an inverse pair and phases 2 and 3 are also an inverse pair. Phases 5 and 6 in Figures 7(e) and 7(f) fulfill all these requirements: Phase 5 is orthogonal to phase 2, phase 6 is orthogonal to phase 4, and phases 5 and 6 are inverse: (7)Vph5=I0R2R3R1+R2+R3-I0′R1′R3′R1′+R2′+R3′+S5B,Vph6=I0′R2′R3′R1′+R2′+R3′-I0R1R3R1+R2+R3+S6B.It holds that Vph2+Vph5=S2+S5B and Vph4+Vph6=S4+S6B. So the complete spinning scheme uses all six possible combinations of current flow through the device: (8)Vtotal=Vph1+Vph2+Vph3+Vph4+Vph5+Vph6=S1+S2+S3+S4+S5+S6B.It cancels out electric offset errors and thermoelectric offset errors as long as the device is electrically linear. Electrical linearity means that the equivalent electric circuit consists of resistors, which are constant versus applied potentials. In practice, this is not the case: due to the junction field effect [13] and velocity saturation the resistance values in the equivalent circuit depend on the applied potentials roughly with 10%/V. This means that the resistance values change slightly in different operating phases of the spinning scheme and consequently the offset does not get canceled out perfectly. Moreover, due to this electrical nonlinearity of the device, the current density is increased near contacts at high potential and this leads to an inhomogeneous temperature distribution in the Hall device, which rotates synchronously with the spinning scheme. Therefore the scheme does not cancel out thermoelectric voltages perfectly, which adds another contribution to the so-called residual offset in the total output signal Vtotal.Obviously, the current does not spin around continuously in space like with conventional 4C-HHalls. So the term “spinning” is misleading and the term “contact commutation” is more correct. The essential feature is that each contact acts as positive supply terminal in two phases, as negative supply terminal in two phases, and as sense contact in two phases.


## 5. Measurement Results

### 5.1.
120° Symmetric 3C-HHalls

Figure8 shows the layout of 3C-HHalls, whereby three devices were connected in parallel such that the current flow directions in the left device and in the right device are rotated by ±120° against the current flow direction in the center device. In practice this arrangement acts as a single device with three times larger plate thickness. In the following we treat this arrangement as a single device; for example, by internal resistance Rinb we mean the resistance of all three devices in parallel operated in a mode according to Figure 6(b) and by internal resistance Rina we mean the total resistance of two such triples operated in a mode according to Figure 6(a). The doping concentration of the devices was very low: 2E15/cm3 and the thickness was 0.7 μm. The length of the edges of each triangular device was 40 μm and the spacing of the contacts was 20 μm. The contacts had the shape of 60° sectors of circles with 10 μm radius, whereby the centers of the circles coincided with the corners of the triangle. Each device was isolated against its surroundings by a reverse biased pn-junction along the perimeter and at the bottom. At the top there was no pn-junction. Instead, a top metal plate was isolated against the Hall effect region by oxide layers and the top plate was grounded. All samples were made from 750 μm thick silicon chips, glued on small printed circuit boards, wire-bonded, and covered by transparent gel. Measurements were done in a darkened zero-Gauss chamber at room temperature.Figure 8
Layout of three devices of type 3C-HHall connected in parallel.The internal resistance versus supply voltage was measured (see Figure9). The marked nonlinearity of 13.4%/V comes from the junction field effect. The ratio of resistance is 1.505, which is in accordance with the theory of Section 3. This ratio is nearly constant with supply voltage.Figure 9
Input resistance of the 3C-HHalls of Figure8 in operating modes (a), (b), and (c) of Figures 6(a), 6(b), and 6(c) measured at room temperature. Vin is averaged over all operating phases.The supply voltage related magnetic sensitivity is plotted versus supply voltage in Figure10. At low supply voltages the ratio of sensitivities is 1.60; according to our theory it should be 1.50. The deviation is 6.7%. The slope versus input voltage is ∂Sua/∂Vina=-7.8%/V, ∂Sub/∂Vinb=+15.9%/V, and ∂Suc/∂Vinc=-15.9%/V.Figure 10
Voltage related magnetic sensitivitySu of the 3C-HHalls of Figure 8 in operating modes (a), (b), and (c) of Figures 6(a), 6(b), and 6(c) measured at room temperature. Vin is averaged over all operating phases.The following offset cancellation schemes were investigated: in mode (a) the devices were operated like in Figure6(a) and the six-phase Iv-biasing as described in the section Iv-biasing was used. When the devices were operated in mode (b) or mode (c) according to Figure 6(b) or Figure 6(c) the offset was cancelled out like this: the devices were operated in three consecutive phases such that output voltages were tapped between contactsC1-C2,C2-C3, andC3-C1; then both current sources were swapped and the three phases were repeated; finally all six output voltages were summed up. The label “modes (b) + (c)” means that the phase signals of both schemes (b) and (c) were added up.Figure11 shows measurement results of the residual offset which depends strongly on the supply voltage: at large supply voltage (~3 V) the self-heating as well as the electrical nonlinearity of the device gives a large equivalent residual offset of more than 1 mT. At small supply voltage residual offset below 100 μT is feasible. Modes (b) and (c) have 2⋯3 times larger offset than mode (a), except for very low supply voltage, where mode (a) has the largest offset. It seems to be a disadvantage for the 3C-HHall that in modes (b) and (c) the output contacts are at positive or negative supply rail. On the other hand, the combination “modes (b) + (c)” seems to cancel out a significant systematic offset error in individual modes (b) and (c) so that, finally, the combination “modes (b) + (c)” has a lower offset. Two types of conventional octagonal Hall plates with four contacts and 90° symmetry were also characterized. Their lateral size was 80 μm, and the thickness was 0.9 μm and 1.6 μm, respectively. The doping of the 4C-HHalls was roughly four times larger than the doping of the 3C-HHall. The internal resistance of the 4C-HHalls was 40% larger than their sheet resistance RS They were operated in a conventional spinning current scheme comprising four phases, where constant current was forced through them and voltage was tapped at their output terminals. Figure 11 shows that the residual offset of these 4C-HHalls was 10⋯30 times smaller. Part of this difference can be explained by the larger doping level and thickness, but a major part seems to come from the lower thermoelectric symmetry of the 3C-HHall: modes (b) and (c) have no pairs of inverse phases and the combination “modes (b) + (c)” has pairs of inverse phases, yet at very different common mode potentials. Note that all devices in Figure 11 are single devices and the offset can be further reduced if a circuit takes the average over output signals of several devices according to the laws of statistics.Figure 11
Residual offset of the 3C-HHalls of Figure8 in operating modes (a), (b), and (c) of Figures 6(a), 6(b), and 6(c) measured at room temperature. Vin is averaged over all operating phases; “modes (b) + (c)” means that the signals of both operating phases (b) and (c) were summed up. The residual offset of two types of conventional Hall plates with four contacts (4C-HHall) and different sheet resistance RS is also shown.


### 5.2. Asymmetric 3C-VHalls

Measurements were carried out on test structures shown in Figure2. These are 5C-VHalls which we can also operate as 3C-VHalls, if we let the two outer contacts C1, C5 float; that is, we simply ignore terminal T1. The devices are 41.5 μm long and 4.6 μm wide and the Hall effect regions extend 5.5 μm into the substrate. The contacts are 1.1 μm × 4.6 μm and they are spaced apart by 5 μm. The devices were made in BiCMOS technology with a highly conductiven-buried layer at the bottom of a VHall device. The Hall effect region had a doping of about 3E15/cm3, which is way smaller than the doping of thenCMOS-well (2E17/cm3). The contacts were made ofn+S/D diffusion andnCMOS-well. Along the perimeter of the devices there is a deep trench at ground potential filled with polysilicon and isolated with a thin dielectric layer. The trench simultaneously patterns the Hall effect region and the buried layer. At the top of the device there is a grounded metal plate (not shown in Figure 2), which is isolated from the Hall effect region by oxide layers.Operation as 5C-VHall Device. Since the 5C-VHall has only four terminals (contacts C1 and C5 are connected to the same terminal T1 (cf. Figure 2)) it can be operated like a conventional 4C-HHall: current flows through the odd terminals and voltage is tapped at the even terminals and vice versa. At room temperature the input resistance at the odd terminals is 4 kOhm and at the even terminals it is 3 kOhm (both at small supply voltages). At larger supply voltages this resistance increases by 8.7%/V due to velocity saturation and charge modulation at the outer surfaces. At 2 V supply the resistance between the odd terminals changes by 4.7% if the polarity of the supply voltage is inverted, which is a clear sign of charge modulation at the trench walls. At small supply voltage the voltage related magnetic sensitivity is 39.5 mV/V/T at the odd terminals and 30.7 mV/V/T at the even terminals. It decreases by 6.3%/V at larger supply voltage. The ratio of input resistance between even and odd terminals is equal to the ratio of voltage related magnetic sensitivities at these terminals, because the current related magnetic sensitivity is the same for even and odd terminals, as was proven in [14]. A conventional spinning scheme of type “Iv-biasing” was carried out: constant current was forced and output voltage was sampled and added up over all four operating phases as described in [1]. Twenty samples were made from 750 μm thick silicon, attached to small printed circuit boards, wire-bonded, covered by transparent gel, and characterized in a darkened zero-Gauss chamber. Figure 12 plots the equivalent residual offset versus supply voltage. Additional test structures were characterized with devices of the same type connected in a forced symmetrization scheme according to Figure 3 and no notable improvement on residual offset was observed (beyond factor two, which is explained by the parallel connection of four devices).Figure 12
Measured residual offset of 5C-VHalls of Figure2 operated in conventional spinning current scheme.Operation as 3C-VHall Device. The resistance between C2 and C4 was 3.8 kOhm. Between C3 and one of its neighboring contacts (C2 or C4) it was 14% smaller. It increased by 10%/V with the supply voltage. In an operation according to Figure 6(a) the voltage related magnetic sensitivity at C3 was 38 mV/V/T, at C2 and C4 it was 14% larger: 43 mV/V/T. We executed the Iv-biasing six-phase offset cancellation scheme and derived the residual offset for 13 samples (see Figure 13). So the spinning scheme basically works.Figure 13
Measured residual offset of 3C-VHalls operated in Iv-biasing six-phase offset cancellation scheme. The devices were actually 5C-VHalls from Figure2 with the outer contacts C1, C5 floating.Comparison of Figures12 and 13 shows a smaller offset for the 3C-VHall. This becomes more evident if we plot the standard deviation of both offsets versus supply voltage in Figure 14. For the 5C-VHall it is 200 μTrms at 0.5 V supply and 550 μTrms at 1 V supply. For the 3C-VHall it is 100 μTrms at 0.5 V and 260 μTrms at 1 V supply. So the measurement indicates that the residual offset of the 5C-VHall is twice the residual offset of the 3C-VHall. At 0.55 V supply the ultralow offset VHall in [9] has 50 μTrms offset, yet it is composed of 16 tubs, whereas the 3C-VHall in Figure 14 is only a single tub. A parallel connection of four 3C-VHalls of Figure 14 has the same internal resistance as the ultralow offset VHall in [9] and is expected to have the same offset, namely, 100/sqrt(4) = 50 μTrms. Factor 10 difference in offset errors reported between the ultralow offset VHall and the fully symmetrical VHall in Table  1 of [9] can be explained by the different number of devices (factor 2) and by the different supply voltage: according to Figure 14 the offset at a supply voltage of 2.44 V is roughly 7 times larger than that at 0.55 V. In [9] the doping concentration is higher and so factor 7 may well reduce to a factor of 5. So it seems that both devices in [9] and our 3C-VHall in Figure 14 show similar residual offset errors at low supply voltage.Figure 14
Standard deviation of the residual offsets of Figures12 and 13.


## 5.1.
120° Symmetric 3C-HHalls

Figure8 shows the layout of 3C-HHalls, whereby three devices were connected in parallel such that the current flow directions in the left device and in the right device are rotated by ±120° against the current flow direction in the center device. In practice this arrangement acts as a single device with three times larger plate thickness. In the following we treat this arrangement as a single device; for example, by internal resistance Rinb we mean the resistance of all three devices in parallel operated in a mode according to Figure 6(b) and by internal resistance Rina we mean the total resistance of two such triples operated in a mode according to Figure 6(a). The doping concentration of the devices was very low: 2E15/cm3 and the thickness was 0.7 μm. The length of the edges of each triangular device was 40 μm and the spacing of the contacts was 20 μm. The contacts had the shape of 60° sectors of circles with 10 μm radius, whereby the centers of the circles coincided with the corners of the triangle. Each device was isolated against its surroundings by a reverse biased pn-junction along the perimeter and at the bottom. At the top there was no pn-junction. Instead, a top metal plate was isolated against the Hall effect region by oxide layers and the top plate was grounded. All samples were made from 750 μm thick silicon chips, glued on small printed circuit boards, wire-bonded, and covered by transparent gel. Measurements were done in a darkened zero-Gauss chamber at room temperature.Figure 8
Layout of three devices of type 3C-HHall connected in parallel.The internal resistance versus supply voltage was measured (see Figure9). The marked nonlinearity of 13.4%/V comes from the junction field effect. The ratio of resistance is 1.505, which is in accordance with the theory of Section 3. This ratio is nearly constant with supply voltage.Figure 9
Input resistance of the 3C-HHalls of Figure8 in operating modes (a), (b), and (c) of Figures 6(a), 6(b), and 6(c) measured at room temperature. Vin is averaged over all operating phases.The supply voltage related magnetic sensitivity is plotted versus supply voltage in Figure10. At low supply voltages the ratio of sensitivities is 1.60; according to our theory it should be 1.50. The deviation is 6.7%. The slope versus input voltage is ∂Sua/∂Vina=-7.8%/V, ∂Sub/∂Vinb=+15.9%/V, and ∂Suc/∂Vinc=-15.9%/V.Figure 10
Voltage related magnetic sensitivitySu of the 3C-HHalls of Figure 8 in operating modes (a), (b), and (c) of Figures 6(a), 6(b), and 6(c) measured at room temperature. Vin is averaged over all operating phases.The following offset cancellation schemes were investigated: in mode (a) the devices were operated like in Figure6(a) and the six-phase Iv-biasing as described in the section Iv-biasing was used. When the devices were operated in mode (b) or mode (c) according to Figure 6(b) or Figure 6(c) the offset was cancelled out like this: the devices were operated in three consecutive phases such that output voltages were tapped between contactsC1-C2,C2-C3, andC3-C1; then both current sources were swapped and the three phases were repeated; finally all six output voltages were summed up. The label “modes (b) + (c)” means that the phase signals of both schemes (b) and (c) were added up.Figure11 shows measurement results of the residual offset which depends strongly on the supply voltage: at large supply voltage (~3 V) the self-heating as well as the electrical nonlinearity of the device gives a large equivalent residual offset of more than 1 mT. At small supply voltage residual offset below 100 μT is feasible. Modes (b) and (c) have 2⋯3 times larger offset than mode (a), except for very low supply voltage, where mode (a) has the largest offset. It seems to be a disadvantage for the 3C-HHall that in modes (b) and (c) the output contacts are at positive or negative supply rail. On the other hand, the combination “modes (b) + (c)” seems to cancel out a significant systematic offset error in individual modes (b) and (c) so that, finally, the combination “modes (b) + (c)” has a lower offset. Two types of conventional octagonal Hall plates with four contacts and 90° symmetry were also characterized. Their lateral size was 80 μm, and the thickness was 0.9 μm and 1.6 μm, respectively. The doping of the 4C-HHalls was roughly four times larger than the doping of the 3C-HHall. The internal resistance of the 4C-HHalls was 40% larger than their sheet resistance RS They were operated in a conventional spinning current scheme comprising four phases, where constant current was forced through them and voltage was tapped at their output terminals. Figure 11 shows that the residual offset of these 4C-HHalls was 10⋯30 times smaller. Part of this difference can be explained by the larger doping level and thickness, but a major part seems to come from the lower thermoelectric symmetry of the 3C-HHall: modes (b) and (c) have no pairs of inverse phases and the combination “modes (b) + (c)” has pairs of inverse phases, yet at very different common mode potentials. Note that all devices in Figure 11 are single devices and the offset can be further reduced if a circuit takes the average over output signals of several devices according to the laws of statistics.Figure 11
Residual offset of the 3C-HHalls of Figure8 in operating modes (a), (b), and (c) of Figures 6(a), 6(b), and 6(c) measured at room temperature. Vin is averaged over all operating phases; “modes (b) + (c)” means that the signals of both operating phases (b) and (c) were summed up. The residual offset of two types of conventional Hall plates with four contacts (4C-HHall) and different sheet resistance RS is also shown.


## 5.2. Asymmetric 3C-VHalls

Measurements were carried out on test structures shown in Figure2. These are 5C-VHalls which we can also operate as 3C-VHalls, if we let the two outer contacts C1, C5 float; that is, we simply ignore terminal T1. The devices are 41.5 μm long and 4.6 μm wide and the Hall effect regions extend 5.5 μm into the substrate. The contacts are 1.1 μm × 4.6 μm and they are spaced apart by 5 μm. The devices were made in BiCMOS technology with a highly conductiven-buried layer at the bottom of a VHall device. The Hall effect region had a doping of about 3E15/cm3, which is way smaller than the doping of thenCMOS-well (2E17/cm3). The contacts were made ofn+S/D diffusion andnCMOS-well. Along the perimeter of the devices there is a deep trench at ground potential filled with polysilicon and isolated with a thin dielectric layer. The trench simultaneously patterns the Hall effect region and the buried layer. At the top of the device there is a grounded metal plate (not shown in Figure 2), which is isolated from the Hall effect region by oxide layers.Operation as 5C-VHall Device. Since the 5C-VHall has only four terminals (contacts C1 and C5 are connected to the same terminal T1 (cf. Figure 2)) it can be operated like a conventional 4C-HHall: current flows through the odd terminals and voltage is tapped at the even terminals and vice versa. At room temperature the input resistance at the odd terminals is 4 kOhm and at the even terminals it is 3 kOhm (both at small supply voltages). At larger supply voltages this resistance increases by 8.7%/V due to velocity saturation and charge modulation at the outer surfaces. At 2 V supply the resistance between the odd terminals changes by 4.7% if the polarity of the supply voltage is inverted, which is a clear sign of charge modulation at the trench walls. At small supply voltage the voltage related magnetic sensitivity is 39.5 mV/V/T at the odd terminals and 30.7 mV/V/T at the even terminals. It decreases by 6.3%/V at larger supply voltage. The ratio of input resistance between even and odd terminals is equal to the ratio of voltage related magnetic sensitivities at these terminals, because the current related magnetic sensitivity is the same for even and odd terminals, as was proven in [14]. A conventional spinning scheme of type “Iv-biasing” was carried out: constant current was forced and output voltage was sampled and added up over all four operating phases as described in [1]. Twenty samples were made from 750 μm thick silicon, attached to small printed circuit boards, wire-bonded, covered by transparent gel, and characterized in a darkened zero-Gauss chamber. Figure 12 plots the equivalent residual offset versus supply voltage. Additional test structures were characterized with devices of the same type connected in a forced symmetrization scheme according to Figure 3 and no notable improvement on residual offset was observed (beyond factor two, which is explained by the parallel connection of four devices).Figure 12
Measured residual offset of 5C-VHalls of Figure2 operated in conventional spinning current scheme.Operation as 3C-VHall Device. The resistance between C2 and C4 was 3.8 kOhm. Between C3 and one of its neighboring contacts (C2 or C4) it was 14% smaller. It increased by 10%/V with the supply voltage. In an operation according to Figure 6(a) the voltage related magnetic sensitivity at C3 was 38 mV/V/T, at C2 and C4 it was 14% larger: 43 mV/V/T. We executed the Iv-biasing six-phase offset cancellation scheme and derived the residual offset for 13 samples (see Figure 13). So the spinning scheme basically works.Figure 13
Measured residual offset of 3C-VHalls operated in Iv-biasing six-phase offset cancellation scheme. The devices were actually 5C-VHalls from Figure2 with the outer contacts C1, C5 floating.Comparison of Figures12 and 13 shows a smaller offset for the 3C-VHall. This becomes more evident if we plot the standard deviation of both offsets versus supply voltage in Figure 14. For the 5C-VHall it is 200 μTrms at 0.5 V supply and 550 μTrms at 1 V supply. For the 3C-VHall it is 100 μTrms at 0.5 V and 260 μTrms at 1 V supply. So the measurement indicates that the residual offset of the 5C-VHall is twice the residual offset of the 3C-VHall. At 0.55 V supply the ultralow offset VHall in [9] has 50 μTrms offset, yet it is composed of 16 tubs, whereas the 3C-VHall in Figure 14 is only a single tub. A parallel connection of four 3C-VHalls of Figure 14 has the same internal resistance as the ultralow offset VHall in [9] and is expected to have the same offset, namely, 100/sqrt(4) = 50 μTrms. Factor 10 difference in offset errors reported between the ultralow offset VHall and the fully symmetrical VHall in Table  1 of [9] can be explained by the different number of devices (factor 2) and by the different supply voltage: according to Figure 14 the offset at a supply voltage of 2.44 V is roughly 7 times larger than that at 0.55 V. In [9] the doping concentration is higher and so factor 7 may well reduce to a factor of 5. So it seems that both devices in [9] and our 3C-VHall in Figure 14 show similar residual offset errors at low supply voltage.Figure 14
Standard deviation of the residual offsets of Figures12 and 13.


## 6. Conclusion

The paper discusses Hall plates (HHalls) and Vertical Hall effect devices (VHalls) with only three contacts. Various geometries with smaller or higher degree of symmetry were shown. Hall sensor devices with single tubs were shown as well as arrangements, where several tubs are connected into a ring circuit. Several operating modes of these devices were discussed and their signal-to-noise ratios were compared. Unfortunately, at given input resistance, the signal-to-noise ratio of 3C-Halls is generally smaller than the SNR of conventional 4C-Halls even though 3C-Halls achieve higher voltage related magnetic sensitivity. The equivalent circuit diagram of 3C-Hall comprises only three resistors and two current controlled voltage sources. Numerical simulations of several operating modes suggest that the equivalent circuit correctly predicts the output signals. An offset cancellation scheme for 3C-Halls was studied. The roles of orthogonal and inverse pairs of operating phases were elucidated. Measurement results on the residual offset of symmetric 3C-HHalls and asymmetric 3C-VHalls show that the offset cancellation schemes also work in practice. The residual offset of 3C-HHalls was found to be larger than that of conventional 4C-HHalls. However, the residual offset of 3C-VHalls was found to be smaller than that of conventional 5C-VHalls. A comparison with [9] indicates that, despite fairly different doping level, technology, layout, and wiring of tubs, in silicon single 3C-VHall devices have 100 μTrms residual offset error at 0.5 V supply.In general it was found that unconventional devices like the ones with three contacts shed new light on topics like spinning current schemes and signal-to-noise ratio. Further studies of these devices are likely to bring more aspects to our attention, both in theory and in practice; this paper could touch only on the basic topics of unconventional Hall effect devices.



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*Source: 5625607-2016-04-05.xml*