# An Analytic Model for Estimating the Length of the Velocity Saturated Region in Double Gate Bilayer Graphene Transistors

Authors: M. Saeidmanesh; M. J. Kiani; Kang Eng Siew; E. Akbari; H. Karimi; Razali Ismail
Journal: Journal of Nanomaterials
 (2013)

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## Abstract

An analytical model for surface potential of asymmetric double gate Bilayer Graphene (BLG) transistors is presented on the basis of two-dimensional Poisson’s equation. To verify the accuracy of potential model, the modelling data are compared with the simulation data of FlexPDE program and a good agreement is observed. From surface potential expression, the device behaviour in velocity saturation region is investigated. As a result, lateral electric field and length of velocity saturation region (Ld) are formulated and their dependence on several device parameters is carefully examined.


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## Body

## 1. Introduction

To meet the targets seen by International Technology Roadmap for Semiconductors (ITRS), jointly efforts have been made on proposing new structures and materials for future generation nanoscale Metal-Oxide Field Effect Transistors (MOSFETs). In this regard, carbon base materials such as carbon nanotubs (CNTs) and graphene nanoribbons (GNRs) are known as promising materials for post silicon era because of their excellent electronic properties [1]. While graphene outperforms CNT from a chirality point of view [2], it offers the same interesting electronic properties. For instance, both experimental and theoretical studies show the exceptional high carrier mobility in graphene which promises the graphene based ballistic FETs [3].On the other hand, graphene is a gapless material in its original form. Till now, either narrowing down the graphene to graphene nanoribbon or breaking the symmetry in BLG have been adopted to induce the band gap in the graphene. In BLG, the band-gap is induced by introducing a potential difference between two layers as a result of an external perpendicular electric field [4, 5]. Moreover, the potential difference can be realized with applying different voltages to the top and back gates in double gate MOSFETs which means the band-gap can be controlled by gate bias [6]. Despite the comprehensive studies on electronic properties of BLG, the lack of research on studying its behaviour near the drain junction is felt strongly.Velocity saturation is a common phenomenon in short channel devices. It occurs in the high field region near the drain when the applied voltage to drain contact is higher than the drain saturation voltage [7]. In this region, the carriers are excited to high kinetic energies and scatter frequently. Length of velocity saturation region is an important parameter in nanoscale MOSFETs; it can be used to calculate some other parameters such as effective channel length and lateral breakdown voltage [8], drain current at drain region [9], substrate current, and high electron generation [10]. Although several analytical models have been proposed for saturation region in conventional material [9–15], there is a lack of research on modelling the behaviour of carbon based MOSFETs and especially BLG based MOSFETs in this region. Therefore, in this paper an analytical model is presented for surface potential of asymmetric and double gate BLG based MOSFETs, then lateral electric field and Ld are modelled according to potential distribution model and the effect of several device parameters on them is investigated. To evaluate the accuracy of surface potential model, the FlexPDE Poisson equation solver is employed; the comparisons show good agreement between the modelling and simulation data.The paper is organized as follows. In Section2 the potential distribution along the channel is modelled for proposed structure. Section 3 deals with the analysis of obtained results and illustrations. In Section 4 the main conclusions are drawn.


## 2. 2D Potential Model

A schematic cross section of a double gate BLGFET with the definition of the geometrical characteristics is shown in Figure1. The first and second graphene layers are arranged in AB-stacking [16]. Using the common Poisson’s equation, the potential distribution, Φ(x,y), for any point (x,y) of BLG is given by [14](1)∂2Φ(x,y)∂x2+∂2Φ(x,y)∂y2=q(ND+ni)ɛg,0≤x≤tch,0≤y≤L,
where tch is the BLG channel thickness; ɛg is the dielectric constant of graphene; q is the electron charge; L is the length of BLG channel; ND [in cm-3] is the doping concentration; ni [in cm-3] is the intrinsic carrier concentration of bilayer graphene and is given by [17]
(2)ni=∫0∞‍DoS(E)[f(E-EFS)+f(E-EFD)]dE,
where f(E-EFi)=1/(1+e(E-EFi)/KBT); EFs and EFd are Fermi energies of source and drain, respectively; and DoS is the density of state.Figure 1
Cross view of bilayer graphene double gate transistor.In as much as the strong inversion region, the charge controls the channel potential along they-direction [18, 19]; (1) is valid for weak inversion region where the potential can be approximated by a simple parabolic function along the (x) [20, 21]:(3)Φ(x,y)=P0(y)+P1(y)x+P2(y)x2,
where coefficients P0, P1, and P2 are functions of y only and can be solved by defining the conditions of Φ(0,y)=Φf(y), Φ(tch,y)=Φb(y), and
(4)dΦ(x,y)dx|x=0=ɛoxɛgΦf(y)-Vfg′tox,dΦ(x,y)dx|x=tch=ɛoxɛgVbg′-Φb(y)tox,
where ɛox is the oxide dielectric; Φf(y) and Φb(y) are potential on front and back channel surfaces, respectively; Vfg′=Vfg-Vfb, Vbg′=Vbg-Vfb; Vfg and Vbg are front and back gate voltages; Vfb=ϕm-[(Eg/2)+(KBT/q)ln(ND/ni)] is the flat-band voltage, where ϕm is the metal work function, T is the temperature, and KB is the Boltzmann constant. The coefficients Pi(i=0,1,2) can be determined by applying the boundary conditions of (4) in (3):(5a)P0(y)=Φf(y),(5b)P1(y)=ɛoxɛgΦf(y)-Vfg′tox,(5c)P2(y)=(1+Cox/Cch)Vfg′+Vbg′-(2+Cox/Cch)Φf(y)tch2(1+2Cch/Cox),where Cox=ɛox/tox and Cch=ɛg/tch. Substituting (5a), (5b), and (5c) in (3), one can obtain the potential distribution in every point (x,y) of channel and then the front surface potential can be obtained as
(6)∂2Φf(y)∂2y-αΦf(y)=β,
where(7a)α=2(2+Cox/Cch)tch2(1+2Cch/Cox)+(2tchtoxɛg+ɛoxtch2/ɛgtox)x-(2+Cox/Cch)x2,(7b)β=q(ND+ni)tch2(1+2Cch/Cox)-2(1+Cox/Cch)Vfg′-2Vbg′tch2(1+2Cch/Cox)+(2tchtoxɛg+ɛoxtch2/ɛgtox)x-(2+Cox/Cch)x2.solving (6) with boundary conditions of Φf(0)=Vbi and Φf(L)=Vbi+Vds, where Vbi=VTln(ND/ni) is the built-in potential of the channel-drain and channel-source junctions with VT=KBT/q as thermal voltage, the front gate surface potential along the channel can be given by
(8)Φf(y)=C1exp(αy)+C2exp(-αy)-βα,
where(9a)C1=ϑS-ϑSexp(αL)-ϑDexp(αL)-exp(-αL),(9b)C2=ϑSexp(αL)-ϑDexp(αL)-exp(-αL),(9c)ϑS=βα+Vbi,(9d)ϑD=βα+Vbi+VDS.The surface potential of the device along the drain side of channel for three different values of drain-source voltages is depicted in Figure 2. To verify the accuracy of surface potential model, the FlexPDE Poisson equation solver is utilized within the defined boundary conditions of (4) with tox=1nm, ND=1×1020cm-3, ni=5×1017cm-3, L=20nm, tch=1.3nm, and Vfb=0.2V. The program solves the Poisson’s equation numerically within the defined boundary condition. An excellent agreement is seen between the simulation results and those of the surface potential model given by (8). The accordance between analytical and simulation results shows that the boundary conditions used in FlexPDE are selected properly.Figure 2
The surface potential along the drain side channel length for three different values of drain-source voltages withtox=1 nm, ND=1×1020cm-3, and ni=5×1017cm-3. The solid lines represent modelling results and symbols represent simulation results of FlexPDE.The lateral electric field iny direction of channel is the derivation of (8) and is given by
(10)E(0,y)=α[C1exp(αy)-C2exp(-αy)].
According to the definition of drain saturation voltage, Φf(L-LD)=Vsat, one can solve (8) for Vsat to obtain LD as
(11)LD=1αC1exp(αL)+C2exp(-α(2LD-L))Vsat+β/α,
which can be solved numerically.


## 3. Results and Discussion

In this section, the analytical results of proposed model are presented and compared against the previously published results. Since neither experimental nor simulation data are available forLd and channel electric field of graphene based MOSFETs, the presented model can only be verified by the simulation data of conventional devices. In Figure 3 lateral electric field is plotted as a function of channel length at drain side. It can be seen that by moving toward the drain, the electric field is increased. In particular, the effect of oxide thickness variations on the electric field is shown in Figure 3(a) which indicates that the pick value of electric field is decreased by thick oxide. This result is compatible with that of silicon reported in [15]. In addition, the effect of drain voltage variations on electric filed is depicted in Figure 3(b) where the electric field increases as the drain voltage increases. The effect of drain voltage on electric field is more intensive for the points closer to the drain contact.Lateral electric field along the drain side channel length for different values of: (a) oxide thicknesses withL=20nm, Vds=1V and ND=1×1020cm-3 and (b) drain-source voltages with L=20nm, tox=1nm and ND=1×1020cm-3.
(a)
(b)The length of velocity saturation region is plotted against drain-source voltage and channel length in Figure4. It is evident that Ld increases as drain source and channel length increase, though for the channel longer than 20 nm, the Ld is invariable. Thickening the oxide causes the electric field to increase and hence the Ld also increases as shown in Figure 4(a). Doping concentration has a strong effect on Ld in small drain-source voltages as illustrated in Figure 4(b); however, as ND increases the Ld decreases for all drain source voltages. Finally, the channel length dependence of Ld is depicted in Figure 4(c). It is shown that for long channel devices (e.g., L>20nm) the change of Ld with the channel length is not very significant. On the other hand, this variation is more pronounced for devices with smaller channel length. For the sake of comparison, the presented structure of  [13] is amended and the proposed model is applied on it. Then, the obtained results of si-FET are compared against those of BLG-FET. The comparison shows that the Ld of si-FETs for L>25nm cases increases almost linearly while for BLG-FETs the Ld shows a smaller dependence on channel length.Length of velocity saturation region versus drain-source voltage and channel length for different values of: (a) oxide thicknesses withL=20nm and ND=1×1020cm-3, (b) doping concentrations with L=20nm, and tox=2nm, and (c) drain-source voltages with tox=2nm and ND=1×1020cm-3.
(a)
(b)
(c)


## 4. Conclusion

An analytical model was presented for surface potential of asymmetric double gate BLG transistors on the basis of 2D Poisson’s equation. The surface potential model was verified using FlexPDE Poisson’s equation solver and a good agreement was observed. Furthermore, the device behaviour in saturation velocity region was investigated and lateral electric field and length of velocity saturation region were formulated. In addition, the effect of several device parameters was examined on device behaviour in saturation region. The potential distribution andLd can be useful to providing a physical insight for BLG transistor characteristics analysis.



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*Source: 560252-2013-11-11.xml*