# A Novel Differential Log-Companding Amplifier for Biosignal Sensing

Authors: Zigang Dong; Xiaolin Zhou; Yuanting Zhang
Journal: Journal of Sensors
 (2016)

---

## Abstract

We proposed a new method for designing the CMOS differential log-companding amplifier which achieves significant improvements in linearity, common-mode rejection ratio (CMRR), and output range. With the new nonlinear function used in the log-companding technology, this proposed amplifier has a very small total harmonic distortion (THD) and simultaneously a wide output current range. Furthermore, a differential structure with conventionally symmetrical configuration has been adopted in this novel method in order to obtain a high CMRR. Because all transistors in this amplifier operate in the weak inversion, the supply voltage and the total power consumption are significantly reduced. The novel log-companding amplifier was designed using a 0.18μm CMOS technology. Improvements in THD, output current range, noise, and CMRR are verified using simulation data. The proposed amplifier operates from a 0.8 V supply voltage, shows a 6.3 μA maximum output current range, and has a 6 μW power consumption. The THD is less than 0.03%, the CMRR of this circuit is 74 dB, and the input referred current noise density is 166.1
fA
/
Hz. This new method is suitable for biomedical applications such as electrocardiogram (ECG) signal acquisition.


---

## Body

## 1. Introduction

In recent years, portable and wearable personal healthcare devices have become more and more popular in the world. For these kinds of devices, the biomedical signal acquisition is an important part. The analog amplifier is one of the key building blocks to the signal acquisition unit. Therefore, several requirements such as low power, low noise, low voltage, high total harmonic distortion (THD), and high common-mode rejection ratio (CMRR) are imposed on the amplifier in the biomedical applications. The log-companding technique [1, 2] is a new tool to reduce the amplifier’s supply voltage, the internal voltage dynamic range (DR), and the power consumptions. It is also a good method to solve the trade-off between increasing the signal dynamic range and decreasing the supply voltage [3]. This technique, indeed, provides a practical solution for biomedical applications for its property of low power consumption, especially for the portable and wearable medical devices.For the log-companding technique, the input signal firstly needs to be compressed from the current domain to the voltage domain by logarithmic (log) law. Then, a nonlinear signal processing can be done in the voltage domain. Finally, the processed signal is expanded back to the linear current domain from voltage domain to realize an external linear amplification. The log-companding technique is realized with MOS transistors biased in the subthreshold region for their exponential current versus voltage characteristics which consume very low power.However, this technique has its limitations. For example, the output current range and the signal linearity are difficult to improve because of the property of MOS transistor operating in the weak inversion. To reduce the distortion, the transistors are biased with low currents which will limit the input and output current swings and reduce the signal-to-noise ratio (SNR). Although the biased currents can be improved by enhancing the widths of the transistors, it will increase the power consumption and induce a large parasitic capacitance. Because the differential operation of the conventional differential log-companding amplifier is operating in the current domain [4–7], it is not very effective in improving CMRR and THD for the log-companding technique.In this paper, a novel method is proposed to improve the performance in linearity, CMRR, and low power of the log-companding amplifier by exploiting a nonlinear function and introducing a new differential stage. This method realizes the differential operation between the input signals in the log and linear domains, which is more effective in eliminating the common-mode input signal. A novel nonlinear function is employed to improve the system linearity and extend the output linear range. This paper is organized as follows: the log-companding design technique will be introduced in Section2. In Section 3, the novel log-companding amplifier will be presented. The simulation results will be listed in Section 4, and Section 5 includes the conclusion.


## 2. Log-Companding Design Techniques

### 2.1. Basics of Log-Companding Techniques

For the expanding technique, the input signal in current domain is firstly compressed to voltage domain. Then, a nonlinear process is performed in the voltage domain. Finally, the processed signal is expanded back to the current domain to ensure an external linear function with the input signal. The block diagram of log-companding technique is shown in Figure1 [8].Figure 1
Diagram of log-companding technique.As shown in Figure1, the log-companding technique includes three basic building blocks:I-V compressor F
-
1, nonlinear function, andV-I expander F. Compressor F
-
1 and expander F are used to perform log-compression and log-expansion, respectively, by using a MOS transistor biased in weak inversion region which exactly gives the logarithmic function.According to the EKV model [9],I-V function of a NMOS transistor can be expressed as follows:(1)
I
D
=
I
S
W
L
ln
2
⁡
1
+
e
V
G
B
-
V
T
O
N
-
n
V
S
B
/
2
n
U
t
-
I
S
W
L
ln
2
⁡
1
+
e
V
G
B
-
V
T
O
N
-
n
V
D
B
/
2
n
U
t
I
S
=
2
n
β
U
t
2
,where I
S, n, β, V
T
O
N, and U
t stand for the specific current, subthreshold slope, current factor, threshold voltage, and thermal potential, respectively. V
G
B, V
D
B, and V
S
B are the gate-bulk, drain-bulk, and source-bulk voltage difference, respectively. MOS transistors can operate in three main operating regions which are called weak inversion, moderate inversion, and strong inversion, respectively. Each operating region can be further categorized into three saturation regions which can be called conduction, forward, and reverse saturation, respectively. Under these conditions,I-V (1) can be simplified as follows:(2)
I
D
=
I
S
W
L
e
V
GB
-
V
TON
/
n
U
t
e
-
V
SB
/
U
t
(in weak inversion and forward saturation) and(3)
I
D
=
I
S
W
L
e
V
GB
-
V
TON
/
n
U
t
e
-
V
SB
/
U
t
-
e
-
V
DB
/
U
t
(in moderate inversion and conduction saturation).In the conventional log-companding amplifier, all MOS transistors are biased in weak forward inversion such as in the blocks of compressorF
-
1 and expander F shown in Figure 1, since it exactly gives the logarithmic function. Moreover, the compressor and expander functions are two reciprocal functions to ensure external linear amplification.For the PMOS operating in moderate conduction and weak forward inversion,I-V functions are depicted as follows:(4)
I
D
=
I
S
W
L
e
-
V
GB
-
V
TOP
/
n
U
t
e
V
SB
/
U
t
-
e
V
DB
/
U
t
(in moderate inversion and conduction saturation) and(5)
I
D
=
I
S
W
L
e
-
V
GB
-
V
TOP
/
n
U
t
e
V
SB
/
U
t
(in weak inversion and forward saturation).


### 2.2. Conventional Log-Companding Amplifiers

The main purpose of every amplifier is to obtain a linearly scaled copy of the input signal at the output port. In other words, the input signal is multiplied by a gain factor to yield the output signal. For the log-companding amplifier, however, this step is accomplished by adding a gain factor to the compression signal in the log region that is translated from the input signal by the log law, which corresponds to the part of nonlinear function in Figure1. The general CMOS implementation of the log-companding amplifier topology is shown in Figure 2 [3].Figure 2
The general log-companding amplifier topology (auxiliary circuitry in dashed line).


## 2.1. Basics of Log-Companding Techniques

For the expanding technique, the input signal in current domain is firstly compressed to voltage domain. Then, a nonlinear process is performed in the voltage domain. Finally, the processed signal is expanded back to the current domain to ensure an external linear function with the input signal. The block diagram of log-companding technique is shown in Figure1 [8].Figure 1
Diagram of log-companding technique.As shown in Figure1, the log-companding technique includes three basic building blocks:I-V compressor F
-
1, nonlinear function, andV-I expander F. Compressor F
-
1 and expander F are used to perform log-compression and log-expansion, respectively, by using a MOS transistor biased in weak inversion region which exactly gives the logarithmic function.According to the EKV model [9],I-V function of a NMOS transistor can be expressed as follows:(1)
I
D
=
I
S
W
L
ln
2
⁡
1
+
e
V
G
B
-
V
T
O
N
-
n
V
S
B
/
2
n
U
t
-
I
S
W
L
ln
2
⁡
1
+
e
V
G
B
-
V
T
O
N
-
n
V
D
B
/
2
n
U
t
I
S
=
2
n
β
U
t
2
,where I
S, n, β, V
T
O
N, and U
t stand for the specific current, subthreshold slope, current factor, threshold voltage, and thermal potential, respectively. V
G
B, V
D
B, and V
S
B are the gate-bulk, drain-bulk, and source-bulk voltage difference, respectively. MOS transistors can operate in three main operating regions which are called weak inversion, moderate inversion, and strong inversion, respectively. Each operating region can be further categorized into three saturation regions which can be called conduction, forward, and reverse saturation, respectively. Under these conditions,I-V (1) can be simplified as follows:(2)
I
D
=
I
S
W
L
e
V
GB
-
V
TON
/
n
U
t
e
-
V
SB
/
U
t
(in weak inversion and forward saturation) and(3)
I
D
=
I
S
W
L
e
V
GB
-
V
TON
/
n
U
t
e
-
V
SB
/
U
t
-
e
-
V
DB
/
U
t
(in moderate inversion and conduction saturation).In the conventional log-companding amplifier, all MOS transistors are biased in weak forward inversion such as in the blocks of compressorF
-
1 and expander F shown in Figure 1, since it exactly gives the logarithmic function. Moreover, the compressor and expander functions are two reciprocal functions to ensure external linear amplification.For the PMOS operating in moderate conduction and weak forward inversion,I-V functions are depicted as follows:(4)
I
D
=
I
S
W
L
e
-
V
GB
-
V
TOP
/
n
U
t
e
V
SB
/
U
t
-
e
V
DB
/
U
t
(in moderate inversion and conduction saturation) and(5)
I
D
=
I
S
W
L
e
-
V
GB
-
V
TOP
/
n
U
t
e
V
SB
/
U
t
(in weak inversion and forward saturation).


## 2.2. Conventional Log-Companding Amplifiers

The main purpose of every amplifier is to obtain a linearly scaled copy of the input signal at the output port. In other words, the input signal is multiplied by a gain factor to yield the output signal. For the log-companding amplifier, however, this step is accomplished by adding a gain factor to the compression signal in the log region that is translated from the input signal by the log law, which corresponds to the part of nonlinear function in Figure1. The general CMOS implementation of the log-companding amplifier topology is shown in Figure 2 [3].Figure 2
The general log-companding amplifier topology (auxiliary circuitry in dashed line).


## 3. Novel Log-Companding Amplifier

The proposed differential log-companding amplifier consists of four main parts including a compressor, a differentiator, a processor, and an expander [10]. The compressor is employed to logarithmically compress the input current signal into voltage signal. The differentiator is used to compare the difference between the two input current signals in voltage domain; the processer will process the nonlinear signal to improve the CMRR and THD. The expander will convert the voltage signal back to the current signal using log law to maintain external linear amplification.


### 3.1. Compressor

The compressor is shown in Figure3, where i
1 and i
2 are the input current. All of the MOS transistors in this schematic are biased in weak forward saturation. From (2) and Figure 4, we can get the following:(6)
I
1
-
I
2
=
i
1
-
i
2
I
1
+
I
2
=
I
b
=
I
s
W
L
N
3
e
V
b
-
V
TON
/
n
U
t
I
1
=
I
s
W
L
N
1
e
V
X
B
-
V
TON
/
n
U
t
e
-
V
SB
/
n
U
t
I
2
=
I
s
W
L
N
2
e
V
Y
B
-
V
TON
/
n
U
t
e
-
V
SB
/
n
U
t
I
1
-
I
2
I
1
+
I
2
=
i
1
-
i
2
I
b
=
I
1
/
I
2
-
1
I
1
/
I
2
+
1
=
e
V
X
Y
/
n
U
t
-
1
e
V
X
Y
/
n
U
t
+
1
=
tanh
⁡
V
X
Y
2
n
U
t
.Figure 3
The diagram of compressor.Figure 4
The diagram of differentiator.Therefore,(7)
i
1
-
i
2
=
I
b
tanh
⁡
V
X
Y
2
n
U
t
,where I
b is the quiescent operating current which will fix the input circuit operating point and control the amplifier’s gain by tuning its value.


### 3.2. Differentiator

As shown in Figure4, V
ref is a biased voltage that is provided by the biased circuit (it is not shown in this paper) to bias the MOS P
1, P
7 in weak forward inversion. V
dm is the output of differentiator.Suppose that the MOS transistors are biased in weak forward inversion; recalling (2) and (5), we can get(8)
V
X
Y
=
V
dm
-
V
ref
(9)
i
1
-
i
2
=
I
b
tanh
⁡
V
dm
-
V
ref
2
n
U
t
.The differentiator plays an important role in getting a high CMRR since the differential operation in the voltage domain.


### 3.3. Nonlinear Convertor and Expander

The basic nonlinear processor is shown in Figure6. The circuit converts the input signal V
dm from voltage domain to current domain by MOS P
7 for conveniently tuning the signal. The current mirror involves two pairs of composite MOS transistors N
12 and N
13, respectively. MOS transistors P
8, P
9, and N
16 expand the current signal back to voltage domain and complete signal V
dm nonlinear conversion to ensure linear amplification.Suppose thatP
8 operates in weak forward saturation and the others in Figure 5 operate in weak inversion; according to (5), the drain current of P
7 can be written as(10)
I
=
I
s
W
L
P
7
e
-
V
dB
+
V
TOP
/
n
U
t
,where(11)
V
B
=
V
DD
.Figure 5
The diagram convertor and expander.Figure 6
The current bias.According to (4) and (5) and assuming that the supply voltage is enough to saturate transistor P
9, the current and voltage expressions of P
8 and P
9 can be given by(12)
I
bias
=
I
s
W
L
P
9
e
-
V
OB
+
V
TOP
/
n
U
t
e
V
SB
/
n
U
t
(13)
I
bias
+
I
=
I
s
W
L
P
8
e
-
V
OB
+
V
TOP
/
n
U
t
1
-
e
V
SB
/
n
U
t
.From (10)–(13), we can get(14)
1
+
W
/
L
P
8
W
/
L
P
9
I
bias
+
I
s
W
L
P
7
e
-
V
dB
+
V
TOP
/
n
U
t
=
I
s
W
L
P
8
e
-
V
OB
+
V
TOP
/
n
U
t
.Multiplye
V
ref
/
n
U
t by both sides of (14), rearranged to give(15)
I
s
W
L
P
8
e
V
ref
-
V
O
/
n
U
t
-
I
s
W
L
P
7
e
V
ref
-
V
dm
/
n
U
t
=
1
+
W
/
L
P
8
W
/
L
P
9
I
bias
e
-
V
DD
+
V
TOP
-
V
ref
/
n
U
t
.Let(16)
M
=
1
+
W
/
L
P
8
/
W
/
L
P
9
I
bias
I
s
e
-
V
DD
+
V
TOP
-
V
ref
/
n
U
t
.Equation (15) can be written as(17)
e
V
dm
-
V
ref
/
n
U
t
=
W
/
L
P
7
/
W
/
L
P
8
e
V
O
-
V
ref
/
n
U
t
1
-
M
/
W
/
L
P
8
e
V
O
-
V
ref
/
n
U
t
.Then, let us take a look at the following function:(18)
e
2
x
=
f
1
-
f
.Solving (18) for f, this yields(19)
f
=
tanh
⁡
x
+
1
e
2
x
+
1
.In most practical cases, the second term of the right hand of (19) is much less than the first. For example, if n
=
1.2, U
t
=
26 mv, V
dm
=
0, V
ref
=
400 mv, calculated to give(20)
Δ
=
1
e
V
ref
-
V
dm
/
n
U
t
+
1
≈
2.7
×
1
0
-
6
.For this reason, assuming that(21)
M
=
W
L
P
7and combining (9), (17), (18), and (19), we find(22)
i
1
-
i
2
=
I
b
W
/
L
P
7
W
/
L
P
8
e
V
O
-
V
ref
/
n
U
t
.From (2) and (22), the output current is given by(23)
i
o
=
W
/
L
P
8
W
/
L
N
17
W
/
L
P
7
W
/
L
N
3
e
V
ref
-
V
b
/
n
U
t
i
1
-
i
2
.Recalling (16) and (21), the biasing current can be expressed as(24)
I
bias
=
I
s
W
/
L
P
7
W
/
L
P
9
W
/
L
P
8
+
W
/
L
P
9
e
V
DD
+
V
TOP
-
V
ref
/
n
U
t
,whereI
bias is implemented as shown in Figure 6.Although the derivation of (23) is based on the assumption that all MOS transistors operate in weak forward inversion, it can also keep the performance of the proposed amplifier when P
7, P
8, and P
9 operate in moderate inversion.


## 3.1. Compressor

The compressor is shown in Figure3, where i
1 and i
2 are the input current. All of the MOS transistors in this schematic are biased in weak forward saturation. From (2) and Figure 4, we can get the following:(6)
I
1
-
I
2
=
i
1
-
i
2
I
1
+
I
2
=
I
b
=
I
s
W
L
N
3
e
V
b
-
V
TON
/
n
U
t
I
1
=
I
s
W
L
N
1
e
V
X
B
-
V
TON
/
n
U
t
e
-
V
SB
/
n
U
t
I
2
=
I
s
W
L
N
2
e
V
Y
B
-
V
TON
/
n
U
t
e
-
V
SB
/
n
U
t
I
1
-
I
2
I
1
+
I
2
=
i
1
-
i
2
I
b
=
I
1
/
I
2
-
1
I
1
/
I
2
+
1
=
e
V
X
Y
/
n
U
t
-
1
e
V
X
Y
/
n
U
t
+
1
=
tanh
⁡
V
X
Y
2
n
U
t
.Figure 3
The diagram of compressor.Figure 4
The diagram of differentiator.Therefore,(7)
i
1
-
i
2
=
I
b
tanh
⁡
V
X
Y
2
n
U
t
,where I
b is the quiescent operating current which will fix the input circuit operating point and control the amplifier’s gain by tuning its value.


## 3.2. Differentiator

As shown in Figure4, V
ref is a biased voltage that is provided by the biased circuit (it is not shown in this paper) to bias the MOS P
1, P
7 in weak forward inversion. V
dm is the output of differentiator.Suppose that the MOS transistors are biased in weak forward inversion; recalling (2) and (5), we can get(8)
V
X
Y
=
V
dm
-
V
ref
(9)
i
1
-
i
2
=
I
b
tanh
⁡
V
dm
-
V
ref
2
n
U
t
.The differentiator plays an important role in getting a high CMRR since the differential operation in the voltage domain.


## 3.3. Nonlinear Convertor and Expander

The basic nonlinear processor is shown in Figure6. The circuit converts the input signal V
dm from voltage domain to current domain by MOS P
7 for conveniently tuning the signal. The current mirror involves two pairs of composite MOS transistors N
12 and N
13, respectively. MOS transistors P
8, P
9, and N
16 expand the current signal back to voltage domain and complete signal V
dm nonlinear conversion to ensure linear amplification.Suppose thatP
8 operates in weak forward saturation and the others in Figure 5 operate in weak inversion; according to (5), the drain current of P
7 can be written as(10)
I
=
I
s
W
L
P
7
e
-
V
dB
+
V
TOP
/
n
U
t
,where(11)
V
B
=
V
DD
.Figure 5
The diagram convertor and expander.Figure 6
The current bias.According to (4) and (5) and assuming that the supply voltage is enough to saturate transistor P
9, the current and voltage expressions of P
8 and P
9 can be given by(12)
I
bias
=
I
s
W
L
P
9
e
-
V
OB
+
V
TOP
/
n
U
t
e
V
SB
/
n
U
t
(13)
I
bias
+
I
=
I
s
W
L
P
8
e
-
V
OB
+
V
TOP
/
n
U
t
1
-
e
V
SB
/
n
U
t
.From (10)–(13), we can get(14)
1
+
W
/
L
P
8
W
/
L
P
9
I
bias
+
I
s
W
L
P
7
e
-
V
dB
+
V
TOP
/
n
U
t
=
I
s
W
L
P
8
e
-
V
OB
+
V
TOP
/
n
U
t
.Multiplye
V
ref
/
n
U
t by both sides of (14), rearranged to give(15)
I
s
W
L
P
8
e
V
ref
-
V
O
/
n
U
t
-
I
s
W
L
P
7
e
V
ref
-
V
dm
/
n
U
t
=
1
+
W
/
L
P
8
W
/
L
P
9
I
bias
e
-
V
DD
+
V
TOP
-
V
ref
/
n
U
t
.Let(16)
M
=
1
+
W
/
L
P
8
/
W
/
L
P
9
I
bias
I
s
e
-
V
DD
+
V
TOP
-
V
ref
/
n
U
t
.Equation (15) can be written as(17)
e
V
dm
-
V
ref
/
n
U
t
=
W
/
L
P
7
/
W
/
L
P
8
e
V
O
-
V
ref
/
n
U
t
1
-
M
/
W
/
L
P
8
e
V
O
-
V
ref
/
n
U
t
.Then, let us take a look at the following function:(18)
e
2
x
=
f
1
-
f
.Solving (18) for f, this yields(19)
f
=
tanh
⁡
x
+
1
e
2
x
+
1
.In most practical cases, the second term of the right hand of (19) is much less than the first. For example, if n
=
1.2, U
t
=
26 mv, V
dm
=
0, V
ref
=
400 mv, calculated to give(20)
Δ
=
1
e
V
ref
-
V
dm
/
n
U
t
+
1
≈
2.7
×
1
0
-
6
.For this reason, assuming that(21)
M
=
W
L
P
7and combining (9), (17), (18), and (19), we find(22)
i
1
-
i
2
=
I
b
W
/
L
P
7
W
/
L
P
8
e
V
O
-
V
ref
/
n
U
t
.From (2) and (22), the output current is given by(23)
i
o
=
W
/
L
P
8
W
/
L
N
17
W
/
L
P
7
W
/
L
N
3
e
V
ref
-
V
b
/
n
U
t
i
1
-
i
2
.Recalling (16) and (21), the biasing current can be expressed as(24)
I
bias
=
I
s
W
/
L
P
7
W
/
L
P
9
W
/
L
P
8
+
W
/
L
P
9
e
V
DD
+
V
TOP
-
V
ref
/
n
U
t
,whereI
bias is implemented as shown in Figure 6.Although the derivation of (23) is based on the assumption that all MOS transistors operate in weak forward inversion, it can also keep the performance of the proposed amplifier when P
7, P
8, and P
9 operate in moderate inversion.


## 4. Simulation Results

The differential log-companding amplifier is designed in a standard 0.18μm CMOS technology. The supply voltage is 0.8 V and the bias voltage V
b is 320 mv. Note that the amplifier’s gain can be controlled by voltage V
b. Because all the aforementioned deductions are based on the EKV model, the design adopts the EKV model from the foundry in the following simulations to verify the analytical conclusions.The output current changes from 0.23μA to 13.6 μA when the input current varies from −20 nA to 20 nA as shown in Figure 7. The transient response of the output current is shown in Figure 8 with a sinusoidal input signal of 10 kHz frequency and 20 nApp peak-to-peak amplitude. Figure 9 shows the frequency response of the amplifier. The CMRR of log-companding amplifier is up to 73 dB using two stages of the differential structures shown in Figures 3 and 4. The THD of the proposed circuit is less than 0.03% at the maximum output as illustrated in Figure 10.Figure 7
The output current curve with a varied input current.Figure 8
Transient response of output current of the amplifier.Figure 9
Frequency response of the amplifier.Figure 10
The distribution of THD with respect to the gain current.Considering that THD and CMRR are influenced by the device mismatch, the result of Monte Carlo simulation is provided as shown in Figure11. THD is more than 80 dB and has a satisfactory result, CMRR is almost more than 72 dB and a very few points degrade. Figure 12 gives the comparison between the simulated gains and the predicted gain according to (24). The figure shows a good estimation.Figure 11
The Monte Carlo simulation.Figure 12
The amplifier gain curve with a variedV
b.The corner simulation results are shown in Table1, which exhibit a good capability of operating in the real circumstance. Three corner simulations are different in temperature and same in voltage supply. Open loop gains vary only 5 dB in the range of different corners. 3 dB frequency has poor value in the worst case but it is acceptable for biosignal sensing application. They all have a good performance in THD and CMRR.Table 1
The corner simulation results.
Typical
Worst case
Best case
MOS model
Typical
Fast
Slow
Temperature (°C)
27
0
80
Voltage supply (V)
0.8
0.8
0.8
Open loop gain (dB)
50
51.7
46.8
3 dB frequency (kHz)
510
340
850
Maximum input range (nApp)
20
10
46
Maximum output swing (μApp)
6.3
2.58
10
THD@maximum output swing (%)
0.028
0.056
0.03
CMRR (dB)
73
77.8
64.2Table2 displays the performance comparison with other design methods. They employed the same current-mode topology and work below the voltage supply 1 V. This work has the least power consumption only 6 μW and the best input dynamic range 92.9 dB. The proposed amplifier in this paper shows the lowest THD and the highest CMRR. Furthermore, it also shows excellent performance in low supply voltage and low power consumption.Table 2
Performance comparison with other works.
This work
[11]
[4]
[8]
Technology
0.18μm CMOS
0.18μm CMOS
0.25μm CMOS
—
Topology
Current mode
Current mode
Current mode
Current mode
Supply voltage (V)
0.8
1
0.6
1
Open gain (dB)
50 dB
44.5/50/55.9
−40 to 38
−40 to +40
Bandwidth (Hz)
510 k
0.3~1 k~10 k
200 k
—
Input referred noise density (fA/sqrt (Hz))
166.1 fA (@10 kHz)
153 fA (@10 kHz)
—
—
Maximum input current (nApp)
20
20
—
—
Input dynamic range (dB)
92.9
53.29
—
—
Power consumption (μW)
6
13
3.16
25
CMRR (dB)
74
—
35.76
—
THD@maximum input (%)
0.0287@50 dB
1.03
0.55
0.6


## 5. Conclusions

A novel high linearity, low power, and high CMRR differential log-companding amplifier is introduced in this work. The amplifier is designed in a standard 0.18μm CMOS technology with excellent linearity, high CMRR, and low power consumption. With the new nonlinear function used in the log-companding technology, the proposed amplifier has a very small THD and simultaneously a wide output current range. Furthermore, a differential structure with conventionally symmetrical configuration has been adopted in the novel method in order to obtain a high CMRR. The voltage supply is 0.8 V, the power consumption is 6 μW, and the THD is less than 0.03% at the maximum input. The CMRR of this circuit is 74 dB and the input referred current noise density is 166.1
fA
/
Hz. It can be used in biomedical signal processing to decrease total power consumption, to ensure the signal linearity, and to eliminate common-mode noise. In conclusion, this technique can be used to design log-companding amplifier for many portable and wearable personal healthcare applications.



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*Source: 5358963-2016-09-19.xml*