# Oscillation-Based Test Applied to a Wideband CCII

Authors: Pablo Petrashin; Luis Toledo; Walter Lancioni; Piotr Osuch; Tinus Stander
Journal: VLSI Design
 (2017)

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## Abstract

Oscillation-based testing (OBT) has been proven to be a simple, yet effective VLSI test for numerous circuit types. This paper investigates, for the first time, the application of OBT verification for second generation current conveyors (CCIIs). The OBT is formed by connecting the CCII into a simple Wien bridge oscillator and monitoring both the amplitude and frequency of oscillation. The fault detection rate, taking into account both the open and short circuit fault simulation analyses, indicates 96.34% fault coverage using a combination of amplitude and frequency output sensing in all technology corners. The only nondetected faults are short circuits betweenVDD and VSS, which can be detected using other techniques such as IDDQ testing. This method is found to be sensitive to resistor and capacitor process variation in the Wien bridge oscillator, but mitigating test steps are proposed.


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## Body

## 1. Introduction

Despite the digital implementation of modern communication subsystems, analog front-ends and active filters are still used extensively in mixed-signal ICs. The second generation current conveyor (CCII) is an adaptable multifunction component that can be applied in a large number of analog circuits (such as active continuous time filters and all-pass networks) and has been the subject of intensive study for the last decade [1–4]. Most CCII-based circuits use only all-transistor CCIIs, resistors, and capacitors, making their use attractive compared to large on-chip inductors. Additionally, the component count of these structures is usually very low, further decreasing the area cost [1].Given the prominent role CCIIs play in integrated systems, it would be prudent to define explicit test procedures for individual CCII elements as part of larger VLSI production testing. Due to large CMOS process tolerances as well as potential failure points, a nonintrusive testing procedure using a minimal number of input and output test vectors is necessary, especially in mass produced telecommunication systems on chip (SOC). Excellent reviews of analog IC testing can be found in [5, 6], highlighting various simulation-before-test and simulation-after-test techniques. It is, however, evident that most of these tests require multiple complex text vectors and swept DC or AC inputs. Some attempt at a formalized test of a CCII was made in [7], but the procedure is not exhaustive and the conclusions are not generally applicable. It depends significantly on the configuration used and on a very singular fault-set selection. The method requires sweeping an input voltage between a given range, making the procedure difficult to implement. As the method is analog, it is further complicated by the read-out (faulty/nonfaulty) of the produced test result.In contrast, the oscillation-based test (OBT) technique, introduced in the early 1990s [8], is a vectorless technique that can be used either in offline testing or as the core of the so-called OBIST (Oscillation-Based Built-In-Self-Test). The principle of OBT is to convert the circuit under test (CUT) into an oscillator during the test phase by adding a feedback loop (either globally to the total CUT or locally to specific parts of it) to produce self-sustained oscillation monitored at an output. Faulty behavior is then indicated by deviation from the fault-free operation in either the frequency or the amplitude of the oscillations [9]. This method has been used extensively for operational amplifiers, filters, and data converters [8–10]. The benefit of this approach is that a single test (with a single output and no input vector) can detect multiple problems, thus reducing the number of test points and probe pads. OBT, therefore, avoids the problem of test vector generation, requires relatively simple and few measurement vectors, and generally does not require intrusive circuit modification during the testing phase. These characteristics make OBT an appealing strategy.In this work, we evaluate the suitability of OBT for testing CCIIs for the first time and develop a novel test procedure for CCIIs accordingly by making use of the linear characteristics in the feedback loop. The procedure is evaluated through fault simulation and fault coverage.


## 2. Circuit under Test

Among the numerous implementations available for CCII circuits in literature [1–4, 11] a positive Type II current conveyor is adopted and implemented in the AMS C35 0.35 μm CMOS process [12], as shown in Figure 1. The transistor sizing for the elements of Figure 1 is shown in Table 1.Table 1
Transistor sizing for the circuit under test.
Device name
W
/
L (μm)
M1, M2
14/0.35
M3, M4
37,8/0.35
Mxx PMOS
19/0.35
Mxx NMOS
7/0.35Figure 1
CCII circuit under test.In Figures2 and 3 the output voltage as a function of frequency and its corresponding DC transfer characteristic with IREF fixed to 10 μA are shown, respectively.Figure 2
Output voltage and phase transfer characteristic.Figure 3
DC transfer characteristic.


## 3. OBT Implementation

In order to perform an OBT on the circuit, the CUT must be placed into a self-sustained oscillation condition. The implementation of the OBT depends heavily on the characteristics of the system under test. The oscillator has to be designed and implemented based upon several considerations, such as the characteristics of the system, the possibility of partitioning the CUT, the observable outputs, and the analog or digital nature of the signal. Consequently, the application of this strategy to each new class of circuits becomes a challenging task. Here, we apply the CCII as the gain element in a simple Wien bridge oscillator [13] as shown in Figure 4.Figure 4
A voltage mode Wien bridge oscillator using a CCII+.A number of additional components are required to switch the CCII into an oscillator test circuit. Since the CCII only has three terminals, this is easily accomplished by 3 pairs of switches, shown as SW1, SW2, and SW3 in Figure4. In this way, the CUT itself is not modified to establish an oscillating output, making the OBT integration minimally invasive and, therefore, limiting the signal degradation in normal operating mode. The selection of signal path switches with adequate electrical performance is critical, as these remain connected to the CUT in both OBT and normal operating modes. The switches should be chosen to have on and off characteristics as close to the ideal (short circuits and open circuits, resp.) as possible.In Figure4, SW1, SW2, and SW3 are controlled by test signal T, which isolates the CUT from the rest of the circuit and connects it to the testing circuitry and test output in order to perform the test.The resonant condition of this oscillator circuit is given by(1)s2C1C2R1R2+sC1R1+C2R2+C1R2R1-R42R3+1+R22R3.For the sake of simplicity, the selectionsC1=C2=C and R1=R2=R3=R are made. With this simplification, the oscillation frequency can be calculated as(2)ω0=321CR.Figure5 shows the output waveform of the CCII-based oscillator with C=0.2 μF and R=10 kΩ. IREF is kept at 10 μA as before. Under these conditions, the circuit reaches a final, stable oscillating condition within 1.5 ms at f0=75 kHz with ±35 m Vpp output swing. This will be the comparison reference when simulating faults. Selecting different values of R and C do not affect the test procedure (or coverage) other than changing the nominal value of f0.Figure 5
Oscillator output waveform of the operational (without faults) circuit.The conventional OBT procedure is applied [14], whereby the circuit is switched into this oscillating condition and its output voltage amplitude and oscillation frequency are compared to that of the nonfaulty output in Figure 5.


## 4. Fault Modeling

Traditionally, the efficiency of OBT has been evaluated at a structural level by using single-catastrophic and single-deviation fault models. In this way, it is possible to use the well-known metric of fault coverage for qualifying the test.In this work, we focus on catastrophic faults at both device and circuit level, thereby evaluating the efficiency of OBT for the faults that may cause severe failures in the circuit. Working from the schematic, an exhaustive fault list is generated, considering only catastrophic faults. This fault list includes all possible open and short circuit faults of transistors, with only the gate contact open fault omitted from analysis. The analysis is further extended to short faults at the circuit level. This extends the fault coverage to all probable faults and allows comparisons with other published results.The CUT has 11 nodes, as numbered in Figure1, with the schematically redundant ones listed in Table 2. The reference node and its schematically redundant subnodes are connected at the same potential, making it impossible to detect behavioral differences between them. For this reason, only the reference nodes of Table 2 (with the suffix “S,” “D,” or “G” in the node names referring to the source, drain, or gate, resp.) are considered for short fault simulations. In this way, we consider 527 potential short circuit faults (considering all redundant nodes) and 26 open circuit faults (considering only drain and source contacts on the transistors).Table 2
List of main and redundant nodes.
Reference node
Redundant nodes
1
M10_S, M9_S, M8_S, M7_S
2
M13_S, M12_S, M11_S, M5_S, M6_S
3
M13_D, M13_G, M12_G, M11_G
4
M10_D, M9_G, M10_G
5
M1_D, M1_G, M2_G
6
M1_S, M3_S
7
M2_S, M4_S
8
M7_D, M6_D
9
M3_D, M3_G, M4_G
10
M10_D, M10_G, M6_G
11
M8_D, M8_G, M7_GSchematically redundant subnodes are, of course, not physically redundant nodes, as the CUT may produce different outputs for open faults at different schematically redundant nodes. Therefore, for open faults, all nodes in this table are considered, excluding the gate open contact fault as is pointed out previously.Fault simulations are carried out using SPICE, with the technology rules of AMS C35 process.As the CUT has tuning capability through variation of IREF, parameter drift of nominal TT (Typical, Typical) conditions is usually compensated for postproduction. Under these conditions, the fault coverage for only the TT operating case would be representative of devices operating anywhere within the four corners (FF, FS, SF, and SS). However, tuning each CUT before testing could be, in some cases, excessively time consuming and thus impractical for exhaustive application. One way to avoid this time loss is simply to perform the test without tuning the circuit (though tuning or prior characterization ofR and C in the OBT may be necessary, as discussed in Section 5). In order to prove the effectiveness of this idea, the test coverage is evaluated in simulation for all five cases (TT, FF, FS, SF, and SS) in Table 3, for a fixed IREF=10 μA, using as reference for percentage calculation of the amplitude and frequency of the nonfaulty oscillation circuit with TT parameters. This is done to ensure, firstly, that circuits with acceptable parametric drift are not incorrectly detected as faulty and, secondly, that faulty circuits with acceptable parametric drift are still rejected by the OBT. Corner analysis is opted for, as opposed to Monte Carlo analysis, as it has been shown to identify more extreme variation from nominal operating conditions associated with interdie process variation than what is produced by a typical Monte Carlo analysis (which is more suited for intradie variation) [15–17].Table 3
Short circuit fault results for all the five technology corners.
Tech corner
N1-N2
N4–N11
N6–N8
Δ
f (%)
Δ
V
p
p (%)
Δ
f (%)
Δ
V
p
p (%)
Δ
f (%)
Δ
V
p
p (%)
FF
2,05%
−8,69%
21,11%
185,35%
−3,42%
240,96%
FS
0,27%
39,42%
23,84%
154,12%
−3,40%
200,16%
SF
1,13%
−56,43%
16,83%
159,10%
−6,37%
211,71%
SS
−2,47%
0,71%
20,04%
129,33%
−5,69%
171,85%
TT
0,53%
−0,55%
20,94%
158,88%
−4,24%
207,59%As has been proposed in previous literature on OBT [8–10, 14] open circuit faults are modeled by a 10 MΩ resistor, while short circuit faults are modeled by a 10 Ω resistor. It is assumed here that a fault is detected when the oscillation frequency or amplitude falls outside of a tolerance band of ±5% from the nominal values simulated in the TT case. This is in keeping with the state-of-the-art in OBT techniques [14] and also allows for nonfaulty FF (which features a +2,39% increase in f0 compared to the TT simulated case), FS (−0,34% f0 compared to the TT), SF (+1,01%), and SS (−2,28%) circuits to pass the test.Table3 presents the simulation results for short circuit faults that do not result in a loss of oscillation output altogether, as was the case with all open circuit faults. It should be noted that only one fault of each schematically redundant fault set is presented. In this way, all injected faults giving a nonoscillating condition are not presented in this table, and thus the corresponding faults are considered to be detected. The open circuit faults table is not presented because all these faults are detected through complete loss of oscillation.From Table3, the remarkable efficiency of OBT applied to this circuit becomes evident. Of the 527 injected faults, only a few (short circuits between VDD and VSS) are not observable in the test. This is shown to be true, not only for the TT case, but also for all technology corners. This particular fault can, however, easily be detected with a simple IDDQ test. Furthermore, with the exception of VDD-VSS short circuit, all faults are detectable with amplitude measurement alone. It should be noted that some works [7] exclude from the fault list those faults that are known to be nondetectable with the methodology used. If the same principle is applied here and VDD-VSS short circuit faults are excluded from analysis, 100% fault coverage could be claimed. It is further noted that the oscillation outputs (f0 and Vpp) of a faultless CUT are within the allowable ±5% variation under all operating corners.


## 5. Process Variation inR and C

In the preceding discussion, the method was shown to operate across all NMOS and PMOS corner variations of the all-transistor CUT, assuming perfect knowledge ofR and C used in the attached Wien bridge oscillator. To analyse the impact of RC process variation on test coverage, a corner variation simulation of the RC components with a nominal-corner CUT is performed, with the resulting variation of f0 and Vpp as shown in Figures 6 and 7.Figure 6
Center frequency variation for various process corner variations ofRC.Figure 7
V
p
p variation for various process corner variations ofRC.These results indicate that a circuit operating in one of the nonnominalRC process corners would invalidate the test coverage in Table 3, as a large percentage of correctly operating circuits would produce f0 or Vpp outside the ±5% variation threshold.It is, however, evident from our preceding analysis that the OBT method is agnostic to the specific values off0 or Vpp, rather relying on known nominal values as determined by the specific RC corner. Knowledge of this corner (which may be readily obtained by including probed R and C measurements, as is already commonly done in CMOS fabrication) is sufficient to recalibrate the nominal operating conditions and boundary thresholds for the OBT test.Alternatively,R and C may be made tunable by using triode-region and varactor MOS devices, respectively. After tuning the RC constant to the desired value, the OBT test procedure can be carried out as described.


## 6. Evaluation of Short Circuit and Open Circuit Impedance Values

The state-of-the-art in OBT testing [8–10, 14] uses 10 Ω resistors to represent short circuit faults and 10 MΩ resistors to represent open circuit faults. As open and short circuits on-chip may assume a wide variety of impedance values [18], it would be prudent to analyse the effect of substituted impedance value variation on the OBT technique.To validate these substituted impedance choices, two representative faults (one a short circuit between N6 and N8 and one an open circuit at the drain of M1) are simulated in the TT technology corner, for various resistance choices, as shown in Figures8 and 9.Figure 8
Center frequency and peak-to-peak variation for various choices of short fault resistances for circuit fault N6–N8.Figure 9
Center frequency and peak-to-peak variation for various choices of open fault resistances for circuit fault drain of open circuited M1.The measured outputsf0 and Vpp show no variation for short circuit representations as high as 1 kΩ, two orders of magnitude higher than the selected value of 10 Ω. Similarly, the nonoscillating faulty circuit only resumes oscillation if the open circuit fault impedance is reduced to below 100 kΩ, two orders of magnitude lower than the selected value of 10 MΩ. It is clear, from these analysis, that the OBT test coverage remains valid for a wide range of actual fault impedances on-chip.


## 7. Conclusions

An OBT scheme has been applied to a CCII+ circuit for the first time. For evaluating OBT in this context, we adopted catastrophic fault models at both device and circuit level. The fault simulation results show 96.34% fault coverage that could be improved to achieve 100% by including additional IDDQ testing. This is consistent with other works [7] but with much easier implementation. It is also shown that OBT can correctly detect faults and pass nonfaulty circuits in all five CMOS technology corners, without the need of tuning the circuit, strongly simplifying the procedure by reducing the testing time. It is further shown that the previously applied 10 Ω and 10 MΩ impedance values to represent short circuits and open circuits are “safe” choices, with the OBT only suffering from degraded accuracy for short circuit impedances of above 1 kΩ or open circuit impedances below 100 kΩ.The method is, however, shown to be sensitive to process variation in the values ofR and C used in the Wien bridge oscillator. This can be mitigated by establishing a priori knowledge of the R and C process corners through measurement and recalibrating the nominal test values of f0 and Vpp accordingly without loss of test coverage. The problem may be circumvented altogether by incorporating a tunableRC feedback network into the OBT circuit, though this would increase the test complexity and cost.Future work will include comparison of the fault coverage in different CCII-based oscillators with respect to component count, fault coverage, and influence on nominal operating conditions. Replacing the sinusoidal output with a Schmitt trigger oscillator [1] will also be investigated, as this may allow for wideband fault finding using output harmonic analysis.



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