# Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

Authors: Anjali Priya; Nilesh Anand Srivastava; Ram Awadh Mishra
Journal: Journal of Nanotechnology
 (2019)

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## Abstract

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.


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## Body

## 1. Introduction

Incorporation of new technologies is going to be more crucial in the coming era of CMOS devices [1, 2]. Short channel effect has become the major problem in performance improvement at the nanotechnology node [3]. Various technologies have been reported recently regarding the improvement in the device performance at nanometre nodes such as FinFET, FD SOI, recessed-source and drain, and gate engineering [4–20]. In last few years, FinFET devices have gained popularity due to better short channel immunity [4]. However, the fin structure was found to be more complex as compared to FD SOI MOSFETs. The leakage and power consumption are drastically reduced by the use of the FD SOI structure [5–7]. Dielectric isolation in SOI MOSFET reduces parasitic capacitances and substrate leakage current, which tempted the device for analog and digital applications [8]. Since FD SOI MOSFET is associated with the problem of higher source/drain series resistance, the structure of single-metal gate (SMG) recessed-source/drain MOSFET was introduced [9, 10]. In Re-S/D-based device, the depth of source and drain is expanded in the buried insulated layer. It reduces capacitances and gives better drive current [11].To increase the drive current capability, multimaterial gate [12–14] is associated with recessed-source/drain MOSFET. To reduce DIBL, hot carrier effect [15], and gate transport efficiency, the dual-metal gate (DMG) structure was acquainted in the papers [16]. In [17], TMG Re-S/D SOI MOSFET was proposed, in which work functions are in the descending order from the source end to drain end. Due to distinct work function of gate metal contacts, there is a spike identified in the channel electric field. So the carrier transport efficiency is improved, and so the driving capability of the device is also improved [18]. There is suppressed hot carrier effect (HCE) due to high work function of the control gate than the screen gates.The three metals in the gate structures give two step potential profile. It reduces DIBL and improves the current transit speed [19]. So, it enhances current-driving capability which ensures SCEs reduction. It can be the same threshold voltage with reduced doping due to gate engineering [20]. It assures immunity against mobility degradation and improved transconductance.Moreover, use of portable devices in the integration of VLSI circuits requires low power and high speed. At the level of circuit design, the power reduction shifts towards the consideration of a different logic style. CMOS logic offers all requirement of lower and high speed, but in CMOS, the size of the PMOS transistor is larger than the NMOS transistor to balance the rise and fall time. Sometimes, in the logic circuits, it requires to reduce the area for some applications. It can be fulfilled by the use of pseudo-NMOS logic. It uses the n+ 1 transistor as compared to CMOS which uses 2n transistors in the logic circuit [21]. Here, TMG Re-S/D FD SOI MOSFET has been utilized for the performance analysis of aforesaid pseudo-NMOS inverter for low-power digital applications.In this work, threshold voltage of triple-metal gate Re-S/D SOI MOSFET is analyzed for the first time, which is the extension of previous work [17] because surface potential is required to model the threshold voltage of the device. However, to describe the overall electrostatic performance of the device, the threshold voltage model is necessary. Here, analytical threshold voltage model for the device under consideration has been proposed by assuming certain parabolic approximations and verified against two-dimensional mathematical simulations. It is analyzed by varying device parameters like Re-S/D thickness, oxide thickness, and body thickness. Effect of DIBL for a different Re-S/D thickness has also been discussed. Threshold voltage, subthreshold slope, and on/off current ratio have been compared for SMG, DMG, and TMG. It is also investigated by 2D TCAD simulator Silvaco ATLAS [22]. Furthermore, the studied device has been analyzed for the design of the pseudo-NMOS inverter for the estimation of its switching behaviour.Section2 discusses the materials and methods of device design and the specifications. The analytical modeling has been presented in Section 3, and corresponding results are discussed in Section 4. Furthermore, the design and analysis of the pseudo-NMOS inverter is shown in Section 5, and the overall contribution is mentioned in Section 6.


## 2. Materials and Methods

The cross-sectional view of the TMG Re-S/D SOI MOSFET is shown in Figure1, where L, tsi, tox, trsd, tbox, and dbox represent the channel length, silicon body thickness, oxide thickness, Re-S/D thickness, buried oxide (BOX) layer thickness, and S/D overlap over the BOX layer, respectively. The x-axis is taken along the front oxide-channel interface, and y-axis is taken along the source-channel interface. The three metals of the gate are M1(control gate), M2(screen gate: first), and M3(screen gate: second) in which Au, Mo, and Ti are the metal materials. The length of these three metals are termed as L1, L2, and L3 where L1+L2+L3 = L. Na, Nd, and Nsub are concentration levels of the channel region, source/drain region, and substrate region. Also, under the zero bias condition, it is assumed that channel is fully depleted. The structures of single-metal, double-metal, and triple-metal gate are described in Table 1 for 90 nm channel length.Figure 1
Cross-sectional view of TMG recessed-S/D UTB SOI MOSFET.Table 1
Device structure of SMG, DMG, and TMG Re-S/D SOI MOSFET.
Device
L
1
L
2
L
3
∅
M
1
∅
M
2
∅
M
3
SMG Re-S/D
90
—
—
4.8 eV (Au)
—
—
DMG Re-S/D
45
45
—
4.8 eV (Au)
4.6 eV (Mo)
—
TMG Re-S/D
30
30
30
4.8 eV (Au)
4.6 eV (Mo)
4.4 eV (Ti)


## 3. Analytical Modeling

The device under consideration is shown in Figure1, for which under parabolic approximations, 2D Poisson’s equation for the potential at the surface of the channel is presented as follows:(1)∂2∅ix,y∂x2+∂2∅ix,y∂y2=qNaεsi,where i = 1, 2, and 3 for region 10≤x≤L1, 2L1≤x≤L1+L2, and 3L1+L2≤x≤L. εsi is the silicon permittivity. The solution of (1) is defined as follows:(2)∅ix,y=∅six+Ci1xy+Ci2xy2,where ∅six is the surface potential at the SiO2/Si interface. The coefficient Ci1x and Ci2x can be determined from the following boundary condition.At the boundary line of region 1 and 2,(3)∂∅1x,y∂xx=L1=∂∅2x,y∂xx=L1,∂∅2x,y∂xx=L1+L2=∂∅3x,y∂xx=L1+L2.At boundary line between SiO2 and Si,(4)εsi⋅∂∅1x,y∂yy=0=Cox1⋅∅s1x−VGS−VFB1L1,εsi⋅∂∅2x,y∂yy=0=Cox2⋅∅s2x−VGS−VFB2L2,εsi⋅∂∅3x,y∂yy=0=Cox3⋅∅s3x−VGS−VFB3L3.Oxide capacitancesCox1, Cox2, and Cox3 and flat band voltage VFB1, VFB2, and VFB3 are defined in [17]. At the boundary line between the Si and BOX layer,(5)εsi⋅∂∅1x,y∂yy=tsi=Crsd1⋅Vs−VFB4−∅b1xL1+Crsd2⋅VD−VFB4−∅b1xL1+Cbox1⋅Vsub−VFB5−∅b1xL1,εsi⋅∂∅2x,y∂yy=tsi=Crsd3⋅Vs−VFB4−∅b2xL2+Crsd4⋅VD−VFB4−∅b2xL2+Cbox2⋅Vsub−VFB5−∅b2xL2,εsi⋅∂∅3x,y∂yy=tsi=Crsd5⋅Vs−VFB4−∅b3xL3+Crsd6⋅VD−VFB4−∅b3xL3+Cbox3⋅Vsub−VFB5−∅b3xL3.Re-S/D capacitancesCrsd1, Crsd2, Crsd3, Crsd4, Crsd5, and Crsd6 and flat band voltage VFB4 and VFB5 are defined in [17]. ∅bi is the surface potential of the backchannel:(6)at source side:∅10,y=Vbi,at drain side:∅3L,y=Vbi+VDS,where Vbi and VDS are the barrier potential and drain-to-source bias. Threshold voltage is described as the gate voltage in which the minimum surface potential is equal to twice the Fermi potential. In the TMG structure, there are three metal gates with different work functions. The minimum surface potential is defined under the region of highest work function (control gate).In the recessed-source/drain structure, backchannel inversion is also significant as compared to front channel inversion due to certain length of recessed-source/drain. Therefore, threshold voltage for the front and backchannel is analyzed in this modeling. Threshold voltage is described with a larger minimum surface potential.


### 3.1. Front Threshold Voltage

Surface potential at SiO2/Si is calculated as follows [17]:(7)d2∅sixdx2−Gsi∅six=Hsi,i=1,2,3,where Gsi and Hsi are defined in paper [17]. Now, the threshold voltage can be evaluated by following expression:(8)∅s1,minVGS=Vth=∅s1xminVGS=Vth=2∅F,si,where ∅s1,min is the minimum surface potential at the front channel and xmin presents the position of minimum surface potential from the source side. It can be obtained as(9)d∅s1dxx=xmin=0,where ∅F,si is the Fermi potential in the channel region and is defined as(10)∅F,si=kTqlnNani,where ni is the intrinsic carrier concentration. Solving equation (1) gives the following expression of threshold voltage:(11)Vth=−bs+bs2−4ascs2as.The derived formulas of coefficientsas, bs, and cs are shown in Appendix A.


### 3.2. Back Threshold Voltage

Surface potential at the SiO2/BOX interface is calculated as follows [17]:(12)d2∅bixdx2−Gbi∅bix=Hbi,i=1,2,3,where Gbi and Hbi are defined in [17]. Similarly, threshold voltage for the backchannel can be obtained by evaluating the following expression:(13)∅b1,minVGS=Vth=∅b1xminVGS=Vth=2∅F,si,where ∅b1,min is the minimum surface potential in the backchannel and xmin presents the position of the minimum surface potential from the source side. It can be obtained as(14)d∅b1dxx=xmin=0.Solving this equation gives the following expression of threshold voltage:(15)Vth=−bb+bb2−4abcb2ab.The derived formulas of coefficientsab, bb, and cb are shown in Appendix B.In the next section, the corresponding results has been discussed and verified against simulation results.


## 3.1. Front Threshold Voltage

Surface potential at SiO2/Si is calculated as follows [17]:(7)d2∅sixdx2−Gsi∅six=Hsi,i=1,2,3,where Gsi and Hsi are defined in paper [17]. Now, the threshold voltage can be evaluated by following expression:(8)∅s1,minVGS=Vth=∅s1xminVGS=Vth=2∅F,si,where ∅s1,min is the minimum surface potential at the front channel and xmin presents the position of minimum surface potential from the source side. It can be obtained as(9)d∅s1dxx=xmin=0,where ∅F,si is the Fermi potential in the channel region and is defined as(10)∅F,si=kTqlnNani,where ni is the intrinsic carrier concentration. Solving equation (1) gives the following expression of threshold voltage:(11)Vth=−bs+bs2−4ascs2as.The derived formulas of coefficientsas, bs, and cs are shown in Appendix A.


## 3.2. Back Threshold Voltage

Surface potential at the SiO2/BOX interface is calculated as follows [17]:(12)d2∅bixdx2−Gbi∅bix=Hbi,i=1,2,3,where Gbi and Hbi are defined in [17]. Similarly, threshold voltage for the backchannel can be obtained by evaluating the following expression:(13)∅b1,minVGS=Vth=∅b1xminVGS=Vth=2∅F,si,where ∅b1,min is the minimum surface potential in the backchannel and xmin presents the position of the minimum surface potential from the source side. It can be obtained as(14)d∅b1dxx=xmin=0.Solving this equation gives the following expression of threshold voltage:(15)Vth=−bb+bb2−4abcb2ab.The derived formulas of coefficientsab, bb, and cb are shown in Appendix B.In the next section, the corresponding results has been discussed and verified against simulation results.


## 4. Results and Discussion

Analytical model of the threshold voltage for the studied structure has also been compared with TCAD ATLAS Simulator [21]. In the ATLAS simulation, different types of the physical model have been used like field-dependent mobility mode (FLDMOB), concentration-dependent mobility mode (CVT), and Fermi-Dirac statistical model. The doping profile is uniform. The device parameters have been chosen as per the ITRS roadmap. The device channel length (L) is 90 nm, and it has been varied from 20 nm to 300 nm in order to evidence the scaling challenges. The front oxide thickness (tox) is considered as 2 nm, buried oxide thickness (tbox) as 200 nm, silicon channel thickness (tsi) of 10 nm, and Re-S/D thickness (trsd) of 30 nm. The studied MOSFET is characterized with uniform source/drain concentration (Nd) of 1020 cm−3 and low bulk doping (Nsub) of 1015 cm−3.


### 4.1. Threshold Voltage

The comparative study of threshold voltage for SMG, DMG, and TMG Re-S/D SOI MOSFET is shown in Figure2. One can find that TMG offers smallest roll off in threshold till 40 nm as compared to DMG and can be further optimized with the metal gate length ratio. Also, there is 14%-15% improvement in the TMG Re-S/D SOI MOSFET in threshold voltage and 0.5%–1% error in between simulation and model. Figure 3 shows the graph for the threshold voltage by varying length ratio of screen and control gates keeping the overall gate length constant. Roll off in threshold voltage is decreased by choosing a shorter screen gate length, but the effect of drain potential variation becomes considerable which indicates poor immunity to DIBL. So, the ratio (L1:L2) can be optimized to reduce roll off in threshold voltage.Figure 2
Comparison of threshold voltage for SMG, DMG, and TMG Re-S/D SOI MOSFETFigure 3
Threshold voltage for different ratios of control gate and screen gates of TMG Re-S/D SOI MOSFET.Figure4 presents the graph of Vth with channel length, while recessed-source/drain thickness is a variable parameter. For a larger recessed-source/drain thickness, roll off is higher at a shorter channel length, which shows the reduction of gate controllability over the channel and so the SCEs. In the Re-S/D MOSFET, inversion in the backchannel occurs before inversion in the front channel. At zero recessed thickness, device behaves like conventional SOI MOSFET in which the front gate controls the channel. So recessed-source/drain thickness should be optimized for trade-off between the SCEs and the backchannel control. Figure 5 shows the graph of Vth versus channel length by varying work function values of three materials of gate. Threshold voltage is observed to be increased for higher values of work function and also have less roll off. When the difference between the work function is reduced, the channel will be more prone to drain voltage variation which shows more HCEs. So work function should be maintained to optimize between SCEs and HCEs.Figure 4
Threshold voltage for different values of recessed-source/drain thickness.Figure 5
Threshold voltage for different sets of values of work functions for TMG Re-S/D SOI MOSFET.Figure6 shows the graph of DIBL versus channel length for varying the length ratio of control gate and screen gates, while the overall channel length is constant. The graph shows the reduction of DIBL at a shorter length of the control gate. It demonstrates that the structure will be less susceptible to DIBL when control gate length is kept lower. Figure 7 shows the graph of drain-induced barrier lowering (DIBL) plotted against channel length by varying the thickness of the recessed-source/drain region. Here, DIBL is the difference between the threshold voltage at drain to the source voltage value of 0.1 V and 0.05 V. It has been observed that DIBL is minimized by increasing the thickness of recessed-source/drain thickness.Figure 6
DIBL for the different ratios of control gate and screen gates of the TMG device.Figure 7
DIBL for the different values of recessed-source/drain thickness.


### 4.2. Electrostatic Performance

The graph of drain current versus gate voltage for single, double, and TMG Re-S/D SOI MOSFET is shown in Figure8. This graph reveals that the drain current is better in the case of TMG. This high current is due to high electric field, which results from three gate metals. The increment in the electric field at the edge of metals accelerates the carriers, which automatically enhances the transport efficiency of the carriers. There is 3–17% enhancement in the drain current for TMG recessed-S/D MOSFET. However, this signifies a lesser change as compared to SMG and DMG. Moreover, it is well known that the on-current behaviour of all the three devices depends upon recessed-S/D structure. This is the reason that all the three devices have almost the same on current behaviour due to recessed-S/D, and due to the TMG structure, electrostatic characteristics such as off-state leakage, threshold voltage, and DIBL will be improved. Figure 9 represents the on/off current ratio with respect to channel length. It shows that the switching (Ion/Ioff) current ratio is higher for TMG than DMG and SMG. The peaks in the electric field are increased due to the two interface of metal gate. So the current transport efficiency becomes better in comparison to dual and single-metal gate. On/off current ratio is increased by the increasing gate length. As compared to studied DMG Re-S/D, there is 3–17% improvement in the on/off current ratio in TMG. Figure 10 is the graph of the on/off current ratio at a different value of oxide thickness. As shown in the graph, on/off current ratio is larger for a small value of oxide thickness. When the thickness is increased, on/off current ratio is decreased. It is due to the enhancement of on current as compared to off current. It presents the better current transport at a small oxide region thickness. Ion/Ioff current ratio for the TMG Re-S/D device is better as compared to DMG and SMG due to the better current transport.Figure 8
Drain current versus gate voltage for SMG, DMG, and TMG Re-S/D SOI MOSFET.Figure 9
I
on/Ioff at various channel lengths for SMG, DMG, and TMG Re-S/D SOI MOSFET.Figure 10
I
on/Ioff for SMG, DMG, and TMG Re-S/D SOI MOSFET versus oxide thickness.On/off current ratio with the variation of the thickness of the Re-S/D region is shown in Figure11. It shows the higher on/off current ration at zero Re-S/D thickness and lower at 100 nm thickness. Since at 0 nm thickness, the resistance value of the MOSFET is increased. So the thickness is slightly increased to optimize between resistance and current. It also shows the 2–10% better on/off current ratio for the TMG Re-S/D structure. Figure 12 represents the graph of subthreshold slope at different values of channel length. As shown in the graph, the subthreshold value is decreased towards higher channel length. The value of subthreshold slope is approximately 70 mV/dec at a higher channel length. It increases at a lower value due to high leakage. It also shows the lower value for TMG as compared to DMG and SMG Re-S/D SOI MOSFET. There is 0.5-6% decrease in the subthreshold slope for TMG as compared to DMG Re-S/D. Figure 13 presents the subthreshold slope with the variation of oxide thickness at 90 nm channel length. As shown in the graph, the subthreshold value is decreased by decreasing oxide thickness. The subthreshold value is between 60 and 73 mV/dec, which is approximately close to the ideal value of 70 mV/dec. Subthreshold slope for TMG is lower than that for DMG and SMG Re-S/D structures, which show that TMG is better immune to SCEs than DMG and SMG. It is observed that 0.7–1.5% reduction in the subthreshold slope for TMG Re-S/D SOI MOSFET. Subthreshold slope with the variation of Re-S/D thickness is represented in Figure 14. As shown in the graph, the subthreshold value is lower for 0 nm Re-S/D thickness, but it increases the series resistance of the MOSFET. The subthreshold value for 100 nm thickness is higher. So, Re-S/D thickness is kept in between to optimize between resistance and SCEs, i.e., at 30 nm. It also shows the 0.01–0.3% better results for the TMG Re-S/D device as compared to others.Figure 11
I
on/Ioff for SMG, DMG, and TMG Re-S/D SOI MOSFET versus Re-S/D thickness.Figure 12
Subthreshold slope at a different channel length for SMG, DMG, and TMG Re-S/D SOI MOSFET.Figure 13
Subthreshold slope for SMG, DMG, and TMG Re-S/D SOI MOSFET versus oxide thickness at 90 nm channel length.Figure 14
Subthreshold slope for SMG, DMG, and TMG Re-S/D SOI MOSFET versus Re-S/D thickness.The performances of the parameters are compared in Table2. Table 2 is shown for 90 nm channel length in which threshold voltage has been approximately 14% improved for the TMG structure. There is 0.4–0.8% improvement in DIBL and subthreshold slope for TMG Re-S/D as compared to others, which shows better immunity to SCEs. For TMG Re-S/D MOSFET, it is observed to approximate 6% improvement in on/off current ratio and approximate 3% enhancement in transconductance. It shows that TMG Re-S/D MOSFET has superior current driving ability as compared to others.Table 2
Performance comparison of SMG, DMG, and TMG Re-S/D SOI MOSFET.
Parameters
SMG Re-S/D
DMG Re-S/D
TMG Re-S/D
Threshold voltage (V)
0.284
0.379
0.432
DIBL (mV/V)
24.8
24.6
24.5
Subthreshold slope (mV/dec)
68.1
67.5
66.9
I
on/Ioff
2.052 × 108
3.316 × 108
3.537 × 108
Transconductance (S/µm)
5.559 × 10−4
5.903 × 10−4
6.041 × 10−4Also, it is necessary to examine charge distribution at the interfaces of the three metal gates. As, in the channel, uniform charge density has been assumed for the modeling of the proposed device. The plot of carrier concentration vs. position along the channel is shown in Figure15. It is clear from the plot that the device offers almost uniform charge density in the channel and even all the metal interfaces have equal charge distribution. The uniform charge density of 19.25 cm−3 and 19.40 cm−3 is observed at the first and second metal interfaces, respectively. These performance features of TMG Re-S/D FD SOI MOSFET have made it a suitable candidate for the analysis and design of today’s low-power integrated circuits (ICs). In the next section, an attempt has been made to analyze the studied device performance in digital circuitry.Figure 15
Carrier concentration along the position of channel length for TMG Re-S/D FD SOI MOSFET.


## 4.1. Threshold Voltage

The comparative study of threshold voltage for SMG, DMG, and TMG Re-S/D SOI MOSFET is shown in Figure2. One can find that TMG offers smallest roll off in threshold till 40 nm as compared to DMG and can be further optimized with the metal gate length ratio. Also, there is 14%-15% improvement in the TMG Re-S/D SOI MOSFET in threshold voltage and 0.5%–1% error in between simulation and model. Figure 3 shows the graph for the threshold voltage by varying length ratio of screen and control gates keeping the overall gate length constant. Roll off in threshold voltage is decreased by choosing a shorter screen gate length, but the effect of drain potential variation becomes considerable which indicates poor immunity to DIBL. So, the ratio (L1:L2) can be optimized to reduce roll off in threshold voltage.Figure 2
Comparison of threshold voltage for SMG, DMG, and TMG Re-S/D SOI MOSFETFigure 3
Threshold voltage for different ratios of control gate and screen gates of TMG Re-S/D SOI MOSFET.Figure4 presents the graph of Vth with channel length, while recessed-source/drain thickness is a variable parameter. For a larger recessed-source/drain thickness, roll off is higher at a shorter channel length, which shows the reduction of gate controllability over the channel and so the SCEs. In the Re-S/D MOSFET, inversion in the backchannel occurs before inversion in the front channel. At zero recessed thickness, device behaves like conventional SOI MOSFET in which the front gate controls the channel. So recessed-source/drain thickness should be optimized for trade-off between the SCEs and the backchannel control. Figure 5 shows the graph of Vth versus channel length by varying work function values of three materials of gate. Threshold voltage is observed to be increased for higher values of work function and also have less roll off. When the difference between the work function is reduced, the channel will be more prone to drain voltage variation which shows more HCEs. So work function should be maintained to optimize between SCEs and HCEs.Figure 4
Threshold voltage for different values of recessed-source/drain thickness.Figure 5
Threshold voltage for different sets of values of work functions for TMG Re-S/D SOI MOSFET.Figure6 shows the graph of DIBL versus channel length for varying the length ratio of control gate and screen gates, while the overall channel length is constant. The graph shows the reduction of DIBL at a shorter length of the control gate. It demonstrates that the structure will be less susceptible to DIBL when control gate length is kept lower. Figure 7 shows the graph of drain-induced barrier lowering (DIBL) plotted against channel length by varying the thickness of the recessed-source/drain region. Here, DIBL is the difference between the threshold voltage at drain to the source voltage value of 0.1 V and 0.05 V. It has been observed that DIBL is minimized by increasing the thickness of recessed-source/drain thickness.Figure 6
DIBL for the different ratios of control gate and screen gates of the TMG device.Figure 7
DIBL for the different values of recessed-source/drain thickness.


## 4.2. Electrostatic Performance

The graph of drain current versus gate voltage for single, double, and TMG Re-S/D SOI MOSFET is shown in Figure8. This graph reveals that the drain current is better in the case of TMG. This high current is due to high electric field, which results from three gate metals. The increment in the electric field at the edge of metals accelerates the carriers, which automatically enhances the transport efficiency of the carriers. There is 3–17% enhancement in the drain current for TMG recessed-S/D MOSFET. However, this signifies a lesser change as compared to SMG and DMG. Moreover, it is well known that the on-current behaviour of all the three devices depends upon recessed-S/D structure. This is the reason that all the three devices have almost the same on current behaviour due to recessed-S/D, and due to the TMG structure, electrostatic characteristics such as off-state leakage, threshold voltage, and DIBL will be improved. Figure 9 represents the on/off current ratio with respect to channel length. It shows that the switching (Ion/Ioff) current ratio is higher for TMG than DMG and SMG. The peaks in the electric field are increased due to the two interface of metal gate. So the current transport efficiency becomes better in comparison to dual and single-metal gate. On/off current ratio is increased by the increasing gate length. As compared to studied DMG Re-S/D, there is 3–17% improvement in the on/off current ratio in TMG. Figure 10 is the graph of the on/off current ratio at a different value of oxide thickness. As shown in the graph, on/off current ratio is larger for a small value of oxide thickness. When the thickness is increased, on/off current ratio is decreased. It is due to the enhancement of on current as compared to off current. It presents the better current transport at a small oxide region thickness. Ion/Ioff current ratio for the TMG Re-S/D device is better as compared to DMG and SMG due to the better current transport.Figure 8
Drain current versus gate voltage for SMG, DMG, and TMG Re-S/D SOI MOSFET.Figure 9
I
on/Ioff at various channel lengths for SMG, DMG, and TMG Re-S/D SOI MOSFET.Figure 10
I
on/Ioff for SMG, DMG, and TMG Re-S/D SOI MOSFET versus oxide thickness.On/off current ratio with the variation of the thickness of the Re-S/D region is shown in Figure11. It shows the higher on/off current ration at zero Re-S/D thickness and lower at 100 nm thickness. Since at 0 nm thickness, the resistance value of the MOSFET is increased. So the thickness is slightly increased to optimize between resistance and current. It also shows the 2–10% better on/off current ratio for the TMG Re-S/D structure. Figure 12 represents the graph of subthreshold slope at different values of channel length. As shown in the graph, the subthreshold value is decreased towards higher channel length. The value of subthreshold slope is approximately 70 mV/dec at a higher channel length. It increases at a lower value due to high leakage. It also shows the lower value for TMG as compared to DMG and SMG Re-S/D SOI MOSFET. There is 0.5-6% decrease in the subthreshold slope for TMG as compared to DMG Re-S/D. Figure 13 presents the subthreshold slope with the variation of oxide thickness at 90 nm channel length. As shown in the graph, the subthreshold value is decreased by decreasing oxide thickness. The subthreshold value is between 60 and 73 mV/dec, which is approximately close to the ideal value of 70 mV/dec. Subthreshold slope for TMG is lower than that for DMG and SMG Re-S/D structures, which show that TMG is better immune to SCEs than DMG and SMG. It is observed that 0.7–1.5% reduction in the subthreshold slope for TMG Re-S/D SOI MOSFET. Subthreshold slope with the variation of Re-S/D thickness is represented in Figure 14. As shown in the graph, the subthreshold value is lower for 0 nm Re-S/D thickness, but it increases the series resistance of the MOSFET. The subthreshold value for 100 nm thickness is higher. So, Re-S/D thickness is kept in between to optimize between resistance and SCEs, i.e., at 30 nm. It also shows the 0.01–0.3% better results for the TMG Re-S/D device as compared to others.Figure 11
I
on/Ioff for SMG, DMG, and TMG Re-S/D SOI MOSFET versus Re-S/D thickness.Figure 12
Subthreshold slope at a different channel length for SMG, DMG, and TMG Re-S/D SOI MOSFET.Figure 13
Subthreshold slope for SMG, DMG, and TMG Re-S/D SOI MOSFET versus oxide thickness at 90 nm channel length.Figure 14
Subthreshold slope for SMG, DMG, and TMG Re-S/D SOI MOSFET versus Re-S/D thickness.The performances of the parameters are compared in Table2. Table 2 is shown for 90 nm channel length in which threshold voltage has been approximately 14% improved for the TMG structure. There is 0.4–0.8% improvement in DIBL and subthreshold slope for TMG Re-S/D as compared to others, which shows better immunity to SCEs. For TMG Re-S/D MOSFET, it is observed to approximate 6% improvement in on/off current ratio and approximate 3% enhancement in transconductance. It shows that TMG Re-S/D MOSFET has superior current driving ability as compared to others.Table 2
Performance comparison of SMG, DMG, and TMG Re-S/D SOI MOSFET.
Parameters
SMG Re-S/D
DMG Re-S/D
TMG Re-S/D
Threshold voltage (V)
0.284
0.379
0.432
DIBL (mV/V)
24.8
24.6
24.5
Subthreshold slope (mV/dec)
68.1
67.5
66.9
I
on/Ioff
2.052 × 108
3.316 × 108
3.537 × 108
Transconductance (S/µm)
5.559 × 10−4
5.903 × 10−4
6.041 × 10−4Also, it is necessary to examine charge distribution at the interfaces of the three metal gates. As, in the channel, uniform charge density has been assumed for the modeling of the proposed device. The plot of carrier concentration vs. position along the channel is shown in Figure15. It is clear from the plot that the device offers almost uniform charge density in the channel and even all the metal interfaces have equal charge distribution. The uniform charge density of 19.25 cm−3 and 19.40 cm−3 is observed at the first and second metal interfaces, respectively. These performance features of TMG Re-S/D FD SOI MOSFET have made it a suitable candidate for the analysis and design of today’s low-power integrated circuits (ICs). In the next section, an attempt has been made to analyze the studied device performance in digital circuitry.Figure 15
Carrier concentration along the position of channel length for TMG Re-S/D FD SOI MOSFET.


## 5. Design and Analysis of Pseudo-NMOS Inverter

Recently, pseudo-NMOS inverter has been accepted as the faster design as compared to the conventional inverter [23]. Here, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter is designed by using PMOS and NMOS pairs, as shown in Figure 16. PMOS transistor is connected as pull-up load in which its gate is connected permanently to ground. Since it is not driven by any signals, it is always in the ON condition. NMOS is used as pull-down or driver circuit. Its gate is connected with input signals. It is equivalent to the operation of NMOS technology in the depletion mode. So, it is called pseudo-NMOS. In this circuit, PMOS works in the linear region, so it has low resistance and hence low time constant. However, NMOS works in the subthreshold region due to which it is fastest among other CMOS logic. It has the advantage of less area and high speed, but also it has the disadvantage of significant static power consumption.Figure 16
Pseudo-NMOS inverter.The voltage transfer characteristics (VTC) of pseudo-NMOS inverter for TMG, DMG, and SMG recessed-S/D FD SOI MOSFET are shown in Figure17. One can observe from the plot that the switching distance of TMG Re-S/D MOSFET is less as compared to DMG and SMG Re-S/D MOSFET. The TMG offers better characteristics due to the higher threshold and lesser threshold voltage variability as compared to DMG and SMG Re-S/D FD SOI MOSFETs. This will directly affect the noise immunity levels of SMG and DMG as compared to the TMG structure. So, the performance of TMG Re-S/D-based pseudo-NMOS is better as it responds rapidly. Furthermore, in order to analyze the scaling constraints versus switching characteristics of the TMG Re-S/D FD SOI MOSFET, this has been scaled down to 45 nm.Figure 17
Voltage transfer characteristic curve of pseudo-NMOS for TMG, DMG, and SMG Re-S/D FD SOI MOSFET.The VTC curve of the pseudo-NMOS inverter for TMG Re-S/D MOSFET at various channel lengths is shown in Figure18. In short channel devices, barrier for electron injection from source to channel reduces due to overlapping of source and drain depletion regions. It leads to reduced threshold voltage. At the lower threshold voltage, NMOS transistor turns on earlier than the one with higher threshold voltage. Similarly, the PMOS transistor takes time to turn off. So, the switching distance is increased. So, threshold voltage varies with channel length. It reduces by reducing the channel length of the device. Therefore, switching distance is large for a smaller channel length. It is clear from the plot that the device resembles the inverter characteristics even if it is scaled down to 45 nm. Moreover, the performance of the inverter at 90 nm channel length of TMG Re-S/D MOSFET is found to be better as its characteristics tend towards the ideal value and switching is faster. So, we have analyzed the device further at 90 nm channel length for its transient behaviour.Figure 18
VTC curve of pseudo-NMOS for TMG Re-S/D FD SOI MOSFET at different channel lengths.The transient analysis of pseudo-NMOS inverter for TMG Re-S/D FD SOI MOSFET is presented in Figure19 at 90 nm channel length. In the transient analysis, input voltage has been given in pulse waveform with 0 to 1 V amplitude and 10 ps of cycle. As the supply voltage given in the inverter is 1 V, output voltage waveform switches between 0 and 1 V. The graph itself shows the inversion characteristics for input and output voltage, and the propagation delay between input and output switching is observed. When the output goes low to high value, the delay, i.e., τplh, is observed as 0.59 ps, and when the output goes high to low output, the delay, i.e., τphl, is observed as 0.27 ps. As the total propagation delay of the pseudo-NMOS is the average of τphl and τplh, the total delay comes as 0.43 ps. The comparison with the previous literature is shown in Table 3. This is very less for the circuit to be operated faster, and hence, the studied device could be optimized for high-speed applications.Figure 19
Transient analysis of pseudo-NMOS for TMG Re-S/D FD SOI MOSFET at 90 nm channel length.Table 3
Comparison of delay of inverters at 90 nm channel length.
References
Inverter delay
Samanta et al. [24]
0.31 ns
Sing et al. [25]
9.43 ps
Rodoni et al. [26]
4.7 ps
Proposed pseudo-NMOS
0.43 ps


## 6. Conclusion

In this contribution, design and analysis of recessed-S/D SOI MOSFET-based pseudo-NMOS inverter has been presented for low-power and high-speed applications. First, a comparison of threshold voltage and electrostatic performance has been discussed for single-metal, double-metal, and triple-metal gate recessed-source/drain (Re-S/D) SOI MOSFET. The model for threshold voltage helps to optimize the SCEs for short channel devices. The gate of three materials which are laterally joined shows better immunity to SCEs and DIBL which is the major concern of SOI MOSFET. The accuracy of the analytical model has been verified with the result of the two-dimensional TCAD simulator of Silvaco ATLAS, and it shows good agreement with 0.5–1% error in results. The comparison of threshold voltage indicates that the TMG-based device offers better immunity to SCEs than other Re-S/D SOI MOSFETs as less roll off seen in case of TMG. The TMG device provides significant reduction in the DIBL effect even if there are parameter variations. The enhancement in the drain current reveals that the TMG is better than the DMG and SMG Re-S/D SOI MOSFET in terms of current-driving capability. These advanced features of the TMG device made it a suitable candidate to further analyze it for high speed switching applications. For this, a pseudo-NMOS inverter has been designed and simulated using TMG Re-S/D FD SOI MOSFET. It is found that the inverter shows the excellent characteristics in case of TMG as compared to others as the TMG device resembles almost ideal VTC atVdd = 1 V. The transient analysis shows that the studied circuit allows very less propagation delay of 0.43 ps. So, the device could be suggested for high-speed and low-power IC applications. Moreover, channel engineering and the analysis of analog and high-frequency performances can be the future work of this device.



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*Source: 4935073-2019-03-28.xml*