# A 3.22–5.45 GHz and 199 dBc/Hz FoMT CMOS Complementary Class-C DCO

Authors: Lei Ma; Na Yan; Sizheng Chen; Yangzi Liu; Hao Min
Journal: Wireless Communications and Mobile Computing
 (2018)

---

## Abstract

This paper implements a complementary Class-C digitally controlled oscillator (DCO) with differential transistor pairs. The transistors are dynamically biased by feedback loops separately benefiting the robust oscillation start-up with low power consumption. By optimizing three switched capacitor arrays and employing fractional capacitor array with sigma-delta modulator (SDM), the presented DCO operates from 3.22 GHz to 5.45 GHz with a 51.5% frequency tuning range and 0.1 ppm frequency resolution. The design was implemented in a 65 nm CMOS process with power consumption of 2.8 mA at 1.2 V voltage supply. Measurement results show that the phase noise is about −126 dBc/Hz at 3 MHz offset from a 5.054 GHz carrier frequency with the1/f3 corner frequency of 260 KHz. The resulting FoMT achieves 199.4 dBc/Hz and varies less than 2 dB across the frequency tuning range.


---

## Body

## 1. Introduction

Combining the high spectral purity, wide FTR, and low power consumption is still one of the most challenging targets in the design of frequency synthesizers, especially for the cellular GSM/WCDMA/LTE applications. In recent years, ADPLLs are deeply researched and widely used in cellular applications because of their downscaled area, low power consumption, and improved phase noise performance in advanced CMOS technology [1, 2]. DCO is one of the most challenging design blocks because good phase noise performance should be ensured with low power consumption and it needs to satisfy the wide FTR and high-frequency resolution simultaneously in ADPLL.Compared with traditionalLC-tank oscillators, the differential transistor pairs based Class-C oscillator delivers briefer and taller pulses and maximizes the output oscillation amplitude, which leads to a minimization of the phase noise [3]. It means that the phase noise can be improved theoretically with the same current consumption.This paper implements a wide FTR and high FoMT Class-C DCO based on 65 nm 1P9M CMOS process. Two feedback loops ensure the robust oscillation start-up of DCO [4, 5], which is achieved by adjusting the DC biasing voltage of the differential transistor pairs synchronously reducing power consumption. The FTR and frequency resolution of the presented DCO are improved and optimized by employing the three capacitor arrays and the fractional array with SDM.The remaining paper is divided into three parts. Description of the presented complementary Class-C DCO is given in Section2 and measurement results are shown in Section 3. Conclusion is described in Section 4.


## 2. Complementary Class-C DCO

### 2.1. Architecture Description

Figure1 shows the complementary Class-C DCO architecture. Two cross-coupled pairs M1/M2 and M3/M4 provide negative resistance to recover the energy losses in the resonant load. The current mirror is made up of M1/M2 and M1bias/M2bias to provide the dc current bias, and it also has a high enough transconductance initially by using the negative feedback to ensure a robust start-up oscillation. Moreover, in steady state, the bias voltage VBN falls from its start-up value which maximizes the output swing [4]. M5 works as a level shifter to provide dc bias voltages VBP and VT through the common-mode negative feedback.LC-tank is composed of a tapped inductor and three capacitor arrays.Figure 1
Schematic view of Class-C DCO.


### 2.2. Design of Capacitor Arrays

DCO’s resonant frequencyfCKV can be tuned by switching the varactors between on-state and off-state as (1), in which C0,k, dk, andΔCkare the kth varactor’s off-state capacitance value, digitally controlled signal, and ΔC, separately. ΔC is the capacitance differential value between the on-state and off-state and Cp is the whole parasitic capacitance. Capacitor arrays include coarse array, medium array, and fine array and their corresponding FTS are KDCO_C, KDCO_M, and KDCO_F, respectively. The capacitor arrays are constructed by PMOS varactor because of its high density capacitance. (1)fCKV=12πL∑k=0N-1C0,k+dk¯ΔCk-1+Cp.For coarse array,KDCO_C is proportional to the inductor value L, ΔC, and the cube of fCKV as shown in (2):(2)KDCO_C=ΔfLSB=≈∂f∂C·ΔCLSB=2π2LfCKV3ΔCLSB(3)Hols=α+ρ·fRs·fRs·KDCO_CK^DCO.Equation (3) gives the s-domain open loop transfer function of ADPLL [2], α and ρ are loop parameters, fR is reference clock, and K^DCO is the normalized gain of DCO. In coarse array, KDCO_C changes 4.85 times (≈(5.45/3.22)3) across the entire FTR, and ADPLL’s Hol(s) also changes with KDCO_C as (3), which will result in instability of ADPLL loop. Therefore, varactors with different ΔC value are adopted at different frequency points realizing a constant KDCO_C to ensure the loop stability.(4)KDCO_C,i=12πLC-12πLC+ΔCi-1KDCO_C,i+1=12πLC-ΔCi-12πLC.ForLC-DCO, the ithKDCO_C and the i+1thKDCO_C can be calculated by (4), where ΔCi-1, ΔCi, and C are the ithΔC, the i+1thΔC, and all the capacitors of the coarse array, respectively. In order to get constant KDCO_C, KDCO,i should be equal to KDCO,i+1, which means (5)1-11+ΔCi-1/C=11-ΔCi/C-1.From (5), it can be concluded that the linearity of KDCO_C only depends on ΔCi/C. Finally, the coarse array is designed according to (2)~(5) with constant 24 MHz/LSB’s KDCO_C which is equal to the reference clock 24 MHz. 89 varactors make up the coarse array to cover the wide FTR and they are decoded from 7 bits coarse oscillator tuning word (OTW), as shown in Figure 1; the postfixes _C, _M, _FI, and _FF are, respectively, the OTW of coarse array, medium array, integral fine array, and fractional fine array.For the wide FTR application, the coarse array has the varactors with the biggestΔC in the resonant tank. For PMOS varactor shown in Figure 2, the relevant parasitic capacitance can be classified into three parts as shown in Figure 2: (1) the oxide layer capacitance between gate and channel: C1=WLCOX, where COX is the capacitance of gate oxide layer per unit area and W and L are the gate width and gate length, respectively; (2) the depletion layer capacitance between substrate and channel: C2=WLqεsiNnwell/(4φF), where q is a charge constant, εsi is the dielectric constant of silicon, Nnwell is the doping concentration of N-well, andφFis the built-in potential; (3) the overlapping capacitance among gate, source, and drain: C3 and C4 equal to WCOV, where COV is the overlapping capacitance per unit width.Figure 2
Parasitic capacitance model in PMOS varactor.Therefore, when the PMOS varactor operates in inversion region, capacitance is maximized toCmax. When the PMOS varactor operates in depletion region, capacitance is minimized to Cmin.So the capacitance ratio is(6)CR=CmaxCmin=LCOX+2COVLqεsiNnwell/4φF+2COV.BecauseCOV>qεsiNnwell/(4φF), CR increases when L is increased, and higher CR means the wider FTR.When PMOS varactor operates in depletion region, channel is not formed; the parasitic resistance only includes gate resistanceRg and metal contact parasitic resistance of source and drain Ra, so the Q value of PMOS varactor in depletion region is (7)Qdep=1ωRg+RaCmin.However, when the PMOS varactor lies in inversion region, theQ value can be inferred from [9] as the following equation shows:(8)Qinv=12kpVGS-VTpωCOXL2.In (8), kp is the gain factor of PMOS transistor, VGS is the voltage difference between gate and source, and VTp is the threshold voltage for PMOS transistor. It can be concluded that Qinv is inversely proportional to the square of L.Therefore, theQ value, symmetry, and Cp are mainly determined by the coarse array. For the coarse array, it is difficult to trade off the Q value and the region of FTR. Finally, the channel length of the coarse array is set to 600 nm. As shown in the postsimulation in a 65 nm CMOS process, the Q value is higher than 25 and the CR is about 7. Both of them satisfy the phase noise and the FTR requirements.However, for the medium and fine array, frequency resolution is the most important design factor. 200 nm and 60 nm channel length are chosen, respectively, for high-frequency resolution and highQ value. Both of them are composed of unit cap array because their FTS varies a little with the change of frequency and these two arrays’ FTS have little effect on the loop stability of ADPLL. The FTR of medium and fine arrays should respectively cover several LSBs of coarse and medium arrays so that the OTW of current array will not overflow due to the process, voltage, and temperature (PVT) variations. In the process of ADPLL locking, OTW overflow means that medium tuning or fine-tuning period cannot be finished and loss-of-lock may occur. According to the possible largest frequency error due to PVT variations and the required frequency resolution of the current locking period, 6-bit medium arrays and 7-bit fine arrays are designed to cover 4 LSBs of KDCO_C and 8 LSBs of KDCO_M, respectively. Finally, the locking process of ADPLL can be divided into three frequency locking periods step by step without the possibility of loss-of-lock due to OTW overflow.In order to improve the phase noise performance of the DCO, MOS varactor is controlled digitally. As shown in Figure3, OTW (Oscillator Tuning Word) is decoded into the thermal code to control the on/off states of MOS varactor with an inverting driver. The voltage level of digital control signal dk can be adjusted by VHigh and VLow. Figure 3 also shows the curve of a PMOS varactor capacitance versus VGS (C-V curve). MOS varactors change linearly from V1 to V2 and A0 is the output amplitude of DCO. During the whole oscillation period, the originalC-V curve has to be transferred into the averageC-V curve with red dashed dotted line as shown in Figure 3. Therefore, in order to stop the PMOS varactor from inducing the noise on the dk, the varactor must be working in the on/off states region of the averageC-V curve.Figure 3
DCO capacitor array.The finite frequency tuning resolution introduces the quantization noise and contributes the output phase noise of the ADPLL and hence a small tuning step is desired. The frequency resolution requirement is 0.1 ppm, but the smallest FTS is limited by the smallestΔC in 65 nm process. Figure 4 compares the phase noise contribution among MASH 1, MASH 1-1, and MASH 1-1-1 SDM; it can be seen that MASH 1-1-1 SDM has the lowest in-band phase noise contribution and the best noise shaping character. Moreover, their out-band phase noise contributions are almost the same. Therefore, 10-bit OTW_FF is dithered with MASH 1-1-1 SDM to control 6-bit fractional capacitor arrays to improve the frequency resolution and decrease the noise contribution. The phase noise contribution of SDM to ADPLL is simulated with MATLAB as shown and it is below −150 dBc/Hz, which means it affects in a small way the whole phase noise performance. In Figure 5, Eq1(z), Eq2(z), and Eq3(z) are the quantization noise of each accumulator. Therefore, the output frequency of SDM can be deduced from (9)C1=OTWF_F+1-z-1∗Eq1zC2=-Eq1z∗z-1+1-z-1∗Eq2zC3=-Eq2z∗z-1+1-z-1∗Eq3zfout=C1z-3+C2z-2-z-3+C3z-1-2z-2+z-3∗KDCO_F=OTWF_F∗z-3+z-11-z-13∗Eq1z∗KDCO_F.Figure 4
The comparison of phase noise contribution of SDM.Figure 5
MASH 1-1-1 sigma-delta modulator.


### 2.3. Class-C DCO’s Negative Feedback Loops

In Figure1, current IBP is chosen to bias M5 providing a level shift voltage. ARCnetwork is used to provide a dc bias voltage, and VBP is higher than the tank common-mode voltage, which permits a larger resonator swing before the M3/M4 is pushed into the triode region. This is the same technique employed to bias the M1/M2. Moreover, a highRC constant of theRC biasing network is used to low-pass filter the noise introduced to VBN and VBP, optimizing the phase noise [5]. Ctail not only integrates the difference between IBN and the current exhausted by the DCO but also filters the high-frequency noise contribution from M1bias/M2bias, improving the phase noise [4].The simulated transient voltage of DCO is given in Figure6(a); Vout is the oscillation output of DCO. Initially, the M1bias/M2bias are diode-connected (at DC) and IBN is mirrored (multiplied byN) to the DCO core, which makes both PMOS and NMOS cross-coupled MOSFET work in saturation region and provide a high transconductance to guarantee a robust start-up. As the oscillator amplitude is increased, the average current IDC depleted by M1bias/M2bias increases and then the superfluous current will be integrated into Ctail reducing VBN and guiding the switching pair M1/M2 to work in Class-C mode. At the same time, VBP increases and pushes PMOS working in Class-C mode. VT is finally changed to the half value of the VDD to offer the common-mode voltage of DCO and the same overdrive of PMOS and NMOS pairs. Figure 6(b) shows the transient simulation result of M1’s current (blue line) when M1 operates at Class-C mode; the tall and short pulses maximize the output oscillation amplitude (red line), which minimizes the phase noise of DCO.Figure 6
Transient voltage waveform of Class-C DCO (a) andM1 current transient simulation result (b).
(a)
(b)Referring to the noise analysis in [10], the proposed DCO’s noise from feedback loop can be inferred in (10), wherevn2-RB,vn2-r0,M5, and vn2-IBare, respectively, the white noise voltage power spectral density by bias resistor RB, bias MOSFET M5, and bias MOSFET M1bias/M2bias. ωp is the single pole in the feedback loop. The gnl2(θc)Γosc2(θc) is the amplification and frequency translation that the feedback loop noise must undergo first.(10)NFL=1T∫-θC/2θC/22vn2¯RB+vn2¯r0,M5+vn2¯IB1+ωp2gnl2θcΓosc2θcdθc=2vn2¯RB+vn2¯r0,M5+vn2¯IB1+ωp2g02fflVOSC.Therefore, the total amount of phase noise can be deduced in (11) where K is Boltzmann constant, Tk is the absolute temperature in Kelvin, C is the capacitor inLC resonant bank, VOSC is the oscillation amplitude of DCO, 2R is the parasitics losses, and γ is the technology coefficient. fcp(VOSC) and ffl(VOSC) are, respectively, weighing factors of cross-coupled MOSFETs and feedback loops. (11)PNΔω=KTkΔω2C2Vosc21R+γαg0fcpVosc+2vn2¯RB+vn2¯r0,M5+vn2¯IBΔω2C2Vosc21+ωp2g02fflVOSC.


## 2.1. Architecture Description

Figure1 shows the complementary Class-C DCO architecture. Two cross-coupled pairs M1/M2 and M3/M4 provide negative resistance to recover the energy losses in the resonant load. The current mirror is made up of M1/M2 and M1bias/M2bias to provide the dc current bias, and it also has a high enough transconductance initially by using the negative feedback to ensure a robust start-up oscillation. Moreover, in steady state, the bias voltage VBN falls from its start-up value which maximizes the output swing [4]. M5 works as a level shifter to provide dc bias voltages VBP and VT through the common-mode negative feedback.LC-tank is composed of a tapped inductor and three capacitor arrays.Figure 1
Schematic view of Class-C DCO.


## 2.2. Design of Capacitor Arrays

DCO’s resonant frequencyfCKV can be tuned by switching the varactors between on-state and off-state as (1), in which C0,k, dk, andΔCkare the kth varactor’s off-state capacitance value, digitally controlled signal, and ΔC, separately. ΔC is the capacitance differential value between the on-state and off-state and Cp is the whole parasitic capacitance. Capacitor arrays include coarse array, medium array, and fine array and their corresponding FTS are KDCO_C, KDCO_M, and KDCO_F, respectively. The capacitor arrays are constructed by PMOS varactor because of its high density capacitance. (1)fCKV=12πL∑k=0N-1C0,k+dk¯ΔCk-1+Cp.For coarse array,KDCO_C is proportional to the inductor value L, ΔC, and the cube of fCKV as shown in (2):(2)KDCO_C=ΔfLSB=≈∂f∂C·ΔCLSB=2π2LfCKV3ΔCLSB(3)Hols=α+ρ·fRs·fRs·KDCO_CK^DCO.Equation (3) gives the s-domain open loop transfer function of ADPLL [2], α and ρ are loop parameters, fR is reference clock, and K^DCO is the normalized gain of DCO. In coarse array, KDCO_C changes 4.85 times (≈(5.45/3.22)3) across the entire FTR, and ADPLL’s Hol(s) also changes with KDCO_C as (3), which will result in instability of ADPLL loop. Therefore, varactors with different ΔC value are adopted at different frequency points realizing a constant KDCO_C to ensure the loop stability.(4)KDCO_C,i=12πLC-12πLC+ΔCi-1KDCO_C,i+1=12πLC-ΔCi-12πLC.ForLC-DCO, the ithKDCO_C and the i+1thKDCO_C can be calculated by (4), where ΔCi-1, ΔCi, and C are the ithΔC, the i+1thΔC, and all the capacitors of the coarse array, respectively. In order to get constant KDCO_C, KDCO,i should be equal to KDCO,i+1, which means (5)1-11+ΔCi-1/C=11-ΔCi/C-1.From (5), it can be concluded that the linearity of KDCO_C only depends on ΔCi/C. Finally, the coarse array is designed according to (2)~(5) with constant 24 MHz/LSB’s KDCO_C which is equal to the reference clock 24 MHz. 89 varactors make up the coarse array to cover the wide FTR and they are decoded from 7 bits coarse oscillator tuning word (OTW), as shown in Figure 1; the postfixes _C, _M, _FI, and _FF are, respectively, the OTW of coarse array, medium array, integral fine array, and fractional fine array.For the wide FTR application, the coarse array has the varactors with the biggestΔC in the resonant tank. For PMOS varactor shown in Figure 2, the relevant parasitic capacitance can be classified into three parts as shown in Figure 2: (1) the oxide layer capacitance between gate and channel: C1=WLCOX, where COX is the capacitance of gate oxide layer per unit area and W and L are the gate width and gate length, respectively; (2) the depletion layer capacitance between substrate and channel: C2=WLqεsiNnwell/(4φF), where q is a charge constant, εsi is the dielectric constant of silicon, Nnwell is the doping concentration of N-well, andφFis the built-in potential; (3) the overlapping capacitance among gate, source, and drain: C3 and C4 equal to WCOV, where COV is the overlapping capacitance per unit width.Figure 2
Parasitic capacitance model in PMOS varactor.Therefore, when the PMOS varactor operates in inversion region, capacitance is maximized toCmax. When the PMOS varactor operates in depletion region, capacitance is minimized to Cmin.So the capacitance ratio is(6)CR=CmaxCmin=LCOX+2COVLqεsiNnwell/4φF+2COV.BecauseCOV>qεsiNnwell/(4φF), CR increases when L is increased, and higher CR means the wider FTR.When PMOS varactor operates in depletion region, channel is not formed; the parasitic resistance only includes gate resistanceRg and metal contact parasitic resistance of source and drain Ra, so the Q value of PMOS varactor in depletion region is (7)Qdep=1ωRg+RaCmin.However, when the PMOS varactor lies in inversion region, theQ value can be inferred from [9] as the following equation shows:(8)Qinv=12kpVGS-VTpωCOXL2.In (8), kp is the gain factor of PMOS transistor, VGS is the voltage difference between gate and source, and VTp is the threshold voltage for PMOS transistor. It can be concluded that Qinv is inversely proportional to the square of L.Therefore, theQ value, symmetry, and Cp are mainly determined by the coarse array. For the coarse array, it is difficult to trade off the Q value and the region of FTR. Finally, the channel length of the coarse array is set to 600 nm. As shown in the postsimulation in a 65 nm CMOS process, the Q value is higher than 25 and the CR is about 7. Both of them satisfy the phase noise and the FTR requirements.However, for the medium and fine array, frequency resolution is the most important design factor. 200 nm and 60 nm channel length are chosen, respectively, for high-frequency resolution and highQ value. Both of them are composed of unit cap array because their FTS varies a little with the change of frequency and these two arrays’ FTS have little effect on the loop stability of ADPLL. The FTR of medium and fine arrays should respectively cover several LSBs of coarse and medium arrays so that the OTW of current array will not overflow due to the process, voltage, and temperature (PVT) variations. In the process of ADPLL locking, OTW overflow means that medium tuning or fine-tuning period cannot be finished and loss-of-lock may occur. According to the possible largest frequency error due to PVT variations and the required frequency resolution of the current locking period, 6-bit medium arrays and 7-bit fine arrays are designed to cover 4 LSBs of KDCO_C and 8 LSBs of KDCO_M, respectively. Finally, the locking process of ADPLL can be divided into three frequency locking periods step by step without the possibility of loss-of-lock due to OTW overflow.In order to improve the phase noise performance of the DCO, MOS varactor is controlled digitally. As shown in Figure3, OTW (Oscillator Tuning Word) is decoded into the thermal code to control the on/off states of MOS varactor with an inverting driver. The voltage level of digital control signal dk can be adjusted by VHigh and VLow. Figure 3 also shows the curve of a PMOS varactor capacitance versus VGS (C-V curve). MOS varactors change linearly from V1 to V2 and A0 is the output amplitude of DCO. During the whole oscillation period, the originalC-V curve has to be transferred into the averageC-V curve with red dashed dotted line as shown in Figure 3. Therefore, in order to stop the PMOS varactor from inducing the noise on the dk, the varactor must be working in the on/off states region of the averageC-V curve.Figure 3
DCO capacitor array.The finite frequency tuning resolution introduces the quantization noise and contributes the output phase noise of the ADPLL and hence a small tuning step is desired. The frequency resolution requirement is 0.1 ppm, but the smallest FTS is limited by the smallestΔC in 65 nm process. Figure 4 compares the phase noise contribution among MASH 1, MASH 1-1, and MASH 1-1-1 SDM; it can be seen that MASH 1-1-1 SDM has the lowest in-band phase noise contribution and the best noise shaping character. Moreover, their out-band phase noise contributions are almost the same. Therefore, 10-bit OTW_FF is dithered with MASH 1-1-1 SDM to control 6-bit fractional capacitor arrays to improve the frequency resolution and decrease the noise contribution. The phase noise contribution of SDM to ADPLL is simulated with MATLAB as shown and it is below −150 dBc/Hz, which means it affects in a small way the whole phase noise performance. In Figure 5, Eq1(z), Eq2(z), and Eq3(z) are the quantization noise of each accumulator. Therefore, the output frequency of SDM can be deduced from (9)C1=OTWF_F+1-z-1∗Eq1zC2=-Eq1z∗z-1+1-z-1∗Eq2zC3=-Eq2z∗z-1+1-z-1∗Eq3zfout=C1z-3+C2z-2-z-3+C3z-1-2z-2+z-3∗KDCO_F=OTWF_F∗z-3+z-11-z-13∗Eq1z∗KDCO_F.Figure 4
The comparison of phase noise contribution of SDM.Figure 5
MASH 1-1-1 sigma-delta modulator.


## 2.3. Class-C DCO’s Negative Feedback Loops

In Figure1, current IBP is chosen to bias M5 providing a level shift voltage. ARCnetwork is used to provide a dc bias voltage, and VBP is higher than the tank common-mode voltage, which permits a larger resonator swing before the M3/M4 is pushed into the triode region. This is the same technique employed to bias the M1/M2. Moreover, a highRC constant of theRC biasing network is used to low-pass filter the noise introduced to VBN and VBP, optimizing the phase noise [5]. Ctail not only integrates the difference between IBN and the current exhausted by the DCO but also filters the high-frequency noise contribution from M1bias/M2bias, improving the phase noise [4].The simulated transient voltage of DCO is given in Figure6(a); Vout is the oscillation output of DCO. Initially, the M1bias/M2bias are diode-connected (at DC) and IBN is mirrored (multiplied byN) to the DCO core, which makes both PMOS and NMOS cross-coupled MOSFET work in saturation region and provide a high transconductance to guarantee a robust start-up. As the oscillator amplitude is increased, the average current IDC depleted by M1bias/M2bias increases and then the superfluous current will be integrated into Ctail reducing VBN and guiding the switching pair M1/M2 to work in Class-C mode. At the same time, VBP increases and pushes PMOS working in Class-C mode. VT is finally changed to the half value of the VDD to offer the common-mode voltage of DCO and the same overdrive of PMOS and NMOS pairs. Figure 6(b) shows the transient simulation result of M1’s current (blue line) when M1 operates at Class-C mode; the tall and short pulses maximize the output oscillation amplitude (red line), which minimizes the phase noise of DCO.Figure 6
Transient voltage waveform of Class-C DCO (a) andM1 current transient simulation result (b).
(a)
(b)Referring to the noise analysis in [10], the proposed DCO’s noise from feedback loop can be inferred in (10), wherevn2-RB,vn2-r0,M5, and vn2-IBare, respectively, the white noise voltage power spectral density by bias resistor RB, bias MOSFET M5, and bias MOSFET M1bias/M2bias. ωp is the single pole in the feedback loop. The gnl2(θc)Γosc2(θc) is the amplification and frequency translation that the feedback loop noise must undergo first.(10)NFL=1T∫-θC/2θC/22vn2¯RB+vn2¯r0,M5+vn2¯IB1+ωp2gnl2θcΓosc2θcdθc=2vn2¯RB+vn2¯r0,M5+vn2¯IB1+ωp2g02fflVOSC.Therefore, the total amount of phase noise can be deduced in (11) where K is Boltzmann constant, Tk is the absolute temperature in Kelvin, C is the capacitor inLC resonant bank, VOSC is the oscillation amplitude of DCO, 2R is the parasitics losses, and γ is the technology coefficient. fcp(VOSC) and ffl(VOSC) are, respectively, weighing factors of cross-coupled MOSFETs and feedback loops. (11)PNΔω=KTkΔω2C2Vosc21R+γαg0fcpVosc+2vn2¯RB+vn2¯r0,M5+vn2¯IBΔω2C2Vosc21+ωp2g02fflVOSC.


## 3. Measurement Results

The Class-C DCO was fabricated in a standard 65 nm CMOS process. Figure7 offers the die photo of Class-C DCO; it occupies the area of 0.21 mm2 without PADs. Figure 8(a) shows that the different phase noise measurement results in 1 MHz frequency offset at the different resonant frequency, which changes with coarse array code from −118.3 dBc/Hz to −114.8 dBc/Hz. The phase noise measurement results of Class-C DCO with SDM and without SDM at 5.054 GHz are shown in Figure 8(b); the 1/f3 corner frequency is about 260 KHz. Although SDM brings spurs, it can be seen that the phase noise performance with SDM is still better than the phase noise performance without SDM. With SDM, it is −116 dBc/Hz and −126 dBc/Hz at 1 MHz and 3 MHz frequency offset, respectively. Figure 8(c) shows the frequency spectrum of DCO at 3.34 GHz; it can be seen that SDM brings spurs about 10 dBc at point 3 and point 4 on the frequency spectrum of DCO, but it can be suppressed by the loop character of ADPLL. Figure 9 shows that the frequency and KDCO_C change versus the coarse array code. The measured KDCO_C is around 24 MHz/LSB with a maximum deviation of 1.64 MHz/LSB. Figure 10(a) displays the KDCO_M at different frequency points, the red line and the blue line show the KDCO_M at 3.32 GHz and 5.45 GHz, respectively, and KDCO_M changes from 1.5 MHz/LSB to 7.4 MHz/LSB across the whole FTR because KDCO_M is proportional to the cube of fCKV as (2) shows. Figure 10(b) gives the KDCO_F at different frequency points, and it changes from 120 KHz/LSB to 455 KHz/LSB through the whole FTR, with the same reason of KDCO_M. After 10-bit SDM, fractional array’s frequency resolution KDCO_F will be divided by 210, so the final frequency resolution varies from 117 Hz to 444 Hz, which is less than 0.1 ppm. When all the varactors change from on-state to off-state, the DCO will work from 3.22 GHz to 5.45 GHz, with the FTR of 51.5%.Figure 7
Die photo of Class-C DCO.Figure 8
Measurement results of phase noise @ 1 MHz offset versus Coarse Code (a) phase noise of Class-C DCO at 5.054 GHz (b) and frequency spectrum with/without SDM (c).
(a)
(b)
(c)Figure 9
Measurement results of frequency range and frequency step of coarse array.Figure 10
Measurement results of frequency range and frequency step of medium array (a) and fine array (b).
(a)
(b)Table1 shows the comparison table of state-of-the-artLC-tank oscillators [2, 6–8]. Without the SDM, this DCO has achieved the frequency resolution of 120 KHz, which is close to other references, but it can be 117 Hz after SDM. Reference [8] is also a complementary Class-C DCO, but this work has better performance than it. Reference [6] is traditionalLC-DCO; this work shows higher FoM than it due to its Class-C mode. This design works at close frequency with [6–8] while displaying wider FTR and better FoMT due to the design and optimization of capacitor arrays.Table 1
Comparison with the state of the art.
[2]
[6]
[7]
[8]
This work
Technology
40 nm
65 nm
16 nm
65 nm
65 nm
Freq. (GHz)
5.11
6.8
3.6
2.2
5.054
FTR (%)
64.6
20
22
9.1
51.5
Power (mW)
8
1
0.6
1.5
3.4
f
m (MHz)
1
3
10
3
3
PN@fm  (dBc/Hz)
−130
−116
−134
−117
−126
Frequency resolution (Hz)
29 K
116 K
1.3 K
-
120 K (wo SDM)/117 (wi SDM)
FoM1 (dBc/Hz)
187
183
188
173
185.2
FoMT2 (dBc/Hz)
203
189
195
172
199.4
1
F
o
M
=
10
log
10
⁡
f
o
s
c
/
f
m
2
1
/
P
D
C
m
W
-
P
N; 2FoMT=FoM1+20log10⁡FTR/10.


## 4. Conclusion

This paper presented a complementary Class-C digitally controlled oscillator (DCO) with differential transistor pairs. With three optimized capacitor arrays and a fractional array dithered by SDM, the DCO works from 3.22 GHz to 5.45 GHz with 51.5% FTR and less than 0.1 ppm frequency resolution. Through two feedback loops, the start-up oscillation is ensured and low power consumption is realized. The achieved phase noise is −126 dBc/Hz at 3 MHz offset from 5.054 GHz with the1/f3 corner frequency of 260 KHz while consuming only 2.8 mA at 1.2 V voltage supply. The final FoM and FoMT are 185.2 dBc/Hz and 199.4 dBc/Hz, respectively.



---

*Source: 4968391-2018-01-31.xml*