# Analysis of Power Transfer Efficiency of Standard Integrated Circuit Immunity Test Methods

Authors: Hai Au Huynh; Hak-Tae Lee; Wansoo Nah; SoYoung Kim
Journal: International Journal of Antennas and Propagation
 (2015)

---

## Abstract

Direct power injection (DPI) and bulk current injection (BCI) methods are defined in IEC 62132-3 and IEC 62132-4 as the electromagnetic immunity test method of integrated circuits (IC). The forward power measured at the RF noise generator when the IC malfunctions is used as the measure of immunity level of the IC. However, the actual power that causes failure in ICs is different from forward power measured at the noise source. Power transfer efficiency is used as a measure of power loss of the noise injection path. In this paper, the power transfer efficiencies of DPI and BCI methods are derived and validated experimentally with immunity test setup of a clock divider IC. Power transfer efficiency varies significantly over the frequency range as a function of the test method used and the IC input impedance. For the frequency range of 15 kHz to 1 GHz, power transfer efficiency of the BCI test was constantly higher than that of the DPI test. In the DPI test, power transfer efficiency is particularly low in the lower test frequency range up to 10 MHz. When performing the IC immunity tests following the standards, these characteristics of the test methods need to be considered.


---

## Body

## 1. Introduction

Advances in integrated circuit (IC) design technology have increased the density of transistors and made the structure of ICs more complex. Furthermore, the operating frequency of ICs has increased. The increase in density and high operating frequency of ICs has made the influence of electromagnetic fields on devices more complex and difficult to analyze. In addition, there are higher expectations for the performance of ICs in terms of electromagnetic immunity, because most ICs operate in environments with electromagnetic waves and disturbance signals. Therefore, the method used to predict the electromagnetic immunity level of an IC during the design stage is extremely important.IEC proposed standards for direct power injection (DPI) and bulk current injection (BCI) [1–3] methods to measure the conductive immunity of ICs to radio-frequency (RF) current and power induced by electromagnetic disturbance. In the DPI method, the RF disturbance power is injected to ports of the device under test (DUT) via a coupling capacitor to cause failure in operation of the DUT. In the BCI method, RF power is injected to cause failure of the DUT by the BCI probe. The maximum forward power level where the DUT still operates correctly is the electromagnetic immunity level of the DUT. Injected RF power is transferred to the chip through noise injection paths including cables, injection capacitors, injection probes, and traces. Some portion of the injected noise power is therefore consumed in the injection path. The actual power that causes chip failure is thus different from the forward power measured at the generator.In related work [4], the authors derived an equation for the power transfer efficiency of the bulk current injection method. Power transfer efficiency was determined as the ratio of power transferred to the chip and the forward power at the RF generator. This equation was confirmed by Agilent Design Systems (ADS) [5] simulation and then applied to estimate the real injected power at the failure point of a DUT operation.In this paper, the power transfer efficiency of the DPI/BCI methods is derived and calculated based on equivalent circuit models of the noise injection path [6–9]. Scattering parameter measurements are used to validate the accuracy of the equivalent circuit models. The immunity of a clock divider IC is tested by DPI and BCI methods and the power transfer efficiencies are obtained. The immunity level of the clock divided circuit is evaluated as the ratio of the power measured at the RF source to the real injected power at the input of the DUT. The DPI power transfer efficiency is compared with the BCI power transfer efficiency, and differences between the two methods were analyzed. The analysis of the power transfer efficiency of the DPI method suggests that there is a significant amount of injected noise power loss due to the reflection at the input port.The rest of this paper is structured as follows. Derivation of the power transfer efficiency equation is shown in Section2. In Section 3, the DPI and BCI equivalent circuit models are explained. Results and discussions are presented in Section 4. Concluding remarks are provided in Section 5.


## 2. Power Transfer Efficiency Derivation

Figure1 shows the basic concept underlying the DPI and BCI test methods. Noise power is generated from a RF generator and injected to the DUT via a coupling capacitor in the DPI method versus a BCI probe in the BCI method. Noise power flows through injection components and PCB traces before entering the chip. The injection path from the RF generator to the chip can be considered to be a two-port network, as shown in Figure 2. The two-port network can be divided into three main parts: RF source, injection path, and load, as shown in Figure 2(a). Figure 2(b) shows the RF power flow and the related scattering parameters. The RF generator has a matching output impedance of Zs=50Ω.Figure 1
The concept of IC immunity test. (a) DPI test. (b) BCI test.
(a)
(b)Figure 2
(a) The 2-port circuit network diagram of the BCI test. (b) The flow of RF power with the scattering parameters and the reflection coefficient.
(a)
(b)The power transfer efficiency,Hp, is defined as the ratio of power at the load (PL) and forward power measured at the RF source (Ps) of the two-port network of Figure 2(b) as expressed in the following equation: (1)Hp=PLPs.The forward power reported from the RF generator is the power transmitted to the load when the load impedance matchesZs, and the forward power of the RF generator is expressed as follows: (2)Ps=18Vs2Zs.The relationship ofV1, V2, and the scattering parameters is expressed in (3) from the signal flow graph shown in Figure 2(b) [10, 11]. Consider(3)V1-=S11V1++S12V2+=S11V1++S12ΓLV2-,V2-=S21V1++S22V2+=S21V1++S22ΓLV2-.Using (3), the power transferred to the test chip, PL, can be expressed as follows [4]: (4)PL=12Z0V2+2-V2-2=12Z0V2-21-ΓL2=Vs28Z0S211-S22ΓL1-Γs1-ΓsΓin21-ΓL2.Γ
s, Γin, and ΓLare the reflection coefficients at the source, input port, and load, respectively. Consider(5)Γs=Zs-Z0Zs+Z0,Γin=V1-V1+=S11+S12ΓLV2-V1+,ΓL=ZL-Z0ZL+Z0.Finally, the equation for power transfer efficiency is derived as follows:(6)Hp=PLPs=ZsZ0S211-S22ΓL1-Γs1-ΓsΓin21-ΓL2.Practically, the power at the injection port of the DPI/BCI test, which is measured at nodeV1, is different from the forward power due to impedance mismatch of the RF source and the rest of the DPI/BCI network. The power at the input of the noise injection port (Pin) considering the reflections at the injection equipment is calculated as follows:(7)Pin=12Z1I12=Vs28Z011-ΓsΓin21-Γs21-Γin2.


## 3.  Equivalent Circuit Model

To determine the DPI/BCI power transfer efficiency, accurate equivalent circuit models for the injection capacitor, injection probe, PCB, package, and IC are needed.


### 3.1. Chip Model

The chip model includes the equivalent circuit model of the package and schematic netlist and parasitic interconnection of the IC. The DUT package is a 208-pin quad flat package (QFP).The IC used in this work is a clock divider that divides the input clock into two lower frequency clocks by a factor of four and sixteen, respectively. The clock divider was designed using a 180 nm Magna process. The block diagram and operation of the clock divider are shown in Figure3. We evaluated the RF noise immunity of the clock divider when noise was injected to the supply voltage, VDD. The parasitic RC components were added to the netlist of the IC using Calibre xRC of Mentor graphics [12] based on the layout created by Cadence [13].Figure 3
Clock divider block and function.To capture the IC reflection characteristics and to perform simulations using ADS, the reflection coefficientS(1,1) of the VDD pin of the clock divider design references to the VSS pin was extracted from the simulation setup shown in Figure 4. S(1,1) was extracted and imported to ADS as the chip core model.Figure 4
IC parameter extraction set-up.The dimensional parameters of package pins, lead frames, and package bonding wires were determined by measuring X-ray pictures of the chip package as shown in Figure5. The equivalent circuit model was obtained using (8) derived from [14]. In the equations, w is the width, t is the thickness, l is the length, and h is the height of the conductor. Consider(8)R=ρlw×t,L=μ0l2πln⁡⁡8hw+t+1,C=ε0εrl1.13wh1+1.44wh0.11+1.46wh0.42.Figure 5
X-ray picture of the chip package.The package equivalent circuit model shown in Figure6 was connected to the IC core model. The VDD/VSS port impedance of IC is shown in Figure 7(a). The Z(1,1) parameter of the circuit including the package and IC core was simulated by ADS and the simulation model is shown in Figure 7(b). The same Z(1,1) parameter was determined by measuring the real chip and compared with simulation results to validate the package and IC core model. The comparison results are shown in Figure 7(c).Figure 6
Equivalent circuit model of the package.Figure 7
Chip model validation. (a) VDD/VSS port impedance of IC. (b) Package and IC simulation setup. (c) Chip VDD/VSS port impedanceZ(1,1) comparison.
(a)
(b)
(c)


### 3.2. DPI Capacitor and BCI Probe Circuit Models

Accurate impedance of the capacitor was obtained from its datasheet. For the High Q/Low ESR (equivalent serial resistor) capacitor model, the ESR value was specified in the product specifications. Using the capacitor value and the resonant frequency specified in the datasheet, the equivalent serial inductance was calculated using (9):(9)L=14π2fres2C,where fres is the resonant frequency of the capacitor. The DPI capacitor equivalent circuit is the combination of the ESR, ESL, and capacitor connected in serial. The mounting pad parasitic of the DPI capacitor was part of the PCB; thus it will be considered in the PCB model. Details of the structure of the DPI capacitor equivalent circuit and its impedance are provided in Figure 8.Figure 8
Impedance and equivalent circuit model of the DPI capacitor.An equivalent circuit model of the BCI probe was created using the method specified in related work [4, 7]. The BCI probe model was F130-1 from Fisher Custom Communications, Inc. The equivalent circuit model of the BCI probe and its insertion loss S(2,1) are shown in Figure 9.Figure 9
Insertion loss and equivalent circuit model of the BCI probe.


### 3.3. PCB Modeling

The PCB used in this paper was designed with four layers, as shown in Figure10. The injection trace and the DPI capacitor were located in the top layer. The second and the third layers were the ground and VDD plane, respectively. The fourth layer was an additional trace to measure the output signal of the DUT. The width of all the traces on the PCB was designed so that the PCB had a characteristic impedance of 50 Ω. The total thickness of the PCB was 0.8 mm, while the distance between the top and ground plane was 0.11 mm and the copper thickness was 0.035 mm. The dielectric layer was prepreg with εr=4.11.Figure 10
PCB dimensional structure.Figure11 shows the PCB used in the DPI test. The SMA connector was used at the injection port and the power supply port. A pad was located in the middle of the transmission trace to mount the DPI capacitor. The DPI transmission trace was divided into segments. PCB traces were located over a ground plane in the second layer; thus they are approximately modeled as a microstrip structure [15]. Each segment was modeled as a RLCG L-network as shown in Figure 12(a). The R, L, G, and C values of the L-network are calculated using the following equation: (10)C=ε0εra×bd,L=μ0dba,G=2πfCtan⁡δ,R=Rdc+Rac=2σctba+2baπfμ0σc.Figure 11
Overview of PCB trace used in DPI test.Figure 12
Validation of PCB equivalent circuit model including DPI capacitor. (a) Equivalent circuit model of a segment. (b)S(2,1) comparison.
(a)
(b)a is the trace length, b is the trace width, d is the dielectric thickness, and t is the conductor thickness. Each trace should be divided into a number of segments whose lengths are less than one-tenth of the wavelength at the maximum test frequency. A similar modeling methodology, π-segment, was applied to the vias used to mount the SMA connect on a PCB [16].To experimentally validate the accuracy of the equivalent circuit model of the noise injection path of the DPI, which included the PCB and DPI capacitor, simulations were performed using ADS to generate the insertion loss between port 1, which is the injection port, and port 2 at the chip footprint, as shown in Figure11. S(2,1) of the real PCB was measured by VNA and compared with the simulation results to validate the PCB equivalent circuit model, as shown in Figure 12(b).The overall equivalent circuit model of the DPI and BCI test method was constructed by combining all the circuit components described above. The final equivalent circuit model structures of DPI and BCI are shown in Figure13. The cable used to connect from RF source to input port was 50 Ω coaxial cable, but the power loss in those cables was neglected in the simulation.Figure 13
Overall simulation model.


## 3.1. Chip Model

The chip model includes the equivalent circuit model of the package and schematic netlist and parasitic interconnection of the IC. The DUT package is a 208-pin quad flat package (QFP).The IC used in this work is a clock divider that divides the input clock into two lower frequency clocks by a factor of four and sixteen, respectively. The clock divider was designed using a 180 nm Magna process. The block diagram and operation of the clock divider are shown in Figure3. We evaluated the RF noise immunity of the clock divider when noise was injected to the supply voltage, VDD. The parasitic RC components were added to the netlist of the IC using Calibre xRC of Mentor graphics [12] based on the layout created by Cadence [13].Figure 3
Clock divider block and function.To capture the IC reflection characteristics and to perform simulations using ADS, the reflection coefficientS(1,1) of the VDD pin of the clock divider design references to the VSS pin was extracted from the simulation setup shown in Figure 4. S(1,1) was extracted and imported to ADS as the chip core model.Figure 4
IC parameter extraction set-up.The dimensional parameters of package pins, lead frames, and package bonding wires were determined by measuring X-ray pictures of the chip package as shown in Figure5. The equivalent circuit model was obtained using (8) derived from [14]. In the equations, w is the width, t is the thickness, l is the length, and h is the height of the conductor. Consider(8)R=ρlw×t,L=μ0l2πln⁡⁡8hw+t+1,C=ε0εrl1.13wh1+1.44wh0.11+1.46wh0.42.Figure 5
X-ray picture of the chip package.The package equivalent circuit model shown in Figure6 was connected to the IC core model. The VDD/VSS port impedance of IC is shown in Figure 7(a). The Z(1,1) parameter of the circuit including the package and IC core was simulated by ADS and the simulation model is shown in Figure 7(b). The same Z(1,1) parameter was determined by measuring the real chip and compared with simulation results to validate the package and IC core model. The comparison results are shown in Figure 7(c).Figure 6
Equivalent circuit model of the package.Figure 7
Chip model validation. (a) VDD/VSS port impedance of IC. (b) Package and IC simulation setup. (c) Chip VDD/VSS port impedanceZ(1,1) comparison.
(a)
(b)
(c)


## 3.2. DPI Capacitor and BCI Probe Circuit Models

Accurate impedance of the capacitor was obtained from its datasheet. For the High Q/Low ESR (equivalent serial resistor) capacitor model, the ESR value was specified in the product specifications. Using the capacitor value and the resonant frequency specified in the datasheet, the equivalent serial inductance was calculated using (9):(9)L=14π2fres2C,where fres is the resonant frequency of the capacitor. The DPI capacitor equivalent circuit is the combination of the ESR, ESL, and capacitor connected in serial. The mounting pad parasitic of the DPI capacitor was part of the PCB; thus it will be considered in the PCB model. Details of the structure of the DPI capacitor equivalent circuit and its impedance are provided in Figure 8.Figure 8
Impedance and equivalent circuit model of the DPI capacitor.An equivalent circuit model of the BCI probe was created using the method specified in related work [4, 7]. The BCI probe model was F130-1 from Fisher Custom Communications, Inc. The equivalent circuit model of the BCI probe and its insertion loss S(2,1) are shown in Figure 9.Figure 9
Insertion loss and equivalent circuit model of the BCI probe.


## 3.3. PCB Modeling

The PCB used in this paper was designed with four layers, as shown in Figure10. The injection trace and the DPI capacitor were located in the top layer. The second and the third layers were the ground and VDD plane, respectively. The fourth layer was an additional trace to measure the output signal of the DUT. The width of all the traces on the PCB was designed so that the PCB had a characteristic impedance of 50 Ω. The total thickness of the PCB was 0.8 mm, while the distance between the top and ground plane was 0.11 mm and the copper thickness was 0.035 mm. The dielectric layer was prepreg with εr=4.11.Figure 10
PCB dimensional structure.Figure11 shows the PCB used in the DPI test. The SMA connector was used at the injection port and the power supply port. A pad was located in the middle of the transmission trace to mount the DPI capacitor. The DPI transmission trace was divided into segments. PCB traces were located over a ground plane in the second layer; thus they are approximately modeled as a microstrip structure [15]. Each segment was modeled as a RLCG L-network as shown in Figure 12(a). The R, L, G, and C values of the L-network are calculated using the following equation: (10)C=ε0εra×bd,L=μ0dba,G=2πfCtan⁡δ,R=Rdc+Rac=2σctba+2baπfμ0σc.Figure 11
Overview of PCB trace used in DPI test.Figure 12
Validation of PCB equivalent circuit model including DPI capacitor. (a) Equivalent circuit model of a segment. (b)S(2,1) comparison.
(a)
(b)a is the trace length, b is the trace width, d is the dielectric thickness, and t is the conductor thickness. Each trace should be divided into a number of segments whose lengths are less than one-tenth of the wavelength at the maximum test frequency. A similar modeling methodology, π-segment, was applied to the vias used to mount the SMA connect on a PCB [16].To experimentally validate the accuracy of the equivalent circuit model of the noise injection path of the DPI, which included the PCB and DPI capacitor, simulations were performed using ADS to generate the insertion loss between port 1, which is the injection port, and port 2 at the chip footprint, as shown in Figure11. S(2,1) of the real PCB was measured by VNA and compared with the simulation results to validate the PCB equivalent circuit model, as shown in Figure 12(b).The overall equivalent circuit model of the DPI and BCI test method was constructed by combining all the circuit components described above. The final equivalent circuit model structures of DPI and BCI are shown in Figure13. The cable used to connect from RF source to input port was 50 Ω coaxial cable, but the power loss in those cables was neglected in the simulation.Figure 13
Overall simulation model.


## 4. Simulation and Measurement Results

The experimental set-up for the DPI test is specified in IEC 62132 part 4 while the BCI test set-up is specified in part 3, as shown in Figure14. In the standard, the test frequency range is 150 kHz~1 GHz. The overall simulation model was specified in the previous section, and the simulation was performed using ADS.Figure 14
Chip immunity test setup. (a) DPI test. (b) BCI test.
(a)
(b)The normal operation output of CLK1 of the clock divider chip, which was used as the DUT of the immunity test, is shown in Figure15(a). RF disturbance power was injected to the power pin (VDD) of the clock divider. The function generator provided the input clock, and the period jitter of the clock output (CLK1) was measured by oscilloscope to determine failure. The clock cycle of the input clock from the function generator was 100 ns, and the period of the CLK1 was 400 ns in simulation. The actual measurement results show that the period of CLK1 signal varied in a range of 399 ns~401 ns (±1 ns) in normal condition. Therefore, in DPI/BCI test, the clock divider was considered to have failed when the period of CLK1 was out-of-range by more than ±1 ns, as shown in Figure 15(b).Figure 15
Measurement results of clock divider operation. (a) Operation under normal conditions. (b) Operation under failure conditions.
(a)
(b)The power transfer efficiencies (Hp) of the BCI and DPI methods were calculated using the equations proposed in Section 2 and compared with ADS simulations results to validate our model. The overall equivalent circuit model for ADS simulation is shown in Figure 13. A scattering parameter for all components in the BCI and DPI two-port networks was used to calculate the power transfer efficiency using the proposed equation. Simulated and calculated BCI and DPI power transfer efficiencies are compared in Figures 16(a) and 16(b). The load condition of the result in Figure 16 is the chip impedance, which is the input impedance of the VDD/VSS port of the clock divider chip as shown in Figure 7. Chip impedance includes the package and chip core equivalent circuit model. The power transfer efficiency (Hp) calculations and ADS simulation results matched well.Figure 16
Power transfer efficiency (Hp) comparison. (a) DPI method. (b) BCI method.
(a)
(b)To further understand DPI/BCI power transfer efficiency and analyze the effect of load condition on efficiency, DPI/BCI power transfer efficiency was plotted for two load conditions: a 50 Ω load and the chip impedance load. When applying chip impedance to the load, power transfer had complex fluctuations due to the complexity of the chip impedance. The results obtained for DPI and BCI with two different loads are shown in Figures17(a) and 17(b), respectively. Load condition did affect the power transfer efficiency of both DPI and BCI methods.Figure 17
Comparison of power transfer efficiency under different load conditions. (a) DPI method. (b) BCI method.
(a)
(b)For a perfect 50 Ω load, the power transfer efficiency was affected only by the injection path. DPI and BCI power transfer efficiencies were compared for the same 50 Ω load condition, as shown in Figure18. At low frequencies, the BCI method had a higher efficiency than the DPI method. In particular, in the frequency range from 1 MHz to 300 MHz, the power transfer efficiency of the BCI method increased significantly due to the design bandwidth of the BCI probe model F130. The DPI power transfer efficiency crossed over the efficiency of BCI in frequency from 150 MHz to 6 GHz. The declination of power transfer efficiency of the DPI method was faster than that of the BCI method in the frequency range higher than 4 GHz due to the slope of the power transfer efficiency.Figure 18
Comparison of DPI and BCI power transfer efficiency. (a) With 50 Ω load. (b) With chip VDD/VSS port impedance load.
(a)
(b)The immunity of the clock divider chip was tested using DPI and BCI test methods under the test conditions specified in the previous section. The forward power (Ps) was measured at each frequency when the chip operation failed. The proposed power transfer equation was applied to calculate the actual delivered power to the chip, which can be used as the actual immunity level of the chip. Delivered power to the chip, PL, was calculated from (11), which is a result of Hp in (6). Consider(11)PLdBm=PsdBm+HpdB.The DPI/BCI immunity test results for the IC using forward power (Ps) measured at the RF source and real injected power (PL) calculated from power transfer efficiency are compared in Figure 19.Figure 19
Measured forward power (Ps) and calculated real injected power (PL) by the power transfer efficiency (HpdB) with chip load. (a) DPI. (b) BCI.
(a)
(b)To analyze the reason for the declination in power transfer efficiency, the forward power at source was set at 0 dBm, and the power at the input port of the DPI and BCI network (Pin) was calculated using (7) and plotted in Figure 20. Due to impedance mismatch, the forward power from the RF source was reflected at the input of the DPI/BCI test equipment. The reflection coefficient S(1,1) parameter of DPI and BCI method is plotted in Figure 21. At low frequencies up to 1 MHz, the reflections of both DPI and BCI method are significantly high; thus most of the forward power is reflected at the input port. From 1 MHz, the reflections are reduced, and the power entering DPI and BCI network increases. The reflection coefficient of BCI was reduced significantly at frequency range of 10~100 MHz and that of DPI was reduced at 100 MHz~1 GHz. These properties explain the differences of the power transfer efficiency between DPI and BCI methods as shown in Figure 18. At high frequencies, a significant amount of power was reflected at the input of the DPI/BCI test equipment due to the increase of the reflection coefficient. Therefore, power transfer efficiency decreases at high frequencies.Figure 20
Comparison of DPI and BCI input power (Pin). (a) With 50Ωload. (b) With chip VDD/VSS port impedance load.
(a)
(b)Figure 21
Comparison of DPI and BCI input reflectionS(1,1) with chip VDD/VSS port impedance load.


## 5. Conclusions

In this paper, model based equations for the power transfer efficiency of the DPI and BCI methods, defined in IEC 62132-3 and IEC 62132-4, were derived. In the DPI and BCI tests, the RF noise power is delivered to the chip through an injection path including the DPI capacitor or BCI probe, traces, and wires. From the power transfer efficiency, the loss when RF power passes through the injection path can be estimated. The real injected power which reflects the actual immunity level of the device under test can be calculated using power transfer efficiency equation. The DPI and BCI immunity tests are performed for the clock divider IC. The magnitudes of the real power that reach the test IC at the chip failure point for each standard immunity test methods are determined using the proposed model.The power transfer efficiencies and the reflected input power of the DPI and BCI test methods are compared. For the test frequency range of 150 kHz to 1 GHz, which is defined in the standard, the power transfer efficiency of BCI method is constantly high. In the DPI test, with a default capacitor value of 6.8 nF, the power transfer efficiency is particularly low in the lower test frequency range up to 10 MHz. This means that even though the engineers perform the DPI test on the IC, due to the high loss in the noise injection path, the RF noise will not reach the IC. If the value of the DPI capacitor is selected to be smaller than 6.8 nF, the low frequency range having small power transfer efficiency is expanded. In future IEC IC immunity test standards, these aspects of the DPI test should be considered.



---

*Source: 497647-2015-05-10.xml*