# MOS Current Mode Logic with Capacitive Coupling

Authors: Kirti Gupta; Neeta Pandey; Maneesha Gupta
Journal: ISRN Electronics
 (2012)

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## Abstract

A new MOS current mode logic (MCML) style exhibiting capacitive coupling to enhance the switching speed of the digital circuits is proposed. The mechanism of capacitive coupling and its effect on the delay are  analytically modeled. SPICE simulations to validate the accuracy of the analytical model have been carried out with TSMC 0.18μm CMOS technology parameters. Several logic gates such as five-stage ring oscillator, NAND, XOR2, XOR3, multiplexer, and demultiplexer based on the proposed logic style are implemented and their performance is compared with the conventional logic gates. It is found that the logic gates based on the proposed MCML style lower the delay by 23 percent. An asynchronous FIFO based on the proposed MCML style has also been implemented as an application.


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## Body

## 1. Introduction

The rapid advances in the VLSI technology have led to the development of high-resolution mixed-signal applications. These applications demand high performance digital circuits to be integrated with analog circuitry on the same chip. MOS current mode logic (MCML) style has been widely used in digital circuits design for mixed-signal applications as they provide an analog friendly environment due to the low switching noise [1–4]. MCML circuits exhibit high switching speed, high noise immunity and better power efficiency at high operating frequencies along with a drawback of static power consumption [5–8].In mixed-signal applications, the digital circuits are extensively used in the realization of digital signal processor functional units such as finite impulse response (FIR) filter and FFT module. The functional units are required to perform computations at high speed to efficiently use the bandwidth in communication systems which is also increasing. Therefore it is necessary to improve the speed of conventional MCML circuits. In this paper, a new MCML style with capacitive coupling that increases the switching speed of the circuits is proposed.The paper first presents a brief introduction to conventional MCML style in Section2. Thereafter, the architecture of the MCML style with capacitive coupling is proposed in Section 3. The mechanism of capacitive coupling is explained, and an expression for the delay is derived. The theoretical propositions are validated through SPICE simulations using TSMC 0.18 μm CMOS technology parameters in Section 4. The simulation results of several logic gates and an asynchronous FIFO are also presented in the same section. Finally, the conclusions are drawn in Section 5.


## 2. Conventional MCML Circuits

A conventional MCML circuit consists of three main components which includes a pull-down network (PDN), a constant current source, and a load circuit. The circuit of a conventional MCML inverter is shown in Figure1. Its PDN consists of a source-coupled transistor pair MC2-MC3 with input A. The constant current source MC1 generates the bias current ISS while the load MC4 determines the output voltage swing [9]. The circuit works on the principle of current steering, where the bias current ISS is steered to one of the circuit branches depending on the input voltage. When the voltage at input A is high, the bias current ISS is steered to transistor MC2 and results in a low VOL (VOL=VDD-VP) at the output node Q and a high voltage (VOH=VDD) at the other node Q- where VP is the voltage drop across the load [9]. Conversely, when the input  A  is low, the bias current ISS is steered to MC3, and a high voltage is obtained at the node Q.Figure 1
Conventional MCML inverter.


## 3. Proposed MCML Style

### 3.1. Basic Architecture

The basic architecture of the proposed MCML style includes a PDN, a constant current source, and a load that exhibits capacitive coupling to increase the switching speed of the circuits. An inverter based on the proposed logic style is shown in Figure2. Its PDN consists of a source-coupled transistor pair M2-M3 to implement the logic function and a current source M1 to generate the bias current ISS. The load includes one NMOS and one PMOS transistors M4-M5 as shown in Figure 2. The reference voltage VREF is chosen to be one threshold voltage above the supply voltage to allow the transistor M4 operation in linear region by making the potential at intermediate node (X,Y) as VREF. The circuit also works on the principle of current steering. The phenomenon of capacitive coupling in the proposed circuit is described in the following section.Figure 2
Proposed MCML inverter.


### 3.2. Capacitive Coupling

In this section, the phenomenon of capacitive coupling in the proposed circuit is described, and an expression for the delay is derived. An expression for conventional MCML inverter delay, using the same method, is also given.


#### 3.2.1. Capacitive Coupling Analysis

The phenomenon of capacitive coupling occurs in the load during the transition at output node voltage. This can be explained by considering the half circuit of the inverter (Figure2) and identifying the capacitances at different nodes in the load (M4-M5). The capacitances are shown in Figure 3 where Cgdi, Cdbi and Cgsi represent the gate-drain capacitance, drain-bulk capacitance and gate-source capacitance of the ith transistor in the load. The capacitances Cgs4 and Cgd5 can be represented by the coupling capacitance between node Q and the intermediate node X as CC (CC=Cgs4+Cgd5) whereas Cgd4 and Cdb5 are the capacitance between node X and ground as CX(CX=Cgd4+Cdb5). Initially, let the voltage at input A is assumed to be equal to high so that the voltage at Q is low (VQ=VOL). For a high-to-low transition at the input, the transistor M2 turns off and the voltage at Q(VQ) begins to rise from VOL  to  VOH. This change in the output voltage gets coupled to node X through CC.Figure 3
Parasitic capacitances of the transistors M4 and M5 in the load circuit.LetiCC and  iCX be the transient currents flowing through CC  and CX, respectively. By applying the KCL, the current equation at node X can be written as
(1)iCC-iCX≈0,
where it is assumed that negligible current flows in transistor M5. Substituting the current values
(2)CXdVXdt≈CCd(VQ-VX)dt
which can be rearranged as
(3)dVXdt=CCCC+CXdVQdt.
It can be observe that an increase in the output voltage will result in an increase in the voltage of the node X. Multiplying (3) by dt and integrating both sides give
(4)∫VREFVX(t)dVX=(CCCC+CX)∫0tdVQdtdt.
Completing the integral on the left side and rearranging it give
(5)VX(t)=VREF+m∫0t(dVQdt)dt,(6)=VREF+m[VQ(t)-VQ(0)],
where m=CC/(CC+CX) represents the capacitance ratio and VREF=VDD+VT. Further VX(t) may be expressed as
(7)VX(t)={VDD+VT+m[VQ(t)-VOL]forVX(0)=VOL…risingoutputVDD+VT-m[VOH-VQ(t)]forVX(0)=VOH…fallingoutput.


#### 3.2.2. Delay

The delay of the proposed MCML inverter can be modeled by solving the state equation of the output node in the time domain [10]. The half circuit of the proposed MCML inverter with the parasitic capacitances of the transistors is shown in Figure 4(a), where Cout represents the output that includes the interconnect capacitance and the input capacitance of the subsequent stage, respectively. The total capacitance at the output node CLis shown in Figure 4(b) which may be computed as
(8)CL=Cgd2+Cdb2+Cgs5+Cgd5+Cgs4+Cout.
The current through capacitor CL may be written as
(9)CLdVQdt=iCL=iD,4-iD,2.(a) Different capacitances in the half circuit of the proposed MCML inverter. (b) Half circuit of the proposed MCML inverter with load capacitanceCL.
(a)
(b)When the input switches from high to low, the current through transistor M2 becomes zero such thatCL begins to charge through the load transistor M4. Thus, (9) reduces to
(10)CLdVQdt=iD,4.The rising output voltage initiates the process of capacitive coupling in the load circuit. It is clear from (7) that the gate potential of M4 remains greater than or equal to VREF during the charging process, hence M4 operates in linear region throughout the switching process. Therefore, the delay tPLH may be calculated by solving (10) as
(11)tPLH=∫t0t1dt=CL∫VOLV50%(1iD,4)dVQ.
Substituting iD,4in (11) results in(12)tPLH=2CLkn,4∫VOLV50%(1[2(VX-VQ-VT)(VDD-VQ)-(VDD-VQ)2])dVQ,wherekn,4 is the transconductance parameter of transistor M4 (13)tPLH=2CLkn,4∫VOLV50%(1(VDD-VQ)[VDD+(2m-1)VQ-2mVOL])dVQ.Evaluating the integral yields(14)tPLH=CLkn,41m(VDD-VOL)×lnVDD-VQVDD+(2m-1)VQ-2mVOL|VOLV50%.
Equation (14) evaluates to
(15)tPLH=CLkn,41m(VDD-VOL)×lnVDD+2m(V50%-VOL)-V50%VDD-V50%.Similar analysis for a conventional MCML inverter (Figure1) gives the delay as(16)tPLH=CLkp,41(VDD+VT,p)[lnVDD+2VT,p+V50%VDD-V50%-lnVDD+2VT,p+VOLVDD-VOL],wherekp,4, and VT,pare the transconductance and the threshold voltage of PMOS transistor MC4, respectively.


## 3.1. Basic Architecture

The basic architecture of the proposed MCML style includes a PDN, a constant current source, and a load that exhibits capacitive coupling to increase the switching speed of the circuits. An inverter based on the proposed logic style is shown in Figure2. Its PDN consists of a source-coupled transistor pair M2-M3 to implement the logic function and a current source M1 to generate the bias current ISS. The load includes one NMOS and one PMOS transistors M4-M5 as shown in Figure 2. The reference voltage VREF is chosen to be one threshold voltage above the supply voltage to allow the transistor M4 operation in linear region by making the potential at intermediate node (X,Y) as VREF. The circuit also works on the principle of current steering. The phenomenon of capacitive coupling in the proposed circuit is described in the following section.Figure 2
Proposed MCML inverter.


## 3.2. Capacitive Coupling

In this section, the phenomenon of capacitive coupling in the proposed circuit is described, and an expression for the delay is derived. An expression for conventional MCML inverter delay, using the same method, is also given.


### 3.2.1. Capacitive Coupling Analysis

The phenomenon of capacitive coupling occurs in the load during the transition at output node voltage. This can be explained by considering the half circuit of the inverter (Figure2) and identifying the capacitances at different nodes in the load (M4-M5). The capacitances are shown in Figure 3 where Cgdi, Cdbi and Cgsi represent the gate-drain capacitance, drain-bulk capacitance and gate-source capacitance of the ith transistor in the load. The capacitances Cgs4 and Cgd5 can be represented by the coupling capacitance between node Q and the intermediate node X as CC (CC=Cgs4+Cgd5) whereas Cgd4 and Cdb5 are the capacitance between node X and ground as CX(CX=Cgd4+Cdb5). Initially, let the voltage at input A is assumed to be equal to high so that the voltage at Q is low (VQ=VOL). For a high-to-low transition at the input, the transistor M2 turns off and the voltage at Q(VQ) begins to rise from VOL  to  VOH. This change in the output voltage gets coupled to node X through CC.Figure 3
Parasitic capacitances of the transistors M4 and M5 in the load circuit.LetiCC and  iCX be the transient currents flowing through CC  and CX, respectively. By applying the KCL, the current equation at node X can be written as
(1)iCC-iCX≈0,
where it is assumed that negligible current flows in transistor M5. Substituting the current values
(2)CXdVXdt≈CCd(VQ-VX)dt
which can be rearranged as
(3)dVXdt=CCCC+CXdVQdt.
It can be observe that an increase in the output voltage will result in an increase in the voltage of the node X. Multiplying (3) by dt and integrating both sides give
(4)∫VREFVX(t)dVX=(CCCC+CX)∫0tdVQdtdt.
Completing the integral on the left side and rearranging it give
(5)VX(t)=VREF+m∫0t(dVQdt)dt,(6)=VREF+m[VQ(t)-VQ(0)],
where m=CC/(CC+CX) represents the capacitance ratio and VREF=VDD+VT. Further VX(t) may be expressed as
(7)VX(t)={VDD+VT+m[VQ(t)-VOL]forVX(0)=VOL…risingoutputVDD+VT-m[VOH-VQ(t)]forVX(0)=VOH…fallingoutput.


### 3.2.2. Delay

The delay of the proposed MCML inverter can be modeled by solving the state equation of the output node in the time domain [10]. The half circuit of the proposed MCML inverter with the parasitic capacitances of the transistors is shown in Figure 4(a), where Cout represents the output that includes the interconnect capacitance and the input capacitance of the subsequent stage, respectively. The total capacitance at the output node CLis shown in Figure 4(b) which may be computed as
(8)CL=Cgd2+Cdb2+Cgs5+Cgd5+Cgs4+Cout.
The current through capacitor CL may be written as
(9)CLdVQdt=iCL=iD,4-iD,2.(a) Different capacitances in the half circuit of the proposed MCML inverter. (b) Half circuit of the proposed MCML inverter with load capacitanceCL.
(a)
(b)When the input switches from high to low, the current through transistor M2 becomes zero such thatCL begins to charge through the load transistor M4. Thus, (9) reduces to
(10)CLdVQdt=iD,4.The rising output voltage initiates the process of capacitive coupling in the load circuit. It is clear from (7) that the gate potential of M4 remains greater than or equal to VREF during the charging process, hence M4 operates in linear region throughout the switching process. Therefore, the delay tPLH may be calculated by solving (10) as
(11)tPLH=∫t0t1dt=CL∫VOLV50%(1iD,4)dVQ.
Substituting iD,4in (11) results in(12)tPLH=2CLkn,4∫VOLV50%(1[2(VX-VQ-VT)(VDD-VQ)-(VDD-VQ)2])dVQ,wherekn,4 is the transconductance parameter of transistor M4 (13)tPLH=2CLkn,4∫VOLV50%(1(VDD-VQ)[VDD+(2m-1)VQ-2mVOL])dVQ.Evaluating the integral yields(14)tPLH=CLkn,41m(VDD-VOL)×lnVDD-VQVDD+(2m-1)VQ-2mVOL|VOLV50%.
Equation (14) evaluates to
(15)tPLH=CLkn,41m(VDD-VOL)×lnVDD+2m(V50%-VOL)-V50%VDD-V50%.Similar analysis for a conventional MCML inverter (Figure1) gives the delay as(16)tPLH=CLkp,41(VDD+VT,p)[lnVDD+2VT,p+V50%VDD-V50%-lnVDD+2VT,p+VOLVDD-VOL],wherekp,4, and VT,pare the transconductance and the threshold voltage of PMOS transistor MC4, respectively.


## 3.2.1. Capacitive Coupling Analysis

The phenomenon of capacitive coupling occurs in the load during the transition at output node voltage. This can be explained by considering the half circuit of the inverter (Figure2) and identifying the capacitances at different nodes in the load (M4-M5). The capacitances are shown in Figure 3 where Cgdi, Cdbi and Cgsi represent the gate-drain capacitance, drain-bulk capacitance and gate-source capacitance of the ith transistor in the load. The capacitances Cgs4 and Cgd5 can be represented by the coupling capacitance between node Q and the intermediate node X as CC (CC=Cgs4+Cgd5) whereas Cgd4 and Cdb5 are the capacitance between node X and ground as CX(CX=Cgd4+Cdb5). Initially, let the voltage at input A is assumed to be equal to high so that the voltage at Q is low (VQ=VOL). For a high-to-low transition at the input, the transistor M2 turns off and the voltage at Q(VQ) begins to rise from VOL  to  VOH. This change in the output voltage gets coupled to node X through CC.Figure 3
Parasitic capacitances of the transistors M4 and M5 in the load circuit.LetiCC and  iCX be the transient currents flowing through CC  and CX, respectively. By applying the KCL, the current equation at node X can be written as
(1)iCC-iCX≈0,
where it is assumed that negligible current flows in transistor M5. Substituting the current values
(2)CXdVXdt≈CCd(VQ-VX)dt
which can be rearranged as
(3)dVXdt=CCCC+CXdVQdt.
It can be observe that an increase in the output voltage will result in an increase in the voltage of the node X. Multiplying (3) by dt and integrating both sides give
(4)∫VREFVX(t)dVX=(CCCC+CX)∫0tdVQdtdt.
Completing the integral on the left side and rearranging it give
(5)VX(t)=VREF+m∫0t(dVQdt)dt,(6)=VREF+m[VQ(t)-VQ(0)],
where m=CC/(CC+CX) represents the capacitance ratio and VREF=VDD+VT. Further VX(t) may be expressed as
(7)VX(t)={VDD+VT+m[VQ(t)-VOL]forVX(0)=VOL…risingoutputVDD+VT-m[VOH-VQ(t)]forVX(0)=VOH…fallingoutput.


## 3.2.2. Delay

The delay of the proposed MCML inverter can be modeled by solving the state equation of the output node in the time domain [10]. The half circuit of the proposed MCML inverter with the parasitic capacitances of the transistors is shown in Figure 4(a), where Cout represents the output that includes the interconnect capacitance and the input capacitance of the subsequent stage, respectively. The total capacitance at the output node CLis shown in Figure 4(b) which may be computed as
(8)CL=Cgd2+Cdb2+Cgs5+Cgd5+Cgs4+Cout.
The current through capacitor CL may be written as
(9)CLdVQdt=iCL=iD,4-iD,2.(a) Different capacitances in the half circuit of the proposed MCML inverter. (b) Half circuit of the proposed MCML inverter with load capacitanceCL.
(a)
(b)When the input switches from high to low, the current through transistor M2 becomes zero such thatCL begins to charge through the load transistor M4. Thus, (9) reduces to
(10)CLdVQdt=iD,4.The rising output voltage initiates the process of capacitive coupling in the load circuit. It is clear from (7) that the gate potential of M4 remains greater than or equal to VREF during the charging process, hence M4 operates in linear region throughout the switching process. Therefore, the delay tPLH may be calculated by solving (10) as
(11)tPLH=∫t0t1dt=CL∫VOLV50%(1iD,4)dVQ.
Substituting iD,4in (11) results in(12)tPLH=2CLkn,4∫VOLV50%(1[2(VX-VQ-VT)(VDD-VQ)-(VDD-VQ)2])dVQ,wherekn,4 is the transconductance parameter of transistor M4 (13)tPLH=2CLkn,4∫VOLV50%(1(VDD-VQ)[VDD+(2m-1)VQ-2mVOL])dVQ.Evaluating the integral yields(14)tPLH=CLkn,41m(VDD-VOL)×lnVDD-VQVDD+(2m-1)VQ-2mVOL|VOLV50%.
Equation (14) evaluates to
(15)tPLH=CLkn,41m(VDD-VOL)×lnVDD+2m(V50%-VOL)-V50%VDD-V50%.Similar analysis for a conventional MCML inverter (Figure1) gives the delay as(16)tPLH=CLkp,41(VDD+VT,p)[lnVDD+2VT,p+V50%VDD-V50%-lnVDD+2VT,p+VOLVDD-VOL],wherekp,4, and VT,pare the transconductance and the threshold voltage of PMOS transistor MC4, respectively.


## 4. Simulation Results

This section first demonstrates the phenomenon of capacitive coupling in the proposed MCML inverter (Figure2) to verify the theoretical propositions presented in Section 3. Thereafter, the performance of the proposed MCML logic style is compared with the conventional MCML logic style by simulating different logic gates. Lastly, the simulation results for an asynchronous FIFO based on the proposed style are presented. All the simulations are performed by using TSMC 0.18 μm CMOS technology parameters with VT=0.5V and a supply voltage of 1.8 V. The bias current of all the circuits is taken as 100 μA uniformly.


### 4.1. Proposed MCML Inverter

The proposed MCML inverter (Figure2) with m=0.6 and VOL=1.4 V is designed and simulated to demonstrate the phenomenon of capacitive coupling. The aspect ratios of the transistors calculated are (W/L)M1=0.81/0.18, (W/L)M2,M3=26.8/0.18, (W/L)M4=0.68/0.18, (W/L)M5=0.54/1.35. The waveforms at the input, X, and output nodes are shown in Figure 5. It can be observed that the rising output voltage increases the voltage of node X which confirms the relation between voltages at node Q and X (3). Also, it can be observed that during a low-to-high transition at the output, for an output voltage VQ=1.8 V the potential at node X raises VX= 2.54 V and is in accordance with (7) in Section 3.Figure 5
Voltages at different nodes of the proposed MCML inverter.The delay of the proposed MCML inverter expressed by (15) is validated for different values of m ranging from 0.1 to 1. The error in the predicted and the simulated delay is plotted for different values of m in Figure 6 and is always is less than 12%. Thus, the simulation results are in close agreement with the theoretical values.Figure 6
Error in the predicted and the simulated delay for the proposed MCML inverter with respect tom.


### 4.2. Performance Comparison

Several logic gates such as inverter, five-stage ring oscillator (RO5), NAND, XOR2, XOR3, multiplexer, and demultiplexer based on the proposed MCML style and conventional MCML style are implemented for the purpose of comparison. The aspect ratios of the transistors in the PDN of the two styles are taken to be same. It may be noted that since all the circuits are implemented with the same supply voltage and bias current, therefore they will consume the same static power which is computed as the product of the supply voltage and bias current [4]. The delay of the gates based on both the logic styles is listed in Table 1. It can be observed that an improvement varying from 16% to 23% can be obtained in delay by using the proposed MCML logic style.Table 1
Delay comparison of logic gates.
Logic gate
Delay of conventional MCML-based circuit (ps)
Delay of proposed MCML-based circuit (ps)
Percentage reduction
Inverter (CL = 50 fF)
209
165
21%
Inverter (CL = 100 fF)
419
340
18%
Inverter (CL = 250 fF)
985
827
16%
Ring Oscillator (RO5)
290
250
14%
NAND
1795
1503
16%
XOR2
1950
1506
22%
XOR3
2153
1800
16%
2 : 1 Multiplexer
1955
1511
23%
1 : 2 Demultiplexer
1988
1600
19.5%


### 4.3. Application Example

An asynchronous FIFO is implemented as an application of the proposed MCML logic style. An asynchronous FIFO connects the sender and the receiver through a data bus consisting of separate request and acknowledge signals, and data signals [11–13]. The block diagram of a 4 stage FIFO is shown in Figure 7. It comprises of four stages wherein each stage consists of a functional unit and a control unit. The functional unit has a combinational stage for computing the result of each stage and a matched delay element inserted in the request line. The control unit employs a double-edge triggered flip-flop (DETFF) and a C element to control the communication between the successive stages. The signals shown as Req(in) and Ack(out) communicate the data, Data(in) between sender and the first stage. At the receiver side, the signals Req(out) and Ack(in) are used to synchronize the output data, Data(out) with the receiver and the last stage. Initially, the input data, Data(in) is loaded in the first stage of the FIFO and the Req(in) is asserted to low to start the data transfer. This results in a transition at the output of a C-element such that the data is stored in the DETFF of the first stage. At the same time an acknowledge signal Ack(out) is given to the sender. The stored data then flows through the different stages in the FIFO. Then, a request signal Req(out) is generated by the last stage to the receiver to enable the receiver to accept the data. This is followed by an acknowledge signal, Ack(in) from the destination to the last stage.Figure 7
Block diagram of 4-stage asynchronous FIFO.The circuits of the control unit elements based on the proposed logic style are shown in Figure8. The waveforms obtained through the simulation of a four-stage asynchronous FIFO are shown below in Figure 9. The first three waveforms correspond to the input data Data(in), request signal (Req_in), and acknowledge signal (Ack_out) at the sender section. The last three graphs are the acknowledge signal Ack(in), data Data(out) and request signal Req(out). It can be found that the asynchronous FIFO based on the proposed logic style outputs the sampled data correctly.Control unit elements based on the proposed MCML style (a) DETFF (b) C-element.
(a)
(b)Figure 9
Transient response of the 4-stage asynchronous FIFO based on the proposed MCML style.


## 4.1. Proposed MCML Inverter

The proposed MCML inverter (Figure2) with m=0.6 and VOL=1.4 V is designed and simulated to demonstrate the phenomenon of capacitive coupling. The aspect ratios of the transistors calculated are (W/L)M1=0.81/0.18, (W/L)M2,M3=26.8/0.18, (W/L)M4=0.68/0.18, (W/L)M5=0.54/1.35. The waveforms at the input, X, and output nodes are shown in Figure 5. It can be observed that the rising output voltage increases the voltage of node X which confirms the relation between voltages at node Q and X (3). Also, it can be observed that during a low-to-high transition at the output, for an output voltage VQ=1.8 V the potential at node X raises VX= 2.54 V and is in accordance with (7) in Section 3.Figure 5
Voltages at different nodes of the proposed MCML inverter.The delay of the proposed MCML inverter expressed by (15) is validated for different values of m ranging from 0.1 to 1. The error in the predicted and the simulated delay is plotted for different values of m in Figure 6 and is always is less than 12%. Thus, the simulation results are in close agreement with the theoretical values.Figure 6
Error in the predicted and the simulated delay for the proposed MCML inverter with respect tom.


## 4.2. Performance Comparison

Several logic gates such as inverter, five-stage ring oscillator (RO5), NAND, XOR2, XOR3, multiplexer, and demultiplexer based on the proposed MCML style and conventional MCML style are implemented for the purpose of comparison. The aspect ratios of the transistors in the PDN of the two styles are taken to be same. It may be noted that since all the circuits are implemented with the same supply voltage and bias current, therefore they will consume the same static power which is computed as the product of the supply voltage and bias current [4]. The delay of the gates based on both the logic styles is listed in Table 1. It can be observed that an improvement varying from 16% to 23% can be obtained in delay by using the proposed MCML logic style.Table 1
Delay comparison of logic gates.
Logic gate
Delay of conventional MCML-based circuit (ps)
Delay of proposed MCML-based circuit (ps)
Percentage reduction
Inverter (CL = 50 fF)
209
165
21%
Inverter (CL = 100 fF)
419
340
18%
Inverter (CL = 250 fF)
985
827
16%
Ring Oscillator (RO5)
290
250
14%
NAND
1795
1503
16%
XOR2
1950
1506
22%
XOR3
2153
1800
16%
2 : 1 Multiplexer
1955
1511
23%
1 : 2 Demultiplexer
1988
1600
19.5%


## 4.3. Application Example

An asynchronous FIFO is implemented as an application of the proposed MCML logic style. An asynchronous FIFO connects the sender and the receiver through a data bus consisting of separate request and acknowledge signals, and data signals [11–13]. The block diagram of a 4 stage FIFO is shown in Figure 7. It comprises of four stages wherein each stage consists of a functional unit and a control unit. The functional unit has a combinational stage for computing the result of each stage and a matched delay element inserted in the request line. The control unit employs a double-edge triggered flip-flop (DETFF) and a C element to control the communication between the successive stages. The signals shown as Req(in) and Ack(out) communicate the data, Data(in) between sender and the first stage. At the receiver side, the signals Req(out) and Ack(in) are used to synchronize the output data, Data(out) with the receiver and the last stage. Initially, the input data, Data(in) is loaded in the first stage of the FIFO and the Req(in) is asserted to low to start the data transfer. This results in a transition at the output of a C-element such that the data is stored in the DETFF of the first stage. At the same time an acknowledge signal Ack(out) is given to the sender. The stored data then flows through the different stages in the FIFO. Then, a request signal Req(out) is generated by the last stage to the receiver to enable the receiver to accept the data. This is followed by an acknowledge signal, Ack(in) from the destination to the last stage.Figure 7
Block diagram of 4-stage asynchronous FIFO.The circuits of the control unit elements based on the proposed logic style are shown in Figure8. The waveforms obtained through the simulation of a four-stage asynchronous FIFO are shown below in Figure 9. The first three waveforms correspond to the input data Data(in), request signal (Req_in), and acknowledge signal (Ack_out) at the sender section. The last three graphs are the acknowledge signal Ack(in), data Data(out) and request signal Req(out). It can be found that the asynchronous FIFO based on the proposed logic style outputs the sampled data correctly.Control unit elements based on the proposed MCML style (a) DETFF (b) C-element.
(a)
(b)Figure 9
Transient response of the 4-stage asynchronous FIFO based on the proposed MCML style.


## 5. Conclusion

In this paper, a new MCML style with capacitive coupling to increase the speed of the digital circuits is proposed. The phenomenon of capacitive coupling occurs in the load of the proposed style. The coupling phenomenon has been explained and analyzed. An expression for the delay has also been derived and validated through SPICE simulations using TSMC 0.18μm CMOS technology parameters. Several logic gates based on the proposed logic style are implemented and their performance is compared with the conventional logic gates. It is found that a delay reduction of up to 23 percent delay reduction can be achieved by employing the proposed MCML style in the design of logic circuits.



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*Source: 473257-2012-11-05.xml*