# Design of CMOS Tunable Image-Rejection Low-Noise Amplifier with Active Inductor

Authors: Ler Chun Lee; Abu Khari bin A'ain; Albert Victor Kordesch
Journal: VLSI Design
 (2007)

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## Abstract

A fully integrated CMOS tunable image-rejection low-noise
amplifier (IRLNA) has been designed using Silterra's
industry standard 0.18μm RF CMOS process. The notch filter is designed using an
active inductor. Measurement results show that the notch filter
designed using active inductor contributes additional
1.19 dB to the noise figure of the low-noise amplifier
(LNA). A better result is possible if the active inductor is
optimized. Since active inductors require less die area, the die
area occupied by the IRLNA is not significantly different from a
conventional LNA, which was designed for comparison. The proposed
IRLNA exhibits S21 of 11.8 dB, S11 of
−17.8 dB,
S22 of
−10.7 dB,
and input 1 dB compression point of
−12 dBm at
3 GHz


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## Body

## 1. Introduction

Recently,
direct-conversion and low-intermediate frequency (low-IF) receivers have   become
highly popular choices in RFIC since they avoid the need for expensive
external passive components such as surface-acoustic wave (SAW) filters for
image rejection. Unfortunately, serious problems do exist for direct-conversion
and low-IF receivers. The direct-conversion receiver is very sensitive to DC
offset and low-frequency interference signals. Since IF of the
direct-conversion receiver is zero, there is a little doubt that flicker noise
will produce a maximum negative effect in direct-conversion receivers. A low-IF
receiver has many of the attributes of a direct-conversion receiver but has
lower sensitivity to DC offsets and flicker noise. However, the image rejection
problem reappears [1].The superheterodyne receiver is the most widely used receiver front-end
architecture and exhibits good RF performance. Proper image signal filtering is
required. This can be done by using external SAW filters. The drawbacks of
using SAW filters are increased cost and device size [2]. To overcome these
problems, recent research has focused on IRLNA that uses a notch filter to
reject the image signals [3–6].Unlike on-chip spiral inductors,  active inductors have smaller die area,
larger inductance, higher-quality factor (Q), tunable inductance, and Q. The Q of the spiral inductor is usually low, this
being due to the wiring and substrate losses. Unfortunately, active inductors
have poor noise performance, poor linearity, and higher-power dissipation, and
are more sensitive to process, voltage supply, and temperature (PVT) variation
compared to spiral inductors.The paper is organized as follows: Section2 introduces the concept and
design of active inductors. Section 3 discusses several popular types of IRLNA
that have been reported in the literature. The proposed IRLNA designed using an
active inductor is presented in Section 4, with measurement results. Section 5
concludes the paper.


## 2. Active Inductor Circuit Design

Active inductor is an attractive
alternative to low-Q on-chip spiral inductors. For monolithic RFIC
applications, the design of the active inductor using gyrator is best described
in Figure 1(a). g1, g2,  C1, and C2 are parasitic conductance and capacitance,
respectively. Gm1 and Gm2 represent transconductors and are connected back-to-back to form a gyrator.
The input admittance of the gyrator circuit, Yin,
is shown as follows: (1)Yin=1Zin=g1+sC1+Gm1Gm2sC2+g2.(a) Active inductor for RFIC applications; (b) simplified model for active inductor.
(a)(b)The third item in (1) behaves as an inductor with resistive loss. Based
on (1), the active inductor can be modeled as a resonator as shown in Figure 1(b), where (2)L=C2Gm1Gm2,rs=g2Gm1Gm2.The active inductor proposed in [7] was used in this design. The
simplified circuit design of the active inductor is shown in Figure 2.
According to [7], if gm1≈gm2>>g2,
thenFigure 2
Simplified circuit diagram of the active inductor used in this
design.(3)Gm1(s)≈0.5gm11+s(Cgs1+C3)/(gm1+gm2+g3), where g3 and C3 are the parasitic conductance and capacitance
at node 3, respectively. The input admittance, Yin in Figure 2, can be calculated from (1) and (3)
as follows: (4)Yin=sC1+g1+Zs−1,Zs≈sC2+[g2−(ω2C2(Cgs1+C3)/(gm1+gm2+g3))]0.5gm1gm3.From (4), the inductance can be tuned by
varying C2,
while Q of the active inductor can be tuned by varying C3.
Hence, two varactors are added at node 2 and node 3 for inductance and Q
tuning, respectively.


## 3. Overview of Existing IRLNA Design

## 3.1. Second-and Third-Order Active Notch Filters

The first fully
integrated IRLNA using a second-order active filter was introduced in [8] using
0.5 μm bipolar technology with 25 GHz transit frequency. The second-order
active notch filter is based on a series LC resonator that resonates at the
image frequency. Figure 3(a) shows the cascade LNA  with the  second-order active filter. The input impedance of the
second-order active notch filter is given by [8] (5)Zin=sLf1+1sCπ+1sCf1+Rind+rbb−gmω2CπCf1, where Cπ, gm,
and rbb are the emitter-base capacitance,
transconductance, and base resistance of Q3. Rind is the resistive loss of the inductor. At
image frequency, the input impedance of the active notch filter becomes
minimum. That will decrease the gain of the LNA. However, the notch filter
might have negative impact on the LNA because the input impedance of the
second-order active notch filter might be lower than the case without the
filter. The power gain and noise figure of the IRLNA will degrade due to the
signal loss.IRLNA
with (a) second-order active notch filter and (b) third-order active notch filter.
(a)(b)To overcome the limitation of the IRLNA proposed in [8], a CMOS
third-order active notch filter has been proposed in [5], as shown in Figure 3(b). Assuming that all the parasitic components are cancelled, the input
impedance of the active notch filter now can be expressed as follows [5]: (6)Zin=s2Lf2Ceq+1s(s2CttLf2Ceq+Ctt+Ceq), where Ctt=C4+Cgs4
and Ceq−1=Cgs4−1+Cf2−1.From (6), the active notch filter proposed in [5] can have high impedance
at the wanted signal frequency and low impedance at the image signal
frequency.


## 3.2. Third-Order Passive Notch Filter

Third-order passive notch
filter technique was proposed in [3] for CMOS IRLNA, as shown in Figure 4. The
input impedance of the passive notch filter as given by [3] is the following: (7)Zin=L2(Cv1+C5)s2+1Cv1C5L2s3+C5s.Figure 4
CMOS IRLNA with
third-order passive notch filter.Similar to the notch filter proposed in [5],
the passive notch filter shown in Figure 4 has low and high input impedance at
image signal frequency and wanted signal frequency, respectively. Since CMOS
spiral inductors usually have very low Q, a cross-connected differential
transistor pair has been used as a negative impedance circuit to increase Q of
the notch filter. The notch frequency tuning of the IRLNA can be done by using
varactor Cv1.


## 4. Proposed IRLNA Using Active Inductor

Since spiral inductors
consume large die area compared to active devices, the use of active inductor
to replace spiral inductor becomes an attractive choice for notch filters.
Circuit diagram of the proposed IRLNA using active inductor is shown in Figure5. The spiral inductor in the notch filter in Figure 4 has been replaced by an
active inductor. Since the notch frequency of the image-rejection notch filter
can be tuned by the active inductor, the varactor in Figure 4 can be
eliminated. If the Q of the active inductor is high enough, the input impedance
of the notch filter shown in Figure 5 is approximated by (7).Figure 5
Complete
schematic for the proposed IRLNA.The wanted signal frequency and image signal frequency are
located at(8)fwanted=±12πLC1,fimage=±12πL(C1+Cs1).The active inductor shown in Figure2 is used to implement our
proposed IRLNA. The active die area for the active inductor including DC
biasing circuits is 70×162 μm2, which is much smaller than a
spiral inductor that typically requires 300×300 μm2. As mentioned
in Section 2, two NMOSs
in N-well varactors were added at node 2 and node 3 for inductance and Q tuning,
respectively. The proposed IRLNA adopts popular source-degenerated LNA
architecture for low-noise, which is shown in Figure 5. An extra capacitor Cex together with Lg and Ls is used to obtain power-constrained
simultaneous noise and input matching [5].As mentioned before,Cs1 together with the active inductor forms a
third-order notch filter for image rejection. All the devices shown in Figure 5
are implemented on-chip.The proposed IRLNA was fabricated using Silterra’s 0.18μm industry
standard RF CMOS process. For comparison, an LNA identical to the proposed
IRLNA but without notch filter was included in the fabrication. The die
micrograph of the LNA and IRLNA is shown in Figure 6. All the DC, S-parameters,
and noise figure measurements were performed on wafer using Cascade Microtech’s
RF probe station with GSG Infinity probes. Due to the DC biasing startup
circuit problem, the actual DC biasing active inductor is different from the
predicted value. Current sources located at node 1 and node 2 of the active
inductor operate in linear region and this lowers Q of the active inductor.
Measured Q of the active inductor returns a value of around 5 to 8, and this is
lower than the expected value. The low-Q active inductor has a negative impact
on the gain and noise performance of the IRLNA.Die micrograph for (a) proposed IRLNA and (b) LNA.
(a)(b)S-parameters of the IRLNA and LNA are shown in
Figures7 and 8. As can be observed from Figure 7, the notch filter designed
using active inductor can provide additional 8.25 dB image rejection at 1.42 GHz. An active inductor with higher Q would further improve the image-rejection
of the notch filter. A comparison between the performance of the proposed IRLNA
and the LNA is shown in Table 1. S21 of the proposed IRLNA is 2.8 dB lower than
the LNA, which is mainly due to the low-Q active inductor.Table 1
Comparison between proposed IRLNA and LNA.
ParametersProposed
IRLNALNAOperating frequency3.06 GHz3.16 GHzS11−17.8 dB−30.7 dBS2111.8 dB14.6 dBS12−29.2 dB−21.5 dBS22−10.7 dB−15.4 dBNoise
figure (NF)Simulation2.73 dB1.44 dBMeasurement6.95 dB5.76 dBMeasurement*4.95 dB3.76 dBNoise
factor (F)Simulation1.871.39Measurement4.953.77Measurement*3.132.381 dB compression point−12 dBm−15 dBmImage-rejection (filter
only)8.25 dB—Image-rejection
tuning range1.25–1.49 GHz—Power
dissipation11 mW7.2 mW* Worst case estimated noise figures after de-embedding losses from
cable and GSG Infinity probe. Actual noise figures will be better.Figure 7
S21
of LNA and proposed IRLNA.Figure 8
S11
and S22 of LNA and proposed IRLNA.In Table1, the noise figures (NFs) of the LNA and IRLNA are much higher than simulation
results. The excess noise is contributed from the losses of Cascade
Microtech
high-frequency cable and GSG Infinity probe that precede the LNA
and IRLNA. The calibration of the noise figure analyzer is unable to remove
these losses. Further experiments showed that the Cascade Microtech high-frequency
cable has additional  loss around 1.3 dB compared to Agilent coaxial cable 11500F. Hence, it
is reasonable to estimate that the loss preceding the LNA, including the input
GSG Infinity probe, is at least 2 dB. In addition, system port mismatch due to
the on-wafer NF measurement will further increase the uncertainties of the NF
measurement [9]. Besides that, there is additional noise probably contributed
by the DC power supply itself. Adding a large capacitor between VDD and ground
can reduce that problem.However, comparing noise factor difference (Fdifference)
between IRLNA and LNA, the measured Fdifference (after de-embedding)
is 56% higher than simulation results. The discrepancy of Fdifference between measurement and simulation may be due to several factors mentioned
below.(a)
Low-Q active
inductor (due to the DC biasing circuit) results in lower gain of the LNA at
the operating frequency. This can be observed from S21 of the LNA and IRLNA
shown in Table 1. IRLNA’s NF increases due to the lower gain.(b)
Actual losses preceding the LNA in the NF measurement
system are more than 2 dB if all the losses (e.g., adapter loss and input port mismatch) are taken into
consideration. Discrepancy ofFdifference in measurement and
simulation will be smaller if all the losses preceding LNA are considered.(c)
Noise contributed from the active inductor is
underestimated. Short-channel NMOS devices contribute more thermal noise than
the value predicted by long-channel theory [10]. Long-channel thermal noise
equation was used in the simulation.Thanks to the
active inductor, the actual die area occupied by the proposed IRLNA is
approximately the same as the LNA.Besides noise
performance, sensitivity of the active inductor to PVT variations is also a
very important design challenge that needs to be considered.gm of the MOSFET is the most sensitive parameter
to PVT variations in the active inductor.
A wider notch frequency tuning range can overcome PVT variations. Some
applications like HIPERLAN require a tuning range of 150 MHz, whereas 802.11a
requires tuning range of 675 MHz to cover the desired
frequency band [1, 3]. The tuning range of the active inductor notch filter in
this paper is limited by the varactor tuning range. A higher tuning range could
be obtained by tuning MOSFET’s gm,
rather than using varactors. The tuning
range (Lmax/Lmin) of active inductors can reach more
than 10:1 [11], which is sufficient to cover all the desired frequency bands
and PVT variations.


## 5. Conclusion

Although the active inductor is noisy and has
limited dynamic range compared to spiral inductors, in this paper we show that
it is usable for IRLNA design. With proper design, the noise contribution from
the active inductor can be reduced to its minimum level. Further improvements
are still in progress, which aim to reduce the active inductor’s noise
contribution, power dissipation, and increase its frequency tuning range to
compensate PVT variations.



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*Source: 479173-2008-02-28.xml*