# Optimization of DC-DC Converters via Geometric Programming

Authors: U. Ribes-Mallada; R. Leyva; P. Garcés
Journal: Mathematical Problems in Engineering
 (2011)

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## Abstract

The paper presents a new methodology for optimizing the design of DC-DC converters. The magnitudes that we take into account are efficiency, ripples, bandwidth, and RHP zero placement. We apply a geometric programming approach, because the variables are positives and the constraints can be expressed in a posynomial form. This approach has all the advantages of convex optimization. We apply the proposed methodology to a boost converter. The paper also describes the optimum designs of a buck converter and a synchronous buck converter, and the method can be easily extended to other converters. The last example allows us to compare the efficiency and bandwidth between these optimal-designed topologies.


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## Body

## 1. Introduction

Methods of mathematical programming are useful in the processes of design in engineering when these processes have to maximize a certain magnitude and when at the same time there are certain design or operating constraints. The optimal design of DC-DC converters has been studied by several authors. Some of them use graphical methods, but these cannot deal with more than two variables simultaneously, and the variables are rarely constrained. Examples of these methods are the efficiency optimization of a monolithic DC-DC converter [1] and the losses optimization in a switching power converter for envelope tracking in RF amplifiers [2].The fact that the expressions used are nonlinear has prompted some authors to use nonlinear programming methods, particularly algorithms based on Lagrangian functions. Important related studies are those of Seeman and Sanders [3], who optimized a switched-capacitor converter design by means of Lagrangian functions, and those of Balachandran and Lee [4] and Wu et al. [5], which describe the optimization of DC-DC converters by means of augmented Lagrangian functions with penalty functions. Other nonlinear programming methods such as the sequential quadratic programming method have also been used for designing of DC-DC converters. For example, Busquets-Monge et al. [6] designed a boost power-factor-corrector converter using this method.In addition to nonlinear programming techniques, other optimizing methods have been used in converter optimization such as genetic algorithms or probabilistic methods. A genetic algorithm was used to optimize harmonic noise in AC/AC converters in [7], and the Monte Carlo search method has been used to optimize the cost, the weight, and the volume of converters for automotive applications in [8].Nevertheless, neither general purpose nonlinear programming methods nor the other aforementioned nonlinear optimization techniques ensure that the global optimum is reached because of a local optimum can stop the searching process. Moreover, in some cases, these methods fail to detect the unfeasibility of the problem.In contrast, unlike other methods that accept any nonlinear function, geometric programming (GP) is able to globally optimize a problem when the objective function and the constraint have a given form. GP ensures that the global solution is readily found or that the unfeasibility is detected very quickly. GP has never been used in the design of DC-DC converters, but it has proved successful in other electrical fields [9–11]. The technique has been used for designing CMOS op-amp [9], electrical transformers [10], and synchronous motors [11].Although researchers in optimization methods have been interested in GP since the 1960s [12], the real advantages of this technique are only starting to be appreciated now. The reason for this is the significant development of interior point methods for solving convex optimization problems in the last fifteen years [13]. GP methods are now extremely efficient and reliable. GP uses the concepts of monomial function and posynomial function as the form to express objective function and constraints; we review these concepts in the following section.In the present paper, we apply GP to the task of sizing DC-DC converter components. Specifically, we impose constraints on voltage ripples, current ripples, bandwidth, RHP zero locations, conduction operation mode, and efficiency. First, we choose efficiency as the objective function, then we do the same for the bandwidth. We apply the technique to a boost converter. Also, in subsequent sections, we apply the technique to a buck converter and a synchronous buck converter, then we compare the performances of them to demonstrate the versatility of the procedure.The paper is organized as follows: we review the GP concepts in Section2. Section 3 describes the designing magnitudes of a boost converter, the optimization program, and the verification of the solution. Section 4 compares the optimal design of a buck converter with that of a synchronous buck converter. Finally, Section 5 summarizes the main conclusions.


## 2. Basics on Geometric Programming

The most well-known optimization method is surely the simplex method. This method readily provides a solution to linear programming problems, that is, problems with a linear objective function subject to linear constraints that limit the selection of variable values. On the other hand, general purpose nonlinear optimization methods deliver a solution for nonlinear problems, but they depend on the starting point, since general purpose nonlinear optimization methods are only able to reach a local optimum. In addition, these optimization methods find it difficult to detect the infeasibility of a problem.In 1984, Narendra Karmarkar [14] developed an algorithm for linear programming which, in contrast to the simplex method, reaches an optimal solution by traversing the interior of the feasible region. Interior point methods readily solve not only linear optimization problems but also convex problems, that is, problems with a convex objective function and convex constraints. Therefore, any optimization problem that can be modeled as a convex problem can be readily solved by interior point algorithms. There is a great deal of software as MATLAB that has coded interior point methods. We review the concepts of convex set and convex function in the following paragraphs.A setC is convex if the line segment between any two points in C lies in C; that is, if for any x1,x2∈C and any θ with 0≤θ≤1, we have(2.1)θx1+(1-θ)x2∈C.Obviously, a generic finite-dimensional real vector spaceRn is convex, and a set of Rn with entirely positives coordinates R++n is also a convex set.A functionf:Rn→R is convex if the domain of f is a convex set and if for all points  x,y belonging to the domain of  f, and given a certain θ with 0≤θ≤1, we have(2.2)f(θx+(1-θ)y)≤f(θx)+f((1-θ)y).Obviously, both linear and affine functions are convex. Another example of convex function iseax on R, for any a∈R. Also, ∑k=1KeakTy+bk and  log(∑k=1KeakTy+bk) are convex functions in R++n [12].There are certain kinds of nonlinear optimization problems, known as geometric programs, that can be transformed into convex optimization problems by means of a logarithmic change of variables. Such problems can be modeled using the concepts of monomial and posynomial function.Given a vectorx=(x1,…,xn)∈R++n, a monomial function is defined as(2.3)g(x)=cx1a1x2a2⋯xnan,
where c is a positive real constant called the monomial coefficient and  a1,…,an are real constants that are referred to as the exponents of the monomial.The sum of monomial functions is named a posynomial function; that is,(2.4)f(x)=∑k=1Kckx1a1kx2a2k⋯xnank.Using these concepts, a geometric program is defined as(2.5)minimizef0(x)subjecttofi(x)≤1i=1,…,m,gj(x)=1j=1,…,p,
where f0,…,fm are posynomial functions and g1,…,gp are monomial functions.The geometric program (2.5) is not convex; however, it can be made convex by means of the change of variables y=log(x) or (x=ey) and replacing fi≤1 with log(fi)≤0 and gj=1 with log(gj)=0. Once transformed, the geometric program is written as(2.6)minimizelog⁡(ey)subjecttolog⁡(fi(ey))≤0i=1,…,m,log⁡(gj(ey))=0j=1,…,p.The geometric program (2.6) can be readily solved using interior point algorithms because it is convex. Thus, modeling an engineering optimization problem as a geometric program solves the problem in a quick and reliable manner. This approach has been used in several engineering problems. In the next section, we analyze design magnitudes in DC-DC converters and confirm that they can be written in posynomial form.


## 3. Optimal Design in Boost Converters

In this section, we revisit losses, ripples, and other magnitudes that appear in the boost converter design process. On the basis of these expressions, we provide an optimal design and evaluate the influence of converter parameters. Specifically, we optimize the efficiency when the current ripple, voltage ripple, the bandwidth, and the RHP zero location are limited. Afterwards, we optimize the bandwidth when efficiency is constrained.


### 3.1. The Design Magnitudes in Boost Converters

Although the expressions are well known, we revisit the expressions for the sake of completeness.Figure1 depicts the boost topology. We consider the following state vector:(3.1)x=[iLvC],
where iL is the inductor current and vC is the output voltage. State equations (3.2) model the converter dynamic behaviour in mode ON (when  Q1  is ON and D1 is inactive) which corresponds to a value of the control signal u=1, and in mode OFF (when Q1 is OFF and D1 is active), which corresponds to u=0. Thus,(3.2)diLdt=-vCL(1-u)+ViLu,dvCdt=iLC(1-u)-vCRC,
where L, C, and R stand for the inductor value, the capacitor value, and the load value, respectively and Vi represents the input voltage. The expressions of the converter model (3.2) are valid only when it works in continuous conduction mode, as restriction (3.5) imposes.Figure 1
Boost converter.A consequence of expression (3.2) is that under the hypothesis of low voltage variation in the capacitor, the current ripple is a triangular waveform whose amplitude depends on its slope during TON and the time that it remains in  TON; namely,(3.3)ΔiL=VidLfs,
where VC is the steady-state output voltage, fs stands for the switching frequency, and d is the switch duty-cycle which corresponds to d=TON/(TON+TOFF).Voltage ripple can be expressed, according to [15], as(3.4)ΔvC=VCdfsCR.In addition to ripple constraints, we impose the following restriction to make the boost converter operate in continuous conduction mode (CCM):(3.5)Lfs>VC2Iod(1-d)2.Another important property that should satisfy a design is to have a good enough bandwidth. The following expression binds the minimal required bandwidthωo:(3.6)ωo=(1-d)LC,ωo>2π(afs),
where a is a percentage of the switching frequency.Given that the boost converter has an RHP zero, we take into account its placement. A design should ensure that the RHP zero location is greater than the crossover frequency; otherwise, the converter will have bad gain and phase margins. The following constraint ensures that the boost converter has good robust margins [16]. This constraint reduces the limitations on dynamical performances caused by the RHP zero(3.7)(1-d)2RL>5(1-d)LC.One of the most important magnitudes in the design of a boost converter is its power consumption, which is made up of conduction losses caused by parasitic resistances, and switching losses caused by parasitic capacitances.We have used a model of losses that consider only parasitic resistances and capacitances. Nevertheless, parasitic inductances related to layout could be taken into account according to expression of [15], but they are usually much less significant than resistive and capacitive parasitic losses.In the following analysis, we consider the MOSFET losses, the diode losses, and the ohmic losses in the inductor and the capacitor.


#### 3.1.1. Dissipated Power in the Switches

In this subsection, we first revisit the power losses in the transistor and then those induced by the diode.The total power consumption of MOSFETPQ1 consists of conduction losses PON and switching losses PSW.QuantitiesPQ1,PON, and PSW can be approximated by(3.8)PQ1=PON+PSW,
where
(3.9)PON=((Io(1-d))2+ΔiL212)DRDS,PSW=(VC-Vf)(Io(1-d)-ΔiL2)TswONfs+(VC-Vf)(Io(1-d)+ΔiL2)TswOFFfs,
where Io/(1-d) stands for the MOSFET average current and TswON and TswOFF represent the transition time to on and to off, respectively. Times TswON and TswOFF depend on the gate drive and MOSFET features, RDS stands for the on-resistance of MOSFET, and Vf represents the forward voltage drop in the body diode.The total power dissipated by the diodePd can be expressed as(3.10)Pd=VfIo(1-d)+QrrSchottkyVcfs,
where QrrSchottky is the reverse recovery charge in the diode. We have considered that the diode is implemented in Schottky technology. For the sake of clarity, we have not taken into account ohmic losses in the diode. Nevertheless, the procedure would allow to consider them adding to expression (3.10) the term rdIrms2, where rd is diode dynamic resistance and Irms2 is the mean square diode current.


#### 3.1.2. Losses at Passive Elements

The inductor is responsible for a substantial portion of the converter’s energy consumption. The losses in this passive element consist of winding losses and core losses, but these can approximately be characterized by a constant equivalent series resistanceRL. Consequently, the power dissipated by the inductive element is expressed as(3.11)Pind=((Io(1-d))2+ΔiL212)RL.Similarly, the capacitor losses can be approximated by(3.12)Pcond=(IeffC)2RC,
where RC is the equivalent series resistance in the capacitive element. The waveform of the capacitor current is shown in Figure 2, and its rms value corresponds to(3.13)IeffC=∫0DTs(-Io)2+∫DTsTs(-2Δic(1-d)Tst+(Δic-Iod))2dt.Figure 2
Waveform of the capacitor current.


#### 3.1.3. Total Power Losses and Efficiency in a Boost Converter

Given the expressions (3.1), (3.2), (3.3), and (3.4), the total power losses in the boost converter are written as(3.14)Pboost=PQ1+Pd+Pind+Pcond.The terms on the right contribute unevenly depending on the operating conditions of the converter.Efficiency is defined as(3.15)η=100PloadPload+Pboost,
where Pload=VCIo is the averaged power at the load.


### 3.2. Geometric Programming for Boost Converter Optimal Design

In this section, we describe an optimization program that can be solved using geometric programming, because the magnitudes are posynomial. Also, we give an example of the procedure for a realistic set of parameters, and finally, we show that the optimum has been reached. Furthermore, we show the influence of small variations around the optimal point on the performance.


#### 3.2.1. Optimization Program for Boost Converters

In this subsection, we minimize the converter power consumption which is equivalent to maximize the efficiency. Our optimization variables are the size of the storing elements and the switching frequency. In addition, we constrain the ripples, the bandwidth, and the RHP zero location and impose the continuous conduction mode. Thus, the following geometric program allows us to optimally design a boost converter:(3.16)minimizeL,C,fs⁡PboostsubjecttoLmin⁡≤L≤Lmax⁡Cmin⁡≤C≤Cmax⁡fsmin⁡≤fs≤fsmax⁡ΔiL≤a%ofIoΔvC≤b%ofVCCMconstraint(3.5)BWconstraint(3.6)RHPzeroconstraint(3.7).


#### 3.2.2. Example of Optimal Design of a Boost Converter

We show the input values used in the example. The input values are the voltage ratio, the MOSFET and diode parameters, and the variable bounds and the ripple bounds.The values for the voltage ratio, MOSFET, and diode parameters are shown in Table1.Table 1
Input values of the design example.
Vi5 VVC10 VIo2 ARDS5.2 mΩTswON10-8 sTswOFF10-8 sQrrdb25·10-8  AQrrSchottky50·10-9 AVf0.9 VTable2 indicates the bounds imposed on the optimization variables. Some of these limits do not constrain performance; however, others do, and it is particularly important to determine which values these are.Table 2
Variable bounds on the design example.
Lmin=0.1 μHLma´x=10 mHCmi´n=0.1 μFCma´x=100 μFfsmi´n=10 kHzfsma´x=800 kHzΔIo<15%IoΔVC<1%VCThe optimum obtained corresponds to(3.17)OptimalvaluesofvariablesL*=79.95μHC*=95.946μFfs*=104.23kHz;OptimalvaluesofobjectivefunctionPboost*=2.097W;CurrentandvoltageripplesandBWΔiL*=0.3AΔvC*=0.1VBW*=908.56Hz;Efficiencyη*=90.5%.In order to illustrate the versatility of the procedure, next, we show the result when the purpose is to maximize the bandwidth when the efficiency is constrained to be greater than 85%(3.2.2)OptimalvaluesofvariablesL*=10.41μHC*=12.5μFfs*=800kHz;OptimalvaluesofobjectivefunctionPboost*=2.44W;CurrentandvoltageripplesandBWΔiL*=0.3AΔvC*=0.1VBW*=6.97kHz;Efficiencyη*=89.12%.It can be seen that solution (3.2.2) has a much better bandwidth than (3.17) but that this is at the expense of an efficiency decrease.


#### 3.2.3. Verification of the Optimal Solution in a Boost Converter

In this subsection, we analyze some plots to verify the optimality of solution (3.17) and to evaluate which constraint limits the efficiency. The plots indicate that any variation that fulfils the constraints around the optimal values (3.16) causes an efficiency decrease. The optimal values of certain variables corresponds to limits of an active restriction, this implies that the relaxation of the limits will increase the efficiency.Figure3 depicts the efficiency with respect to frequency values. Red squares correspond to switching frequency values that do not satisfy the current ripple constraint, and black circles are admissible values. The optimal switching frequency value corresponds to the highest black circle. Therefore, the relaxation of the current ripple constraint will increase the efficiency.Figure 3
3-Efficiency versus switching frequency.Figure4 depicts the variation of inductance value around the optimum. Red squares represent inductance values that do not comply with the current ripple constraint, and black circles represent the admissible values. The minimum inductance that satisfies the restrictions corresponds to the highest black circle.Figure 4
4-Efficiency versus inductance.Figure 5
Efficiency versus capacitance.(a) Buck topology (b) Synchronous buck topology.
(a)(b)Efficiency versus switching frequency. (a) Buck (b) Synchronous buck.
(a)(b)Efficiency versus inductance. (a) Buck (b) synchronous buck.
(a)(b)Efficiency versus capacitor value. (a) Buck (b) synchronous buck.
(a)(b)We proceed similarly for the capacitor design variableC. The next plot shows that a variation around the optimal capacitor has very little influence on the efficiency.This graphical process shows that (3.16) is the optimum result and allows us to determine which variables are limited by the design specifications. Finally, the slope of the lines gives an insight into the efficiency increase when a certain constraint is relaxed. Next, we extend this procedure to the buck converter and the synchronous buck converter.


## 3.1. The Design Magnitudes in Boost Converters

Although the expressions are well known, we revisit the expressions for the sake of completeness.Figure1 depicts the boost topology. We consider the following state vector:(3.1)x=[iLvC],
where iL is the inductor current and vC is the output voltage. State equations (3.2) model the converter dynamic behaviour in mode ON (when  Q1  is ON and D1 is inactive) which corresponds to a value of the control signal u=1, and in mode OFF (when Q1 is OFF and D1 is active), which corresponds to u=0. Thus,(3.2)diLdt=-vCL(1-u)+ViLu,dvCdt=iLC(1-u)-vCRC,
where L, C, and R stand for the inductor value, the capacitor value, and the load value, respectively and Vi represents the input voltage. The expressions of the converter model (3.2) are valid only when it works in continuous conduction mode, as restriction (3.5) imposes.Figure 1
Boost converter.A consequence of expression (3.2) is that under the hypothesis of low voltage variation in the capacitor, the current ripple is a triangular waveform whose amplitude depends on its slope during TON and the time that it remains in  TON; namely,(3.3)ΔiL=VidLfs,
where VC is the steady-state output voltage, fs stands for the switching frequency, and d is the switch duty-cycle which corresponds to d=TON/(TON+TOFF).Voltage ripple can be expressed, according to [15], as(3.4)ΔvC=VCdfsCR.In addition to ripple constraints, we impose the following restriction to make the boost converter operate in continuous conduction mode (CCM):(3.5)Lfs>VC2Iod(1-d)2.Another important property that should satisfy a design is to have a good enough bandwidth. The following expression binds the minimal required bandwidthωo:(3.6)ωo=(1-d)LC,ωo>2π(afs),
where a is a percentage of the switching frequency.Given that the boost converter has an RHP zero, we take into account its placement. A design should ensure that the RHP zero location is greater than the crossover frequency; otherwise, the converter will have bad gain and phase margins. The following constraint ensures that the boost converter has good robust margins [16]. This constraint reduces the limitations on dynamical performances caused by the RHP zero(3.7)(1-d)2RL>5(1-d)LC.One of the most important magnitudes in the design of a boost converter is its power consumption, which is made up of conduction losses caused by parasitic resistances, and switching losses caused by parasitic capacitances.We have used a model of losses that consider only parasitic resistances and capacitances. Nevertheless, parasitic inductances related to layout could be taken into account according to expression of [15], but they are usually much less significant than resistive and capacitive parasitic losses.In the following analysis, we consider the MOSFET losses, the diode losses, and the ohmic losses in the inductor and the capacitor.


### 3.1.1. Dissipated Power in the Switches

In this subsection, we first revisit the power losses in the transistor and then those induced by the diode.The total power consumption of MOSFETPQ1 consists of conduction losses PON and switching losses PSW.QuantitiesPQ1,PON, and PSW can be approximated by(3.8)PQ1=PON+PSW,
where
(3.9)PON=((Io(1-d))2+ΔiL212)DRDS,PSW=(VC-Vf)(Io(1-d)-ΔiL2)TswONfs+(VC-Vf)(Io(1-d)+ΔiL2)TswOFFfs,
where Io/(1-d) stands for the MOSFET average current and TswON and TswOFF represent the transition time to on and to off, respectively. Times TswON and TswOFF depend on the gate drive and MOSFET features, RDS stands for the on-resistance of MOSFET, and Vf represents the forward voltage drop in the body diode.The total power dissipated by the diodePd can be expressed as(3.10)Pd=VfIo(1-d)+QrrSchottkyVcfs,
where QrrSchottky is the reverse recovery charge in the diode. We have considered that the diode is implemented in Schottky technology. For the sake of clarity, we have not taken into account ohmic losses in the diode. Nevertheless, the procedure would allow to consider them adding to expression (3.10) the term rdIrms2, where rd is diode dynamic resistance and Irms2 is the mean square diode current.


### 3.1.2. Losses at Passive Elements

The inductor is responsible for a substantial portion of the converter’s energy consumption. The losses in this passive element consist of winding losses and core losses, but these can approximately be characterized by a constant equivalent series resistanceRL. Consequently, the power dissipated by the inductive element is expressed as(3.11)Pind=((Io(1-d))2+ΔiL212)RL.Similarly, the capacitor losses can be approximated by(3.12)Pcond=(IeffC)2RC,
where RC is the equivalent series resistance in the capacitive element. The waveform of the capacitor current is shown in Figure 2, and its rms value corresponds to(3.13)IeffC=∫0DTs(-Io)2+∫DTsTs(-2Δic(1-d)Tst+(Δic-Iod))2dt.Figure 2
Waveform of the capacitor current.


### 3.1.3. Total Power Losses and Efficiency in a Boost Converter

Given the expressions (3.1), (3.2), (3.3), and (3.4), the total power losses in the boost converter are written as(3.14)Pboost=PQ1+Pd+Pind+Pcond.The terms on the right contribute unevenly depending on the operating conditions of the converter.Efficiency is defined as(3.15)η=100PloadPload+Pboost,
where Pload=VCIo is the averaged power at the load.


## 3.1.1. Dissipated Power in the Switches

In this subsection, we first revisit the power losses in the transistor and then those induced by the diode.The total power consumption of MOSFETPQ1 consists of conduction losses PON and switching losses PSW.QuantitiesPQ1,PON, and PSW can be approximated by(3.8)PQ1=PON+PSW,
where
(3.9)PON=((Io(1-d))2+ΔiL212)DRDS,PSW=(VC-Vf)(Io(1-d)-ΔiL2)TswONfs+(VC-Vf)(Io(1-d)+ΔiL2)TswOFFfs,
where Io/(1-d) stands for the MOSFET average current and TswON and TswOFF represent the transition time to on and to off, respectively. Times TswON and TswOFF depend on the gate drive and MOSFET features, RDS stands for the on-resistance of MOSFET, and Vf represents the forward voltage drop in the body diode.The total power dissipated by the diodePd can be expressed as(3.10)Pd=VfIo(1-d)+QrrSchottkyVcfs,
where QrrSchottky is the reverse recovery charge in the diode. We have considered that the diode is implemented in Schottky technology. For the sake of clarity, we have not taken into account ohmic losses in the diode. Nevertheless, the procedure would allow to consider them adding to expression (3.10) the term rdIrms2, where rd is diode dynamic resistance and Irms2 is the mean square diode current.


## 3.1.2. Losses at Passive Elements

The inductor is responsible for a substantial portion of the converter’s energy consumption. The losses in this passive element consist of winding losses and core losses, but these can approximately be characterized by a constant equivalent series resistanceRL. Consequently, the power dissipated by the inductive element is expressed as(3.11)Pind=((Io(1-d))2+ΔiL212)RL.Similarly, the capacitor losses can be approximated by(3.12)Pcond=(IeffC)2RC,
where RC is the equivalent series resistance in the capacitive element. The waveform of the capacitor current is shown in Figure 2, and its rms value corresponds to(3.13)IeffC=∫0DTs(-Io)2+∫DTsTs(-2Δic(1-d)Tst+(Δic-Iod))2dt.Figure 2
Waveform of the capacitor current.


## 3.1.3. Total Power Losses and Efficiency in a Boost Converter

Given the expressions (3.1), (3.2), (3.3), and (3.4), the total power losses in the boost converter are written as(3.14)Pboost=PQ1+Pd+Pind+Pcond.The terms on the right contribute unevenly depending on the operating conditions of the converter.Efficiency is defined as(3.15)η=100PloadPload+Pboost,
where Pload=VCIo is the averaged power at the load.


## 3.2. Geometric Programming for Boost Converter Optimal Design

In this section, we describe an optimization program that can be solved using geometric programming, because the magnitudes are posynomial. Also, we give an example of the procedure for a realistic set of parameters, and finally, we show that the optimum has been reached. Furthermore, we show the influence of small variations around the optimal point on the performance.


### 3.2.1. Optimization Program for Boost Converters

In this subsection, we minimize the converter power consumption which is equivalent to maximize the efficiency. Our optimization variables are the size of the storing elements and the switching frequency. In addition, we constrain the ripples, the bandwidth, and the RHP zero location and impose the continuous conduction mode. Thus, the following geometric program allows us to optimally design a boost converter:(3.16)minimizeL,C,fs⁡PboostsubjecttoLmin⁡≤L≤Lmax⁡Cmin⁡≤C≤Cmax⁡fsmin⁡≤fs≤fsmax⁡ΔiL≤a%ofIoΔvC≤b%ofVCCMconstraint(3.5)BWconstraint(3.6)RHPzeroconstraint(3.7).


### 3.2.2. Example of Optimal Design of a Boost Converter

We show the input values used in the example. The input values are the voltage ratio, the MOSFET and diode parameters, and the variable bounds and the ripple bounds.The values for the voltage ratio, MOSFET, and diode parameters are shown in Table1.Table 1
Input values of the design example.
Vi5 VVC10 VIo2 ARDS5.2 mΩTswON10-8 sTswOFF10-8 sQrrdb25·10-8  AQrrSchottky50·10-9 AVf0.9 VTable2 indicates the bounds imposed on the optimization variables. Some of these limits do not constrain performance; however, others do, and it is particularly important to determine which values these are.Table 2
Variable bounds on the design example.
Lmin=0.1 μHLma´x=10 mHCmi´n=0.1 μFCma´x=100 μFfsmi´n=10 kHzfsma´x=800 kHzΔIo<15%IoΔVC<1%VCThe optimum obtained corresponds to(3.17)OptimalvaluesofvariablesL*=79.95μHC*=95.946μFfs*=104.23kHz;OptimalvaluesofobjectivefunctionPboost*=2.097W;CurrentandvoltageripplesandBWΔiL*=0.3AΔvC*=0.1VBW*=908.56Hz;Efficiencyη*=90.5%.In order to illustrate the versatility of the procedure, next, we show the result when the purpose is to maximize the bandwidth when the efficiency is constrained to be greater than 85%(3.2.2)OptimalvaluesofvariablesL*=10.41μHC*=12.5μFfs*=800kHz;OptimalvaluesofobjectivefunctionPboost*=2.44W;CurrentandvoltageripplesandBWΔiL*=0.3AΔvC*=0.1VBW*=6.97kHz;Efficiencyη*=89.12%.It can be seen that solution (3.2.2) has a much better bandwidth than (3.17) but that this is at the expense of an efficiency decrease.


### 3.2.3. Verification of the Optimal Solution in a Boost Converter

In this subsection, we analyze some plots to verify the optimality of solution (3.17) and to evaluate which constraint limits the efficiency. The plots indicate that any variation that fulfils the constraints around the optimal values (3.16) causes an efficiency decrease. The optimal values of certain variables corresponds to limits of an active restriction, this implies that the relaxation of the limits will increase the efficiency.Figure3 depicts the efficiency with respect to frequency values. Red squares correspond to switching frequency values that do not satisfy the current ripple constraint, and black circles are admissible values. The optimal switching frequency value corresponds to the highest black circle. Therefore, the relaxation of the current ripple constraint will increase the efficiency.Figure 3
3-Efficiency versus switching frequency.Figure4 depicts the variation of inductance value around the optimum. Red squares represent inductance values that do not comply with the current ripple constraint, and black circles represent the admissible values. The minimum inductance that satisfies the restrictions corresponds to the highest black circle.Figure 4
4-Efficiency versus inductance.Figure 5
Efficiency versus capacitance.(a) Buck topology (b) Synchronous buck topology.
(a)(b)Efficiency versus switching frequency. (a) Buck (b) Synchronous buck.
(a)(b)Efficiency versus inductance. (a) Buck (b) synchronous buck.
(a)(b)Efficiency versus capacitor value. (a) Buck (b) synchronous buck.
(a)(b)We proceed similarly for the capacitor design variableC. The next plot shows that a variation around the optimal capacitor has very little influence on the efficiency.This graphical process shows that (3.16) is the optimum result and allows us to determine which variables are limited by the design specifications. Finally, the slope of the lines gives an insight into the efficiency increase when a certain constraint is relaxed. Next, we extend this procedure to the buck converter and the synchronous buck converter.


## 3.2.1. Optimization Program for Boost Converters

In this subsection, we minimize the converter power consumption which is equivalent to maximize the efficiency. Our optimization variables are the size of the storing elements and the switching frequency. In addition, we constrain the ripples, the bandwidth, and the RHP zero location and impose the continuous conduction mode. Thus, the following geometric program allows us to optimally design a boost converter:(3.16)minimizeL,C,fs⁡PboostsubjecttoLmin⁡≤L≤Lmax⁡Cmin⁡≤C≤Cmax⁡fsmin⁡≤fs≤fsmax⁡ΔiL≤a%ofIoΔvC≤b%ofVCCMconstraint(3.5)BWconstraint(3.6)RHPzeroconstraint(3.7).


## 3.2.2. Example of Optimal Design of a Boost Converter

We show the input values used in the example. The input values are the voltage ratio, the MOSFET and diode parameters, and the variable bounds and the ripple bounds.The values for the voltage ratio, MOSFET, and diode parameters are shown in Table1.Table 1
Input values of the design example.
Vi5 VVC10 VIo2 ARDS5.2 mΩTswON10-8 sTswOFF10-8 sQrrdb25·10-8  AQrrSchottky50·10-9 AVf0.9 VTable2 indicates the bounds imposed on the optimization variables. Some of these limits do not constrain performance; however, others do, and it is particularly important to determine which values these are.Table 2
Variable bounds on the design example.
Lmin=0.1 μHLma´x=10 mHCmi´n=0.1 μFCma´x=100 μFfsmi´n=10 kHzfsma´x=800 kHzΔIo<15%IoΔVC<1%VCThe optimum obtained corresponds to(3.17)OptimalvaluesofvariablesL*=79.95μHC*=95.946μFfs*=104.23kHz;OptimalvaluesofobjectivefunctionPboost*=2.097W;CurrentandvoltageripplesandBWΔiL*=0.3AΔvC*=0.1VBW*=908.56Hz;Efficiencyη*=90.5%.In order to illustrate the versatility of the procedure, next, we show the result when the purpose is to maximize the bandwidth when the efficiency is constrained to be greater than 85%(3.2.2)OptimalvaluesofvariablesL*=10.41μHC*=12.5μFfs*=800kHz;OptimalvaluesofobjectivefunctionPboost*=2.44W;CurrentandvoltageripplesandBWΔiL*=0.3AΔvC*=0.1VBW*=6.97kHz;Efficiencyη*=89.12%.It can be seen that solution (3.2.2) has a much better bandwidth than (3.17) but that this is at the expense of an efficiency decrease.


## 3.2.3. Verification of the Optimal Solution in a Boost Converter

In this subsection, we analyze some plots to verify the optimality of solution (3.17) and to evaluate which constraint limits the efficiency. The plots indicate that any variation that fulfils the constraints around the optimal values (3.16) causes an efficiency decrease. The optimal values of certain variables corresponds to limits of an active restriction, this implies that the relaxation of the limits will increase the efficiency.Figure3 depicts the efficiency with respect to frequency values. Red squares correspond to switching frequency values that do not satisfy the current ripple constraint, and black circles are admissible values. The optimal switching frequency value corresponds to the highest black circle. Therefore, the relaxation of the current ripple constraint will increase the efficiency.Figure 3
3-Efficiency versus switching frequency.Figure4 depicts the variation of inductance value around the optimum. Red squares represent inductance values that do not comply with the current ripple constraint, and black circles represent the admissible values. The minimum inductance that satisfies the restrictions corresponds to the highest black circle.Figure 4
4-Efficiency versus inductance.Figure 5
Efficiency versus capacitance.(a) Buck topology (b) Synchronous buck topology.
(a)(b)Efficiency versus switching frequency. (a) Buck (b) Synchronous buck.
(a)(b)Efficiency versus inductance. (a) Buck (b) synchronous buck.
(a)(b)Efficiency versus capacitor value. (a) Buck (b) synchronous buck.
(a)(b)We proceed similarly for the capacitor design variableC. The next plot shows that a variation around the optimal capacitor has very little influence on the efficiency.This graphical process shows that (3.16) is the optimum result and allows us to determine which variables are limited by the design specifications. Finally, the slope of the lines gives an insight into the efficiency increase when a certain constraint is relaxed. Next, we extend this procedure to the buck converter and the synchronous buck converter.


## 4. A Comparison between Optimal Designs of  Buck Converters and Synchronous Buck Converters

The object of this subsection is to show that the proposed procedure can be used to compare different alternatives once we have ensured that they are optimal. Again, we review the magnitudes of the buck and synchronous buck converter. Figure1 shows these topologies.


### 4.1. The Design Magnitudes

The state equation corresponds, in both cases, to(4.1)diLdt=-VCL+ViLu,dvCdt=iLC-VCRC.Therefore, in the buck and synchronous buck converters, the current and voltage ripples corresponds, respectively, to(4.2)ΔiL=VC(1-d)Lfs,(4.3)ΔvC=VC(1-d)8Lfs2C.The continuous conduction mode constraint is(4.4)Lfs>VC2Io(1-d).And the bandwidth can be expressed by(4.5)ωo=1LC,ωo>2π(10%fs).As in the boost converter, the buck converter’s losses occur in the MOSFET, diode, inductor, and capacitor. In the following subsection, we present each of these losses in detail.


#### 4.1.1. Dissipated Power in Buck Converter Switches

MOSFET losses correspond to(4.6)PQ1=PONQ+PSW,PON=(Io2+ΔiL212)DRDS,PSW=Vi(Io-ΔiL2)TswONfs+Vi(Io+ΔiL2)TswOFFfs.And diode losses are described by(4.7)Pd=VfIo(1-D)+QrrSchottkyVifs.


#### 4.1.2. Losses in Passive Elements

The power dissipated by the inductor is(4.8)Pind=(Io2+ΔiL212)RL.Similarly, the capacitor losses can be described by(4.9)Pcond=(ΔiL212)RC.


#### 4.1.3. Total Power Losses and Efficiency in the Buck Converter

Given the expressions (4.6)–(4.9), the total power losses in the buck converter are written as(4.10)Pbuck=PQ1+Pd+Pind+Pcond.


#### 4.1.4. Dissipated Power at Switches in Synchronous Buck Converter

Losses in the high side MOSFETPQ1 in synchronous buck converter are the same as PQ1 in the buck converter. Losses in the low side MOSFET PQ2 corresponds to(4.1.4)PQ2=PONQ2+Pdb,PONQ2=(Io2+ΔI122)(1-D)RDS,Pdb=Vf(Io-Δi12)Tdead1fs+Vf(Io+Δi12)Tdead2fs+QrrVifs,
where Vf represents the forward voltage drop in the body diode, Tdead1 and Tdead2 are the dead times introduced by the synchronous rectification, and  Qrr corresponds to the body diode charge.In addition, losses in the storage element are the same in both the buck and synchronous buck converter. Hence, the total power losses in the synchronous buck converter are written as(4.12)PSynchronousbuck=PQ1+PQ2+Pind+Pcond.


### 4.2. Optimization Program for Buck Converters and Synchronous Buck Converters

According to expressions (4.10) for the buck converters and (4.12) for the synchronous buck converters, the optimization program is expressed as(4.13)minimizeL,C,fsPbuckorPSynchronousbucksubjecttoLmin⁡≤L≤Lmax⁡Cmin⁡≤C≤Cmax⁡fsmin⁡≤fs≤fsmax⁡ΔiL≤a%ofIoΔvC≤b%ofVCCCMconstraint(4.3)BWconstraint(4.4).In the following section, we instantiate the objective function and the ripple constraints for both converters, and we provide and verify the solution.


#### 4.2.1. Example of Optimal Design

Table3 shows the input values for the buck converter and for the synchronous buck converter.Table 3
Design example input values.
Vi10 VVC5 VIo10 AThe parametersTdead1 and Tdead2 of the synchronous buck converter are equal to 200 ns. The remaining of values are those in Tables 1 and 2.Thus, the optimal values for each case are(4.14)OptimalvaluesofvariablesL*=19.34μHC*=10.98μFfs*=86.18kHzOptimalvaluesofobjectivefunctionPbuck*=5.148WCurrentandvoltageripplesandBWΔiL*=1.5AΔvC*=0.198VBW*=10.92kHzEfficiencyη*=90.66%OptimalvaluesofvariablesL*=8.23μHC*=22.05μFfs*=56.68kHzOptimalvaluesofobjectivefunctionPSynchronousbuck*=1.542WCurrentandvoltageripplesandBWΔiL*=2.25AΔvC*=0.225VBW*=11.81kHzEfficiencyη*=93.57%.As in the boost converter, we try also to optimize the bandwidth when the efficiency greater than 85%. The results are as follows:(4.15)OptimalvaluesofvariablesL*=2.08μHC*=0.31μFfs*=800kHzOptimalvaluesofobjectivefunctionPbuck*=6.38WCurrentandvoltageripplesandBWΔiL*=1.5AΔvC*=0.75VBW*=197.2kHzEfficiencyη*=88.68%OptimalvaluesofvariablesL*=0.58μHC*=1.17μFfs*=800kHzOptimalvaluesofobjectivefunctionPSynchronousbuck*=3.51WCurrentandvoltageripplesandBWΔiL*=2.25AΔvC*=0.3VBW*=192.5kHzEfficiencyη*=86.48%.
Again, there is a bandwidth increment at the expense of an efficiency decrease.


### 4.3. Verification of the Optimal Solution in Buck and Synchronous Buck Converters

The following plots verify that the optimum (4.14) has been reached and show the sensitivity to optimization variables.It can be seen that the synchronous buck converter is more efficient than the buck converter and that the size of storing elements differs greatly.


## 4.1. The Design Magnitudes

The state equation corresponds, in both cases, to(4.1)diLdt=-VCL+ViLu,dvCdt=iLC-VCRC.Therefore, in the buck and synchronous buck converters, the current and voltage ripples corresponds, respectively, to(4.2)ΔiL=VC(1-d)Lfs,(4.3)ΔvC=VC(1-d)8Lfs2C.The continuous conduction mode constraint is(4.4)Lfs>VC2Io(1-d).And the bandwidth can be expressed by(4.5)ωo=1LC,ωo>2π(10%fs).As in the boost converter, the buck converter’s losses occur in the MOSFET, diode, inductor, and capacitor. In the following subsection, we present each of these losses in detail.


### 4.1.1. Dissipated Power in Buck Converter Switches

MOSFET losses correspond to(4.6)PQ1=PONQ+PSW,PON=(Io2+ΔiL212)DRDS,PSW=Vi(Io-ΔiL2)TswONfs+Vi(Io+ΔiL2)TswOFFfs.And diode losses are described by(4.7)Pd=VfIo(1-D)+QrrSchottkyVifs.


### 4.1.2. Losses in Passive Elements

The power dissipated by the inductor is(4.8)Pind=(Io2+ΔiL212)RL.Similarly, the capacitor losses can be described by(4.9)Pcond=(ΔiL212)RC.


### 4.1.3. Total Power Losses and Efficiency in the Buck Converter

Given the expressions (4.6)–(4.9), the total power losses in the buck converter are written as(4.10)Pbuck=PQ1+Pd+Pind+Pcond.


### 4.1.4. Dissipated Power at Switches in Synchronous Buck Converter

Losses in the high side MOSFETPQ1 in synchronous buck converter are the same as PQ1 in the buck converter. Losses in the low side MOSFET PQ2 corresponds to(4.1.4)PQ2=PONQ2+Pdb,PONQ2=(Io2+ΔI122)(1-D)RDS,Pdb=Vf(Io-Δi12)Tdead1fs+Vf(Io+Δi12)Tdead2fs+QrrVifs,
where Vf represents the forward voltage drop in the body diode, Tdead1 and Tdead2 are the dead times introduced by the synchronous rectification, and  Qrr corresponds to the body diode charge.In addition, losses in the storage element are the same in both the buck and synchronous buck converter. Hence, the total power losses in the synchronous buck converter are written as(4.12)PSynchronousbuck=PQ1+PQ2+Pind+Pcond.


## 4.1.1. Dissipated Power in Buck Converter Switches

MOSFET losses correspond to(4.6)PQ1=PONQ+PSW,PON=(Io2+ΔiL212)DRDS,PSW=Vi(Io-ΔiL2)TswONfs+Vi(Io+ΔiL2)TswOFFfs.And diode losses are described by(4.7)Pd=VfIo(1-D)+QrrSchottkyVifs.


## 4.1.2. Losses in Passive Elements

The power dissipated by the inductor is(4.8)Pind=(Io2+ΔiL212)RL.Similarly, the capacitor losses can be described by(4.9)Pcond=(ΔiL212)RC.


## 4.1.3. Total Power Losses and Efficiency in the Buck Converter

Given the expressions (4.6)–(4.9), the total power losses in the buck converter are written as(4.10)Pbuck=PQ1+Pd+Pind+Pcond.


## 4.1.4. Dissipated Power at Switches in Synchronous Buck Converter

Losses in the high side MOSFETPQ1 in synchronous buck converter are the same as PQ1 in the buck converter. Losses in the low side MOSFET PQ2 corresponds to(4.1.4)PQ2=PONQ2+Pdb,PONQ2=(Io2+ΔI122)(1-D)RDS,Pdb=Vf(Io-Δi12)Tdead1fs+Vf(Io+Δi12)Tdead2fs+QrrVifs,
where Vf represents the forward voltage drop in the body diode, Tdead1 and Tdead2 are the dead times introduced by the synchronous rectification, and  Qrr corresponds to the body diode charge.In addition, losses in the storage element are the same in both the buck and synchronous buck converter. Hence, the total power losses in the synchronous buck converter are written as(4.12)PSynchronousbuck=PQ1+PQ2+Pind+Pcond.


## 4.2. Optimization Program for Buck Converters and Synchronous Buck Converters

According to expressions (4.10) for the buck converters and (4.12) for the synchronous buck converters, the optimization program is expressed as(4.13)minimizeL,C,fsPbuckorPSynchronousbucksubjecttoLmin⁡≤L≤Lmax⁡Cmin⁡≤C≤Cmax⁡fsmin⁡≤fs≤fsmax⁡ΔiL≤a%ofIoΔvC≤b%ofVCCCMconstraint(4.3)BWconstraint(4.4).In the following section, we instantiate the objective function and the ripple constraints for both converters, and we provide and verify the solution.


### 4.2.1. Example of Optimal Design

Table3 shows the input values for the buck converter and for the synchronous buck converter.Table 3
Design example input values.
Vi10 VVC5 VIo10 AThe parametersTdead1 and Tdead2 of the synchronous buck converter are equal to 200 ns. The remaining of values are those in Tables 1 and 2.Thus, the optimal values for each case are(4.14)OptimalvaluesofvariablesL*=19.34μHC*=10.98μFfs*=86.18kHzOptimalvaluesofobjectivefunctionPbuck*=5.148WCurrentandvoltageripplesandBWΔiL*=1.5AΔvC*=0.198VBW*=10.92kHzEfficiencyη*=90.66%OptimalvaluesofvariablesL*=8.23μHC*=22.05μFfs*=56.68kHzOptimalvaluesofobjectivefunctionPSynchronousbuck*=1.542WCurrentandvoltageripplesandBWΔiL*=2.25AΔvC*=0.225VBW*=11.81kHzEfficiencyη*=93.57%.As in the boost converter, we try also to optimize the bandwidth when the efficiency greater than 85%. The results are as follows:(4.15)OptimalvaluesofvariablesL*=2.08μHC*=0.31μFfs*=800kHzOptimalvaluesofobjectivefunctionPbuck*=6.38WCurrentandvoltageripplesandBWΔiL*=1.5AΔvC*=0.75VBW*=197.2kHzEfficiencyη*=88.68%OptimalvaluesofvariablesL*=0.58μHC*=1.17μFfs*=800kHzOptimalvaluesofobjectivefunctionPSynchronousbuck*=3.51WCurrentandvoltageripplesandBWΔiL*=2.25AΔvC*=0.3VBW*=192.5kHzEfficiencyη*=86.48%.
Again, there is a bandwidth increment at the expense of an efficiency decrease.


## 4.2.1. Example of Optimal Design

Table3 shows the input values for the buck converter and for the synchronous buck converter.Table 3
Design example input values.
Vi10 VVC5 VIo10 AThe parametersTdead1 and Tdead2 of the synchronous buck converter are equal to 200 ns. The remaining of values are those in Tables 1 and 2.Thus, the optimal values for each case are(4.14)OptimalvaluesofvariablesL*=19.34μHC*=10.98μFfs*=86.18kHzOptimalvaluesofobjectivefunctionPbuck*=5.148WCurrentandvoltageripplesandBWΔiL*=1.5AΔvC*=0.198VBW*=10.92kHzEfficiencyη*=90.66%OptimalvaluesofvariablesL*=8.23μHC*=22.05μFfs*=56.68kHzOptimalvaluesofobjectivefunctionPSynchronousbuck*=1.542WCurrentandvoltageripplesandBWΔiL*=2.25AΔvC*=0.225VBW*=11.81kHzEfficiencyη*=93.57%.As in the boost converter, we try also to optimize the bandwidth when the efficiency greater than 85%. The results are as follows:(4.15)OptimalvaluesofvariablesL*=2.08μHC*=0.31μFfs*=800kHzOptimalvaluesofobjectivefunctionPbuck*=6.38WCurrentandvoltageripplesandBWΔiL*=1.5AΔvC*=0.75VBW*=197.2kHzEfficiencyη*=88.68%OptimalvaluesofvariablesL*=0.58μHC*=1.17μFfs*=800kHzOptimalvaluesofobjectivefunctionPSynchronousbuck*=3.51WCurrentandvoltageripplesandBWΔiL*=2.25AΔvC*=0.3VBW*=192.5kHzEfficiencyη*=86.48%.
Again, there is a bandwidth increment at the expense of an efficiency decrease.


## 4.3. Verification of the Optimal Solution in Buck and Synchronous Buck Converters

The following plots verify that the optimum (4.14) has been reached and show the sensitivity to optimization variables.It can be seen that the synchronous buck converter is more efficient than the buck converter and that the size of storing elements differs greatly.


## 5. Conclusions

The present paper describes a reliable and efficient procedure for optimizing DC-DC converter design that is based on geometric programming. In order to illustrate the procedure, we apply it to a boost converter to show how it optimizes efficiency and bandwidth. Then, we compare optimal designs for a buck converter and a synchronous buck converter, considering both efficiency and bandwidth as optimization functions. We have used plots that show that the optimum has been reached, and they also give an insight into sensitivity to constraint bounds. Proposals to extend the procedure to AC-DC and DC-AC converters are being studied.



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*Source: 458083-2011-09-15.xml*