# Energy-Efficient UART Design on FPGA Using Dynamic Voltage Scaling for Green Communication in Industrial Sector

Authors: D. Haripriya; Keshav Kumar; Anurag Shrivastava; Hamza Mohammed Ridha Al-Khafaji; Vishal Moyal; Sitesh Kumar Singh
Journal: Wireless Communications and Mobile Computing
 (2022)

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## Abstract

In the present scheme of the world, the problem of shortage of power is seen across the world which can be a vulnerability to various communication securities. The scope of proposed research is that it is a step towards completing green communication technology concepts. In order to improve energy efficiency in communication networks, we designed UART using different nanometers of FPGA, which consumes the least amount of energy. This shortage is happening because of expanding of industries across the world and the rapid growth of the population. Therefore, to save the power for our upcoming generation, the globe is moving towards the concept and ideas of green communication and power-/energy-efficient gadget. In this work, a power-efficient universal asynchronous receiver transmitter (UART) is implemented on 28 nm Artix-7 field-programmable gate array (FPGA). The objective of this work is to reduce the power utilization of UART with the FPGA device in industries. To do this, the same authors have used voltage scaling techniques and compared the results with the existing FPGA works.


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## Body

## 1. Introduction

In recent times, it has been observed that the whole globe is suffering from one serious problem which is power deficiency. This is happening all over the globe due to the vast increase in the population as well as industrialization. Therefore, to save power for our upcoming generation, the whole world is going towards the concept of energy-/power-efficient gadgets and green communication technology. The “green communication” refers to methods for conserving energy resources for future generations without affecting current generation use. As a result, UART may be useful in developing green communication concepts. Our research work is a step towards fulfilling the designs of green communication technologies. The green communication enables totally better idea of working, interacting, and cooperating, allowing corporations to go further while reducing pollution, greenhouse gas emissions, and power usage. Many organizations are reluctant to make the switch due to the high initial expenditures. We created UART utilizing various nanometers FPGA, which consumes the least amount of energy, in order to minimize energy usage in communication networks. UART is an abbreviation for universal asynchronous receiver transmitter. UART has a frequency of 1 GHZ, a responsibility cycle of 50%, and a time period of 1 ns. The responsibility cycle of a signal is the amount of time it is used. The power and duty cycle relationship = (PW/T) 100, where D is the responsibility cycle, PW is the pulse width, and T is the signal’s time period. In UART, data is sent at a particular frequency called Baud rate. In the UART time technique, the data is sampled when the baud rates of the receiver and transmitter are properly aligned. In the process of data transfer, the data is sent in an irregular way via UART connection. That is, no clock signal is necessary to transfer data from UART A to UART B. As a result, UART may be useful in developing green communication concepts. The hardware circuit of UART device is associated with microcontrollers, laptops, and CPU of a computer. Sometimes it can be dedicated to an integrated circuit (IC). Despite a lot of new communicating ideas, UART communication is most preferred for serial communication. This is because UART devices are easily integrable, and it only uses two wires to perform the serial communication, which is given in Figure 1.Figure 1
Serial communication in UART [1].The data transfer in UART takes place in the form of packets; i.e., the UART sends data to another UART in the form of packets of bits. Since the communication of data in UART transfers data in an asynchronous manner, that is, for sending data from UART A to UART B, no clock signal is required. Therefore, UART can be beneficial for promoting the ideas of green communication. If we compare the proposed method with existing methods in this research, voltage scaling is used to calculate power, and the findings of the study are compared to previous methodologies. It has been found that researchers have employed a variety of strategies to minimize power consumption in previous studies, yet consumption can still be lowered. The existing works done on UART implementation on FPGA to promote the ideas of green communication are explained in Section2.The present article has been planned into seven sections. Section1 describes the introduction of UART with green communication. Section 2 puts light on related work. The implementation setup and methodology have been mentioned in Section 3. Section 4 described the thermal properties for different voltage values. The power calculation of UART has been discussed in Section 5. Finally, Section 6 portrays the conclusion and possible future works based on the proposed framework.


### 1.1. Field-Programmable Gate Array (FPGA)

Unlike the other microcontrollers, FPGAs are also those gadgets that are composed up of semiconductor materials [2–4]. These devices work similarly to the other microcontrollers but have one distinguished property which makes FPGA more convenient than the other microcontrollers. The major and the most important advantage of using FPGAs is these [5] can be reprogrammed after its manufacturing. The feature of being reprogrammed makes FPGAs handier and convenient to be used than the other microcontrollers [6, 7]. The major building blocks of FPGAs are look-up tables (LUTs), configurable logic blocks (CLBs), flip-flops, input/output (I/O) devices, memory devices, and buffers [8]. The building components of FPGAs are shown in Figure 2. FPGA devices are used for performing the green communication too. Green communication is the techniques in which we tend to save the energy resources for our future generation without compromising the use of present generation. The FPGA version of green computing model of UART is shown in Figure 3.Figure 2
Building blocks of FPGAs.Figure 3
Green computing model of UART.


## 1.1. Field-Programmable Gate Array (FPGA)

Unlike the other microcontrollers, FPGAs are also those gadgets that are composed up of semiconductor materials [2–4]. These devices work similarly to the other microcontrollers but have one distinguished property which makes FPGA more convenient than the other microcontrollers. The major and the most important advantage of using FPGAs is these [5] can be reprogrammed after its manufacturing. The feature of being reprogrammed makes FPGAs handier and convenient to be used than the other microcontrollers [6, 7]. The major building blocks of FPGAs are look-up tables (LUTs), configurable logic blocks (CLBs), flip-flops, input/output (I/O) devices, memory devices, and buffers [8]. The building components of FPGAs are shown in Figure 2. FPGA devices are used for performing the green communication too. Green communication is the techniques in which we tend to save the energy resources for our future generation without compromising the use of present generation. The FPGA version of green computing model of UART is shown in Figure 3.Figure 2
Building blocks of FPGAs.Figure 3
Green computing model of UART.


## 2. Literature Work

The authors created an energy-efficient instruction register for integrating green communication on Virtex 4, Virtex 5, and Virtex 6 FPGAs [9]. As a result, while much work has been done to incorporate the ideas of green communication and energy-/power-efficient devices for future generations on CU with various FPGAs, no work has been done to implement the CU circuit on Kintex-7 ultrascale FPGA, so in this work, the CU circuit is being designed on Kintex-7 ultrascale FPGA to promote green communication techniques.To provide a high-performance FIFO for the CPU while reducing power usage, Saxena et al. [10] employed voltages and frequency scaling techniques to create FPGA-based FIFO architecture. They altered frequency from 20 M Hz to 250 MHz while keeping the voltage constant at 2.3 volt, while for the other experiments, they maintained the frequency constant while varying voltages from 1 volt to 2.3 volt. They concluded that the voltage scaling reduces power usage by 95.79 percent, whereas frequency scaling reduces power consumption by 4.38 percent.Kumar et al. [1] proposed a Spartan-3 and Spartan-6 field-programmable gate arrays that are used to create a low-power transceiver (FPGA). As a transceiver, a universal asynchronous receiver transmitter (UART) device is employed. The power analysis findings are aimed on Spartan-3 and Spartan-6 FPGAs, and the implementation of UART is achievable with EDA tools named Xilinx 14.1. By altering the voltage supply, the change of different power of chips built on FPGA is noticed, for example, input/output (I/O) power consumption, leakage power absorption, signal power utilization, logic power utilization, and the use of complete power. This study examines how voltage changes affect the power consumption of the UART on Spartan-3 and Spartan-6 FPGA devices. Spartan-6 is proven to be more power efficient as the voltage supply is increased.In the current international situation, the global energy crisis is a very serious concern. The energy crisis in India, as well as a scarcity of natural resources such as crude oil, coal, and other minerals, has an impact on the country’s economy [11]. Global demand for energy has risen dramatically as a result of population increase and industrial development. So, in order to save energy, we are creating a UART with FPGAs that uses less power. The universal asynchronous receiver transmitter, or UART, is a serial data transfer device. For data transfer, just two wires are required in UART. Not only that, but there are no clock signals needed to run UART. When the voltage is at its maximum, the UART creates less noise and interference, allowing the signal to travel further [12, 13]. The writers created an electronic control unit (ECU) on FPGA to control the vehicle’s system. For parallel work, the reduced instruction set computer (RISC) machine (ARM) processor is utilized in conjunction with FPGA [14].Kumar and Pandey [14] used stub series terminated logic (SSTL) IO with three distinct FPGAs with varying nanometer (nm) gate sizes: 28 nm SP AR TAN-7, 20 nm KINTEX-7 ultrascale, and 16 nm ZYNQ ultrascale+. The model was created and implemented using the VIV ADO ISE tool. According to the power study, the 16 nm ZYNQ ultrascale+ requires the most power for operation with SSTL18 I IO, while the 28 nm SP AR TAN-7 requires the least power for operation with SSTL135 IO, and the 20 nm KINTEX-7 ultrascale sits in the middle of both of these devices.Pandey et al. [5] proposed that a power-efficient control unit (CU) is designed and implemented on the Kintex-7 ultrascale FPGA. The VIVADO HLx design suite is used to simulate and analyze the control unit. The energy consumed of the control unit is examined for various frequency values, and it is discovered that as the frequency grows, so does the total power consumption. As a result, the control unit is better suited to operate at low frequencies in order to reduce power consumption. In addition, lowering the device operating frequency of the control unit from 5 GHz to 100 MHz reduces the overall power usage by 36%.


## 3. Implementation Setup and Methodology

The implementation and simulation of UART protocol with FPGA are done on XILINX ISE design suite [5, 15]. The results of power consumption of UART are observed for various input voltage ranging from 2.5 V to 0.75 V which is shown in Figure 4. The power calculation is done by X power analyzer tool [16, 17].Figure 4
Voltage range for power calculation.


## 4. Thermal Properties for Different Voltage Values

The three thermal possessions are related to FPGA which are termed such as(i)
Effective thermal resistance to air (effective TJA) (oC/W). It shows how the power is distributed to ambient air. For all the value of voltage it is 3.3°C/W [18–20](ii)
Maximum (max) ambient temperature (MAT) (°C). Under operating conditions, it is expressed as the temperature around the FPGA [21–23](iii)
Junction temperature (JT) (°C). It is called as the operational temperature of the FPGA [5, 24]. It is the aggregate total on chips power, effective TJA, and MAT [5]The thermal properties with all the voltage range of values for UART protocol for Artix-7 FPGA are represented in Figure5.Figure 5
Thermal properties for different voltage values.


## 5. Power Calculation of UART

The total power (TP) dissipation of UART protocol on FPGA device is the sum up of the dynamic power (DP) of the device and the static power (SP) of the device [25, 26]. Although there are a large number of innovative communication concepts, serial communication via UART is still the most popular. This is due to the ease with which UART devices may be integrated and the fact that serial communication is accomplished with only two wires. The dynamic power is the power calculated when there is any switching in the device, whereas the static power is the steady-state power of the device. In a FPGA device the clock, logic, IO, and signal power are the device static power, whereas the leakage power is the device dynamic power [3, 4]. Whenever the transmission rates of the transmitter and the receiver are suitably aligned, the data is sampled using the UART time approach. Microcontrollers, laptops, and a computer’s CPU are all connected to the physical circuit of a UART device. Sometimes, it can be dedicated to an integrated circuit (IC).
(1)TP=DP+Sp.


### 5.1. Power Analysis for 2.5 V Voltage

When the voltage is set to 2.5 V for the power calculation, then, there is no SP consumption for the FPGA device; that is, the SP is 0.00 W. On the other hand, the DP, which is the leakage power consumption, is 2.074 W. Hence, the TP of the UART for 2.5 V is 2.075 W. The TP for the voltage of 2.5 V is shown in Figure6.Figure 6
TP for the voltage of 2.5 V.


### 5.2. Power Analysis for 2.0 V Voltage

When the voltage is set to 2.0 V, the TP consumption of the device becomes 0.420 W. For 2.0 V voltage, the leakage power is 0.420 W. There is no consumption of SP for the device at this level of voltage. The TP at this voltage value is equivalent to the leakage power of the FPGA. The power consumption for 2.0 V voltage is represented in Figure7.Figure 7
TP for the voltage of 2.0 V.


### 5.3. Power Analysis for 1.5 V Voltage

For the voltage value of 1.5 V, the device DP is 0.110 W, and there is no power utilization of SP. Hence, the TP for this voltage becomes similar to the DP. The TP utilization for this voltage is 0.111 W. The power consumption for this value of voltage is described in Figure8.Figure 8
TP for the voltage of 1.5 V.


### 5.4. Power Analysis for 1.0 V Voltage

When the voltage is regulated to 1.0 V for the power calculation, then, there is no SP consumption for the FPGA device that is the SP is 0.00 W. On the other hand, the DP, which is the leakage power consumption, is 0.042 W. Hence, the TP of the UART for 2.5 V is 0.043 W. The TP for the voltage of 1.0 V is shown in Figure9.Figure 9
TP for the voltage of 1.0 V.


### 5.5. Power Analysis for 0.9 V Voltage

When the voltage is tweaked to 0.9 V, the TP consumption of the device becomes 0.038 W. For 0.9 V voltage, the leakage power is 0.037 W. There is no consumption of SP for the device at this level of voltage. The TP at this voltage value is equivalent to the leakage power of the FPGA. The power consumption for 0.9 V voltage is represented in Figure10.Figure 10
TP for the voltage of 0.9 V.


### 5.6. Power Analysis for 0.75 V Voltage

When the voltage is regulated to 0.75 V for the power calculation, then, there is no SP consumption for the FPGA device; that is, the SP is 0.00 W. On the other hand, the DP, which is the leakage power consumption, is 0.033 W. Hence, the TP of the UART for 0.75 V is 0.033 W. The TP for the voltage of 0.75 V is shown in Figure11.Figure 11
TP for the voltage of 0.75 V.By analyzing the power, it can be seen that as the value of voltage drops, the power consumption gets decreased. The power consumption is higher for 2.5 V voltage and lower for 0.75 V voltage. The TP consumption for all the value of voltages is represented in Figure12.Figure 12
TP for all voltage values.


### 5.7. Comparative Power Analysis

From the related work section, it is observed that a lot of work has been done by the researchers to optimize the power consumption of the UART protocol. The voltage scaling method is used to calculate power, and the findings of the study are compared to previous methodologies. It has been found that researchers have employed a variety of strategies to minimize power consumption in previous studies, yet consumption can still be lowered. In this section, we have compared our best results with the existing work in recent times. In this work, we have found that the power consumption of UART is optimized when the input supplied voltage is 0.75 V. Of all the rest of the values of voltages, the power consumption is higher as it is explained in Section4. The comparative power analysis of our work with the other existing work is described in Table 1.Table 1
Comparative power analysis.
S. noReferenceFPGAPower (W)1.[9]Virtex 617.2262.[10]Virtex 62.2443.[1]Virtex 61.2934.[11]Virtex 645.3345.[12]Kintex 71.8046.[13]Virtex 40.1777.[14]Virtex 61.4078.[27]Spartan 60.2969.[28]Spartan 60.29710.[4]Spartan 30.08011.This workArtix 70.033From Table1, it can be seen that in [9] using the capacitance scaling technique, the TP consumption is 17.226 W. When the thermal characteristics are adjusted in [10], the power usage is 2.244 W. On the Virtex-6 FPGA, TP consumption reaches 1.2936 W in [1]. By adjusting the capacitance at the output load in [11], the power dissipation is increased to 45.334 W. [12] uses multiple IO standards to reduce the TP consumption on the Kintex-7 FPGA to 1.804 W. The power dissipation in [13] is 0.177 W due to the utilization of numerous FPGAs with varied nanoscale technologies. The power consumption of UART is 1.407 W in [14] when various IO standards are used. On the Spartan-6 FPGA, the UART power reaches 0.296 W in [27]. Using the frequency scaling technique, [28] determined that the power usage of the UART is 0.297 W. In [4] with the idea of voltage scaling, the power consumption of UART is 0.080 W on Spartan-3 FPGA. But in our work, the power of UART reaches to 0.033 W, by applying the voltage scaling approach on 28 nm Artix-7 FPGA. The comparison of the total power consumption of our proposed method with the existing techniques is shown in Figure 13.Figure 13
Total power comparisons.The problem of energy shortage is affecting the entire planet. This is occurring as a result of massive population and industry expansion throughout the world. As a result, the entire globe is attempting to embrace green communication technology and power/energy saving gadgets. This project is only focused on these technologies. The dynamic power is computed when the device is switched on; meanwhile, the static power is determined when the device is in its stable state. At 2.0 V voltage, there is no use of SP by the gadget. At this voltage level, the TP is equal to the FPGA’s leakage power. When the voltage is controlled at 1.0 V for power calculations, the FPGA device consumes no SP, resulting in an SP of 0.00 W. When the voltage is increased to 0.9 V, the device’s TP consumption drops to 0.038 W. The leakage power at 0.9 V voltage is 0.037 W. When looking at the power, it can be seen that when the voltage value decreases, the power consumption increases.


## 5.1. Power Analysis for 2.5 V Voltage

When the voltage is set to 2.5 V for the power calculation, then, there is no SP consumption for the FPGA device; that is, the SP is 0.00 W. On the other hand, the DP, which is the leakage power consumption, is 2.074 W. Hence, the TP of the UART for 2.5 V is 2.075 W. The TP for the voltage of 2.5 V is shown in Figure6.Figure 6
TP for the voltage of 2.5 V.


## 5.2. Power Analysis for 2.0 V Voltage

When the voltage is set to 2.0 V, the TP consumption of the device becomes 0.420 W. For 2.0 V voltage, the leakage power is 0.420 W. There is no consumption of SP for the device at this level of voltage. The TP at this voltage value is equivalent to the leakage power of the FPGA. The power consumption for 2.0 V voltage is represented in Figure7.Figure 7
TP for the voltage of 2.0 V.


## 5.3. Power Analysis for 1.5 V Voltage

For the voltage value of 1.5 V, the device DP is 0.110 W, and there is no power utilization of SP. Hence, the TP for this voltage becomes similar to the DP. The TP utilization for this voltage is 0.111 W. The power consumption for this value of voltage is described in Figure8.Figure 8
TP for the voltage of 1.5 V.


## 5.4. Power Analysis for 1.0 V Voltage

When the voltage is regulated to 1.0 V for the power calculation, then, there is no SP consumption for the FPGA device that is the SP is 0.00 W. On the other hand, the DP, which is the leakage power consumption, is 0.042 W. Hence, the TP of the UART for 2.5 V is 0.043 W. The TP for the voltage of 1.0 V is shown in Figure9.Figure 9
TP for the voltage of 1.0 V.


## 5.5. Power Analysis for 0.9 V Voltage

When the voltage is tweaked to 0.9 V, the TP consumption of the device becomes 0.038 W. For 0.9 V voltage, the leakage power is 0.037 W. There is no consumption of SP for the device at this level of voltage. The TP at this voltage value is equivalent to the leakage power of the FPGA. The power consumption for 0.9 V voltage is represented in Figure10.Figure 10
TP for the voltage of 0.9 V.


## 5.6. Power Analysis for 0.75 V Voltage

When the voltage is regulated to 0.75 V for the power calculation, then, there is no SP consumption for the FPGA device; that is, the SP is 0.00 W. On the other hand, the DP, which is the leakage power consumption, is 0.033 W. Hence, the TP of the UART for 0.75 V is 0.033 W. The TP for the voltage of 0.75 V is shown in Figure11.Figure 11
TP for the voltage of 0.75 V.By analyzing the power, it can be seen that as the value of voltage drops, the power consumption gets decreased. The power consumption is higher for 2.5 V voltage and lower for 0.75 V voltage. The TP consumption for all the value of voltages is represented in Figure12.Figure 12
TP for all voltage values.


## 5.7. Comparative Power Analysis

From the related work section, it is observed that a lot of work has been done by the researchers to optimize the power consumption of the UART protocol. The voltage scaling method is used to calculate power, and the findings of the study are compared to previous methodologies. It has been found that researchers have employed a variety of strategies to minimize power consumption in previous studies, yet consumption can still be lowered. In this section, we have compared our best results with the existing work in recent times. In this work, we have found that the power consumption of UART is optimized when the input supplied voltage is 0.75 V. Of all the rest of the values of voltages, the power consumption is higher as it is explained in Section4. The comparative power analysis of our work with the other existing work is described in Table 1.Table 1
Comparative power analysis.
S. noReferenceFPGAPower (W)1.[9]Virtex 617.2262.[10]Virtex 62.2443.[1]Virtex 61.2934.[11]Virtex 645.3345.[12]Kintex 71.8046.[13]Virtex 40.1777.[14]Virtex 61.4078.[27]Spartan 60.2969.[28]Spartan 60.29710.[4]Spartan 30.08011.This workArtix 70.033From Table1, it can be seen that in [9] using the capacitance scaling technique, the TP consumption is 17.226 W. When the thermal characteristics are adjusted in [10], the power usage is 2.244 W. On the Virtex-6 FPGA, TP consumption reaches 1.2936 W in [1]. By adjusting the capacitance at the output load in [11], the power dissipation is increased to 45.334 W. [12] uses multiple IO standards to reduce the TP consumption on the Kintex-7 FPGA to 1.804 W. The power dissipation in [13] is 0.177 W due to the utilization of numerous FPGAs with varied nanoscale technologies. The power consumption of UART is 1.407 W in [14] when various IO standards are used. On the Spartan-6 FPGA, the UART power reaches 0.296 W in [27]. Using the frequency scaling technique, [28] determined that the power usage of the UART is 0.297 W. In [4] with the idea of voltage scaling, the power consumption of UART is 0.080 W on Spartan-3 FPGA. But in our work, the power of UART reaches to 0.033 W, by applying the voltage scaling approach on 28 nm Artix-7 FPGA. The comparison of the total power consumption of our proposed method with the existing techniques is shown in Figure 13.Figure 13
Total power comparisons.The problem of energy shortage is affecting the entire planet. This is occurring as a result of massive population and industry expansion throughout the world. As a result, the entire globe is attempting to embrace green communication technology and power/energy saving gadgets. This project is only focused on these technologies. The dynamic power is computed when the device is switched on; meanwhile, the static power is determined when the device is in its stable state. At 2.0 V voltage, there is no use of SP by the gadget. At this voltage level, the TP is equal to the FPGA’s leakage power. When the voltage is controlled at 1.0 V for power calculations, the FPGA device consumes no SP, resulting in an SP of 0.00 W. When the voltage is increased to 0.9 V, the device’s TP consumption drops to 0.038 W. The leakage power at 0.9 V voltage is 0.037 W. When looking at the power, it can be seen that when the voltage value decreases, the power consumption increases.


## 6. Conclusion and Future Scope

In the work introduced in this research, we have implemented UART on 28 nm Artix-7 FPGA for green communication. The analysis and simulation are implemented on XILINX design suite, and the power calculation is done through X power analyzer. The purpose of this research is to lower the power usage of UART in companies using an FPGA device. The scientists employed voltage scaling techniques to accomplish this and compared the findings to previous FPGA work. In this work, the power calculation is done by scaling voltage, and the results of the analysis are compared with the existing techniques. It is observed that in the existing works, researchers have used a lot of different techniques to reduce the power consumption, but the consumption can be reduced up to 0.080 W of power in [1]. In the other work, the power consumption is relatively more than the power consumption in [1]. From comparing our results with [1], it is found that in our proposed design, the power consumption is reduced up to 58.75%. The implementation of UART can be done on the upcoming advanced ultrascale and ultrascale+ FPGAs in future. Later these designs can be converted into ASIC design which is handier and portable than FPGAs.



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