# Switched Capacitor Based High Step-Up Multilevel Inverter with Self-Balancing Ability and Low Switching Stress

Authors: M. Venkatesan; S. Gouse Basha; A. Ramkumar; R. Manikandan; M. Easwaran; Baseem Khan
Journal: International Transactions on Electrical Energy Systems
 (2022)

---

## Abstract

In this article, the switched capacitor (SC) based high step-up multilevel inverter is proposed with self-balancing capability. The proposed SC inverter topology is to step up the high output voltage from the very low input voltage without any bulky transformer. This proposed inverter generates single-phase AC voltage with a frequency of 50 Hz from a very low DC input voltage of 50 V with any intermediate DC-DC conversion stage. Hence, the proposed SC inverter is highly suitable for fuel cell, photovoltaic (PV) applications, and shunt active power filter (SAPF). To control the SC inverter, a multicarrier pulse width modulation (PWM) technique is engaged in the inverter. The high step-up voltage level can be achieved by the charging and discharging process of the SC. Furthermore, the stress voltage of the switches does not exceed the applied voltage and the total standing voltage of the inverter is greatly reduced without H-bridges. The comparative analysis of the proposed SC inverter is made for the components, peak inverse voltage (PIV), total standing voltage (TSV), boosting ability, and voltage balancing of capacitors. The main theme of the paper is producing a thirteen-level sinusoidal current with acceptable total harmonic distortion (THD) at different loads, low PIV, TSV, high boosting ability, and self-balancing of capacitors with fewer passive components. The whole system is examined by using MATLAB/Simulink.


---

## Body

## 1. Introduction

The researcher and industrialist focus on the high-quality output voltage for various applications due to the advancement of power electronics converter topologies and their benefits. For both domestic and industrial applications, there is a rising demand for high-quality and reliable electricity essential especially in aerospace industries. The design of an inverter unit is a very crucial task with a high-quality output voltage for grid-connected applications [1]. Two ways are applied to convert DC-AC conversion. In most of the applications, the intermediate stage is involved for DC-DC conversion and it is followed by DC-AC conversion [2]. But, the problem in the two-stage conversion is the involvement of passive components, dc-link voltage problem, and boosting ability limitations. But, a single-stage converter is failed to enhance the output voltage required levels. In the above conversion process, two or three-level inverters are used and are unable to generate high voltages without adding harmonics, switching losses, and operating limits. Voltage stress, harmonics, capacitor voltage balancing, and total standing voltage are all issues that MLIs face [3]. A self-balanced SC-based MLI is designed to resolve these issues. MLIs have become very popular in industrial applications because they result in less THD than a conventional two-level inverter. MLIs are used in a wide range of applications, including energy conversion, hybrid cars, and uninterruptible power supplies [4]. In the face of their popularity, classical MLIs have many issues, including the need for more switches, gate driver circuits, capacitor voltage, and balancing for multiple output levels [5]. Researchers and industry leaders are concentrating on new topologies that address the issues with traditional MLIs. They are primarily focused on reducing the number of switches, driver circuits, voltage balancing, and complexity requirements [6]. MLI topologies are designed using a diversity of features, including DC sources, capacitors, semiconductor switches, modularity, output levels, peak inverse voltage (PIV), and total standing voltage (TSV) [7]. MLIs based on switched capacitors have been used for a few years to solve problems with classical inverters. Conferring to the literature [8], five-level SC inverters with self-balancing capacitor voltages have been developed. In [9], discusses a seven-level SC-based inverter topology with boosting capability. In [10], presents a nine-level switched-capacitor-based inverter with quadruple boosting capability. In [11], proposes a self-balanced nine-level SC inverter that uses two DC sources that can be boosted. Four DC sources are used in [12] to create a 13-level inverter, which is quite expensive for DC voltage sources. Furthermore, the authors investigated 13-level inverters by using two DC sources and a few power switches as well in [13]. In [14] complexity and cost of a fifteen-level inverter with four DC sources are debated. Due to H-bridges, the multiport SC-based multilevel inverter has high switching stress and total standing voltage. An SC-based 13-level inverter with a high step-up boost and self-balancing capacity is proposed to resolve the shortcomings of conventional MLIs. In the aero industry, size and weight are a serious concern, which is why designs that realize the same efficiency with smaller volumes are favored in many applications, even with their higher cost. These inverters are suitable for SAPF applications.


### 1.1. Motivation and Research Questions

According to the study, in many applications, a traditional PWM inverter is used to transform DC to AC voltage. In such operations, a conventional inverter generates the higher harmonic content in the output and also requires a large DC-link voltage. To reduce the harmonic content, a passive filter is applied at the output side and the inverter is subjected to a higher operating frequency. Furthermore, a VSI inverter is developed with an intermediate stage (DC-DC converter) for aerospace applications. From the disputes, the conventional VSI generates more harmonic content and a passive filter is required to compensate for it. On the other hand, intermediate stage-based VSI generates the high output voltage from the low input DC voltage. The problem is more losses due to the additional DC-DC conversion stage. To overcome the inadequacies of the conventional inverter, MLIs topologies are proposed by the researchers. The conventional MLI topologies are producing staircase waveforms and are also able to operate at higher operating frequencies. However, the conventional MLIs are required more DC-link capacitors, several switching devices for constructing higher level MLIs, and voltage balancing issues. For many applications, the quality of the voltage and size, as well as weight, is needed to consider while designing inverter circuits. Therefore, the design of the inverter is a very curial task. In this proposed work, a switched-capacitor-based high step-up inverter is proposed without any DC-DC converter from the very low input voltage. The proposed topology has a simple structure, easy to analyze, and low cost due to a single DC source, a simple gate driver circuit, and no additional DC-DC conversion stage. The proposed inverter is designed to generate single-phase AC voltage with a frequency of 50 Hz from low-power DC sources. The additional feature of the proposed topology has a voltage that gains 5 times of applied voltage. The multicarrier phase disposition PWM control scheme is used to drive the gate pulses of the proposed inverter. The capacitors charge and discharge the voltages by the self-balancing process. The blocking voltage of each switch used in this topology has the same voltage which equals the applied voltage.


## 1.1. Motivation and Research Questions

According to the study, in many applications, a traditional PWM inverter is used to transform DC to AC voltage. In such operations, a conventional inverter generates the higher harmonic content in the output and also requires a large DC-link voltage. To reduce the harmonic content, a passive filter is applied at the output side and the inverter is subjected to a higher operating frequency. Furthermore, a VSI inverter is developed with an intermediate stage (DC-DC converter) for aerospace applications. From the disputes, the conventional VSI generates more harmonic content and a passive filter is required to compensate for it. On the other hand, intermediate stage-based VSI generates the high output voltage from the low input DC voltage. The problem is more losses due to the additional DC-DC conversion stage. To overcome the inadequacies of the conventional inverter, MLIs topologies are proposed by the researchers. The conventional MLI topologies are producing staircase waveforms and are also able to operate at higher operating frequencies. However, the conventional MLIs are required more DC-link capacitors, several switching devices for constructing higher level MLIs, and voltage balancing issues. For many applications, the quality of the voltage and size, as well as weight, is needed to consider while designing inverter circuits. Therefore, the design of the inverter is a very curial task. In this proposed work, a switched-capacitor-based high step-up inverter is proposed without any DC-DC converter from the very low input voltage. The proposed topology has a simple structure, easy to analyze, and low cost due to a single DC source, a simple gate driver circuit, and no additional DC-DC conversion stage. The proposed inverter is designed to generate single-phase AC voltage with a frequency of 50 Hz from low-power DC sources. The additional feature of the proposed topology has a voltage that gains 5 times of applied voltage. The multicarrier phase disposition PWM control scheme is used to drive the gate pulses of the proposed inverter. The capacitors charge and discharge the voltages by the self-balancing process. The blocking voltage of each switch used in this topology has the same voltage which equals the applied voltage.


## 2. Multilevel Switched-Capacitor Inverter

A multilevel-based high step-up switched-capacitor inverter is proposed. Figure1 shows the single-stage conversion which converts DC voltage into AC voltage with any intermediate stage. To generate 230 V, 50 Hz, an SC-based high step-up multilevel inverter is designed for various applications without any intermediate stage. The proposed switched-capacitor inverter circuit consists of five switched cells and each switched cell has one switched capacitor. A thirteen-level SC inverter is formed by connecting the five switched cells in sequence and it is depicted in Figure 2.Figure 1
. A single-stage voltage source inverter (VSI).Figure 2
. A high step-up SC multilevel inverter.The main idea of a switched capacitor is to increase the output voltage from a very low DC input voltage. The input DC voltage comes from low-power sources including batteries, solar panels, and fuel cells.During charging of the capacitor, the input DC source is connected in parallel to the capacitor through the switchesSa2 and Sa5. The charges in the capacitor will be discharged positively by conducting the switches Sa2 and Sa3 i.e., +Vdc. Similarly, switches Sa1 and Sa4 will be conducted to discharge the capacitor negatively, which is equal to −Vdc. It is observed that the switching pairs (Sa1,Sa2) and (Sa3, Sa4) are operated complementary for turn-on and turn-off processes. Initially, the five capacitors are completely charged, which equals the input DC voltage by connecting in parallel with the input DC source. To obtain the required staircase output, the charged capacitors will be discharged in series at the desired switching frequency. Table 1 shows the various modes of operation and the states of the capacitor.Table 1
. Modes of operation and state of capacitors.
Voltage levelConduction of switchesConduction of diodesState of capacitorsC1C2C3C4C5+VdcSa3, Sb2, Sc2, Sd2, Se2, Sf2, Sa2Sb4, Sc4, Sd4, Se4, Sf4↑↑↑↑↑+2VdcSa3, Sb2, Sb3, Sc2, Sd2, Se2, Sf2, Sa2Sc4, Sd4, Se4, Sf4↓↑↑↑↑+3VdcSa3, Sb2, Sb3, Sc2, Sc3,Sd2, Se2, Sf2, Sa2Sd4, Se4, Sf4↓↓↑↑↑+4VdcSa3, Sb2, Sb3, Sc2, Sc3,Sd2, Sd3, Se2, Sf2, Sa2Se4,Sf4↓↓↓↑↑+5VdcSa3, Sb2, Sb3, Sc2, Sc3,Sd2, Sd3, Se2, Se3, Sf2, Sa2Sf4↓↓↓↓↑+6VdcSa3, Sb2, Sb3, Sc2, Sc3,Sd2, Sd3, Se2, Se3, Sf2, Sf3, Sa2—↓↓↓↓↓−6VdcSa1, Sf4, Sf1, Se4, Se1,Sd4, Sd1, Sc4, Sc1,Sb4, Sb1, Sa4—↓↓↓↓↓−5VdcSa1, Sf4, Se4, Se1,Sd4, Sd1, Sc4, Sc1,Sb4, Sb1, Sa4Sf2↓↓↓↓↑−4VdcSa1, Sf4, Se4, Sd4, Sd1, Sc4, Sc1,Sb4, Sb1, Sa4Sf2, Se2,↓↓↓↑↑−3VdcSa1, Sf4, Se4, Sd4, Sc4, Sc1,Sb4, Sb1, Sa4Sf2, Se2, Sd2↓↓↑↑↑−2VdcSa1, Sf4, Se4, Sd4, Sc4, Sb4, Sb1, Sa4Sf2, Se2, Sd2, Sc2↓↑↑↑↑−VdcSa1, Sf4, Se4, Sd4, Sc4, Sb4, Sa4Sf2, Se2, Sd2, Sc2, Sb2↑↑↑↑↑↑ = Charging; ↓ = Discharging.


## 3. Carrier-Based PWM Control

In terms of regulating output voltage and reducing harmonic content, PWM control techniques are essential. Furthermore, a harmonic reduction is in line with the switching frequency. In carrier PWM control, the magnitude and frequency of all carriers are equal. (N-1) carriers are decided for the N-level inverter for realizing the N-level inverter output voltage. Among the carrier-based PWM, PD is generating high-quality output voltage [15]. To generate the gate pulses for the high step-up SC inverter, a multicarrier-dependent Phase Disposition PWM scheme can be used. As shown in Figure 3, the amplitude of high frequency twelve carrier triangular signals (C1–C12) is compared with the magnitude of the fundamental frequency sinusoidal reference signal. At timing instants, t1–t6 produces positive voltage levels, and the timing instants t13–t18 produce negative levels of output. For the carrier signal amplitude ACi = 1, reference signal magnitude Ar = 5.9, fr = 50 Hz, and Fs = 20 KHz, then the timing instants are given as follows:(1)ti=sin−1Aci/Ar2πfr,where, i = time instants 1, 2, 3….(2)t1=sin−11/Ar2πfr,t2=sin−12/Ar2πfr.(3)t3=sin−13/Ar2πfr.Figure 3
. PWM control logic.The flowchart of the switching strategy is given in Figure4. Initially, the sinusoidal reference signal (Vr), positive carrier signal (Vcp), and negative carrier signal (Vcn) are initialized. At first, the sinusoidal reference signal (Vr) is compared with the positive carrier signal (Vcp) i.e., if Vr > Vcp is satisfied, then the pulses are given to the switches Sa1,Sb1, Sc1, Sd1, Se1, and Sf1, and if Vr > Vcp is not satisfied, then the pulses are given to the switches Sa2,Sb2, Sc2, Sd2, Se2, and Sf2. Similarly, the negative carrier signal (Vcn) is compared with a sinusoidal reference signal (Vr), i.e., if Vr < Vcn is satisfied, then the pulses are given to Sa3,Sb3, Sc3, Sd3, Se3, and Sf3, and if Vr < Vcn is not satisfied, then the pulses are generated to the switches Sa4,Sb4, Sc4, Sd4, Se4, and Sf4. The modulation index (MI) for the proposed high step-up 13-level inverter is represented in the following equation:(4)MI=Ar6AC.Figure 4
. Switching logic implementation.


## 4. Simulation Results

For the validation of the findings, the proposed high step-up thirteen levels SC inverter is implemented in MATLAB/SIMULINK. They can withstand the voltage of input sourceVDC. The output voltage of the inverter is approximately five times the applied input voltage, which may derive from the PV, fuel cell and battery, and others. To synthesize 13-level output voltage, the phase disposition PWM technique is implemented by comparing 20 kHz carrier wave and 50 Hz reference frequency. The switches can withstand the voltage during the turn-on and turn-off processes. Moreover, the switching stress across each switch is equal to applied input DC (50V) as shown in Figure 5 and Table 2.Figure 5
. Withstanding voltages of switches.Table 2
. Specifications for the proposed inverter.
SpecificationsValueNumber of switched capacitors5Output level produced13Semiconductor switches required29Withstand voltage across the switchVDCSwitching frequency20 KHzInput voltage50 VOutput voltage280 VOutput current2.1 AResistor25 ΩInductor400 mHPeak inverse voltage (PIV)1VDCTotal standing voltage (TSV)29VDCThe proposed topology has five capacitors with a value of 1000μF each. The switched capacitors are charged and discharged using a self-balancing process. When the capacitor is connected in parallel and series with the input DC voltage, as shown in Figure 6, each capacitor charges and discharges a voltage of 50 V.Figure 6
. Withstanding voltages of switches.The capacitor ripple voltage always does not exceed 10% of the capacitor voltage. From Figure7, the capacitor ripple voltage is 3 V, which is not exceeding 10% of the capacitor voltage of 50 V.Figure 7
. Capacitor ripple voltage.The simulation of the proposed topology is carried out at the input voltage VDC = 50 V and the load R = 0.4 KΩ. The output voltages at different modulation indices of 0.99, 0.7, and 0.5 with the voltages of 280 V, 230 V, and 150 V respectively, are shown in Figures 8, 9, and 10. Similarly, for the load R = 25 Ω and L = 400 mH, at modulation index, MI = 0.99, the input voltage VDC is 50 V, frequency is 50 HZ, and the capacitor is 1000 μF, then the proposed inverter produces the thirteen-level output voltage and a current of 280 V and 2.1A respectively, as shown in Figure 11.Figure 8
. MLI output voltage (MI-0.99).Figure 9
. MLI output voltage (MI-0.5).Figure 10
. MLI output voltage (MI-0.7).Figure 11
. Output voltage and current (MI-0.99) and (MI-0.7).The output voltage and level of the inverter are changed by varying the modulation index. For MI = 0.7, the proposed inverter generates the output of eleven levels with the load voltage and current of 230 V and 1.7 A respectively as shown in Figure11. Similarly, for MI = 0.5, the proposed inverter produces the seven-level output with the voltage and current of 150 V and 1.3 A respectively, as shown in Figure 12.Figure 12
. Output voltage and current (MI = 0.5).High harmonic distortions are generated as the modulation index varies, e.g., for MI = 0.99, the THD is 18.07%; for MI = 0.7, the THD is 24.63%; and for MI = 0.5, the THD is 37.77%. Table3 shows the output of the proposed inverter at various modulation indexes. The generated voltage and current of 275.4 V and 2.1A respectively, at MI = 0.99 with thirteen-level output is obtained with voltage and current THD’s of 10.59% and 5.07% respectively. At MI = 0.7, the eleven-level output is obtained with the voltage THD of 14.66% and current THD of 7.65%. The voltage and current THD at MI = 0.5 is 21.58% and 10.94% respectively.Table 3
. Result summary.
Modulation index (MI)Generated output levelVoltage magnitude (V)Current magnitude (A)Voltage THD (%)Current THD (%)0.9913275.42.0910.595.070.711201.41.5714.667.650.57142.81.1121.5810.94The proposed inverter has voltage and current harmonic distortions of 10.59% and 5.07%, respectively, at MI = 0.99, as shown in Figure13. Similarly, the proposed inverter’s voltage and current harmonic distortion analysis at MI = 0.7 is 14.66% and 7.65%, respectively, and at MI = 0.5 is 21.58% and 10.94% as shown in Figures 14 and 15.Figure 13
. THD analysis (MI-0.99). (a) Voltage THD, (b) current THD.
(a)(b)Figure 14
. THD analysis (MI-0.7). (a) Voltage THD, (b) current THD.
(a)(b)Figure 15
. THD analysis (MI-0.7). (a) Voltage THD, (b) current THD.
(a)(b)


## 5. Comparative Analysis

To recognize the performance of the proposed inverter, the proposed thirteen-level inverter is compared with the well-known existing topologies in terms of boosting ability, the number of switches, DC sources, and total standing voltages. Table4, shows that the proposed topology has many advantages in terms of total standing voltage, boosting ability, and peak inverse voltage. Moreover, the proposed inverter has 5 times of boosting ability compared to other topologies.Table 4
. Comparison results between existing topologies and the proposed topology.
MLISwitchesDC sourcesCapacitorsSelf-balancingBoosting abilityH-Bridge circuitPIVTSV[16]24112NoNoNoVDC24VDC[17]3667Yes2 timesYes6VDC36VDC[18]1660No2 timesYes6VDC41VDC[19]820No2 timesNo3VDC32VDC[20]933No2 timesNo6VDC20VDC[21]1860NoNoNo2VDC45VDC[22]1040No2 timesNo5VDC28VDC[13]2216No5 timesYes6VDC48VDC[14]1222Yes2 timesYes3VDC21VDCProposed thirteen-level boost inverter2915Yes5 timesNoVDC29VDCThe NPC- MLI topology [16] have 24 switches, 12 capacitors, and a single DC source that produces the high TSV of 24 VDC. In this topology, the self-balancing capacity is not possible whereas the topologies [14, 17] and proposed thirteen-level boost inverter have the self-balancing ability.The topologies [14, 17], and [13] have H- bridge configuration, which results in the high voltage stress on the switches, whereas the proposed thirteen-level boost inverter does not have H- bridge configuration, which results in the low voltage stress on the switches that result in the low PIV and TSV.The topologies [14, 17] have boosted the ability by 2 times of input voltage, whereas the proposed thirteen level boost inverter topology has to boost the ability by 5 times of input voltage.The topologies [18], and [21] required 6 DC sources, the topology [22] requires 4 DC sources, the topology [19, 20] needs 3 DC sources, and the topology [14] requires 2 DC sources, whereas the proposed thirteen-level inverter requires only a single DC source, which results in the low cost of the topology.The number of capacitors required for topologies [16, 17], and [13] are 12, 7, and 6 capacitors respectively. The proposed thirteen-level boost inverter topology requires 5 capacitors and the capacitor voltages are charged and discharged by the self-balancing process. The proposed thirteen-level boost inverter has the advantage of the self-balancing ability, which reduces the need for balancing circuits in the topology.The voltage across the switches will play a major role in choosing the topology. The voltage stress of the switches in topologies [16,22] is different as shown in Figures 16 and 17, which results in the need for a high amount of filter circuits and high cost of the topology, whereas the proposed topology has the same voltage stress, which is equal to the applied input source as shown in Figure 5. So, the proposed inverter topology does not require any additional filtering circuits, which reduces the cost of the topology.Figure 16
Voltage stress across the switches in [22].Figure 17
Voltage stress across the switches in [16].The topology [13] has switches of 22, which have different voltage stress voltages, which result in a high TSV of 48VDC. The topologies [18,21] have high TSV of 45VDC and 41VDC respectively. The 36 switches used in the topology [17] have PIV of 6VDC results and a high TSV of 36VDC. The proposed thirteen-level boost inverter has 29 switches and all switches have equal voltage stress, which is equal to the input DC voltage. Therefore, the proposed thirteen-level boost inverter has low PIV of VDC and low TSV of 29VDC compared to the existing topologies.The voltage and current harmonic distortions at different modulation indices are shown in Figure18(a). Though the proposed topology has many advantages, the requirement of semiconductor switches is more than the existing topologies for a greater number of levels as shown in Figure 18(b). The proposed inverter topology has low TSV as compared to existing topologies [13, 18, 21], and [17] as shown in Figure 18(c). The usage of capacitors is more in References [16, 17] than the proposed topology, which leads to very expensive as shown in Figure 18(d).Figure 18
. Comparison of expansions. (a) THD percentage, (b) semiconductor switches, (c) total standing voltage, and (d) capacitors required.
(a)(b)(c)(d)


## 6. Conclusion

The proposed SC inverter topology is set up with high output voltage from the very low input voltage (50 V) with any bulky transformer and is also able to generate different magnitudes. To control the SC inverter, a multicarrier PWM technique was engaged to the inverter. Furthermore, without H-bridges, the switches’ stress voltage does not exceed the applied voltage, and the total standing voltage of the inverter is greatly reduced. This proposed inverter generates a single-phase AC output voltage with a frequency of 50 Hz from a very low DC input voltage of 50 V with any intermediate DC-DC conversion stage. As a result, the traditional inverter’s size and weight have decreased. As a result, the proposed SC inverter is ideal for various SAPFs. MATLAB/Simulink was used to check the simulation performance.



---

*Source: 4150590-2022-10-05.xml*