# Research on Control Strategy of AC-DC-AC Substation Based on Modular Multilevel Converter

Authors: Fei Chang; Zhongping Yang; Fei Lin
Journal: Mathematical Problems in Engineering
 (2017)

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## Abstract

Significant disadvantages in power quality especially the unbalance problem and neutral sections restrict the evolution of conventional traction power supply system. A new traction power supply system based on three-phase to single-phase converter is studied, which can transfer active power from three-phase grid to single-phase catenary. One catenary section could be utilized in the new traction power supply system instead of the multiple split sections in conventional system. Three-phase to single-phase converter is the core equipment of new traction power system. MMC (modular multilevel converter) structure of AC-DC-AC substation is proposed in this paper. To solve the problem of the capacitor voltage balancing in MMC, a parallel sorting algorithm based on field programmable gate array (FPGA) is studied. And the correctness and effectiveness of the algorithm are verified by experiments. In addition, it is inevitable that the AC grid voltage will be unbalanced caused by the fault in the new system. Therefore, this paper focuses on the analysis of the effect of the unbalanced grid voltage on the operating characteristics of the MMC system. Finally, the correctness of the theoretical analysis is verified by simulation.


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## Body

## 1. Introduction

A traditional traction power system typically uses two split catenaries, as shown in Figure1(a), so there is neutral section in one substation (SS) and between adjacent SS [1]. When the locomotive is passing through neutral section, the traction and speed will be lost. Meanwhile the system must mitigate critical power quality problems, such as unbalance, harmonic, and reactive power [2]. Compensator-based technologies have been installed to improve the power quality in railway traction power system [3, 4]. The scheme of one catenary line based on a power flow controller (PFC) was used, as shown in Figure 1(b); this scheme was called a cophase traction power supply system [5]. A PFC can balance active power and compensate reactive power and filter harmonic. Although the neutral section at the exit of the substation was canceled in cophase system, that between adjacent SS still exists. To connect all catenaries from different substations, a new traction power supply system is proposed in [6] that is based on a three-phase to single-phase converter as the critical piece of equipment in the substation, as shown in Figure 1(c). The system transfers active power from the isolated three-phase grid to a one-phase traction line and provides the output voltage with a controlled frequency, phase, and amplitude. Based on the control strategy of single-phase converter proposed in this paper, the amplitude and phase of the output voltage of each traction substation can be ensured the same. Therefore, the feeder line between different substations can be connected directly.Figure 1
Three types of traction power supply systems: (a) traditional system; (b) cophase system; and (c) new traction power supply system.
(a)
(b)
(c)Japan Tokaido Shinkansen railway uses 60 Hz single-phase AC; since 2003, there have been 3 sets of 60 MVA EFC (Electronic Frequency Converter) installation and operation. EFC transforms three-phase 50 Hz AC into 60 Hz single-phase AC, and it has the ability to realize the same phase power supply. Figure2 is the EFC topology, which uses a H-bridge cascaded multiple AC-DC-AC topology.Figure 2
H-bridge cascaded multiple AC-DC-AC topology.At present, the European cophase power supply equipment manufacturers are mainly ABB and Siemens company. The main circuit structure of ABB company adopts diode clamped cascaded AC-DC-AC topology, as shown in Figure3; the main circuit structure of Siemens company adopts modular multilevel direct AC-AC conversion (MMDC) topology, as shown in Figure 4.Figure 3
Diode clamped cascaded AC-DC-AC topology.Figure 4
MMDC circuit topology.MMC technology can be regarded as an important milestone in the history of the development of flexible HVDC transmission. Compared with the conventional two-level or three-level converter, modular cascade structure of MMC is easy to achieve high voltage level, to avoid the defects of static and dynamic voltage balancing, large switching loss, and high harmonic content of the device. Figure5 is the MMC structure of AC-DC-AC substation.Figure 5
MMC structure of AC-DC-AC substation.Finally, Table1 compares the four circuit topologies of cophase power supply device.Table 1
Comparison of the circuit topology of advanced cophase power supply device.
Topology type
Diode clamped cascaded AC-DC-AC topology(ABB)
MMDC circuit topology(Siemens)
H-bridge cascaded multiple AC-DC-AC topology(Japan Toshiba)
MMC AC-DC-AC topology(studied in this paper)
Input/output decoupling performance
Excellent
Good
Excellent
Excellent
Input/output transformer
Special single-phase input/output transformer, complex structure and large quantity
Normal three-phase input transformer, no need single-phase output transformer
Special single-phase input/output transformer, complex structure and large quantity
Normal three-phase input transformer, no need single-phase output transformer
Input/output filter
Need
No need
Need
No need
Converter efficiency (excluding transformers)
About 95%
≥99%
About 96%
≥98%
Area covered
Larger
Larger
Large
Larger
Manufacturing cost
Higher
Higher
High
HigherIn this paper, the capacitor voltage balancing problem of MMC was studied firstly and a parallel sorting algorithm based on field programmable gate array (FPGA) was studied.In addition, it is inevitable that the AC grid voltage will be unbalanced caused by the fault, for example, the single-phase grounding fault. It is important to analyze the effect of asymmetric grid voltage on the operation characteristics of the system. In [6, 7], the classical dq decoupling control is used in the rectifier side. However, this control is only applicable to the balanced grid voltage. In this paper, the influence of negative-sequence current is analyzed in detail, and the unified control of positive and negative-sequence current is realized by using PR controller.


## 2. Capacitor Voltage Balancing Control

An important challenge in MMC is balancing the flying-capacitor voltage. There are two primary approaches for balancing the capacitor voltage. One method uses proportional integral (PI) controller [8, 9], which is suitable for less submodules because each capacitor voltage requires a PI controller. The other method is the capacitor voltage sorting algorithm which is suitable for more submodules [10, 11]. Traditional sorting methods (e.g., the bubble sorting method) rely on serial processing, so they are suitable for implementation in DSP, and they need large computation time and have no real-time performance. Based on FPGA hardware technology, a parallel real-time sorting algorithm is studied in this paper [12]. The algorithm uses the FPGA hardware features with parallel computing and can be computed in four clock cycles, and the computation time does not vary with changes in the number of submodules.


### 2.1. Principle of the Parallel Sorting Algorithm Based on FPGA

The algorithm applied to the following examples illustrates the following specific implementation steps while assuming that the bridge arm capacitor voltage arrayAn is equal to 500,510,552,542,531,573,584,521,563,500V for (n=0,…,9).(
1) First Clock Cycle: Pairwise Comparisons for All Capacitor Voltage Values. Specified herein, Am and An are compared: if Am>An, then the comparison result is Z=1; otherwise Z=0. Thus, the original data in the first output is 1 or 0, respectively. The comparison results between the voltage values are shown in Table 2.Table 2
Comparison of capacitor voltage.
A
0(500)
A
1(510)
A
2(552)
A
3(542)
A
4(531)
A
5(573)
A
6(584)
A
7(521)
A
8(563)
A
9(500)
Accumulated value
A
0(500)
0
0
0
0
0
0
0
0
0
0
A
1(510)
1
0
0
0
0
0
0
0
1
2
A
2(552)
1
1
1
1
0
0
1
0
1
6
A
3(542)
1
1
0
1
0
0
1
0
1
5
A
4(531)
1
1
0
0
0
0
1
0
1
4
A
5(573)
1
1
1
1
1
0
1
1
1
8
A
6(584)
1
1
1
1
1
1
1
1
1
9
A
7(521)
1
1
0
0
0
0
0
0
1
3
A
8(563)
1
1
1
1
1
0
0
1
1
7
A
9(500)
1
0
0
0
0
0
0
0
0
1(
2) Second Clock Cycle. The comparison value of the capacitor voltage is recorded to determine the sorting position of the capacitor voltage in the array. As shown in Table 2, the order of each capacitor voltage from small to large is A0,A9,A1,A7,A4,A3,A2,A8,A5,A6.(
3) Third Clock Cycle. The capacitor voltage value is assigned to the corresponding sorting space.(
4) Fourth Clock Cycle. The sorting results of the capacitor voltage are output.Figure6 is the simulation result of the sorting design in QUARTUS. In Figure 6, in0~in9 are the 10 capacitor voltage values; after four clock cycles, the output sorting results are out0~out9, respectively.Figure 6
Simulation result of the sorting design.


### 2.2. Performance Analysis of the Parallel Sorting Algorithm

#### 2.2.1. Time Complexity

Processing of the parallel sorting algorithm only requires four clock cycles in the FPGA, and the time complexity is constant. If the clock cycle of the FPGA is 10 ns, the time required to complete the sorting algorithm is 40 ns. However, using traditional sorting algorithms, such as bubble sorting, the time complexity isn(n-1)/2. If there are 100 capacitor voltages, the computation time required to complete the bubble sorting algorithm is equal to 49.5 μs. Obviously, this computation time is far greater than that of the parallel sorting algorithm.


#### 2.2.2. Space Complexity

Due to the need of full parallel processing, the parallel sorting algorithm takes up a large amount of processing space. Based on the calculated statistics, if the number of the capacitor voltages is equal ton, then the number of comparators required is equal to n-12. Because the number of logic elements (LE) in the FPGA occupied by each comparator is approximately 5, the total number of LE is 5n-12. If each bridge arm has 100 submodules, nearly 50,000 LE are needed. Therefore, a high performance FPGA is needed in the practical application, which will increase the cost of the hardware.


### 2.3. Flow Chart of Capacitor Voltage Balancing Control

The specific implementation process of the MMC capacitor voltage balancing control is shown in Figure7.Figure 7
Flow chart of capacitor voltage balancing control.N
o
n is the number of SMs that need to be switched on in the current control cycle according to the upper controller, and iarm is the corresponding arm current.The switching principles of capacitor voltage balancing algorithm are thus summarized as follows. When the arm current charges the capacitors, it switches on the SMs with the lowest capacitor voltages while switching off those with the highest voltages. When the arm current discharges the capacitors, the SMs with the highest capacitor voltages are switched on while those with the lowest voltages are switched off.


## 2.1. Principle of the Parallel Sorting Algorithm Based on FPGA

The algorithm applied to the following examples illustrates the following specific implementation steps while assuming that the bridge arm capacitor voltage arrayAn is equal to 500,510,552,542,531,573,584,521,563,500V for (n=0,…,9).(
1) First Clock Cycle: Pairwise Comparisons for All Capacitor Voltage Values. Specified herein, Am and An are compared: if Am>An, then the comparison result is Z=1; otherwise Z=0. Thus, the original data in the first output is 1 or 0, respectively. The comparison results between the voltage values are shown in Table 2.Table 2
Comparison of capacitor voltage.
A
0(500)
A
1(510)
A
2(552)
A
3(542)
A
4(531)
A
5(573)
A
6(584)
A
7(521)
A
8(563)
A
9(500)
Accumulated value
A
0(500)
0
0
0
0
0
0
0
0
0
0
A
1(510)
1
0
0
0
0
0
0
0
1
2
A
2(552)
1
1
1
1
0
0
1
0
1
6
A
3(542)
1
1
0
1
0
0
1
0
1
5
A
4(531)
1
1
0
0
0
0
1
0
1
4
A
5(573)
1
1
1
1
1
0
1
1
1
8
A
6(584)
1
1
1
1
1
1
1
1
1
9
A
7(521)
1
1
0
0
0
0
0
0
1
3
A
8(563)
1
1
1
1
1
0
0
1
1
7
A
9(500)
1
0
0
0
0
0
0
0
0
1(
2) Second Clock Cycle. The comparison value of the capacitor voltage is recorded to determine the sorting position of the capacitor voltage in the array. As shown in Table 2, the order of each capacitor voltage from small to large is A0,A9,A1,A7,A4,A3,A2,A8,A5,A6.(
3) Third Clock Cycle. The capacitor voltage value is assigned to the corresponding sorting space.(
4) Fourth Clock Cycle. The sorting results of the capacitor voltage are output.Figure6 is the simulation result of the sorting design in QUARTUS. In Figure 6, in0~in9 are the 10 capacitor voltage values; after four clock cycles, the output sorting results are out0~out9, respectively.Figure 6
Simulation result of the sorting design.


## 2.2. Performance Analysis of the Parallel Sorting Algorithm

### 2.2.1. Time Complexity

Processing of the parallel sorting algorithm only requires four clock cycles in the FPGA, and the time complexity is constant. If the clock cycle of the FPGA is 10 ns, the time required to complete the sorting algorithm is 40 ns. However, using traditional sorting algorithms, such as bubble sorting, the time complexity isn(n-1)/2. If there are 100 capacitor voltages, the computation time required to complete the bubble sorting algorithm is equal to 49.5 μs. Obviously, this computation time is far greater than that of the parallel sorting algorithm.


### 2.2.2. Space Complexity

Due to the need of full parallel processing, the parallel sorting algorithm takes up a large amount of processing space. Based on the calculated statistics, if the number of the capacitor voltages is equal ton, then the number of comparators required is equal to n-12. Because the number of logic elements (LE) in the FPGA occupied by each comparator is approximately 5, the total number of LE is 5n-12. If each bridge arm has 100 submodules, nearly 50,000 LE are needed. Therefore, a high performance FPGA is needed in the practical application, which will increase the cost of the hardware.


## 2.2.1. Time Complexity

Processing of the parallel sorting algorithm only requires four clock cycles in the FPGA, and the time complexity is constant. If the clock cycle of the FPGA is 10 ns, the time required to complete the sorting algorithm is 40 ns. However, using traditional sorting algorithms, such as bubble sorting, the time complexity isn(n-1)/2. If there are 100 capacitor voltages, the computation time required to complete the bubble sorting algorithm is equal to 49.5 μs. Obviously, this computation time is far greater than that of the parallel sorting algorithm.


## 2.2.2. Space Complexity

Due to the need of full parallel processing, the parallel sorting algorithm takes up a large amount of processing space. Based on the calculated statistics, if the number of the capacitor voltages is equal ton, then the number of comparators required is equal to n-12. Because the number of logic elements (LE) in the FPGA occupied by each comparator is approximately 5, the total number of LE is 5n-12. If each bridge arm has 100 submodules, nearly 50,000 LE are needed. Therefore, a high performance FPGA is needed in the practical application, which will increase the cost of the hardware.


## 2.3. Flow Chart of Capacitor Voltage Balancing Control

The specific implementation process of the MMC capacitor voltage balancing control is shown in Figure7.Figure 7
Flow chart of capacitor voltage balancing control.N
o
n is the number of SMs that need to be switched on in the current control cycle according to the upper controller, and iarm is the corresponding arm current.The switching principles of capacitor voltage balancing algorithm are thus summarized as follows. When the arm current charges the capacitors, it switches on the SMs with the lowest capacitor voltages while switching off those with the highest voltages. When the arm current discharges the capacitors, the SMs with the highest capacitor voltages are switched on while those with the lowest voltages are switched off.


## 3. Control of Single-Phase Converter

This paper presents a control strategy of single-phase converter, as shown in Figure8. The outer loop controls the RMS of the voltage, while the inner loop controls the instantaneous value of the voltage.Figure 8
Control strategy of single-phase converter.In the outer loop, the RMS of the single-phase voltageUss is compared with the reference value Uss∗; the error signal is through a PI regulator and multiplied by a standard sinusoidal signal; the result value is then used as a reference value for the inner loop. A single-phase traction converter is controlled by the outer loop, and the RMS of the voltage can theoretically be identical to the steady-state response to ensure that when the load changes or when the system is disturbed, the RMS of the voltage remains constant.The phase synchronization of sinusoidal signals can be realized by GPS between substations. Thus, the amplitude and phase of the output voltage of each traction substation can be ensured the same. There is no circulating current between substations, and there is no master-slave relationship between substations, and any substation fault can be supplied by two adjacent substations, and the system reliability is high.In the inner loop, the instantaneous value of the single-phase voltageuss is compared with the reference value obtained by the outer loop, and the error value passes through the Q-PR regulator to get a reference wave and that compared with the triangular wave to form the trigger pulse. In the inner loop, a Q-PR regulator instead of a PI regulator can achieve no error control of the AC voltage. The instantaneous value of the output voltage is controlled by the inner loop so that the voltage can track a given sine wave to maintain a good sinusoidal output waveform.


## 4. Experimental Verification

Experimental verification is carried out on the hardware in the loop physical experiment platform based on DSP + FPGA and RT-LAB. The experimental structure of the system is shown in Figure5, and the experimental parameters are shown in Table 3.Table 3
Experimental parameters.
Parameters
Values
Rated DC voltage
120 V
Number of SMs of each arm
4
Arm inductance
5 mH
Capacitance of each SM
2000μF
Carrier frequency
1 kHzFigure9 is the three-phase grid current. As can be seen, when the load power is increased, the three-phase current of the power grid is fast response, and the three-phase current is symmetrical in the whole process, and the harmonic content is low. Figure 10 is the voltage and current of traction side. During the whole experiment, the single-phase traction voltage is stable in the 40 V, the single-phase traction current can be quick response when the load changes. In the whole process, the total harmonic distortion of single-phase traction voltage and current is low, and the power factor is close to 1, which can provide high quality power supply for electric locomotive. Figure 11 is MMC capacitor voltage of grid side. Because of the limitation of the number of channels of the oscilloscope, the capacitor voltage waveform of the first submodule of the upper and lower bridge arm of phase A is given. Meanwhile, in order to observe the ripple component of capacitor voltage, the oscilloscope waveform is not DC coupled, so it only shows the AC component of the capacitor voltage. It can be seen that the submodule capacitor voltage of the upper and lower bridge arm is complementary and stable in the whole power step. Also the fluctuation range of the capacitor voltage is not more than 5%. In addition, the sorting time is 40 ns that verified the effectiveness of the capacitor voltage balancing algorithm in this paper.Figure 9
Grid side current.Figure 10
Voltage and current of traction side.Figure 11
MMC capacitor voltage of grid side.


## 5. Characteristic Analysis and Control Strategy for MMC in Rectifier Side under Unbalanced Grid Voltage

### 5.1. Circular Interaction among the Voltage and Current Quantities of the MMC

The structure of the main circuit and the structure of a single submodule (SM) of the MMC converter are shown in Figure12. Three-phase MMC converter is composed of six bridge arms, with each bridge arm consisting of N cascaded SM.Figure 12
Circuit diagram of MMC.As shown in Figure13, a SM is used as an example. In this figure, i is used to denote the ith SM in this arm. Assuming that the arm current and the switching function of this SM are known, the interaction of the voltage and current quantities can be described as follows [13].Figure 13
Interaction among the voltage and current quantities of a SM.(
1) Capacitor Current. The bridge arm current will be coupled to the DC side of the converter through the switching action and will flow into the DC capacitor. For the ith SM of this arm, the relationship between the capacitor current and the switching function is as follows:(1)ic_i=Siix,where Si(t) denotes the switching function of this SM. Si(t)=1, when S1 is on and S2 is off; Si(t)=0, when S1 is off and S2 is on.(
2) Capacitor Ripple Voltage. The current shown in (1) causes a voltage ripple in the capacitor. The nth harmonic component in the capacitor current causes a corresponding voltage ripple with nth harmonic frequency and its time-varying function is expressed as follows:(2)uc_iωn=ic_iωnjωnCd,where Cd is the capacitance of the SM capacitor and ωn is the nth harmonic frequency.(
3) Ripple Voltage of the SM Terminal. The DC side ripple voltage of the SM is coupled to the AC port of the SM through the switching action. The corresponding ripple voltage in the AC port is as follows:(3)uo_i=Siuc_i.(
4) Ripple Voltage of the Phase. Each bridge arm is composed of N cascaded SM, and each phase consists of an upper and a lower bridge arm, so the total ripple voltage of the phase arm is as follows:(4)Δuph=∑i=1NΔup_o_i+∑i=1NΔun_o_i,where Δuph denotes the ripple voltage across the phase and Δup_o_i and Δun_o_i, respectively, denote the AC side ripple voltage of the ith SM in the upper and lower bridge arms.


### 5.2. Characteristic Analysis for MMC in Rectifier Side under Unbalanced Grid Voltage

When the asymmetrical short-circuit fault occurs in AC grid, as the connection of transformer is usuallyY/Δ or Δ/Y which can isolate zero-sequence component, so the effect of negative-sequence current is studied here. Negative-sequence network is shown in Figure 14, the points P and N are similar to the neutral point of the three-phase negative-sequence network, and the electric potential in the AC circuit can be considered to be the same. So it can be considered that the negative-sequence current will not flow into the DC side, only exists in the AC side and the converter, and is the symmetrical distribution in the upper and lower bridge arm of the converter. The simplified equivalent circuit is shown in Figure 15:(5)I˙-=U˙-ZTσ+ZL/2=-2I˙p-=2I˙n-,where I˙- is the negative-sequence current, I˙p- and I˙n- are, respectively, the negative-sequence current in the upper and lower bridge arm, U˙- is the negative-sequence voltage, ZTσ is the impedance of the transformer and ZTσ=ωLTσ, ZL is the impedance of the bridge arm, and ZL=ωLs.Figure 14
Negative-sequence path.Figure 15
Negative-sequence equivalent circuit.The three-phase instantaneous value of negative-sequence current in AC system can be expressed as follows:(6)ia-t=Im-sin⁡ωt-φ-,ib-t=Im-sin⁡ωt-φ-+23π,ic-t=Im-sin⁡ωt-φ--23π,where ia-t, ib-t, and ic-t, respectively, denote three-phase negative-sequence current and Im- and φ- denote amplitude and phase of negative-sequence current, respectively.The average switching function of the converter can be expressed as follows:(7)Sapt=12-m2sin⁡ωt,Sant=12+m2sin⁡ωt,where Sapt and Sant are, respectively, the average switching functions of the SM in the upper and lower arms in phase A and m is the modulation index.(1) Capacitor ripple current caused by negative-sequence current is as follows.Capacitor current of the upper bridge arm in phase A can be expressed as follows:(8)Δicap-t=Sapt·-12ia-t=12-m2sin⁡ωt-Im-2sin⁡ωt-φ-=-Im-4sin⁡ωt-φ--mIm-8cos⁡2ωt-φ-+mIm-8cos⁡φ-.Similarly, capacitor current of the lower bridge arm in phase A is(9)Δican-t=Sant·12ia-t=12+m2sin⁡ωtIm-2sin⁡ωt-φ-=Im-4sin⁡ωt-φ--mIm-8cos⁡2ωt-φ-+mIm-8cos⁡φ-.The capacitor current for phases B and C can be obtained in a similar manner:(10)Δicbp-t=-Im-4sin⁡ωt-φ-+23π-mIm-8cos⁡2ωt-φ-+mIm-8cos⁡φ-+23π,Δicbn-t=Im-4sin⁡ωt-φ-+23π-mIm-8cos⁡2ωt-φ-+mIm-8cos⁡φ-+23π,Δiccp-t=-Im-4sin⁡ωt-φ--23π-mIm-8cos⁡2ωt-φ-+mIm-8cos⁡φ--23π,Δiccn-t=Im-4sin⁡ωt-φ--23π-mIm-8cos⁡2ωt-φ-+mIm-8cos⁡φ--23π.From formulas (8)–(10) it can be seen that the amplitude of fundamental-frequency component of capacitor current caused by negative-sequence current is Im-/4, the amplitude of the second-order harmonic component is mIm-/8, and the DC component is mIm-/8cos⁡φ-.(2) Under normal operating conditions, the DC component of the three-phase capacitor current is(11)icap_dc=ican_dc=Ida2-mIm+8cos⁡φ+,icbp_dc=icbn_dc=Idb2-mIm+8cos⁡φ+,iccp_dc=iccn_dc=Idc2-mIm+8cos⁡φ+.The DC component is zero during the steady-state, which reflects the balance between theac-side active power and the dc-link side active power. Therefore,(12)Ida=Idb=Idc=mIm+4cos⁡φ+=Id3,where Ida, Idb, and Idc, respectively, denote the three-phase DC current; Id denotes the DC current; Im+ and φ+ denote amplitude and phase of positive-sequence current, respectively.Under unbalanced grid voltage, the DC component of the capacitor current is(13)icap_dc′=ican_dc′=Ida′2-mIm+8cos⁡φ++mIm-8cos⁡φ-,icbp_dc′=icbn_dc′=Idb′2-mIm+8cos⁡φ++mIm-8cos⁡φ-+23π,iccp_dc′=iccn_dc′=Idc′2-mIm+8cos⁡φ++mIm-8cos⁡φ--23π.Similarly, the DC component of the capacitor current should be zero, so the three-phase DC current is(14)Ida′=m4Im+cos⁡φ+-Im-cos⁡φ-,Idb′=m4Im+cos⁡φ+-Im-cos⁡φ-+23π,Idc′=m4Im+cos⁡φ+-Im-cos⁡φ--23π.From formula (14) it can be seen that the distribution of DC current in the three-phase bridge arm is no longer symmetrical under unbalanced grid voltage, and the DC current is determined by the amplitude and phase of the negative-sequence current, but still keeping the following relationship: Ida′+Idb′+Idc′=Id. So the DC current caused by the negative-sequence current has the nature of the DC circulating current, which is to regulate the three-phase energy balance.(3) Capacitor ripple voltage caused by negative-sequence current is as follows.The fundamental-frequency component of the capacitor ripple voltages in the upper and lower arms can be obtained as(15)Δucap1-t=-1jωcd·Im-4sin⁡ωt-φ-=Im-4ωcdcos⁡ωt-φ-,Δucan1-t=-Im-4ωcdcos⁡ωt-φ-.The second-order harmonic component of the capacitor ripple voltages in the upper and lower arms can be obtained as(16)Δucap2-t=Δucan2-t=-1j2ωcd·mIm-8cos⁡2ωt-φ-=-mIm-16ωcdsin⁡2ωt-φ-.The ripple voltages on theac side of the SM in the upper and lower arms can be expressed as(17)Δusm_apt=12-12msin⁡ωtΔucap1-t+Δucap2-t,Δusm_ant=12+12msin⁡ωtΔucan1-t+Δucan2-t.The sum of the ripple voltage of all SMs in one phase forms a ripple voltage across this phase. According to (17), the ripple voltage across this phase is expressed as(18)Δua-t=NΔusm_apt+NΔusm_ant=-3NmIm-16ωcdsin⁡2ωt-φ--NmIm-8ωcdsin⁡φ-.The ripple voltage for phases B and C can be obtained in a similar manner:(19)Δub-t=-3NmIm-16ωcdsin⁡2ωt-φ--NmIm-8ωcdsin⁡φ-+23π,Δuc-t=-3NmIm-16ωcdsin⁡2ωt-φ--NmIm-8ωcdsin⁡φ--23π.From formulas (18)-(19) it can be seen that the second-order harmonic component of the capacitor ripple voltages in one phase is(20)Δua2-t=Δub2-t=Δuc2-t=-3NmIm-16ωcdsin⁡2ωt-φ-.In summary, the effects of negative-sequence current include the following: the DC component of the three-phase circulating current is not symmetrical; the amplitude of the capacitor ripple voltage of the SM is increased; there is the second-order harmonic component in the DC voltage.


### 5.3. Control Strategy for MMC in Rectifier Side under Unbalanced Grid Voltage

The control strategy of three-phase converter based on theαβ coordinate system is shown in Figure 16 [14]. A stable DC-link voltage is required in order for the converter to work properly. This can be achieved by introducing a PI controller to maintain the DC-bus voltage Udc at the DC-bus reference voltage Udc∗. Because of the double-frequency ripple component in the DC-bus voltage, in a low-pass filter, such as the hold filter(21)Hs=1-e-Ts/2Ts/2,where T is the fundamental period of the system, H(s) can be adopted to measure the DC component of Udc for feedback.Figure 16
Control strategy of MMC under unbalanced grid voltage.Firstly, according to the DC voltage outer loop, the reference valueidref of the d-axis current is obtained. Since the three-phase converter is mainly used for active power transmission from the three-phase grid, the reference value iqref of the q-axis current is set to 0. Secondly, the reference values iαref and iβref of the current inner loop are obtained by a dq/αβ coordinate transformation, and then, by comparison with the actual current values isα and isβ in the αβ coordinate system, the errors between references and actual currents are used to generate the voltage references uαref and uβref through the quasi-proportional resonant (Q-PR) regulator. The transfer function of Q-PR is as follows [14, 15]: (22)GQ-PRs=Kp+2ωcss2+2ωcs+ω02Kr,where Kp is the proportional coefficient, Kr is the resonant coefficient, ωc is the cut-off frequency which generally ranges from 5 to 15 rad/s, and ω0 is the resonant frequency.Thirdly, the three-phase voltage modulation wavesuaref, ubref, and ucref can be obtained by a αβ/abc transformation. In addition, the three-phase voltage modulation wave is changed from the sine wave to the flat top wave because of the injection of zero-sequence voltage which can effectively improve the utilization of the DC voltage.The expression ofu0 is as follows:(23)u0=0.5max⁡uaref,ubref,ucref+min⁡uaref,ubref,ucref.The three-phase modulation voltage after the injection of zero-sequence voltage is as follows:(24)uaref∗=uaref-u0,ubref∗=ubref-u0,ucref∗=ucref-u0.Finally, the voltage referencesuaref∗, ubref∗, and ucref∗ are easy to generate the pulse width modulation (PWM) signals to drive the three-phase converter.


### 5.4. Simulation Results

A simulation model for a 10 MW/±40 kV MMC system was constructed using PSCAD/EMTDC to verify the theoretical analysis for the electrical quantities of the MMC. The system structure is shown in Figure5, and the simulation parameters are shown in Table 4. When t=3 s, the grounding short-circuit fault of phase A occurs, and the duration time of fault is 1 s.Table 4
Simulation parameters of MMC.
Parameters
Values
Rated capacity of MMC
10 MVA
Transformer ratio (Y/Δ)
110 kV/40 kV
Rated DC voltage of MMC
±40 kV
Number of SMs of each arm
50
Capacitance of each SM
1400μF
Arm inductance
140 mHAs can be seen from Figure17, the grounding short-circuit fault of phase A occurs when t=3 s (Figure 17(a)), and the three-phase current of AC grid is seriously asymmetric (Figure 17(b)); there is the second-order harmonic component in the DC voltage (Figure 17(c)); the DC component of the three-phase circulating current is not symmetrical (Figure 17(d)); the amplitude of the capacitor ripple voltage of the SM is increased (Figure 17(e)). In summary, the simulation results verify the correctness of the theoretical analysis.Figure 17
Simulation results without suppressing the negative-sequence current. (a) Phase voltage of AC grid. (b) Phase current of AC grid. (c) DC voltage. (d) DC component of the circulating current. (e) Capacitor voltage.
(a)
(b)
(c)
(d)
(e)In Figure18, similarly, the grounding short-circuit fault of phase A occurs when t=3 s (Figure 18(a)). Because the negative-sequence current is suppressed, the three-phase current of AC grid is symmetric (Figure 18(b)). The second-order harmonic component in the DC voltage (Figure 18(c)), the DC component of the three-phase circulating current (Figure 18(d)), and the amplitude of the capacitor ripple voltage of the SM (Figure 18(e)) all decreased; but they can not be completely eliminated, due to the existence of negative-sequence voltage.Figure 18
Simulation results with suppressing the negative-sequence current. (a) Phase voltage of AC grid. (b) Phase current of AC grid. (c) DC voltage. (d) DC component of the circulating current. (e) Capacitor voltage.
(a)
(b)
(c)
(d)
(e)


## 5.1. Circular Interaction among the Voltage and Current Quantities of the MMC

The structure of the main circuit and the structure of a single submodule (SM) of the MMC converter are shown in Figure12. Three-phase MMC converter is composed of six bridge arms, with each bridge arm consisting of N cascaded SM.Figure 12
Circuit diagram of MMC.As shown in Figure13, a SM is used as an example. In this figure, i is used to denote the ith SM in this arm. Assuming that the arm current and the switching function of this SM are known, the interaction of the voltage and current quantities can be described as follows [13].Figure 13
Interaction among the voltage and current quantities of a SM.(
1) Capacitor Current. The bridge arm current will be coupled to the DC side of the converter through the switching action and will flow into the DC capacitor. For the ith SM of this arm, the relationship between the capacitor current and the switching function is as follows:(1)ic_i=Siix,where Si(t) denotes the switching function of this SM. Si(t)=1, when S1 is on and S2 is off; Si(t)=0, when S1 is off and S2 is on.(
2) Capacitor Ripple Voltage. The current shown in (1) causes a voltage ripple in the capacitor. The nth harmonic component in the capacitor current causes a corresponding voltage ripple with nth harmonic frequency and its time-varying function is expressed as follows:(2)uc_iωn=ic_iωnjωnCd,where Cd is the capacitance of the SM capacitor and ωn is the nth harmonic frequency.(
3) Ripple Voltage of the SM Terminal. The DC side ripple voltage of the SM is coupled to the AC port of the SM through the switching action. The corresponding ripple voltage in the AC port is as follows:(3)uo_i=Siuc_i.(
4) Ripple Voltage of the Phase. Each bridge arm is composed of N cascaded SM, and each phase consists of an upper and a lower bridge arm, so the total ripple voltage of the phase arm is as follows:(4)Δuph=∑i=1NΔup_o_i+∑i=1NΔun_o_i,where Δuph denotes the ripple voltage across the phase and Δup_o_i and Δun_o_i, respectively, denote the AC side ripple voltage of the ith SM in the upper and lower bridge arms.


## 5.2. Characteristic Analysis for MMC in Rectifier Side under Unbalanced Grid Voltage

When the asymmetrical short-circuit fault occurs in AC grid, as the connection of transformer is usuallyY/Δ or Δ/Y which can isolate zero-sequence component, so the effect of negative-sequence current is studied here. Negative-sequence network is shown in Figure 14, the points P and N are similar to the neutral point of the three-phase negative-sequence network, and the electric potential in the AC circuit can be considered to be the same. So it can be considered that the negative-sequence current will not flow into the DC side, only exists in the AC side and the converter, and is the symmetrical distribution in the upper and lower bridge arm of the converter. The simplified equivalent circuit is shown in Figure 15:(5)I˙-=U˙-ZTσ+ZL/2=-2I˙p-=2I˙n-,where I˙- is the negative-sequence current, I˙p- and I˙n- are, respectively, the negative-sequence current in the upper and lower bridge arm, U˙- is the negative-sequence voltage, ZTσ is the impedance of the transformer and ZTσ=ωLTσ, ZL is the impedance of the bridge arm, and ZL=ωLs.Figure 14
Negative-sequence path.Figure 15
Negative-sequence equivalent circuit.The three-phase instantaneous value of negative-sequence current in AC system can be expressed as follows:(6)ia-t=Im-sin⁡ωt-φ-,ib-t=Im-sin⁡ωt-φ-+23π,ic-t=Im-sin⁡ωt-φ--23π,where ia-t, ib-t, and ic-t, respectively, denote three-phase negative-sequence current and Im- and φ- denote amplitude and phase of negative-sequence current, respectively.The average switching function of the converter can be expressed as follows:(7)Sapt=12-m2sin⁡ωt,Sant=12+m2sin⁡ωt,where Sapt and Sant are, respectively, the average switching functions of the SM in the upper and lower arms in phase A and m is the modulation index.(1) Capacitor ripple current caused by negative-sequence current is as follows.Capacitor current of the upper bridge arm in phase A can be expressed as follows:(8)Δicap-t=Sapt·-12ia-t=12-m2sin⁡ωt-Im-2sin⁡ωt-φ-=-Im-4sin⁡ωt-φ--mIm-8cos⁡2ωt-φ-+mIm-8cos⁡φ-.Similarly, capacitor current of the lower bridge arm in phase A is(9)Δican-t=Sant·12ia-t=12+m2sin⁡ωtIm-2sin⁡ωt-φ-=Im-4sin⁡ωt-φ--mIm-8cos⁡2ωt-φ-+mIm-8cos⁡φ-.The capacitor current for phases B and C can be obtained in a similar manner:(10)Δicbp-t=-Im-4sin⁡ωt-φ-+23π-mIm-8cos⁡2ωt-φ-+mIm-8cos⁡φ-+23π,Δicbn-t=Im-4sin⁡ωt-φ-+23π-mIm-8cos⁡2ωt-φ-+mIm-8cos⁡φ-+23π,Δiccp-t=-Im-4sin⁡ωt-φ--23π-mIm-8cos⁡2ωt-φ-+mIm-8cos⁡φ--23π,Δiccn-t=Im-4sin⁡ωt-φ--23π-mIm-8cos⁡2ωt-φ-+mIm-8cos⁡φ--23π.From formulas (8)–(10) it can be seen that the amplitude of fundamental-frequency component of capacitor current caused by negative-sequence current is Im-/4, the amplitude of the second-order harmonic component is mIm-/8, and the DC component is mIm-/8cos⁡φ-.(2) Under normal operating conditions, the DC component of the three-phase capacitor current is(11)icap_dc=ican_dc=Ida2-mIm+8cos⁡φ+,icbp_dc=icbn_dc=Idb2-mIm+8cos⁡φ+,iccp_dc=iccn_dc=Idc2-mIm+8cos⁡φ+.The DC component is zero during the steady-state, which reflects the balance between theac-side active power and the dc-link side active power. Therefore,(12)Ida=Idb=Idc=mIm+4cos⁡φ+=Id3,where Ida, Idb, and Idc, respectively, denote the three-phase DC current; Id denotes the DC current; Im+ and φ+ denote amplitude and phase of positive-sequence current, respectively.Under unbalanced grid voltage, the DC component of the capacitor current is(13)icap_dc′=ican_dc′=Ida′2-mIm+8cos⁡φ++mIm-8cos⁡φ-,icbp_dc′=icbn_dc′=Idb′2-mIm+8cos⁡φ++mIm-8cos⁡φ-+23π,iccp_dc′=iccn_dc′=Idc′2-mIm+8cos⁡φ++mIm-8cos⁡φ--23π.Similarly, the DC component of the capacitor current should be zero, so the three-phase DC current is(14)Ida′=m4Im+cos⁡φ+-Im-cos⁡φ-,Idb′=m4Im+cos⁡φ+-Im-cos⁡φ-+23π,Idc′=m4Im+cos⁡φ+-Im-cos⁡φ--23π.From formula (14) it can be seen that the distribution of DC current in the three-phase bridge arm is no longer symmetrical under unbalanced grid voltage, and the DC current is determined by the amplitude and phase of the negative-sequence current, but still keeping the following relationship: Ida′+Idb′+Idc′=Id. So the DC current caused by the negative-sequence current has the nature of the DC circulating current, which is to regulate the three-phase energy balance.(3) Capacitor ripple voltage caused by negative-sequence current is as follows.The fundamental-frequency component of the capacitor ripple voltages in the upper and lower arms can be obtained as(15)Δucap1-t=-1jωcd·Im-4sin⁡ωt-φ-=Im-4ωcdcos⁡ωt-φ-,Δucan1-t=-Im-4ωcdcos⁡ωt-φ-.The second-order harmonic component of the capacitor ripple voltages in the upper and lower arms can be obtained as(16)Δucap2-t=Δucan2-t=-1j2ωcd·mIm-8cos⁡2ωt-φ-=-mIm-16ωcdsin⁡2ωt-φ-.The ripple voltages on theac side of the SM in the upper and lower arms can be expressed as(17)Δusm_apt=12-12msin⁡ωtΔucap1-t+Δucap2-t,Δusm_ant=12+12msin⁡ωtΔucan1-t+Δucan2-t.The sum of the ripple voltage of all SMs in one phase forms a ripple voltage across this phase. According to (17), the ripple voltage across this phase is expressed as(18)Δua-t=NΔusm_apt+NΔusm_ant=-3NmIm-16ωcdsin⁡2ωt-φ--NmIm-8ωcdsin⁡φ-.The ripple voltage for phases B and C can be obtained in a similar manner:(19)Δub-t=-3NmIm-16ωcdsin⁡2ωt-φ--NmIm-8ωcdsin⁡φ-+23π,Δuc-t=-3NmIm-16ωcdsin⁡2ωt-φ--NmIm-8ωcdsin⁡φ--23π.From formulas (18)-(19) it can be seen that the second-order harmonic component of the capacitor ripple voltages in one phase is(20)Δua2-t=Δub2-t=Δuc2-t=-3NmIm-16ωcdsin⁡2ωt-φ-.In summary, the effects of negative-sequence current include the following: the DC component of the three-phase circulating current is not symmetrical; the amplitude of the capacitor ripple voltage of the SM is increased; there is the second-order harmonic component in the DC voltage.


## 5.3. Control Strategy for MMC in Rectifier Side under Unbalanced Grid Voltage

The control strategy of three-phase converter based on theαβ coordinate system is shown in Figure 16 [14]. A stable DC-link voltage is required in order for the converter to work properly. This can be achieved by introducing a PI controller to maintain the DC-bus voltage Udc at the DC-bus reference voltage Udc∗. Because of the double-frequency ripple component in the DC-bus voltage, in a low-pass filter, such as the hold filter(21)Hs=1-e-Ts/2Ts/2,where T is the fundamental period of the system, H(s) can be adopted to measure the DC component of Udc for feedback.Figure 16
Control strategy of MMC under unbalanced grid voltage.Firstly, according to the DC voltage outer loop, the reference valueidref of the d-axis current is obtained. Since the three-phase converter is mainly used for active power transmission from the three-phase grid, the reference value iqref of the q-axis current is set to 0. Secondly, the reference values iαref and iβref of the current inner loop are obtained by a dq/αβ coordinate transformation, and then, by comparison with the actual current values isα and isβ in the αβ coordinate system, the errors between references and actual currents are used to generate the voltage references uαref and uβref through the quasi-proportional resonant (Q-PR) regulator. The transfer function of Q-PR is as follows [14, 15]: (22)GQ-PRs=Kp+2ωcss2+2ωcs+ω02Kr,where Kp is the proportional coefficient, Kr is the resonant coefficient, ωc is the cut-off frequency which generally ranges from 5 to 15 rad/s, and ω0 is the resonant frequency.Thirdly, the three-phase voltage modulation wavesuaref, ubref, and ucref can be obtained by a αβ/abc transformation. In addition, the three-phase voltage modulation wave is changed from the sine wave to the flat top wave because of the injection of zero-sequence voltage which can effectively improve the utilization of the DC voltage.The expression ofu0 is as follows:(23)u0=0.5max⁡uaref,ubref,ucref+min⁡uaref,ubref,ucref.The three-phase modulation voltage after the injection of zero-sequence voltage is as follows:(24)uaref∗=uaref-u0,ubref∗=ubref-u0,ucref∗=ucref-u0.Finally, the voltage referencesuaref∗, ubref∗, and ucref∗ are easy to generate the pulse width modulation (PWM) signals to drive the three-phase converter.


## 5.4. Simulation Results

A simulation model for a 10 MW/±40 kV MMC system was constructed using PSCAD/EMTDC to verify the theoretical analysis for the electrical quantities of the MMC. The system structure is shown in Figure5, and the simulation parameters are shown in Table 4. When t=3 s, the grounding short-circuit fault of phase A occurs, and the duration time of fault is 1 s.Table 4
Simulation parameters of MMC.
Parameters
Values
Rated capacity of MMC
10 MVA
Transformer ratio (Y/Δ)
110 kV/40 kV
Rated DC voltage of MMC
±40 kV
Number of SMs of each arm
50
Capacitance of each SM
1400μF
Arm inductance
140 mHAs can be seen from Figure17, the grounding short-circuit fault of phase A occurs when t=3 s (Figure 17(a)), and the three-phase current of AC grid is seriously asymmetric (Figure 17(b)); there is the second-order harmonic component in the DC voltage (Figure 17(c)); the DC component of the three-phase circulating current is not symmetrical (Figure 17(d)); the amplitude of the capacitor ripple voltage of the SM is increased (Figure 17(e)). In summary, the simulation results verify the correctness of the theoretical analysis.Figure 17
Simulation results without suppressing the negative-sequence current. (a) Phase voltage of AC grid. (b) Phase current of AC grid. (c) DC voltage. (d) DC component of the circulating current. (e) Capacitor voltage.
(a)
(b)
(c)
(d)
(e)In Figure18, similarly, the grounding short-circuit fault of phase A occurs when t=3 s (Figure 18(a)). Because the negative-sequence current is suppressed, the three-phase current of AC grid is symmetric (Figure 18(b)). The second-order harmonic component in the DC voltage (Figure 18(c)), the DC component of the three-phase circulating current (Figure 18(d)), and the amplitude of the capacitor ripple voltage of the SM (Figure 18(e)) all decreased; but they can not be completely eliminated, due to the existence of negative-sequence voltage.Figure 18
Simulation results with suppressing the negative-sequence current. (a) Phase voltage of AC grid. (b) Phase current of AC grid. (c) DC voltage. (d) DC component of the circulating current. (e) Capacitor voltage.
(a)
(b)
(c)
(d)
(e)


## 6. Conclusions

In this paper, we studied the control strategy of the AC-DC-AC substation based on MMC. Firstly, a parallel sorting algorithm based on FPGA to solve the MMC capacitor voltage balancing problem was studied. This algorithm can be performed in four clock cycles, and the computation time does not vary with changes in the number of submodules. And the experimental results verify the correctness of the sorting algorithm. Secondly, the effect of negative-sequence current on MMC is analyzed in theory and the correctness of the theoretical analysis is verified by simulation. The effects mainly include the following: the DC component of the three-phase circulating current is not symmetrical; the amplitude of the capacitor ripple voltage of the SM is increased; and there is the second-order harmonic component in the DC voltage. Also, the effective suppression of negative-sequence current is achieved by using PR controller.



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*Source: 4157165-2017-11-08.xml*