# Diophantine Frequency Synthesizer Design for Timekeeping Systems

Authors: Paul P. Sotiriadis; Gregory L. Weaver
Journal: International Journal of Navigation and Observation
 (2008)

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## Abstract

Diophantine Frequency Synthesis (DFS), a number-theoretic approach to the design of very high resolution frequency synthesizers, was introduced in 2006. Further work concerning the impact of controlling mixing products for high-spectral purity was addressed and reported at the 2007 European Frequency and Time Forum. The focus of this paper is on the implementation of nested DFS architectures targeting microphase-type applications for precision timekeeping systems.
We have shown that DFS does not impart any extraordinary design constraints on spectral purity in comparison to commonly used high resolution frequency synthesis techniques such as DDS or fractionalN. Here we describe a design approach for
10 MHz synthesizers with 1E-13 fractional resolution in consecutive steps ranging ±10 Hz. The synthesizers generate their output  from a 10 MHz reference standard. Such synthesizers are essential to accomplishing precision frequency correction in timekeeping systems.


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## Body

## 1. Introduction

In timekeeping systems,
a local frequency and/or phase must be generated and maintained to a very high
degree of accuracy. For example, the Time and Frequency Laboratory of the Johns
Hopkins University Applied Physics Laboratory maintains UTC (APL) within±10 nanoseconds,
based on monthly reports from the Bureau International des Poids et Mesures
(BIPM). Modern timekeeping systems use phase-frequency correction (steering)
through auxiliary synthesizers to maintain the accuracy of their master clocks
to UTC. The frequency step resolution of synthesizers for steering timekeeping
systems is typically 1 μHz or better. Designers of these very fine resolution
synthesizers must carefully consider signal purity, resolution (accuracy to the
global reference), and complexity. Our paper describes the Diophantine Frequency
Synthesis (DFS) design approach for very fine frequency resolution synthesizers
suitable for the maintenance of autonomous clock holdover and microphase
steering in laboratory timekeeping systems.The novel DFS approach
was introduced in 2006 [1, 2]. We have found that DFS alleviates the
conventional trades in performance for frequency synthesizer design without
significantly taxing system complexity or resources. DFS provides high spectral
purity, even in synthesizers with much less than 0.1 PPM resolution steps. In
general, we make this claim in comparison with other fine resolution frequency
synthesizer methods such as Direct Digital Synthesis (DDS) or fractional-N
modulators which are known to present a high degree of unwanted spurious signals
into the output spectrum through the fundamental process that they impart on
the input reference signal [3]. The use of DDS and fractional-N synthesis
design techniques has been widely adopted for timekeeping systems as high-frequency
resolution (accuracy) and fast acquisition (settling time) can be achieved
without the complexity of traditional multiple loop synthesizers. However, DDS
and fractional-N synthesizers both cause phase perturbations in their basic
operation schemes leading to coherent spurious generation [3]. In the case of DDS, accuracy to a desired frequency
necessarily compromises the spectral purity of the output signal by the
incidence of truncation spurious attributable to the finite size of sin/cos lookup
table and the DAC [4].DFS uses only exactly periodic
signals, without employing dithering, interpolation, pulse removal, or any
other approximately-periodic waveform that may corrupt the spectrum close to
the carrier. DFS-based synthesizers present no discontinuity of the reference
frequency phase, such as DDS or fractional-N, and unlike these methods, DFS
does not require any special devices such as high-resolution DACs, accumulators,
or sigma-delta modulators to control the spurious level of the output
signal.However, like traditional multiple loop PLL synthesizer
architectures, DFS does require mixing (or multiplication) to achieve the
output signal. This means that DFS synthesizers can suffer from unwanted
spurious if attention to the circuit design is not adequately respected. In our
2007 EFTF paper, we described an approach for the design of VHF synthesizers
with high-spectral purity of >100 dB spurious free dynamic range and showed
that DFS presents no unique design-related constraints [5]. Rather, DFS design
flexibility provides an advantage to achieving this level of performance in
fine resolution frequency synthesis.


## 2. DFS—Elements of the Theory

DFS is a number-theoretic approach to frequency synthesis. It is
based on mathematical properties of integer numbers and linear Diophantine
equations [2] (by definition, a Diophantine equation is an algebraic equation
whose solutions are required to be integers [6]).DFS
results in high-level architectures using two or more Integer-N PLLs.
It distributes the desirable
output-frequency resolution among these constituent PLLs in such a manner that
the resultant output fractional-frequency resolution is equal to the product of the constituent PLLs’ fractional-frequency resolutions. Consequently, this
property of DFS allows for the output frequency resolution to be made
(arbitrarily) fine, that is, to have a very small frequency step, without using
large prescalers or low
phase-comparator frequencies in the PLL.


### 2.1. The Abstract DFS Concept

DFS considers a PLL as a multiplier of an input frequencyfin by a rational number mi/Ni,
as shown in Figure 1.Figure 1
A two-PLL DFS scheme.In Figure1, two PLLs (i.e., two multipliers by m1/N1 and m2/N2) are driven by the same reference
frequency fin.
Their output signals are mixed (and the mixer’s output is
filtered - not shown) to produce the synthesizer’s output
signal of frequency fout which typically is
fout=f1+f2, as it is here, or fout=f1−f2. Further
discussion on mixing follows in Section 3.As it is always the case with integer-N PLLs, the
frequency resolution (step) of the individual PLLs in Figure 1 equals PLL’s
phase-comparator frequency, that is, fin/N1 and fin/N2, respectively.
Therefore, to get smaller frequency steps (higher resolution) from a single
PLL, a larger prescaler Ni and/or lower reference frequency fin are required. This, necessarily results in a
lower phase-comparator frequency fin/Ni implying slowed frequency lock acquisition (agility) and potentially
increased spurious signal levels closer to the carrier signal of fout [3].DFS overcomes these problems as it allows simultaneously
for both high phase-comparator frequencies at the constituent PLLs and
arbitrarily small frequency step at the output of the synthesizer. In the case of
DFS scheme in Figure1, the frequency step is (1)δfout=finN1N2which can be orders of magnitude smaller that fin/N1 and fin/N2. This property of DFS is generalized in the
case of k PLLs.Throughout this paper, the prescalers (Ni’s) of the PLLs are considered fixed in size. Moreover, it is assumed
that by design, the greatest common divisor of every pair of prescalers, (Ni,Nj), is one , that is, the prescalers are pairwise
prime integers; this is a requirement of the DFS
methodology [2].Finally, it is convenient to replace the value of every
feedback dividermi by the sum m¯i+mi (e.g., as in
Figure 2), where m¯i is a fixed positive integer and the
variable part, mi, is restricted to take integer values within
the range    −Ni to Ni.
So the range of  values of
the feedback divider is m¯i−Ni,…,m¯i+Ni.


### 2.2. Basic Numerical Example of a
Two-PLL DFS Scheme

Consider
the architecture of Figure2 consisting of two PLLs driven by the same
reference frequency fin,
whose output frequencies are
summed resulting in (2)fout=(11+m13+9+m22)fin.Figure 2
A simple two-PLL DFS scheme.Following DFS methodology [2], the prescalers, N1=3 and N2=2,
are fixed and relatively prime by design (small integers were selected here for
illustration purposes).The feedback dividers are11+m1 and 9+m2 with
−3≤m1≤3 and −2≤m2≤2.
So, the range of each PLL feedback
divider is twice the size of the corresponding prescaler. These imply that
frequency f1 can take any of seven values f1∈{8/3,9/3,…,14/3} and frequency f2 can
take any of five values f2∈{7/2,8/2,…,11/2}.Table1
shows (some of) the output frequencies fout that
can be generated by using the DFS algorithm in [2] to program the values of m1 and m2 within their preassumed
ranges −3≤m1≤3 and −2≤m2≤2,
respectively. Every one of the thirteen triplets  (m1,m2,a) in Table 1 satisfies the linear Diophantine equation (3)m13+m22=a6.This way we can synthesize all frequencies of the form (4)fout=f¯out+a6finwith the variable a taking the values −6,−5,…,6 and the
central frequency f¯out being (5)f¯out=(113+92)fin=496fin.Table 1
Frequencies of the DFS example in Figure2.
fout=(113+92)fin+(m13+m22)finm1m2afout/fin=(113+92)+(m13+m22)−30−643/6=49/6+−6/6−1−1−544/6=49/6+−5/6−20−445/6=49/6+−4/60−1−346/6=49/6+−3/6−10−247/6=49/6+−2/61−1−148/6=49/6+−1/600049/6=49/6+0−11150/6=49/6+1/610251/6=49/6+2/601352/6=49/6+3/620453/6=49/6+4/611554/6=49/6+5/630655/6=49/6+6/6Note: the phase comparator frequencies of the individual
PLLs arefin/3 and fin/2 while the synthesizer’s frequency resolution
(step size) is fin/6.In
general, a two-PLL DFS synthesizer results in output frequency(6)fout=(m¯1N1+m¯2N2)fin+aN1N2fin,where the variable a can take any of the consecutive values from −N1N2 to N1N2. This leads, by inspection of (6), to the fundamental property of DFS that
the frequency step can be made much smaller than
the phase-comparator frequencies the constituent PLLs, that is,(7)finN1N2≪finN1,finN2.Expression
(6) itself results from our ability to find a
convenient solution of the linear Diophantine Equation (8)m1N1+m2N2=aN1N2.Note
that the relationship betweenm1, m2,
and a,
governed by (8), is nontrivial and in some
cases is  not unique, in the sense that there may be more than one pair of
integers (m1,m2) that solve (8) for a particular value of
integer a.Furthermore,
it has been proven that if we have a solution(m1,m2) of (8) for a=1,
then we can easily generate solutions for every other value of a;
therefore in a hardware implementation, very few numbers have to be stored. A detailed description of how to solve linear
Diophantine Equations efficiently is also available in [2].


### 2.3. DFS Synthesizers withk  PLLs

The
general abstract high-level architecture ofk-PLL DFS synthesizers is shown in Figure 3.Figure 3
Abstract high-levelk-PLL
DFS scheme.It has
been proven, in [2], that when the integer
variables m1,m2,…,mk are allowed to take any values in the intervals  −N1≤m1≤N1,−N2≤m2≤N2,…,−Nk≤mk≤Nk, respectively, then the following set of
frequencies can be synthesized: (9)fout=f¯out+aN1N2⋯Nkfin,where a can take any of the values (10)a=−N1N2⋯Nk,…,N1N2⋯Nkand the central frequency f¯out is (11)f¯out=(m¯1N1+m¯2N2+⋯+m¯kNk)fin.Therefore, the frequency resolution (step) achieved by k-PLL DFS architectures is (12)δfout=finN1N2⋯Nk.The central frequencyf¯out can be adjusted with
resolution δfout as well. The mathematical details,
theorems, and their proofs of the general k-PLL DFS
architectures can be found in [2].


## 2.1. The Abstract DFS Concept

DFS considers a PLL as a multiplier of an input frequencyfin by a rational number mi/Ni,
as shown in Figure 1.Figure 1
A two-PLL DFS scheme.In Figure1, two PLLs (i.e., two multipliers by m1/N1 and m2/N2) are driven by the same reference
frequency fin.
Their output signals are mixed (and the mixer’s output is
filtered - not shown) to produce the synthesizer’s output
signal of frequency fout which typically is
fout=f1+f2, as it is here, or fout=f1−f2. Further
discussion on mixing follows in Section 3.As it is always the case with integer-N PLLs, the
frequency resolution (step) of the individual PLLs in Figure 1 equals PLL’s
phase-comparator frequency, that is, fin/N1 and fin/N2, respectively.
Therefore, to get smaller frequency steps (higher resolution) from a single
PLL, a larger prescaler Ni and/or lower reference frequency fin are required. This, necessarily results in a
lower phase-comparator frequency fin/Ni implying slowed frequency lock acquisition (agility) and potentially
increased spurious signal levels closer to the carrier signal of fout [3].DFS overcomes these problems as it allows simultaneously
for both high phase-comparator frequencies at the constituent PLLs and
arbitrarily small frequency step at the output of the synthesizer. In the case of
DFS scheme in Figure1, the frequency step is (1)δfout=finN1N2which can be orders of magnitude smaller that fin/N1 and fin/N2. This property of DFS is generalized in the
case of k PLLs.Throughout this paper, the prescalers (Ni’s) of the PLLs are considered fixed in size. Moreover, it is assumed
that by design, the greatest common divisor of every pair of prescalers, (Ni,Nj), is one , that is, the prescalers are pairwise
prime integers; this is a requirement of the DFS
methodology [2].Finally, it is convenient to replace the value of every
feedback dividermi by the sum m¯i+mi (e.g., as in
Figure 2), where m¯i is a fixed positive integer and the
variable part, mi, is restricted to take integer values within
the range    −Ni to Ni.
So the range of  values of
the feedback divider is m¯i−Ni,…,m¯i+Ni.


## 2.2. Basic Numerical Example of a
Two-PLL DFS Scheme

Consider
the architecture of Figure2 consisting of two PLLs driven by the same
reference frequency fin,
whose output frequencies are
summed resulting in (2)fout=(11+m13+9+m22)fin.Figure 2
A simple two-PLL DFS scheme.Following DFS methodology [2], the prescalers, N1=3 and N2=2,
are fixed and relatively prime by design (small integers were selected here for
illustration purposes).The feedback dividers are11+m1 and 9+m2 with
−3≤m1≤3 and −2≤m2≤2.
So, the range of each PLL feedback
divider is twice the size of the corresponding prescaler. These imply that
frequency f1 can take any of seven values f1∈{8/3,9/3,…,14/3} and frequency f2 can
take any of five values f2∈{7/2,8/2,…,11/2}.Table1
shows (some of) the output frequencies fout that
can be generated by using the DFS algorithm in [2] to program the values of m1 and m2 within their preassumed
ranges −3≤m1≤3 and −2≤m2≤2,
respectively. Every one of the thirteen triplets  (m1,m2,a) in Table 1 satisfies the linear Diophantine equation (3)m13+m22=a6.This way we can synthesize all frequencies of the form (4)fout=f¯out+a6finwith the variable a taking the values −6,−5,…,6 and the
central frequency f¯out being (5)f¯out=(113+92)fin=496fin.Table 1
Frequencies of the DFS example in Figure2.
fout=(113+92)fin+(m13+m22)finm1m2afout/fin=(113+92)+(m13+m22)−30−643/6=49/6+−6/6−1−1−544/6=49/6+−5/6−20−445/6=49/6+−4/60−1−346/6=49/6+−3/6−10−247/6=49/6+−2/61−1−148/6=49/6+−1/600049/6=49/6+0−11150/6=49/6+1/610251/6=49/6+2/601352/6=49/6+3/620453/6=49/6+4/611554/6=49/6+5/630655/6=49/6+6/6Note: the phase comparator frequencies of the individual
PLLs arefin/3 and fin/2 while the synthesizer’s frequency resolution
(step size) is fin/6.In
general, a two-PLL DFS synthesizer results in output frequency(6)fout=(m¯1N1+m¯2N2)fin+aN1N2fin,where the variable a can take any of the consecutive values from −N1N2 to N1N2. This leads, by inspection of (6), to the fundamental property of DFS that
the frequency step can be made much smaller than
the phase-comparator frequencies the constituent PLLs, that is,(7)finN1N2≪finN1,finN2.Expression
(6) itself results from our ability to find a
convenient solution of the linear Diophantine Equation (8)m1N1+m2N2=aN1N2.Note
that the relationship betweenm1, m2,
and a,
governed by (8), is nontrivial and in some
cases is  not unique, in the sense that there may be more than one pair of
integers (m1,m2) that solve (8) for a particular value of
integer a.Furthermore,
it has been proven that if we have a solution(m1,m2) of (8) for a=1,
then we can easily generate solutions for every other value of a;
therefore in a hardware implementation, very few numbers have to be stored. A detailed description of how to solve linear
Diophantine Equations efficiently is also available in [2].


## 2.3. DFS Synthesizers withk  PLLs

The
general abstract high-level architecture ofk-PLL DFS synthesizers is shown in Figure 3.Figure 3
Abstract high-levelk-PLL
DFS scheme.It has
been proven, in [2], that when the integer
variables m1,m2,…,mk are allowed to take any values in the intervals  −N1≤m1≤N1,−N2≤m2≤N2,…,−Nk≤mk≤Nk, respectively, then the following set of
frequencies can be synthesized: (9)fout=f¯out+aN1N2⋯Nkfin,where a can take any of the values (10)a=−N1N2⋯Nk,…,N1N2⋯Nkand the central frequency f¯out is (11)f¯out=(m¯1N1+m¯2N2+⋯+m¯kNk)fin.Therefore, the frequency resolution (step) achieved by k-PLL DFS architectures is (12)δfout=finN1N2⋯Nk.The central frequencyf¯out can be adjusted with
resolution δfout as well. The mathematical details,
theorems, and their proofs of the general k-PLL DFS
architectures can be found in [2].


## 3. Frequency-Offset DFS Architectures for Very High Fractional-Frequency Resolution

Synthesizers with very high fractional-frequency resolution like
microphase steppers, advanced signal generators, certain instrumentation
equipment, atomic-clock synthesizers, and so forth, often have performance
specifications that challenge existing technology solutions especially under
cost, power, size, and complexity constraints. DFS offers a new alternative to
DDS and fractional-N PLLs in the design of such systems.For this kind of applications, most appropriate DFS
architecture has been proven to be the one based on frequency
offsetting [3]. Since
frequency offsetting requires mixing, a few comments are in order without any intention to cover the topic of
mixing.


### 3.1. Frequency Mixing

Mixing of two periodic signals at frequenciesf1 and f2 is denoted by ⊗,
see Figure 4, and the outcome is
typically chosen to be either f1+f2 or f1−f2.Figure 4
Frequency-offset
loop.Mixing of three or more signals has a similar
interpretation, note however that the order of performing the mixing of the
signals may be important for getting a spectrally pure output signal. In
general, minimization of mixing spurs involves the choice of the central
frequencies off1 and f2,
their frequency ranges, the choice of the sum or difference, the harmonic
contents of the mixed signals, and of course the type of the mixers.The key
to low-output spurs in DFS synthesizers is the mixing method since the mixers
are the dominant spurs generating circuit elements.


### 3.2. Frequency Offsetting

The
synthesizer architecture in Figure4 is convenient for deriving the sum or
difference between a large fin and a small offset frequency f.Whenf/fin≪1,
the mixing of fin with fin±f can be performed without difficulty and the
mixing spurs can be minimal, for example, [5]. Therefore frequency offsetting
is an effective approach to achieving the frequency summations and/or subtractions
needed to realize DFS with central output frequency close to fin.The following subsections illustrate this
approach for the case of two- and three-PLL DFS schemes. In principle, the
structure of Figure4 can be cascaded k times to create k-PLL DFS architectures.


### 3.3. Two-PLL Frequency-Offset
DFS Architecture

Figure5
shows how two DFS-determined PLLs can be cascaded using an offset synthesizer
structure to form a DFS architecture, where the variable fout can be adjusted in very small-frequency steps
from the reference fin.Figure 5
Two-PLL frequency-offset DFS scheme.Based on
the DFS theory [2], the two PLL output frequencies f1, f2 (we can consider divider R as part of the PLLs) are determined by the
common dividers Q, R,
the two relatively prime integers N1, N2, and the feedback dividers pN1+m1 and pN2+m2 which are partitioned into the fixed, pN1, pN2,
and the variable, m1, m2,
parts. The values of m1, m2 program the value of parameter a in
expression (6). The fixed
integers pN1 and pN2 partially define the central frequencies f¯1, f¯2 of the PLLs. In this application, we also like
to have f¯1=f¯2 which implies that fout=fin when m1=m2=0.Variablesm1 and m2 are allowed to take any value within their ranges −N1,…,N1 and −N2,…,N2, respectively. This results in output-frequency
resolution
equal to δfout=fin/(QRN1N2) and output-frequency range (equal to or
greater than) Δfout=±fin/(QR). (Note the product of N1 and N2 in the
denominator, in contrast to Q that is accounted
for on its first power.)The
factorQ in the denominators determines the pullability
ranges of the VCOs in the PLLs. Specifically, given the ranges of m1 and m2,
the VCO’s fractional pullability is PLPLL_1,2=±(100/Q)%.
The role of p in the numerators is to adjust for the central
output frequencies of the PLLs by counterbalancing Q. The
phase-comparator frequencies of the PLLs are fPC_PLL_i=fin/(QNi), i=1,2.Finally,R is a large divider necessary to generate the
relatively small frequencies f1, f2 from the output frequencies of the PLLs. Divider R also contributes to the output resolution of
the synthesizer and the spectral purity of signals entering the
frequency-offset blocks.With a
microphase stepper application in mind, Figure6 shows a choice of values for N1, N2, R, Q,
and p,
and the corresponding characteristics and performance of the synthesizer they
result in. A resolution of 10 μHz is probably the best that the two-PLL scheme
with 10 MHz input frequency could give. Note that although
the 100 Hz frequency offset is not uncommon in these types
of systems, a higher frequency would be helpful. The pullability range of ±10% is achievable by tunable LC oscillators, and
because of the large divider R,
the phase noise of the oscillators is not a critical issue.Figure 6
Numerical example of the two-PLL frequency-offset DFS scheme in Figure5.As
described in Figure6, the magnitude of R was made large compared to Q, N1,
and N2 to achieve the desired frequency-step resolution of ±10 μHz while keeping the
PLL phase-comparator frequencies relatively large and
easy to filter. This choice was not directed
through any fundamental constraint in the DFS method, but was made from our
design emphasis on high-spectral purity over acquisition speed in a simple,
practical circuit implementation. In the following subsection, we see how
adding one more PLL allows for more choices of the parameters and, in principle,
better overall performance.


### 3.4. Three-PLL Frequency-Offset
DFS Architecture

A
three-PLL frequency-offset DFS architecture is shown in Figure7. Its
principles of operation are very similar to those of the two-PLL one in Figure 5. The
major difference is that because of the odd number of PLLs, centering fout with respect to the input reference fin requires further design consideration.Figure 7
Three-PLL frequency-offset DFS scheme.Specifically,
it  is desirable thatm1=m2=m3=0 implies fout=fin.
To achieve this, we add f1 and f2 to fin and subtract f3.
Moreover, we introduce factors of 2 in PLL 3 and in the R-dividers of PLLs 1 and 2. These result in 2f¯1=2f¯2=f¯3=pfin/(QR) and equal ranges of f1, f2,
and f3.
However, the pullability range of PLL 3 is the half of that of PLLs 1 and 2.
The expression for fout is shown in Figure 7.IntegersN1,N2, and N3 are chosen to be pairwise prime and the
variables m1, m2,
and m3 take values within their ranges −N1,…,N1, −N2,…,N2,
and −N3,…,N3,
respectively. The resulting output frequency resolution is δfout=fin/(2QRN1N2N3) and the output frequency range is (equal to or greater than) Δfout=±fin/(2QR).Again,
with a microphase stepper application in mind, Figure8 shows a choice of numerical
values for N1,N2,N3,R,Q,
and p,
as well as the corresponding characteristics of the resulting synthesizer. Output
frequency resolution of 1 μHz and output range of about ±16 Hz are achieved. The frequency offset has been
raised to 500 Hz for PLLs 1, 2 and to 1000 Hz for PLL 3, and the pullability ranges have
dropped to about ±3% and ±1.6%, respectively. Therefore, as expected, the
three-PLL case provides much more flexibility in the design and much better
characteristics.Figure 8
Numerical example of the three-PLL
frequency-offset DFS scheme in Figure7.


## 3.1. Frequency Mixing

Mixing of two periodic signals at frequenciesf1 and f2 is denoted by ⊗,
see Figure 4, and the outcome is
typically chosen to be either f1+f2 or f1−f2.Figure 4
Frequency-offset
loop.Mixing of three or more signals has a similar
interpretation, note however that the order of performing the mixing of the
signals may be important for getting a spectrally pure output signal. In
general, minimization of mixing spurs involves the choice of the central
frequencies off1 and f2,
their frequency ranges, the choice of the sum or difference, the harmonic
contents of the mixed signals, and of course the type of the mixers.The key
to low-output spurs in DFS synthesizers is the mixing method since the mixers
are the dominant spurs generating circuit elements.


## 3.2. Frequency Offsetting

The
synthesizer architecture in Figure4 is convenient for deriving the sum or
difference between a large fin and a small offset frequency f.Whenf/fin≪1,
the mixing of fin with fin±f can be performed without difficulty and the
mixing spurs can be minimal, for example, [5]. Therefore frequency offsetting
is an effective approach to achieving the frequency summations and/or subtractions
needed to realize DFS with central output frequency close to fin.The following subsections illustrate this
approach for the case of two- and three-PLL DFS schemes. In principle, the
structure of Figure4 can be cascaded k times to create k-PLL DFS architectures.


## 3.3. Two-PLL Frequency-Offset
DFS Architecture

Figure5
shows how two DFS-determined PLLs can be cascaded using an offset synthesizer
structure to form a DFS architecture, where the variable fout can be adjusted in very small-frequency steps
from the reference fin.Figure 5
Two-PLL frequency-offset DFS scheme.Based on
the DFS theory [2], the two PLL output frequencies f1, f2 (we can consider divider R as part of the PLLs) are determined by the
common dividers Q, R,
the two relatively prime integers N1, N2, and the feedback dividers pN1+m1 and pN2+m2 which are partitioned into the fixed, pN1, pN2,
and the variable, m1, m2,
parts. The values of m1, m2 program the value of parameter a in
expression (6). The fixed
integers pN1 and pN2 partially define the central frequencies f¯1, f¯2 of the PLLs. In this application, we also like
to have f¯1=f¯2 which implies that fout=fin when m1=m2=0.Variablesm1 and m2 are allowed to take any value within their ranges −N1,…,N1 and −N2,…,N2, respectively. This results in output-frequency
resolution
equal to δfout=fin/(QRN1N2) and output-frequency range (equal to or
greater than) Δfout=±fin/(QR). (Note the product of N1 and N2 in the
denominator, in contrast to Q that is accounted
for on its first power.)The
factorQ in the denominators determines the pullability
ranges of the VCOs in the PLLs. Specifically, given the ranges of m1 and m2,
the VCO’s fractional pullability is PLPLL_1,2=±(100/Q)%.
The role of p in the numerators is to adjust for the central
output frequencies of the PLLs by counterbalancing Q. The
phase-comparator frequencies of the PLLs are fPC_PLL_i=fin/(QNi), i=1,2.Finally,R is a large divider necessary to generate the
relatively small frequencies f1, f2 from the output frequencies of the PLLs. Divider R also contributes to the output resolution of
the synthesizer and the spectral purity of signals entering the
frequency-offset blocks.With a
microphase stepper application in mind, Figure6 shows a choice of values for N1, N2, R, Q,
and p,
and the corresponding characteristics and performance of the synthesizer they
result in. A resolution of 10 μHz is probably the best that the two-PLL scheme
with 10 MHz input frequency could give. Note that although
the 100 Hz frequency offset is not uncommon in these types
of systems, a higher frequency would be helpful. The pullability range of ±10% is achievable by tunable LC oscillators, and
because of the large divider R,
the phase noise of the oscillators is not a critical issue.Figure 6
Numerical example of the two-PLL frequency-offset DFS scheme in Figure5.As
described in Figure6, the magnitude of R was made large compared to Q, N1,
and N2 to achieve the desired frequency-step resolution of ±10 μHz while keeping the
PLL phase-comparator frequencies relatively large and
easy to filter. This choice was not directed
through any fundamental constraint in the DFS method, but was made from our
design emphasis on high-spectral purity over acquisition speed in a simple,
practical circuit implementation. In the following subsection, we see how
adding one more PLL allows for more choices of the parameters and, in principle,
better overall performance.


## 3.4. Three-PLL Frequency-Offset
DFS Architecture

A
three-PLL frequency-offset DFS architecture is shown in Figure7. Its
principles of operation are very similar to those of the two-PLL one in Figure 5. The
major difference is that because of the odd number of PLLs, centering fout with respect to the input reference fin requires further design consideration.Figure 7
Three-PLL frequency-offset DFS scheme.Specifically,
it  is desirable thatm1=m2=m3=0 implies fout=fin.
To achieve this, we add f1 and f2 to fin and subtract f3.
Moreover, we introduce factors of 2 in PLL 3 and in the R-dividers of PLLs 1 and 2. These result in 2f¯1=2f¯2=f¯3=pfin/(QR) and equal ranges of f1, f2,
and f3.
However, the pullability range of PLL 3 is the half of that of PLLs 1 and 2.
The expression for fout is shown in Figure 7.IntegersN1,N2, and N3 are chosen to be pairwise prime and the
variables m1, m2,
and m3 take values within their ranges −N1,…,N1, −N2,…,N2,
and −N3,…,N3,
respectively. The resulting output frequency resolution is δfout=fin/(2QRN1N2N3) and the output frequency range is (equal to or greater than) Δfout=±fin/(2QR).Again,
with a microphase stepper application in mind, Figure8 shows a choice of numerical
values for N1,N2,N3,R,Q,
and p,
as well as the corresponding characteristics of the resulting synthesizer. Output
frequency resolution of 1 μHz and output range of about ±16 Hz are achieved. The frequency offset has been
raised to 500 Hz for PLLs 1, 2 and to 1000 Hz for PLL 3, and the pullability ranges have
dropped to about ±3% and ±1.6%, respectively. Therefore, as expected, the
three-PLL case provides much more flexibility in the design and much better
characteristics.Figure 8
Numerical example of the three-PLL
frequency-offset DFS scheme in Figure7.


## 4. Summary

In
summary, the general structure of DFS architectures provides the following
desirable properties: the ability to achieve a predetermined center frequency(13)f¯out=(m¯1N1+m¯2N2+⋯+m¯kNk)finwith frequency range (14)f¯out−fintof¯out+finand frequency step (resolution) of (15)δfout=finN1N2⋯Nk,while the phase-comparator frequencies of the constituent PLLs are (16)finN1,finN2,…,finNk.The
application of DFS permits high flexibility on the relationship of the fixed-frequency
reference to output frequency (9) with wide-frequency range (14). Based on
(15), we have shown the design of very fine frequency resolution using two- and
three-PLL nested DFS frequency-offset loops.In the
case of the three-loop system described in Figure7, a fractional frequency
synthesizer capable of 1E-13 has been numerically demonstrated. The method of cascading nested frequency-offset DFS architectures to higher orders
would ultimately result in frequency steering resolution
approaching 1E-15, consistent with the needs of most
precision timekeeping laboratories contributing to UTC.



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*Source: 416958-2008-03-18.xml*