# Control Design and Loop Gain Analysis of DC-to-DC Converters Intended for General Load Subsystems

Authors: Syam Kumar Pidaparthy; Byungcho Choi
Journal: Mathematical Problems in Engineering
 (2015)

---

## Abstract

DC-to-DC converters are usually intended for general applications where the load impedance
characteristics are unknown or undefined. This paper establishes the control design procedures
for DC-to-DC converters in the absence of any prior knowledge on their load impedance. The
proposed control design can be universally adapted to all the DC-to-DC converters regardless
of the impedance characteristics of their actual load. This paper also presents the loop gain
analysis of the converter combined with an actual load whose impedance characteristics are
only available afterward. A graphical analysis method is proposed, which enables us to predict
the loop gain of the converter in the presence of an arbitrary load impedance. The validity of
the analysis method is demonstrated using a current-mode controlled buck converter coupled
with an inductive load, capacitive load, and converter load. Theoretical predictions are verified
with both computer simulations and experimental measurements.


---

## Body

## 1. Introduction

For most practical applications, the load impedance of a converter is unknown or undefined until the actual load is all fabricated and integrated with the DC-to-DC converter, to operate as a complete DC-to-DC power conversion system [1–5]. Accordingly, DC-to-DC converters are to be designed and tested as a standalone module, without any prior information about the load impedance.When the converter is later connected to the actual load, the converter’s performance will be affected by the load impedance. These operational conditions present two major challenges in the control design and performance analysis of DC-to-DC converters for real applications:(i)
The control should be designed in the absence of any knowledge on the load impedance. The resulting design should offer good performance for DC-to-DC converters as a standalone module.(ii)
Whenever the information about the load impedance is available, the converter’s performance in the real application should be assessed as accurately as possible.The prime consideration in control design and performance evaluation is the loop gain of the converter. The loop gain carries the whole information about stability and dynamics of the converter. Both the frequency and time-domain performance criteria are all governed by the loop gain characteristics [6].This paper first presents the control design for DC-to-DC converters whose load impedance characteristics are unspecified. The concept of acurrent-sink loaded converter is adopted in this paper, which allows DC-to-DC converters to be designed using only the DC power requirement. Based on the power stage dynamics, the control design procedures are formulated for good loop gain characteristics of the current-sink loaded converter. The control design procedures can be universally applied to all practical DC-to-DC converters regardless of the impedance characteristics of their actual load.The later part of the paper assumes that the converter is now connected to an actual load, whose impedance information is available only afterward. The paper then investigates the impacts of the load impedance on the loop gain characteristics. The paper presents a graphical method to predict the loop gain of the converter coupled with a practical load subsystem, such as an inductive load, capacitive load, or converter load consisting of a filter stage and another converter downstream.The validity of the design method and accuracy of the analysis result are demonstrated using a current-mode controlled buck converter. Theoretical predictions are verified with both computer simulations on the small-signal model and experimental measurements on the prototype converter using an impedance analyzer.


## 2. Current-Sink Loaded Current-Mode Controlled PWM DC-to-DC Converters

The section reviews the concept of the current-sink loaded converter and presents the small-signal model of current-mode controlled pulsewidth modulated (PWM) DC-to-DC converters operating under the current-sink loaded condition.


### 2.1. Current-Sink Loaded DC-to-DC Converter

Figure1 is a functional representation of the DC-to-DC converter feeding a general load subsystem. The load subsystem is depicted as a parallel combination of an impedance block ZL(s) and ideal current sink IO. ZL(s) is the impedance of the load subsystem, referred to as the load impedance, and IO corresponds to the DC output current flowing into the load subsystem.Figure 1
Functional representation of DC-to-DC converter feeding general load subsystem.The information about the load impedanceZL(s) is usually unavailable at the design stage of the converter. In contrast, the DC output current IO is always predefined before designing the converter. To cope with the problem of the uncertainty in the load impedance, one can envisage a DC-to-DC converter which delivers the rated DC current to an ideal current sink, thereby implying ZL(s)=∞ in Figure 1. The resulting converter is termed as thecurrent-sink loaded DC-to-DC converter. The current-sink loaded converter is designed as a standalone module and its performance can be tested using a current sink load. The performance of the converter coupled with an actual load will be treated in Section 4.


### 2.2. Current-Sink Loaded Current-Mode Controlled PWM DC-to-DC Converters

Current mode control is the most prevailing control scheme [7–15] for PWM DC-to-DC power converters. Figure 2(a) shows a schematic diagram of the current-mode controlled PWM converter feeding a current sink load. Figure 2(a) could represent all the three basic PWM converters, the buck converter, boost converter, and buck/boost converter, with the respective power stage connections. The converter consists of a power stage, pulsewidth modulation (PWM) block, current sensing network (CSN) for current mode control, and voltage feedback circuit. Figure 2(b) is the small-signal model of Figure 2(a), obtained by replacing the active-passive switch pair with the PWM switch model [16] and by replacing the PWM and CSN blocks with their small-signal models [7].Figure 2
Current-sink loaded and current-mode controlled PWM DC-to-DC converter. (a) The diagram represents the buck converter with connectionsa-Xp-Yi-Z, the boost converter with i-Xa-Yp-Z, and the buck/boost converter with a-Xi-Yp-Z. The CSN represents the current sensing network and PWM is the pulsewidth modulation block. (b) Small-signal model: D is the duty ratio and RD=Rl+DD′Re and VD=Vap+(D-D′)ReIL with D′=1-D, Re=0 for the buck converter, and Re=Rc for the boost and buck/boost converters. Consider IL=VO/RDC for the buck converter, IL=-VO/(RDCD′) for the boost converter, and IL=VO/(RDCD′) for the buck/boost converter with RDC=VO/IO. Ri represents the DC gain of CSN. He(s) is the sampling gain of CSN: He(s)=1+s/(ωnQz)+s2/ωn2 with Qz=-2/π and ωn=π/Ts, where Ts is the switching period. Fm=1/((Sn+Se)Ts) is the modulator gain [7] of PWM block with Sn: on-time slope of the sensed inductor current, Sn=VaiRi/L, and Se: slope of the compensation ramp. kr/kf represents the feedback/feedforward gain of current mode control [7]: kr=TsRi/(2L) for the buck converter, kr=(1-D)2TsRi/(2L) for the boost and buck/boost converters, kf=-TsRi/(2L) for the boost converter, and kf=-DTsRi(1-D/2)/L for the buck and buck/boost converters. Fv(s)=Z2/Z1 is the voltage feedback compensation.
(a)
(b)BecauseZL(s)=∞ for the current sink load, the power stage is terminated with the filter capacitor in series with its equivalent series resistance (esr). Nonetheless, the output current IO flowing into the current sink is embedded into the power stage model as a DC load parameter (1)RDC=VOIOwhich determines the coefficient of the dependent current source in the PWM switch model.


## 2.1. Current-Sink Loaded DC-to-DC Converter

Figure1 is a functional representation of the DC-to-DC converter feeding a general load subsystem. The load subsystem is depicted as a parallel combination of an impedance block ZL(s) and ideal current sink IO. ZL(s) is the impedance of the load subsystem, referred to as the load impedance, and IO corresponds to the DC output current flowing into the load subsystem.Figure 1
Functional representation of DC-to-DC converter feeding general load subsystem.The information about the load impedanceZL(s) is usually unavailable at the design stage of the converter. In contrast, the DC output current IO is always predefined before designing the converter. To cope with the problem of the uncertainty in the load impedance, one can envisage a DC-to-DC converter which delivers the rated DC current to an ideal current sink, thereby implying ZL(s)=∞ in Figure 1. The resulting converter is termed as thecurrent-sink loaded DC-to-DC converter. The current-sink loaded converter is designed as a standalone module and its performance can be tested using a current sink load. The performance of the converter coupled with an actual load will be treated in Section 4.


## 2.2. Current-Sink Loaded Current-Mode Controlled PWM DC-to-DC Converters

Current mode control is the most prevailing control scheme [7–15] for PWM DC-to-DC power converters. Figure 2(a) shows a schematic diagram of the current-mode controlled PWM converter feeding a current sink load. Figure 2(a) could represent all the three basic PWM converters, the buck converter, boost converter, and buck/boost converter, with the respective power stage connections. The converter consists of a power stage, pulsewidth modulation (PWM) block, current sensing network (CSN) for current mode control, and voltage feedback circuit. Figure 2(b) is the small-signal model of Figure 2(a), obtained by replacing the active-passive switch pair with the PWM switch model [16] and by replacing the PWM and CSN blocks with their small-signal models [7].Figure 2
Current-sink loaded and current-mode controlled PWM DC-to-DC converter. (a) The diagram represents the buck converter with connectionsa-Xp-Yi-Z, the boost converter with i-Xa-Yp-Z, and the buck/boost converter with a-Xi-Yp-Z. The CSN represents the current sensing network and PWM is the pulsewidth modulation block. (b) Small-signal model: D is the duty ratio and RD=Rl+DD′Re and VD=Vap+(D-D′)ReIL with D′=1-D, Re=0 for the buck converter, and Re=Rc for the boost and buck/boost converters. Consider IL=VO/RDC for the buck converter, IL=-VO/(RDCD′) for the boost converter, and IL=VO/(RDCD′) for the buck/boost converter with RDC=VO/IO. Ri represents the DC gain of CSN. He(s) is the sampling gain of CSN: He(s)=1+s/(ωnQz)+s2/ωn2 with Qz=-2/π and ωn=π/Ts, where Ts is the switching period. Fm=1/((Sn+Se)Ts) is the modulator gain [7] of PWM block with Sn: on-time slope of the sensed inductor current, Sn=VaiRi/L, and Se: slope of the compensation ramp. kr/kf represents the feedback/feedforward gain of current mode control [7]: kr=TsRi/(2L) for the buck converter, kr=(1-D)2TsRi/(2L) for the boost and buck/boost converters, kf=-TsRi/(2L) for the boost converter, and kf=-DTsRi(1-D/2)/L for the buck and buck/boost converters. Fv(s)=Z2/Z1 is the voltage feedback compensation.
(a)
(b)BecauseZL(s)=∞ for the current sink load, the power stage is terminated with the filter capacitor in series with its equivalent series resistance (esr). Nonetheless, the output current IO flowing into the current sink is embedded into the power stage model as a DC load parameter (1)RDC=VOIOwhich determines the coefficient of the dependent current source in the PWM switch model.


## 3. Power Stage Dynamics, Control Design, and Performance of Current-Sink Loaded Converter

Using the small-signal model in Figure2(b), this section presents the power stage dynamics and control design of the current-sink loaded converter. The power stage dynamics of the current-sink loaded converter are discussed in comparison with those of the converter coupled with an arbitrary load impedance. This provides insights on the versatility of the proposed control design. In ensuing discussions, the converter coupled with the load impedance is referred to as animpedance loaded converter. This section also illustrates the theoretical and experimental performance of the current-sink loaded current-mode controlled buck converter.


### 3.1. Control-to-Output Transfer Function

The vital information to the control design is the control-to-output transfer function,Gvci(s)=v^o/v^con, evaluated under the condition that only the current loop is closed and the connection to the voltage feedback compensation Fv(s) is broken at Point A in Figure 2(b). The knowledge of this transfer function allows us to design both the current loop and voltage feedback circuit for good loop gain characteristics. By applying the Mason’s gain rule to Figure 2(b) with v^s=ı^o=0, the control-to-output transfer function is determined as(2)Gvcis=v^ov^con=Fmv^o/d^1-krFmv^o/d^+RiHesFmı^L/d^.Although the Gvci(s) expression is rather involved, it can be reduced to a simple expression [17, 18] with some practical assumptions on power stage parameters and operational conditions. By following the procedures presented in [17], Gvci(s) is casted into the following third-order approximation: (3)Gvci≈Kvc1+s/ωesr1-s/ωrhp1+s/ωpl1+s/Qpωn+s2/ωn2.The noticeable feature of the transfer function is the quadratic term in the denominator. The quadratic term, originated from the sampling effects of the current mode control [7], introduces a double pole at half the switching frequency; ωn=π/Ts.Table1 shows the parameters appearing in the Gvci(s) expression of the three basic current-sink loaded PWM converters. This table also presents the expressions of Gvci(s) for the impedance loaded PWM converters, in order to contrast the small-signal dynamics of the current-sink loaded and impedance loaded converters. The load impedance is denoted as ZL(s) in the Gvci(s) expressions of the impedance loaded converters.Table 1
Control-to-output transfer function for current-sink loaded and impedance loaded PWM converters.
G
vci
(
s
)
=
K
v
c
(
1
-
s
/
ω
rhp
)
(
1
+
s
/
ω
esr
)
(
1
+
s
/
ω
p
l
)
(
1
+
s
/
Q
p
ω
n
+
s
2
/
ω
n
2
) with ωesr=1/CRc,  ωn=π/Ts, Qp=1/π(mcD′-0.5), and mc=1+Se/Sn
Current-sink loaded case
Impedance loaded case
Buck converter
K
v
c
=
L
R
i
1
T
s
m
c
D
′
-
0.5
K
v
c
=
L
R
i
1
T
s
m
c
D
′
-
0.5
+
L
/
Z
L
ω
p
l
=
T
s
m
c
D
′
-
0.5
L
C
ω
p
l
=
T
s
m
c
D
′
-
0.5
+
L
/
Z
L
L
C
ω
rhp
=
∞
ω
rhp
=
∞
Boost converter
K
v
c
=
L
R
i
1
T
s
D
′
2
m
c
-
0.5
+
L
/
R
DC
D
′
K
v
c
=
L
R
i
1
T
s
D
′
2
m
c
-
0.5
+
2
L
/
Z
L
D
′
ω
p
l
=
T
s
D
′
2
m
c
-
0.5
+
L
/
R
DC
D
′
L
C
/
D
′
ω
p
l
=
T
s
D
′
2
m
c
-
0.5
+
2
L
/
Z
L
D
′
L
C
/
D
′
ω
rhp
=
R
DC
D
′
2
L
ω
rhp
=
R
DC
D
′
2
L
Buck/boost converter
K
v
c
=
L
R
i
1
T
s
D
′
2
m
c
-
0.5
+
D
L
/
R
DC
D
′
K
v
c
=
L
R
i
1
T
s
D
′
2
m
c
-
0.5
+
1
+
D
L
/
Z
L
D
′
ω
p
l
=
T
s
D
′
2
m
c
-
0.5
+
D
L
/
R
DC
D
′
L
C
/
D
′
ω
p
l
=
T
s
D
′
2
m
c
-
0.5
+
1
+
D
L
/
Z
L
D
′
L
C
/
D
′
ω
rhp
=
R
DC
D
′
2
D
L
ω
rhp
=
R
DC
D
′
2
D
L
Z
L is the load impedance.The structure of the transfer function and the expressions forωesr, Qp, and ωn are the same in both the current-sink loaded and impedance loaded converters. However, the Kvc and ωpl expressions are different, thereby highlighting the distinct power stage dynamics of the current-sink loaded converters. The DC load parameter, RDC=VO/IO, does not appear in the Gvci(s) expressions for the buck converter. This is the unique feature of the buck converter [6], which is not the case for the boost and buck/boost converters. For the boost and buck/boost converters, RDC emerges as a key parameter of power stage transfer functions.


### 3.2. Control Design Procedures

The most important role ofGvci(s) lies in the control design. Referring to Figure 2(b), the loop gain of the current-sink loaded converter becomes(4)TmC=GvcisFvs,where Fv(s) is the voltage feedback compensation. The subscript C in TmC signifies that the converter is current-sink loaded. Based on the Gvci(s) structure, Fv(s) can be designed for the loop gain offering both stability and good performance of the current-sink loaded converter.Figure3 shows the asymptotic plots for |Gvci| and loop gain |TmC|. The |Gvci| plot is constructed with the conditions ωpl≪ωesr≪ωn and 0.5<Qp. The double pole at ωn produces a peaking in |Gvci| by the amount of 20log⁡Qp.Figure 3
Asymptotic plots for|Gvci| and |TmC| with two-pole one-zero voltage feedback compensation.The loop gain plot|TmC| assumes a two-pole one-zero circuit for the voltage feedback compensation (5)Fvs=Kv1+s/ωzcs1+s/ωpc.The compensation pole ωpc is located at the right-half plane (rhp) zero, ωrhp. The compensation zero ωzc is placed after ωpl but before the loop gain crossover frequency, ωcr.The|TmC| shows the desirable -20 dB/dec slope for wide frequency range and crosses the 0 dB line at high frequencies. As shown in Figure 3, the peaking of 20log⁡Qp also occurs in |TmC| at ωn=π/Ts. If the peaking is large, |TmC| could exceed the 0dB line at ωn, thereby destabilizing the converter [7]. Accordingly, the quality factor Qp should be properly controlled to avoid instability due to an excessive peaking. Based on the preceding discussions, the control design procedures are formulated as follows.Current Loop Design
(1)
Determine the CSN gain,Ri, such that iLpeakRi<Vmax where iLpeak is the peak value of the inductor current and Vmax is the maximum allowable input voltage of the PWM block.
(2)
Determine the slope of the compensation ramp,Se, to provide a quality factor in the range 0.3<Qp<1.3 for the double pole at ωn=π/Ts.Voltage Feedback Compensation Design
(1)
Place the compensation poleωpc at the lowest frequency among the rhp zero, esr zero, and half the switching frequency: ωpc=min⁡ωrhpωesr0.5ωs.
(2)
Locate the compensation zeroωzc at the frequencies higher than ωpl but lower than the loop gain crossover frequency: ωpl<ωzc<ωcr.
(3)
Select the0dB crossover frequency of the loop gain and determine the integrator gain Kv required for the selected ωcr. It is recommended that ωcr=(0.3-1.0)ωesr for buck converters and ωcr=(0.1-0.3)ωrhp for boost and buck/boost converters [6]. From Figure 3, the following relationship is formulated: (6)20log⁡Kvc+20log⁡Kvωpl-40log⁡ωzcωpl-20log⁡ωcrωzc=0dB
leading to the design equation for the integrator gainKv(7)KvcKvωplωplωzc2ωzcωcr=1⟹Kv=ωzcωcrKvcωpl.Invariance of Control Design Procedures. The control-to-output transfer functions of the current-sink loaded converters differ from those of the impedance loaded converters. Nonetheless, when the control design procedures established for the current-sink loaded converters are adapted to the impedance loaded converters, the resulting design is practically identical to that of the current-sink loaded converter case. Furthermore, it can be shown that the control parameters are determined independently from the load impedance characteristics. This implies that the proposed control design can be universally adapted to all practical DC-to-DC converters, irrespective of the load impedance characteristics. Thisinvariance of the control design procedures is justified by the following facts:(i)
The criteria for the current loop design are independent of the load impedance and thus remain the same in both the current-sink loaded and impedance loaded cases.(ii)
The design guidelines for the voltage feedback compensation also remain unchanged. In particular, the integrator gainKv is selected as (8)Kv=ωzcωcrKvcωplfor both the cases, whereωzc is the desired position of the compensation zero and ωcr is the target for the crossover frequency. Because the selection of ωzc and ωcr would be the same for the two cases, Kv will be identical if the product of Kvc and ωpl remains invariant in the two cases.(iii)
From theGvci(s) expressions in Table 1, the following relationship can be inferred: (9)Kvcωpl≈1RiC,for buck converter,D′RiC,for boost and buck/boost convertersfor both the current-sink loaded and impedance loaded converters. The condition for the above approximations can readily be seen from Table1. For most practical cases, the relationships of (9) are valid and all the control parameters become the same for the current-sink loaded and impedance loaded converters. Accordingly, the control parameters are all determined independently from the load impedance.


### 3.3. Design and Performance of Current-Sink Loaded Buck Converter

The preceding design procedures are verified using a current-sink loaded current-mode controlled buck converter. The circuit parameters and operational conditions of the buck converter areVS=16 V, VO=4 V, IO=1 A, Ts=20×10-6 s, L=40 μH, Rl=0.1 Ω, C=470 μF, Rc=0.1 Ω, D=0.25, and RDC=1 Ω. The small-signal parameters and operational conditions are ωesr=2π·3.39×103 rad/s, D=0.25, ωs=2π·50×103 rad/s, Vmax=5.0 V, and iLpeak=4.75 A. Based on these data, the control design is executed as follows:(1)
CSN gain:(10)Ri<Vmax⁡iLpeak=5.04.75=1.05Ω⟹Ri=0.67Ω.(2)
Quality factor of double pole:(11)Qp=1π1+Se/SnD′-0.5=1withSn=2.01×105V/s⟹Se=1.84×104V/s.(3)
Compensation pole:ωpc=ωesr=2π·3.39×103 rad/s.(4)
Compensation zero:ωzc=2π·928 rad/s.(5)
Loop gain crossover frequency:ωcr=ωesr=2π·3.39×103 rad/s.(6)
Integrator gain:(12)Kv=ωzcωcrKvcωplwithKvc=9.38,ωpl=2π·54rad/s⟹Kv=2π·9282π·3.39×1039.382π·54=3.91×104.(7)
Voltage feedback compensation:(13)Fvs=3.91×1041+s/2π·928s1+s/2π·3.39×103.(8)
Voltage feedback circuit:R1=10 kΩ(14)⟹R2=92.3kΩ,C2=1.86nF,C3=0.70nF.The performance of the current-sink loaded buck converter is evaluated with both computer simulations and experimental measurements. The small-signal model in Figure2(b) is used for the computer simulations. On the other hand, an HP4194A impedance analyzer is used for experimental measurements. The loop gain TmC is displayed in Figure 4. The |TmC| crosses the 0dB line at ωcr=2π·3.2×103 rad/s with a phase margin of 70∘. Figure 5 shows the output impedance of the current-sink loaded buck converter, referred to as ZoC hereafter. |ZoC| starts from a very small value and increases linearly until it saturates at 20log⁡Rc=20log⁡0.1=-20dB. The small-signal predictions show a close match with the experimental measurements at low and mid frequencies. On the other hand, there are apparent discrepancies at high frequencies. These discrepancies are due to the high-frequency switching noises and parasitic circuit components, which are ignored in the small-signal analysis but affect the experimental data. The discrepancies usually occur at high frequencies, well above the loop gain crossover frequency, and do not interfere with the evaluation of the closed-loop performance of the converter [6]. These discrepancies will be observed, only at high frequencies, in all the forthcoming transfer functions.Figure 4
Loop gain of current-sink loaded buck converter.Figure 5
Output impedance of current-sink loaded buck converter.


## 3.1. Control-to-Output Transfer Function

The vital information to the control design is the control-to-output transfer function,Gvci(s)=v^o/v^con, evaluated under the condition that only the current loop is closed and the connection to the voltage feedback compensation Fv(s) is broken at Point A in Figure 2(b). The knowledge of this transfer function allows us to design both the current loop and voltage feedback circuit for good loop gain characteristics. By applying the Mason’s gain rule to Figure 2(b) with v^s=ı^o=0, the control-to-output transfer function is determined as(2)Gvcis=v^ov^con=Fmv^o/d^1-krFmv^o/d^+RiHesFmı^L/d^.Although the Gvci(s) expression is rather involved, it can be reduced to a simple expression [17, 18] with some practical assumptions on power stage parameters and operational conditions. By following the procedures presented in [17], Gvci(s) is casted into the following third-order approximation: (3)Gvci≈Kvc1+s/ωesr1-s/ωrhp1+s/ωpl1+s/Qpωn+s2/ωn2.The noticeable feature of the transfer function is the quadratic term in the denominator. The quadratic term, originated from the sampling effects of the current mode control [7], introduces a double pole at half the switching frequency; ωn=π/Ts.Table1 shows the parameters appearing in the Gvci(s) expression of the three basic current-sink loaded PWM converters. This table also presents the expressions of Gvci(s) for the impedance loaded PWM converters, in order to contrast the small-signal dynamics of the current-sink loaded and impedance loaded converters. The load impedance is denoted as ZL(s) in the Gvci(s) expressions of the impedance loaded converters.Table 1
Control-to-output transfer function for current-sink loaded and impedance loaded PWM converters.
G
vci
(
s
)
=
K
v
c
(
1
-
s
/
ω
rhp
)
(
1
+
s
/
ω
esr
)
(
1
+
s
/
ω
p
l
)
(
1
+
s
/
Q
p
ω
n
+
s
2
/
ω
n
2
) with ωesr=1/CRc,  ωn=π/Ts, Qp=1/π(mcD′-0.5), and mc=1+Se/Sn
Current-sink loaded case
Impedance loaded case
Buck converter
K
v
c
=
L
R
i
1
T
s
m
c
D
′
-
0.5
K
v
c
=
L
R
i
1
T
s
m
c
D
′
-
0.5
+
L
/
Z
L
ω
p
l
=
T
s
m
c
D
′
-
0.5
L
C
ω
p
l
=
T
s
m
c
D
′
-
0.5
+
L
/
Z
L
L
C
ω
rhp
=
∞
ω
rhp
=
∞
Boost converter
K
v
c
=
L
R
i
1
T
s
D
′
2
m
c
-
0.5
+
L
/
R
DC
D
′
K
v
c
=
L
R
i
1
T
s
D
′
2
m
c
-
0.5
+
2
L
/
Z
L
D
′
ω
p
l
=
T
s
D
′
2
m
c
-
0.5
+
L
/
R
DC
D
′
L
C
/
D
′
ω
p
l
=
T
s
D
′
2
m
c
-
0.5
+
2
L
/
Z
L
D
′
L
C
/
D
′
ω
rhp
=
R
DC
D
′
2
L
ω
rhp
=
R
DC
D
′
2
L
Buck/boost converter
K
v
c
=
L
R
i
1
T
s
D
′
2
m
c
-
0.5
+
D
L
/
R
DC
D
′
K
v
c
=
L
R
i
1
T
s
D
′
2
m
c
-
0.5
+
1
+
D
L
/
Z
L
D
′
ω
p
l
=
T
s
D
′
2
m
c
-
0.5
+
D
L
/
R
DC
D
′
L
C
/
D
′
ω
p
l
=
T
s
D
′
2
m
c
-
0.5
+
1
+
D
L
/
Z
L
D
′
L
C
/
D
′
ω
rhp
=
R
DC
D
′
2
D
L
ω
rhp
=
R
DC
D
′
2
D
L
Z
L is the load impedance.The structure of the transfer function and the expressions forωesr, Qp, and ωn are the same in both the current-sink loaded and impedance loaded converters. However, the Kvc and ωpl expressions are different, thereby highlighting the distinct power stage dynamics of the current-sink loaded converters. The DC load parameter, RDC=VO/IO, does not appear in the Gvci(s) expressions for the buck converter. This is the unique feature of the buck converter [6], which is not the case for the boost and buck/boost converters. For the boost and buck/boost converters, RDC emerges as a key parameter of power stage transfer functions.


## 3.2. Control Design Procedures

The most important role ofGvci(s) lies in the control design. Referring to Figure 2(b), the loop gain of the current-sink loaded converter becomes(4)TmC=GvcisFvs,where Fv(s) is the voltage feedback compensation. The subscript C in TmC signifies that the converter is current-sink loaded. Based on the Gvci(s) structure, Fv(s) can be designed for the loop gain offering both stability and good performance of the current-sink loaded converter.Figure3 shows the asymptotic plots for |Gvci| and loop gain |TmC|. The |Gvci| plot is constructed with the conditions ωpl≪ωesr≪ωn and 0.5<Qp. The double pole at ωn produces a peaking in |Gvci| by the amount of 20log⁡Qp.Figure 3
Asymptotic plots for|Gvci| and |TmC| with two-pole one-zero voltage feedback compensation.The loop gain plot|TmC| assumes a two-pole one-zero circuit for the voltage feedback compensation (5)Fvs=Kv1+s/ωzcs1+s/ωpc.The compensation pole ωpc is located at the right-half plane (rhp) zero, ωrhp. The compensation zero ωzc is placed after ωpl but before the loop gain crossover frequency, ωcr.The|TmC| shows the desirable -20 dB/dec slope for wide frequency range and crosses the 0 dB line at high frequencies. As shown in Figure 3, the peaking of 20log⁡Qp also occurs in |TmC| at ωn=π/Ts. If the peaking is large, |TmC| could exceed the 0dB line at ωn, thereby destabilizing the converter [7]. Accordingly, the quality factor Qp should be properly controlled to avoid instability due to an excessive peaking. Based on the preceding discussions, the control design procedures are formulated as follows.Current Loop Design
(1)
Determine the CSN gain,Ri, such that iLpeakRi<Vmax where iLpeak is the peak value of the inductor current and Vmax is the maximum allowable input voltage of the PWM block.
(2)
Determine the slope of the compensation ramp,Se, to provide a quality factor in the range 0.3<Qp<1.3 for the double pole at ωn=π/Ts.Voltage Feedback Compensation Design
(1)
Place the compensation poleωpc at the lowest frequency among the rhp zero, esr zero, and half the switching frequency: ωpc=min⁡ωrhpωesr0.5ωs.
(2)
Locate the compensation zeroωzc at the frequencies higher than ωpl but lower than the loop gain crossover frequency: ωpl<ωzc<ωcr.
(3)
Select the0dB crossover frequency of the loop gain and determine the integrator gain Kv required for the selected ωcr. It is recommended that ωcr=(0.3-1.0)ωesr for buck converters and ωcr=(0.1-0.3)ωrhp for boost and buck/boost converters [6]. From Figure 3, the following relationship is formulated: (6)20log⁡Kvc+20log⁡Kvωpl-40log⁡ωzcωpl-20log⁡ωcrωzc=0dB
leading to the design equation for the integrator gainKv(7)KvcKvωplωplωzc2ωzcωcr=1⟹Kv=ωzcωcrKvcωpl.Invariance of Control Design Procedures. The control-to-output transfer functions of the current-sink loaded converters differ from those of the impedance loaded converters. Nonetheless, when the control design procedures established for the current-sink loaded converters are adapted to the impedance loaded converters, the resulting design is practically identical to that of the current-sink loaded converter case. Furthermore, it can be shown that the control parameters are determined independently from the load impedance characteristics. This implies that the proposed control design can be universally adapted to all practical DC-to-DC converters, irrespective of the load impedance characteristics. Thisinvariance of the control design procedures is justified by the following facts:(i)
The criteria for the current loop design are independent of the load impedance and thus remain the same in both the current-sink loaded and impedance loaded cases.(ii)
The design guidelines for the voltage feedback compensation also remain unchanged. In particular, the integrator gainKv is selected as (8)Kv=ωzcωcrKvcωplfor both the cases, whereωzc is the desired position of the compensation zero and ωcr is the target for the crossover frequency. Because the selection of ωzc and ωcr would be the same for the two cases, Kv will be identical if the product of Kvc and ωpl remains invariant in the two cases.(iii)
From theGvci(s) expressions in Table 1, the following relationship can be inferred: (9)Kvcωpl≈1RiC,for buck converter,D′RiC,for boost and buck/boost convertersfor both the current-sink loaded and impedance loaded converters. The condition for the above approximations can readily be seen from Table1. For most practical cases, the relationships of (9) are valid and all the control parameters become the same for the current-sink loaded and impedance loaded converters. Accordingly, the control parameters are all determined independently from the load impedance.


## 3.3. Design and Performance of Current-Sink Loaded Buck Converter

The preceding design procedures are verified using a current-sink loaded current-mode controlled buck converter. The circuit parameters and operational conditions of the buck converter areVS=16 V, VO=4 V, IO=1 A, Ts=20×10-6 s, L=40 μH, Rl=0.1 Ω, C=470 μF, Rc=0.1 Ω, D=0.25, and RDC=1 Ω. The small-signal parameters and operational conditions are ωesr=2π·3.39×103 rad/s, D=0.25, ωs=2π·50×103 rad/s, Vmax=5.0 V, and iLpeak=4.75 A. Based on these data, the control design is executed as follows:(1)
CSN gain:(10)Ri<Vmax⁡iLpeak=5.04.75=1.05Ω⟹Ri=0.67Ω.(2)
Quality factor of double pole:(11)Qp=1π1+Se/SnD′-0.5=1withSn=2.01×105V/s⟹Se=1.84×104V/s.(3)
Compensation pole:ωpc=ωesr=2π·3.39×103 rad/s.(4)
Compensation zero:ωzc=2π·928 rad/s.(5)
Loop gain crossover frequency:ωcr=ωesr=2π·3.39×103 rad/s.(6)
Integrator gain:(12)Kv=ωzcωcrKvcωplwithKvc=9.38,ωpl=2π·54rad/s⟹Kv=2π·9282π·3.39×1039.382π·54=3.91×104.(7)
Voltage feedback compensation:(13)Fvs=3.91×1041+s/2π·928s1+s/2π·3.39×103.(8)
Voltage feedback circuit:R1=10 kΩ(14)⟹R2=92.3kΩ,C2=1.86nF,C3=0.70nF.The performance of the current-sink loaded buck converter is evaluated with both computer simulations and experimental measurements. The small-signal model in Figure2(b) is used for the computer simulations. On the other hand, an HP4194A impedance analyzer is used for experimental measurements. The loop gain TmC is displayed in Figure 4. The |TmC| crosses the 0dB line at ωcr=2π·3.2×103 rad/s with a phase margin of 70∘. Figure 5 shows the output impedance of the current-sink loaded buck converter, referred to as ZoC hereafter. |ZoC| starts from a very small value and increases linearly until it saturates at 20log⁡Rc=20log⁡0.1=-20dB. The small-signal predictions show a close match with the experimental measurements at low and mid frequencies. On the other hand, there are apparent discrepancies at high frequencies. These discrepancies are due to the high-frequency switching noises and parasitic circuit components, which are ignored in the small-signal analysis but affect the experimental data. The discrepancies usually occur at high frequencies, well above the loop gain crossover frequency, and do not interfere with the evaluation of the closed-loop performance of the converter [6]. These discrepancies will be observed, only at high frequencies, in all the forthcoming transfer functions.Figure 4
Loop gain of current-sink loaded buck converter.Figure 5
Output impedance of current-sink loaded buck converter.


## 4. Loop Gain Analysis of Loaded Converter

When the current-sink loaded converter is coupled with a real load subsystem, the loop gain will be affected by the load impedanceZL(s). This section investigates the loop gain characteristics of the buck converter coupled with practical load subsystems.


### 4.1. Loop Gain Expression of Loaded Converter

The converter connected to a real load subsystem is now denoted as theloaded converter. Figure 6 is a small-signal functional model of the loaded converter, formulated for the loop gain analysis. The model is created by merging the current-sink loaded converter and the load impedance ZL(s). In Figure 6, the voltage feedback loop is broken for the loop gain evaluation. Therefore, ZoC′ represents the open-loop output impedance of the current-sink loaded converter. The loop gain of the loaded converter TmL is evaluated as (15)TmLs=-v^xv^con=GvcisZLsZLs+ZoC′Fvs=GvcisFvs1+ZoC′/ZLs.By incorporating the well-known relationship among the closed-loop output impedance ZoC, open-loop output impedance ZoC′, and loop gain, TmC=Gvci(s)Fv(s), of the current-sink loaded converter: (16)ZoC=ZoC′1+TmC.Expression (15) is rearranged as (17)TmLs=TmC1+1+TmCZoC/ZLs.The impedance ratio ZoC/ZL(s) is referred to as theequivalent loop gain, Teq(s), in the previous publications [18, 19]. The loop gain expression (17) is now written as (18)TmLs=TmC1+Teqs+TmCTeqsusing the notation of Teq(s)=ZoC/ZL(s). The loop gain will remain unaffected by the load impedance, TmL≈TmC, when the conditions Teq≪1 and |TmCTeq|≪1 are simultaneously met for all frequencies. However, this requirement is not always satisfied in practice and the loop gain characteristics are thus to be altered by ZL(s). Expression (18) will be used to investigate the loop gain of the experimental buck converter connected to various practical load subsystems.Figure 6
Small-signal functional model of loaded converter.


### 4.2. Loop Gain Characteristics with Practical Load Subsystem

Figure7 depicts the load subsystems used for the loop gain analysis. For generality of the analysis, three different types of load subsystems are considered: an inductive load, capacitive load, and converter load. The inductive and capacitive loads are the circuit representations of practical passive loads. The converter load denotes the load subsystem consisting of a filter stage and another buck converter downstream. The converter load is frequently found in distributed power applications [1, 20–22] where cascaded converters and filter stages are employed together for an efficient and reliable power conversion. Details about the converter load and its input impedance were provided in [20, 23].Figure 7
Load subsystems. (a) Inductive load. (b) Capacitive load. (c) Converter load.
(a)
(b)
(c)Figure8 illustrates the load impedances |ZL| of the three load subsystems, in comparison with the output impedance of the current-sink loaded buck converter, |ZoC|. All the load impedances converge to the DC load parameter, RDC=VO/IO=1 Ω, at low frequencies. However, each input impedance shows quite a distinctive pattern at mid and high frequencies, thereby signifying different impacts on the converter loop gain.Figure 8
Output impedance of current-sink loaded buck converter|ZoC| and input impedance of load subsystems |ZL|.The loop gain of the converter with the three load subsystems,TmL(s), and the loop gain of the current-sink loaded converter, TmC, are shown in Figure 9. For each load subsystem, TmL(s) substantially deviates from TmC and reveals very complex behavior. Nonetheless, the pattern of TmL(s) can be accurately predicted from loop gain expression (18).Figure 9
Loop gain characteristics of buck converter with different load subsystems.The results of the loop gain analysis are given in Figure10, which illustrates |TmC|, |Teq|, |TmCTeq|, and |TmL|, all involved with loop gain expression (18). Referring to Figure 10, the loop gain analysis for each load subsystem is performed as follows:(i)
Inductive load: Figure 10(a) illustrates the case with the inductive load. The condition |Teq|≪1 is well-satisfied for all frequencies. However, |TmCTeq|≪1 is not met at low frequencies. For the frequencies below ωb where the conditions |Teq|≪1 and 1≪|TmCTeq| prevail, the loop gain is given by (19)TmLs=TmC1+Teqs+TmCTeqs≈TmC1+TmCTeqs≈TmCTmCTeqs=1Teqs.Thus,|TmL| follows the mirror image of |Teq| reflected on the 0 dB axis, as confirmed in Figure 10(a). On the other hand, for the frequencies beyond ωb where the conditions |Teq|≪1 and |TmCTeq|≪1 are met, the loop gain of the loaded converter trails the loop gain of the current-sink loaded converter; TmL(s)≈TmC. Both the theoretical and experimental loop gains closely follow the predictions of this analysis.(ii)
Capacitive load: The loop gain analysis for the capacitive load is shown in Figure 10(b). For frequencies below the crossover frequency of TmC, ωcr, the conditions 1≪|TmCTeq| and |Teq|≪|TmCTeq| hold true. The loop gain is given by (20)TmLs=TmC1+Teqs+TmCTeqs≈TmCTeqs+TmCTeqs≈TmCTmCTeqs=1Teqsfor the frequencies in the range0<ω<ωcr. For higher frequencies, the conditions 1≪|Teq| and |TmCTeq|≪|Teq| are effective. These conditions simplify loop gain expression to (21)TmLs=TmC1+Teqs+TmCTeqs≈TmCTeqs+TmCTeqs≈TmCTeqsthus indicating the loop gain magnitude is formed by the relationship ofTmL=|TmC|-|Teq|. The loop gain plots well support this analysis.(iii)
Converter load: Figure 10(c) is the case for the converter load. For the frequencies below ωcr where the conditions |Teq|≪|TmCTeq| and 1≪|TmCTeq| are met, the loop gain is given by (22)TmLs=TmC1+Teqs+TmCTeqs≈TmC1+TmCTeqs≈TmCTmCTeqs=1Teqs.The same as the previous two cases,|TmL| traces the mirror image of |Teq| for wide frequency range. For the frequencies beyond ωcr, |TmL| tracks |TmC| with the conditions |Teq|≪|TmCTeq| and 1≪|TmCTeq|. Figure 10(c) reveals a close correspondence to this analysis.Figure 10
Loop gain analysis. (a) Inductive load. (b) Capacitive load. (c) Converter load.
(a)
(b)
(c)The loop gains exhibit distinctive behavior with different load subsystems. With the inductive load,|TmL| follows the mirror image of |Teq| only at low frequencies. In contrast, with the capacitive and converter loads, |TmL| trails the mirror image of |Teq| until the crossover frequency of |TmC|, showing complex yet predictable pattern for a wide frequency range.


## 4.1. Loop Gain Expression of Loaded Converter

The converter connected to a real load subsystem is now denoted as theloaded converter. Figure 6 is a small-signal functional model of the loaded converter, formulated for the loop gain analysis. The model is created by merging the current-sink loaded converter and the load impedance ZL(s). In Figure 6, the voltage feedback loop is broken for the loop gain evaluation. Therefore, ZoC′ represents the open-loop output impedance of the current-sink loaded converter. The loop gain of the loaded converter TmL is evaluated as (15)TmLs=-v^xv^con=GvcisZLsZLs+ZoC′Fvs=GvcisFvs1+ZoC′/ZLs.By incorporating the well-known relationship among the closed-loop output impedance ZoC, open-loop output impedance ZoC′, and loop gain, TmC=Gvci(s)Fv(s), of the current-sink loaded converter: (16)ZoC=ZoC′1+TmC.Expression (15) is rearranged as (17)TmLs=TmC1+1+TmCZoC/ZLs.The impedance ratio ZoC/ZL(s) is referred to as theequivalent loop gain, Teq(s), in the previous publications [18, 19]. The loop gain expression (17) is now written as (18)TmLs=TmC1+Teqs+TmCTeqsusing the notation of Teq(s)=ZoC/ZL(s). The loop gain will remain unaffected by the load impedance, TmL≈TmC, when the conditions Teq≪1 and |TmCTeq|≪1 are simultaneously met for all frequencies. However, this requirement is not always satisfied in practice and the loop gain characteristics are thus to be altered by ZL(s). Expression (18) will be used to investigate the loop gain of the experimental buck converter connected to various practical load subsystems.Figure 6
Small-signal functional model of loaded converter.


## 4.2. Loop Gain Characteristics with Practical Load Subsystem

Figure7 depicts the load subsystems used for the loop gain analysis. For generality of the analysis, three different types of load subsystems are considered: an inductive load, capacitive load, and converter load. The inductive and capacitive loads are the circuit representations of practical passive loads. The converter load denotes the load subsystem consisting of a filter stage and another buck converter downstream. The converter load is frequently found in distributed power applications [1, 20–22] where cascaded converters and filter stages are employed together for an efficient and reliable power conversion. Details about the converter load and its input impedance were provided in [20, 23].Figure 7
Load subsystems. (a) Inductive load. (b) Capacitive load. (c) Converter load.
(a)
(b)
(c)Figure8 illustrates the load impedances |ZL| of the three load subsystems, in comparison with the output impedance of the current-sink loaded buck converter, |ZoC|. All the load impedances converge to the DC load parameter, RDC=VO/IO=1 Ω, at low frequencies. However, each input impedance shows quite a distinctive pattern at mid and high frequencies, thereby signifying different impacts on the converter loop gain.Figure 8
Output impedance of current-sink loaded buck converter|ZoC| and input impedance of load subsystems |ZL|.The loop gain of the converter with the three load subsystems,TmL(s), and the loop gain of the current-sink loaded converter, TmC, are shown in Figure 9. For each load subsystem, TmL(s) substantially deviates from TmC and reveals very complex behavior. Nonetheless, the pattern of TmL(s) can be accurately predicted from loop gain expression (18).Figure 9
Loop gain characteristics of buck converter with different load subsystems.The results of the loop gain analysis are given in Figure10, which illustrates |TmC|, |Teq|, |TmCTeq|, and |TmL|, all involved with loop gain expression (18). Referring to Figure 10, the loop gain analysis for each load subsystem is performed as follows:(i)
Inductive load: Figure 10(a) illustrates the case with the inductive load. The condition |Teq|≪1 is well-satisfied for all frequencies. However, |TmCTeq|≪1 is not met at low frequencies. For the frequencies below ωb where the conditions |Teq|≪1 and 1≪|TmCTeq| prevail, the loop gain is given by (19)TmLs=TmC1+Teqs+TmCTeqs≈TmC1+TmCTeqs≈TmCTmCTeqs=1Teqs.Thus,|TmL| follows the mirror image of |Teq| reflected on the 0 dB axis, as confirmed in Figure 10(a). On the other hand, for the frequencies beyond ωb where the conditions |Teq|≪1 and |TmCTeq|≪1 are met, the loop gain of the loaded converter trails the loop gain of the current-sink loaded converter; TmL(s)≈TmC. Both the theoretical and experimental loop gains closely follow the predictions of this analysis.(ii)
Capacitive load: The loop gain analysis for the capacitive load is shown in Figure 10(b). For frequencies below the crossover frequency of TmC, ωcr, the conditions 1≪|TmCTeq| and |Teq|≪|TmCTeq| hold true. The loop gain is given by (20)TmLs=TmC1+Teqs+TmCTeqs≈TmCTeqs+TmCTeqs≈TmCTmCTeqs=1Teqsfor the frequencies in the range0<ω<ωcr. For higher frequencies, the conditions 1≪|Teq| and |TmCTeq|≪|Teq| are effective. These conditions simplify loop gain expression to (21)TmLs=TmC1+Teqs+TmCTeqs≈TmCTeqs+TmCTeqs≈TmCTeqsthus indicating the loop gain magnitude is formed by the relationship ofTmL=|TmC|-|Teq|. The loop gain plots well support this analysis.(iii)
Converter load: Figure 10(c) is the case for the converter load. For the frequencies below ωcr where the conditions |Teq|≪|TmCTeq| and 1≪|TmCTeq| are met, the loop gain is given by (22)TmLs=TmC1+Teqs+TmCTeqs≈TmC1+TmCTeqs≈TmCTmCTeqs=1Teqs.The same as the previous two cases,|TmL| traces the mirror image of |Teq| for wide frequency range. For the frequencies beyond ωcr, |TmL| tracks |TmC| with the conditions |Teq|≪|TmCTeq| and 1≪|TmCTeq|. Figure 10(c) reveals a close correspondence to this analysis.Figure 10
Loop gain analysis. (a) Inductive load. (b) Capacitive load. (c) Converter load.
(a)
(b)
(c)The loop gains exhibit distinctive behavior with different load subsystems. With the inductive load,|TmL| follows the mirror image of |Teq| only at low frequencies. In contrast, with the capacitive and converter loads, |TmL| trails the mirror image of |Teq| until the crossover frequency of |TmC|, showing complex yet predictable pattern for a wide frequency range.


## 5. Conclusions

Traditionally, the design and analysis of DC-to-DC converters have been performed based on the assumption that the converters are feeding a resistive load. However, the load of a DC-to-DC converter is commonly a combination of circuit components, electrical devices, and even other converters downstream. The load is characterized by its nonresistive impedance. Furthermore, the load impedance characteristics are unknown or undefined at the design stage of the DC-to-DC converter.This paper presented the control design method, which relies on only the DC power requirement without any prior presumption on the load impedance. Based on the small-signal analysis, the control design procedures are formulated to achieve good loop gain characteristics. The proposed control design can be generally adapted to all the PWM converters regardless of the impedance characteristics of their actual load. Theoretical and practical details about the control design are all demonstrated using a current-mode controlled buck converter.The current paper also presented the loop gain analysis of the current-mode controlled buck converter, which is designed based on only the DC power requirement and later combined with various practical load subsystems. This paper established a general graphical method to predict and interpret the loop gain of the converter combined with an inductive, capacitive, or converter load. The inductive load revealed that the loop gain follows the mirror image of the equivalent loop gain only at low frequencies. In contrast, with the capacitive and converter loads, the loop gain trails the mirror image of the equivalent loop gain until the crossover frequency of the loop gain of the current-sink loaded converter.



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*Source: 426315-2015-07-15.xml*