# A Novel Programmable CMOS Fuzzifiers Using Voltage-to-Current Converter Circuit

Authors: K. P. Abdulla; Mohammad Fazle Azeem
Journal: Advances in Fuzzy Systems
 (2012)

---

## Abstract

This paper presents a new voltage-input, current-output programmable membership function generator circuit (MFC) using CMOS technology. It employs a voltage-to-current converter to provide the required current bias for the membership function circuit. The proposed MFC has several advantageous features. This MFC can be reconfigured to perform triangular, trapezoidal, S-shape, Z-Shape, and Gaussian membership forms. This membership function can be programmed in terms of its width, slope, and its center locations in its universe of discourses. The easily adjustable characteristics of the proposed circuit and its accuracy make it suitable for embedded system and industrial control applications. The proposed MFC is designed using the spice software, and simulation results are obtained.


---

## Body

## 1. Introduction

The concept of Fuzzy Logic was introduced by Zadeh nearly 40 years ago [1–6], and since then numerous applications of this theory has been implemented in various engineering and nonengineering fields. The numerous successful applications of fuzzy-control have sparked a flurry of activities in the analysis and design of fuzzy-control systems. Fuzzy-control theories have some salient features and distinguishing merits. The different fields in which fuzzy logic has been applied include signal processing, computer vision, automatic control, consumer electronics, household appliances, decision making analysis, and so on. The number of applications using fuzzy logic techniques to solve control problems has increased considerably. This rapid growth of fuzzy logic has motivated the researchers to go for efficient realization of fuzzy inference systems (FIS) [7, 8].Fuzzy inference system can be implemented using software or hardware. Software implementation of FIS is useful when an application can be moduled to simulate, and calculate in advance, its multidimensional response characteristic. It provides flexibility as they usually support fuzzy systems with an arbitrary number of rules without any limitation concerning the number, type of membership, and range of inference mechanism. On the other hand, it works on a computer or a processor platform, and it has a drawback of being very slow [9, 10]. Hence it is not used for real-time application. A study of software and hardware implementation of FIS is described in [11], and it demonstrates the advantages of hardware design over software design in terms of speed and computational requirements. Therefore hardware realization is preferred for real-time applications, and various hardware techniques have been proposed [12].The digital and analog techniques constitute the two existent approaches for the hardware realization of fuzzy systems. There are different techniques reported in the literature for the digital design of fuzzy systems. Among them, the most versatile methods are those which use field programmable gate arrays (FPGA) as reported by Maldonado et al. [13] and by Montiel et al. [14]. Even though the digital approach is superior in terms of ease of design, the analog fuzzy logic approach is proposed to get maximum efficiency in terms of silicon area, power consumption, and delay time or processing speed [15–19]. Thus it leads to low-cost and high-speed implementation compared to the digital counterpart. A direct interface of the controller to input and output continuous variables is also possible, thus making the circuitry for analog-to-digital conversion unnecessary and inducing delay in the control loop too.Fuzzification is an important concept used in the fuzzy logic theory. It is the process of converting a crisp value into a fuzzy value. The conversion is actually the incorporation of fuzziness, uncertainty, vagueness, or ambiguity in the crisp quantity. In the real world, the quantities which look crisp actually carry a considerable amount of uncertainty or vagueness. This uncertainty, vagueness, or imprecision in a fuzzy quantity can be represented by a membership function. Membership function is the key element in fuzzy signal processing. This provides a nonlinear relation that measures the compatibility of an object with the concept represented by a fuzzy set. Fuzzy set provides a convenient point of departure from the construction of a conceptual framework used in ordinary sets and have proved to have a much wider scope of applicability, particularly in the fields of pattern classification, information processing, statistical process control, and so forth. The researchers have developed various membership functions for the fuzzy processors using different techniques like digital methods [20, 21], mixed-mode signal [22, 23], and current-mode methods [24, 25]. The design of a membership function depends on the particular application to which the fuzzy processor is being applied.The fuzzifier circuit resented in this paper is a suitable circuit to analyze and tune the nonlinear parameters of membership functions [26]. The important property of this fuzzifier is that by changing the various parameters, a membership function with different shape and slope can be easily generated. The fuzzifier designed here is a programmable circuit. This scheme is expected to find application in neuro-fuzzy processors where adaptation of the membership function parameters is required [27]. The result is a faster, cheaper, and higher controllable design compared to conventional fuzzification techniques. The proposed MFC has been laid out using full-custom techniques to provide standard cell. And it results in a CMOS-MFC standard cell, which could be then used as a standard component for implementing a number of required MFC in integrated circuit [28, 29]. This structure exploits the operation of the MOS differential amplifier as a current switch with soft transition region.The major contributions of the proposed work can be summarized as follows: (1) firstly, the proposed design use a voltage-input, current-output interface which is very useful for the real world sensor interface with current-mode fuzzy-control systems, (2) secondly, the application of the analog voltage-to-current converter makes it easy to tune the nonlinear parameters of the MFC such as width and slope, and (3) finally, the low-power CMOS realization ensures a faster, cheaper, and highly controllable design for embedded system and industrial control applications.This paper is organized into four sections: Section2 describes the architecture of the proposed fuzzy membership function circuit and Section 3 explains the circuit level discretion for the same. It is followed by simulation results graphically described in Section 4, and conclusions are discussed in Section 5.


## 2. The Proposed Circuit

Fuzzifying is the first step in a fuzzy system. The input data of a fuzzy logic controller are usually crisp values acquired from sensor measurement. Therefore, fuzzification interface is needed to calculate the belongingness (membership) of the observed inputs to the defined linguistic terms in the preconditions of the fuzzy rules. This is carried out through the fuzzy membership function circuits (MFCs), which performs a nonlinear transform from their inputs to their outputs. MFCs are provided with the input signal from the external environment, normally in the voltage mode. On the other hand, the processing steps following the fuzzification stage performs better in the current mode.The block diagram of an MFC is as shown in the Figure1.Figure 1
Block diagram of an MFC.The MFC in Figure1 is built of a coupled differential amplifier pair which has two differential pairs and a PMOS current mirror for replicating the drain currents to the output. The two reference voltages, Vref1 and Vref2, where Vref1<Vref2, define the membership function. Depending on the relative values of input voltage Vin and the reference voltages Vref1 and Vref2, the circuit operates in one of the five regions (I–V) as shown in Figure 2.Figure 2
Trapezoidal shape of membership function.Basically, a fuzzy term can be defined by a membership function of trapezoidal shape as shown in Figure2. The core of the function corresponds to the region which has full membership (μ=1), the ascending and descending boundaries are the regions with partial membership (0<μ<1), and support is the sum of core and the boundaries in which μ>0. Further we assume that the current IB1 and IB2 in DP1 and DP2 are ideal and equivalent, the input devices in each differential pairs are symmetric, and the half widths of the transfer regions of DP1 and DP2 are V1 and V2, if W/L is equal for all MOSFETs used, therefore V1=V2=2Vov, where Vov is the overdrive voltage.The MFC shown in Figure1 has four control signals—two voltage signals (Vref1 and Vref2) and two current signals (IB1 and IB2)—for the width and slope tunability, respectively. In the proposed design of MFC, we have used an MOS voltage-to-current converter, which provides the bias current to the differential pairs DP1 and DP2. This voltage to current converter has a good linearity and very high sensitivity. The voltage-to-current converter was designed and simulated to study its characteristics and justify its usefulness in the design of tunable MFC circuits.


## 3. Circuit Level Description

As it can be seen from the Figure1, the two important components of the proposed membership function circuit are the current mirrors and the differential amplifiers. This section explains the circuit level design and analysis of the basic analog structures used in the design of the proposed membership function circuit.


### 3.1. Current Mirrors

The block diagram of a typical current mirror is as shown in Figure3. For an ideal condition, Iout=(BIin),Rin≫0, and Rout≫∞, where Rin and Rout are the input and output impedances, respectively.Figure 3
Block diagram of a current mirror.A current mirror is actually a combination of a diode-connected transistor followed by a single-transistor amplifier. The first one converts the input current into voltage, whereas the latter one converts the voltage into current. The current ratio will be quite accurate, simply because the nonlinearity of the diode-connected MOS transistor (MOST) is compensated by the non-linearity of the amplifying MOST. If the ratio of theirW/L’s is B, then the current ratio is also B. Indeed, these MOSTs have the same VGS, that is, ground-to-source voltage and hence VGS-VT. This ratio is the current gain.


#### 3.1.1. NMOS Current Mirror

In the circuit shown in Figure4, MOSFETs M1 and M2 form a current mirror and gate source voltages of both the MOSFETs are same because they are shorted. In MOSFET M1, the drain is shorted to its gate, thereby forcing it to operate in the saturation mode with
(1)Iin=12Kn′(WL)1(VGS1-VT)2,
where channel length modulation is neglected. Now consider the MOSFET M2. It is also working in the saturation mode, therefore the expression for its drain current (of the threshold voltages of M1 and M2 are equal) is given by
(2)Iout=12Kn′(WL)2(VGS2-VT)2.
Since the gates of M1 and M2 are shorted, VGS1=VGS2, therefore,
(3)IinIout=(W/L)1(W/L)2.
Let (W/L)1=(W/L)2, this implies that Iin=Iout.Figure 4
NMOS current mirror.Now if we would like to replicate more current of same value, then a current replication circuit is used by increasing the number of MOSFETs as shown in the Figure5.Figure 5
NMOS current replication circuit.


#### 3.1.2. Current-Routing and Voltage-Routing

Consider the current mirror shown in Figure6, which has one input and two outputs. At first, assume that Rs1=Rs2=0. Also, assume that the input current is generated by a circuit with desirable properties.Figure 6
NMOS current mirror with two outputs and supply resistances.Since the gate source voltage of M1 must be routed to M2 and M3 here, this case is referred to as an example of thevoltage routingof bias signals. An advantage of this approach is that by routing only two nodes (the gate and the source of M1) around the IC, any number of output currents can be produced.Unfortunately, voltage routing has two disadvantages. First, the input and output transistors in the current mirror may be separated by distances that are large compared to the size of the IC, increasing the potential mismatches. In particular, the threshold voltage typically displays considerable gradient with distance across a wafer. Therefore, when the devices are physically separated by large distances, large current mismatch can result from biasing current sources sharing the same gate-source bias, especially when the overdrive is small. The second disadvantage of voltage routing is that the output currents are sensitive to variations in the supply resistancesRs1 and Rs2.To overcome these problems, the circuit in Figure6 can be built so that M1–M3 are close together physically, and the current outputs Iout1 and Iout2 are routed as required on the IC. This case is referred to as an example of the current routing of bias signals as shown in Figure 7. Current routing reduces the problems with mismatch and supply resistance by reducing the distances between the input and output transistors in the current mirror compared to voltage routing. One disadvantage of current routing is that it requires one node to be routed for each bias signal. Therefore, when the number of bias outputs is large, the die area required for the “interconnect” to distribute the bias currents can be much larger than that required for voltage routing.Figure 7
Bias distribution circuit using both current-routing and voltage-routing.In practice, many ICs use a combination of current and voltage-routing techniques. If the current-routing bus in Figure6 travels over a large distance, the parasitic capacitances on the drains of M2 and M3 may be large. In ICs using both current and voltage routing, currents are routed globally and voltages locally, where the difference between global and local routing depends on distance. When the distance is large enough to significantly worsen mismatch or supply resistance effects, the routing is global. Otherwise, it is local.An effective combination of these bias distribution techniques is to divide an IC into blocks, where bias currents are routed between blocks and bias voltages within the blocks. In this work, for the effective routing of the bias current, both current and voltage routings are used.


### 3.2. Differential Pair

MOS differential pair is widely used as an input stage in operational amplifiers and in many other types of circuits as well. This venerable circuit has a relatively large response to a change in the difference between its two input voltages, but a relatively small response to a change in the average value of its two input voltages. The usefulness of the differential pair stems from two key properties. First, cascades of differential pairs can be directly connected to one another without inter-stage-coupling capacitors. Second, the differential pair is primarily sensitive to the difference between two input voltages, allowing a high degree of rejection of signals common to both inputs.Figure8 shows an MOS differential pair. Here M1 and M2 are two matched transistors, biased by a common current source Iapplied, with identical drain resistance Rd. Vg1 and Vg2 are two input voltages applied at the gates G1 and G2.Figure 8
Differential pair with two inputsVg1 and Vg2.The drain currents of the MOSFET are given by the following relation:(4)id1=I2+(IVov)(Vid2)1-(Vid/2Vov)2,id1=I2-(IVov)(Vid2)1-(Vid/2Vov)2.
When Vid=2Vov,   id1=I and id2=0. When Vid=-2Vov,id2=I and id1=0.


#### 3.2.1. Differential Pair with MOS Loads

The load of a differential pair need not be implemented by linear resistors. Differential pair can employ diode-connected or current-source loads. The diode-connected loads consume voltage headroom, thus creating a trade-off between output voltage swing, output voltage gain, and input common mode range. In order to alleviate the above difficulty, part of the current of the transistors can be provided by PMOS current sources. Here the idea is to lower thegm of the load devices by reducing their current rather than their aspect ratio. For the proposed design, both the differential pairs shown in Figure 1 are connected with diode-connected and current-source loads to increase the gain as shown in Figure 9.Figure 9
Differential pair with current source in addition to diode-connected load.Figure9 shows a differential pair with both diode-connected as well as current-source loads. This configuration can be used to increase the gain. For example, if M3 and M6 carry 80% of the drain current of M1 and M2, then the current through M4 and M5 is reduced by a factor of five. For a given |VGSP-VTHP|, this translates to a factor of five reductions in the transconductance of M4 and M5, because the aspect ratio of the device can be lowered by the same factor. Thus, the differential gain is now approximately five times that of the case with no PMOS current source.


### 3.3. Voltage to Current Converter

As current-mode circuits are restricted to single fan-out, multiple current mirrors are required to share fan-out signals among several operational blocks. Voltage-mode inputs are thus preferable for fuzzy hardware systems, since they must be distributed to the membership function circuits of many rule blocks. Current-mode signals are appreciated afterwards, because of the advantages provided by current-mode processing. Tunable voltage-input current-mode membership function circuits are consequently useful building blocks to proceed fuzzification with current-mode analog hardware. For this reason, a voltage-to-current (V-to-I) converter is used to provide the bias currents in the proposed fuzzifier circuit. The schematic for the proposed voltage-to-current converter is as shown in the Figure 10.Figure 10
Voltage-to-current converter.In the above circuit, the MOS transistors M7, M8, and M9 are operated in the triode region, and a negative feedback loop is established by the MOS transistor M10. There the current through the MOS transistor M10 isB times up-scaled current through the MOS transistor M11, which delivers the output current Iout, proportional to the input voltage ratio as given by the relation:
(5)Iout=BVb3-Vb2Vb1-Vb2Iin,
where B is the ratio of W/L’s of the MOS transistors M10 and M11, and effective Iin is the current through the MOS transistor M7. From the above expression, it is clear that the relationship between the input voltage Vb3 and the output current Iout is linear and can be used as a voltage-to-current converter. In the proposed membership function circuit this voltage-to-current converter is used to tune the width and slope of the Gaussian-shaped membership function.


## 3.1. Current Mirrors

The block diagram of a typical current mirror is as shown in Figure3. For an ideal condition, Iout=(BIin),Rin≫0, and Rout≫∞, where Rin and Rout are the input and output impedances, respectively.Figure 3
Block diagram of a current mirror.A current mirror is actually a combination of a diode-connected transistor followed by a single-transistor amplifier. The first one converts the input current into voltage, whereas the latter one converts the voltage into current. The current ratio will be quite accurate, simply because the nonlinearity of the diode-connected MOS transistor (MOST) is compensated by the non-linearity of the amplifying MOST. If the ratio of theirW/L’s is B, then the current ratio is also B. Indeed, these MOSTs have the same VGS, that is, ground-to-source voltage and hence VGS-VT. This ratio is the current gain.


### 3.1.1. NMOS Current Mirror

In the circuit shown in Figure4, MOSFETs M1 and M2 form a current mirror and gate source voltages of both the MOSFETs are same because they are shorted. In MOSFET M1, the drain is shorted to its gate, thereby forcing it to operate in the saturation mode with
(1)Iin=12Kn′(WL)1(VGS1-VT)2,
where channel length modulation is neglected. Now consider the MOSFET M2. It is also working in the saturation mode, therefore the expression for its drain current (of the threshold voltages of M1 and M2 are equal) is given by
(2)Iout=12Kn′(WL)2(VGS2-VT)2.
Since the gates of M1 and M2 are shorted, VGS1=VGS2, therefore,
(3)IinIout=(W/L)1(W/L)2.
Let (W/L)1=(W/L)2, this implies that Iin=Iout.Figure 4
NMOS current mirror.Now if we would like to replicate more current of same value, then a current replication circuit is used by increasing the number of MOSFETs as shown in the Figure5.Figure 5
NMOS current replication circuit.


### 3.1.2. Current-Routing and Voltage-Routing

Consider the current mirror shown in Figure6, which has one input and two outputs. At first, assume that Rs1=Rs2=0. Also, assume that the input current is generated by a circuit with desirable properties.Figure 6
NMOS current mirror with two outputs and supply resistances.Since the gate source voltage of M1 must be routed to M2 and M3 here, this case is referred to as an example of thevoltage routingof bias signals. An advantage of this approach is that by routing only two nodes (the gate and the source of M1) around the IC, any number of output currents can be produced.Unfortunately, voltage routing has two disadvantages. First, the input and output transistors in the current mirror may be separated by distances that are large compared to the size of the IC, increasing the potential mismatches. In particular, the threshold voltage typically displays considerable gradient with distance across a wafer. Therefore, when the devices are physically separated by large distances, large current mismatch can result from biasing current sources sharing the same gate-source bias, especially when the overdrive is small. The second disadvantage of voltage routing is that the output currents are sensitive to variations in the supply resistancesRs1 and Rs2.To overcome these problems, the circuit in Figure6 can be built so that M1–M3 are close together physically, and the current outputs Iout1 and Iout2 are routed as required on the IC. This case is referred to as an example of the current routing of bias signals as shown in Figure 7. Current routing reduces the problems with mismatch and supply resistance by reducing the distances between the input and output transistors in the current mirror compared to voltage routing. One disadvantage of current routing is that it requires one node to be routed for each bias signal. Therefore, when the number of bias outputs is large, the die area required for the “interconnect” to distribute the bias currents can be much larger than that required for voltage routing.Figure 7
Bias distribution circuit using both current-routing and voltage-routing.In practice, many ICs use a combination of current and voltage-routing techniques. If the current-routing bus in Figure6 travels over a large distance, the parasitic capacitances on the drains of M2 and M3 may be large. In ICs using both current and voltage routing, currents are routed globally and voltages locally, where the difference between global and local routing depends on distance. When the distance is large enough to significantly worsen mismatch or supply resistance effects, the routing is global. Otherwise, it is local.An effective combination of these bias distribution techniques is to divide an IC into blocks, where bias currents are routed between blocks and bias voltages within the blocks. In this work, for the effective routing of the bias current, both current and voltage routings are used.


## 3.1.1. NMOS Current Mirror

In the circuit shown in Figure4, MOSFETs M1 and M2 form a current mirror and gate source voltages of both the MOSFETs are same because they are shorted. In MOSFET M1, the drain is shorted to its gate, thereby forcing it to operate in the saturation mode with
(1)Iin=12Kn′(WL)1(VGS1-VT)2,
where channel length modulation is neglected. Now consider the MOSFET M2. It is also working in the saturation mode, therefore the expression for its drain current (of the threshold voltages of M1 and M2 are equal) is given by
(2)Iout=12Kn′(WL)2(VGS2-VT)2.
Since the gates of M1 and M2 are shorted, VGS1=VGS2, therefore,
(3)IinIout=(W/L)1(W/L)2.
Let (W/L)1=(W/L)2, this implies that Iin=Iout.Figure 4
NMOS current mirror.Now if we would like to replicate more current of same value, then a current replication circuit is used by increasing the number of MOSFETs as shown in the Figure5.Figure 5
NMOS current replication circuit.


## 3.1.2. Current-Routing and Voltage-Routing

Consider the current mirror shown in Figure6, which has one input and two outputs. At first, assume that Rs1=Rs2=0. Also, assume that the input current is generated by a circuit with desirable properties.Figure 6
NMOS current mirror with two outputs and supply resistances.Since the gate source voltage of M1 must be routed to M2 and M3 here, this case is referred to as an example of thevoltage routingof bias signals. An advantage of this approach is that by routing only two nodes (the gate and the source of M1) around the IC, any number of output currents can be produced.Unfortunately, voltage routing has two disadvantages. First, the input and output transistors in the current mirror may be separated by distances that are large compared to the size of the IC, increasing the potential mismatches. In particular, the threshold voltage typically displays considerable gradient with distance across a wafer. Therefore, when the devices are physically separated by large distances, large current mismatch can result from biasing current sources sharing the same gate-source bias, especially when the overdrive is small. The second disadvantage of voltage routing is that the output currents are sensitive to variations in the supply resistancesRs1 and Rs2.To overcome these problems, the circuit in Figure6 can be built so that M1–M3 are close together physically, and the current outputs Iout1 and Iout2 are routed as required on the IC. This case is referred to as an example of the current routing of bias signals as shown in Figure 7. Current routing reduces the problems with mismatch and supply resistance by reducing the distances between the input and output transistors in the current mirror compared to voltage routing. One disadvantage of current routing is that it requires one node to be routed for each bias signal. Therefore, when the number of bias outputs is large, the die area required for the “interconnect” to distribute the bias currents can be much larger than that required for voltage routing.Figure 7
Bias distribution circuit using both current-routing and voltage-routing.In practice, many ICs use a combination of current and voltage-routing techniques. If the current-routing bus in Figure6 travels over a large distance, the parasitic capacitances on the drains of M2 and M3 may be large. In ICs using both current and voltage routing, currents are routed globally and voltages locally, where the difference between global and local routing depends on distance. When the distance is large enough to significantly worsen mismatch or supply resistance effects, the routing is global. Otherwise, it is local.An effective combination of these bias distribution techniques is to divide an IC into blocks, where bias currents are routed between blocks and bias voltages within the blocks. In this work, for the effective routing of the bias current, both current and voltage routings are used.


## 3.2. Differential Pair

MOS differential pair is widely used as an input stage in operational amplifiers and in many other types of circuits as well. This venerable circuit has a relatively large response to a change in the difference between its two input voltages, but a relatively small response to a change in the average value of its two input voltages. The usefulness of the differential pair stems from two key properties. First, cascades of differential pairs can be directly connected to one another without inter-stage-coupling capacitors. Second, the differential pair is primarily sensitive to the difference between two input voltages, allowing a high degree of rejection of signals common to both inputs.Figure8 shows an MOS differential pair. Here M1 and M2 are two matched transistors, biased by a common current source Iapplied, with identical drain resistance Rd. Vg1 and Vg2 are two input voltages applied at the gates G1 and G2.Figure 8
Differential pair with two inputsVg1 and Vg2.The drain currents of the MOSFET are given by the following relation:(4)id1=I2+(IVov)(Vid2)1-(Vid/2Vov)2,id1=I2-(IVov)(Vid2)1-(Vid/2Vov)2.
When Vid=2Vov,   id1=I and id2=0. When Vid=-2Vov,id2=I and id1=0.


### 3.2.1. Differential Pair with MOS Loads

The load of a differential pair need not be implemented by linear resistors. Differential pair can employ diode-connected or current-source loads. The diode-connected loads consume voltage headroom, thus creating a trade-off between output voltage swing, output voltage gain, and input common mode range. In order to alleviate the above difficulty, part of the current of the transistors can be provided by PMOS current sources. Here the idea is to lower thegm of the load devices by reducing their current rather than their aspect ratio. For the proposed design, both the differential pairs shown in Figure 1 are connected with diode-connected and current-source loads to increase the gain as shown in Figure 9.Figure 9
Differential pair with current source in addition to diode-connected load.Figure9 shows a differential pair with both diode-connected as well as current-source loads. This configuration can be used to increase the gain. For example, if M3 and M6 carry 80% of the drain current of M1 and M2, then the current through M4 and M5 is reduced by a factor of five. For a given |VGSP-VTHP|, this translates to a factor of five reductions in the transconductance of M4 and M5, because the aspect ratio of the device can be lowered by the same factor. Thus, the differential gain is now approximately five times that of the case with no PMOS current source.


## 3.2.1. Differential Pair with MOS Loads

The load of a differential pair need not be implemented by linear resistors. Differential pair can employ diode-connected or current-source loads. The diode-connected loads consume voltage headroom, thus creating a trade-off between output voltage swing, output voltage gain, and input common mode range. In order to alleviate the above difficulty, part of the current of the transistors can be provided by PMOS current sources. Here the idea is to lower thegm of the load devices by reducing their current rather than their aspect ratio. For the proposed design, both the differential pairs shown in Figure 1 are connected with diode-connected and current-source loads to increase the gain as shown in Figure 9.Figure 9
Differential pair with current source in addition to diode-connected load.Figure9 shows a differential pair with both diode-connected as well as current-source loads. This configuration can be used to increase the gain. For example, if M3 and M6 carry 80% of the drain current of M1 and M2, then the current through M4 and M5 is reduced by a factor of five. For a given |VGSP-VTHP|, this translates to a factor of five reductions in the transconductance of M4 and M5, because the aspect ratio of the device can be lowered by the same factor. Thus, the differential gain is now approximately five times that of the case with no PMOS current source.


## 3.3. Voltage to Current Converter

As current-mode circuits are restricted to single fan-out, multiple current mirrors are required to share fan-out signals among several operational blocks. Voltage-mode inputs are thus preferable for fuzzy hardware systems, since they must be distributed to the membership function circuits of many rule blocks. Current-mode signals are appreciated afterwards, because of the advantages provided by current-mode processing. Tunable voltage-input current-mode membership function circuits are consequently useful building blocks to proceed fuzzification with current-mode analog hardware. For this reason, a voltage-to-current (V-to-I) converter is used to provide the bias currents in the proposed fuzzifier circuit. The schematic for the proposed voltage-to-current converter is as shown in the Figure 10.Figure 10
Voltage-to-current converter.In the above circuit, the MOS transistors M7, M8, and M9 are operated in the triode region, and a negative feedback loop is established by the MOS transistor M10. There the current through the MOS transistor M10 isB times up-scaled current through the MOS transistor M11, which delivers the output current Iout, proportional to the input voltage ratio as given by the relation:
(5)Iout=BVb3-Vb2Vb1-Vb2Iin,
where B is the ratio of W/L’s of the MOS transistors M10 and M11, and effective Iin is the current through the MOS transistor M7. From the above expression, it is clear that the relationship between the input voltage Vb3 and the output current Iout is linear and can be used as a voltage-to-current converter. In the proposed membership function circuit this voltage-to-current converter is used to tune the width and slope of the Gaussian-shaped membership function.


## 4. Simulation Results

All the above discussed circuits are designed and simulated using spice simulation software to study their characteristics and verify the working. This section provides the results of simulation for the above-discussed circuits and also a brief note on the obtained result.The first result presented is the output for the proposed voltage-to-current converter as shown in Figure11. Here we can observe that the V-I characteristics for the proposed circuit is linear and thus can be used as a voltage-controlled current source that can be used to supply the bias current for the membership function circuit. The required bias current can be set by varying the control voltage Vb3 (Vb1 and Vb2 are fixed conveniently observing (5)).Figure 11
Voltage to Current converter output withVb1=1.5 V, Vb2=0.5 V, 0.75 V, and 1 V, and Vb3 sweep voltage from 1 V to 1.5 V in steps of 50 mV.Thus by varying the voltageVb3 we can control the width and the slope of the Gaussian-shaped membership function as shown in Figures 12, 13 and 14. For all the three simulation, Vb1=1.5 V and Vb2=1 V.Figure 12
Gaussian-shaped membership function,Vb3=1.65 V.Figure 13
Gaussian-shaped membership function,Vb3=1.45 V.Figure 14
Gaussian-shaped membership function,Vb3=1.25 V.Figures15 and 16 shows the simulation results for the width and position tunability through left side and right side, respectively. For the left side tunability the voltage Vlow is varied from 3.75 V to 4.25 V with 0.1 V increment. For right side tunability the voltage Vhigh is varied from 5.75 V to 6.25 V with 0.1 V increment.Figure 15
Width and position tunability through left side.Figure 16
Width and position tunability through right side.From the above simulation results for the membership function circuit, it is clear that we have got three control voltages for the tuning of the membership function:Vb3, Vlow and Vhigh. These voltages can be used to tune the slope, width and position of any particular membership function.


## 5. Conclusions

A new programmable CMOS fuzzifier circuit has been presented. The proposed membership function has the following advantages: proposed MFC is capable of generating different membership functions of different shapes—like Gaussian, S-shape, Z-shape, and trapezoidal—from a single circuit therefore it require lesser hardware. The proposed MFC exhibits a great programmability property just by use of three control voltages—Vref1,Vref2, and Vb3. Thus any characteristics of the MFC are easily obtained. The proposed circuit is very simple and compact and can be VLSI fabricated.



---

*Source: 419370-2012-07-10.xml*