# A Single Switch High Step-Up DC-DC Converter Based on Tri-Winding Coupled Inductor for Renewable Energy Applications

Authors: Mana Hosseinzadehlish; Seyed Majid Hashemzadeh; Saeed Pourjafar; Ebrahim Babaei
Journal: International Transactions on Electrical Energy Systems
 (2022)

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## Abstract

This article introduces a novel nonisolated single-switch high step-up DC-DC converter using a tri-winding coupled inductor (TWCL) for renewable energy applications such as PV systems. Also, the voltage multiplier cell (VMC) is used to attain a high voltage gain. The used VMC acts as a passive clamp circuit and reduces the voltage stress across the power switch. So, a low voltage-rated power switch can be used in the presented converter. The suggested topology uses only one power switch with low on-state resistance (RDS-ON), which leads to a simple control circuit and decreases the conduction losses. Highefficiency, operating with low duty cycle, low peak voltage over semiconductor elements, low turns ratio, the number of the coupled inductor, and high voltage conversion ratio are the significant benefits of the recommended DC-DC converter. To show the achievement of the presented structure, operational mode principles, steady-state, efficiency calculations, and comparison results are provided. Finally, a 120 W experimental prototype with 200 V output voltage and 50 kHz switching frequency is built to prove the usefulness of the suggested high step-up converter. The efficiency is measured 92.11% at rated power.


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## Body

## 1. Introduction

In recent years, fossil fuel energy diminution leads to an increase of the serious economic problems [1]. To solve these significant concerns, renewable energy resources such as photovoltaic (PV) power systems are proposed by researchers [2]. Unfortunately, these sources cannot generate high voltage levels [3]. A method for voltage enhancement is the series connection of the PV panels. However, this method increases the system’s cost. Another suitable method is the high voltage gain DC-DC converters utilization. These converters can be used to obtain the required high voltage levels [4, 5].A classical boost DC-DC converter can obtain high voltage by a high duty cycle near to 1. But, this high duty cycle results in high conduction loss and low efficiency [6, 7]. Another drawback of the classical high step-up converter appears in high voltage utilization, where the power switch suffers from high voltage stress [8, 9]. As a result, the classical boost converter is not proper for high voltage applications. There are various voltage lifting methods that have been proposed by researchers, including switched inductor, voltage multiplier (VMC), switched capacitor (charge pump), and magnetic coupling [10]. The converters that use the abovementioned voltage boosting methods are able to accommodate higher voltage gain than the classical high step-up structure. However, the large number of these presented converters needs a high component count. Therefore, a high cost and complexity and also low efficiency are resulted. The magnetic coupling technique for voltage lifting can be implemented by transformers or coupled inductors [11, 12]. Transformer-based DC-DC converters use isolated or built-in transformers for achieving electrical isolation. However, these types of transformers enhance the cost and volume of the system. Coupled inductors are the precious elements of the nonisolated converters. Using coupled inductors, two or more windings can be implemented by only one core. So, the core losses and cost of the converter are literally decreased. In Reference [13], using coupled inductor and VMC, a high step-up structure with soft-switched ability is suggested. However, in this structure, two power switches are used. Meanwhile, a high voltage gain is obtained in higher numbers of turns ratio. The proposed converter in Reference [14] has used a TWCL and VMCs for voltage boosting. To recycle the leakage inductance’s energy, a passive clamp circuit is utilized to the converter. The main drawback of this structure is the higher number of elements than the other similar structures. In References [15, 16] using magnetic coupling, interleaved high step-up DC-DC converters are presented, which are proper for renewable energy uses. However, these converters suffer from low efficiency due to the high component count. In Reference [17], a fully soft-switched single-switch converter is presented. In this converter, an isolated transformer is used. It has a low cost and volume compared with other isolated converters. However, the maximum voltage on diodes is almost equal to the output voltage. In Reference [18], using coupled inductor, a nonisolated SEPIC-integrated high-voltage conversion ratio boost converter is presented. There is only one power switch in this topology, which decreases the total conduction loss. However, the maximum voltage across diodes is high, and the voltage gain of this structure is low compared to other similar structures. The presented converter in Reference [19] has used the coupled inductor technique for integrating the standard boost converter with VMC to achieve a high step-up hybrid topology for PV uses. However, the number of used diodes is high, which can reduce efficiency by increasing the conduction and forward losses. The converters in References [20, 21] have used coupled inductor in their structures for voltage increasing. However, these converters suffer from low efficiency, a high number of components, and higher maximum voltage stress on switches and diodes. Reference [22] suggested converters based on the coupled inductor, and clamp circuits are used in their structure in order to reduce the voltage stress of the main switch, However, the main downside of the converters proposed in Reference [23, 24] is that high boost factor can be obtained in higher duty cycle and higher number of turns ratio. In References [25–28], TWCL is used for enhancing the voltage gain. This type of coupled inductor has two secondary windings, which give two freedom degrees to regulate voltage gain and semiconductor element voltage stresses.In this paper, a new single-switch nonisolated high step-up DC-DC converter based on TWCL and VMC with high voltage gain is suggested. The used VMC operates as a passive clamp and decreases the voltage stress on the power switch. So, a low voltage-rated power switch can be used in the presented converter. The suggested topology uses only one low on-state resistance (RDS-ON) power switch, which leads to a simple control circuit and decreases the conduction losses. (1) high efficiency, (2) operating with low duty cycle, (3) low turns ratio of the coupled inductor, (4) low voltage stress across semiconductor components, and (5) high voltage conversion ratio are the significant benefits of the presented DC-DC converter. In the rest of the paper, to illustrate the performance of the suggested structure, operational principles, steady-state and efficiency analysis, design considerations, comparison study, and experimental results are provided.


## 2. Suggested Converter and Operational Principle

The configuration of the presented converter is shown in Figure1. This structure includes a TWCL, one power switch (S), four diodes (D1, D2, D3, and Do), and four capacitors (C1, C2, C3, and Co). N1, N2, and N3 are the primary, secondary, and tertiary windings turn number of the TWCL, respectively. Capacitor C1 operates as a voltage-boosting capacitor. D1 and C2 operate as a voltage clamp, which reduces the peak voltage across S. D2 and D3 and C3 operate as a VMC. Diode Do and capacitor Co are the output diode and output filter, respectively. To simplify the operation principles and steady-state analysis, the following suppositions are counted:(1)
All semiconductor elements are ideal.(2)
TWCL is modelled as an ideal tree-winding transformer with magnetizing (Lm) and leakage (Lk) inductances. The secondary and tertiary turn ratios of this transformer are obtained as follows:(1)VN2VN1=N2N1=n2,(2)VN3VN1=N3N1=n3,(3)k=LmLm+Lk.(3)
The used capacitors are large adequately. Hence, the voltages across capacitors are invariable during the switching period (Ts). The operation principles of the recommended topology are analysed in a continuous conduction mode (CCM) and discontinuous conduction mode (DCM). Figures 2(a) and 2(b) show the main waveforms of the suggested structure in CCM and DCM, respectively.Figure 1
Presented converter.Figure 2
Main waveforms of the presented topology: (a) CCM and (b) DCM.
(a)(b)


### 2.1. Mode Analysis in CCM

CCM operation includes four modes. Modes1 and 3 are transient modes with small-time durations and modes 2 and 4 are the main modes of CCM.Mode 1.
[t0 < t < t1]: At t = t0, power switch S is turned ON. So, the magnetizing Lm and leakage Lk inductances of the TWCL receive energy from input sources, and their currents enhance linearly. D1 and Do are conducting and diodes D2 and D3 are reverse-biased. The current pass of mode 1 is shown in Figure 3(a). As can be seen in this figure, capacitors C1 and C3 are discharged through the output diode Do, and the energy of these capacitors along with the tertiary side of the TWCL is transferred to the load. Moreover, C2 is charged through diode D1. This mode finishes at t = t1, when D1 and Do are turned OFF.Figure 3
Equivalent power circuits of the suggested structure in transient modes: (a) mode1 in CCM, (b) mode 3 in CCM, and mode 2 in DCM.
(a)(b)Mode 2.
[t1 < t < t2]: At the beginning of this mode, D2 and D3 are forward-biased, and power switch S is still turned ON. Same as mode 1, Lm and Lk are still charged by Vin and their currents are increased. Also, the currents of the secondary and tertiary sides of the TWCL reduce linearly. The equivalent power circuit of this mode is demonstrated in Figure 4(a). According to this figure, capacitors C1, C3, and Co are charged and C2 is discharged through diode D2.Figure 4
Equivalent power circuits of the suggested structure in main modes: (a) mode 2 in CCM and mode1 in DCM, (b) mode 4 in CCM and mode 3 in DCM, and (c) mode 4 in DCM.
(a)(b)(c)Mode 3.
[t2 < t < t3]: In mode 3, power switch S is turned OFF and all of the diodes are forward-biased. Due to the demagnetizing of Lm and Lk, their currents start to decrease. The energy of Lk is transferred to C1 by D1 and D2. So, the leakage energy is recycled. It should be noticed that during this mode C3 is charged and C2 is discharged. This mode ends at t = t3 when diodes D2 and D3 are turned OFF. The equivalent power circuit of this mode is depicted in Figure 3(b).Mode 4.
[t3 < t < t4]: During this mode, power switch S and D2 and D3 are turned OFF and D1 and Do are conducting. The magnetizing Lm and leakage Lk inductances release their energy. Thus, ilm and ilk are decreased. Also, the currents of the secondary and tertiary sides of the TWCL increased linearly. The energy of Lk is recycled by D1 and C2. The current of diode D1 is decreased, and the current decrease rate of this diode is controlled by Lk. Furthermore, the energy of the capacitors C1 and C3 and the tertiary side of the TWCL is transferred to the load by diode Do. It can be mentioned that during this mode, diode D1 and capacitor C2 act as a passive clamp and suppresses the voltage spikes across the power switch. The equivalent circuit of this mode is presented in Figure 4(b).


### 2.2. Mode Analysis in DCM

The DCM operation of the recommended topology is separated into four modes. Modes1, 2, and 4 are the main modes and mode 3 is the transient mode with a small-time duration. As can be seen in Figure 3, modes 1, 2, and 3 are like to CCM operation. In the fourth mode, the magnetizing and leakage currents (iLm and iLk) of the TWCL fall to zero. All of the semiconductors are turned OFF, and the stored energy in the output capacitor Co is transferred to the load. The equivalent circuit of this mode is presented in Figure 4(c).


## 2.1. Mode Analysis in CCM

CCM operation includes four modes. Modes1 and 3 are transient modes with small-time durations and modes 2 and 4 are the main modes of CCM.Mode 1.
[t0 < t < t1]: At t = t0, power switch S is turned ON. So, the magnetizing Lm and leakage Lk inductances of the TWCL receive energy from input sources, and their currents enhance linearly. D1 and Do are conducting and diodes D2 and D3 are reverse-biased. The current pass of mode 1 is shown in Figure 3(a). As can be seen in this figure, capacitors C1 and C3 are discharged through the output diode Do, and the energy of these capacitors along with the tertiary side of the TWCL is transferred to the load. Moreover, C2 is charged through diode D1. This mode finishes at t = t1, when D1 and Do are turned OFF.Figure 3
Equivalent power circuits of the suggested structure in transient modes: (a) mode1 in CCM, (b) mode 3 in CCM, and mode 2 in DCM.
(a)(b)Mode 2.
[t1 < t < t2]: At the beginning of this mode, D2 and D3 are forward-biased, and power switch S is still turned ON. Same as mode 1, Lm and Lk are still charged by Vin and their currents are increased. Also, the currents of the secondary and tertiary sides of the TWCL reduce linearly. The equivalent power circuit of this mode is demonstrated in Figure 4(a). According to this figure, capacitors C1, C3, and Co are charged and C2 is discharged through diode D2.Figure 4
Equivalent power circuits of the suggested structure in main modes: (a) mode 2 in CCM and mode1 in DCM, (b) mode 4 in CCM and mode 3 in DCM, and (c) mode 4 in DCM.
(a)(b)(c)Mode 3.
[t2 < t < t3]: In mode 3, power switch S is turned OFF and all of the diodes are forward-biased. Due to the demagnetizing of Lm and Lk, their currents start to decrease. The energy of Lk is transferred to C1 by D1 and D2. So, the leakage energy is recycled. It should be noticed that during this mode C3 is charged and C2 is discharged. This mode ends at t = t3 when diodes D2 and D3 are turned OFF. The equivalent power circuit of this mode is depicted in Figure 3(b).Mode 4.
[t3 < t < t4]: During this mode, power switch S and D2 and D3 are turned OFF and D1 and Do are conducting. The magnetizing Lm and leakage Lk inductances release their energy. Thus, ilm and ilk are decreased. Also, the currents of the secondary and tertiary sides of the TWCL increased linearly. The energy of Lk is recycled by D1 and C2. The current of diode D1 is decreased, and the current decrease rate of this diode is controlled by Lk. Furthermore, the energy of the capacitors C1 and C3 and the tertiary side of the TWCL is transferred to the load by diode Do. It can be mentioned that during this mode, diode D1 and capacitor C2 act as a passive clamp and suppresses the voltage spikes across the power switch. The equivalent circuit of this mode is presented in Figure 4(b).


## 2.2. Mode Analysis in DCM

The DCM operation of the recommended topology is separated into four modes. Modes1, 2, and 4 are the main modes and mode 3 is the transient mode with a small-time duration. As can be seen in Figure 3, modes 1, 2, and 3 are like to CCM operation. In the fourth mode, the magnetizing and leakage currents (iLm and iLk) of the TWCL fall to zero. All of the semiconductors are turned OFF, and the stored energy in the output capacitor Co is transferred to the load. The equivalent circuit of this mode is presented in Figure 4(c).


## 3. Steady-State Analysis

### 3.1. Analysis of CCM Operation

To streamline the steady-state analysis of the proposed topology, only modes 2 and 4 are taken into account, owing to the fact that the time intervals of other modes are extremely short. WhenS is turned ON in mode 2, equations (4)–(7) are derived for VN1,VN2,VN3, and VLk:(4)VN1II=LmLm+LkVin=kVin,(5)VN2II=n2VN1II=n2kVin,(6)VN3II=n3VN1II=n3kVin,(7)VLkII=LkLm+LkVin=1−kVin.By using voltage-second balance law toN1, N2, N3, and Lk, equations (8)–(11) are achieved in mode 4(8)VN1IV=−kD1−DVin,(9)VN2IV=−n2kD1−DVin,(10)VN3IV=−n3kD1−DVin,(11)VLkIV=−1−kD1−DVin.The voltages of capacitorsC1, C2, and C3 are achieved as follows:(12)VC2=Vin−VLkIV−Vn1IV−Vn2IV=1+n2kD1−DVin,(13)VC1=VC2+VN2II+VN3II=1+n2k+n3k−n3kD1−DVin,(14)VC3=VN3II=n3kVin.Based on (8), (10), (11), (13), and (14), the output voltage and voltage gain of the recommended structure in CCM are obtained as follows:(15)Vo=Vco=Vin−VLKIV−VN1IV+VC1−VN3IV+VC3=2+n2k+2n3k−n3kD1−DVin,(16)MCCM=VoVin=2+n2k+n3k2−D1−D.The voltage conversion ratio of the presented topology versus duty cycle in terms of the diverse value of the coupling coefficient is depicted in Figure5(a), where the turns ratio is considered to be n2 = n3 = 2. As can be seen in this figure, it is clear that the voltage conversion ratio is enhanced with increasing the leakage inductance; so, to decrease the skin effects and leakage inductance to attain a higher voltage conversion ratio, sandwich winding construction is applied in the used high-frequency TWCL.Figure 5
(a) Voltage conversion ratio of the converter versus duty cycle under various values of the coupling coefficient (forn2 = n3 = N = 2) and (b) voltage gain of the presented structure (MCCM).
(a)(b)By considering the value of the coupling coefficientk equal to 1 and the secondary and tertiary turns ratio equal to N (n2 = n3 = N), the suggested structure’s ideal voltage conversion ratio is derived as follows:(17)MCCM=VoVin=2+N3−D1−D.Figure5(b) indicates the presented DC-DC converter’s ideal voltage conversion ratio (MCCM) versus duty cycle under diverse turns ratio. It is evident that a higher voltage conversion ratio is attained by enhancement of the coupled inductor’s turns ratio either without operating at an extremely large duty cycle.


### 3.2. DCM Operation Analysis

DCM operation consists of four modes in which modes 1, 2, and 3 are the same as modes in CCM operation; so, the voltage and current relations of these modes are similar too. In mode 4, the voltagesVN1, VN2, and VN3 are derived as follows:(18)VN1IV=VN2IV=VN3IV=0.The voltage-second balance law is utilized on the primary winding of the TWCL as follows:(19)∫0DTsVN1Idt+∫DTsD+D′TsVN1IIIdt+∫D+D′TsTsVN1IVdt=0.Based on (19), the voltage Vn1 in mode 2 is attained as follows:(20)VN1III=−DD′Vin.The capacitor voltage can be expressed as follows:(21)VC1=DN+1+D′D′Vin,(22)VC2=DN+1+D′2N+1D′Vin,(23)VC3=NVin.Considering the above equations, the converter’s voltage conversion ratio in DCM operation is obtained as follows:(24)MDCM=VoVin=D2N+2+D′3N+2D′.By considering (24), D′ is calculated as follows (25):(25)D′=D2N+2MDCM−3N+2.The peak current of the magnetizing inductance is obtained as follows:(26)ILmpeak=DTsLmVin.Also, the average current ofCo is written as follows:(27)ICoavg=IDoavg−Io=12D′ILmpeakN−Io.At steady-state operation, the average current of output capacitorICo is zero and Io = Vo/Ro. So, by substituting (25) and (26) in (27), equation (28) is obtained:(28)D22N+2Vin2NVoVo/Vin−3N+2=LmRoTs.The magnetizing inductance time constant is equal to:(29)τLm=LmRoTs.By replacing (29) into (28), the DCM operation voltage gain of the suggested topology is calculated as follows:(30)MDCM=3N+2+3N+22+22N+2/NτLmD22.The voltage gain of the recommended topology at CCM operation and at DCM operation under variousτLm and N = 2 is shown in Figure 6. It is clear that MCCM is higher than MDCM, particularly at higher duty cycles.Figure 6
Voltage conversion ratio of the presented structure versus duty cycle at CCM operation underN = 2 and at DCM operation under various τLm.


### 3.3. Analysis of BCM Operation

To operate the presented structure in boundary conduction mode, the voltage gainMCCM and MDCM should be considered to be equal. Considering equations (17) and (30), the boundary normalized magnetizing inductance time constant can be obtained as follows:(31)τLmB=D1−D22N2+N3−D.The curve ofτLmB versus duty cycle under different turn ratio is depicted in Figure 7. For τLm higher than τLmB, the recommended topology will operate at the CCM condition.Figure 7
Suggested structure’s boundary condition versus duty cycle underN = 2.


## 3.1. Analysis of CCM Operation

To streamline the steady-state analysis of the proposed topology, only modes 2 and 4 are taken into account, owing to the fact that the time intervals of other modes are extremely short. WhenS is turned ON in mode 2, equations (4)–(7) are derived for VN1,VN2,VN3, and VLk:(4)VN1II=LmLm+LkVin=kVin,(5)VN2II=n2VN1II=n2kVin,(6)VN3II=n3VN1II=n3kVin,(7)VLkII=LkLm+LkVin=1−kVin.By using voltage-second balance law toN1, N2, N3, and Lk, equations (8)–(11) are achieved in mode 4(8)VN1IV=−kD1−DVin,(9)VN2IV=−n2kD1−DVin,(10)VN3IV=−n3kD1−DVin,(11)VLkIV=−1−kD1−DVin.The voltages of capacitorsC1, C2, and C3 are achieved as follows:(12)VC2=Vin−VLkIV−Vn1IV−Vn2IV=1+n2kD1−DVin,(13)VC1=VC2+VN2II+VN3II=1+n2k+n3k−n3kD1−DVin,(14)VC3=VN3II=n3kVin.Based on (8), (10), (11), (13), and (14), the output voltage and voltage gain of the recommended structure in CCM are obtained as follows:(15)Vo=Vco=Vin−VLKIV−VN1IV+VC1−VN3IV+VC3=2+n2k+2n3k−n3kD1−DVin,(16)MCCM=VoVin=2+n2k+n3k2−D1−D.The voltage conversion ratio of the presented topology versus duty cycle in terms of the diverse value of the coupling coefficient is depicted in Figure5(a), where the turns ratio is considered to be n2 = n3 = 2. As can be seen in this figure, it is clear that the voltage conversion ratio is enhanced with increasing the leakage inductance; so, to decrease the skin effects and leakage inductance to attain a higher voltage conversion ratio, sandwich winding construction is applied in the used high-frequency TWCL.Figure 5
(a) Voltage conversion ratio of the converter versus duty cycle under various values of the coupling coefficient (forn2 = n3 = N = 2) and (b) voltage gain of the presented structure (MCCM).
(a)(b)By considering the value of the coupling coefficientk equal to 1 and the secondary and tertiary turns ratio equal to N (n2 = n3 = N), the suggested structure’s ideal voltage conversion ratio is derived as follows:(17)MCCM=VoVin=2+N3−D1−D.Figure5(b) indicates the presented DC-DC converter’s ideal voltage conversion ratio (MCCM) versus duty cycle under diverse turns ratio. It is evident that a higher voltage conversion ratio is attained by enhancement of the coupled inductor’s turns ratio either without operating at an extremely large duty cycle.


## 3.2. DCM Operation Analysis

DCM operation consists of four modes in which modes 1, 2, and 3 are the same as modes in CCM operation; so, the voltage and current relations of these modes are similar too. In mode 4, the voltagesVN1, VN2, and VN3 are derived as follows:(18)VN1IV=VN2IV=VN3IV=0.The voltage-second balance law is utilized on the primary winding of the TWCL as follows:(19)∫0DTsVN1Idt+∫DTsD+D′TsVN1IIIdt+∫D+D′TsTsVN1IVdt=0.Based on (19), the voltage Vn1 in mode 2 is attained as follows:(20)VN1III=−DD′Vin.The capacitor voltage can be expressed as follows:(21)VC1=DN+1+D′D′Vin,(22)VC2=DN+1+D′2N+1D′Vin,(23)VC3=NVin.Considering the above equations, the converter’s voltage conversion ratio in DCM operation is obtained as follows:(24)MDCM=VoVin=D2N+2+D′3N+2D′.By considering (24), D′ is calculated as follows (25):(25)D′=D2N+2MDCM−3N+2.The peak current of the magnetizing inductance is obtained as follows:(26)ILmpeak=DTsLmVin.Also, the average current ofCo is written as follows:(27)ICoavg=IDoavg−Io=12D′ILmpeakN−Io.At steady-state operation, the average current of output capacitorICo is zero and Io = Vo/Ro. So, by substituting (25) and (26) in (27), equation (28) is obtained:(28)D22N+2Vin2NVoVo/Vin−3N+2=LmRoTs.The magnetizing inductance time constant is equal to:(29)τLm=LmRoTs.By replacing (29) into (28), the DCM operation voltage gain of the suggested topology is calculated as follows:(30)MDCM=3N+2+3N+22+22N+2/NτLmD22.The voltage gain of the recommended topology at CCM operation and at DCM operation under variousτLm and N = 2 is shown in Figure 6. It is clear that MCCM is higher than MDCM, particularly at higher duty cycles.Figure 6
Voltage conversion ratio of the presented structure versus duty cycle at CCM operation underN = 2 and at DCM operation under various τLm.


## 3.3. Analysis of BCM Operation

To operate the presented structure in boundary conduction mode, the voltage gainMCCM and MDCM should be considered to be equal. Considering equations (17) and (30), the boundary normalized magnetizing inductance time constant can be obtained as follows:(31)τLmB=D1−D22N2+N3−D.The curve ofτLmB versus duty cycle under different turn ratio is depicted in Figure 7. For τLm higher than τLmB, the recommended topology will operate at the CCM condition.Figure 7
Suggested structure’s boundary condition versus duty cycle underN = 2.


## 4. Design Guidance

### 4.1. Voltage Stress Analysis

The voltage stress across the semiconductor components in CCM operation is achieved as follows:(32)VD1=VDo=N+11−DVin=1+N3−DN+2Vo,(33)VD2=2N+11−DVin=1+2N3−DN+2Vo,(34)VD3=N1−DVin=N3−DN+2Vo,(35)Vds=11−DVin=13−DN+2Vo.


### 4.2. Current Stress Analysis

When switchS is in on/off state in CCM operation, the input current’s average value is calculated as follows:(36)Iinon=ILm−NiC2on+NiC3on−iC2on=ILm+3NiC3on,(37)Iinoff=Io+iCooff+iC2off.The average current of capacitors in on/off state is obtained as equations (38) and (39):(38)iC1on=−iC2on=iC3on=−DiCoon=1DIo,(39)iC1off=−iC2off=iC3off=−DiCooff=−11−DIo.Based on the conversion of the power and equations (36), (37), (38), and (39), the magnetizing inductance average value is calculated as follows:(40)ILmavg=MCCM−3N−21−DIo=2N+11−DIo.Also, the magnetizing inductance current ripple is obtained as follows:(41)ΔILm=DTSVinLm.According to equations (40) and (41), the peak current of the magnetizing inductance is calculated as follows:(42)ILmpeak=2N+11−DIo+DTSVin2Lm.By considering the amp-sec balance on capacitors, the average currents of the used diodes will be equal toIo, so the peak currents of power switch and diodes are derived:(43)ID1peak=IDopeak=2Io1−D,(44)ID2peak=ID3peak=2IoD,(45)IdsPeak≈2N−DN−1+2D1−DIo.


### 4.3. Design of Magnetizing Inductance

In order to CCM operation of the presented structure, equations (29) and (31) are used to calculate the minimum value of magnetizing inductance which is attained as follows:(46)Lm≥D1−D2Ro2N2+N3−Dfs.


### 4.4. Design of Capacitors

According toiC = CdVCi/dt, dt = DTS = D/fS and dVCi = ∆VCi, where ∆VCi is the voltage ripple of capacitors that is considered 2% of the voltage on capacitors. Based on equations (12)–(15), the values of capacitors are derived as follows:(47)Ci≥DVoΔVCiRofs,(48)Co≥DVoΔVCoRofs,where i = 1, 2, 3, and 4.


## 4.1. Voltage Stress Analysis

The voltage stress across the semiconductor components in CCM operation is achieved as follows:(32)VD1=VDo=N+11−DVin=1+N3−DN+2Vo,(33)VD2=2N+11−DVin=1+2N3−DN+2Vo,(34)VD3=N1−DVin=N3−DN+2Vo,(35)Vds=11−DVin=13−DN+2Vo.


## 4.2. Current Stress Analysis

When switchS is in on/off state in CCM operation, the input current’s average value is calculated as follows:(36)Iinon=ILm−NiC2on+NiC3on−iC2on=ILm+3NiC3on,(37)Iinoff=Io+iCooff+iC2off.The average current of capacitors in on/off state is obtained as equations (38) and (39):(38)iC1on=−iC2on=iC3on=−DiCoon=1DIo,(39)iC1off=−iC2off=iC3off=−DiCooff=−11−DIo.Based on the conversion of the power and equations (36), (37), (38), and (39), the magnetizing inductance average value is calculated as follows:(40)ILmavg=MCCM−3N−21−DIo=2N+11−DIo.Also, the magnetizing inductance current ripple is obtained as follows:(41)ΔILm=DTSVinLm.According to equations (40) and (41), the peak current of the magnetizing inductance is calculated as follows:(42)ILmpeak=2N+11−DIo+DTSVin2Lm.By considering the amp-sec balance on capacitors, the average currents of the used diodes will be equal toIo, so the peak currents of power switch and diodes are derived:(43)ID1peak=IDopeak=2Io1−D,(44)ID2peak=ID3peak=2IoD,(45)IdsPeak≈2N−DN−1+2D1−DIo.


## 4.3. Design of Magnetizing Inductance

In order to CCM operation of the presented structure, equations (29) and (31) are used to calculate the minimum value of magnetizing inductance which is attained as follows:(46)Lm≥D1−D2Ro2N2+N3−Dfs.


## 4.4. Design of Capacitors

According toiC = CdVCi/dt, dt = DTS = D/fS and dVCi = ∆VCi, where ∆VCi is the voltage ripple of capacitors that is considered 2% of the voltage on capacitors. Based on equations (12)–(15), the values of capacitors are derived as follows:(47)Ci≥DVoΔVCiRofs,(48)Co≥DVoΔVCoRofs,where i = 1, 2, 3, and 4.


## 5. Efficiency Analysis

In order to obtain the efficiency of the suggested topology, the parasitic resistances of elements are assumed as follows:Rds−on: on-state resistance of power switch.RFD1∼Do: the forward resistance of diodes.RC1∼Co: ESR of capacitors.RLN1∼LN3: ESR of the coupled inductor’s windings.VFD1∼Do: the forward voltage of diodes.Efficiency of the presented topology (η) is calculated as follows [29]:(49)η=PoPo+Ploss,(50)Ploss=Pswitch+PRFD1∼Do+PVFD1∼Do+PRC1∼Co+PRLN1∼LN3.The power switch total loss is equal to:(51)PSwitch=PRds−on+PSW.Also, the power switch conduction loss is obtained as follows:(52)PRds−on=Rds−on×Isrms2=Rds−on×2N−DN−1+2D1−D2.The switching loss of the power switch is obtained as follows:(53)PSW=fscsvs2=fscs12+N3−D2.The following equation expresses diode forward resistance losses:(54)PRFD1∼Do=RFD1∼Do×ID1∼Dorms2=RFD1+RFDo×Io1−D2+RFD2+RFD3×IoD2.Forward voltage losses of the used diodes are achieved as follows:(55)PVFD1∼Do=VFD1∼Do×ID1∼Doave=VFD1+VFD2+VFD3+VFDo×Io.Moreover, capacitor power losses are expressed as follows:(56)PRC=RC1∼Co×IC1∼Corms2+RCin×ICinrms2=RC1+RC2+RC3×IoD1−D2+RCo×IoD2+RCin×ILinrms−ILN1rms2.The primary, secondary, and tertiary sides of coupled inductor and input filter’s inductor conduction loss can be obtained as follows:(57)PRL=RLin×ILinrms2+RLN1∼LN3×ILN1∼LN3rms2=RLin×2DN+1+3N1−D2D1−D2+3−D21−DIo2+RLN1×N9−5DD1−DIo2+RLN2×1D1−DIo2+RLN2×4−3DD1−DIo2.


## 6. Comparison Assessment

Table1 shows a comparison between the recommended DC-DC topology and other similar converters in terms of voltage gain, component number, voltage and current stress of the switch, voltage stress of output diode, maximum current stress of diodes, and input current. To prove the performance of the presented structure, five competitive diagrams have been indicated in Figures 8–11.Table 1
Comparison of the suggested DC-DC structure with other comparable converters.
ConverterNumber ofVoltage gainVoltage stress on switchVoltage stress on output diodeCurrent stress on switchMax current stress on diodeContinuous input currentSDCL+CL[4]1451 + 12w(1 + D + N (2 − D))/(1 − D)Vo/(1 + D + N(2 − D))(N + 1) Vo/(1 + D + N(2 − D))(2D + N(3.14 − 2.14D))Io/D(1 − D)(2 + N)Io/(1 − D)Yes[5]1650+12w(2+N +ND)/(1−D)Vo/(2+N+ND)NVo/(2+N+ND)——No[6]1451+12w((N+1) (1+D))/(1−D)Vo/((N+1) (1+D))Vo/(1+D)2 (N+1)Io/D(1− D)2 (N+1)Io/D (1−D)Yes[7]1550+12w(1+D+N(2− D))/(1−D)Vo/(1 + D + N(2 − D))NVo/(1 + D + N(2 − D))2 (N + 1)Io/D2Io/(1 − D)No[11]1550 + 12w(2 + N(2 − D))/(1 − D)Vo/(2 + N(2 − D))Vo/(2 + N(2 − D))(2 + ND (2 − D))Io/D(1 − D)2 (N + 1)Io/(1 − D)Yes[19]1781 + 12w(4-D + N(2 − D))/(1 − D)Vo/(4 − D + N(2 − D))(N ( − -D) − D) Vo/(4 − D + N (2 − D))——No[20]1451 + 12w((N + 1) D + N + 2)/(1 − D)Vo/((N + 1 + N + 2) D)(N + 1) Vo/(N + 1) D + N + 2)(2 + 2N D)Io/D(1 − D)(2 + 2N D)Io/D(1 − D)Yes[21]1451 + 12w(2 + N + D)/(1 − D)Vo/(2 + N + D)(N + 1) Vo/(2 + N + D)(2 + D + N(2 − D))Io/D(1 − D)2 (2D + N(2 − D))Io/D(1 − D)Yes[22]1440 + 12w(1 + N + ND)/(1 − D)Vo/(1 + N + ND)NVo/(1 + N + ND)(1 + ND)Io/D(1 − D)Io/(1 − D)Yes[23]1550 + 12w(2 + 2N)/(1 − D)Vo/(2 + 2N)(N + 1) Vo/(2 + 2N)2 (N + D)Io/D(1 − D)2NIo/D(1 − D)Yes[24]1540 + 12w(1 + D + ND(1 + D))/2(1 − D)Vo/(2< + N + ND)2NDVo/(1 + D + ND(1 + D))(2N + (1 − N)D)Io/D(1 − D)2Io/(1 − D)No[25]2340 + 13w(2 + N(1 + D))/(1 − D)Vo/(2 + N(1 + D))(ND)Vo/(2 + N(1 + D))(2 + N(1 + D))Io/(1 − D)2Io/(1 − D)Yes[26]1660 + 13w((3 − D)N + 2)/(1 − D)Vo/((3 − D)N + 2)(N + 1) Vo/((3 − D)N + 2)((6 − 4D)N + 2)Io/D(1 − D)2Io/(1 − D)Yes[27]2440 + 13w(1 + N + D)/(1 − D)Vo/(1 + N + D)NVo/(1 + N + D)(0.5 N D)Io/D(1 − D)(N + 2)Io/2(1 − D)Yes[28]1441 + 13w(2 − D + N(2 − D))/(1 − D)Vo/(2 − D + N(2 − D))NVo/(2 − D + N(2 − D))——No[30]2222 + 02/(1 − D)Vo/2Vo——Yes[31]2222 + 0(1 − D2)/) (1 − 2D + D2)Vo/(1 − D2)Vo/(1 − D2)——Yes[32]1331 + 12w(N + 2)/(1 − D)Vo/(N + 2)(N + 1) Vo/(N + 2)(2N D + 1) Io/(D)(2N + 2 − ND) Io/(D(1 − D))Yes[33]1440 + 13w(2 + 2N ND)/(1 − D)Vo/(2 + 2N ND)(1 + N Vo)/(2 + 2N ND)(1 + 2N ND + D) Io/(D(1 − D))2Io/(1 − D)Yes[34]1660 + 13w(3 + 4N ND)/(1 − D)Vo/(3 + 4N ND)(2N + 1) Vo/(3 + 4N ND)(3 + 4N ND) Io/(1 − D) + (4 (N + 1)Io/D)2Io/(1 − D)NoProposed1450 + 13w((3 − D)N + 2)/(1 − D)Vo/((3 − D)N + 2)(N + 1) Vo/((3 − D)N + 2)(1 + D + N(3 − D))Io/D(1 − D)2Io/(1 − D)YesFigure 8
Voltage gain comparison of suggested structure with other converters,N = 2.Figure 9
Comparison of the normalized voltage stress of power switch,N = 2.Figure 10
Comparison of the normalized voltage stress of output diode versus,N = 2.Figure 11
(a) Comparison of the normalized current stress of switch,N = 2. (b) Comparison of the normalized maximum current stress of diode, N = 2.
(a)(b)According to Figure8 that illustrates the voltage gain comparison versus duty cycle, it is clear that the suggested structure has a higher voltage conversion ratio than all other converters for all ranges of duty cycle (except converters in References [33, 34]). However, the converter in Reference [34] has more components and high current peak of power switch (based on Figure 11(a)). The voltage gain of the suggested converter is higher than the structure in Reference [33] for duty cycle 0 ˂ D ˂ 0.5, but for higher duty cycles, the gain of the mentioned topology in Reference [33] is greater; that it depicts the superiority of the recommended structure. Operation with high duty cycle leads to high power loss in switches.Figure9 shows the voltage stress comparison of power switches versus D. It is clear that the voltage stress of the power switch in the suggested structure is lower than the one in all introduced converters in Table 1 (except [34]). It means that a low on-state resistance switch can be selected in these converters.Figure10 illustrates the voltage stress comparison of output diode versus duty cycle. It is evident that the voltage stress of the output diode in the presented structure is lower than the other converters for all ranges of duty cycle (except converters in References [5, 11, 19, 25, 28]). The voltage stress of the output diode in converters [5, 19, 28] are lower than the suggested structure for D ˃ 0.4 and D ˂ 0.4, respectively. The voltage stress of the output diode in the structures [11, 25] is lower than the suggested structure for all ranges of D. But, these structures have a higher voltage stress across power switch and lower voltage conversion ratio than the suggested structure.Figure11(a) depicts the current stress comparison of power switches versus D. It is seen that the current stress in the suggested structure is lower than converters [26, 33] and [34] for D ˃ 0.4 and all ranges of duty cycle, respectively. Therefore, the efficiency of the converter in Reference [34] is lower than the proposed converter. Moreover, the minimum rate of current stress of the power switch in the proposed converter happens at duty cycle between 0.3 ˂ D ˂ 0.7. Figure 11(b) displays the maximum current stress comparison of diodes versus duty cycle. As it can be seen, the maximum current stress on diode in the proposed converter is lower than the one in other structures (except the one in converter [22]).


## 7. Experimental Results

In order to certify the suggested converter’s operation and prove the theoretical results, a 120 W sample has been made in the laboratory. In the proposed converter, the input voltage is boosted from 12 V to 200 V for the duty cycle of 0.6. The circuit components and specifications of the experimental prototype are presented in Tables2 and 3, respectively.Table 2
List of the circuit components of the prototype.
ElementSpecificationPower switchSIRF260 N (200 V/50 A),RDS(ON) = 0.04 ΩDiodesMUR2060 (600 V/20μA)C1, C2, and C3200 V/220μFCo450 V/470μFCoupled inductorFerrite EE core withLm = 200 μHLC input filterLin: 50 μHCin: 220 μF/50 VTable 3
Specification of the experimental prototype of the presented topology.
ParameterValueRated output power120 WVin12 VVout200 V(n1/n2/n3)1/2/2Switching frequency (fs)50 kHzDuty cycle0.6The experimental results are shown in Figures12–16. Time per division in the experimental figures is equal to 10µs. Output voltage of the suggested converter is illustrated in Figure 12, which is equal to 200 V for the D = 0.6, which confirms equation (17). It is evident that the voltage ripple of the output voltage is very low.Figure 12
Measured waveform of output voltageVo.Figure 13
Measured voltage waveform of power switch VDS.Figure 14
Voltage waveforms of capacitors, (a) VC1, (b) VC2, and (c) VC3.
(a)(b)(c)Figure 15
Voltage and current waveforms of diodes, (a)VD1 and iD1, (b) VD2 and iD2, (c) VD3 and iD3, and (d) VDo and and iDo.
(a)(b)(c)(d)Figure 16
Measured waveform of input source current Iin. (a) Without low pass filter and (b) with low pass filter.
(a)(b)Figure13 displays the voltage and current of the power switch. Its voltage is equal to 30 V and is much lower than the output voltage, so, it can be noted that a switch with low RDS(on) can be employed in the proposed topology.Also, this experimental result confirms equation (35). Figures 14(a)-14(c) represent the voltage waveforms of capacitors (C1∼ C3). The experimental value of VC1 is equal to 112 V and verifies equation (13). Additionally, VC2 and VC3 are equal to 64 V and 22 V, which verify equations (12) and (14), respectively.The voltage and current waveforms of diodes (D1∼ Do) are indicated in Figures 15(a)-15(d). The value of the voltage across diodes D1 and Do are equal to 88 V. According to equation (32), the theoretical values of the voltages of these diodes are equal to 90. Also, the voltages across diode D2 and D3 are equal to 147 V and 58 V, which confirm equations (33)-(34), respectively. It is plain to see that voltages of diodes are much lower than the output voltage.The input source current with and without low pass filter is depicted in Figure16. An LC low pass filter is applied to the converter’s input port to reduce the input source current ripple. The proposed converter with an LC low pass filter is shown in Figure 1. Theoretical and experimental voltage values of the semiconductor and capacitors are compared and summarized in Table 4. Experimental values are lower, and this difference is because of the parasitic component effect. Table 5 gives power losses of the elements of the proposed converter at Po = 120 W. It is clear that the main part of the proposed converter total losses is attributed to the switch and diode losses.Table 4
Comparison between experimental and theoretical voltage values.
ParameterExperimental value (V)Theoretical value (V)VC1112114VC26466VC32224VCo200204VD18890VD2147150VD35860VDo8890VDS2930Table 5
Power loss specification atPo = 120 W.
ParameterValue (W)Total losses of power switch4.41Total losses of diodes1.02Coupled inductor losses2.11Total losses of capacitors and other0.559Rated output power120Figure17 shows the proportion of component loss breakdown at Po = 120 W, and the measured theoretical and experimental efficiencies of the recommended topology based on equation (49) under various output powers are ranged from 50 W to 120 W. The maximum value of the efficiency is equal to 92.11% which is derived at Po = 120 W and under Vin = 12 V, fS = 50 kHz, n2 = n3 = 2, and duty cycle of 0.6. Also, for output power higher than 80 W, the efficiency is obtained more than 90%. Finally, the experimental prototype of the suggested topology is depicted in Figure 18.Figure 17
(a) Proportion of component loss breakdown at 120 W. (b) Theoretical and experimental efficiencies of the suggested structure under various output power.
(a)(b)Figure 18
Experimental prototype of the proposed converter.


## 8. Conclusion

In this article, a new single-switch nonisolated high gain DC-DC converter is introduced. To attain a high voltage conversion ratio, a three-winding coupled inductor (TWCL) and a voltage multiplier are used in this topology. VMC also operates as a clamp circuit and recycles the energy of the leakage inductance of the coupled inductor, so voltage stress on the power switch and other semiconductors is reduced and the efficiency will be improved. Steady-state and efficiency analysis of the recommended structure is also provided. Lastly, to prove the operation of the presented structure and the validity of the theoretical results, a 120 W experimental sample with 200 V output voltage is built. According to the theoretical and experimental analyses, it can be expressed that the suggested topology has the following superiorities: (1) high voltage conversion ratio in low duty cycle, (2) low number of elements, (3) input and output sides have common ground, and (4) voltage stress across the power switch and diodes is low, so, a power switch with low RDS-ON and low-rated diodes can be used that brings about lower power loss, lower cost, and higher efficiency.



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