# FPGA-Based Fixed Point Implementation of a Real-Time Induction Motor Emulator

Authors: L. Charaabi
Journal: Advances in Power Electronics
 (2012)

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## Abstract

This paper investigates the numerical issue of a discrete-time induction-motor emulator implementation. The stability analysis of the finite-word-length implementation shows a coupling between required word length and the sample rate. We propose specific guidelines to analyze this coupling and to estimate the required data word length for both signals and coefficients of the model. To respect algorithm requirements, an FPGA-based implementation was used for architecture development. The direct torque control is implemented to verify in real time the AC-motor emulator prototype.


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## Body

## 1. Introduction

Control algorithms of electrical drives are usually tested by the attachment of electrical motors. Experimental testing requires direct measuring by employing measurement instrumentation and sensors that would be complex, impractical, noise sensitive, and expensive. Traditionally these tests are performed on motor and inverter models under software simulation environments which are, in most cases, non-real-time and unable to exactly replicate real operational conditions.In order to provide a real-time verification of the implemented control algorithm and increase the realism of simulation, the control algorithm is tested while connected to a real-time emulator for the plant (induction motor and inverter) [1]. Due to their high capacities of executing in real-time complex algorithm, FPGA technology is a good candidate for this kind of RT emulator [2].For reasons of cost, simplicity, speeds and memory space, the real-time emulator of the induction motor is performed with the Euler’s shift discretization method and quantized with fixed point format [3].The robustness of the discretized algorithm is a critical issue in fixed-point format implementation. It is well known that, stable, closed-loop system may become unstable when the algorithm is implemented using a fixed-point processor due to finite-word-length effects. The fractional part precisions in fixed point are chosen to guarantee a minimum signal-to-noise ratio for finite-word-length quantization effects. The integer part is computed using norms [4].In an FPGA implementation, it is possible to use separate fixed-point format for each coefficient and signal in the algorithm. Hence, the use of FPGA allows maintaining a higher computational precision at critical points.In this paper, authors propose a real-time induction motor emulator designed in fixed point format for an FPGA implementation. The starting point is a continuous-time model. Discrete-time models are derived using the traditional shift form approximation. A study in terms of stability and finite-world-length effects is shown and a design technique for choosing the coefficient and signal bit widths is given [5, 6].To demonstrate the accurateness of the real-time induction motor emulator, a particular example is developed: the direct torque control (DTC) of an induction motor [7].The paper is organized as follows. The second section reminds the algorithmic study of a discrete-time induction motor model-based shift form approximation. Section3 gives an efficient methodology for choosing the finite fixed-point word length. Section 4 shows the FPGA-based architecture development and gives emulation results of the induction motor emulator with the DTC algorithm.


## 2. Discrete-Time Model Based on Shift Form Approximation

The block diagram of the complete system is outlined in Figure1 including the control scheme, the induction motor, and the power chain.Figure 1
Block diagram of the DTC technique.As it can be seen, the DTC algorithm is decomposed in three specific blocks.(i)
Transformation block, which is composed by two subalgorithms based on the direct Concordia transformation algorithm for the current and voltage three phases models.(ii)
Estimation block, which is composed by the calculation subalgorithms of flux(ϕs(d,q),ϕs), torque (Γe), and flux sector position. The discrete-time model of the flux subalgorithm is based on the shift form approximation:
(1)ϕs(d,q)(k+1)=ϕs(d,q)(k)+Tvs(d,q)-Tis(d,q).(iii)
command block, which is composed by a look-up table (LUT) corresponding to the switching function of the power inverter.In order to provide a real-time verification of the implemented control algorithm, the DTC is tested while connected to a real-time emulator for the induction motor and inverter.The induction machine is a nonlinear high-order system and for this reason complicated models must be used to control it. The dynamic behaviour of the induction motors can be described by a set of differential equations in a rotating reference frame with an angular velocity ofωλ. Moreover it is assumed that a stationary reference frame is fixed to the stator axis. The proposed model also assumes the classical decoupling between mechanical and electrical modes. It yields that under these assumptions, the state model of the induction motor (IM) is [8]
(2)ddty(t)=A(ω)y(t)+Bu(t),y(t)=Cx(t)+Du(t),
where, x=y=[isdisqϕrdϕrq],u=[usdusq] matrices A, B, C, and D are 4-by-4, 4-by-2, 4-by-4, and 4-by-2, respectively:
(3)A(ω)=[-γ0MsrσLsLrTrMsrσLsLrω0-γ-MsrσLsLrωMsrσLsLrTrMsrTr0-1Tr-ω0MsrTrω-1Tr],B=[1σLs001σLs0000],C=[1000010000100001],D=[00000000].T
r
=
L
r
/
R
r is the rotor time constant, σ is leakage coefficient with σ=1-Msr2/LsLr,γ=(Rs+Msr/LrTr)/σLs,   and ω  is the angular velocity.By means of, the general equation of the electromagnetic torque is transformed to an advantageous form:
(4)Γem=pMsrLr(ϕrdisq-ϕrqisd).The purpose of this section is to develop a computationally efficient discrete-time approximation of the continuous motor model operating in real time.The most used discretization method is based on Forward shift approximation [8]. The shift form approximation is given by
(5)ddt=(z-1)T,
where T is the sampling period.Introducing (5) in  yields
(6)xz(k+1)=Azxz(k)+Bzu(k),yz(k)=Cxz(k)+Du(k),
where
(7)xz(k)=yz(k)=[isd(k)isq(k)ϕrd(k)ϕrq(k)],Az=(I+AT),Bz=BT.The data flow graph (DFG) corresponding to the induction motor model is presented in Figure2. Coefficients ai depend on the parameters of the machine and are obtained for a per unit model.Figure 2
The DFG of induction motor model.The following lines show the different coefficients used for the per unit (PU) DTC algorithm(8)A=[-a10a2a3ω0-a1-a3ωa2a50a6-ω0a5ω-a6],
where, a1=γ, a2=(Msr/σLsLrTr)(ϕu/Iu), a3=(Msr/σLsLr)(vu/Iu), a4=1/σLs, a5=(Msr/Tr)(Iu/ϕu) and a6=1/Tr.The base values are determined from the maximal values by using the following equations, whereIm, vm, and fm are, respectively, the phase maximal current, the phase to neutral maximal voltage, and the maximal frequency of the induction motor:
(9)Iu=2Im,vu=2vm,ϕu=vm2πfm.The solution of the continuous system is
(10)x(t)=eAtx(0)+∫0teA(t-τ)Bu(τ)dτ.And if we consider the solution at the instantkT, we obtain
(11)x(kT)=(eAT)kx(0)+∫0kTeA(kT-τ)Bu(τ)dτ.The solution at the instantkT to the system  is the following:
(12)xz(kT)=(I+AT)kxz(0)+T∑l=0k-1(I+AT)k-l-1Bu(lT).Therefore, the matrices that rule the continuous and discrete time systems are, respectively,eAT and (I+AT), and, consequently, the continuous and discrete time systems will be described by the eigenvalues or the poles of these matrices.The poles of the matrixeAT  are λ=eβT, β being a pole of the matrix A of the continuous time system; the poles of the matrix (I+AT) are (λ=1+βT).In this study, a low power induction motor (1.5 kW) has been considered. The corresponding continuous-time model has four poles for electromagnetic model as illustrated below:(13)β1=(-46,86+0,5j)ω+11336-ω2+46iω2,β3=β1¯,β2=(-46,86+0,5j)ω-11336-ω2+46iω2,β4=β2¯.Let us suppose the following quadratic error function:(14)ε=(eβT-1-βT)(eβT-1-βT)*.Therefore, for sampling periodsT tending to zero the difference between eβT and (1+βT) becomes very small for each βi pole of A, and, consequently, it will optimize the resemblance between the time-domain response of the continuous-time and the discrete-time system.Discrete-time systems resulting from the shift form approximation are sometime unstable. It is possible, however, to select the sampling rate such that the discrete-time system is always stable when the corresponding continuous-time system is stable.  For the shift form realization, the stability domain is located inside the unit circle. Therefore, az-domain pole is stable if its module is less than one:
(15)|βiT+1|<1.Therefore, the most criticalz-domain pole corresponds to the s-domain pole having the greatest module. The pole β1 has the greatest module as function of ω.The locations of poles of the motor for different sampling rate values are shown in Figure3. It can be seen that for high sampling rate, the poles become very close to one. This can be problematic, particularly when finite precision formats are considered.Figure 3
Z-domain pole location of the motor model as function of the sampling frequency.


## 3. Efficient Methodology for Choosing the Word Length of Coefficients and Variables

The following methodology is developed for choosing each coefficient and variable bit width.


### 3.1. Representation of Coefficients

When the model is implemented in fixed-point format, each coefficientak must be given a finite-precision representation composed by an integer and fractional part. Each part is estimated separately.The integer part position for a coefficientak must be estimated by taking the base 2 logarithm of the maximum coefficient:
(16)Bint=⌊log2|ak|⌋+1,
where ⌊x⌋ rounds x to the nearest integer less than or equal to x.The fractional part must be determined by the maximum allowable perturbation of the coefficient from its ideal infinite-precision value. This can be achieved by computing the quantized parameter deviation or sensitivity and the stability margin. The angular velocity is selected to be the worst-case value. By means of Figure3, for pole λ1 and its conjugate, ω is fixed to the maximal value and for pole λ2 and its conjugate ω is equal to zero.Let{a^k} be the quantized parameter set consisting of all quantized coefficients of the state matrix Az. When the model is implemented in fixed-point format, each coefficient of the {ak} set is perturbed:
(17){Δak=a^k-ak}.Due to the finite-word-length effects, eachΔak perturbation is bounded by
(18)|Δak|≤2-BF,
where BF is the number of bits of the fractional part.Due to the perturbation{Δak}  each pole  λi[(ak)] is moved to λ^i=λi[Az(ak+Δak)] and it follows from a first-order approximation that the deviation can be computed with
(19)Δλi=λ^i-λi=∑k=1N∂λi∂akΔak,
where N is the number of modified parameters  (Δak≠0).As an example, for polesλ2  and  λ4, the worst-case deviation is obtained with ω=0. Then, the expression of deviation
(20)Δλ2=Δλ4=∂λ2∂a1Δa1+∂λ2∂a2Δa2+∂λ2∂a5Δa5+∂λ2∂a6Δa6
with,  ∂λ2/∂a1=-∂λ2/∂a6=-(T/2)(1+(a1-a6)/(a1-a6)2+4a5a2) and   ∂λ2/∂a2=(a2/a5)(∂λ2/∂a5)=-(T/2)(2a5/(a1-a6)2+4a5a2).The quantized poleλ^i may be outside the unit circle, especially with high sampling rate; thus, it is critical to know when the finite-word-length error leads to instability. This means to determine how close λi[(ak)] are to the unit circle.  Let us consider the following related measure for each pole:
(21)|∑k=1N(∂λi/∂ak)Δak1-|λi(ak)||<ε,
where 1-|λi(ak)| is called the stability margin of the i th pole and ε is a prescribed maximum allowable percent change in pole location relative to the stability margin.Assuming that all coefficients have the same word-length fractional part, thenΔak=Δa∀k∈{1,…,N}; it follows from inequality (21) that
(22)|Δa|<|1-|λi(ak)|||∑k=1N(∂λi/∂ak)|ε.From inequalities (22) and (18), the required fractional part word length can be derived as
(23)BF=⌊log2(|∑k=1N(∂λi/∂ak)||1-|λi(ak)||1ε)⌋+1.For the studied motor, settingε=5% and T=100 μs, the conditions (23) yield 19 bits for fractional part word length for A matrix coefficients.


### 3.2. Representation of Signals

The next step in the fixed-point motor model implementation is to estimate the format for each signal. An incremental methodology is used to determine the appropriate representation for the state variables. As shown in Figure4, the first step is to find transfer function from each input and the appropriate signal in the DFG. Then the dynamic range (maximum amplitude) of each signal is carried out by using l∞ and l1 norms, and, thus, the integer word length range is identified. Finally, the fractional part word-length is estimated by analysis of the signal-to-quantization-noise ratio (SQNR) for each signal.Figure 4
Incremental methodology for signal representation.The dynamic range (maximum amplitude) of each signal of the DFG allows identifying their integer range.  In practice the maximal current supported by the motor as well as the maximal produced torque and fluxes is known. Therefore, for the per-unit motor model, these dynamic ranges are bounded by 1. Notice that the voltage inputs and the electrical velocity are also normalized. Thus, these dynamic ranges are all bounded by 1:(24)∥isd∥∞=∥isq∥∞=∥Γem∥∞=∥vsq∥∞=∥vsd∥∞=∥ω∥∞=∥ϕrd∥∞=∥ϕrq∥∞=1,
where ∥·∥∞ denotes the  the  l∞ norm, defined by
(25)∥x∥∞=maxk|x(k)|.Now considering internaly1andy2 signals of the DFG, one can see that
(26)y1(z)=a4vsd(z)+a3ϕrd(z)ω(z)+a1isd,y2(z)=a4vsq(z)+a3ϕrq(z)ω(z)+a1isq.Therefore, signalsy1 and y2 are bounded by the same quantity:
(27)∥y1∥∞=∥y2∥∞≤|a4|+|a1|+|a2|.The integer part word length of all the signals is then estimated by taking the base 2 logarithm of the range bound. Table1 illustrates the signal range bounds and the corresponding integer part word length.Table 1
Range bounds for the motor model signals.
Signal
Range bound
Integer size
v
s
d
,
v
s
q
,
Γ
em
,
ω
,
i
s
d
,
i
s
q
,
ϕ
r
d
,
ϕ
r
q
1
1
y
1
,
y
2
1.03
2The fractional part word length is estimated by analyzing the signal-to-quantization-noise ratio (SQNR) for each signal [9]. The SQNR is measured in decibels as
(28)SQNR=10log10(σsignal2σnoise2).There are two possible sources of quantization noise in the induction motor emulator implementation, namely:(i)
the noise introduced by the limited resolution of a possible control technique, producing an input noise varianceσi2,(ii)
the truncation noise which is introduced when products or sums are quantized. This noise propagates through the emulator and appears at outputs.It is assumed that the quantization noise has the following properties.(i)
Each quantization noise source is a stationary white noise process.(ii)
Each noise source is uncorrelated with all other noise sources and the input of the system.(iii)
The error resulting from quantization can then be modeled as a random variable uniformly distributed over the appropriate error range. Therefore, the noise variance due to truncation is(29)σt2=2-2B12,where B is the fractional part word length.To investigate the noise propagation, a noise quantization model of the induction motor emulator is developed in Figure5. The addition is performed without truncation. The quantization is performed after each multiplication; the quantization noise resulting from N multiplications is therefore N-times higher than the one generated by a single multiplication. It yields that the variances of noise et1 and et2 are
(30)σt12=σt42=42-2Ba12,σt22=32-2Bb12.Figure 5
An additive noise model for the truncation and control technique noise through the induction motor model.The output noise variances can be estimated using the matrix transfer function from the input vectoru(k)=[et1(k),et1(k),et2(k),et2(k)] to the output vector  y(k)=[fi(k),fi(k),fϕ(k),fϕ(k)]. Using matrix notation in (5), the transfer function matrix response is
(31)Hv→ϕ,i(z)=D′+C(zI-Az)-1B′=[H11(z)H12(z)H13(z)H14(z)-H12(z)H11(z)-H14(z)H13(z)H31(z)H32(z)H33(z)H34(z)-H32(z)H31(z)-H34(z)H33(z)],
where
(32)B′=[a40000a40000100001],D′=[0000000000000000].Lethx→y(k) denote the impulse response from input x to output y for a linear system. Assuming that the input signal has a maximal value xmax, the output y must be bounded [10] so that
(33)∥y∥∞≤xmax∥hx→y∥1,
where ∥·∥1 denotes the l1 norm, defined by ∥x∥1=∑k=0∞|x(k)|.Using (31) and (33), the variances of resulting output noises are governed by these bounds [11]:
(34)∥σfi2∥∞≤(σt12+σi2)(∥H11(z)∥1+∥H12(z)∥1)+(σt22)(∥H13(z)∥1+∥H14(z)∥1),∥σfϕ2∥∞≤(σt12+σi2)(∥H31(z)∥1+∥H32(z)∥1)+(σt22)(∥H33(z)∥1+∥H34(z)∥1).Each coefficient∥Hij(z)∥1 is computed to have a maximal value as function of electrical velocity ω:
(35)∥Hij(z)∥1=maxω∥Hij(z,ω)∥1.Thel1 norms of discrete-time impulse responses corresponding to these transfer functions are computed approximately by finite sums. Figure 6 shows the impulse response for each coefficient of the matrix  Hv→ϕ,i(z). 								(36)∥σfi2∥∞≤96972-2B12+1246(σi2),(37)∥σfϕ2∥∞≤22752-2B12+115(σi2)Figure 6
Impulse response of the matrixHv→ϕ,i with sample period T=100 μs.Assuming that all signals have the same word length, the first inequality gives the worst-case variance error and therefore the fractional part word length will be selected taking into account this condition.The variances of the sinusoidal input and output signals of the induction motor emulator are expressed in terms of the root mean square. Hence (18) gives
(38)σsignal2=signalrms2=12.Assume that(39)σi2=2-2Bi12,
where  Bi  is the fractional part word length of the input voltage. The resolution is strongly dependent on the PWM one.Substituting (38) and (28) in (36) gives this condition:
(40)SQNRfi≥-10log10(1628.2-2B+208.2-2Bi).Figure7 shows the SQNR as function of the fractional part word length for different Bi bits.  With a 10-bit Bi word-length, we obtain SQNR=75db for 18-bit B wordlength.Figure 7
SQNR as function of the signal fractional part word length.


## 3.1. Representation of Coefficients

When the model is implemented in fixed-point format, each coefficientak must be given a finite-precision representation composed by an integer and fractional part. Each part is estimated separately.The integer part position for a coefficientak must be estimated by taking the base 2 logarithm of the maximum coefficient:
(16)Bint=⌊log2|ak|⌋+1,
where ⌊x⌋ rounds x to the nearest integer less than or equal to x.The fractional part must be determined by the maximum allowable perturbation of the coefficient from its ideal infinite-precision value. This can be achieved by computing the quantized parameter deviation or sensitivity and the stability margin. The angular velocity is selected to be the worst-case value. By means of Figure3, for pole λ1 and its conjugate, ω is fixed to the maximal value and for pole λ2 and its conjugate ω is equal to zero.Let{a^k} be the quantized parameter set consisting of all quantized coefficients of the state matrix Az. When the model is implemented in fixed-point format, each coefficient of the {ak} set is perturbed:
(17){Δak=a^k-ak}.Due to the finite-word-length effects, eachΔak perturbation is bounded by
(18)|Δak|≤2-BF,
where BF is the number of bits of the fractional part.Due to the perturbation{Δak}  each pole  λi[(ak)] is moved to λ^i=λi[Az(ak+Δak)] and it follows from a first-order approximation that the deviation can be computed with
(19)Δλi=λ^i-λi=∑k=1N∂λi∂akΔak,
where N is the number of modified parameters  (Δak≠0).As an example, for polesλ2  and  λ4, the worst-case deviation is obtained with ω=0. Then, the expression of deviation
(20)Δλ2=Δλ4=∂λ2∂a1Δa1+∂λ2∂a2Δa2+∂λ2∂a5Δa5+∂λ2∂a6Δa6
with,  ∂λ2/∂a1=-∂λ2/∂a6=-(T/2)(1+(a1-a6)/(a1-a6)2+4a5a2) and   ∂λ2/∂a2=(a2/a5)(∂λ2/∂a5)=-(T/2)(2a5/(a1-a6)2+4a5a2).The quantized poleλ^i may be outside the unit circle, especially with high sampling rate; thus, it is critical to know when the finite-word-length error leads to instability. This means to determine how close λi[(ak)] are to the unit circle.  Let us consider the following related measure for each pole:
(21)|∑k=1N(∂λi/∂ak)Δak1-|λi(ak)||<ε,
where 1-|λi(ak)| is called the stability margin of the i th pole and ε is a prescribed maximum allowable percent change in pole location relative to the stability margin.Assuming that all coefficients have the same word-length fractional part, thenΔak=Δa∀k∈{1,…,N}; it follows from inequality (21) that
(22)|Δa|<|1-|λi(ak)|||∑k=1N(∂λi/∂ak)|ε.From inequalities (22) and (18), the required fractional part word length can be derived as
(23)BF=⌊log2(|∑k=1N(∂λi/∂ak)||1-|λi(ak)||1ε)⌋+1.For the studied motor, settingε=5% and T=100 μs, the conditions (23) yield 19 bits for fractional part word length for A matrix coefficients.


## 3.2. Representation of Signals

The next step in the fixed-point motor model implementation is to estimate the format for each signal. An incremental methodology is used to determine the appropriate representation for the state variables. As shown in Figure4, the first step is to find transfer function from each input and the appropriate signal in the DFG. Then the dynamic range (maximum amplitude) of each signal is carried out by using l∞ and l1 norms, and, thus, the integer word length range is identified. Finally, the fractional part word-length is estimated by analysis of the signal-to-quantization-noise ratio (SQNR) for each signal.Figure 4
Incremental methodology for signal representation.The dynamic range (maximum amplitude) of each signal of the DFG allows identifying their integer range.  In practice the maximal current supported by the motor as well as the maximal produced torque and fluxes is known. Therefore, for the per-unit motor model, these dynamic ranges are bounded by 1. Notice that the voltage inputs and the electrical velocity are also normalized. Thus, these dynamic ranges are all bounded by 1:(24)∥isd∥∞=∥isq∥∞=∥Γem∥∞=∥vsq∥∞=∥vsd∥∞=∥ω∥∞=∥ϕrd∥∞=∥ϕrq∥∞=1,
where ∥·∥∞ denotes the  the  l∞ norm, defined by
(25)∥x∥∞=maxk|x(k)|.Now considering internaly1andy2 signals of the DFG, one can see that
(26)y1(z)=a4vsd(z)+a3ϕrd(z)ω(z)+a1isd,y2(z)=a4vsq(z)+a3ϕrq(z)ω(z)+a1isq.Therefore, signalsy1 and y2 are bounded by the same quantity:
(27)∥y1∥∞=∥y2∥∞≤|a4|+|a1|+|a2|.The integer part word length of all the signals is then estimated by taking the base 2 logarithm of the range bound. Table1 illustrates the signal range bounds and the corresponding integer part word length.Table 1
Range bounds for the motor model signals.
Signal
Range bound
Integer size
v
s
d
,
v
s
q
,
Γ
em
,
ω
,
i
s
d
,
i
s
q
,
ϕ
r
d
,
ϕ
r
q
1
1
y
1
,
y
2
1.03
2The fractional part word length is estimated by analyzing the signal-to-quantization-noise ratio (SQNR) for each signal [9]. The SQNR is measured in decibels as
(28)SQNR=10log10(σsignal2σnoise2).There are two possible sources of quantization noise in the induction motor emulator implementation, namely:(i)
the noise introduced by the limited resolution of a possible control technique, producing an input noise varianceσi2,(ii)
the truncation noise which is introduced when products or sums are quantized. This noise propagates through the emulator and appears at outputs.It is assumed that the quantization noise has the following properties.(i)
Each quantization noise source is a stationary white noise process.(ii)
Each noise source is uncorrelated with all other noise sources and the input of the system.(iii)
The error resulting from quantization can then be modeled as a random variable uniformly distributed over the appropriate error range. Therefore, the noise variance due to truncation is(29)σt2=2-2B12,where B is the fractional part word length.To investigate the noise propagation, a noise quantization model of the induction motor emulator is developed in Figure5. The addition is performed without truncation. The quantization is performed after each multiplication; the quantization noise resulting from N multiplications is therefore N-times higher than the one generated by a single multiplication. It yields that the variances of noise et1 and et2 are
(30)σt12=σt42=42-2Ba12,σt22=32-2Bb12.Figure 5
An additive noise model for the truncation and control technique noise through the induction motor model.The output noise variances can be estimated using the matrix transfer function from the input vectoru(k)=[et1(k),et1(k),et2(k),et2(k)] to the output vector  y(k)=[fi(k),fi(k),fϕ(k),fϕ(k)]. Using matrix notation in (5), the transfer function matrix response is
(31)Hv→ϕ,i(z)=D′+C(zI-Az)-1B′=[H11(z)H12(z)H13(z)H14(z)-H12(z)H11(z)-H14(z)H13(z)H31(z)H32(z)H33(z)H34(z)-H32(z)H31(z)-H34(z)H33(z)],
where
(32)B′=[a40000a40000100001],D′=[0000000000000000].Lethx→y(k) denote the impulse response from input x to output y for a linear system. Assuming that the input signal has a maximal value xmax, the output y must be bounded [10] so that
(33)∥y∥∞≤xmax∥hx→y∥1,
where ∥·∥1 denotes the l1 norm, defined by ∥x∥1=∑k=0∞|x(k)|.Using (31) and (33), the variances of resulting output noises are governed by these bounds [11]:
(34)∥σfi2∥∞≤(σt12+σi2)(∥H11(z)∥1+∥H12(z)∥1)+(σt22)(∥H13(z)∥1+∥H14(z)∥1),∥σfϕ2∥∞≤(σt12+σi2)(∥H31(z)∥1+∥H32(z)∥1)+(σt22)(∥H33(z)∥1+∥H34(z)∥1).Each coefficient∥Hij(z)∥1 is computed to have a maximal value as function of electrical velocity ω:
(35)∥Hij(z)∥1=maxω∥Hij(z,ω)∥1.Thel1 norms of discrete-time impulse responses corresponding to these transfer functions are computed approximately by finite sums. Figure 6 shows the impulse response for each coefficient of the matrix  Hv→ϕ,i(z). 								(36)∥σfi2∥∞≤96972-2B12+1246(σi2),(37)∥σfϕ2∥∞≤22752-2B12+115(σi2)Figure 6
Impulse response of the matrixHv→ϕ,i with sample period T=100 μs.Assuming that all signals have the same word length, the first inequality gives the worst-case variance error and therefore the fractional part word length will be selected taking into account this condition.The variances of the sinusoidal input and output signals of the induction motor emulator are expressed in terms of the root mean square. Hence (18) gives
(38)σsignal2=signalrms2=12.Assume that(39)σi2=2-2Bi12,
where  Bi  is the fractional part word length of the input voltage. The resolution is strongly dependent on the PWM one.Substituting (38) and (28) in (36) gives this condition:
(40)SQNRfi≥-10log10(1628.2-2B+208.2-2Bi).Figure7 shows the SQNR as function of the fractional part word length for different Bi bits.  With a 10-bit Bi word-length, we obtain SQNR=75db for 18-bit B wordlength.Figure 7
SQNR as function of the signal fractional part word length.


## 4. FPGA-Based Induction Motor Emulator

### 4.1. System Architecture

The induction motor emulator is implemented using modular and standard design principles on a Xilinx Development kit, which contain a FPGA from SPARTAN III family, the XC3s200.The emulator module requires important hardware resource. Therefore, the corresponding architecture is optimized in terms of consumed resources by the AAA methodology [12] which leads to only 3 multipliers.As in [13], the proposed architecture consists in a control unit and a data path. The control unit generates a suitable timing schedule to control the data path and other local sequencers. Figure 8 depicts the proposed system architecture.Figure 8
Proposed system architecture.After the specification of the algorithm with data wordlength and sampling frequency, we propose to develop a modular architecture for the induction motor model to be implemented through an FPGA device.


### 4.2. System Architecture under Test in Open Loop

Figure9 depicts the proposed system architecture. It includes a set of dedicated modules to guarantee the real-time hardware in the loop (HIL) simulation.Figure 9
Proposed system architecture.The functional blocks of the global architecture are listed below.(i)
The UART (Universal Asynchronous Receiver Transmitter) module that provides a serial communication between the host PC and the implemented architecture. The UART allows both reconfigurations in real time of the induction motor model by tuning its coefficients and data acquisition to be visualized on the PC. To solve the dialogs between the UART implemented on the FPGA board and the PC, MATLAB's serial port interface is used.(ii)
The input voltage stimuli module. It generates three digital values, which represent the three phases voltage. One can control the output waves amplitude and frequency in real time via the UART module. This module is used to test the induction motor (IM) module.(iii)
The IM module that requires the most important hardware resources. It implements the induction motor model.(iv)
The global sequencer module. It represents the control unit that generates a suitable timing schedule to control data path and other local sequencers.The real-time simulation results presented in Figure10 with 10 kHz sampling frequency show a slight difference between the torque produced by the implemented motor model architecture and the simulated torque under MATLAB environment under continuous-time conditions.   This difference is too small to affect the performance of the real-time model.Figure 10
Simulated torque and torque produced by the implemented model on FPGA during a start-up.


### 4.3. System Architecture under Test with DTC Algorithm

The DTC is a well-known induction motor control strategy [7]. This control algorithm is selected to be tested with the real time induction motor model. The implemented architecture of the DTC control algorithm has been tested with the induction motor model architecture in real time. Figure 11 illustrates the proposed real time test bed. It includes a set of dedicated modules to guarantee a real-time simulation.(i)
The UART (Universal Asynchronous Receiver Transmitter) module that provides a serial communication between the host PC and the implemented architecture.(ii)
The stimuli module. It generates the references for the DTC control algorithm.Figure 11
Real-time test bed.The torque and the stator flux are collected from the serial interface and visualized under Matlab-Simulink environment. Figure12 illustrates the real-time emulation results.Real-time simulation results, obtained with DTC algorithm and the IM emulator: (a) steady-state stator flux vector locus, (b) estimated torque response to a step control from 0 N·m to 4 N·m.T = 100 μs, ω=500 rpm and Φs* = 1.15 wb.
(a)
(b)


## 4.1. System Architecture

The induction motor emulator is implemented using modular and standard design principles on a Xilinx Development kit, which contain a FPGA from SPARTAN III family, the XC3s200.The emulator module requires important hardware resource. Therefore, the corresponding architecture is optimized in terms of consumed resources by the AAA methodology [12] which leads to only 3 multipliers.As in [13], the proposed architecture consists in a control unit and a data path. The control unit generates a suitable timing schedule to control the data path and other local sequencers. Figure 8 depicts the proposed system architecture.Figure 8
Proposed system architecture.After the specification of the algorithm with data wordlength and sampling frequency, we propose to develop a modular architecture for the induction motor model to be implemented through an FPGA device.


## 4.2. System Architecture under Test in Open Loop

Figure9 depicts the proposed system architecture. It includes a set of dedicated modules to guarantee the real-time hardware in the loop (HIL) simulation.Figure 9
Proposed system architecture.The functional blocks of the global architecture are listed below.(i)
The UART (Universal Asynchronous Receiver Transmitter) module that provides a serial communication between the host PC and the implemented architecture. The UART allows both reconfigurations in real time of the induction motor model by tuning its coefficients and data acquisition to be visualized on the PC. To solve the dialogs between the UART implemented on the FPGA board and the PC, MATLAB's serial port interface is used.(ii)
The input voltage stimuli module. It generates three digital values, which represent the three phases voltage. One can control the output waves amplitude and frequency in real time via the UART module. This module is used to test the induction motor (IM) module.(iii)
The IM module that requires the most important hardware resources. It implements the induction motor model.(iv)
The global sequencer module. It represents the control unit that generates a suitable timing schedule to control data path and other local sequencers.The real-time simulation results presented in Figure10 with 10 kHz sampling frequency show a slight difference between the torque produced by the implemented motor model architecture and the simulated torque under MATLAB environment under continuous-time conditions.   This difference is too small to affect the performance of the real-time model.Figure 10
Simulated torque and torque produced by the implemented model on FPGA during a start-up.


## 4.3. System Architecture under Test with DTC Algorithm

The DTC is a well-known induction motor control strategy [7]. This control algorithm is selected to be tested with the real time induction motor model. The implemented architecture of the DTC control algorithm has been tested with the induction motor model architecture in real time. Figure 11 illustrates the proposed real time test bed. It includes a set of dedicated modules to guarantee a real-time simulation.(i)
The UART (Universal Asynchronous Receiver Transmitter) module that provides a serial communication between the host PC and the implemented architecture.(ii)
The stimuli module. It generates the references for the DTC control algorithm.Figure 11
Real-time test bed.The torque and the stator flux are collected from the serial interface and visualized under Matlab-Simulink environment. Figure12 illustrates the real-time emulation results.Real-time simulation results, obtained with DTC algorithm and the IM emulator: (a) steady-state stator flux vector locus, (b) estimated torque response to a step control from 0 N·m to 4 N·m.T = 100 μs, ω=500 rpm and Φs* = 1.15 wb.
(a)
(b)


## 5. Conclusions

This work has presented an optimized fixed-point format induction motor model intended for real-time simulation and emulation. With the analysis of the coupling between the sample rate and the data word length, this work has provided a theoretical guideline to find the optimal hardware implementation. The proposed architecture of the model has been successfully verified by the development and implementation of a real-time test bed that contains the AC-motor model and a DTC control algorithm.The methodology for estimating the appropriate data word length may be applied to other various discrete-time system realizations.



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*Source: 409671-2012-10-31.xml*