# Optimization and Characterization of CMOS for Ultra Low Power Applications

Authors: Mohd. Ajmal Kafeel; S. D. Pable; Mohd. Hasan; M. Shah Alam
Journal: Journal of Nanotechnology
 (2015)

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## Abstract

Aggressive voltage scaling into the subthreshold operating region holds great promise for applications with strict energy budget. However, it has been established that higher speed superthreshold device is not suitable for moderate performance subthreshold circuits. The design constraint for selectingV
t
h and T
O
X is much more flexible for subthreshold circuits at low voltage level than superthreshold circuits. In order to obtain better performance from a device under subthreshold conditions, it is necessary to investigate and optimize the process and geometry parameters of a Si MOSFET at nanometer technology node. This paper calibrates the fabrication process parameters and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length. Thereafter, the calibrated device for superthreshold application is optimized for better performance under subthreshold conditions using TCAD simulation. The device simulated in this work shows 9.89% improvement in subthreshold slope and 34% advantage in I
O
N
/
I
O
F
F ratio for the same drive current.


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## Body

## 1. Introduction

While universal scaling trends of CMOS technology are mostly focused on achieving higher speed, selection of device fabrication process parameters for ULP applications with lower operating frequencies is still under exploration [1–5]. It has been shown recently that subthreshold circuits are significantly benefitted by optimizing the device parameters [3]. Process and geometry parameters of superthreshold circuits are largely governed by the different leakage currents and, hence, its static power dissipation [6–10]. However, due to lower supply bias, gate leakage current, DIBL, and punchthrough effects are negligible under subthreshold conditions [11]. Therefore, to some extent, design constraint for selecting V
t
h and T
O
X becomes more flexible in case of device operated under subthreshold regime.For superthreshold devices, scaling ofV
t
h is restricted by the amount of static leakage, mainly subthreshold leakage current in nanometer technology nodes [2, 3]. Such a high V
t
h device will give significant performance penalty under subthreshold conditions due to lower subthreshold leakage current, which is used to perform necessary digital computations. Hence, the choice of V
t
h is a tradeoff between speed and leakage power dissipation in case of superthreshold applications. However, in subthreshold region, lower static leakage power dissipation due to scaled V
D
D even below V
t
h allows further reduction in V
t
h to enhance the speed.Along with subthreshold leakage current, gate leakage is also a major hurdle in aggressive scaling ofT
O
X to obtain better control over the channel for a superthreshold device [2, 3]. In general, T
O
X scales down slowly from 130 nm technology node to keep minimum gate leakage current in case of high frequency applications [2] due to higher supply bias. However, it degrades “S” and causes lowering of I
O
N
/
I
O
F
F ratio. In subthreshold operating region due to lower V
D
D, reducing T
O
X will not significantly increase the gate leakage current [11]. In addition, transistor input capacitance is smaller under subthreshold conditions than the superthreshold regime [3]. Hence, more aggressive scaling of T
O
X is possible under subthreshold conditions to achieve higher speed and lower energy consumption.In addition, it is an established fact that a superthreshold device in nanometer technology nodes requires halo and retrograde doping to suppress short channel effects. Halo and retrograde wells are used to reduce DIBL and punchthrough effects and to controlV
t
h of the device independent of its subthreshold slope. However, in subthreshold regime, due to supply bias lower than V
t
h, DIBL and punchthrough effects are negligible. Hence, subthreshold device characteristics are less sensitive to halo and retrograde doping. Therefore, this paper investigates the design of a subthreshold NMOS device at 45 nm technology node with better subthreshold slope and higher drive current capability.


## 2. Calibration of a MOS Device

TransistorsL
g and T
O
X, as shown in Figure 1, primarily set the transistor performance parameters [12]. Authors in [13] fabricated the optimized 35 nm gate length NMOS device with 676 μA/μm drive current, subthreshold slope = 86 mV/dec., and I
O
F
F = 100 nA/μm at V
D
D = 0.85 V. This device was fully optimized for short channel effect suppression and parasitic resistance reduction. In order to obtain an optimum subthreshold device, there is a need first to design a superthreshold device with better performance at 45 nm technology node. The physical dimensions of a 35 nm NMOS device, fabricated by Toshiba and listed in Table 1, are considered for simulation purposes [13]. The poly-Si thickness is 150 nm, while the distance of S/D contact to gate is 52 nm. In simulation, the source and drain electrodes are treated as ohmic contacts. The resulting SDE junction depth is 15 nm for NMOS and 28 nm for PMOS. Lower T
O
X for PMOS causes more drive current in PMOS which is comparable to NMOS. Lower T
O
X in case of PMOS will cause more vertical electric field in channel which further increases subthreshold drive current in PMOS.Table 1
Physical dimensions used for 35 nm gate length MOSFET [8].
Gate length
T
OX
(nm)
Junction depth (nm)
Poly silicon thickness (nm)
Spacer thickness
nFET
35
1–1.2
20
150
52.5
pFET
35
0.95
33
150
52.5Figure 1
Cross-section drawing of a CMOS transistor.Furthermore, channel doping and halo doping are tuned to calibrate our device with the NMOS fabricated in [13] and corresponding electrical characteristics are listed in Table 2. At first, the simulation project matches the published process details of real structure as accurately as possible. It includes the physical parameters as given in Table 1. The calibrated 45 nm device structure, as shown in Figure 2, is obtained with physical parameters as listed in Table 1. The drain current versus gate voltage (I
D
S-V
G
S) and drain current versus drain voltage are the primary targets for calibration in device simulations. The calibration starts by adjusting the electrostatic to match subthreshold slope, drain current, and I
O
F
F. Finally, device measurements are matched to the previously published calibrated device [13] by doping profiles adjustment so as to achieve the desired I-V characteristics. The flowchart of the calibration process is given in Figure 3 [14]. For process calibration, tuned mobility parameters are used. The matched calibrated electrical characteristics are then obtained through TCAD simulation. The important figures of merit, extracted from simulation, are then compared with the experimental data in Table 2. This is the starting point for investigating the effect of physical and process parameters under subthreshold conditions.Table 2
Simulation and experimental performance parameters.
Toshiba (experimental)
This work (simulation)
n-MOSFET
p-MOSFET
n-MOSFET
p-MOSFET
I
ON
(μA/μm)
676
272
676
300
I
OFF
(nA/μm)
100
100
106
110
SS (mV/dec)
86.1
92.3
83.88
90.56Figure 2
Simulation structure of 45 nm NMOS.Figure 3
Flowchart for calibration methodology used in simulation [8].


## 3. Effect of Oxide Thickness and Channel Length on Device Parameters

As seen in Section1, one of the key methods to enable gate length scaling over the past several generations is to scale the T
O
X [15]. Therefore, T
O
X scaling has been instrumental in controlling short channel effects as MOS gate dimensions have been reduced. This improves the control of the gate electrode over the channel, which enables both shorter channel lengths and higher performance. As T
O
X scales down, increase in gate leakage current becomes significant below 65 nm technology node as shown in Figure 4. In addition, gate capacitance also increases significantly with T
O
X scaling for superthreshold circuits. To reduce the increased gate leakage, a gate dielectric with higher dielectric constant is introduced below 45 nm [16]. However, due to lower V
D
D, gate leakage component is negligible under subthreshold as compared to superthreshold conditions.Figure 4
Effect ofT
O
X scaling and gate leakage versus Intel technology [10].The effective gate capacitanceC
g of a transistor is dominated by intrinsic depletion and parasitic capacitances, which are strongly dependent on T
O
X [17]. In energy constraint subthreshold design, circuits are normally optimized to enhance the speed [18, 19]. To reduce these capacitances, higher value of T
O
X is preferred. However, it reduces the gate control over the channel; hence, it results in higher value of “S
.” Hence, for moderate speed application with some loss of energy, significant improvement in speed can be achieved. In addition, as shown in Figure 5, under subthreshold conditions (V
G
S
<
0.3), T
O
X scaling does not increase C
g significantly contrary to superthreshold operating region. The effective channel length also determines subthreshold leakage current and V
t
h.Figure 5
Gate capacitance as a function ofV
G
S for 45 nm NMOS.Therefore, this section examines the joint impact ofT
O
X and L
g scaling on the device performance. The calibrated NMOS structure, as shown in Figure 2, is simulated to investigate the effect of L
g and T
O
X on the characteristics of NMOS device under subthreshold conditions at V
D
D = 150 mV. L
g and T
O
X are varied from 30 nm to 50 nm and 0.6 nm to 1.3 nm respectively. The values of halo doping and substrate doping are kept constant at 1.6
e
+
19/cm3 and 2.2
e
+
18/cm3, respectively.It is observed from Figure6 that an increase in L
g and a decrease in T
O
X reduce “S” significantly. Increasing L
g from 35 to 50 nm reduces “S” by approximately 6 mV/decade for different values of T
O
X. It is clear from Figure 7 that an increase in channel length has negligible effect on the gate capacitance. Therefore, longer channel length will result in lower power dissipation and better performance because of improved “S
.” Also, reducing T
O
X from 1 to 0.8 nm at L
g = 35 nm reduces “S” by 2.3 mV/decade and increases C
g by 12%. Therefore, careful selection of T
O
X is required so that the improvement in “S” will not be masked by the increase in C
g and hence the power dissipation (C
g
V
D
D
2f). However, from Figure 7, it is evident that T
O
X is having large impact on C
g as compared to L
g. In addition, it has been evident that the increase in L
g reduces I
O
N and I
O
F
F current by 14x and 22x, respectively, at T
O
X = 1 nm. Therefore, I
O
N
/
I
O
F
F ratio increases by 1.36x at T
O
X=1 nm with the increase in L
g. This also reduces the power consumption. From Figure 8, optimum value of L
g can be obtained for better values of “S” and I
O
N
/
I
O
F
F ratio for different values of T
O
X.Figure 6
Subthreshold slope as a function ofL
g and T
O
X for 45 nm NMOS.Figure 7
Gate capacitance as a function ofL
g and T
O
X for 45 nm NMOS.Figure 8
Subthreshold slope andI
O
N
/
I
O
F
F as a function of L
g and T
O
X for 45 nm NMOS.From the above analysis, it can be concluded that, for energy efficient ULP circuits, larger value ofL
g can be used to reduce the energy consumption due to lower “S” and higher I
O
N
/
I
O
F
F ratio. However, for higher performance ULP circuits, increase in L
g will significantly reduce the drive current and hence the speed. Therefore, higher value of L
g is not suitable for high performance ULP applications.


## 4. Effect of Doping Profile under Subthreshold Conditions

In scaled superthreshold transistors, halo and retrograde doping profiles are used to suppress short channel effects (SCE) like DIBL lowering and body punchthrough [20]. However, in subthreshold region, SCE plays a minor role as compared to superthreshold regime because of lower V
D
D [11]. Hence, it has been established that halo and retrograde doping are less effective under subthreshold conditions. Also low doping level can reduce the bottom junction capacitance. Therefore, it is important to investigate the effect of doping profile under subthreshold conditions in nanometer technology domain.It is observed from Figure9 that the reductions in substrate (N
s
u
b) and halo doping increase the drain current (I
s
u
b) significantly. The decrease in N
s
u
b doping concentration by 50% increases I
s
u
b by 3.5x. Also reducing N
h
a
l
o by 4x increases I
s
u
b by 2.25x. However, from Figure 10, it is observed that reducing N
s
u
b by 50% increases “S” by 0.7 mV/decade and I
O
F
F by 3.88x. Therefore, a trade-off is involved in improving the drive current, “S,” and I
O
F
F on reducing N
s
u
b doping concentration. Similar performance trend is observed by changing the halo doping concentration. Figures 11 and 12 show the drive current and subthreshold slope as a function of halo and substrate doping.Figure 9
Drain current as a function of channel doping for different halo doping.Figure 10
I
O
F
F as function of channel doping.Figure 11
Drain current as a function of halo doping.Figure 12
Subthreshold slope as a function of halo doping and channel doping.


## 5. Subthreshold Device Characterization

This section mainly targets improvement of the subthreshold slope so that energy consumption can be reduced [11]. The calibrated device is then tuned at optimum values of L
g, T
O
X, N
s
u
b, and N
h
a
l
o to achieve best subthreshold characteristics. Optimized device parameters from Section 4 are used to achieve better subthreshold slope under subthreshold conditions. Figure 13 shows the comparison of the subthreshold slope as a function of supply voltage for the conventional and the optimized device under subthreshold condition. As shown in Figure 13, the optimized device shows 9.89% improvement in subthreshold slope over the conventional device operated in subthreshold region. Also, as shown in Table 3, I
O
N
/
I
O
F
F ratio increases by 34% in case of optimized device for the same drive current. Since effect of DIBL is very small under subthreshold conditions this work has not considered the DIBL during optimization.Table 3
Comparison of performance parameters under subthreshold conditions.
Toshiba (experimental)
This work (simulation)
I
ON (μA/μm)
1.79
1.68
I
OFF (nA/μm)
32
19.9
SS (mV/dec)
82.58
74.41Figure 13
Subthreshold slope as a function of supply voltage.


## 6. Conclusion

The device designed for superthreshold circuits is not suitable for optimum subthreshold operation. This paper proposed new device process parameters to improve the subthreshold slope and to enhance the speed of subthreshold circuits. It has successfully concluded that optimizing the device for subthreshold region results in improvement in both the subthreshold slope and theI
O
N
/
I
O
F
F ratio. Hence, in order to obtain the better performance of device under subthreshold conditions, it is necessary to optimize the process and geometry parameters of Si-MOSFET at nanometer technology node due to relaxed constraint for different leakage currents and short channel effects.



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*Source: 395090-2015-12-22.xml*