# Applications of Wireless Communication in a New Dual Branch CTS Charge Pump Based on Employing Clock Matched Technology

Authors: Jiayang Li
Journal: Wireless Communications and Mobile Computing
 (2021)

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## Abstract

With the increase in communication requirements, new communication technologies and implementation methods have developed rapidly. The rise of emerging markets such as the Internet of Things, smart homes, smart cities, and wearables has promoted the development of wireless communication integrated circuits in the direction of monolithic, low energy consumption, and high energy efficiency. This paper proposes a new dual branch charge pump based on CTS charge pump with enhanced current drive capability and undesired charge transfer completely eliminated. Clock matched technology is proposed to completely eliminate undesired charge transfer caused by delay turn on and off of the auxiliary transistors in the traditional CTS charge pump. The current drive capability is enhanced by employing NMOS transistors with 2Vdd gate drive voltage, while traditional dual branch CTS charge pumps are based on PMOS with 1Vdd gate drive voltage. The output voltage ripple is also reduced resulting from a dual branch structure. Simulation results of output voltage gain and power efficiency for the proposed charge pump and other traditional charge pumps are provided. Comparisons are made to show the improvement of the proposed charge pump compared with other traditional charge pumps.


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## Body

## 1. Introduction

With Soc (system on chip) having been widely employed in electronic equipment in the recent decade, the blocks built in Soc are also significantly increased contributing to various power supply demands. A charge pump, a circuit consisting of switches and capacitors, becomes a preference in the application of nonvolatile memory [1], defect monitoring [2], energy harvesting [3], and so on resulting from its relatively high efficiency and integration simplicity compared with other step-up power converters such as the boost converter.The most basic charge pump circuit was proposed by Dickson [4]. However, the traditional Dickson charge pump suffers from severe voltage drop caused by diode-connected transistors in each stage. The voltage drop caused by diode-connected transistors can be significantly reduced by employing a charge transfer switch [5]. The first charge pump without voltage drop loss was proposed in [6] based on [5]. However, undesired charge transfer occurs in [5, 6] caused by the delay turn on and turn off of the auxiliary transistor with a nonideal clock signal, which reduces the power efficiency and output voltage gain. Some researchers designed dual branch charge pumps [7] based on [6] to reduce undesired charge transfer in traditional charge transfer switch charge pumps. However, undesired charge transfer still exists in [7], and conduction loss in [7] is increased caused by lower gate drive voltage contributing to lower power efficiency and output voltage gain.This paper proposes a new dual branch charge pump based on [5, 7] with no undesired charge transfer and increased gate drive voltage, contributing to higher power efficiency and voltage gain. The conduction loss is significantly decreased by employing NMOS with 2Vdd gate drive voltage compared with PMOS and 1Vdd gate drive voltage in [7]. Undesired charge transfer is eliminated by employing a nonoverlapping clock [8] and accurate time delay circuit [9]. Section 2 discusses the undesired charge transfer in traditional charge pumps including [6, 7]. Section 3 introduces the proposed charge pump. An optimized gate drive strategy for auxiliary transistors to completely eliminate undesired charge transfer is proposed in Section 4. The simulation result of the performance for the above charge pumps based on 0.18 μm technology is listed in Section 5. Section 6 is the conclusion of this paper.


## 2. Conventional Charge Pumps and Drawbacks

The Dickson charge pump proposed in [4] consists of diode-connected transistors and flying capacitors driving by clock signals. Figure 1(a) shows the schematic of N stage Dickson charge, while Figure 1(b) shows the clock signal for this N stage Dickson charge pump. The voltage drop loss in each stage approximately equals to the threshold voltage of the diode-connected transistor. The clock signal pumps the bottom plane of the flying capacitor and helps increase the voltage of the top plane to charge the next stage. The output voltage expression is given in [10]:
(1)Vout=N+1VDD−VT−NILC·f,where Vout is the output voltage, N is the number of pumping stages, VT is the threshold voltage of the diode connect transistor, f is the clock frequency, C is the capacitor, and IL is the output current. According to the expression, there is a voltage drop in each pumping stage which significantly reduces the output voltage gain.Figure 1
(a)N stage Dickson charge pump; (b) clock signal for Dickson charge pump.
(a)(b)The schematic of the PMOS CTS charge pump proposed in [6] is shown in Figure 2(a). With the help of auxiliary of PN pair, there is no voltage drop in each pumping stage. However, charge transfer from high voltage node to low voltage node reduces the voltage gain and power efficiency. The following is the analysis of how undesired charge transfer occurs in the CTS charge pump. Let us take stage three as an example. Assume ϕ1 is low and ϕ2 is high, the voltage of node 1 is 1Vdd, and the voltage of node 2 and node 3 is 3Vdd. By this way, MN3 is on and MP3 is off, and M3 is on. Charge transfers from node 2 to node 3 occur in this period of time. When ϕ2 transfer from 1Vdd to zero, the voltage of node 2 transfers from 3Vdd to 2Vdd. MP3 will turn on since the voltage of node 2 reaches 3Vdd−Vthp while MN3 will not turn off until the voltage of node 1 reached 2Vdd−Vthn. Undesired charge transfer from node 3 to node 1 occurs in this period of time. Meanwhile, if ϕ2 is low and ϕ1 is high, when ϕ1 transfer from 1Vdd to zero, MN3 starts to turn on since voltage of node 1 reached 2Vdd−Vthn. This also contributes to undesired charge transfer from node 3 to node 1. What is more, the simultaneous turn on of MP3 and MP3 also causes M3 turning on, resulting in reverse current from node 3 to node 2.Figure 2
(a) Schematic of traditional CTS charge pump; (b) undesired charge transfer in traditional CTS charge pump.
(a)(b)The charge pump proposed in [7] is aimed at reducing the undesired charge transfer. Figure 3(a) shows the CP2 charge pump proposed in [7]. We use stage 3 to analyze the charge transfer again. When ϕ2 is high and ϕ1 is low, the voltage of node B4 and node B3 is about 4Vdd; then, MPA3 turns off. The voltage of node A2 is 3Vdd while the node of B2 is 2Vdd; then, MNA3 turns on. In the clock transfer period, MPA3 turns on since VB4−VB3>∣Vthp∣, while MNA3 will not turn off until VA2−VB2<∣Vthn∣. The only condition that CP2 charge pump eliminates undesired charge transfer is that Vthn+Vthp=Vdd. Otherwise, undesired charge transfer happens in both node A3 to node A2 and node B4 to node B2. Another problem of the CP2 charge pump is that when MA3 turns on, the gate voltage is provided by node B2. By this way, the gate drive voltage is only 1Vdd, resulting in higher conduction loss and reducing voltage gain and current drive capability.Figure 3
(a) Schematic of CP2 proposed in [7]; (b) undesired charge transfer in CP2 charge pump proposed in [7].
(a)(b)


## 3. Proposed Charge Pump Circuit

The following dual branch charge pump is proposed based on traditional CTS charge pump [5] and CP2 charge pump [7]. The charge pump is composed of two branches with a complementary clock signal. The work principle is as follows.


### 3.1. First Stage

The first stage is the same as the CP2 charge pump proposed in [7], which is composed of a single NMOS transistor for each branch. When ϕ1 is high and ϕ2 is low, the voltage of node A1 is 1Vdd and the voltage of node B is zero. By this way, MA1 turns off and MB1 turns on, charging node B1 to 1Vdd. When the clock flips, the voltage of node B1 pumps to 2Vdd and MA1 turns on charging node A1 to 1Vdd. By this way, MA1 and MB1 can turn on and off effectively by the voltage from the complementary branch and do not need start up transistor.


### 3.2. Middle Stage

Since the work principle is the same for middle stages, we choose stage three to explain the mechanism. The clock signal of auxiliary NMOS transistorϕ1′ is considered to be the same as ϕ1in this section. The NMOS transistor Ak3 is used to start up the circuit. When ϕ2 is high and ϕ1 is low, the voltage of node A4 is 5Vdd and node B4 is 4Vdd. MAP3 turns on, MAN3 turns off, and MA3 turns on. When the clock flips, the voltage of node A4 is 4Vdd and the voltage of node B4 is 5Vdd. By this way, MAP3 turns off and MAN3 turns on, resulting in the turning off of MA3. When MA3 turns on, the gate drive voltage is 2Vdd, which is much larger than that in the CP2 charge pump in [7], contributing to much smaller conduction loss.


### 3.3. Output Stage

The output stage for each branch is composed of a diode-connected NMOS and a PMOS. The diode-connected NMOS is aimed at providing a control signal to the previous stage, while the PMOS controlled by the complementary branch is aimed at controlling the output branch. It is shown in Figure4.Figure 4
Schematic of proposed charge pump.When the voltage of Bn is low and the voltage of An is high, MAout turns on and the output voltage is provided by branch A. When the clock flips, MBout turns on and the output voltage is provided by branch B. This mechanism eliminates the voltage drop in [5] and reduces the output voltage ripple effective. This mechanism also provides better current drive capability.


## 3.1. First Stage

The first stage is the same as the CP2 charge pump proposed in [7], which is composed of a single NMOS transistor for each branch. When ϕ1 is high and ϕ2 is low, the voltage of node A1 is 1Vdd and the voltage of node B is zero. By this way, MA1 turns off and MB1 turns on, charging node B1 to 1Vdd. When the clock flips, the voltage of node B1 pumps to 2Vdd and MA1 turns on charging node A1 to 1Vdd. By this way, MA1 and MB1 can turn on and off effectively by the voltage from the complementary branch and do not need start up transistor.


## 3.2. Middle Stage

Since the work principle is the same for middle stages, we choose stage three to explain the mechanism. The clock signal of auxiliary NMOS transistorϕ1′ is considered to be the same as ϕ1in this section. The NMOS transistor Ak3 is used to start up the circuit. When ϕ2 is high and ϕ1 is low, the voltage of node A4 is 5Vdd and node B4 is 4Vdd. MAP3 turns on, MAN3 turns off, and MA3 turns on. When the clock flips, the voltage of node A4 is 4Vdd and the voltage of node B4 is 5Vdd. By this way, MAP3 turns off and MAN3 turns on, resulting in the turning off of MA3. When MA3 turns on, the gate drive voltage is 2Vdd, which is much larger than that in the CP2 charge pump in [7], contributing to much smaller conduction loss.


## 3.3. Output Stage

The output stage for each branch is composed of a diode-connected NMOS and a PMOS. The diode-connected NMOS is aimed at providing a control signal to the previous stage, while the PMOS controlled by the complementary branch is aimed at controlling the output branch. It is shown in Figure4.Figure 4
Schematic of proposed charge pump.When the voltage of Bn is low and the voltage of An is high, MAout turns on and the output voltage is provided by branch A. When the clock flips, MBout turns on and the output voltage is provided by branch B. This mechanism eliminates the voltage drop in [5] and reduces the output voltage ripple effective. This mechanism also provides better current drive capability.


## 4. Undesired Charge Transfer Eliminating Method

Before proposing the method of eliminating undesired charge transfer, we should first analyze the mechanism of undesired charge transfer in the proposed charge pump. Since the work principles are the same in the middle stage, stage 3 is used to explain. Firstly, we analyze the condition thatϕ1′ equals to ϕ1. Assume at the beginning, ϕ2 is high and ϕ1 is low. The voltage of node A4 is 5Vdd and node B4 is 4Vdd. MAP3 turns on, MAN3 turns off, and MA3 turns on. When ϕ2 transfer to low and ϕ1 transfer to high, MN2 will not turn on until ϕ1 reaches Vthn, while MP2 will turn off since VA4−VB4<Vthp. If we use the original clock ϕ1 and ϕ2 to control the auxiliary NMOS in the PN switch pair, undesired charge transfer will happen as shown in Figure 5(a) unless Vthn+1/2Vthp=1/2Vdd. But the undesired charge transfer is significantly reduced compared with charge pumps proposed in [5, 6]. However, if we give a delay to the clock signal of the auxiliary NMOS transistor MAN3 to match the turn on and turn off time of MAN3 and MPN3, undesired charge transfer can be eliminated in this clock transfer period. The time delay element proposed in [9] can provide a time delay of 0.82 ps per resolution with very low power consumption. Figure 5(b) shows the elimination of undesired charge transfer by giving a delay to clock ϕ1. However, another problem occurs if we simply give a delay to ϕ1 to eliminate the undesired charge transfer in this clock transfer period; undesired charge transfer will become more severe in the complementary clock phase shown in Figure 5(c). The method to figure out this problem is to use nonoverlapping clock [8] shown in Figure 5(d). By employing a nonoverlapping clock and delay block, MAP3 will turn off simultaneously when MAN3 turns on. In the complementary clock transfer period, MAN3 will turn off before MAP3 turns on. A new clock signal ϕ1′ is formed by this way. Undesired charge transfer is completely eliminated by employing the new clock signal ϕ1′, and we call it clock matched technology.Figure 5
(a) Undesired charge transfer in original clock; (b) eliminating undesired charge transfer using delay block; (c) more severe undesired charge transfer in original clock with delay; (d) completely eliminating undesired charge transfer by using delay element and nonoverlapping clock.
(a)(b)(c)(d)


## 5. Simulation Results

Simulation results are provided in this section to make a comparison between the proposed charge pump and traditional charge pumps. All simulation results are performed in 0.18μm CMOS technology with the Cadence Spectre Circuit Simulator. All charge pumps are simulated in the same branch conditions with 1 MHz clock and 1.5 nF flying capacitors.All transistors are designed with the same dimension except for auxiliary transistors with much smaller size. A triple well structure is used to eliminate the body effect in all the charge pumps.Figures6(a) and 6(b) show the voltage gain and power efficiency for the proposed charge pump at a fixed load current of 100 μA with supply voltage varying from 0.9 V to 1.5 V. According to the figure, the output voltage shows linear growth as the stage increases, while the power efficiency decreases with stage increasing. The proposed charge pump with higher supply voltage also has a better performance in power efficiency simulation.Figure 6
(a) Voltage gain with different power stages with 100μA load current for the proposed charge pump; (b) power efficiency with different power stages with 100 μA load current for the proposed charge pump.
(a)(b)Figures7(a) and 7(b) show the comparison of the voltage gain and power efficiency of the proposed charge pump, CP2 charge pump in [7], and traditional CTS charge pump in [6] with different power stages with 1.5 V supply voltage at a fixed load current of 200 μA.Figure 7
(a) Comparison of different charge pump voltage gains with 1.5 V power supply at 200μA load current; (b) comparison of different charge pump power efficiencies with 1.5 V power supply at 200 μA load current.
(a)(b)As shown in Figures7(a) and 7(b), the proposed charge pump achieves the highest voltage gain and power efficiency among the three charge pumps. Figures 8(a) and 8(b) show the comparison of voltage gain and power efficiency for 4 stage charge pumps with different load current and fixed 1.5 V supply voltage.Figure 8
(a) The voltage gain for different charge pumps with different load current; (b) the power efficiency for different charge pumps with different load current.
(a)(b)As shown in Figures8(a) and 8(b), the proposed charge pump has the highest output voltage gain and power efficiency when the load current varies from 25 μA to 200 μA resulting from the elimination of undesired charge transfer and lower conduction loss. The employment of NMOS also helps the proposed charge pump to increase current drive ability. By this way, the advantage on voltage gain of the proposed charge becomes significant as the load current increases. The power efficiency for the proposed charge pump at low load current condition has not got obvious superiority resulting from extra auxiliary NMOS transistors used to start up the circuit, while it performs much better in high load current condition contributed by the lower conduction loss and the elimination of undesired charge transfer.Figure9(a) shows the output voltage waveform for the proposed charge pump, [6], and CP2 in [8] with 1.5 V supply voltage and 200 μA load current. As shown in the figure, the proposed charge pump has the fastest startup time among the three charge pumps. Figure 9(b) shows the output voltage ripple in the same simulation condition. Details of output voltage gain performance for the three charge pumps are shown in Table 1.Figure 9
(a) Comparison of output voltage waveform for different charge pumps with 1.5 V power supply and 200μA load current; (b) comparison of output voltage ripple for different charge pumps with 1.5 V supply voltage and 200 μA load current.
(a)(b)Table 1
Comparison of output voltage gain performance of the proposed charge pump, [6], and [7] with 1.5 V supply voltage and 200 μA load current.
Proposed charge pumpCP2 charge pumpTraditional CTS charge pumpOutput voltage (V)7.0666.9566.437Voltage gain (V/V)4.714.634.29Response time (μA)88.5119.5306.4Output voltage ripple (mV)6.46.879Output voltage percentage (V/V%)0.09050.09781.2273According to the details shown in Table1, the proposed charge pump achieves the highest voltage gain with the lowest voltage ripple and fastest startup time.


## 6. Conclusion

This paper proposes a new dual branch charge pump based on [5, 7] with undesired charge transfer eliminated and enhanced load current drive ability and output voltage gain. Clock matched technology based on nonoverlapping clock [8] and delay element [9] is used to eliminate undesired charge transfer. Conduction loss is reduced by the employment of NMOS and 2Vdd gate drive voltage compared to the charge pump proposed in [7]. The dual branch structure also provides better load current drive capability. Simulation shows that the proposed charge pump has the highest voltage gain and power efficiency with reduced voltage ripple and fast startup speed compared with [6, 7].



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