# Modeling and Analysis of New Multilevel Inverter for Solar Photovoltaic Power Plant

Authors: Xiaoqiang Guo; Ran He; Mehdi Narimani
Journal: International Journal of Photoenergy
 (2016)

---

## Abstract

Solar photovoltaic (PV) power plant is an effective way to utilize the renewable energy sources. EMI is one of the major concerns in PV power plant. Typically, the multilevel inverters are used in high voltage PV power plant. However, the conventional multilevel inverters require more semiconductors, which complicate the circuit structure and control algorithm. In this paper, a novel five-level inverter is introduced for the high voltage PV power plant applications. The model of the inverter is analyzed. With the redundant switching states, a new modulation strategy is proposed to reduce the common-mode voltage and EMI. The proposed approach is able to eliminate the common-mode voltage; meanwhile it has the capability of balancing the capacitor voltages. The cosimulation tests with the Matlab/Simulink and S-function are carried out. The results verify the effectiveness of the proposed method.


---

## Body

## 1. Introduction

The solar photovoltaic power plant is recently attracting much attention throughout the world. Typically, the multilevel inverters are applied in high voltage PV power plant [1–4], mainly due to the high voltage capability, low switching frequency, and low power losses [5, 6]. The classic multilevel topologies include the diode clamped, flying capacitor, and cascaded H-bridge converters [7–12]. However, these kinds of converters give rise to common-mode voltage (CMV), which could induce the ground leakage currents, as well as electromagnetic interference (EMI). And the EMI is one of the major concerns in PV power plant applications [13–16]. To reduce the EMI, many interesting methods have been reported in literature. For example, the CMV reduction for cascaded converters has been discussed in [17–19]. The CMV reduction strategies for neutral point clamped topologies have been reported in [20–22]. As for other types of multilevel converters, the space vector modulation (SVM) for CMV reduction of a four-level inverter is presented in [23] and for a five-level inverter is presented in [24]. Unfortunately, the balance of the capacitor voltage is not considered in the abovementioned modulation strategies. Actually, the balance of the capacitor voltage is one of the key issues in multilevel converters [7, 25]. Therefore, the modulation strategy which is able to eliminate the CMV and balance the capacitor voltage needs further investigation.The objective of this paper is to present the modeling and analysis of a novel five-level inverter for PV power plant applications. The rest of the paper is organized as follows. Section2 presents the analysis of the system operation principle. The proposed strategy is discussed in Section 3. The simulation interface and results are shown in Section 4. Finally, the conclusion is presented in Section 5.


## 2. Analysis of the New Five-Level Inverter

### 2.1. Operation of the Novel Five-Level Inverter

The novel five-level inverter, as shown in Figure1, is a combination of a flying capacitor inverter and a neutral point clamped inverter presented in [26]. To ensure the equally spaced steps in the output voltages, the capacitors C
x
1 and C
x
2 (x
=
a
,
b
,
c) are charged to 1
/
4
V
d
c and C
x
3 is charged to 3
/
4
V
d
c. V
d
c is the dc-link voltage. As shown in Table 1, the phase voltages are V
d
c
/
2, V
d
c
/
4, 0, -
V
d
c
/
4, and -
V
d
c
/
2, with respect to the midpoint n of the dc-link, corresponding to the phase switching states S
k
(
k
=
a
,
b
,
c
)
=
2,1
,
0
,
-
1
,
-
2.Table 1
Switching states of the five-level inverter.
S
1
x
S
2
x
S
3
x
S
4
x
S
5
x
S
6
x
S
7
x
S
8
x
V
C
x
1
V
C
x
2
V
C
x
3
V
x
n
i
x
>
0
i
x
<
0
i
x
>
0
i
x
<
0
i
x
>
0
i
x
<
0
1
1
1
1
0
0
0
0
—
—
—
—
—
—
V
d
c/2
(a)
1
1
0
1
1
0
0
0
C
D
—
—
—
—
V
d
c/4
(b)
0
1
1
1
0
0
0
1
—
—
—
—
D
C
(c)
1
0
1
1
0
0
1
0
D
C
D
C
C
D
(d)
1
1
0
0
1
1
0
0
C
D
C
D
—
—
0
(e)
1
0
0
1
1
0
1
0
—
—
D
C
C
D
(f)
0
1
0
1
1
0
0
1
C
D
—
—
D
C
(g)
0
0
1
1
0
0
1
1
D
C
D
C
—
—
(h)
0
0
0
1
1
0
1
1
—
—
D
C
—
—
−V
d
c/4
(i)
1
0
0
0
1
1
1
0
—
—
—
—
C
D
(j)
0
1
0
0
1
1
0
1
C
D
C
D
D
C
(k)
0
0
0
0
1
1
1
1
—
—
—
—
—
—
−V
d
c/2
(l)
C: charging; D: discharging.Figure 1
Schematic of the novel five-level inverter.


### 2.2. Common-Mode Voltage in the Novel Five-Level Inverter

The relationship between phase voltages and switching states can be expressed as follows:(1)
V
x
n
=
V
d
c
2
S
x
=
2
V
d
c
4
S
x
=
1
0
S
x
=
0
-
V
d
c
4
S
x
=
-
1
-
V
d
c
2
S
x
=
-
2
x
=
a
,
b
,
c
,
V
a
n
=
V
d
c
4
×
S
a
,
V
b
n
=
V
d
c
4
×
S
b
,
V
c
n
=
V
d
c
4
×
S
c
.The CMV is(2)
V
C
M
=
V
a
n
+
V
b
n
+
V
c
n
3
.S
s
u
m can be defined as (3)
S
s
u
m
=
S
a
+
S
b
+
S
c
.And the CMV generated by switching states can be expressed as(4)
V
C
M
S
s
u
m
=
V
d
c
12
×
S
s
u
m
.According to (4), the CMV of all the switching states can be calculated. Table 2 demonstrates the number of switching states corresponding to each CMV; for instance, 19 switching states make CMV zero. The switching states that make zero CMV are shown in Table 3, where(5)
S
a
+
S
b
+
S
c
=
0
.Table 2
CMV and switching states.
CMV
The number of switching states
V
d
c/2
1
5V
d
c/12
3
V
d
c/3
6
V
d
c/4
10
V
d
c/6
15
V
d
c/12
18
0
19
−V
d
c/12
18
−V
d
c/6
15
−V
d
c/4
10
−V
d
c/3
6
−5V
d
c/12
3
−V
d
c/2
1Table 3
Switching states with zero CMV.
CMV
Switching states
0
2-1-1, 20-2, 10-1, 11-2, 02-2, 01-1, -12-1, -220, -110, -211, -202, -101, -1-12, 0-22, 0-11, 1-21, 2-20, 1-10, 000Figure2 shows the 19 switching states that generate zero CMV where the switching states are symmetric in the space vector diagram. The switching states in the different sectors can be transformed into region I. For example, switching states (01-1), (-110), (-101), (0-11), and (1-10) can be converted to (10-1) in region I using the corresponding angle. Therefore, without considering the voltage balancing of the capacitors, the inverter can properly operate by employing the switching states and selecting the appropriate switching sequence.Figure 2
Space vector diagram in a five-level inverter.


## 2.1. Operation of the Novel Five-Level Inverter

The novel five-level inverter, as shown in Figure1, is a combination of a flying capacitor inverter and a neutral point clamped inverter presented in [26]. To ensure the equally spaced steps in the output voltages, the capacitors C
x
1 and C
x
2 (x
=
a
,
b
,
c) are charged to 1
/
4
V
d
c and C
x
3 is charged to 3
/
4
V
d
c. V
d
c is the dc-link voltage. As shown in Table 1, the phase voltages are V
d
c
/
2, V
d
c
/
4, 0, -
V
d
c
/
4, and -
V
d
c
/
2, with respect to the midpoint n of the dc-link, corresponding to the phase switching states S
k
(
k
=
a
,
b
,
c
)
=
2,1
,
0
,
-
1
,
-
2.Table 1
Switching states of the five-level inverter.
S
1
x
S
2
x
S
3
x
S
4
x
S
5
x
S
6
x
S
7
x
S
8
x
V
C
x
1
V
C
x
2
V
C
x
3
V
x
n
i
x
>
0
i
x
<
0
i
x
>
0
i
x
<
0
i
x
>
0
i
x
<
0
1
1
1
1
0
0
0
0
—
—
—
—
—
—
V
d
c/2
(a)
1
1
0
1
1
0
0
0
C
D
—
—
—
—
V
d
c/4
(b)
0
1
1
1
0
0
0
1
—
—
—
—
D
C
(c)
1
0
1
1
0
0
1
0
D
C
D
C
C
D
(d)
1
1
0
0
1
1
0
0
C
D
C
D
—
—
0
(e)
1
0
0
1
1
0
1
0
—
—
D
C
C
D
(f)
0
1
0
1
1
0
0
1
C
D
—
—
D
C
(g)
0
0
1
1
0
0
1
1
D
C
D
C
—
—
(h)
0
0
0
1
1
0
1
1
—
—
D
C
—
—
−V
d
c/4
(i)
1
0
0
0
1
1
1
0
—
—
—
—
C
D
(j)
0
1
0
0
1
1
0
1
C
D
C
D
D
C
(k)
0
0
0
0
1
1
1
1
—
—
—
—
—
—
−V
d
c/2
(l)
C: charging; D: discharging.Figure 1
Schematic of the novel five-level inverter.


## 2.2. Common-Mode Voltage in the Novel Five-Level Inverter

The relationship between phase voltages and switching states can be expressed as follows:(1)
V
x
n
=
V
d
c
2
S
x
=
2
V
d
c
4
S
x
=
1
0
S
x
=
0
-
V
d
c
4
S
x
=
-
1
-
V
d
c
2
S
x
=
-
2
x
=
a
,
b
,
c
,
V
a
n
=
V
d
c
4
×
S
a
,
V
b
n
=
V
d
c
4
×
S
b
,
V
c
n
=
V
d
c
4
×
S
c
.The CMV is(2)
V
C
M
=
V
a
n
+
V
b
n
+
V
c
n
3
.S
s
u
m can be defined as (3)
S
s
u
m
=
S
a
+
S
b
+
S
c
.And the CMV generated by switching states can be expressed as(4)
V
C
M
S
s
u
m
=
V
d
c
12
×
S
s
u
m
.According to (4), the CMV of all the switching states can be calculated. Table 2 demonstrates the number of switching states corresponding to each CMV; for instance, 19 switching states make CMV zero. The switching states that make zero CMV are shown in Table 3, where(5)
S
a
+
S
b
+
S
c
=
0
.Table 2
CMV and switching states.
CMV
The number of switching states
V
d
c/2
1
5V
d
c/12
3
V
d
c/3
6
V
d
c/4
10
V
d
c/6
15
V
d
c/12
18
0
19
−V
d
c/12
18
−V
d
c/6
15
−V
d
c/4
10
−V
d
c/3
6
−5V
d
c/12
3
−V
d
c/2
1Table 3
Switching states with zero CMV.
CMV
Switching states
0
2-1-1, 20-2, 10-1, 11-2, 02-2, 01-1, -12-1, -220, -110, -211, -202, -101, -1-12, 0-22, 0-11, 1-21, 2-20, 1-10, 000Figure2 shows the 19 switching states that generate zero CMV where the switching states are symmetric in the space vector diagram. The switching states in the different sectors can be transformed into region I. For example, switching states (01-1), (-110), (-101), (0-11), and (1-10) can be converted to (10-1) in region I using the corresponding angle. Therefore, without considering the voltage balancing of the capacitors, the inverter can properly operate by employing the switching states and selecting the appropriate switching sequence.Figure 2
Space vector diagram in a five-level inverter.


## 3. Proposed Strategy

### 3.1. Modulation Strategy

The CMV can not be eliminated in the conventional carrier-based modulation presented in [6] and this is because the different switching states generate different CMVs. For example, when the given reference falls into the shaded triangle in Figure 2, only one of the three switching states, namely, (10-1), is with zero CMV; however with the conventional modulation the CMV cannot be kept zero.Figure3(a) shows the three-level space vector diagram and Figure 3(b) is the same as Figure 2 rotated by 30 degrees. There are 27 switching states and 7 redundant switching states in Figure 3(a) where the redundant switching states operate similar to synthesize reference vectors. Therefore, regardless of redundant switching states, the number of actually working switching states is 19, which is the same as five-level switching states with zero CMV. In other words, there is corresponding relationship between three-level switching states and five-level switching states with zero CMV as shown in Table 4. For example, switching state (20-2) in a five-level space vector diagram with zero CMV is corresponding to a (200) switching state in a three-level diagram, and similarly switching state (10-1) in a five-level diagram is corresponding to switching states (211) or (100) in a three-level diagram.Table 4
Relationship between three-level switching states and five-level switching states.
Three-level switching states
Five-level switching states
200
20-2
211, 100
10-1
210
11-2
211, 110
01-1
220
02-2
120
-12-1
020
-220
121, 010
-110
021
-211
022
-202
122, 011
-101
012
-1-12
112, 001
0-11
002
0-22
102
1-21
202
2-20
101, 212
1-10
201
2-1-1
222, 111, 000
000Figure 3
Space vector diagram: (a) three levels and (b) five levels (CMV = 0).
(a)
(b)Table4 shows the relationship between the three-level switching states and five-level switching states with zero CMV. This feature results in the three-level modulation strategy employing Table 4 being used for a five-level inverter while achieving zero CMV.To achieve the three-level modulation strategy, there are space vector modulation and carrier-based modulation. Due to the complex calculation and implementation of space vector modulation, the carrier-based modulation is used in this paper.It should be noted that the zero CMV is achieved where the capacitor voltages are balanced. The following section will present a strategy to balance the capacitor voltages in each phase.


### 3.2. Capacitor Voltage Balancing Strategy

The capacitor voltagesV
C
x
1 and V
C
x
2 should be kept at 1/4 of the dc bus voltage (V
d
c/4) and V
C
x
3 should be maintained at 3/4 of the dc bus voltage (
3
V
d
c
/
4
) to ensure the proper operation of the five-level inverter. The voltage deviation of flying capacitor is defined as the difference between flying capacitor voltage and the given value, which can be expressed as(6)
Δ
V
C
x
1
=
V
C
x
1
-
V
d
c
4
,
Δ
V
C
x
2
=
V
C
x
2
-
V
d
c
4
,
Δ
V
C
x
3
=
V
C
x
3
-
3
V
d
c
4
,where V
C
x
1, V
C
x
2, and V
C
x
3 are capacitor voltages and Δ
V
C
x
1, Δ
V
C
x
2, and Δ
V
C
x
3 are the deviation of capacitor voltages. The capacitor voltage can be balanced by controlling the absolute value of the deviation voltages close to zero.The switching states (a)~(k) can affect the current flowing into the flying capacitors and can change the capacitor voltages by either charging or discharging. Taking switching state (
b
) as an example, when i
k
>
0, the capacitor C
x
1 is charged, and when i
k
<
0, the capacitor C
x
1 is discharged.The capacitor voltage balancing strategy can be defined as follows:(i)
Switching stateS
k
=
1 is employed to control capacitor voltages V
C
x
1 and V
C
x
3.
(ii)
Switching stateS
k
=
-
1 is employed to control capacitor voltages V
C
x
2 and V
C
x
3.
(iii)
Switching stateS
k
=
0 is employed to control capacitor voltages V
C
x
1 and V
C
x
2.Details of the control method are shown in Tables5, 6, and 7.Table 5
Control table for capacitor voltage:S
x
=
1.
Input conditions
Output results
S
x
ΔV
C
1
ΔV
C
3
The chosen switching states
1
>0
>0
(c)
>0
<0
(
d
)
<0
>0
(c)
<0
<0
(b)Table 6
Control table for capacitor voltage:S
x
=
-
1.
Input conditions
Output results
S
x
ΔV
C
2
ΔV
C
3
The chosen switching states
−1
>0
>0
(
j)
>0
<0
(k)
<0
>0
(j)
<0
<0
(i)Table 7
Control table for capacitor voltage:S
x
=
0.
Input conditions
Output results
S
x
i
x
ΔV
C
1
ΔV
C
2
The chosen switching states
0
>0
>0
>0
(h)
>0
<0
(e)
<0
>0
(g)
<0
<0
(e)
0
<0
>0
>0
(e)
>0
<0
(f)
<0
>0
(
h)
<0
<0
(h)


### 3.3. Integration Capacitor Voltage Balancing with PWM Schemes

The abovementioned capacitor voltage balancing method can be easily integrated with the proposed zero CMV modulation strategy. The schematic diagram of the integration is shown in Figure4. The procedure consists of the following steps:(1)
First, the three-level switching states are generated by a dual-carrier-based PWM scheme.
(2)
According to Table4, the five-level switching states corresponding to three-level switching states can be determined to keep the novel five-level inverter with zero CMV.
(3)
Finally, the capacitor voltage balancing can be achieved by using control tables of Table5, 6, and 7 and considering the direction of phase current i
k.Figure 4
The control diagram of the novel five-level inverter.


## 3.1. Modulation Strategy

The CMV can not be eliminated in the conventional carrier-based modulation presented in [6] and this is because the different switching states generate different CMVs. For example, when the given reference falls into the shaded triangle in Figure 2, only one of the three switching states, namely, (10-1), is with zero CMV; however with the conventional modulation the CMV cannot be kept zero.Figure3(a) shows the three-level space vector diagram and Figure 3(b) is the same as Figure 2 rotated by 30 degrees. There are 27 switching states and 7 redundant switching states in Figure 3(a) where the redundant switching states operate similar to synthesize reference vectors. Therefore, regardless of redundant switching states, the number of actually working switching states is 19, which is the same as five-level switching states with zero CMV. In other words, there is corresponding relationship between three-level switching states and five-level switching states with zero CMV as shown in Table 4. For example, switching state (20-2) in a five-level space vector diagram with zero CMV is corresponding to a (200) switching state in a three-level diagram, and similarly switching state (10-1) in a five-level diagram is corresponding to switching states (211) or (100) in a three-level diagram.Table 4
Relationship between three-level switching states and five-level switching states.
Three-level switching states
Five-level switching states
200
20-2
211, 100
10-1
210
11-2
211, 110
01-1
220
02-2
120
-12-1
020
-220
121, 010
-110
021
-211
022
-202
122, 011
-101
012
-1-12
112, 001
0-11
002
0-22
102
1-21
202
2-20
101, 212
1-10
201
2-1-1
222, 111, 000
000Figure 3
Space vector diagram: (a) three levels and (b) five levels (CMV = 0).
(a)
(b)Table4 shows the relationship between the three-level switching states and five-level switching states with zero CMV. This feature results in the three-level modulation strategy employing Table 4 being used for a five-level inverter while achieving zero CMV.To achieve the three-level modulation strategy, there are space vector modulation and carrier-based modulation. Due to the complex calculation and implementation of space vector modulation, the carrier-based modulation is used in this paper.It should be noted that the zero CMV is achieved where the capacitor voltages are balanced. The following section will present a strategy to balance the capacitor voltages in each phase.


## 3.2. Capacitor Voltage Balancing Strategy

The capacitor voltagesV
C
x
1 and V
C
x
2 should be kept at 1/4 of the dc bus voltage (V
d
c/4) and V
C
x
3 should be maintained at 3/4 of the dc bus voltage (
3
V
d
c
/
4
) to ensure the proper operation of the five-level inverter. The voltage deviation of flying capacitor is defined as the difference between flying capacitor voltage and the given value, which can be expressed as(6)
Δ
V
C
x
1
=
V
C
x
1
-
V
d
c
4
,
Δ
V
C
x
2
=
V
C
x
2
-
V
d
c
4
,
Δ
V
C
x
3
=
V
C
x
3
-
3
V
d
c
4
,where V
C
x
1, V
C
x
2, and V
C
x
3 are capacitor voltages and Δ
V
C
x
1, Δ
V
C
x
2, and Δ
V
C
x
3 are the deviation of capacitor voltages. The capacitor voltage can be balanced by controlling the absolute value of the deviation voltages close to zero.The switching states (a)~(k) can affect the current flowing into the flying capacitors and can change the capacitor voltages by either charging or discharging. Taking switching state (
b
) as an example, when i
k
>
0, the capacitor C
x
1 is charged, and when i
k
<
0, the capacitor C
x
1 is discharged.The capacitor voltage balancing strategy can be defined as follows:(i)
Switching stateS
k
=
1 is employed to control capacitor voltages V
C
x
1 and V
C
x
3.
(ii)
Switching stateS
k
=
-
1 is employed to control capacitor voltages V
C
x
2 and V
C
x
3.
(iii)
Switching stateS
k
=
0 is employed to control capacitor voltages V
C
x
1 and V
C
x
2.Details of the control method are shown in Tables5, 6, and 7.Table 5
Control table for capacitor voltage:S
x
=
1.
Input conditions
Output results
S
x
ΔV
C
1
ΔV
C
3
The chosen switching states
1
>0
>0
(c)
>0
<0
(
d
)
<0
>0
(c)
<0
<0
(b)Table 6
Control table for capacitor voltage:S
x
=
-
1.
Input conditions
Output results
S
x
ΔV
C
2
ΔV
C
3
The chosen switching states
−1
>0
>0
(
j)
>0
<0
(k)
<0
>0
(j)
<0
<0
(i)Table 7
Control table for capacitor voltage:S
x
=
0.
Input conditions
Output results
S
x
i
x
ΔV
C
1
ΔV
C
2
The chosen switching states
0
>0
>0
>0
(h)
>0
<0
(e)
<0
>0
(g)
<0
<0
(e)
0
<0
>0
>0
(e)
>0
<0
(f)
<0
>0
(
h)
<0
<0
(h)


## 3.3. Integration Capacitor Voltage Balancing with PWM Schemes

The abovementioned capacitor voltage balancing method can be easily integrated with the proposed zero CMV modulation strategy. The schematic diagram of the integration is shown in Figure4. The procedure consists of the following steps:(1)
First, the three-level switching states are generated by a dual-carrier-based PWM scheme.
(2)
According to Table4, the five-level switching states corresponding to three-level switching states can be determined to keep the novel five-level inverter with zero CMV.
(3)
Finally, the capacitor voltage balancing can be achieved by using control tables of Table5, 6, and 7 and considering the direction of phase current i
k.Figure 4
The control diagram of the novel five-level inverter.


## 4. Simulation Interface and Results

The cosimulation between Matlab/Simulink and S-function is realized to verify the effectiveness of the proposed method, as shown in Figure5. The simulation parameters are listed in Table 8. In Simulink environment, the model of each system component is expressed by block diagram, and the lines among the block diagram indicate the direction of the signal flow. From the perspective of the whole system,Simulink is fast and convenient. However, for some complex and lengthy program code, it is not suitable with modularity. That is the reason why S-function is used for the simulation interface. The cosimulation system is very useful to tackle the demand of the simulation and implementation of complex multilevel inverter systems.Table 8
Simulation parameters.
Inverter parameters
Values
Input dc voltage
12 kV
Capacitor
1000μF
Inverter rating
3 MVA
Output frequency
50 Hz
Output inductance
5 mH
Power factor
0.9
Modulation index
0.95
Switching frequency
700 HzFigure 5
Matlab/Simulink and S-function cosimulation.Figure6 shows the performance of the five-level inverter with conventional and proposed modulations. The total harmonic distortion of the line-line voltage with conventional modulation is 17.32% and the CMV cannot be eliminated, varying within the range of V
d
c/6 and -
V
d
c/6. Whereas the total harmonic distortion of the line-line voltage with proposed modulation is 37.41%, however, the CMV can be effectively eliminated. It should be noted that, like other modulation strategy regarding the common-mode voltage reduction, the voltage THD will be higher. However, it mainly consists of high frequency components. So the THD can be reduced with the output filter, as shown in Figure 7.Figure 6
Simulation results of different modulations.
(a)
Conventional modulation method
(b)
Proposed modulation methodFigure 7
Simulation results from half to full loads.To evaluate the dynamic performance of the proposed modulation, a step change from half load to full load has been studied att
=
0.1 s, as shown in Figure 7. The voltage of the flying capacitors can be maintained at the nominal values and the CMV can be kept constant at zero before and after the step change.In order to verify the performance of the proposed control strategy with and without the proposed control, the simulation test is carried out and shown in Figure8. In this case, the proposed controller is enabled and, at t
=
0.05 s, the controller is disabled; then the controller is reactivated at t
=
0.1 s. As can be seen from Figure 8, when the controller is deactivated, the capacitor voltages diverge and the CMV gets bigger. However, when the controller is reactivated, the capacitor voltage starts converging and the CMV approaches zero rapidly, which verifies the effectiveness of the proposed control strategy.Figure 8
Simulation results with and without proposed controller.


## 5. Conclusion

The modeling and analysis of a novel five-level inverter for PV power plant applications has been presented in this paper. The common-mode voltage can be eliminated by selecting the specific switching states. Also, the balancing of flying capacitor voltages can be achieved with a simple control strategy. In contrast to the conventional solutions, our proposal reduces the number of calculations which simplifies the implementation, and thus it is very attractive for PV power plant applications, where the EMI is a major concern. It should be noted that this paper mainly focuses on the CMV and EMI reduction of the five-level inverter for PV power plant. The MPPT and other issues of PV power plant are the subject of the future research.



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*Source: 4063167-2016-09-21.xml*