# A Novel Structure for Transformerless Grid-Connected PV Inverter to Eliminate Common-Mode Current under Mismatch Condition

Authors: Alireza Katouli; Mohammad Rezanejad; Jafar Adabi
Journal: International Transactions on Electrical Energy Systems
 (2022)

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## Abstract

Common-mode current is one of the major challenges in transformerless grid-connected photovoltaic (PV) inverters. This current is affected when the PV arrays are exposed to different environmental conditions and its value increases. This paper attempts to investigate the effect of mismatched condition on voltage balance of PV arrays, which leads to the increment of common-mode current. A new circuit structure is presented for compensating for voltage drop caused by partial shading and ambient temperature and removing the effect on the common-mode current. To validate the proposed structure, a laboratory prototype of this circuit is implemented.


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## Body

## 1. Introduction

In recent years, grid-connected photovoltaic (PV) systems have become increasingly significant due to rising prices of fossil fuel, sustainability of solar energy, and its reliability. Two categories of inverters (with transformer isolation and transformerless) can be employed for connecting PV systems to the grid. Transformerless inverters have attracted more attention due to some advantages such as smaller size, lower price, and higher efficiency [1–3].There are two methods for connecting PV arrays to transformerless inverter input. In the first method, the PV arrays are connected in series and to the inverter. In the second one, the PV arrays are divided into two equal parts and their midpoint is connected to the middle of the separate DC link capacitors (see Figure1). A DC/DC converter might be located between the arrays and inverter. The benefit of the second method over the first one is its separate and accurate control of each of the array sections, which causes the improvement of the maximum power point tracking (MPPT) [6, 7].Figure 1
Previous proposed topologies. (a) Proposed topology in [4]; (b) proposed topology in [5].
(a)(b)Mismatched condition is one of the major problems of photovoltaic systems, which leads to the reduction of the generated energy by the PV arrays. Many structures are presented to solve this problem by balancing the input voltage or creating bypass path for the current [8–13].One type of these structures is switched-capacitor converters which balance the input voltage through charging and discharging of capacitors [8, 9]. The resonant switched capacitors are used for balancing input voltage by transferring additional energy from an array with higher voltage to an array with lower voltage [10]. A switched-capacitor converter with one capacitor and several switches is presented in [11], which performs balancing. Other converters include buck-boost converters and multiwinding transformers [12, 13]. In [14], a single-stage transformerless PV inverter topology and the PWM strategy are proposed for producing continuous power from the PV during any condition of solar radiance. The objective of paper [15] is to present a new modulation strategy for the leakage current reduction of Z source four-leg inverter for transformerless PV systems. In [16], a new circuit configuration for the inverter having a single DC link capacitor and seven IGBTs is proposed. The common-mode voltage is kept at a constant value and the ground leakage current is suppressed. The aim of [17] is to present a new type of transformerless inverters, which is a common ground-based topology and can improve the performance of the system by its inherent boosting feature and unipolar PWM scheme. In [18], a new inverter topology is proposed. The proposed inverter develops a four-level voltage through four switches, two diodes, and four capacitors.A major challenge in connecting PV arrays to the power grid through transformerless inverters is the common-mode current. It flows through parasitic capacitors and is located between photovoltaic arrays and ground, which leads to some major issues [19, 20]. It causes loss increase, quality reduction of the injected current to the grid, electromagnetic interference, inaccurate performance of the protective relays, and especially some issues related to the personal safety [21, 22].Therefore, suppression or elimination of common-mode current has turned into a hot topic over the recent decades through inventing many structures by separating PV arrays from AC source or adding an extra clamped circuit [23–26]. In the separating method, the panel is separated from the grid by adding one or more switches to the main structure. The main converters in this category are H5 [23], H6 [24], HERIC [25], and the high-efficiency transformerless inverter presented in [26]. In clamp circuit method, an additional circuit is employed for clamping the midpoint voltage of the inverter legs. A common-mode reduction method is to connect grid negative terminal to the midpoint of DC link capacitors, which causes a constant common-mode voltage equal to half of input value [27].Many of the recent solutions for common-mode current elimination in two-subarray PV system were only successful with equal DC link capacitors. Environmental condition leads to variation of DC link voltages, which increases common-mode current.Different topologies are presented to solve this problem. A new inverter topology is proposed in [4], which is derived by combining two half bridge inverters along with their respective AC bypass. Two serially connected arrays are controlled individually by these two half bridge inverters. As the voltage across parasitic capacitors has only low frequency components, the magnitude of leakage current is low and remains within the standard permissible range (see Figure 1(a)). In [28], each PV array is controlled by a buck-boost-based inverter.In [5], two subarrays are connected in series. The neutral point clamped-based structure of the inverter leads to elimination of leakage current (see Figure 1(b)). Despite the fact that all these topologies are able to eliminate leakage current during environmental condition, they lose output power significantly in this condition.In this paper, a structure is introduced which eliminates the common-mode current considering partial shading and ambient temperature effect. Among all topologies that were mentioned before, those in [4, 5] and proposed topology are the only structures that considered leakage current during environmental condition. The remainder of the paper is organized as follows: an investigation of the common-mode current is presented in Section 2; an introduction and investigation of the presented circuit are presented in Section 3; simulation and experimental results are presented in Section 4; ultimately, conclusions are provided in Section 5.


## 2. Investigating the Common-Mode Current and the Effects of Environmental Condition

Figure2 shows the common-mode current loop, where CPV is the parasitic capacitance and its value depends on size and frame of the PV array, humidity, and so forth. Points A and B are the midpoints of inverter legs and N is the negative terminal of DC link.Figure 2
Leakage current path for transformerless PV inverters.Common-mode voltage (VCM) and differential-mode voltage (VDM) are related to VBN and VAN, which are expressed as follows [29]:(1)VCM=VAN+VBN2,(2)VDM=VAN−VBN.VDM causes generation of additional common-mode voltage (VCM_DM) and influences on common-mode current which is obtained as [30](3)VCM−DM=VAN−VBN2×L1−L22L1+L2,where L1 and L2 are grid side filters. Therefore, the total common-mode voltage and common-mode current will be equal to(4)VCM−all=VCM+VCM−DM=VAN+VBN2+VAN−VBN2×L1−L22L1+L2,(5)ICM=CPV×dVCM−alldt.Obviously, ifL1 and L2 are equal, VCM_DM will be zero and the value of the total common-mode voltage will be equal to VCM [31]. It is concluded that the common-mode current would be zero by keeping VCM constant.Normally, in order to eliminate the common-mode current in grid-connected transformerless inverters, they can be restructured by adding some other switches and elements in order to stabilize common-mode voltage at a certain level using special switching states. Switching modes of Figure1 can be categorized into the three following states:To generate +VDC output voltage, legs A and B are connected to points P and N of DC link input, respectively, and, therefore, common-mode voltage is calculated:(6)VCM=VAN+VBN2=VAP+VPN+VBN2=0+VDC+02=VDC2.To generate zero output voltage, legsA and B are connected to point O and PVs are separated from the source. In this state, the common-mode voltage is obtained as(7)VCM=VAN+VBN2=VAO+VON+VBO+VON2=0+VDC/2+0+VDC/22=VDC2.To generate −VDC output voltage, legs A and B are connected to N and P, respectively. Like the first state, the common-mode voltage is equal to(8)VCM=VAN+VBN2=VAN+VBP+VPN2=0+0+VDC2=VDC2.Therefore, the common-mode voltages of all states are the same and equal toVDC/2, which does not generate common-mode current. This condition is valid until the voltages of both capacitors are equal. However, if a PV array is subjected to different environmental condition, the voltage of the related array will be reduced, which leads to unbalanced capacitors voltages. For example, in Figure 2, in case of mismatched condition on the upper subarray, VC1 reduces to VDC/2 − ΔV (ΔV is the voltage drop caused by mismatched condition) and C2 capacitor's voltage will be equal to VDC/2. Therefore, the common-mode voltages during achieving output voltages of +VDC, 0, and −VDC, respectively, are(9)VCM=VAN+VBN2=VDC/2−ΔV+VDC/2+02=VDC−ΔV2,(10)VCM=VAN+VBN2=VDC/2+VDC/22=VDC2,(11)VCM=VAN+VBN2=VDC/2−ΔV+VDC/2+02=VDC−ΔV2.As can be observed, the common-mode voltage would have different values in every state, which leads to the generation of common-mode current. As the amount of partial shading and ambient temperature increases, the amount of voltage drop increases, too.


## 3. Circuit Topology and Its Operating Principals

The general structure of proposed circuit is shown in Figure3.Figure 3
Proposed topology.This circuit consists of primary section which is applied for common-mode current elimination and the effect of mismatched condition and secondary section which is an inverter for grid-connection purposes. At first, it is assumed that the circuit is in a normal no-mismatch condition.


### 3.1. Circuit Performance in Normal Condition

In this case, switches S7 and S8 are turned off which exit inductors of the primary section (L1, L2) and the circuit has four modes of operation (see Figure 4). Hence, assuming that the voltages of C1 and C2 are VDC/2, the performance states of the circuit are expressed as follows (see Figure 5):Figure 4
Operating modes of proposed topology in normal condition. (a) Stage A-1. (b) Stage A-2. (C) Stage A-3. (d) Stage A-4.
(a)(b)(C)(d)Figure 5
Normal operating modes diagram.State A-1: switches S1, S4, S5, and S6 are on. Here, VAN, VBN, and output voltage are equal to VDC, 0, and VDC. The common-mode voltage in this state is VDC/2 (see Figure 4(a)).State A-2: switches S1, S2, and S6 and diode D3 are on. Here, VAN and VBN are equal to VDC/2, and the output voltage is 0. In this case, PV is disconnected from the grid for freewheeling. The common-mode voltage for this state is VDC/2 (see Figure 4(b)).State A-3: In this case, switches S2, S3, S5, and S6 are on. Here, VAN is equal to 0 and VBN is equal to VDC, and the output voltage is equal to −VDC. The common-mode voltage in this state is VDC/2 (see Figure 4(c)).State A-4: In this case, switches S4, S3, and S5 and diode D4 are on. Here, VAN and VBN are equal to VDC/2, and the output voltage is 0. In this state, PV is disconnected from the grid for freewheeling. The common-mode voltage in this state is VDC/2 (see Figure 4(d)).As can be observed,VCM is VDC/2 for all states, which causes the elimination of the common-mode current according to equation (5).


### 3.2. Circuit Performance under Mismatch Condition

As mentioned in Figure3, proposed circuit has two primary and secondary sections with the function of capacitor voltage balancing and grid connection, respectively.


#### 3.2.1. Considering the Circuit without Primary Circuit (S7 and S8: OFF)

If mismatch condition occurs at first subarray,VC1 is VDC/2 − ΔV and VC2 is VDC/2. Therefore, common-mode voltages at states A-1 to A-4 in mismatch condition will be as follows:(12)StateA−1:VCM=VAN+VBN2=VDC/2−ΔV+VDC/2+02=VDC−ΔV2,(13)StateA−2:VCM=VDC/2+VDC/22=VDC2,(14)StateA−3:VCM=VAN+VBN2=VDC/2−ΔV+VDC/2+02=VDC−ΔV2,(15)StateA−4:VCM=VDC/2+VDC/22=VDC2.


#### 3.2.2. Considering the Circuit with Primary Circuit (S7 and S8: ON)

As can be observed, the common-mode voltage for each state is different from the other ones, which creates common-mode current according to equation (5). Therefore, a balancing circuit is required. In this case, depending on the location of shading and ambient temperature (upper or lower subarrays), the mismatch effect on the common-mode current can be eliminated by switching switches S7 or S8. It is worth mentioning that switching of these two switches is independent of other circuit components.When the mismatch occurs on thePVs, the circuit has six modes of operation (see Figures 6 and 7). Assuming that the shading falls on the upper PV, common-mode voltages for these six states are as follows:Figure 6
Mismatch operating modes (VAB = VDC). (a) L2 charging; (b) L2 discharging.
(a)(b)Figure 7
Mismatch operating modes (VAB = 0). (a) L2 charging; (b) L2 discharging.
(a)(b)StateB-1: switches S1, S4, S5, and S6 are on. Here, VAN is equal to VDC and VBN is equal to 0, and the output voltage is equal to VDC. By turning switch S8, L2 inductor current begins to increase (see Figure 6(a)).StateB-2: like the first state, switches S1, S4, S5, and S6 are on, and VDC = VAN, VBN = 0, and the output voltage is VAB = VDC. Here, by turning switch S8 off, inductor L2 which is charged by the lower subarray will be discharged on capacitor C1 and cause an increase in capacitor voltage (see Figure 6(b)).StateB-3: according to Figure 7(a), switches S1, S2, and S6 and diode D3 are on, and PV is disconnected from the grid for freewheeling. Here, VAN and VBN are equal to VDC/2 and output voltage is 0. Here, by turning switch S8 on, inductor L2 is charged by capacitor C2.StateB-4: Like state 3, switches S1, S2, and S6 and diode D3 are on, VBN and VAN are equal to VDC/2, and the output voltage is 0. Here, by turning switch S8 off, inductor L2 which was previously charging begins to discharge in capacitor C1 (see Figure 7(b)).StateB-5: In this case, according to Figure 8(a), switches S2, S3, S5, and S6 are on. Here, VAN is 0 and VBN is equal to VDC, and the output voltage is equal to −VDC. In this state, by turning switch S8 on, inductor L2 is charged by capacitor C2.Figure 8
Mismatch operating modes (VAB = −VDC). (a) L2 charging; (b) L2 discharging.
(a)(b)StateB-6: In this case, like state 5, switches S2, S3, S5, and S6 are on, and VAN = 0, VBN = VDC, and VAB = −VDC. Here, by turning switch S8 off, inductor L2 is discharged in capacitor C1 (Figure 8(b)).As can be observed in all the above six states, regardless of the inverter conditions, the primary circuit can charge or dischargeL2 by turning S7 off and switching of S8. Therefore, it compensates the voltage drop caused by partial shading on the upper PV. The conceptual waveforms of gate signal of the switches, leg voltages, and common-mode voltage of all possible states are brought in Figure 9(a). The same procedure can be carried out for partial shading of lower subarray. In this case, signals of S1 and S4, S2 and S3, S5 and S6, and S8 and S7 will be replaced with each other (see Figure 9(b)).Figure 9
Mismatch operating modes diagram. (a) Shading on upperPV; (b) shading on lower PV.
(a)(b)


### 3.3. Switching Method

When the insolation level and ambient temperature of subarrayPV1 are different from those of PV2, the MPP parameters of the two subarrays differ from each other. By considering that both subarrays are operating at their respective MPP and neglecting the losses incurred in power processing stages, the average power involved with C1 and C2 (PC1 and PC2) over a cycle can be assumed equal to the power extracted from PV1 and PV2. Therefore,(16)PC1+PC2=PPV1+PPV2.The average power injected to the grid,Pg, can be written as(17)Pg=PPV1+PPV2,and(18)Pg=VgridIgridcosφ=12VmImcosφ,where Vm and Im are the amplitude and current of the grid voltage (vgrid and Igrid), respectively. The relation of output and input voltage of inverter can be expressed as(19)Vm=maVC1+VC2,where ma is the modulation index of the inverter.By combining the above equations, the power injected to the grid can be expressed as(20)Pg=12maVC1+VC2Imcosφ=PPV1+PPV2.Hence,(21)PPV1=12maVC1Imcosφ.Similarly,(22)PPV2=12maVC2Imcosφ.Therefore,(23)VC1=2PPV1maImcosϕ,(24)VC2=2PPV2maImcosϕ.By combining (20), (21), and (22),(25)VC1=VmPPV1maPPV1+PPV2,(26)VC2=VmPPV2maPPV1+PPV2.Based on the above equations, the control strategy of the proposed scheme is shown in Figure10.Figure 10
Control strategy of S8 and S9 of the proposed structure.In this control strategy, both subarrays operate at their corresponding MPPT simultaneously. Two separate MPP trackers are employed to determine the values ofPV1 and PV2, which are required to estimate VC1 and VC2. Using (25) and (26), VC1 and VC2 are estimated [4, 28]. VC1 and VC2 are compared to Vref2 (which in this case is 200 V) and after two separate PI controllers and a PWM block for every two, S7 and S8 are determined. Hence, two voltage sensors that otherwise would have been required to determine VC1 and VC2 get eliminated.The switching method of the presented circuit is unipolar SPWM which is displayed in Figure11. First (second) cycles occur when the shading falls on upper (lower) PV, where Vc is triangular waveform and Vref is reference waveform which is obtained as feedback from the grid. By comparing these two waveforms, depending on where the mismatch occurs, the switching method of switches is determined. Control method of the circuit is shown in Figure 12.Figure 11
Basic modulation strategy of the proposed topology.Figure 12
Proposed topology control strategy.Switching states of S7 and S8 are directly determined by Figure 10.


### 3.4. Stability

Given Table1 and Figure 13, new Sa, Sb, and Sc functions are defined for switching of the proposed inverter.(27)Sa=S1−S2,(28)Sb=S2−S1,(29)Sc=S4−S3,(30)Sd=S3−S2,(31)Se=S1−S4,Table 1
Switching states and terminal voltages.
VoutS1S2S5S6SaSbScSdSeS8 onS8 off+110111−1010C1 chargingC1 discharging01101001−10C1 chargingC1 discharging−10111−1100−1C1 chargingC1 dischargingFigure 13
Schematic of the proposed inverter.and, using Table1 and Figure 13, the inverter model can be written as(32)Vout=SaVDC+SbVC1+ScVC2+SdVL1+SeVL2.The capacitors dynamics are expressed as(33)IC1=C1dvC1dt=−Sbig+ScIL2,(34)IC2=C2dvC2dt=−Sbig+ScIL1,and the inductors dynamics are expressed as(35)VL1=SbVC1−ScVC2,(36)diL1dt=1L1SbVC1−ScVC2,(37)VL2=ScVC2−SbVC1,(38)diL2dt=1L2ScVC2−SbVC1,while the grid model and the current dynamics can be written as(39)digdt=1Lg−rgig+1LgVout−Vg.One can define the grid current error asX1 = ig − ig∗, where ig∗ represents the grid current reference signal. Similarly, the capacitors voltage errors may be defined as X2 = VC1 − VC1∗ and X3 = VC2 − VC2∗, where VC1∗ and VC2∗ are constant DC voltages. The inductors current errors may be defined as X4 = IL1 − IL1∗ and X5 = IL2 − IL2∗, where IL1∗ and IL2∗ are constant DC currents.From the above equations, the current error derivative can be written asx1. = dig/dt−dig∗/dt.Using (13), ig = X1 + ig∗, VC1 = X2 + VC1∗, VC2 = X3 + VC2∗, IL1 = X4 + IL1∗, and IL2 = X5 + IL2∗, one can obtain(40)x1.=1LgSaVDC+SbX2+VC1∗+ScX3+VC2∗+SdSbX2+VC1∗−ScX3+VC2∗++SeScX3+VC2∗−SbX2+VC1∗−rgX1+ig∗+Vg+Lgdigdt.Similarly, after substituting the expressions ofig = X1 + ig∗, IL1 = X4 + IL1∗, and IL2 = X5 + IL2∗ in (7) and (8), the capacitors voltage errors may be written as(41)x2.=1C1_Sbig+ScIL2=−1C1SbX1+ig∗+ScX5+IL2∗,(42)x3.=1C2_Sbig+ScIL1=−1C2SbX1+ig∗+ScX4+IL1∗.Similarly, after substituting the expressions ofVC1 = X2 + VC1∗ and VC2 = X3 + VC2∗ in (10) and (12), the inductors current errors may be written as(43)x4.=1L1SbX2+VC1∗−ScX3+VC2∗.(44)x5.=1L2ScX3+VC2∗−SbX2+VC1∗.The Lyapunov function can be defined in terms of system state errors, represented by vectorx. Assume that the equilibrium of controlled system is at the origin x = 0. When the energy function becomes zero, the system is settled at the equilibrium point, and if the energy function is rapidly increasing, then the system is unstable, and it is asymptotically stable if the energy is decreasing. The stability of a system is guaranteed if the following conditions hold:(1)
V (x) is positive definite(2)
−V(x) is negative definite(3)
V (x) goes to ∞ as ǀxǀ ∞A Lyapunov function in terms of system’s errors is suggested as follows:(45)vx=12a1x12+12a2x22+12a3x32+12a4x42+12a5x52,where α1 and α2 are real positive numbers, which must be properly selected. It is clear that the above function is positive definite. Lyapunov control theory states that stability of the controlled system presented above is guaranteed if we ensure that, for all values of x, v˙x<0.Derivative of (45) with respect to time yields(46)v˙x=a1x1x˙1+a2x2x˙2+a3x3x˙3+a4x4x˙4+a5x5x˙5.Using equations (40)–(44) in (46), one can getv˙x = X1X2 (α1SbSd−Se/Lg − α2Sb/C1) + X1X3 (α1ScSe−Sd/Lg − α3Sb/C2) − X2X5 (α2Se/C1 + α5Sb/L2) − X3X4 (α3Sd/C2 + α4Sc/L1) + X2X4 (α2Sd/C1 + α4Sb/L1) + X3X5 (α5Sc/L2+α3Se/L2) − X12α1rg/Lg+X1 (α1VDC+VC1∗Sb+SdSb+SeSb+VC2∗Sc+ScSd+SeSd−rgig∗−Vg/Lg−α1dig∗/dt) + X2 (α2−Sbig∗+SdiL1∗+SeiL2∗/C1) + X3 (α3−Sbig∗+SdiL1∗+SeiL2∗/C2) + X4 (α4SbvC1∗−ScVC2∗/L1) + X5 (α5ScvC2∗−SbVC1∗/L2) (36).In order to eliminateX1X2, X1X3, X2X5, X3X4, X2X4, and X3X5 terms, gains are chosen to satisfy(47)α1=LgC1Sd−Seα2,(48)α3=ScC2Se−SdLgSbα1,(49)α2=−SbC1L2Seα5,(50)α3=−ScC2SdLe1α4,(51)α4=−SdL1C1Sbα2,(52)α4=−SeScα2.After eliminatingX1X2, X1X3, X2X5, X3X4, X2X4, and X3X5 terms, we have(53)v˙x=−X12α1rgLg+X1α1VDC+VC1∗Sb+SdSb+SeSb+VC2∗Sc+ScSd+SeSd−rgig∗−VgLg−α1dig∗dt+X2α2−Sbig∗+SdiL1∗+SeiL2∗C1+X3α3−Sbig∗+SdiL1∗+SeiL2∗C2+X4α4SbvC1∗−ScVC2∗L1+X5α5ScvC2∗−SbVC1∗L2.Then we have(54)v˙x=−X12α1rgLg+X1α1VDC+VC1∗Sb+SdSb+SeSb+VC2∗Sc+ScSd+SeSd−rgig∗−VgLg︸λ1X1−α1dig∗dt+X2α2−Sbig∗+SdiL1∗+SeiL2∗C1︸λ2X2+X3α3−Sbig∗+SdiL1∗+SeiL2∗C2︸λ3X3+X4α4SbvC1∗−ScVC2∗L1︸λ4X4+X5α5ScvC2∗−SbVC1∗L2︸λ5X5.In order to makev˙x<0,(55)λ1−α1rgLg,λ2,λ3,λ4,λ5<0.


### 3.5. Reliability

Reliability evaluation of the proposed converter circuit is presented using Markov approach. Note that hazard rates of power electronic components are only considered in their useful life and other phases such as debugging (which are related to manufacturing errors) and fatigue phases of the components are not considered in the analysis. Figure14 shows the Markov chain of the mentioned system, which is not employing any fault tolerant scheme.Figure 14
Markov chain of proposed topology.It has only three states:State1: proposed topology completely feeds power to the grid and eliminates common-mode current.State2: proposed topology completely feeds power to the grid but cannot eliminate the common-mode current.State3: failure.λ12 is expressed as(56)λ12=λS7+λS8+λD1+λD2+λL1+λL2,(57)λ23=∑i=06λSi+∑i=312λDi+λL3+λL4+2λC,(58)λ13=∑i=06λSi+∑i=312λDi+λL3+λL4+2λC.λS, λd, λL, and λC are the failure rates of switches, diodes, inductors, and capacitors, respectively, which are calculated as(59)λS=λbπTπAπQπE,(60)λd=λbπTπSπCπQπE,(61)λL=λbπCπQπE,(62)λC=λbπCVπQπE.For each component,λb, πQ, and πE are basic failure rate factor, quality factor, and environment factor of mentioned components, respectively. πA is the application factor of the switch. πcv and πC are capacitance factor and inductor construction factor, respectively. Also, πS is the electrical stress factor of the diode. Mentioned parameters can be easily extracted from [32] regarding the type of the component and its application. πT is the temperature factor for switches and diodes:(63)πTS=exp−19251TjS+273−1298,(64)πTd=exp−30911Tjd+273−1298.In the above two equations, TjS and Tjd are the junction temperatures of the switch and diode, respectively.(65)TjS=TA+RjAS×PLOSSS,(66)Tjd=TA+RjAd×PLOSSD.TA is the ambient temperature. PLOSSS and PLOSSD are the losses of the switch and diode, respectively. RjAS and RjAd are the junction ambient resistance. According to Figure 1 and mentioned equations, the probability of each state is calculated as(67)ddtP1tP2tP3t=P1tP2tP3tλ11λ12λ13λ21λ22λ23λ31λ32λ33,where P1, P2, and P3 are probabilities of states 1, 2, and 3, respectively. λ is the transition matrix, where(68)λ11=−λ12,λ22=−λ23,λ31=λ21=λ32=0.Assuming that the chain is started from state1, which is healthy state, the following initial condition occurs and the reliability is calculated as(69)P0=100.The reliability is calculated as(70)Rt=P1t+P2t,and the mean time to failure (MTTF) is obtained as(71)MTTF=∫0∞Rtdt.


## 3.1. Circuit Performance in Normal Condition

In this case, switches S7 and S8 are turned off which exit inductors of the primary section (L1, L2) and the circuit has four modes of operation (see Figure 4). Hence, assuming that the voltages of C1 and C2 are VDC/2, the performance states of the circuit are expressed as follows (see Figure 5):Figure 4
Operating modes of proposed topology in normal condition. (a) Stage A-1. (b) Stage A-2. (C) Stage A-3. (d) Stage A-4.
(a)(b)(C)(d)Figure 5
Normal operating modes diagram.State A-1: switches S1, S4, S5, and S6 are on. Here, VAN, VBN, and output voltage are equal to VDC, 0, and VDC. The common-mode voltage in this state is VDC/2 (see Figure 4(a)).State A-2: switches S1, S2, and S6 and diode D3 are on. Here, VAN and VBN are equal to VDC/2, and the output voltage is 0. In this case, PV is disconnected from the grid for freewheeling. The common-mode voltage for this state is VDC/2 (see Figure 4(b)).State A-3: In this case, switches S2, S3, S5, and S6 are on. Here, VAN is equal to 0 and VBN is equal to VDC, and the output voltage is equal to −VDC. The common-mode voltage in this state is VDC/2 (see Figure 4(c)).State A-4: In this case, switches S4, S3, and S5 and diode D4 are on. Here, VAN and VBN are equal to VDC/2, and the output voltage is 0. In this state, PV is disconnected from the grid for freewheeling. The common-mode voltage in this state is VDC/2 (see Figure 4(d)).As can be observed,VCM is VDC/2 for all states, which causes the elimination of the common-mode current according to equation (5).


## 3.2. Circuit Performance under Mismatch Condition

As mentioned in Figure3, proposed circuit has two primary and secondary sections with the function of capacitor voltage balancing and grid connection, respectively.


### 3.2.1. Considering the Circuit without Primary Circuit (S7 and S8: OFF)

If mismatch condition occurs at first subarray,VC1 is VDC/2 − ΔV and VC2 is VDC/2. Therefore, common-mode voltages at states A-1 to A-4 in mismatch condition will be as follows:(12)StateA−1:VCM=VAN+VBN2=VDC/2−ΔV+VDC/2+02=VDC−ΔV2,(13)StateA−2:VCM=VDC/2+VDC/22=VDC2,(14)StateA−3:VCM=VAN+VBN2=VDC/2−ΔV+VDC/2+02=VDC−ΔV2,(15)StateA−4:VCM=VDC/2+VDC/22=VDC2.


### 3.2.2. Considering the Circuit with Primary Circuit (S7 and S8: ON)

As can be observed, the common-mode voltage for each state is different from the other ones, which creates common-mode current according to equation (5). Therefore, a balancing circuit is required. In this case, depending on the location of shading and ambient temperature (upper or lower subarrays), the mismatch effect on the common-mode current can be eliminated by switching switches S7 or S8. It is worth mentioning that switching of these two switches is independent of other circuit components.When the mismatch occurs on thePVs, the circuit has six modes of operation (see Figures 6 and 7). Assuming that the shading falls on the upper PV, common-mode voltages for these six states are as follows:Figure 6
Mismatch operating modes (VAB = VDC). (a) L2 charging; (b) L2 discharging.
(a)(b)Figure 7
Mismatch operating modes (VAB = 0). (a) L2 charging; (b) L2 discharging.
(a)(b)StateB-1: switches S1, S4, S5, and S6 are on. Here, VAN is equal to VDC and VBN is equal to 0, and the output voltage is equal to VDC. By turning switch S8, L2 inductor current begins to increase (see Figure 6(a)).StateB-2: like the first state, switches S1, S4, S5, and S6 are on, and VDC = VAN, VBN = 0, and the output voltage is VAB = VDC. Here, by turning switch S8 off, inductor L2 which is charged by the lower subarray will be discharged on capacitor C1 and cause an increase in capacitor voltage (see Figure 6(b)).StateB-3: according to Figure 7(a), switches S1, S2, and S6 and diode D3 are on, and PV is disconnected from the grid for freewheeling. Here, VAN and VBN are equal to VDC/2 and output voltage is 0. Here, by turning switch S8 on, inductor L2 is charged by capacitor C2.StateB-4: Like state 3, switches S1, S2, and S6 and diode D3 are on, VBN and VAN are equal to VDC/2, and the output voltage is 0. Here, by turning switch S8 off, inductor L2 which was previously charging begins to discharge in capacitor C1 (see Figure 7(b)).StateB-5: In this case, according to Figure 8(a), switches S2, S3, S5, and S6 are on. Here, VAN is 0 and VBN is equal to VDC, and the output voltage is equal to −VDC. In this state, by turning switch S8 on, inductor L2 is charged by capacitor C2.Figure 8
Mismatch operating modes (VAB = −VDC). (a) L2 charging; (b) L2 discharging.
(a)(b)StateB-6: In this case, like state 5, switches S2, S3, S5, and S6 are on, and VAN = 0, VBN = VDC, and VAB = −VDC. Here, by turning switch S8 off, inductor L2 is discharged in capacitor C1 (Figure 8(b)).As can be observed in all the above six states, regardless of the inverter conditions, the primary circuit can charge or dischargeL2 by turning S7 off and switching of S8. Therefore, it compensates the voltage drop caused by partial shading on the upper PV. The conceptual waveforms of gate signal of the switches, leg voltages, and common-mode voltage of all possible states are brought in Figure 9(a). The same procedure can be carried out for partial shading of lower subarray. In this case, signals of S1 and S4, S2 and S3, S5 and S6, and S8 and S7 will be replaced with each other (see Figure 9(b)).Figure 9
Mismatch operating modes diagram. (a) Shading on upperPV; (b) shading on lower PV.
(a)(b)


## 3.2.1. Considering the Circuit without Primary Circuit (S7 and S8: OFF)

If mismatch condition occurs at first subarray,VC1 is VDC/2 − ΔV and VC2 is VDC/2. Therefore, common-mode voltages at states A-1 to A-4 in mismatch condition will be as follows:(12)StateA−1:VCM=VAN+VBN2=VDC/2−ΔV+VDC/2+02=VDC−ΔV2,(13)StateA−2:VCM=VDC/2+VDC/22=VDC2,(14)StateA−3:VCM=VAN+VBN2=VDC/2−ΔV+VDC/2+02=VDC−ΔV2,(15)StateA−4:VCM=VDC/2+VDC/22=VDC2.


## 3.2.2. Considering the Circuit with Primary Circuit (S7 and S8: ON)

As can be observed, the common-mode voltage for each state is different from the other ones, which creates common-mode current according to equation (5). Therefore, a balancing circuit is required. In this case, depending on the location of shading and ambient temperature (upper or lower subarrays), the mismatch effect on the common-mode current can be eliminated by switching switches S7 or S8. It is worth mentioning that switching of these two switches is independent of other circuit components.When the mismatch occurs on thePVs, the circuit has six modes of operation (see Figures 6 and 7). Assuming that the shading falls on the upper PV, common-mode voltages for these six states are as follows:Figure 6
Mismatch operating modes (VAB = VDC). (a) L2 charging; (b) L2 discharging.
(a)(b)Figure 7
Mismatch operating modes (VAB = 0). (a) L2 charging; (b) L2 discharging.
(a)(b)StateB-1: switches S1, S4, S5, and S6 are on. Here, VAN is equal to VDC and VBN is equal to 0, and the output voltage is equal to VDC. By turning switch S8, L2 inductor current begins to increase (see Figure 6(a)).StateB-2: like the first state, switches S1, S4, S5, and S6 are on, and VDC = VAN, VBN = 0, and the output voltage is VAB = VDC. Here, by turning switch S8 off, inductor L2 which is charged by the lower subarray will be discharged on capacitor C1 and cause an increase in capacitor voltage (see Figure 6(b)).StateB-3: according to Figure 7(a), switches S1, S2, and S6 and diode D3 are on, and PV is disconnected from the grid for freewheeling. Here, VAN and VBN are equal to VDC/2 and output voltage is 0. Here, by turning switch S8 on, inductor L2 is charged by capacitor C2.StateB-4: Like state 3, switches S1, S2, and S6 and diode D3 are on, VBN and VAN are equal to VDC/2, and the output voltage is 0. Here, by turning switch S8 off, inductor L2 which was previously charging begins to discharge in capacitor C1 (see Figure 7(b)).StateB-5: In this case, according to Figure 8(a), switches S2, S3, S5, and S6 are on. Here, VAN is 0 and VBN is equal to VDC, and the output voltage is equal to −VDC. In this state, by turning switch S8 on, inductor L2 is charged by capacitor C2.Figure 8
Mismatch operating modes (VAB = −VDC). (a) L2 charging; (b) L2 discharging.
(a)(b)StateB-6: In this case, like state 5, switches S2, S3, S5, and S6 are on, and VAN = 0, VBN = VDC, and VAB = −VDC. Here, by turning switch S8 off, inductor L2 is discharged in capacitor C1 (Figure 8(b)).As can be observed in all the above six states, regardless of the inverter conditions, the primary circuit can charge or dischargeL2 by turning S7 off and switching of S8. Therefore, it compensates the voltage drop caused by partial shading on the upper PV. The conceptual waveforms of gate signal of the switches, leg voltages, and common-mode voltage of all possible states are brought in Figure 9(a). The same procedure can be carried out for partial shading of lower subarray. In this case, signals of S1 and S4, S2 and S3, S5 and S6, and S8 and S7 will be replaced with each other (see Figure 9(b)).Figure 9
Mismatch operating modes diagram. (a) Shading on upperPV; (b) shading on lower PV.
(a)(b)


## 3.3. Switching Method

When the insolation level and ambient temperature of subarrayPV1 are different from those of PV2, the MPP parameters of the two subarrays differ from each other. By considering that both subarrays are operating at their respective MPP and neglecting the losses incurred in power processing stages, the average power involved with C1 and C2 (PC1 and PC2) over a cycle can be assumed equal to the power extracted from PV1 and PV2. Therefore,(16)PC1+PC2=PPV1+PPV2.The average power injected to the grid,Pg, can be written as(17)Pg=PPV1+PPV2,and(18)Pg=VgridIgridcosφ=12VmImcosφ,where Vm and Im are the amplitude and current of the grid voltage (vgrid and Igrid), respectively. The relation of output and input voltage of inverter can be expressed as(19)Vm=maVC1+VC2,where ma is the modulation index of the inverter.By combining the above equations, the power injected to the grid can be expressed as(20)Pg=12maVC1+VC2Imcosφ=PPV1+PPV2.Hence,(21)PPV1=12maVC1Imcosφ.Similarly,(22)PPV2=12maVC2Imcosφ.Therefore,(23)VC1=2PPV1maImcosϕ,(24)VC2=2PPV2maImcosϕ.By combining (20), (21), and (22),(25)VC1=VmPPV1maPPV1+PPV2,(26)VC2=VmPPV2maPPV1+PPV2.Based on the above equations, the control strategy of the proposed scheme is shown in Figure10.Figure 10
Control strategy of S8 and S9 of the proposed structure.In this control strategy, both subarrays operate at their corresponding MPPT simultaneously. Two separate MPP trackers are employed to determine the values ofPV1 and PV2, which are required to estimate VC1 and VC2. Using (25) and (26), VC1 and VC2 are estimated [4, 28]. VC1 and VC2 are compared to Vref2 (which in this case is 200 V) and after two separate PI controllers and a PWM block for every two, S7 and S8 are determined. Hence, two voltage sensors that otherwise would have been required to determine VC1 and VC2 get eliminated.The switching method of the presented circuit is unipolar SPWM which is displayed in Figure11. First (second) cycles occur when the shading falls on upper (lower) PV, where Vc is triangular waveform and Vref is reference waveform which is obtained as feedback from the grid. By comparing these two waveforms, depending on where the mismatch occurs, the switching method of switches is determined. Control method of the circuit is shown in Figure 12.Figure 11
Basic modulation strategy of the proposed topology.Figure 12
Proposed topology control strategy.Switching states of S7 and S8 are directly determined by Figure 10.


## 3.4. Stability

Given Table1 and Figure 13, new Sa, Sb, and Sc functions are defined for switching of the proposed inverter.(27)Sa=S1−S2,(28)Sb=S2−S1,(29)Sc=S4−S3,(30)Sd=S3−S2,(31)Se=S1−S4,Table 1
Switching states and terminal voltages.
VoutS1S2S5S6SaSbScSdSeS8 onS8 off+110111−1010C1 chargingC1 discharging01101001−10C1 chargingC1 discharging−10111−1100−1C1 chargingC1 dischargingFigure 13
Schematic of the proposed inverter.and, using Table1 and Figure 13, the inverter model can be written as(32)Vout=SaVDC+SbVC1+ScVC2+SdVL1+SeVL2.The capacitors dynamics are expressed as(33)IC1=C1dvC1dt=−Sbig+ScIL2,(34)IC2=C2dvC2dt=−Sbig+ScIL1,and the inductors dynamics are expressed as(35)VL1=SbVC1−ScVC2,(36)diL1dt=1L1SbVC1−ScVC2,(37)VL2=ScVC2−SbVC1,(38)diL2dt=1L2ScVC2−SbVC1,while the grid model and the current dynamics can be written as(39)digdt=1Lg−rgig+1LgVout−Vg.One can define the grid current error asX1 = ig − ig∗, where ig∗ represents the grid current reference signal. Similarly, the capacitors voltage errors may be defined as X2 = VC1 − VC1∗ and X3 = VC2 − VC2∗, where VC1∗ and VC2∗ are constant DC voltages. The inductors current errors may be defined as X4 = IL1 − IL1∗ and X5 = IL2 − IL2∗, where IL1∗ and IL2∗ are constant DC currents.From the above equations, the current error derivative can be written asx1. = dig/dt−dig∗/dt.Using (13), ig = X1 + ig∗, VC1 = X2 + VC1∗, VC2 = X3 + VC2∗, IL1 = X4 + IL1∗, and IL2 = X5 + IL2∗, one can obtain(40)x1.=1LgSaVDC+SbX2+VC1∗+ScX3+VC2∗+SdSbX2+VC1∗−ScX3+VC2∗++SeScX3+VC2∗−SbX2+VC1∗−rgX1+ig∗+Vg+Lgdigdt.Similarly, after substituting the expressions ofig = X1 + ig∗, IL1 = X4 + IL1∗, and IL2 = X5 + IL2∗ in (7) and (8), the capacitors voltage errors may be written as(41)x2.=1C1_Sbig+ScIL2=−1C1SbX1+ig∗+ScX5+IL2∗,(42)x3.=1C2_Sbig+ScIL1=−1C2SbX1+ig∗+ScX4+IL1∗.Similarly, after substituting the expressions ofVC1 = X2 + VC1∗ and VC2 = X3 + VC2∗ in (10) and (12), the inductors current errors may be written as(43)x4.=1L1SbX2+VC1∗−ScX3+VC2∗.(44)x5.=1L2ScX3+VC2∗−SbX2+VC1∗.The Lyapunov function can be defined in terms of system state errors, represented by vectorx. Assume that the equilibrium of controlled system is at the origin x = 0. When the energy function becomes zero, the system is settled at the equilibrium point, and if the energy function is rapidly increasing, then the system is unstable, and it is asymptotically stable if the energy is decreasing. The stability of a system is guaranteed if the following conditions hold:(1)
V (x) is positive definite(2)
−V(x) is negative definite(3)
V (x) goes to ∞ as ǀxǀ ∞A Lyapunov function in terms of system’s errors is suggested as follows:(45)vx=12a1x12+12a2x22+12a3x32+12a4x42+12a5x52,where α1 and α2 are real positive numbers, which must be properly selected. It is clear that the above function is positive definite. Lyapunov control theory states that stability of the controlled system presented above is guaranteed if we ensure that, for all values of x, v˙x<0.Derivative of (45) with respect to time yields(46)v˙x=a1x1x˙1+a2x2x˙2+a3x3x˙3+a4x4x˙4+a5x5x˙5.Using equations (40)–(44) in (46), one can getv˙x = X1X2 (α1SbSd−Se/Lg − α2Sb/C1) + X1X3 (α1ScSe−Sd/Lg − α3Sb/C2) − X2X5 (α2Se/C1 + α5Sb/L2) − X3X4 (α3Sd/C2 + α4Sc/L1) + X2X4 (α2Sd/C1 + α4Sb/L1) + X3X5 (α5Sc/L2+α3Se/L2) − X12α1rg/Lg+X1 (α1VDC+VC1∗Sb+SdSb+SeSb+VC2∗Sc+ScSd+SeSd−rgig∗−Vg/Lg−α1dig∗/dt) + X2 (α2−Sbig∗+SdiL1∗+SeiL2∗/C1) + X3 (α3−Sbig∗+SdiL1∗+SeiL2∗/C2) + X4 (α4SbvC1∗−ScVC2∗/L1) + X5 (α5ScvC2∗−SbVC1∗/L2) (36).In order to eliminateX1X2, X1X3, X2X5, X3X4, X2X4, and X3X5 terms, gains are chosen to satisfy(47)α1=LgC1Sd−Seα2,(48)α3=ScC2Se−SdLgSbα1,(49)α2=−SbC1L2Seα5,(50)α3=−ScC2SdLe1α4,(51)α4=−SdL1C1Sbα2,(52)α4=−SeScα2.After eliminatingX1X2, X1X3, X2X5, X3X4, X2X4, and X3X5 terms, we have(53)v˙x=−X12α1rgLg+X1α1VDC+VC1∗Sb+SdSb+SeSb+VC2∗Sc+ScSd+SeSd−rgig∗−VgLg−α1dig∗dt+X2α2−Sbig∗+SdiL1∗+SeiL2∗C1+X3α3−Sbig∗+SdiL1∗+SeiL2∗C2+X4α4SbvC1∗−ScVC2∗L1+X5α5ScvC2∗−SbVC1∗L2.Then we have(54)v˙x=−X12α1rgLg+X1α1VDC+VC1∗Sb+SdSb+SeSb+VC2∗Sc+ScSd+SeSd−rgig∗−VgLg︸λ1X1−α1dig∗dt+X2α2−Sbig∗+SdiL1∗+SeiL2∗C1︸λ2X2+X3α3−Sbig∗+SdiL1∗+SeiL2∗C2︸λ3X3+X4α4SbvC1∗−ScVC2∗L1︸λ4X4+X5α5ScvC2∗−SbVC1∗L2︸λ5X5.In order to makev˙x<0,(55)λ1−α1rgLg,λ2,λ3,λ4,λ5<0.


## 3.5. Reliability

Reliability evaluation of the proposed converter circuit is presented using Markov approach. Note that hazard rates of power electronic components are only considered in their useful life and other phases such as debugging (which are related to manufacturing errors) and fatigue phases of the components are not considered in the analysis. Figure14 shows the Markov chain of the mentioned system, which is not employing any fault tolerant scheme.Figure 14
Markov chain of proposed topology.It has only three states:State1: proposed topology completely feeds power to the grid and eliminates common-mode current.State2: proposed topology completely feeds power to the grid but cannot eliminate the common-mode current.State3: failure.λ12 is expressed as(56)λ12=λS7+λS8+λD1+λD2+λL1+λL2,(57)λ23=∑i=06λSi+∑i=312λDi+λL3+λL4+2λC,(58)λ13=∑i=06λSi+∑i=312λDi+λL3+λL4+2λC.λS, λd, λL, and λC are the failure rates of switches, diodes, inductors, and capacitors, respectively, which are calculated as(59)λS=λbπTπAπQπE,(60)λd=λbπTπSπCπQπE,(61)λL=λbπCπQπE,(62)λC=λbπCVπQπE.For each component,λb, πQ, and πE are basic failure rate factor, quality factor, and environment factor of mentioned components, respectively. πA is the application factor of the switch. πcv and πC are capacitance factor and inductor construction factor, respectively. Also, πS is the electrical stress factor of the diode. Mentioned parameters can be easily extracted from [32] regarding the type of the component and its application. πT is the temperature factor for switches and diodes:(63)πTS=exp−19251TjS+273−1298,(64)πTd=exp−30911Tjd+273−1298.In the above two equations, TjS and Tjd are the junction temperatures of the switch and diode, respectively.(65)TjS=TA+RjAS×PLOSSS,(66)Tjd=TA+RjAd×PLOSSD.TA is the ambient temperature. PLOSSS and PLOSSD are the losses of the switch and diode, respectively. RjAS and RjAd are the junction ambient resistance. According to Figure 1 and mentioned equations, the probability of each state is calculated as(67)ddtP1tP2tP3t=P1tP2tP3tλ11λ12λ13λ21λ22λ23λ31λ32λ33,where P1, P2, and P3 are probabilities of states 1, 2, and 3, respectively. λ is the transition matrix, where(68)λ11=−λ12,λ22=−λ23,λ31=λ21=λ32=0.Assuming that the chain is started from state1, which is healthy state, the following initial condition occurs and the reliability is calculated as(69)P0=100.The reliability is calculated as(70)Rt=P1t+P2t,and the mean time to failure (MTTF) is obtained as(71)MTTF=∫0∞Rtdt.


## 4. Simulation and Experimental Results

To verify the accuracy of the performance of the presented circuit, the circuit is simulated in MATLAB using parameters in Table2 and then an experimental setup is implemented. The frequency of the proposed topology is 10 KHz, and L1 and L2 are the output filters. Control parameters are set as Kp = 20 and Ki = 30 and solar modules have been used in simulation.Table 2
Circuit parameters and devices used in simulation and experiment.
Parameter or devicesSymbolValue or modelSimulationExperimentInput voltageVDC1, VDC2200 V30 VInput capacitorsCin1, Cin2300µF330µFEquivalent parasitic capacitorCPv10 nF10 nFSwitching frequencyfsw10 KHz10 KHZBoost inductorsL1, L2830µH830µHDiodesD1,…,6—MU560SwitchesS1,…,8—IRF640BSimulation results are brought in Figures15–18. Insolation of PV2 is maintained at 100%, while insolation level of PV1 is at 50% and the temperature of PV1 is increased by 5°C. Figure 15 shows the voltages of VC1 and VPV1. Output voltage of inverter (Vout), VAN, and VBN are shown in Figures 16(a)–16(c), respectively. Figure 17 shows grid voltage and output current of inverter, respectively. According to Figure 18(a), common-mode voltage is constant on 200 V which causes the elimination of the common-mode current, as shown in Figure 18(b).Figure 15
Voltage ofPV1 and C1.Figure 16
(a)Vout, (b) VAN, and (c) VBN.
(a)(b)(c)Figure 17
Grid voltage (Vgrid) and current (ig).Figure 18
Common-mode simulation results. (a)VCM; (b) ICM.
(a)(b)Figure19 shows experimental results. The proposed topology is connected to the grid. However, due to some limitations in lab, the circuit is tested by the input voltage of 60 Volt, and, instead of using PV, DC source voltage is employed. Parasitic capacitor between PV and ground is replaced by an external capacitor (Cpv).Figure 19
Experimental results of proposed topology. (a)Vgrid, Igrid, and VAB. (b) VAN, VBN, and 2VCM. (c) Vgrid, VAB, and ICM.
(a)(b)(c)Figure19(a) shows the grid-connected voltage, current, and the output voltage of inverter (VAB). The Total Harmonic Distortion (THD) of the grid-connected voltage is 4.85%. Further, VAN, VBN, and 2VCM are shown in Figure 19(b). According to Figure 18(b), the common-mode voltage is constant, which causes the elimination of the common-mode current, as shown in Figure 19(c).For displaying waveforms, Gwinstek GDS-2204E oscilloscope and Gwinstek GOP-050 differential probe are applied. As can be observed in Figure19(b), VCM is 30 V and is constant in all cycles, which results in elimination of ICM.Figure20(a) shows performance of the transformerless inverter without proposed balancing stage during mismatched condition. As can be seen from this figure, the voltage of PV1 is dropped due to the different environmental condition. As a result, the output voltage of inverter (VAB) is decreased and the leakage current is increased to about 5 Amps.Figure 20
VPV1, VPV2, VAB, and ICM under partial shading condition. (a) VPV1 insolation = 33%, VPV2 insolation = 100% without balancing stage, (b) VPV1 insolation = 33%, and VPV2 insolation = 100% with balancing stage.
(a)(b)Figure20(b) illustrates the performance of the proposed topology with proposed balancing stage during mismatched condition. As can be seen from Figure 20(b), the voltage of PV1 is dropped due to the different ambient condition. However, because of proposed balancing stage, inverter output voltage (VAB) remains unchanged and the leakage current is eliminated.Figure21 shows the efficiency curve of the proposed inverter during mismatch condition for the ranges between 100 watts and 800 watts, where the peak of efficiency is 98.21%.Figure 21
Efficiency curve of the proposed inverter.In order to evaluate the performance of the proposed topology during mismatched condition, a 2.5 KW version of the proposed inverter is simulated. In this simulation, insolation ofPV2 is maintained at 100%, while insolation level of PV1 varies from 100% to 10%. The result is compared to the following inverters (which are simulated with the same condition): (1) H-bridge based inverter presented in [26] which has the highest efficiency reported in the literature and (2) inverters presented in [4, 5] which have capability of servicing two separate subarrays under mismatched atmospheric condition. Considering the fact that, among all topologies that are mentioned in this paper, those in [4, 5] are the only topologies that eliminate the leakage current under mismatch condition, the result of this comparison is shown in Figure 22. It can be inferred from this figure that although all of these topologies eliminate the leakage current, the proposed topology is the most effective among the mentioned topologies.Figure 22
Power fed to the grid by topology in [26], topology in [4], topology in [5], and proposed inverter during mismatched operating condition.


## 5. Conclusion

Mismatched environmental condition and common-mode current (in transformerless inverters) are the most important challenges faced in the applications of thePV arrays. Many structures have been proposed so far. In this paper, first, the partial shading and ambient temperature effect on the common-mode current are investigated. Then, a circuit was presented which can eliminate common-mode current in PV arrays connected to the grid with transformerless inverters in both normal and mismatched environmental conditions. Results of simulation and practical implementation of the proposed circuit prove the accuracy of the circuit performance.



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*Source: 3890731-2022-03-08.xml*