# A Novel Segmented Modeling Method of Via including the Effect of Power/Ground Plane Pair

Authors: Zhaowen Yan; Zhicai Ma; Guochang Shi; Mingming Che
Journal: International Journal of Antennas and Propagation
 (2013)

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## Abstract

This paper focuses on the modeling method of common interconnects which act as coupling channels in the analysis of PCB immunity. Fast modeling and parameters extraction of power/ground plane pair are realized using cavity resonance method. The calculated results of the model match with the simulation results of HFSS within 9 GHz, which demonstrates the effectiveness of the modeling method. Besides, segmented via modeling method including the effect of power/ground plane pair is proposed. In this modeling method, via structure is decomposed into three parts, and each part is modeled, respectively. The modeling of single via and differential vias in single plane pair and multilayer is completed using this method. High accuracy is reached due to the adoption of the effect of power/ground plane pair and the adoption of second-order circuit model of capacitance and inductance, where the parameters can be gotten from analytic formulas. Finally, considering an actual signal network, for example, the equivalent circuit model of the network, is established, and every part of the equivalent circuit model is imported into Designer for cosimulation. The results are consistent with the simulation results of HFSS within 9 GHz.


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## Body

## 1. Introduction

Modern design of electronic system has reached the GHz and UHF in frequency. The signal integrity, power integrity and electromagnetic compatibility problems are arising from high-speed products [1, 2]. With the continuous improvement of the density and speed of modern high-frequency circuits, the simulation technology of interconnect structure for chip-level, package-level, and board-level circuit design becomes more and more important.Power distribution network (PDN) is the largest and most complex interconnect structure in PCB layout. All devices of the system are connected to the PDN either directly or indirectly, and about 40 percent of the interconnect space is used for PDN layout. PDN provides a stable supply voltage for the chip and additionally acts as the return path of the signal line. The performance of PDN affects the quality of signal transmission directly. To analyze the effect of PDN to signal integrity, the basis is to model the power/ground plane pair accurately. Thus, the parasitic parameters of electromagnetic field are found, the EMC problems caused by the resonant characteristics can be reduced, and the circuit stability is improved.Via is an important interconnection structure. In the design of the high-frequency circuit of the multilayer PCB (GHz and above), the parasitic parameters of signal via have a certain impact on signal integrity, and its effect has become one of the key constraint factors of high-speed PCB design. It may cause the failure of the entire design in case of improper handling. Via modeling plays an important role in the field of microwave and signal integrity. Via modeling approach can be broadly divided into(1) quasistatic method; (2) full-wave simulation method; (3) field-based analysis method; (4) physics-based via modeling. Quasistatic method is applied to the case of the low frequency and it is well studied now. FEM, FDTD, and TML are used for full-wave simulation method to complete modeling and study via characteristics. The full-wave simulation method provides much accurate result of via features of PCB and packages because of its high accuracy compared to other methods. However, full-wave simulation needs longer timed and it is not favorable to optimize the design. Although some full-wave analytical methods are fairly accurate, they need a lot of calculations and their speed is very slow, for example, the finite difference time domain method [3, 4]. Some methods are very simple and fast, but they are not precise enough for the analysis of complex high-frequency circuits, for example, the semi-quasistatic method and physics-based method [5, 6]. Field-based analysis method and physics-based via modeling method are currently very popular compared to the other two methods. The physical concepts of the method are clear, the simulation is fast, and it is suitable for Spice simulators. Zhang and Fan have done related researches aimed at the method [7–12]. Their modeling adopts the first-order capacitance circuit model combined with the impedance characteristics of power/ground plane pair in the center of via.In [7], a physics-based via-plane model combined with transmission lines models for traces is used. Differential via transition measurements are presented and compared with simulations results of an equivalent circuit model. The differential circuit model is composed of four main parts: transmission lines, transmission line-to-via transition, antipad capacitances, and cavities. The paper shows that the process of modeling can require a series of adjustments to get reasonable results. In [8], an analytical formula using electromagnetic analysis for the evaluation of the via-plate capacitances is derived. They correspond to different via transition structures. The via-plate capacitances are for vias crossing at least one plate pair, while the excess capacitances are parasitics for vias crossing a single plate from one side to the other. In [9], vias are modeled using an analytical formulation for the parallel-plate impedance and capacitive elements, whereas the trace-via transitions are described by modal decomposition. Different scenarios are analyzed including thru-hole and buried vias, power vias, and coupled traces routed into different layers. In [10], the physics-based via model and the intrinsic via model are investigated and compared, and the insights toward their limitations in practical engineering applications are gained. The accuracy of the improved intrinsic via model and the conventional physics-based via model is studied by comparing them with either an analytical formula or numerical simulations for a via in a circular plate pair with various edge boundary conditions. In [11], an efficient microwave network method is proposed for signal and power integrity analysis of a multilayer printed circuit board. The admittance matrix of a single plate pair with ports defined in via holes both on top and bottom plates is obtained through the intrinsic via circuit model and impedance matrix between two plates. A recursive algorithm is provided to obtain the combined admittance matrix of two layers of plate pair coupled through via holes on a common plate. Reference [12] proposes an efficient analytical method for assembling the S-parameter networks describing each block of the physics-based via model. This technique is suitable to construct and simulate the model for SI and PI analyses of a complex multilayer PCB with multiple vias.On the basis of the methods discussed in the previous paragraph, combined with the microwave network theory, a segmented via modeling method including the effect of power/ground plane pair is proposed in this paper. Fast modeling and parameters extraction of power/ground plane pair are realized by using cavity resonance method firstly. The resonance effect of the parallel-plate is considered firstly because of the serious impact of cavity resonance characteristics on the transmission quality of via. In the modeling, the resonance effect is reflected by combining the impedance of power/ground plane pair with the circuit model of via. Then, via model is further decomposed into the following three parts:(1) the vertical conversion structure of the top-level transmission line to via; (2) the vertical via structure of the middle multilayer; (3) the vertical conversion structure of via to the bottom transmission line. The inductance part is introduced aiming at overcoming the shortage of first-order capacitance circuit model. Each part has been modeled accurately by using the LC second-order circuit, and then, each part of the equivalent circuit is cascaded. The capacitance and inductance parameters are extracted by the corresponding analytical formulas.The modeling of single via and differential vias in single plane pair and multilayer is constructed as examples. In order to verify the validity and accuracy of the method, the results of the models are compared with full-wave simulation results of HFSS as well as the first-order full-capacitance circuit model. Results show that via modeling method has more explicit physical meaning. It simplifies the complexity of the modeling and shortens the calculation time. The frequency application scope of the model reaches 10 GHz with higher accuracy in high frequency. The phase characteristics are also well matched with the full-wave simulation results. The amplitude and phase characteristics can be verified by the feature selective validation (FSV) technique [13–15]. The FSV method is a technique to allow the objective, quantified comparison of data for inter aliavalidation of computational electromagnetics. The FSV method does this by comparing the data using a reliability function-like heuristic, producing an assessment that offers tiered information from a single overall numerical analysis to a detailed point-by-point review of the data concentrating on either the individual features or the trends. Further, a conversion has been proposed that provides a natural-language equivalent of the quantitative numerical output [14]. The FSV verification results of this paper will be published in a subsequent paper.


## 2. Modeling of Power/Ground Plane Pair

The main shortcoming and negative effect of the power/ground plane pair structure is its performance as the resonant cavity for electromagnetic wave. The cavity characteristics of power/ground plane pair will severely affect the transmission quality of via. Accurate modeling for the power/ground plane pair is must for achieving high-precision modeling of via. It is used to improve the circuit stability by obtaining its parasitic effects of electromagnetic fields and reducing the electromagnetic radiation of high-speed circuit.


### 2.1. The Resonance Characteristics

The power/ground plane pair can be modeled as a waveguide. When the electromagnetic wave propagates to the boundary where there is a discontinuous point, it will produce a reflection, and it will result in the generation of resonance phenomenon. As shown in Figure1, the power plane can be seen as a cavity or resonant network that consists of inductance and capacitance. The resonance will occur in a certain frequency range. The edge effect of power plane and ground plane (i.e., the reflection and radiation of the edge) is also a problem which is needed to pay attention to. The standing wave of the cavity will cause serious coupling in near circuit and interconnects.Figure 1
Resonance effect and edge effect.When a via thrills through the power/ground plane pair, the transmission quality of signal will suffer if the via is located in place with high impedance since the power/ground plane pair constitutes a return path of via. In this case, the impedance of return path is equal to the input impedance of places where via locates. When the input impedance is large, it will cause impedance mutation on the return path, which leads to a variety of signal integrity problems. At the same time, the return path will inject energy to the power/ground plane pair, resulting in an reverse resonance. But if the via is located in places of the smallest impedance, it will not cause discontinuities of via return path. Therefore, optimizing the location of via can lead to avoiding the affection of some resonant modes.


### 2.2. Modeling of Integrated Rectangular Plane Pair

Figure2 shows a rectangular power/ground plane pair. It is placed in a three-dimensional Cartesian coordinate system for easy description of various physical parameters, setting a vertex of the bottom of the plate for the origin of coordinate. The length of the parallel-plate is a, the width is b, the medium thickness is h, and the location coordinates of the two ports port1 and port2, are (xi,yi) and (xj,yj), respectively.Figure 2
Integrated rectangular plane pair.The input impedanceZpp is closely related to boundary conditions of the plates. Commonly, the actual circuit has three kinds of boundary conditions which are as follows.(1)
Perfect Magnetic Conductor boundary (also known as the PMC boundary), which can be used to model a finite parallel-plate as electrically open.(2)
Perfect Electrical Conductor boundary (also known as the PEC boundary), which can be used to model a finite parallel-plate as electrically short.(3)
Perfectly Matched Layer boundary (also known as PML boundary), which can be used to model an infinite plate or a parallel-plate that can be regarded as infinite.For PEC and PMC boundaries, the impedance of parallel-plate is calculated as follows [16]:
(1)Zij(ω)=jωμdab·∑m=0∞∑n=0∞Cm2·Cn2·Fboundary·Fport(mπ/a)2+(nπ/b)2-k2,
where
(2)Fboundary={cos(mπxia)·cos(mπxja)·cos(nπyib)·cos(nπyjb)forPMCsin(mπxia)·sin(mπxja)·sin(nπyib)·sin(nπyjb)forPEC,Fport=sinc(mπWxi2a)·sinc(mπWyi2a)·sinc(nπWxi2b)·sinc(nπWyi2b),k=ωε0εrμ(1-jtanδ+(2/ωμσ/d)2),
where j is the imaginary unit, ω is the angular frequency, μ is the permittivity of the dielectric material, k is the phase velocity, d is the spacing between parallel-plate, a and b are the length and width of the plate, and (xi,yi) and (xj,yj) are the location coordinates of any two points on the plate. Wx and Wy are used to characterize the port size where m,n=0,1,2,…, Cm=Cn=1 when m and n are equal to zero and Cm=Cn=2 for others. Fboundary includes the boundary conditions of parallel-plate and the port position coordinates on the parallel-plate. Fport includes the physical size of the port. For rectangular cross-section port, Wx and Wy are the length and width of its cross-section, respectively. The surrounding boundary conditions and the metal plates on and underside the substrate material form the resonant cavity structure when plate spacing is very small. Its resonant frequency can be calculated as
(3)f(m,n)=12πμε(mπa)2+(nπb)2,
where integer m and integer n stand for the resonant mode. The maximum of Zij corresponds to the resonant frequency.For Perfectly Matched Layer boundary (PML), which is applied for fully absorbing boundary or boundary that locates at infinity, the input impedance of parallel-plate is independent of the parallel-plate size and the port location. The impedance can be calculated as(4)Zpp=jηd2πρ0·H0(2)(kρ0)H1(2)(kρ0).The above equation is defined in cylindrical coordinates, whereη=με is the intrinsic impedance of the substrate material, H0(2) and H1(2) are zero-order and first-order Hank function of class 2, and ρ0 is the radius of the cylindrical port. For rectangular port with cross-section shape of Lx×Ly, ρ0 can be approximately taken as (Lx+Ly)/π.


### 2.3. Example of Modeling of Power/Ground Plane Pair

As shown in Figure2, the plate dimensions are shown as follows, a=1600 mil, b=1400 mil, h=63.3 mil, the location of the two ports are (800 mil, 675 mil) and (800 mil, 725 mil), respectively, the coordinate origin locates in the lower left vertices, and port size is 10 × 10 mil. The simulation results of self-impedance and mutual impedance by MATLAB are shown in Figure 3. It is easy to see that the calculations of equivalent circuit and simulation results of full-wave HFSS are well matched.The curves of impedance parameters of integrated rectangular plate based on resonant cavity method.
(a)
Z
11 amplitude
(b)
Z
21 amplitude


## 2.1. The Resonance Characteristics

The power/ground plane pair can be modeled as a waveguide. When the electromagnetic wave propagates to the boundary where there is a discontinuous point, it will produce a reflection, and it will result in the generation of resonance phenomenon. As shown in Figure1, the power plane can be seen as a cavity or resonant network that consists of inductance and capacitance. The resonance will occur in a certain frequency range. The edge effect of power plane and ground plane (i.e., the reflection and radiation of the edge) is also a problem which is needed to pay attention to. The standing wave of the cavity will cause serious coupling in near circuit and interconnects.Figure 1
Resonance effect and edge effect.When a via thrills through the power/ground plane pair, the transmission quality of signal will suffer if the via is located in place with high impedance since the power/ground plane pair constitutes a return path of via. In this case, the impedance of return path is equal to the input impedance of places where via locates. When the input impedance is large, it will cause impedance mutation on the return path, which leads to a variety of signal integrity problems. At the same time, the return path will inject energy to the power/ground plane pair, resulting in an reverse resonance. But if the via is located in places of the smallest impedance, it will not cause discontinuities of via return path. Therefore, optimizing the location of via can lead to avoiding the affection of some resonant modes.


## 2.2. Modeling of Integrated Rectangular Plane Pair

Figure2 shows a rectangular power/ground plane pair. It is placed in a three-dimensional Cartesian coordinate system for easy description of various physical parameters, setting a vertex of the bottom of the plate for the origin of coordinate. The length of the parallel-plate is a, the width is b, the medium thickness is h, and the location coordinates of the two ports port1 and port2, are (xi,yi) and (xj,yj), respectively.Figure 2
Integrated rectangular plane pair.The input impedanceZpp is closely related to boundary conditions of the plates. Commonly, the actual circuit has three kinds of boundary conditions which are as follows.(1)
Perfect Magnetic Conductor boundary (also known as the PMC boundary), which can be used to model a finite parallel-plate as electrically open.(2)
Perfect Electrical Conductor boundary (also known as the PEC boundary), which can be used to model a finite parallel-plate as electrically short.(3)
Perfectly Matched Layer boundary (also known as PML boundary), which can be used to model an infinite plate or a parallel-plate that can be regarded as infinite.For PEC and PMC boundaries, the impedance of parallel-plate is calculated as follows [16]:
(1)Zij(ω)=jωμdab·∑m=0∞∑n=0∞Cm2·Cn2·Fboundary·Fport(mπ/a)2+(nπ/b)2-k2,
where
(2)Fboundary={cos(mπxia)·cos(mπxja)·cos(nπyib)·cos(nπyjb)forPMCsin(mπxia)·sin(mπxja)·sin(nπyib)·sin(nπyjb)forPEC,Fport=sinc(mπWxi2a)·sinc(mπWyi2a)·sinc(nπWxi2b)·sinc(nπWyi2b),k=ωε0εrμ(1-jtanδ+(2/ωμσ/d)2),
where j is the imaginary unit, ω is the angular frequency, μ is the permittivity of the dielectric material, k is the phase velocity, d is the spacing between parallel-plate, a and b are the length and width of the plate, and (xi,yi) and (xj,yj) are the location coordinates of any two points on the plate. Wx and Wy are used to characterize the port size where m,n=0,1,2,…, Cm=Cn=1 when m and n are equal to zero and Cm=Cn=2 for others. Fboundary includes the boundary conditions of parallel-plate and the port position coordinates on the parallel-plate. Fport includes the physical size of the port. For rectangular cross-section port, Wx and Wy are the length and width of its cross-section, respectively. The surrounding boundary conditions and the metal plates on and underside the substrate material form the resonant cavity structure when plate spacing is very small. Its resonant frequency can be calculated as
(3)f(m,n)=12πμε(mπa)2+(nπb)2,
where integer m and integer n stand for the resonant mode. The maximum of Zij corresponds to the resonant frequency.For Perfectly Matched Layer boundary (PML), which is applied for fully absorbing boundary or boundary that locates at infinity, the input impedance of parallel-plate is independent of the parallel-plate size and the port location. The impedance can be calculated as(4)Zpp=jηd2πρ0·H0(2)(kρ0)H1(2)(kρ0).The above equation is defined in cylindrical coordinates, whereη=με is the intrinsic impedance of the substrate material, H0(2) and H1(2) are zero-order and first-order Hank function of class 2, and ρ0 is the radius of the cylindrical port. For rectangular port with cross-section shape of Lx×Ly, ρ0 can be approximately taken as (Lx+Ly)/π.


## 2.3. Example of Modeling of Power/Ground Plane Pair

As shown in Figure2, the plate dimensions are shown as follows, a=1600 mil, b=1400 mil, h=63.3 mil, the location of the two ports are (800 mil, 675 mil) and (800 mil, 725 mil), respectively, the coordinate origin locates in the lower left vertices, and port size is 10 × 10 mil. The simulation results of self-impedance and mutual impedance by MATLAB are shown in Figure 3. It is easy to see that the calculations of equivalent circuit and simulation results of full-wave HFSS are well matched.The curves of impedance parameters of integrated rectangular plate based on resonant cavity method.
(a)
Z
11 amplitude
(b)
Z
21 amplitude


## 3. Segmented Modeling Method of Via

### 3.1. Overview of the Modeling Method

The effect of via switching on signal transmission quality must be considered in the high-frequency field. The most important factor that impacts the performance of via switching is the resonant cavity generated by power/ground plane pair. The characteristics of power/ground plane pair have seriously hampered the transmission performance over via, especially in the vicinity of the resonance point [17]. Therefore, the resonator effect of parallel-plate is considered firstly in the modeling method used in this paper. Figure 4 is a flow chart of via modeling method used in this paper.Figure 4
Flowchart of segmented via modeling method.As shown in Figure5, a single via structure is decomposed in the center position of each plate (the same with decomposition of the differential vias). The decomposition creates mainly three parts: (1) the vertical conversion structure of the top-level transmission line to via; (2) the vertical via structure of the middle multilayer; (3) the vertical conversion structure of via to the bottom transmission line. Each part has been modeled accurately using the LC second-order circuit. The capacitance and inductance parameters are extracted by the corresponding analytical formulas (see Section 2.2). The first part and third part are of the similar structure, so the same method can be used for modeling. The established equivalent circuit model of the vertical conversion structure is shown in Figure 6.Figure 5
Diagram of single via structure decomposition.Equivalent circuit of top (bottom) layer microstrip to the upper (lower) part of the via vertical conversion structure.
(a)
Single via
(b)
Differential viasFor the modeling of multilayer, the resonator effect of parallel-plate on the transmission performance of via has been considered firstly in the modeling process. In doing so, the first step of the solution is to extract the impedance model of plane pair at the center of via circle; then, add the model to the second-order circuit model of via, and finally, simulate and seek solution in ADS. The final equivalent circuit model of the vertical via structure in multilayer is shown in Figure7.Equivalent circuit model of the vertical via structure in multilayer.
(a)
Single via
(b)
Differential vias


### 3.2. Parameter Extraction

The parameters of equivalent circuit of via can be solved by using the corresponding analytical formulas [8, 18–20]. Among them, the capacitance of via to plate surface is mainly divided into three parts: the capacitance of via pad to plate, the capacitance of middle cylinder to plate, and the capacitance of up/down cylinder to plate, respectively. It is shown in Figure 8.Figure 8
Capacitance of via for each part.The formulas of capacitance for each part are shown as follows. The capacitance of via pad to plate is expressed as (5). The first part of (5) is the coaxial capacitance between the pad and reference plane because of a certain thickness of the pad. The capacitance of the middle cylinder to plate is expressed as (6). The plate thickness d can be ignored in the calculation of (6), because the calculation of (5) has already considered the influence of plate thickness. The h in (6) is the height of the cylinder in the middle of via, and v is the number of segments which the middle column is divided into. The capacitance of up/down cylinder to plate is expressed as (7). In (7), the impact of d can also be ignored. The h is the height of the up/down cylinder of via. The calculation part of DIII is the stray capacitance of the pad to plate, so here the dielectric constant should be the dielectric constant of the air ε0. In (5) to (7), rantipad  is antipad radius, rpad  is pad radius, and rviabody  is via radius. Consider
(5)Cpad=2πdε0εrln(rantipad/rpad)+1.4ε0εrrpad{rantipad-rpadln(rantipad/rpad)}2×{π20.985rpad(rantipad-rviabody)Λ(rantipad/rpad-1)2-4ln(sin(φ)-1)(1φsin(2φ))2(rantipad-rviabody)Λ(rantipad/rpad-1)2},
where
(6)φ=π2(rantipad-rpadrantipad-rviabody),Λ=((χ01(rpadrviabody))}2{J0(χ01)N0(χ01(rpadrviabody))-N0(χ01)J0(χ01(rpadrviabody))}2)×((J02(χ01)J02(χ01(rantipad/rviabody)))-1)-1,χ01=3.1rantipad/rviabody-1,Cviabody=B(2πε0εrln(rantipad/rviabody)),
where
(7)B=∑p=1v(h+d)(rantipad-rviabody)v((h/2)-(p-1)(h/2v))2+(rantipad-rviabody)2,Ctop/bottom=A[DΙ+DΙΙ+DΙΙΙ],
where
(8)A=2πε0εrln(rantipad/rviabody),DΙ=∑p=1v(h+d)(rantipad-rviabody)v(h-(p-1)(h/v))2+(rantipad-rviabody)2,DΙΙ=∑p=1v(((rpad-rviabody)v))2)-1/2)-1((h2+(rantipad-rpad)2)(rpad-rviabody))×(v((rpad-rviabody)v))2)1/v(((rpad-rviabody)v))2h2+(((rpad-rviabody)v)(rantipad-rpad)+(p-1)×((rpad-rviabody)v))2)1/2)-1),DΙΙΙ=∑p=1v(h2+(rantipad-rpad)2)dv(rantipad-rpad)2+(h+((p-1)d/v))2.
For the signal via, we have
(9)Csignalvia=3Cpad+2Cviabody+2Ctop/bottom.For an interplane return via, we have(10)Creturnvia=2ADΙ+2πdε0εrln(rantipad/rreturnvia).For differential vias, the mutual capacitance of vias can be calculated by(11)Cmutualcapacitance=hπε0εrln{(s/2rviabody)[1+1-(2rviabody/s)2]}.
Here, s is the distance between differential vias.The self-inductance and mutual inductance between the various parts of via are calculated by(12)Lij=5.08{ln((hs)+1+(hs)2)-(1+(sh)2)+(sh)},
where h is the height of via and s is equal to the radius of via when the self-inductance is calculated.


## 3.1. Overview of the Modeling Method

The effect of via switching on signal transmission quality must be considered in the high-frequency field. The most important factor that impacts the performance of via switching is the resonant cavity generated by power/ground plane pair. The characteristics of power/ground plane pair have seriously hampered the transmission performance over via, especially in the vicinity of the resonance point [17]. Therefore, the resonator effect of parallel-plate is considered firstly in the modeling method used in this paper. Figure 4 is a flow chart of via modeling method used in this paper.Figure 4
Flowchart of segmented via modeling method.As shown in Figure5, a single via structure is decomposed in the center position of each plate (the same with decomposition of the differential vias). The decomposition creates mainly three parts: (1) the vertical conversion structure of the top-level transmission line to via; (2) the vertical via structure of the middle multilayer; (3) the vertical conversion structure of via to the bottom transmission line. Each part has been modeled accurately using the LC second-order circuit. The capacitance and inductance parameters are extracted by the corresponding analytical formulas (see Section 2.2). The first part and third part are of the similar structure, so the same method can be used for modeling. The established equivalent circuit model of the vertical conversion structure is shown in Figure 6.Figure 5
Diagram of single via structure decomposition.Equivalent circuit of top (bottom) layer microstrip to the upper (lower) part of the via vertical conversion structure.
(a)
Single via
(b)
Differential viasFor the modeling of multilayer, the resonator effect of parallel-plate on the transmission performance of via has been considered firstly in the modeling process. In doing so, the first step of the solution is to extract the impedance model of plane pair at the center of via circle; then, add the model to the second-order circuit model of via, and finally, simulate and seek solution in ADS. The final equivalent circuit model of the vertical via structure in multilayer is shown in Figure7.Equivalent circuit model of the vertical via structure in multilayer.
(a)
Single via
(b)
Differential vias


## 3.2. Parameter Extraction

The parameters of equivalent circuit of via can be solved by using the corresponding analytical formulas [8, 18–20]. Among them, the capacitance of via to plate surface is mainly divided into three parts: the capacitance of via pad to plate, the capacitance of middle cylinder to plate, and the capacitance of up/down cylinder to plate, respectively. It is shown in Figure 8.Figure 8
Capacitance of via for each part.The formulas of capacitance for each part are shown as follows. The capacitance of via pad to plate is expressed as (5). The first part of (5) is the coaxial capacitance between the pad and reference plane because of a certain thickness of the pad. The capacitance of the middle cylinder to plate is expressed as (6). The plate thickness d can be ignored in the calculation of (6), because the calculation of (5) has already considered the influence of plate thickness. The h in (6) is the height of the cylinder in the middle of via, and v is the number of segments which the middle column is divided into. The capacitance of up/down cylinder to plate is expressed as (7). In (7), the impact of d can also be ignored. The h is the height of the up/down cylinder of via. The calculation part of DIII is the stray capacitance of the pad to plate, so here the dielectric constant should be the dielectric constant of the air ε0. In (5) to (7), rantipad  is antipad radius, rpad  is pad radius, and rviabody  is via radius. Consider
(5)Cpad=2πdε0εrln(rantipad/rpad)+1.4ε0εrrpad{rantipad-rpadln(rantipad/rpad)}2×{π20.985rpad(rantipad-rviabody)Λ(rantipad/rpad-1)2-4ln(sin(φ)-1)(1φsin(2φ))2(rantipad-rviabody)Λ(rantipad/rpad-1)2},
where
(6)φ=π2(rantipad-rpadrantipad-rviabody),Λ=((χ01(rpadrviabody))}2{J0(χ01)N0(χ01(rpadrviabody))-N0(χ01)J0(χ01(rpadrviabody))}2)×((J02(χ01)J02(χ01(rantipad/rviabody)))-1)-1,χ01=3.1rantipad/rviabody-1,Cviabody=B(2πε0εrln(rantipad/rviabody)),
where
(7)B=∑p=1v(h+d)(rantipad-rviabody)v((h/2)-(p-1)(h/2v))2+(rantipad-rviabody)2,Ctop/bottom=A[DΙ+DΙΙ+DΙΙΙ],
where
(8)A=2πε0εrln(rantipad/rviabody),DΙ=∑p=1v(h+d)(rantipad-rviabody)v(h-(p-1)(h/v))2+(rantipad-rviabody)2,DΙΙ=∑p=1v(((rpad-rviabody)v))2)-1/2)-1((h2+(rantipad-rpad)2)(rpad-rviabody))×(v((rpad-rviabody)v))2)1/v(((rpad-rviabody)v))2h2+(((rpad-rviabody)v)(rantipad-rpad)+(p-1)×((rpad-rviabody)v))2)1/2)-1),DΙΙΙ=∑p=1v(h2+(rantipad-rpad)2)dv(rantipad-rpad)2+(h+((p-1)d/v))2.
For the signal via, we have
(9)Csignalvia=3Cpad+2Cviabody+2Ctop/bottom.For an interplane return via, we have(10)Creturnvia=2ADΙ+2πdε0εrln(rantipad/rreturnvia).For differential vias, the mutual capacitance of vias can be calculated by(11)Cmutualcapacitance=hπε0εrln{(s/2rviabody)[1+1-(2rviabody/s)2]}.
Here, s is the distance between differential vias.The self-inductance and mutual inductance between the various parts of via are calculated by(12)Lij=5.08{ln((hs)+1+(hs)2)-(1+(sh)2)+(sh)},
where h is the height of via and s is equal to the radius of via when the self-inductance is calculated.


## 4. Examples of Segmented Modeling of Via

### 4.1. Modeling of Via in Single Plane Pair

#### 4.1.1. Modeling of Single Via

First, considering the simplest case, that is, via switching between microstrip and microstrip in single plane pair, the PCB board size of the model is as follows: lengtha=1600 mil, width b=1400 mil, and intermediate dielectric thickness d=63.3 mil. Via size is as follows: antipad diameter Dantipad=40 mil, pad diameter Dpad=20 mil, via diameter Dviabody=12 mil, microstrip width W=10 mil, reference dielectric thickness h=5.7 mil, medium is FR4, and loss angle tangent is 0.02. The conductivity of the conductor plate σ=5.8E7 S/m, the thickness of microstrip and conductor plate t=1 mil, and the distance of the port to the center of the circle is 25 mil. The side view of via structure is shown in Figure 9. Equivalent circuit of modeling in ADS is shown in Figure 10.Figure 9
Side view of single via structure.Figure 10
Equivalent circuit of single via in single plane pair.As shown in Figure10, Ltp is the inductance of microstrip to the ground, Ctp is ​​the summation capacitance of microstrip and pad to the ground, Ltv is the self-inductance of top-bottom cylinder, Ctv is the capacitance of top-bottom cylinder to the ground, L is the inductance of the middle column, and C is the capacitance of the middle column to the reference plane. The simulation results are shown in Figures 11 and 12, and the simulation time of the model is less than 1 s. It can be seen that the S-parameters of this method are in good agreement with the simulation results of HFSS. The amplitude of  S21 and  S11 is closer to the full-wave simulation results than first-order full-capacitance circuit model in high-frequency field. Phase characteristics of the S11 are far superior to first-order full-capacitor circuit model. At the same time, S11  characteristics in the vicinity of the resonant frequency are reflected accurately, and S21 has been described precisely in the entire modeling frequency. The maximum of S11 and the minimum of S21 are both corresponding to the resonant peak of the input impedance of the plane pairs where via locates. The transmission quality has been seriously reduced near the resonant frequency because of the enhanced reflection. The resonance effect of plane pair on the S11 and S21 is characterized accurately. The maxima of the reflection curve and minima of the transmission curve are both caused by the resonance effect of plane pair. Reducing the impedance of plane pair can improve the transmission quality of via.S
21 of a single via structure: (a) amplitude; (b) phase.
(a)
(b)S
11 of a single via structure: (a) amplitude; (b) phase.
(a)
(b)


#### 4.1.2. Modeling of Differential Vias

The equivalent circuit model of differential vias in single plane pair is created in this section. The two vias are located at −25 mil, 0 mil and 25 mil, 0 mil, and the distance between the two vias is 50 mil. The other parameters of the board are the same as those in Section4.1.1. Besides the mutual coupling of the two vias, they also face coupling with the power/ground plane pair. The side view of via structure and equivalent circuit model are shown in Figures 13 and 14, respectively. The simulation results are shown in Figures 15 and 16.Figure 13
Side view of differential vias structure in single plane pair.Figure 14
Equivalent circuit model of differential vias in single plane pair.S
21 of a differential vias structure: (a) amplitude; (b) phase.
(a)
(b)S
11 of a differential vias structure: (a) amplitude; (b) phase.
(a)
(b)It can be seen from the figures that the equivalent circuit model and full-wave simulation results of HFSS matched well. The amplitude ofS21 is in good agreement with simulation results of HFSS below 6 GHz. The deviation increases as frequency increases above 6 GHz, but the maximum deviation does not exceed 2.2 dB. The amplitude of S11 and simulation results of HFSS also match well below 6 GHz, and the maximum deviation does not exceed 8 dB.


### 4.2. Modeling of Multilayer Via

#### 4.2.1. Modeling of Single Via

When via switches in multilayer, each plane pair can be considered independent of each other. Each plane pair can adopt the modeling method of single plane pair, and then, they are cascaded up in the return path. In this section, the modeling of via between the top microstrip and the bottom microstrip that contains three plane pairs has been analyzed. The thickness of the 3 plane pairs from top to bottom is 10 mil, 63.3 mil, and 10 mil, respectively. PCB board size is the same as that in Section4.1.1. The side view of via structure and equivalent circuit model are shown in Figures 17 and 18. The simulation results are shown in Figures 19 and 20. The simulation results of HFSS are also given as a comparison. The results are consistent with the simulation results of HFSS mentioned previously. It is similar to the discussed condition of single plane pair.Figure 17
Side view of single via structure in multilayer.Figure 18
Equivalent circuit of single via in multilayer.S
21 of single via structure in multilayer: (a) amplitude; (b) phase.
(a)
(b)S
11 of single via structure in multilayer: (a) amplitude; (b) phase.
(a)
(b)


#### 4.2.2. Modeling of Differential Via

Similar to the modeling of single via in multilayer plane pairs, the side view and equivalent circuit model of the differential vias structure in multilayer are shown in Figures21 and 22. The simulation results are shown in Figures 23 and 24. The results are consistent with the simulation results of HFSS.Figure 21
Side view of differential vias structure in multilayer.Figure 22
Equivalent circuit model of differential vias in multilayer.S
21 of differential vias in multilayer: (a) amplitude; (b) phase.
(a)
(b)S
11 of differential vias in multilayer: (a) amplitude; (b) phase.
(a)
(b)


## 4.1. Modeling of Via in Single Plane Pair

### 4.1.1. Modeling of Single Via

First, considering the simplest case, that is, via switching between microstrip and microstrip in single plane pair, the PCB board size of the model is as follows: lengtha=1600 mil, width b=1400 mil, and intermediate dielectric thickness d=63.3 mil. Via size is as follows: antipad diameter Dantipad=40 mil, pad diameter Dpad=20 mil, via diameter Dviabody=12 mil, microstrip width W=10 mil, reference dielectric thickness h=5.7 mil, medium is FR4, and loss angle tangent is 0.02. The conductivity of the conductor plate σ=5.8E7 S/m, the thickness of microstrip and conductor plate t=1 mil, and the distance of the port to the center of the circle is 25 mil. The side view of via structure is shown in Figure 9. Equivalent circuit of modeling in ADS is shown in Figure 10.Figure 9
Side view of single via structure.Figure 10
Equivalent circuit of single via in single plane pair.As shown in Figure10, Ltp is the inductance of microstrip to the ground, Ctp is ​​the summation capacitance of microstrip and pad to the ground, Ltv is the self-inductance of top-bottom cylinder, Ctv is the capacitance of top-bottom cylinder to the ground, L is the inductance of the middle column, and C is the capacitance of the middle column to the reference plane. The simulation results are shown in Figures 11 and 12, and the simulation time of the model is less than 1 s. It can be seen that the S-parameters of this method are in good agreement with the simulation results of HFSS. The amplitude of  S21 and  S11 is closer to the full-wave simulation results than first-order full-capacitance circuit model in high-frequency field. Phase characteristics of the S11 are far superior to first-order full-capacitor circuit model. At the same time, S11  characteristics in the vicinity of the resonant frequency are reflected accurately, and S21 has been described precisely in the entire modeling frequency. The maximum of S11 and the minimum of S21 are both corresponding to the resonant peak of the input impedance of the plane pairs where via locates. The transmission quality has been seriously reduced near the resonant frequency because of the enhanced reflection. The resonance effect of plane pair on the S11 and S21 is characterized accurately. The maxima of the reflection curve and minima of the transmission curve are both caused by the resonance effect of plane pair. Reducing the impedance of plane pair can improve the transmission quality of via.S
21 of a single via structure: (a) amplitude; (b) phase.
(a)
(b)S
11 of a single via structure: (a) amplitude; (b) phase.
(a)
(b)


### 4.1.2. Modeling of Differential Vias

The equivalent circuit model of differential vias in single plane pair is created in this section. The two vias are located at −25 mil, 0 mil and 25 mil, 0 mil, and the distance between the two vias is 50 mil. The other parameters of the board are the same as those in Section4.1.1. Besides the mutual coupling of the two vias, they also face coupling with the power/ground plane pair. The side view of via structure and equivalent circuit model are shown in Figures 13 and 14, respectively. The simulation results are shown in Figures 15 and 16.Figure 13
Side view of differential vias structure in single plane pair.Figure 14
Equivalent circuit model of differential vias in single plane pair.S
21 of a differential vias structure: (a) amplitude; (b) phase.
(a)
(b)S
11 of a differential vias structure: (a) amplitude; (b) phase.
(a)
(b)It can be seen from the figures that the equivalent circuit model and full-wave simulation results of HFSS matched well. The amplitude ofS21 is in good agreement with simulation results of HFSS below 6 GHz. The deviation increases as frequency increases above 6 GHz, but the maximum deviation does not exceed 2.2 dB. The amplitude of S11 and simulation results of HFSS also match well below 6 GHz, and the maximum deviation does not exceed 8 dB.


## 4.1.1. Modeling of Single Via

First, considering the simplest case, that is, via switching between microstrip and microstrip in single plane pair, the PCB board size of the model is as follows: lengtha=1600 mil, width b=1400 mil, and intermediate dielectric thickness d=63.3 mil. Via size is as follows: antipad diameter Dantipad=40 mil, pad diameter Dpad=20 mil, via diameter Dviabody=12 mil, microstrip width W=10 mil, reference dielectric thickness h=5.7 mil, medium is FR4, and loss angle tangent is 0.02. The conductivity of the conductor plate σ=5.8E7 S/m, the thickness of microstrip and conductor plate t=1 mil, and the distance of the port to the center of the circle is 25 mil. The side view of via structure is shown in Figure 9. Equivalent circuit of modeling in ADS is shown in Figure 10.Figure 9
Side view of single via structure.Figure 10
Equivalent circuit of single via in single plane pair.As shown in Figure10, Ltp is the inductance of microstrip to the ground, Ctp is ​​the summation capacitance of microstrip and pad to the ground, Ltv is the self-inductance of top-bottom cylinder, Ctv is the capacitance of top-bottom cylinder to the ground, L is the inductance of the middle column, and C is the capacitance of the middle column to the reference plane. The simulation results are shown in Figures 11 and 12, and the simulation time of the model is less than 1 s. It can be seen that the S-parameters of this method are in good agreement with the simulation results of HFSS. The amplitude of  S21 and  S11 is closer to the full-wave simulation results than first-order full-capacitance circuit model in high-frequency field. Phase characteristics of the S11 are far superior to first-order full-capacitor circuit model. At the same time, S11  characteristics in the vicinity of the resonant frequency are reflected accurately, and S21 has been described precisely in the entire modeling frequency. The maximum of S11 and the minimum of S21 are both corresponding to the resonant peak of the input impedance of the plane pairs where via locates. The transmission quality has been seriously reduced near the resonant frequency because of the enhanced reflection. The resonance effect of plane pair on the S11 and S21 is characterized accurately. The maxima of the reflection curve and minima of the transmission curve are both caused by the resonance effect of plane pair. Reducing the impedance of plane pair can improve the transmission quality of via.S
21 of a single via structure: (a) amplitude; (b) phase.
(a)
(b)S
11 of a single via structure: (a) amplitude; (b) phase.
(a)
(b)


## 4.1.2. Modeling of Differential Vias

The equivalent circuit model of differential vias in single plane pair is created in this section. The two vias are located at −25 mil, 0 mil and 25 mil, 0 mil, and the distance between the two vias is 50 mil. The other parameters of the board are the same as those in Section4.1.1. Besides the mutual coupling of the two vias, they also face coupling with the power/ground plane pair. The side view of via structure and equivalent circuit model are shown in Figures 13 and 14, respectively. The simulation results are shown in Figures 15 and 16.Figure 13
Side view of differential vias structure in single plane pair.Figure 14
Equivalent circuit model of differential vias in single plane pair.S
21 of a differential vias structure: (a) amplitude; (b) phase.
(a)
(b)S
11 of a differential vias structure: (a) amplitude; (b) phase.
(a)
(b)It can be seen from the figures that the equivalent circuit model and full-wave simulation results of HFSS matched well. The amplitude ofS21 is in good agreement with simulation results of HFSS below 6 GHz. The deviation increases as frequency increases above 6 GHz, but the maximum deviation does not exceed 2.2 dB. The amplitude of S11 and simulation results of HFSS also match well below 6 GHz, and the maximum deviation does not exceed 8 dB.


## 4.2. Modeling of Multilayer Via

### 4.2.1. Modeling of Single Via

When via switches in multilayer, each plane pair can be considered independent of each other. Each plane pair can adopt the modeling method of single plane pair, and then, they are cascaded up in the return path. In this section, the modeling of via between the top microstrip and the bottom microstrip that contains three plane pairs has been analyzed. The thickness of the 3 plane pairs from top to bottom is 10 mil, 63.3 mil, and 10 mil, respectively. PCB board size is the same as that in Section4.1.1. The side view of via structure and equivalent circuit model are shown in Figures 17 and 18. The simulation results are shown in Figures 19 and 20. The simulation results of HFSS are also given as a comparison. The results are consistent with the simulation results of HFSS mentioned previously. It is similar to the discussed condition of single plane pair.Figure 17
Side view of single via structure in multilayer.Figure 18
Equivalent circuit of single via in multilayer.S
21 of single via structure in multilayer: (a) amplitude; (b) phase.
(a)
(b)S
11 of single via structure in multilayer: (a) amplitude; (b) phase.
(a)
(b)


### 4.2.2. Modeling of Differential Via

Similar to the modeling of single via in multilayer plane pairs, the side view and equivalent circuit model of the differential vias structure in multilayer are shown in Figures21 and 22. The simulation results are shown in Figures 23 and 24. The results are consistent with the simulation results of HFSS.Figure 21
Side view of differential vias structure in multilayer.Figure 22
Equivalent circuit model of differential vias in multilayer.S
21 of differential vias in multilayer: (a) amplitude; (b) phase.
(a)
(b)S
11 of differential vias in multilayer: (a) amplitude; (b) phase.
(a)
(b)


## 4.2.1. Modeling of Single Via

When via switches in multilayer, each plane pair can be considered independent of each other. Each plane pair can adopt the modeling method of single plane pair, and then, they are cascaded up in the return path. In this section, the modeling of via between the top microstrip and the bottom microstrip that contains three plane pairs has been analyzed. The thickness of the 3 plane pairs from top to bottom is 10 mil, 63.3 mil, and 10 mil, respectively. PCB board size is the same as that in Section4.1.1. The side view of via structure and equivalent circuit model are shown in Figures 17 and 18. The simulation results are shown in Figures 19 and 20. The simulation results of HFSS are also given as a comparison. The results are consistent with the simulation results of HFSS mentioned previously. It is similar to the discussed condition of single plane pair.Figure 17
Side view of single via structure in multilayer.Figure 18
Equivalent circuit of single via in multilayer.S
21 of single via structure in multilayer: (a) amplitude; (b) phase.
(a)
(b)S
11 of single via structure in multilayer: (a) amplitude; (b) phase.
(a)
(b)


## 4.2.2. Modeling of Differential Via

Similar to the modeling of single via in multilayer plane pairs, the side view and equivalent circuit model of the differential vias structure in multilayer are shown in Figures21 and 22. The simulation results are shown in Figures 23 and 24. The results are consistent with the simulation results of HFSS.Figure 21
Side view of differential vias structure in multilayer.Figure 22
Equivalent circuit model of differential vias in multilayer.S
21 of differential vias in multilayer: (a) amplitude; (b) phase.
(a)
(b)S
11 of differential vias in multilayer: (a) amplitude; (b) phase.
(a)
(b)


## 5. Comprehensive Modeling Method of Coupled Channels

Assume an actual circuit of signal network shown in Figure25. The drive-side connects with a 10 mm long microstrip. The signal flows through via 1 to the bottom plate from the top level of a three-layer board with EBG structure. The signal flows back to the top through via 2 after transmission of an 11 mm long microstrip. Finally, the signal is connected to sensitive devices by an 8 mm long microstrip. For such a network model, assume that the drive-side is coupled into a certain number of conducted noises. The key task of this section is to study how the signal of the receiver will change under the effect of coupling.Signal network.
(a)
Front view
(b)
Side viewFor the signal network shown in Figure25, the entire signal path can be divided into three parts for modeling. They are the AB section of the signal line 1, BC section of via switching, and CD section of the signal line 2, respectively. The circuit board dimensions are known as 32 mm × 32 mm; the three plates are all 10 mil thickness, and the size of via is as follows: the diameter of antipad Dantipad=40 mil, the diameter of pad Dpad=20 mil, the diameter of via Dviabody=12 mil, the width of microstrip W = 10 mil, the thickness of reference dielectric h=5.7 mil, the media is FR4 and dielectric constant εr=4.4, and loss angle tangent is 0.02. The conductivity of the conductor plate σ=5.8E7 S/m, the thickness of the microstrip t=1 mil, the two vias are located at 16 mm, 16 mm and 27 mm, 16 mm, and the distance of the port to the center via is 30 mil.Modeling of the transmission line is relatively very mature in the present study. As the paper is based on Agilent circuit simulate software ADS for modeling and simulation, the transmission line can be modeled as lossy transmission line or ideal transmission line, which considers characteristic impedance and transmission delay, or microstrip and stripline model in ADS. TheS-parameter curves of signal line 1 (similar to signal line 2 in S-parameter curves) are shown in Figure 26.Simulation results of line 1.
(a)
S
11 amplitude
(b)
S
21 amplitudeVia switching part of the segment BC has been modeled in detail in Section3. Its equivalent circuit model and simulation results are shown in Figures 27 and 28. The comparison with full-wave simulation results of HFSS is also given in Figure 28. The two curves overlap well, indicating that the signal transmission parameters extracted by the two methods are equivalent.Figure 27
Equivalent circuit of via switching.Simulation results of switching via.
(a)
S
21 amplitude
(b)
S
11 amplitude


## 6. Conclusion

This paper focuses on the modeling and simulation of common interconnects of PCB. Fast modeling and parameters extraction of power/ground plane pair are realized using cavity resonance method. The calculated results match well with the simulation results of HFSS. Besides, the segmented via modeling method including the effect of power/ground plane pair is proposed. This modeling method is used for analysis of manifold via structures. This paper completes the modeling of single via and differential vias in single plane pair and multilayer. Finally, considering an assumed signal network, for example, the equivalent circuit model of the coupled channels, is established. Every part of the equivalent circuit model is imported into Designer for cosimulation. The results are consistent with the previous simulation results of HFSS, thus, proving the validity and accuracy of the modeling method.



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*Source: 389516-2013-09-30.xml*