# Analysis of Random Variation in Subthreshold FGMOSFET

Authors: Rawid Banchuin
Journal: Active and Passive Electronic Components
 (2016)

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## Abstract

The analysis of random variation in the performance of Floating Gate Metal Oxide Semiconductor Field Effect Transistor (FGMOSFET) which is an often cited semiconductor based electronic device, operated in the subthreshold region defined in terms of its drain current (ID), has been proposed in this research. ID is of interest because it is directly measurable and can be the basis for determining the others. All related manufacturing process induced device level random variations, their statistical correlations, and low voltage/low power operating condition have been taken into account. The analysis result has been found to be very accurate since it can fit the nanometer level SPICE BSIM4 based reference with very high accuracy. By using such result, the strategies for minimizing variation in ID can be found and the analysis of variation in the circuit level parameter of any subthreshold FGMOSFET based circuit can be performed. So, the result of this research has been found to be beneficial to the variability aware design of subthreshold FGMOSFET based circuit.


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## Body

## 1. Introduction

The FGMOSFET in subthreshold region has been found to be an extensively utilized semiconductor based electronic device for low voltage/low power circuits [1–16]. The concept of variability aware design has been applied to such low voltage/low power circuits for handling the effects of the manufacturing process induced device level random variations [6, 10–16]. The examples of these variations are the variation in channel width (W) and channel length (L) and so forth. These device level variations affect the circuit level performances of FGMOSFET such as ID, transconductance (gm), and drain to source resistance (rds). Similar to the ordinary Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the subthreshold FGMOSFET is more susceptible to these variations than that in the above-threshold region and ID has been found to be the key circuit level performance as it is directly measurable and can be the basis for determining the others according to their relationships.According to the importance ofID, various analyses of random variation in ID of the ordinary MOSFET caused by manufacturing process induced device level random variations have been performed in the analytical manner where the subthreshold region operated MOSFET has also been concerned [17–23]. For FGMOSFET, on the other hand, the previous studies have been mostly focused on variations in the circuit level performances of certain FGMOSFET based circuits where subthreshold FGMOSFET based circuits have also been considered [6, 10–12, 15, 23–29]. Unfortunately, the analysis results of these previous researches are applicable only to their dedicated circuits. Moreover, the variability analysis of a single subthreshold FGMOSFET, which is more versatile as it is applicable to any subthreshold FGMOSFET based circuits, has never been performed in any previous work.Hence, the analysis of random variation inID (ΔID) of subthreshold FGMOSFET caused by manufacturing process induced device level random variations has been proposed in this research. All related device level random variations, their statistical correlations, and low voltage/low power operating condition have been taken into account. The obtained analysis result has been found to be very accurate since it can fit the nanometer level SPICE BSIM4 based reference with very high accuracy. By using the obtained result, the strategies for minimizing ΔID can be found and the analysis of variation in the circuit level performance of any subthreshold FGMOSFET based circuit can be done. So, the result of this research has been found to be beneficial to the variability aware design of subthreshold FGMOSFET based circuit which is an interesting low voltage/low power semiconductor application. In the next section, the overview of FGMOSFET will be addressed followed by the proposed analysis in Section 3. The verification of the analysis result and discussions will be, respectively, given in Sections 4 and 5. Finally, the conclusion will be drawn in Section 6.


## 2. The Overview of FGMOSFET

FGMOSFET is a special type of MOSFET with an additional gate, namely, floating gate isolated within the oxide. A cross-sectional view of an N-type FGMOSFET withN inputs where N>1 can be shown as in Figure 1 where the symbol and equivalent circuit are shown in Figure 2. Such equivalent circuit is composed of a MOSFET, N input capacitances (C1,C2,C3,…,CN), overlap capacitance between floating gate and drain (Cfd), overlap capacitance between floating gate and source (Cfs), and parasitic capacitance between floating gate and substrate (Cfb).Figure 1
A cross-sectional view of N-type,N inputs FGMOSFET.Figure 2
The symbol (a) and equivalent circuit model (b) of an N-type,N inputs FGMOSFET.
(a) (b)Let{i}={1,2,3,…,N} and let any ith input capacitance be denoted by Ci; the floating gate voltage, VFG, can be given by(1)VFG=∑i=1NCiVi+CfdVD+CfsVS+CfbVB+Q^CT,where Vi is the input voltage at any ith input gate, VD is the drain voltage, VS is the source voltage, and VB is the bulk voltage. Moreover, Q^ stands for the charge stored on the floating gate. Finally, CT denotes the total capacitance of the floating gate which can be defined as (2)CT=∑i=1NCi+Cfd+Cfs+Cfb.Letki, kfd, kfs, and kfb denote the coupling factor of any ith input gate, drain, source, and bulk and be defined as ki=Ci/CT, kfd=Cfd/CT, kfs=Cfs/CT, and kfb = Cfb/CT, respectively; VFG can be alternatively given as in (3). From either (1) or (3), it can be seen that VFG depends on Vi, VD, VS, and VB:(3)VFG=∑i=1NkiVi+kfdVD+kfsVS+kfbVB+Q,where Q denotes charge stored on the floating gate per CT and is equal to Q^/CT.


## 3. The Proposed Analysis

By usingVFG as given by (3), ID of the subthreshold region operated FGMOSFET can be given without assuming that 1≫exp⁡[-VDS/VT] for covering the low voltage/low power operating condition which may have very low VDS that invalidates this assumption, as(4)ID=I0WL1-exp⁡-VDSVT×exp⁡∑i=1NkiVi+kfdVD+kfsVS+kfbVBnVT-VSVT+QVT,where I0, n, VDS, and VT stand for subthreshold specific current which depends on various physical parameters, for example, gate oxide capacitance (Cox) and threshold voltage (Vth), subthreshold parameter, drain to source voltage, and thermal voltage, respectively.Since the variations inW (ΔW), L (ΔL), Q (ΔQ), n (Δn), I0 (ΔI0), kfd (Δkfd), kfs (Δkfs), kfb (Δkfb), and ki (Δki), which are related to manufacturing process of the FGMOSFET, contribute ΔID of our interest, ΔID can be given in terms of its contributors as(5)ΔID=∂ID∂I0ΔI0+∂ID∂WΔW+∂ID∂LΔL+∂ID∂nΔn+∂ID∂QΔQ+∂ID∂kfdΔkfd+∂ID∂kfsΔkfs+∂ID∂kfbΔkfb+∑i=1N∂ID∂kiΔki,where variations in the physical parameters of I0, for example, those in Cox (ΔCox) and Vth (ΔVth), have been taken into account by ΔI0. By using (4), derivatives in (5) can be given by (6)∂ID∂I0=WL1-exp⁡-VDSVTexp⁡∑i=1NkiVi+kfdVD+kfsVS+kfbVBnVT-VSVT+QVT,∂ID∂W=I0L1-exp⁡-VDSVTexp⁡∑i=1NkiVi+kfdVD+kfsVS+kfbVBnVT-VSVT+QVT,∂ID∂L=-I0WL21-exp⁡-VDSVTexp⁡∑i=1NkiVi+kfdVD+kfsVS+kfbVBnVT-VSVT+QVT,∂ID∂n=-I0Wn2VTL∑i=1NkiVi+kfdVD+kfsVS+kfbVB1-exp⁡-VDSVT×exp⁡∑i=1NkiVi+kfdVD+kfsVS+kfbVBnVT-VSVT+QVT,∂ID∂Q=I0WVTL1-exp⁡-VDSVTexp⁡∑i=1NkiVi+kfdVD+kfsVS+kfbVBnVT-VSVT+QVT,∂ID∂kfd=I0VDWnVTL1-exp⁡-VDSVTexp⁡∑i=1NkiVi+kfdVD+kfsVS+kfbVBnVT-VSVT+QVT,∂ID∂kfs=I0VsWnVTL1-exp⁡-VDSVTexp⁡∑i=1NkiVi+kfdVD+kfsVS+kfbVBnVT-VSVT+QVT,∂ID∂kfb=I0VBWnVTL1-exp⁡-VDSVTexp⁡∑i=1NkiVi+kfdVD+kfsVS+kfbVBnVT-VSVT+QVT,∂ID∂ki=I0ViWnVTL1-exp⁡-VDSVTexp⁡∑i=1NkiVi+kfdVD+kfsVS+kfbVBnVT-VSVT+QVT.From (5)–(6), it can be seen that ΔID is very mathematically cumbersome. So, it is worthy to look for the alternative manners of analysis, for example, the per-unit based analysis which performs the analysis in terms of the per-unit value of ΔID (ΔID/ID). By using (4)–(6), ΔID/ID can be given as follows:(7)ΔIDID=ΔI0I0+ΔWW-ΔLL+QVTΔQQ-∑i=1NkiVi+kfdVD+kfsVS+kfbVBnVTΔnn+kfdVDnVTΔkfdkfd+kfsVSnVTΔkfskfs+kfbVBnVTΔkfbkfb+∑i=1NkiVinVTΔkiki,where ΔW/W,  ΔL/L,  ΔQ/Q,  Δn/n,  ΔI0/I0,  Δkfd/kfd, Δkfs/kfs,  Δkfb/kfb, and Δki/ki are the per-unit values of ΔW,  ΔL,  ΔQ,  Δn,  ΔI0,  Δkfd,  Δkfs,  Δkfb, and Δki, respectively.Since it has been found thatΔID/ID is much more compact than ΔID, the per-unit based analysis is preferable and has been chosen for this research. It has also been found that ΔI0 and ΔW contribute ΔID in the similar directions which are opposite to that of ΔL. Finally, the directions of contributions to ΔID of Δn, Δkfd, Δkfs, Δkfb, and Δki depend on Vi, VS, VD, and VB whereas that of ΔQ is solely dependent on the polarity of Q. As ΔID/ID is a random variable similar to its contributors, that is, ΔW, ΔL, ΔQ, Δn, ΔI0, Δkfd, Δkfs, Δkfb, and Δki, it is convenient to analyze its statistical behavior by using its standard deviation as its mean is equal to zero similar to those of the contributors. By taking the statistical correlations of the contributors into account, the standard deviation of ΔID/ID (σΔID/ID) has been found to be given by(8)σΔID/ID=σΔI0/I02+σΔW/W2+σΔL/L2+QVT2σΔQ/Q2+1nVT∑i=1NkiVi+kfdVD+kfsVS+kfbVB2σΔn/n2+kfdVDnVT2σσΔkfd/kfd22+kfsVSnVT2σσΔkfs/kfs22+kfbVSnVT2σσΔkfb/kfb22+∑i=1NkiVinVT2σΔki/ki2+2ρΔI0,ΔWσΔI0/I02σΔW/W2-2ρΔI0,ΔLσΔI0/I02σΔL/L2+2ρΔI0,ΔQQVTσΔI0/I02σΔQ/Q2-2ρΔI0,ΔnnVT∑i=1NkiVi+kfdVD+kfsVS+kfbVBσΔI0/I02σΔn/n2+2ρΔI0,ΔkfdkfdVDnVTσΔI0/I02σΔkfd/kfd2+2ρΔI0,ΔkfskfsVSnVTσΔI0/I02σΔkfs/kfs2+2ρΔI0,ΔkfbkfbVBnVTσΔI0/I02σΔkfb/kfb2+∑i=1N2kiVinVTρΔI0,ΔkiσΔI0/I02σΔki/ki2-2ρΔW,ΔLσΔW/W2σΔL/L2+2QVTρΔW,ΔQσΔW/W2σΔQ/Q2-2ρΔW,ΔnnVT∑i=1NkiVi+kfdVD+kfsVS+kfbVBσΔW/W2σΔn/n2+2ρΔW,ΔkfdkfdVDnVTσΔW/W2σΔkfd/kfd2+2ρΔW,ΔkfskfdVSnVTσΔW/W2σΔkfs/kfs2+2ρΔW,ΔkfbkfdVBnVTσΔW/W2σΔkfb/kfb2+∑i=1N2kiVinVTρΔW,ΔkiσΔW/W2σΔki/ki2+2ρΔL,ΔnnVT∑i=1NkiVi+kfdVD+kfsVS+kfbVBσΔL/L2σΔn/n2-2QVTρΔL,ΔQσΔL/L2σΔQ/Q2-2ρΔL,ΔkfdkfdVDnVTσΔL/L2σΔkfd/kfd2-2ρΔL,ΔkfskfsVSnVTσΔL/L2σΔkfs/kfs2-2ρΔL,ΔkfbkfdVBnVTσΔL/L2σΔkfb/kfb2-∑i=1N2kiVinVTρΔL,ΔkiσΔL/L2σΔki/ki2-2ρΔn,ΔQQVT∑i=1NkiVi+kfdVD+kfsVS+kfbVBnVTσΔn/n2σΔQ/Q2-2ρΔn,ΔkfdkfdVDnVT∑i=1NkiVi+kfdVD+kfsVS+kfbVBnVTσΔn/n2σΔkfd/kfd2-2ρΔn,ΔkfskfsVSnVT∑i=1NkiVi+kfdVD+kfsVS+kfbVBnVTσΔn/n2σΔkfs/kfs2-2ρΔn,ΔkfbkfbVBnVT∑i=1NkiVi+kfdVD+kfsVS+kfbVBnVTσΔn/n2σΔkfb/kfb2-∑i=1N2kiVi∑i=1NkiVi+kfdVD+kfsVS+kfbVBnVT2ρΔn,ΔkiσΔn/n2σΔki/ki2+2QVTkfdVDnVTρΔQ,ΔkfdσΔQ/Q2σΔkfd/kfd2+2QVTkfsVSnVTρΔQ,ΔkfsσΔQ/Q2σΔkfs/kfs2+2QVTkfbVBnVTρΔQ,ΔkfbσΔQ/Q2σΔkfb/kfb2+∑i=1N2QVTkiVinVTρΔQ,ΔkiσΔQ/Q2σΔki/ki2+2kfdVDnVTkfsVSnVTρΔkfd,ΔkfsσΔkfd/kfd2σΔkfs/kfs2+2kfdVDnVTkfbVBnVTρΔkfd,ΔkfbσΔkfd/kfd2σΔkfb/kfb2+∑i=1N2kfdVDnVTkiVinVTρΔkfd,ΔkiσΔkfd/kfd2σΔki/ki2+2kfsVSnVTkfbVBnVTρΔkfs,ΔkfbσΔkfs/kfs2σΔkfb/kfb2+∑i=1N2kfsVSnVTkiVinVTρΔkfs,ΔkiσΔkfs/kfs2σΔki/ki2+∑i=1N2kfbVBnVTkiVinVTρΔkfb,ΔkiσΔkfb/kfb2σΔki/ki2+∑j=1j≠iN∑i=1NkiVinVTkjVjnVTρΔki,ΔkfjσΔki/ki2σΔkj/kj20.5,where σΔX/X2 denotes the variance of ΔX/X and {ΔX/X}={ΔW/W,ΔL/L,ΔQ/Q,Δn/n,ΔI0/I0,Δkfd/kfd,Δkfs/kfs,Δkfb/kfb,Δki/ki}. Moreover, ρΔX,ΔY denotes the correlation coefficient of ΔX and ΔY which displays the degree of their statistical correlation; for example, ρΔW,ΔL denotes the correlation coefficient of ΔW and ΔL and displays the degree of their statistical correlation. It can be seen from (8) that the 1st up to the 9th terms of σΔID/ID have been solely contributed by each of σΔX/X2’s where the others have been contributed by the statistical correlations based terms. Moreover, by keeping in mind that ΔW, ΔL, ΔQ, Δn, ΔI0  Δkfd, Δkfs, Δkfb, and Δk are zero mean random variables, ρΔX,ΔY can be obtained by using (9) where E· stands for the expectation operator:(9)ρΔX,ΔY=EΔXΔYσΔXσΔY.


## 4. Verification of the Analysis Result

The proposed analysis result has been verified at the nanometer level based on the 65 nm level CMOS process technology, two-input FGMOSFET of both N-type and P-type, and SPICE BSIM4 [30] with all necessary SPICE parameters provided by PTM. Since two-input FGMOSFET has been assumed, we let N=2; that is, {Ci}={C1,C2} and {ki}=k1,k2. It should be noted that both k1 and k2 can be arbitrary constants as our device is not in the triode region which is the only region of FGMOSFET that the coupling factors are functions of VD [31]. So, we let k1=k2=0.5 in order to balance the influence of both FGMOSFET inputs. We also let W=120 nm and L=80 nm and also assume that Ci≫Cfd,Cfs,Cfb and Q^ is extremely small as has been done in many previous works on subthreshold FGMOSFET, for example, [1–3, 6–8, 11, 15]. For making the influences of all device level variations be unbiased, all of such variations have been assumed to be statistically equivalent by letting them be normally distributed with zero means and 1% standard deviations. As a result, ΔXΔY such as ΔWΔL employs a normal product distribution [32] as the products of the manufacturing process induced device level random variations, for example, ΔWΔL, ΔI0ΔQ, and ΔnΔL, are the product of two normally distributed random variables. Moreover, all ρΔx,Δy’s have been assumed to be given by 0.5 which is a reasonable estimation [33]. So, each device level variation must be expressed in terms of a weighted sum of its correlated and uncorrelated components which are both normally distributed [33] and have equal weights given by 0.5.In order to perform the verification, the formulatedσΔID/ID has been compared to its SPICE BSIM4 based reference (σΔID/IDSPICE) obtained by using the Monte-Carlo SPICE simulation with 1000 runs. The SPICE BSIM4 based modelling of FGMOSFET with two inputs can be done by using the two-input version of the equivalent circuit of FGMOSFET in Figure 2 where the core MOSFET has been modelled by using the SPICE BSIM4 and the simulation methodology proposed in [34] has been adopted for solving the convergence problem of the simulator.As the resulting verification,σΔID/ID and σΔID/IDSPICE have been comparatively plotted against the magnitude of the voltage of the 1st and 2nd input of FGMOSFET denoted by V1 and V2, respectively. The minimum values of both V1 and V2 are 0 volts and the maximum values have been chosen so that the both N-type and P-type FGMOSFETs operate in the subthreshold region. The comparative plots of σΔID/ID and σΔID/IDSPICE against V1 (where V2=0) of N-type and P-type subthreshold FGMOSFET can be shown in Figure 3 where the similar plots against V2 (where V1=0) are shown in Figure 4.Figure 3
N-type and P-type subthreshold FGMOSFET based comparative plots againstV1 where V2=0.Figure 4
N-type and P-type subthreshold FGMOSFET based comparative plots againstV2 where V1=0.From Figures3 and 4 where σΔID/ID and σΔID/IDSPICE have been, respectively, shown in blue lines and red dots for N-type subthreshold FGMOSFET (green lines and black dots for P-type device), highly strong agreements between σΔID/ID and σΔID/IDSPICE can be observed. Moreover, the average errors of σΔID/ID from σΔID/IDSPICE determined by using the data sets of Figure 3 have been found to be 1.6245% and 1.8904% for N-type and P-type subthreshold FGMOSFET based comparison. On the other hand, such errors determined by using the data sets of Figure 4 have been found to be 1.8244% and 1.9518% for the N-type and P-type device based comparison, respectively. This means that the analysis result is very accurate for both N-type and P-type subthreshold FGMOSFET. If desired, σΔID/ID can fit σΔID/IDSPICE obtained by using the data from more advanced technology node, for example, 45 nm, 32 nm, and 28 nm. For doing so, the optimum parameters of subthreshold MOSFET’s ID such as I0, n, W, and L, extracted from the measured ID of the advanced technology node under consideration by using the optimization algorithm [35], must be adopted.From Figures3 and 4, it can be seen that σΔID/ID of the subthreshold FGMOSFET of both N-type and P-type grow larger when either V1 or V2 are lowered. This implies that the subthreshold FGMOSFET under very low voltage/low power operating condition is subjected to very large ΔID. It can also be seen that both σΔID/ID’s with respect to V1 and V2 of the P-type subthreshold FGMOSFET are lower than those of the N-type device. This means that the P-type device is more robust to the manufacturing process induced device level random variations than its N-type counterpart and has been found to be more preferable. Finally, even though the aforementioned average errors of the P-type device are larger than those of the N-type counterpart, it does not mean that our analysis result is more suitable to the less robust device. This is because the differences in these average errors which are very small as they are less than 0.3% are caused by the differences between the extraction errors of the subthreshold MOSFET’s drain current analytical model parameters from the 65 nm level CMOS technology based drain current data of the N-type and P-type MOSFET.


## 5. Discussions

Since the subthreshold FGMOSFET under very low voltage/low power operating condition is subjected to very largeΔID as stated above, omitting such condition in the designing of those circuits with crucial variability related issues has been found to be a simple strategy to avoid large ΔID. However, this strategy is not recommended according to the necessity of such condition for obtaining the low voltage/low power circuit. As a result, the operating condition regardless of strategies for minimizing ΔID must be determined. Fortunately, these strategies can be obtained by using our formulated ΔID/ID given by (7). From this equation, it can be seen that(10)∂ΔID/ID∂ΔI0/I0=1,(11)∂ΔID/ID∂ΔW/W=1,(12)∂ΔID/ID∂ΔL/L=-1,(13)∂ΔID/ID∂ΔQ/Q=QVT,(14)∂ΔID/ID∂Δn/n=-∑i=1NkiVi+kfdVD+kfsVS+kfbVBnVT,(15)∂ΔID/ID∂Δkfd/kfd=kfdVDnVT,(16)∂ΔID/ID∂Δkfs/kfs=kfsVsnVT,(17)∂ΔID/ID∂Δkfb/kfb=kfbVBnVT,(18)∂ΔID/ID∂Δki/ki=kiVinVT.Obviously, (10)–(18), respectively, determine the contributions of ΔI0, ΔW, ΔL, ΔQ, Δn, Δkfd, Δkfs, Δkfb, and Δki to ΔID. So, minimizing them yields the minimization of ΔID. It can be seen that (∂ΔID/ID)/(∂ΔI0/I0), (∂ΔID/ID)/(∂ΔW/W), and (∂ΔID/ID)/(∂ΔL/L) are constant, so, they cannot be minimized by any means. On the other hand, (∂ΔID/ID)/(∂ΔQ/Q) is proportional to Q, (∂ΔID/ID)/(∂Δn/n), (∂ΔID/ID)/(∂Δkfd/kfd), (∂ΔID/ID)/(∂Δkfs/kfs), (∂ΔID/ID)/(∂Δkfb/kfb), and (∂ΔID/ID)/(∂Δki/ki) are inversely proportional to n, and (∂ΔID/ID)/(∂Δn/n), (∂ΔID/ID)/(∂Δkfd/kfd), (∂ΔID/ID)/(∂Δkfs/kfs), and (∂ΔID/ID)/(∂Δkfb/kfb) are proportional to kfd, kfs, and kfb, that is, proportional to Cfd, Cfs, and Cfb. Thus, it can be seen that ΔID can be minimized by minimizing Q, Cfd, Cfs, and Cfb and maximizing n. In order to do so, Q can be minimized by several means such as using UV shining [13] and using a dummy stacked contact [36]. On the other hand, the effects of Cfd, Cfs, and Cfb can be minimized by ensuring that Cfd,Cfs,Cfb≪Ci. Moreover, n can be maximized by minimizing the oxide capacitance per-unit area between the floating gate and the bulk.Apart from yielding the above strategies, ourΔID/ID is also applicable to the analysis of variation in the circuit level performance of any subthreshold FGMOSFET based circuit in which the formulated σΔID/ID given by (8) has been found to be beneficial as well. For performing such analysis, we let the circuit level performance of the subthreshold FGMOSFET based circuit of our interest be P; thus, the random variation in P (ΔP) can be given by(19)ΔP=∑k=1MIDk∂P∂IDkΔIDkIDk,where M, IDk, and ΔIDk/IDk denote number of FGMOSFETs within the circuit which contribute P, ID, and ΔID/ID of any kth FGMOSFET which can be determined by using (7), respectively. It can be seen from (19) that ΔP can be determined after every ΔIDk/IDk has been found.According to the definition ofΔIDk/IDk above, it is a zero mean random variable and so does ΔP. As a result, it is convenient to analyze the statistical behavior of ΔP by using its standard deviation, that is, σΔP. By taking the statistical correlations between each random variation in IDk into account, σΔP can be given by (20), where ρΔIDk,ΔIDl denotes the correlation coefficient of ΔIDk and ΔIDl which are the random variations in IDk and IDl, that is, ID of any lth FGMOSFET where l≠k, respectively. Since σΔIDk/IDk and σΔIDl/IDl are, respectively, σΔID/ID of kth and lth FGMOSFET, they can be determined by using (8). After finding all σΔIDk/IDk’s and σΔIDl/IDl’s, σΔP can be obtained:(20)σΔP=∑k=1MIDk2∂P∂IDk2σΔIDk/IDk2+∑l=1l≠kM∑k=1MIDkIDl∂P∂IDk∂P∂IDlρΔIDk,ΔIDlσΔIDk/IDkσΔIDl/IDl0.5.As a practical example, letP be the output current (Iout) of the subthreshold FGMOSFET based OTA [11] whose core circuit has been depicted in Figure 5 where V+ (V-) and VDD denote the voltage at the positive (negative) input of the OTA and the supply voltage, respectively. For this OTA, M1 and M2 which have two inputs serve as an input differential pair and the averaging circuit has been included for improving the linearity. According to [11], Iout can be given in terms of ID of M1 and M2, that is, ID1 and ID2 as (21)Iout=ID1-ID2.Figure 5
The core circuit of the subthreshold FGMOSFET based OTA proposed in [11].Since the bodies of these FGMOSFETS are grounded and their sources are tied together as shown in Figure5, we have VB1=VB2=0 and VS1=VS2. Thus, we can let both VS1 and VS2 be given by VS. As a result, ID1 and ID2 can be, respectively, given by(22)ID1=I01W1L11-exp⁡-VDS1VT×exp⁡k11V++k12VDD+kfd1VD1+kfs1VSn1VT-VSVT+Q1VT,ID2=I02W2L21-exp⁡-VDS2VT×exp⁡k21V-+k22VDD+kfd2VD2+kfs2VSn2VT-VSVT+Q2VT,where k11(k21),  k12(k22),   kfd1(kfd2), and kfs1(kfs2) stand for k1, k2, kfd, and kfs of M1(M2). These coupling factors can be given by (23)k11=C11C11+C12+Cfd1+Cfs1+Cfb1,k12=C12C11+C12+Cfd1+Cfs1+Cfb1,kfd1=Cfd1C11+C12+Cfd1+Cfs1+Cfb1,kfs1=Cfs1C11+C12+Cfd1+Cfs1+Cfb1,k11=C11C11+C12+Cfd1+Cfs1+Cfb1,k12=C12C11+C12+Cfd1+Cfs1+Cfb1,kfd1=Cfd1C11+C12+Cfd1+Cfs1+Cfb1,kfs1=Cfs1C11+C12+Cfd1+Cfs1+Cfb1,where C11(C21), C12(C22), Cfd1(Cfd2), Cfs1(Cfs2), and Cfb1(Cfb2) stand for C1, C2, Cfd, Cfs, and Cfb of M1(M2), respectively.So, the random variation inIout (ΔIout) can be given by using (19) with M=2 as(24)ΔIout=ID1ΔID1ID1-ID2ΔID2ID2,where both ΔID1/ID1 and ΔID2/ID2 can be determined by using (7) as they are ΔID/ID of M1 and M2. For determining ΔID1/ID1, we let N=2, V1=V+, V2=VDD, k1=k11, k2=k12, kfd = kfd1, kfs=kfs1, and VB1=0 in (7). For determining ΔID2/ID2 on the other hand, we let N=2, V1=V-, V2=VDD, k1=k21, k2=k22, kfd=kfd2, kfs=kfs2, and VB2=0.Moreover, the standard deviation ofΔIout (σΔIout) can be obtained by using (20) with M=2 as follows:(25)σΔIout=ID12σΔID1/ID12+ID22σΔID2/ID22+2ID1ID2ρΔID1,ΔID2σΔID1/ID1σΔID2/ID20.5,where σΔID1/ID1 and σΔID2/ID2 can be determined by using (8) as they are σΔID/ID of M1 and M2. Similar to determining ΔID1/ID1 and ΔID2/ID2, we let N=2, V1=V+, V2=VDD, k1=k11, k2=k12, kfd=kfd1, kfs=kfs1, and VB1 = 0 for determining σΔID1/ID1 and let N=2, V1=V-, V2=VDD, k1=k21, k2=k22, kfd=kfd2, kfs=kfs2, and VB2=0 for determining σΔID2/ID2. Finally, we can plot σΔIout against σΔID1/ID1 and σΔID2/ID2 as shown in Figure 6 where σΔIout has been expressed in a per-unit basis with respect to the nominal Iout and the magnitude of ρΔID1,ΔID2 has been assumed to be 0.5 which implies a reasonable medium degree of correlation between ΔID1 and ΔID2. From Figure 6, it can be seen that σΔIout is increased with respect to σΔID1/ID1 and σΔID2/ID2. It can also be seen that even small amounts σΔID1/ID1 and σΔID2/ID2 can induce considerably large σΔIout. As an example, σΔID1/ID1=0.09 and σΔID2/ID2=0.08, that is, ΔID1 and ΔID2 of 9% and 8% of the nominal ID1 and ID2, respectively, yield σΔIout=0.26 which is equivalent to ΔIout as large as 26% of the nominal Iout. So, it can be seen that the adverse effect of ΔID to the performance of subthreshold FGMOSFET based circuits is significant.Figure 6
The 3D plotσΔIout of the subthreshold FGMOSFET based OTA versus σΔID1/ID1 and σΔID2/ID2.


## 6. Conclusion

In this research, the analysis ofΔID of subthreshold FGMOSFET, which is an often cited semiconductor based electronic device, has been performed. All related device level random variations, that is, ΔW, ΔL, ΔQ, Δn, and ΔI0 which cover variations in the physical parameters of I0, for example, ΔCox and ΔVth, Δki, Δkfd, Δkfs, and Δkfb and their statistical correlations, have been taken into account. Moreover, the low voltage/low power operating condition has also been concerned. The obtained result has been found to be very accurate since it can fit the nanometer level SPICE BSIM4 based reference with very high accuracy where the average error of each verification scenario has been, respectively, found to be 1.6245% (1.8904%) and 1.8244% (1.9518%) for N-type (P-type) subthreshold FGMOSFET.Based on the proposed analysis result, it has been found that the subthreshold FGMOSFET under low voltage/low power operating condition is subjected to largeΔID and the P-type subthreshold FGMOSFET has been found to be a more preferable device as it is more robust to the manufacturing process induced device level random variations than its N-type counterpart. It has also been found that ΔID can be minimized by minimizing Q, Cfd, Cfs, and Cfb, maximizing n, and avoiding the extremely low voltage/low power operating condition. The design technics for obtaining minimum Q, Cfd, Cfs, and Cfb and maximum n have been suggested. Moreover, the analysis of variation in the circuit level performance of any subthreshold FGMOSFET based circuit can be done based on the proposed result as illustrated above in which the subthreshold FGMOSFET based OTA has been focused on. So, the result of this research has been found to be beneficial to the variability aware analysis and design of subthreshold FGMOSFET based circuit which is an interesting semiconductor application.



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*Source: 3741250-2016-07-28.xml*