# Differential Difference Current Conveyor Transconductance Amplifier: A New Analog Building Block for Signal Processing

Authors: Neeta Pandey; Sajal K. Paul
Journal: Journal of Electrical and Computer Engineering
 (2011)

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## Abstract

A new active building block for analog signal processing, namely, differential difference current conveyor transconductance amplifier (DDCCTA), is presented, and performance is checked through PSPICE simulations which show the usability of the proposed element is up to 201 MHz. The proposed block is implemented using 0.25μm TSMC CMOS technology. Some of the applications are presented using the proposed DDCCTA, namely, a voltage mode multifunction filter, a current mode universal filter, an oscillator, current and voltage amplifiers, and grounded inductor simulator. The feasibility of DDCCTA and its applications is confirmed via PSPICE simulations.


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## Body

## 1. Introduction

The analog integrated circuit design in current mode is receiving increased attention due to some potential performance features like wide bandwidth, less circuit complexity, wide dynamic range, low power consumption, and high operating speed [1]. The current mode approach has emerged as an alternate method besides the traditional voltage mode circuits. The current mode active elements are appropriate to operate with signals in current or voltage or mixed mode and are gaining acceptance as building blocks in high-performance circuit designs. A number of current mode active elements such as operational transconductance amplifier (OTA) [2], current conveyors (CCs) [3–5], differential voltage current conveyor (DVCC) [6], differential difference current conveyor (DDCC) [7], current feedback operational amplifier (CFOA) [8] are available in the literature.Recently some new analog building blocks, such as current conveyor transconductance amplifier (CCTA) [9, 10], current controlled current conveyor transconductance amplifier (CCCCTA) [11], current difference transconductance amplifier (CDTA) [12], current controlled current difference transconductance amplifier (CCCDTA) [13], differential voltage current conveyor transconductance amplifier (DVCCTA) [14], and differential voltage current controlled conveyor transconductance amplifier (DVCCCTA) [15], are reported in the literature. These may be constructed by cascading of current mode building blocks with transconductance amplifier (TA) analog building blocks in monolithic chip for compact implementation of signal processing circuits and systems. It is well known that DDCC has some advantages [7, 16, 17] specially for applications demanding differential and floating inputs, over CCII or CCCII owing to three high input impedance terminals for DDCC compared to one high input impedance terminal for CCII or CCCII. However, DDCC does not have a powerful inbuilt tuning property in contrast to CCCII. The DDCC is more versatile than DVCC as it has an extra high input impedance terminal.The main intention of this paper is to propose a new active building block, namely, differential difference current conveyor transconductance amplifier (DDCCTA), which has DDCC [7] as input block and is followed by a TA. The DDCCTA has all the good properties of CCTA, CCCCTA, and DVCCTA including the possibility of inbuilt tuning of the parameters of the signal processing circuits to be implemented and also all the versatile and special properties of DDCC such as easy implementation of differential and floating input circuits. However, the same may be implemented using separate DDCC and OTA analog building blocks, but it will be more convenient and useful if DDCCTA is implemented in monolithic chip which will result in compact implementation of signal processing circuits and systems. Section 2 deals with the proposed DDCCTA circuit and some of its properties. Section 3 is devoted for some of its applications in developing signal processing circuits such as voltage mode (VM) filter, current mode (CM) filter, oscillator, current and voltage amplifier, and grounded inductor simulator. The functionality of all the proposed circuits has been verified using SPICE simulations. The conclusion is given in Section 4.


## 2. Proposed DDCCTA

The DDCCTA is based on DDCC [7] and consists of differential amplifier, current mirrors, and TA. The port relationships of the DDCCTA as shown in Figure 1 can be characterized by the following matrix: (1)[IY1IY2IY3VXIZ1+IZ2+I01-IO2-]=[0000000000000000000000001-110000000010000000100000000-gm0000000-gm000]×[VY1VY2VY3IXVZ1+VZ2+VO1-VO2-],
where gm is transcon/ductance of the DDCCTA.Figure 1
Circuit symbol of the proposed DDCCTA.The CMOS-based internal circuit of DDCCTA in CMOS is depicted in Figure2. It consists of the circuit of DDCC [7] (transistors M1 to M14) followed by a transconductance amplifier (transistors M15 to M24). The derivation of port relationships is given in Sections 2.1 to 2.3 [13].Figure 2
DDCCTA implementation.


### 2.1. Relationship between Voltages ofX Port and Y1, Y2, and Y3 Ports

The voltage atX port may be found by analyzing the differential difference part (comprising of transistors M1 to M10) of the circuit of Figure 2 as follows:(2)VX=β1VY1-β2VY2+βVY3+εV,
where(3)β1=1P1(gm3gm6+gm3(gm4gm5-gm3gm6)gm3+gm4),β2=1P1(gm1gm5+gm1(gm1gm5-gm2gm6)gm1+gm2),β3=1P1(gm2gm6+gm2(gm1gm5-gm2gm6)gm1+gm2),εV=-IBP1(gm1gm5-gm2gm6gm1+gm2+gm4gm5-gm3gm6gm3+gm4),P1=gm4gm5-gm4(gm4gm5-gm3gm6)gm3+gm4,
and IB represents current through transistor Mi (i=7,8,10,12,14). With matched transconductances gm1=gm2=gm3=gm4 and gm5=gm6, VX is obtained as(4)VX=VY1-VY2+VY3.


### 2.2. Relationship between Currents atZ1+, Z2+, and X Ports

The analysis of the portion of the circuit comprising of transistors M9 to M14 of the circuit of Figure2 gives(5)IZ1+=α1IX+εI1,IZ2+=α2IX+εI2,
where(6)α1=gm11gm9,εI1=(1-gm11gm9)IB,α2=gm13gm9,εI2=(1-gm13gm9)IB.
For matched transconductances gm9=gm11=gm13, the port currents are simplified to (7)IZ1+=IZ2+=IX.


### 2.3. Relation for Currents atO1- and O2- Ports

The proposed DDCCTA contains a transconductor cell comprising of transistors M15 to M24. Assuming gate voltages of transistors M17 and M18 asVT1 and VT2, the output currents IO1- and IO2- may be found, respectively, as(8)IO1-=-(γ1VT1-γ2VT2+εT1),IO2-=-(γ3VT1-γ4VT2+εT2),
where(9)γ1=gm17(gm16gm22gm15gm21-1gm15gm19gm21×(gm16gm17gm19gm22-gm15gm18gm20gm21gm17+gm18)),γ2=gm18(gm20gm19+1gm15gm19gm21×(gm16gm17gm19gm22-gm15gm18gm20gm21gm17+gm18)),γ3=gm17(gm16gm24gm15gm21-1gm15gm19gm21×(gm16gm17gm19gm24-gm15gm18gm23gm21gm17+gm18)),γ4=gm18(gm23gm19+1gm15gm19gm21×(gm16gm17gm19gm24-gm15gm18gm23gm21gm17+gm18)),εT1=-IBiasgm15gm19gm21×(gm16gm17gm19gm22-gm15gm18gm20gm21gm17+gm18),εT2=-IBiasgm15gm19gm21×(gm16gm17gm19gm24-gm15gm18gm23gm21gm17+gm18).
With gm17=gm18, gm21=gm22=gm24, gm15=gm16=gm19=gm20=gm23, the output currents IO1- and IO2- reduce to(10)IO1-=-(gm17VT1-gm18VT2),(11)IO2-=-(gm17VT1-gm18VT2).
In the circuit, VT1=VZ1+ and VT2=0; hence the output currents are simplified to (12)IO1-=-gm17VZ1+,IO2-=-gm17VZ1+.The value ofgm17 is obtained as 2μCox(W/L)17IBias if transistors are biased in strong inversion region and 2IBias/VT(VT=KT/q) if transistors are biased in subthreshold region which can be adjusted by bias current IBias.


### 2.4. Simulation

To validate the behaviour of the proposed element, PSPICE simulations have been carried out using TSMC 0.25μm CMOS process model parameters. The supply voltages of VDD=-VSS=1.25 V and VBB=-0.8 V are used. The aspect ratio of various transistors for DDCCTA is given in Table 1. The DC transfer characteristics of the proposed DDCCTA from Y1, Y2, and Y3 terminals to X terminal are shown in the Figure 3. It is clear that the voltage at X terminal follows the Y terminal voltages in the range of −200 mV to +200 mV. The variation of current at Z1+ and Z2+ terminals with X terminal current from −100 μA to 100 μA is shown in Figure 4. It may be noted that there is deviation for current below −80 μA. The variation of the transconductance value by changing IBias from 0 to 500 μA is depicted in Figure 5. The decreases in transconductance for larger bias currents than 450 μA or so is due to transistors (M17, M18) entering in linear region of operation from saturation region. The maximum transconductance is about 1.6 mS. The other circuit performance parameters of the DDCCTA are summarised in Table 2.Table 1
Aspect ratio of various transistors.
TransistorAspect ratio (W(μm)/L(μm))M1–M410/0.5M5, M65/0.5M7, M827.25/0.5M9, M11, M138.5/0.5M10, M12, M1444/0.5M15, M16, M19–M245/0.5M17, M1827/0.5Table 2
Circuit performance parameters of the DDCCTA.
Power consumption1.8 mWInput voltage linear range (voltage inputs)−200 mV to +200 mVInput current linear range (current input)−80μA to 100 μAParasitic atY ports (RY,CY)very high, 20 fFParasitic atZ ports (RZ,CZ)218 kΩ, 35 fFParasitic atO- ports (RO-,CO-)324 kΩ, 20 fF−3 dB bandwidth (at IBias=100μA)236 MHz forVX/VY223 MHz forIZ/Ix201 MHz forIO-/VzInput bias range for controlling transconductance amplifier10 nA to 450μADC transfer characteristic for voltage transfer from (a)Y1 port to X port, (b) Y2 port to X port, and (c) Y3 port to X port.
(a)(b)(c)Figure 4
DC transfer characteristic for current transfer fromX port to Z1+ and Z2+ ports.Figure 5
Variation of transconductance with bias current.


## 2.1. Relationship between Voltages ofX Port and Y1, Y2, and Y3 Ports

The voltage atX port may be found by analyzing the differential difference part (comprising of transistors M1 to M10) of the circuit of Figure 2 as follows:(2)VX=β1VY1-β2VY2+βVY3+εV,
where(3)β1=1P1(gm3gm6+gm3(gm4gm5-gm3gm6)gm3+gm4),β2=1P1(gm1gm5+gm1(gm1gm5-gm2gm6)gm1+gm2),β3=1P1(gm2gm6+gm2(gm1gm5-gm2gm6)gm1+gm2),εV=-IBP1(gm1gm5-gm2gm6gm1+gm2+gm4gm5-gm3gm6gm3+gm4),P1=gm4gm5-gm4(gm4gm5-gm3gm6)gm3+gm4,
and IB represents current through transistor Mi (i=7,8,10,12,14). With matched transconductances gm1=gm2=gm3=gm4 and gm5=gm6, VX is obtained as(4)VX=VY1-VY2+VY3.


## 2.2. Relationship between Currents atZ1+, Z2+, and X Ports

The analysis of the portion of the circuit comprising of transistors M9 to M14 of the circuit of Figure2 gives(5)IZ1+=α1IX+εI1,IZ2+=α2IX+εI2,
where(6)α1=gm11gm9,εI1=(1-gm11gm9)IB,α2=gm13gm9,εI2=(1-gm13gm9)IB.
For matched transconductances gm9=gm11=gm13, the port currents are simplified to (7)IZ1+=IZ2+=IX.


## 2.3. Relation for Currents atO1- and O2- Ports

The proposed DDCCTA contains a transconductor cell comprising of transistors M15 to M24. Assuming gate voltages of transistors M17 and M18 asVT1 and VT2, the output currents IO1- and IO2- may be found, respectively, as(8)IO1-=-(γ1VT1-γ2VT2+εT1),IO2-=-(γ3VT1-γ4VT2+εT2),
where(9)γ1=gm17(gm16gm22gm15gm21-1gm15gm19gm21×(gm16gm17gm19gm22-gm15gm18gm20gm21gm17+gm18)),γ2=gm18(gm20gm19+1gm15gm19gm21×(gm16gm17gm19gm22-gm15gm18gm20gm21gm17+gm18)),γ3=gm17(gm16gm24gm15gm21-1gm15gm19gm21×(gm16gm17gm19gm24-gm15gm18gm23gm21gm17+gm18)),γ4=gm18(gm23gm19+1gm15gm19gm21×(gm16gm17gm19gm24-gm15gm18gm23gm21gm17+gm18)),εT1=-IBiasgm15gm19gm21×(gm16gm17gm19gm22-gm15gm18gm20gm21gm17+gm18),εT2=-IBiasgm15gm19gm21×(gm16gm17gm19gm24-gm15gm18gm23gm21gm17+gm18).
With gm17=gm18, gm21=gm22=gm24, gm15=gm16=gm19=gm20=gm23, the output currents IO1- and IO2- reduce to(10)IO1-=-(gm17VT1-gm18VT2),(11)IO2-=-(gm17VT1-gm18VT2).
In the circuit, VT1=VZ1+ and VT2=0; hence the output currents are simplified to (12)IO1-=-gm17VZ1+,IO2-=-gm17VZ1+.The value ofgm17 is obtained as 2μCox(W/L)17IBias if transistors are biased in strong inversion region and 2IBias/VT(VT=KT/q) if transistors are biased in subthreshold region which can be adjusted by bias current IBias.


## 2.4. Simulation

To validate the behaviour of the proposed element, PSPICE simulations have been carried out using TSMC 0.25μm CMOS process model parameters. The supply voltages of VDD=-VSS=1.25 V and VBB=-0.8 V are used. The aspect ratio of various transistors for DDCCTA is given in Table 1. The DC transfer characteristics of the proposed DDCCTA from Y1, Y2, and Y3 terminals to X terminal are shown in the Figure 3. It is clear that the voltage at X terminal follows the Y terminal voltages in the range of −200 mV to +200 mV. The variation of current at Z1+ and Z2+ terminals with X terminal current from −100 μA to 100 μA is shown in Figure 4. It may be noted that there is deviation for current below −80 μA. The variation of the transconductance value by changing IBias from 0 to 500 μA is depicted in Figure 5. The decreases in transconductance for larger bias currents than 450 μA or so is due to transistors (M17, M18) entering in linear region of operation from saturation region. The maximum transconductance is about 1.6 mS. The other circuit performance parameters of the DDCCTA are summarised in Table 2.Table 1
Aspect ratio of various transistors.
TransistorAspect ratio (W(μm)/L(μm))M1–M410/0.5M5, M65/0.5M7, M827.25/0.5M9, M11, M138.5/0.5M10, M12, M1444/0.5M15, M16, M19–M245/0.5M17, M1827/0.5Table 2
Circuit performance parameters of the DDCCTA.
Power consumption1.8 mWInput voltage linear range (voltage inputs)−200 mV to +200 mVInput current linear range (current input)−80μA to 100 μAParasitic atY ports (RY,CY)very high, 20 fFParasitic atZ ports (RZ,CZ)218 kΩ, 35 fFParasitic atO- ports (RO-,CO-)324 kΩ, 20 fF−3 dB bandwidth (at IBias=100μA)236 MHz forVX/VY223 MHz forIZ/Ix201 MHz forIO-/VzInput bias range for controlling transconductance amplifier10 nA to 450μADC transfer characteristic for voltage transfer from (a)Y1 port to X port, (b) Y2 port to X port, and (c) Y3 port to X port.
(a)(b)(c)Figure 4
DC transfer characteristic for current transfer fromX port to Z1+ and Z2+ ports.Figure 5
Variation of transconductance with bias current.


## 3. Applications

### 3.1. Multifunction Voltage Mode Filter

In this section a multifunction voltage mode (VM) filter is proposed. It uses a single DDCCTA, two grounded capacitors, and a grounded resistor. The proposed multifunction VM filter is shown in Figure6. The analysis of circuit yields the output voltages at various nodes as(13)Vout1Vin=s2C1C2RD(s),Vout2Vin=sC2D(s),Vout3Vin=-gmD(s),
where(14)D(s)=s2C1C2R+sC2+gm.Figure 6
Proposed voltage mode filter.It may be observed from (13) that high-pass, band-pass, and low-pass responses are available simultaneously at Vout1, Vout2, and Vout3, respectively. Thus, the proposed structure is a single-input-and-three-output voltage mode filter. It may be noted that no component matching constraint is required. The responses are characterized by pole frequency (ω0), bandwidth (ω0/Q0), and quality factor (Q0) as(15)ω0=(gmRC1C2)1/2,ω0Q0=1RC1,Q0=(gmRC1C2)1/2.Equation (15) reveals that for high-pass and band-pass responses the pole frequency (ω0) and quality factor (Q0) can be adjusted by gm, that is, by bias current of DDCCTA, without disturbing ω0/Q0. The ω0 and Q0 are orthogonally adjustable with simultaneous adjustment of gm and R such that the product gmR remains constant and the quotient gm/R varies and vice versa. The resistance R being a grounded one may easily be implemented as a variable resistance using only two MOS [17]. Equation (15) also indicates that high values of Q-factor will be obtained from moderate values of ratios of passive components, that is, from low component spread [22]. These ratios can be chosen as gmR=(C1/C2)=Q0. Hence, the spread of the component values becomes of the order of Q0. This feature of the filter related to the component spread allows the realization of high Q0 values more accurately compared to the topologies where the spread of passive components becomes Q0 or Q02. It can also be easily evaluated to show that the sensitivities of pole ω0 and pole Q0 are within unity in magnitude. Thus, the proposed structures, can be classified as insensitive.A detailed study of the available similar type of single-active-element-based (such as CCCTA, DBTA, and DVCCCTA) voltage mode filters and the proposed one is given in Table3. It reveals that the topology [18, 19] uses excessive number of passive components whereas the proposed topology uses one extra passive component, namely, resistor (R) than [11, 15]. The proposed topology also provides the availability of a maximum number of simultaneous responses. Structures [11, 18, 19] use floating passive components and also use matching condition. Topology [11] needs input signal Vin, -Vin, and -2Vin; hence there is requirement of additional circuits. Thus, it reveals that although the proposed topology realizes only LP, HP, and BP responses, it has two or more advantages over the other available topologies [11, 15, 18, 19].Table 3
Comparative study of the available similar type of single-active-element-based VM filters.
ReferenceActive element used and number of passive componentsGrounded passive componentsAvailability of LP, HP, BP, notch, and AP responsesNumber of available simultaneous responsesNo inversion of input voltageNo requirement of gain of input signal such as2Vin and 3VinTunabilityNo matching condition[11]CCCCTA, 2NoAll1NoNoYesNo[15]DVCCCTA, 2Yes22YesYesYesYes[18]DBTA, 5NoLP, HP, BP, Notch1YesYesYesNo[19]DBTA,4NoAll2YesYesYesNoProposedDDCCTA, 3YesLP, HP, BP3YesYesYesYesLP: low pass; HP: high pass; BP: band pass; Notch: notch response; AP: all pass.To verify the functionality of the proposed single-DDCCTA-based voltage mode filter, SPICE simulations have been carried out using TSMC 0.25μm CMOS process model parameters and supply voltages of VDD=-VSS=1.25V and VBB=-0.8V. The filter is designed for a pole frequency of f0=1.59 MHz, Q=1, the component values are found to be C1=C2=100 pF, R=1 kΩ, and bias current of DVCCTA equals 100 μA. Figure 7 shows the simulation results for high-pass (Vout1), band-pass (Vout2), and low-pass (Vout3) filter responses which are available simultaneously.Figure 7
Simulated responses of the proposed voltage mode filter.


### 3.2. MISO Current Mode Universal Filter

A multiple-input single-output (MISO) universal current mode (CM) filter is proposed in this section which is obtained by grounding voltage input in Figure6 and exciting it with current inputs as shown in Figure 8. It employs a single DDCCTA, two grounded capacitors, and a grounded resistor. Analysis of this circuit gives the output current as(16)Iout1=-s2C1C2RIin1-(sC2+gm)Iin2+sC1Iin3D(s),Iout2=(Iin1-Iin2)sC2Rgm+gmIin3+D(s)Iin4D(s),
where (17)D(s)=s2C1C2R+sC2+gm.Figure 8
Current mode universal filter.Table4 shows the availability of each filter response and the corresponding selection of input currents Iin1, Iin2, Iin3, and Iin4. Thus, the proposed structure is a four-input-single-output current mode filter. It may be noted that there is no component matching constraint for obtaining any filter response. The filter parameters are the same as given in (15). The grounded resistance (R) may easily be implemented as variable one using only two MOS [17] for full electronic control of filter parameters. The ω0, Q0, and ω0/Q0 can be orthogonally adjusted for low-pass, high-pass, and band-pass responses the way discussed in Section 3.1.Table 4
TheIin1, Iin2, Iin3, and Iin4 values selection for each filter function response.
Filter responsesInputsOutputIin1Iin2Iin3Iin4Low pass0010Iout2Band pass0010Iout11000Iout20100Iout2High pass1000Iout1Notch0101Iout2, R = 1/gmAll pass0101Iout2, R = 1/gmA detailed study of the available similar type of active-element-based (such as CCCCTA, CCCDTA, and CCCCTA) CM filters and the proposed one is given in Table5. It reveals that although the proposed structure needs one extra resistor, the reported structures [11, 13, 20, 21] suffer from one or more features. In addition some active elements are required to sense current in [13, 21]. Thus, structures in [11, 13, 20, 21] will require some extra circuits to compensate the shortcomings in their features in comparison to the proposed one.Table 5
Comparative study of the available similar type of single-active-element-based CM filters.
ReferenceActive element used and number of passive componentsGrounded passive componentsAvailability of LB, HP, BP, notch, and AP responsesNo requirement of current inversionNo requirement of gain of input signal such as 2Iin and 3IinOutput current at high impedanceTunabilitySimple/no matching condition[11]CCCCTA, 2YesYesYesNoYesYesYes[13]CCCDTA, 2YesYesNoYesNoYesYes[20]CCCDTA, 2YesYesYesNoYesYesYes[21]CCCCTA, 2YesNoYesYesNoYesYesProposedDVCCTA, 3YesYesYesYesYesYesYesLP: low pass; HP: high pass; BP: band pass; Notch: notch response; AP: all pass.The proposed universal MISO current mode filter is validated through SPICE simulations. The circuit of Figure8 for a pole frequency of f0=1.59  MHz, Q=1 has been designed with the component values of C1=C2=100 pF, R=1 kΩ, and bias current of DDCCTA equal to 100 μA. Figure 9(a) shows the simulation results for band pass (Iout1) and low pass (Iout2) filter responses which are available simultaneously for Iin=Iin3, Iin1=Iin2=Iin4=0. Figure 9(b) shows the simulation results for band pass (Iout2) and high-pass (Iout1) filter responses which are available simultaneously for Iin=Iin1, Iin2=Iin3=Iin4=0. Notch and all pass responses are shown in Figures 9(c) and 9(d) with Iin=Iin2=Iin4, Iin1=Iin3=0 and R=1 kΩ and 2 kΩ, respectively.Simulated responses of the proposed current mode universal filter: (a) low pass and band pass; (b) high pass and band pass; (c) notch; (d) all pass.
(a)(b)(c)(d)


### 3.3. Oscillator

The current mode filter of Figure8 may be used as oscillator when output Iout2 is connected to Iin1 as shown in Figure 10. The analysis of the circuit of Figure 10 gives the following characteristic equation:(18)s2C1C2R+sC2(Rgm-1)+gm=0.
The condition and frequency of oscillation may be computed as
(19)CO:gm=1R,FO:ω0=gmRC1C2.
The oscillations are available at outputs Vout1 and Vout2, and they are related as(20)Vout1=-gmsC2Vout2.
Thus, these voltages exhibit quadrature relationship. The current oscillations are also available at high output impedance at Iout.Figure 10
Proposed Oscillator.To verify the proposed circuit, an oscillator was designed for 1.59 MHz withC1=C2=100 pF, R=1 kΩ, and bias current of 100 μA. The simulated current and quadrature voltage waveforms are shown in Figure 11 for which the total harmonic distortion is 1.28%.Outputs of the proposed oscillator: (a) quadrature output voltages atVout1 and Vout2; (b) current oscillation at Iout.
(a)(b)


### 3.4. Voltage Amplifier, Current Amplifier, and Grounded Inductor

The proposed DDCCTA may also be configured for voltage and current amplifiers and grounded inductor simulator as shown in Figures12, 13, and 14, respectively. The transfer functions may be expressed as follows:Figure 12
Voltage amplifier.Figure 13
Current amplifier.Figure 14
Grounded inductor simulator.(i) voltage amplifier:(21)VoutVin=1Rgm,(ii) current amplifier:(22)IoutIin=Rgm,(iii) grounded inductor simulator:(23)Zin=VinIin=sCRgm.
It may be noted that the gain of amplifiers and inductance can be adjusted by gm, that is, by varying bias current of DDCCTA.To verify the proposed amplifiers, the simulations have been carried out forR=0.5 kΩ (2 kΩ) for voltage (current) amplifier and bias current of 25 μA to 400 μA. The results are depicted in Figures 15 and 16. The inductor simulator is also validated through simulation with R=0.5 KΩ, C=100 pF, and bias current of 90 μA. Figure 17 shows the simulated and theoretical results and there is close agreement between the two.Figure 15
Voltage gain.Figure 16
Current gain.Figure 17
Frequency response of grounded inductor.


## 3.1. Multifunction Voltage Mode Filter

In this section a multifunction voltage mode (VM) filter is proposed. It uses a single DDCCTA, two grounded capacitors, and a grounded resistor. The proposed multifunction VM filter is shown in Figure6. The analysis of circuit yields the output voltages at various nodes as(13)Vout1Vin=s2C1C2RD(s),Vout2Vin=sC2D(s),Vout3Vin=-gmD(s),
where(14)D(s)=s2C1C2R+sC2+gm.Figure 6
Proposed voltage mode filter.It may be observed from (13) that high-pass, band-pass, and low-pass responses are available simultaneously at Vout1, Vout2, and Vout3, respectively. Thus, the proposed structure is a single-input-and-three-output voltage mode filter. It may be noted that no component matching constraint is required. The responses are characterized by pole frequency (ω0), bandwidth (ω0/Q0), and quality factor (Q0) as(15)ω0=(gmRC1C2)1/2,ω0Q0=1RC1,Q0=(gmRC1C2)1/2.Equation (15) reveals that for high-pass and band-pass responses the pole frequency (ω0) and quality factor (Q0) can be adjusted by gm, that is, by bias current of DDCCTA, without disturbing ω0/Q0. The ω0 and Q0 are orthogonally adjustable with simultaneous adjustment of gm and R such that the product gmR remains constant and the quotient gm/R varies and vice versa. The resistance R being a grounded one may easily be implemented as a variable resistance using only two MOS [17]. Equation (15) also indicates that high values of Q-factor will be obtained from moderate values of ratios of passive components, that is, from low component spread [22]. These ratios can be chosen as gmR=(C1/C2)=Q0. Hence, the spread of the component values becomes of the order of Q0. This feature of the filter related to the component spread allows the realization of high Q0 values more accurately compared to the topologies where the spread of passive components becomes Q0 or Q02. It can also be easily evaluated to show that the sensitivities of pole ω0 and pole Q0 are within unity in magnitude. Thus, the proposed structures, can be classified as insensitive.A detailed study of the available similar type of single-active-element-based (such as CCCTA, DBTA, and DVCCCTA) voltage mode filters and the proposed one is given in Table3. It reveals that the topology [18, 19] uses excessive number of passive components whereas the proposed topology uses one extra passive component, namely, resistor (R) than [11, 15]. The proposed topology also provides the availability of a maximum number of simultaneous responses. Structures [11, 18, 19] use floating passive components and also use matching condition. Topology [11] needs input signal Vin, -Vin, and -2Vin; hence there is requirement of additional circuits. Thus, it reveals that although the proposed topology realizes only LP, HP, and BP responses, it has two or more advantages over the other available topologies [11, 15, 18, 19].Table 3
Comparative study of the available similar type of single-active-element-based VM filters.
ReferenceActive element used and number of passive componentsGrounded passive componentsAvailability of LP, HP, BP, notch, and AP responsesNumber of available simultaneous responsesNo inversion of input voltageNo requirement of gain of input signal such as2Vin and 3VinTunabilityNo matching condition[11]CCCCTA, 2NoAll1NoNoYesNo[15]DVCCCTA, 2Yes22YesYesYesYes[18]DBTA, 5NoLP, HP, BP, Notch1YesYesYesNo[19]DBTA,4NoAll2YesYesYesNoProposedDDCCTA, 3YesLP, HP, BP3YesYesYesYesLP: low pass; HP: high pass; BP: band pass; Notch: notch response; AP: all pass.To verify the functionality of the proposed single-DDCCTA-based voltage mode filter, SPICE simulations have been carried out using TSMC 0.25μm CMOS process model parameters and supply voltages of VDD=-VSS=1.25V and VBB=-0.8V. The filter is designed for a pole frequency of f0=1.59 MHz, Q=1, the component values are found to be C1=C2=100 pF, R=1 kΩ, and bias current of DVCCTA equals 100 μA. Figure 7 shows the simulation results for high-pass (Vout1), band-pass (Vout2), and low-pass (Vout3) filter responses which are available simultaneously.Figure 7
Simulated responses of the proposed voltage mode filter.


## 3.2. MISO Current Mode Universal Filter

A multiple-input single-output (MISO) universal current mode (CM) filter is proposed in this section which is obtained by grounding voltage input in Figure6 and exciting it with current inputs as shown in Figure 8. It employs a single DDCCTA, two grounded capacitors, and a grounded resistor. Analysis of this circuit gives the output current as(16)Iout1=-s2C1C2RIin1-(sC2+gm)Iin2+sC1Iin3D(s),Iout2=(Iin1-Iin2)sC2Rgm+gmIin3+D(s)Iin4D(s),
where (17)D(s)=s2C1C2R+sC2+gm.Figure 8
Current mode universal filter.Table4 shows the availability of each filter response and the corresponding selection of input currents Iin1, Iin2, Iin3, and Iin4. Thus, the proposed structure is a four-input-single-output current mode filter. It may be noted that there is no component matching constraint for obtaining any filter response. The filter parameters are the same as given in (15). The grounded resistance (R) may easily be implemented as variable one using only two MOS [17] for full electronic control of filter parameters. The ω0, Q0, and ω0/Q0 can be orthogonally adjusted for low-pass, high-pass, and band-pass responses the way discussed in Section 3.1.Table 4
TheIin1, Iin2, Iin3, and Iin4 values selection for each filter function response.
Filter responsesInputsOutputIin1Iin2Iin3Iin4Low pass0010Iout2Band pass0010Iout11000Iout20100Iout2High pass1000Iout1Notch0101Iout2, R = 1/gmAll pass0101Iout2, R = 1/gmA detailed study of the available similar type of active-element-based (such as CCCCTA, CCCDTA, and CCCCTA) CM filters and the proposed one is given in Table5. It reveals that although the proposed structure needs one extra resistor, the reported structures [11, 13, 20, 21] suffer from one or more features. In addition some active elements are required to sense current in [13, 21]. Thus, structures in [11, 13, 20, 21] will require some extra circuits to compensate the shortcomings in their features in comparison to the proposed one.Table 5
Comparative study of the available similar type of single-active-element-based CM filters.
ReferenceActive element used and number of passive componentsGrounded passive componentsAvailability of LB, HP, BP, notch, and AP responsesNo requirement of current inversionNo requirement of gain of input signal such as 2Iin and 3IinOutput current at high impedanceTunabilitySimple/no matching condition[11]CCCCTA, 2YesYesYesNoYesYesYes[13]CCCDTA, 2YesYesNoYesNoYesYes[20]CCCDTA, 2YesYesYesNoYesYesYes[21]CCCCTA, 2YesNoYesYesNoYesYesProposedDVCCTA, 3YesYesYesYesYesYesYesLP: low pass; HP: high pass; BP: band pass; Notch: notch response; AP: all pass.The proposed universal MISO current mode filter is validated through SPICE simulations. The circuit of Figure8 for a pole frequency of f0=1.59  MHz, Q=1 has been designed with the component values of C1=C2=100 pF, R=1 kΩ, and bias current of DDCCTA equal to 100 μA. Figure 9(a) shows the simulation results for band pass (Iout1) and low pass (Iout2) filter responses which are available simultaneously for Iin=Iin3, Iin1=Iin2=Iin4=0. Figure 9(b) shows the simulation results for band pass (Iout2) and high-pass (Iout1) filter responses which are available simultaneously for Iin=Iin1, Iin2=Iin3=Iin4=0. Notch and all pass responses are shown in Figures 9(c) and 9(d) with Iin=Iin2=Iin4, Iin1=Iin3=0 and R=1 kΩ and 2 kΩ, respectively.Simulated responses of the proposed current mode universal filter: (a) low pass and band pass; (b) high pass and band pass; (c) notch; (d) all pass.
(a)(b)(c)(d)


## 3.3. Oscillator

The current mode filter of Figure8 may be used as oscillator when output Iout2 is connected to Iin1 as shown in Figure 10. The analysis of the circuit of Figure 10 gives the following characteristic equation:(18)s2C1C2R+sC2(Rgm-1)+gm=0.
The condition and frequency of oscillation may be computed as
(19)CO:gm=1R,FO:ω0=gmRC1C2.
The oscillations are available at outputs Vout1 and Vout2, and they are related as(20)Vout1=-gmsC2Vout2.
Thus, these voltages exhibit quadrature relationship. The current oscillations are also available at high output impedance at Iout.Figure 10
Proposed Oscillator.To verify the proposed circuit, an oscillator was designed for 1.59 MHz withC1=C2=100 pF, R=1 kΩ, and bias current of 100 μA. The simulated current and quadrature voltage waveforms are shown in Figure 11 for which the total harmonic distortion is 1.28%.Outputs of the proposed oscillator: (a) quadrature output voltages atVout1 and Vout2; (b) current oscillation at Iout.
(a)(b)


## 3.4. Voltage Amplifier, Current Amplifier, and Grounded Inductor

The proposed DDCCTA may also be configured for voltage and current amplifiers and grounded inductor simulator as shown in Figures12, 13, and 14, respectively. The transfer functions may be expressed as follows:Figure 12
Voltage amplifier.Figure 13
Current amplifier.Figure 14
Grounded inductor simulator.(i) voltage amplifier:(21)VoutVin=1Rgm,(ii) current amplifier:(22)IoutIin=Rgm,(iii) grounded inductor simulator:(23)Zin=VinIin=sCRgm.
It may be noted that the gain of amplifiers and inductance can be adjusted by gm, that is, by varying bias current of DDCCTA.To verify the proposed amplifiers, the simulations have been carried out forR=0.5 kΩ (2 kΩ) for voltage (current) amplifier and bias current of 25 μA to 400 μA. The results are depicted in Figures 15 and 16. The inductor simulator is also validated through simulation with R=0.5 KΩ, C=100 pF, and bias current of 90 μA. Figure 17 shows the simulated and theoretical results and there is close agreement between the two.Figure 15
Voltage gain.Figure 16
Current gain.Figure 17
Frequency response of grounded inductor.


## 4. Conclusion

A new analog building block, namely, DDCCTA, is presented and some of its properties are discussed. It is found that the proposed DDCCTA is useful up to about 201 MHz. As applications of the proposed DDCCTA, VM multifunction filter, CM universal filter, quadrature oscillator, voltage and current amplifiers, and grounded inductor simulator topology are presented. The resistor being grounded may easily be implemented as a variable one using only two MOS [17]. The simulation results verify the theory.



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*Source: 361384-2011-11-30.xml*