# Break-before-Make CMOS Inverter for Power-Efficient Delay Implementation

Authors: Janez Puhan; Dušan Raič; Tadej Tuma; Árpád Bűrmen
Journal: The Scientific World Journal
 (2014)

---

## Abstract

A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.


---

## Body

## 1. Introduction

Serial connection of inverters is often used for implementing low-precision delay in digital systems. However, the delay of cascaded inverters is power efficient only for small delays, which leads to an excessive power loss when longer delays are required. Each inverter in the chain drains additional parasitic energy that is approximately equal to the dynamic energy required for changing its input. Often the number of delay stages in a chain is reduced at the expense of increased node capacitances as long as capacitive loads do not introduce excessive direct-path energy.Direct-path current is a well-known source of internal dynamic power consumption in CMOS logic. In well-designed circuits, it is estimated to be less than 20% of the dynamic dissipation [1] but may prohibitively increase in circuits with significant capacitive loads. The problem is efficiently solved if NMOS and PMOS gates of the CMOS inverter are driven by separate, time-skewed signals. This solution has been applied for large capacitive loads in [2] and later in [3–5]. All of these circuits have additional driving stages inserted in front of the split inverter inputs. The overhead of the additional components in terms of area and power consumption is justified only if it is outweighed by the savings obtained in the driving stages of large capacitive loads. On the gate-level logic, the overhead is hardly justified since the loads are small. Other gate-level techniques have also been proposed with the aim of reducing internal static power due to leakage currents in nanometer technologies [6, 7]. These techniques come with an area overhead and do not improve internal dynamic power.The solution proposed in Figure1 addresses the internal dynamic power consumption problem by inserting a bidirectional delay element at the inverter output to provide time-skewed signals for the next split-input inverter stage. The proposed structure provides break-before-make (BBM) switching with very low component overhead. No additional stages are needed. The overhead is low enough for the circuit to be used with small loads that are common in gate-level circuit design.BBM inverter structures with time domain responses: (a) CMOS to BBM converter, (b) BBM inverter, and (c) BBM to CMOS converter.
(a)
(b)
(c)


## 2. Circuit Operation

Input signal is transformed into two time-skewed signals by CMOS to BBM converter in Figure1(a). At high to low transition of the input signaldi both transistors switch, the PMOS opens and the NMOS goes into high-impedance state. The PMOS pulls the output node p
o to logical high. The delay t
d
f is defined by the PMOS transistor. The output node n
o follows with delay defined by the bidirectional delay element. Similar process is repeated in the opposite direction at low to high transition of d
i. Output signal pair p
o, n
o of the CMOS to BBM converter is used as input time-skewed signals p
i, n
i for the proposed inverter in Figure 1(b).The proposed inverter is composed of a serially connected PMOS transistor, a bidirectional delay element, and a NMOS transistor. Circuit operation is best explained by an ideal transport delay timing diagram (Figure1(b) right). The inverter input and output signals are applied as signal pairs p
i, n
i and p
o, n
o, respectively. From the point of view of static signals, the two signals in a signal pair represent the same logical level. Because of the built-in delay, they never change simultaneously. The first transition also referred to asisolation (nonbold slope in timing diagram in Figure 1(b)) is followed by the second transition also referred to asinformation (bold slope in timing diagram in Figure 1(b)). The isolation slope always precedes the information slope in any logical transition. Isolation time t
i is the time interval between the isolation and the information. During the isolation time, the inverter output is in a high-impedance state (indicated by the grayed output signal areas in timing diagram in Figure 1(b)), preserving the old logical state on capacitive load and preventing the direct-path current from flowing between the power supply and the ground.Let us first assume that the input nodesp
i and n
i change from logical low to logical high, as presented in timing diagram in Figure 1(b). The voltage on node p
i rises first, representing the isolation slope. The information slope at node n
i follows after the rising isolation time t
i
r. The isolation slope switches the PMOS transistor into a high-impedance state. The old logical state is preserved on a capacitive load until the information slope opens the NMOS transistor and pulls the output node n
o to logical low. Because of the bidirectional delay element, the output node p
o transits to logical low later than node n
o and the state switching transient is complete. A similar process takes place when p
i and n
i transits from logical high to logical low.The input isolation times are reproduced at the output thus allowing cascaded operation. Time skewing between input and output nodes of serially connected inverters is therefore guaranteed throughout the whole cascade.Now, let us assume that one or both isolation timest
i
r, t
i
f are increased. This increases the time during which both transistors are in a high-impedance state but do not affect the skew between the output signals. The later depends only on the bidirectional delay element. Isolation times of serially connected inverters therefore do not accumulate from stage to stage. If the isolation time is reduced, the circuit functionality is maintained until t
i
r or t
i
f becomes zero, and the circuit operation becomes identical to that of a standard CMOS inverter. Generally, the isolation slopes are defined by the inverter transistors, while the information slopes are defined by the delay element.The role of input signals differs depending on the transition. Isolation slope is the falling edge at the NMOS gate or the rising edge at the PMOS gate. Similarly, the rising edge at the NMOS gate and the falling edge at the PMOS gate represent information slope. Because of dual input and output signals, the standard timing parameters must be redefined. Delay timest
d
r and t
d
f are defined between input information slope and output isolation slope as presented in timing diagram in Figure 1(b). Standard rise and fall time definitions (10% to 90% and vice versa) apply to each signal separately. Isolation times t
i
r and t
i
f are defined as the delay between the isolation slope and the corresponding information slope.Time-skewed input signals are merged back into a single output by BBM to CMOS converter in Figure1(c). An isolation falling slope on n
i is followed by the information falling slope on p
i. The first switches the NMOS transistor into a high-impedance state. Low logical state on output d
o is preserved on capacitive load until the information slope opens the PMOS transistor. During the isolation time t
i
f, the converter output is in a high-impedance state. The PMOS pulls the output node d
o to logical high with delay t
d
f. Similar process is going on at rising isolation and information slopes.The propagation delayT
p is defined as the average of the low-to-high (t
d
LH
⁡) and the high-to-low (t
d
HL) transition. For BBM inverter (Figure 1(b)), t
d
LH
⁡
=
t
i
r
+
t
d
f and t
d
HL
=
t
i
f
+
t
d
r. For a symmetric circuit with t
d
r
=
t
d
f
=
t
d and t
i
r
=
t
i
f
=
t
i, the propagation delay is given by
(1)
T
p
=
t
i
r
+
t
d
f
+
t
i
f
+
t
d
r
2
=
t
d
+
t
i
.
Assuming that t
d is proportional to the equally sized standard CMOS inverter propagation delay (T
p
,
CMOS), the following linear relation can be obtained:
(2)
T
p
=
k
1
T
p
,
CMOS
+
t
i
.
By definition, T
p
,
CMOS is the average of the rise and the fall delay (t
d
LH
⁡
,
CMOS and t
d
HL
,
CMOS) of a CMOS inverter. Eliminated direct path in the proposed inverter provides more switching current for charging and discharging the capacitive load represented by the next stage. Therefore, t
d
<
t
d
,
CMOS and k
1
<
1.


## 3. Charge Delay Analysis

Circuit power efficiency is measured by the power-delay product (PDP) and energy-delay product (EDP
=
PDP
T
p) [8, 9]. PDP corresponds to the energy required for one gate switch. EDP, on the other hand, represents a trade-off between energy and performance. Usually, PDP and EDP should be as low as possible thus resulting in minimum delay at minimal possible energy consumption.When designing a low-precision delay, the situation is turned upside down. The goal is to implement the required delayT
p at lowest possible energy consumption. EDP can be reduced by reducing the supply voltage or the charge. Because the supply voltage cannot be changed, this means that we are looking for minimal charge Q required for implementing delay T
p.A standard two-stage CMOS buffer is depicted in Figure2. A simplified transistor model (3) [10] is assumed. The model merges transistor geometry and technology parameters into factor β
=
(
μ
ɛ
/
t
o
x
)
(
w
/
l
), where μ is surface mobility of the carriers, ɛ and t
o
x are permittivity and thickness of the gate insulator, and w and l are transistor channel’s width and length, respectively. Transistor capacitances are represented by C
L
P and C
L
N. Consider
(3)
i
d
=
0
v
g
s
≤
V
T
β
v
g
s
-
V
T
v
d
s
-
v
d
s
2
2
v
d
s
≤
v
g
s
-
V
T
β
2
v
g
s
-
V
T
2
v
d
s
>
v
g
s
-
V
T
.
If input signal rise and fall times are zero, then no direct-path current is present in the first stage. Dynamic charge (4) charging and discharging capacitive loads C
L
P and C
L
N represents the only consumption in the first stage. Consider
(4)
Q
d
=
∫
t
0
t
0
+
T
‍
i
1
+
i
C
d
t
=
C
L
P
+
C
L
N
V
D
D
.
By solving the Kirchhoff’s current law for the internal node, input rise and fall times for the second stage can be obtained. They can be approximated by (5) [11]. Consider
(5)
i
d
N
1
+
C
L
P
v
i
-
V
D
D
′
+
C
L
N
v
i
′
=
0
,
i
d
P
1
+
C
L
P
v
i
-
V
D
D
′
+
C
L
N
v
i
′
=
0
,
t
f
=
k
2
C
L
P
+
C
L
N
β
N
1
V
D
D
,
t
r
=
k
3
C
L
P
+
C
L
N
β
P
1
V
D
D
.
Constants k
2 and k
3 are equal for V
T
N
=
-
V
T
P.Figure 2
Two-stage CMOS buffer.The second stage has no load. Internal voltage is directly transferred to the output. Therefore, no dynamic consumption is present in the second stage. Since rise and fall times (5) of the second stage input signal are not zero, direct-path current flows during the transition resulting in charge:
(6)
Q
s
=
∫
t
0
t
0
+
T
‍
i
2
d
t
.
With a linear approximation of the internal voltage transitions during rise and fall times (5), the static charge can be calculated as
(7)
Q
s
=
β
N
2
6
V
D
D
V
D
D
+
V
T
P
-
V
T
N
3
1
+
β
N
2
/
β
P
2
2
t
r
+
t
f
.
Because there is no capacitive load, no delay is added in the second stage. The low-to-high and the high-to-low output delays are proportional to t
f and t
r, respectively. Consider
(8)
t
d
LH
⁡
,
CMOS
=
k
4
t
f
,
t
d
HL
,
CMOS
=
k
5
t
r
.
If the second stage is symmetric, k
4
=
k
5
=
1
/
2.AssumingV
T
N
=
-
V
T
P
=
V
T and symmetric first stage β
N
1
=
β
P
1
=
β
1, the rise and the fall times t
r, t
f  (5) are equal. Additional symmetry in the second stage β
N
2
=
β
P
2
=
β
2 simplifies the Q
(
T
p
,
CMOS
) relation into
(9)
Q
=
Q
d
+
Q
s
=
2
β
1
V
D
D
2
k
2
+
β
2
6
V
D
D
V
D
D
-
2
V
T
3
T
p
,
CMOS
.
The propagation delay can be expressed as
(10)
T
p
,
CMOS
=
t
d
LH
⁡
,
CMOS
=
t
d
HL
,
CMOS
=
k
2
C
L
P
+
C
L
N
2
β
1
V
D
D
.
The propagation delay is generated by the first stage (β
1) and the second stage gate capacitances. The static and the dynamic consumption increases linearly with T
p
,
CMOS.


## 4. Bidirectional Delay Implementation

In the simplest case, the bidirectional delay can be implemented with a single resistorR
d (Figure 3), which in combination with the capacitances of the next stage provides the isolation time.Figure 3
Two-stage BBM buffer with RC delay implementation.The dynamic charge (4) required for charging and discharging capacitive loads C
L
P and C
L
N remains the only cause for the power consumption in the first stage.Internal node voltagev
i
P, v
i
N transients are required for computing the isolation times. Equations (11) and (12) must be solved to obtain t
d
f, t
i
f and t
d
r, t
i
r, respectively. Consider
(11)
i
d
N
1
+
C
L
P
v
i
P
-
V
D
D
′
+
C
L
N
v
i
N
′
=
0
,
v
i
N
-
v
i
P
=
R
d
C
L
P
v
i
P
-
V
D
D
′
,
(12)
i
d
P
1
+
C
L
P
v
i
P
-
V
D
D
′
+
C
L
N
v
i
N
′
=
0
,
v
i
P
-
v
i
N
=
R
d
C
L
N
v
i
N
′
.
The solution of the equations is complicated and is not appropriate for manual calculation.Discharging load capacitancesC
L
P and C
L
N can be dealt with separately in (11) assuming high R
d. R
d
→
∞ causes v
i
P
′
→
0 and C
L
N is discharged first. Influence of C
L
P current is negligible. Equation (11) simplifies into i
d
N
1
+
C
L
N
v
i
N
′
=
0. The same deduction holds for charging load capacitances C
L
P and C
L
N in (12). R
d
→
∞ causes v
i
N
′
→
0 and (12) simplifies into i
d
P
1
+
C
L
P
v
i
P
-
V
D
D
′
=
0. Delay times t
d
f and t
d
r can be obtained by solving the simplified versions of (11) and (12) as in (5)(13)
t
d
f
=
k
6
C
L
N
β
N
1
V
D
D
,
t
d
r
=
k
7
C
L
P
β
P
1
V
D
D
.
The isolation time depends on the RC constant. Consider
(14)
t
i
f
=
k
8
R
d
C
L
P
,
t
i
r
=
k
8
R
d
C
L
N
.
Constants k
6 and k
7 are equal for V
T
N
=
-
V
T
P.Since node voltagesv
i
P and v
i
N are time skewed, static consumption Q
s in the second stage is zero. The total consumption is therefore equal to the dynamic consumption in the first stage (4). Assuming V
T
N
=
-
V
T
P
=
V
T and symmetric first stage β
N
1
=
β
P
1
=
β
1, the propagation delay (1) can be expressed as
(15)
T
p
=
k
6
β
1
V
D
D
+
k
8
R
d
C
L
P
+
C
L
N
2
,
which can be used to obtain
(16)
Q
=
2
β
1
V
D
D
2
k
6
+
k
8
R
d
β
1
V
D
D
T
p
.
Charge consumption again linearly increases with propagation delay.To ensure rise and fall delay symmetryt
d
LH
⁡
=
t
d
f
+
k
9
t
i
f
=
t
d
HL
=
t
d
r
+
k
10
t
i
r, a balance among variables in (13) and (14) is required. If both stages are symmetric and V
T
N
=
-
V
T
P, then the second stage gate capacitances must also be equal (C
L
P
=
C
L
N). Capacitances C
L
P and C
L
N depend only on the gate capacitance in the first approximation. The condition C
L
P
=
C
L
N can be met by increasing channel length of the second stage NMOS transistor, which degrades its driving performance. Yet another way is to assume that capacitive load is composed of gate capacitance and various stray capacitances (C
L
=
C
gate
+
C
stray). Smaller NMOS gate can be partly compensated by adding more parasitic capacitance to the NMOS gate. Larger parasitic NMOS stray capacitance can be introduced by different gate connections in case the layout allows such modifications.The analysis above holds ifR
d is high enough and static consumption Q
s is consequently negligible. The isolation slope must end before the information slope begins. In the first approximation conditions,
(17)
k
2
C
L
N
β
N
1
V
D
D
<
k
11
R
d
C
L
P
,
k
3
C
L
P
β
P
1
V
D
D
<
k
11
R
d
C
L
N
must be fulfilled, leading to
(18)
R
d
>
max
⁡
k
2
C
L
N
k
11
C
L
P
β
N
1
V
D
D
,
k
3
C
L
P
k
11
C
L
N
β
P
1
V
D
D
.
The dependency of Q
s on R
d is depicted in Figure 4.Figure 4
Q
s
(
R
d
) dependence obtained with SPICE simulation for V
T
N
=
0.5
V, V
T
P
=
-
0.5
V, K
P
N
=
350
μ
A
/
V
2, K
P
P
=
90
μ
A
/
V
2, C
o
x
=
8.6
mAs
/
V
m
2, V
D
D
=
1.8
V, w
P
1
=
860
nm, l
P
1
=
180
nm, w
N
1
=
220
nm, l
N
1
=
180
nm, w
P
2
=
310
nm, l
P
2
=
180
nm, w
N
2
=
220
nm, and l
N
2
=
250
nm.Although the concept of introducing a bidirectional delay usingR
d can be expanded to logic gates, the overhead of increased delay combined with double wiring hardly justifies the energy savings. This approach shows its advantage in circuits with productive use of delay, such as edge-triggered storage elements and clock distribution networks.


## 5. Optimization Problem

Analysis of the circuit in Figure3 shows that obtaining a specific delay t
requested with minimum charge consumption is an optimization problem. Minimum of the function Q
(
R
d
,
w
,
l
) represent the optimal solution. Vectors w and l represent transistor channel widths and lengths, which define gain factors (β) and capacitances. The implicit constraint t
d
LH
⁡
=
t
d
HL
=
t
requested is imposed on the solution.Delay implementation withR
d causes long charging phases of C
L
P and C
L
N. Transient phenomena of the information slope may not be concluded before the transistors in the next stage switch state (Figure 5). The input signal must remain constant during the transient. Otherwise the next delay is shortened. For this reason another implicit constraint defining the maximum length of the transient is introduced into the optimization problem k
12
R
d
C
L
P
<
t
max
⁡ and k
12
R
d
C
L
N
<
t
max
⁡. The input signal must stay constant for at least t
max
⁡ after every transition.Figure 5
Transient phenomena obtained with SPICE simulation forR
d
=
10
k
Ω.The manual calculation is derived from a simplified static transistor model (3). Dynamic behavior is modeled with constant gate capacitances C
L
P and C
L
N. These capacitances are voltage dependent. The optimization procedure of a real world BBM buffer must consider numerous higher order effects that were neglected in the first approximation, such as:(i)
input signal is not an ideal rectangular shape voltage generator,
(ii)
output load is not zero,
(iii)
the MOSFET should include model with higher order static (channel-length modulation, short-channel effect, sub-threshold conductivity, etc.) and dynamic (nonlinear capacitances, etc.) effects,
(iv)
parasites (layout, wiring, etc.) have to be taken into account.


## 6. Transistor-Based Delay Implementation

R
d implementation with high-resistance polysilicon is area consuming and poorly controlled. One or more MOS transistors can be used instead. If a single delay transistor is connected as a diode or a triode (Figure 6), then the output voltage swing is reduced. The voltage drop is defined by the threshold voltage of the delay transistor V
T
d. Voltage swing reduction applies to one or both outputs depending on the configuration. This has several implications. The dynamic charge Q
d  (4) is reduced from C
L
V
D
D to C
L
V
swing consequently reducing the power consumption. This causes the delay to increase due to transistor’s high resistance in the saturation region and results in long transient phenomena in the information slope. On the other hand, the lower voltage swing is required for reaching the threshold voltage of the next stage, which in turn decreases the delay. A fairly high supply voltage V
D
D
>
5
V
T
d is required. Long information transients and high supply voltage make the reduced swing topologies inappropriate.Figure 6
Single transistor delay implementations (*the threshold voltage modified due to the body effect). Transistors Pd and Nd are connected as diodes while transistors Pt and Nt are connected as triodes.Full-swing can be achieved with additional level restoration transistors (Figure7). The PMOS (NMOS) level restoration transistor restores the high (low) level. Level restoration transistor(s) can be combined in parallel with any delay element from Figure 6. Controlling signals p
c, n
c are delayed input signals p
i, n
i, which can for instance be obtained at the next stage output.Figure 7
Level restoration.On gate level, every additional component introduces its own parasitic capacitances causing additional power overhead that must be justified. Therefore, the number of transistors must be kept as low as possible. At least two transistors are needed for full-swing delay implementation. Possible topologies are shown in Figure8. There are four combinations of PMOS and NMOS delay transistors in triode mode (PtNt), level restoration transistors without delay transistors (PfNf), and PMOS or NMOS delay transistor with appropriate level restoration transistor (PtNf and PfNt). Controlling level restoration signals (p
c, n
c) is taken from the next stage output. Using feedback for level restoration is a logical choice, since level restoration is required immediately after the next stage switches state.Figure 8
Two transistor full-swing delay implementations.


## 7. Noninverting Delay Cell

The dual-ramp (i.e., BBM) CMOS inverter is well suited for building low-power low-precision delay elements. It conveniently combines the delay with short-circuit current elimination. Generally, the delay circuit can be constructed as cascade of several BBM stages comprising elements depicted in Figure1. In the simplest case the circuit can be reduced to the interfacing elements depicted in Figures 1(a) and 1(c). This results in a 6-transistor noninverting delay cell when full-swing delay topologies from Figure 8 are used.To verify the proposed principle, all four variations of the simple dual-ramp delay cell were compared to a standard serial connection of two CMOS inverters. All five delay circuits were sized for smallest possible charge consumption at a required delay. Digital cell sizing, including delay, is highly dependent on a required fan-in and fan-out properties. To eliminate this dependence, standard input and output unit inverters were added, defining equal fan-in and fan-out properties (Figure9) for delay circuits. Both inverters contribute to the delay and are considered as part of the cell. The final sizing (i.e., optimization result) of a delay circuit is of course tailored to the selected pair of input and output standard unit inverters. Standard CMOS and dual-ramp (BBM) delay cells with input and output buffers are shown in Figure 9.Standard (a) and proposed (b) simple dual-ramp (i.e., BBM) delay cell.
(a)
(b)


## 8. Results

Sizing cells from Figure9 to a required delay is an eight- or a twelve-dimensional optimization problem. Finding the global minimum is not a trivial task, especially if there are plenty of local minima. Therefore, every optimization run was repeated several times in various parts of the parameter space until the global minimum was confirmed.A parallel version of SADE [12] global optimization method was used. The optimization procedure ran in parallel on a cluster of 100 computing nodes driven by the PyOPUS [13] library. 25 Intel Core i5 2.66 GHz processors (4 nodes per processor) were used. Circuit simulations were performed by the Synopsys HSPICE circuit simulator with the TSMC 0.18
μ
m
/
1.8
V process parameters.Beside transistor sizing, the delay and power dissipation also depend on the circuit layout. Automatic layout procedure and extracting parasitic node capacitances should be done in every iteration before the simulation. The authors could not include the layout and extraction steps into the optimization loop due to not small, but, nevertheless, limited computer power. Therefore, the node capacitances due to layout were not taken into account. To approximate the real conditions, transistor parasitics due to the connection geometry were included. Layout rules (A
d
=
A
s
=
0.8
μ
m
×
w, P
d
=
P
s
=
1.5
μ
m
+
w) were applied. But, in spite of described imperfection, the obtained results for standard and proposed delay cell still indicate the capabilities of the two topologies.Straightforward sizing of the cells produces inappropriate results. Optimizer finds a sizing with small consumption and a perfect delay match. These are in fact degenerated circuits whose operation depends on poorly defined parasitics causing very long internal transients (Figure5). To obtain usable solutions based on well-defined manufacturing process parameters, such as gate capacitance and intrinsic transconductance, additional implicit constraints were required.The first set of safeguarding constraints avoids extreme over- and undershoots thus preventing circuit operation based on parasitic capacitances (e.g., Miller capacitance). Miller capacitances of large transistors are the main source of the delay time. In that unwanted case, the delay results from charging and discharging the parasitic capacitances.The second set of constraints ensures that the steady state is reached aftert
max
⁡ (Figure 5). Very long internal transients with smaller charge consumption are otherwise superior from the optimization point of view.The third set represents additional requirements needed to obtain noise resistant circuits. Noise margins are obtained by requiring stable steady state node voltages duringp- and n-substrate potential disturbances.Figure10 illustrates the results summarized in Table 1. Each topology was sized targeting delays from 100 ps to 5 ns. Charge consumption growth with delay becomes approximately linear for delays above 1 ns as (9) and (16) predict. The topology with PMOS transistor in triode mode and NMOS level restoration transistor (PtNf) turns out as the most efficient. In comparison with the standard topology, charge savings are slightly higher than 40%.Table 1
Charge consumption results for the standard (std.) and the BBM delay cells depicted in Figure9 measured for one rising and one falling slope. The columns denoted by the percent sign represent the percentage of the standard delay cell’s consumption.
T
p [ns]
std. [fAs]
PtNt [fAs]
[%]
PtNf [fAs]
[%]
PfNt [fAs]
[
%
]
PfNf [fAs]
[
%
]
0.1
34*
45*
—
78*
—
44*
—
97*
—
0.2
26
30
115
87*
—
30
115
62*
—
0.35
32
34
106
34
106
35
109
42
131
0.5
39
38
97
35
90
39
100
38
97
0.75
65
45
69
42
65
46
71
46
71
1.0
77
58
75
49
64
58
75
55
71
2.0
113
86
76
67
59
86
76
93
82
3.5
153
118
77
89
58
118
77
130
85
5.0
186
142
76
108
58
143
77
177
95
*Delay target was not achieved.Figure 10
Dependence of charge consumption on the delay.Elimination of static consumption can be observed in the third stage. It is the only stage actually driven by time-skewed signals. Drain currents forT
p
=
750 ps sizing are depicted in Figure 11. Similar current transients can be observed with other BBM topologies and delays. The large direct-path current in the standard topology (shadowed) is almost completely eliminated in the PtNf topology. The optimization procedure obtained the required delay with large channel lengths in the second stage. This means that the bulk of the delay is caused by the third stage gate capacitances.Figure 11
Third stage drain currents obtained with SPICE simulation forT
p
=
750 ps (sizing: std. w
P
1
=
220
nm, l
P
1
=
370
nm, w
N
1
=
220
nm, l
N
1
=
880
nm, w
P
2
=
880
nm, l
P
2
=
730
nm, w
N
2
=
1.05
μ
m, l
N
2
=
1.32
μ
m; PtNf w
P
1
=
220
nm, l
P
1
=
740
nm, w
N
1
=
390
nm, l
N
1
=
180
nm, w
P
t
=
220
nm, l
P
t
=
350
nm, w
N
f
=
220
nm, l
N
f
=
950
nm, w
P
2
=
220
nm, l
P
2
=
180
nm, w
N
2
=
220
nm, and l
N
2
=
220
nm).


## 9. Applications

Dual-ramp BBM delay cells can be used for constructing low-power delay lines. All that needs to be done is to replace standard delay elements with proposed ones, as shown in Figure12. The number of stages in one delay element T
p can vary depending on the required delay.Figure 12
Delay line implemented with BBM delay dells.The BBM inverter with level restoration can be used as a key element in a leading-edge pulse generator (Figure13). Pulse generators are frequently used for generating precharge or data-strobe pulses in dynamic logic and flip-flops. Since, in this case, the delay is needed only for the low-to-high transition, the circuit can be simplified. A single BBM stage provides enough delay for the AND-type edge detection. The width of the generated pulse is defined by the AND gate delay and the parasitic capacitance of node p combined with the resistance of the discharging NMOS feedback transistor. The inherent delay of the output pulse dictated by the AND gate provides enough time to reset node p through the NMOS feedback transistor. The voltage level of node n is restored through the precharging PMOS transistor. In this context, the BBM inverter acts as a feedback switch with limited impact on the delay.Figure 13
BBM based leading-edge pulse generator.The BBM topology in Figure13 was compared to standard leading-edge pulse generator with various delay line lengths. Low-power cells (inverter and NAND gate) from industry standard library were used. Input and output buffers were added to equalize fan-in and fan-out properties. Manufacturing process layout rules defining transistor geometry were applied during the sizing procedure (i.e., optimization). And of course some previously described constraints were essential to obtain sensible results.The results are summarized in Table2. The pulse width, the total charge consumption, and the delay line charge consumption of the standard leading-edge pulse generator with 3, 5, 7, 9, and 11 cascaded inverters in the delay were measured first. Then, the BBM topology was sized to the individual pulse widths. The charge consumptions of the equivalent BBM based leading-edge pulse generators were obtained. The simplicity of the delay implementation saves up to 50% of the total switching energy compared to the standard realization. The advantage of the BBM based circuit is clearly presented when the charge consumption of the delay line is measured separately. For standard implementation, the consumption linearly increases with the number of inverters in the delay. On the other hand, the consumption of the BBM inverter is almost constant. This is due to the constant number of transistors. A slight increase can be observed for longer pulse widths, which is caused by higher parasitic capacitances of larger transistors required in that case. Note that the consumption of the inverter supplying the feedback is included only in the total charge consumption measurement.Table 2
Charge consumption results for the standard and the BBM based leading-edge pulse generator depicted in Figure13 measured for one input impulse. The columns denoted by the percent sign represent the percentage of the standard realization’s consumption.
Standard
BBM based
Number of inv.
Width [ps]
Total [fAs]
Delay [fAs]
Total [fAs]
[%]
Delay [fAs]
[%]
3
200
171
56
143*
—
17*
—
5
330
210
93
142
68
16
17
7
450
247
130
147
60
16
12
9
570
284
167
153
54
16
10
11
690
321
204
161
50
17
8
*Pulse width target was not achieved.Two potential topology modifications not requiring the feedback are given in Figures14 and 15. The AND gate delay therefore does not affect the width of the generated pulse. The price for removing the feedback is an increased number of transistors, which causes higher charge consumption compared to the feedback implementation from Figure 13.Figure 14
BBM delay cell with biased NMOS current discharge.Figure 15
Dynamically biased delay cell.The delay is defined more precisely if the discharge current is controlled by a biased MOS transistor [14] (Figure 14). The leading-edge delay of the input signal is defined by the time needed for discharging the parasitic capacitance of node p through the NMOS feedback transistor M1. Transistor M4 presets node n before the delay transient, providing the inverted input signal. The latter is combined with the delayed output signal for switching the current through M2/M3 when the biasing voltage on the M1 gate is needed [15].The DC power consumption of the biasing circuit can be reduced by dynamic biasing presented in Figure15. When the input signal is low, the circuit prepares the initial conditions for the delay transient: the voltage of node d is clamped by M2 to V
T
N and node s is precharged through M3 to V
D
D. In the active phase, when input goes to high, node d is charged by the parasitic capacitance of node s through the transmission gate M4/M5, thus raising the M1 gate voltage to the desired level for the delay transient. The effective voltage at the M1 gate is given by V
d
=
(
V
D
D
C
s
+
V
T
N
C
d
)
/
(
C
s
+
C
d
), where C
s and C
d are the parasitic capacitances of nodes s and d, respectively. Parasitic capacitances can be trimmed by adding diffusion areas to the relevant transistors or using gate oxide capacitors. The transistors in the switching network (M2⋯M6) are minimum sized.


## 10. Conclusion

A modified static CMOS inverter has been presented which reduces direct-path current in circuits, where the delay is a required part of the circuit’s functionality. The proposed BBM inverter is well-suited for building low-power low-precision delay elements due to its ability to combine delay and direct-path current elimination in one single stage. The suppression is based on the serially connected delay element in the inverter output thus providing time-skewed output signals. Two output signals provide additional capabilities for compact functional solutions. The principle of operation has been verified by performing delay cell optimizations for various delay element implementations. With the exception of very short delays, the proposed BBM inverter structure improves the power budget compared to the standard cascaded inverter transport delay implementation. Besides the delay lines, variations of the proposed topology can be used in other slow transition circuits. Edge-detector circuit featuring BBM topology has been presented.



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*Source: 349131-2014-11-26.xml*