# Photovoltaic Energy Harvester with Power Management System

Authors: M. Ferri; D. Pinna; E. Dallago; P. Malcovati
Journal: Journal of Sensors
 (2010)

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## Abstract

We present a photovoltaic energy harvester, realized in 0.35-μm CMOS technology. The proposed system collects light energy from the environment, by means of 2-mm2 on-chip integrated microsolar cells, and accumulates it in an external capacitor. While the capacitor is charging, the load is disconnected. When the energy in the external capacitor is enough to operate the load for a predefined time slot, the load is connected to the capacitor by a power management circuit. The choice of the value of the capacitance determines the operating time slot for the load. The proposed solution is suitable for discrete-time-regime applications, such as sensor network nodes, or, in general, systems that require power supply periodically for short time slots. The power management circuit includes a charge pump, a comparator, a level shifter, and a linear voltage regulator. The whole system has been extensively simulated, integrated, and experimentally characterized.


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## Body

## 1. Introduction

Modern ultralow power integrated circuits have reached such a high level of complexity, that for many applications traditional batteries are no longer sufficient, since they cannot guarantee a long enough life time [1]. These applications, such as sensor nodes or lab-on-chip, often include very stressing computational algorithms and wireless communication systems. By harvesting energy from the environment, for example in the form of light, vibrations, or thermal gradients, such systems could work for nearly infinite time without the need of replacing batteries. Energy harvesting not only allows the improvement of the lifetime of the device and the reduction of its weight, but it also enables entirely new applications, that are otherwise not feasible, given the lifetime and size of the batteries. Despite the technology scaling, indeed, electrochemical batteries show a slow growth in terms of energy density and represent a bottleneck for weight and volume [2–4].Light can be considered the most copious energy source in many environments. Photovoltaic energy scavengers can reach conversion efficiencies ranging from 20%, in standard monocrystalline silicon planar technology, to almost 50% [5, 6], in multimaterial planar wafers, considering an illumination of 1000 W/m2 from the sun. Moreover the photo-electric phenomena [7] in doped silicon allows retrieving the highest amount of power with respect to any other types of harvesters. Moreover, photovoltaic cells are intrinsically compatible with standard integrated circuit technologies [8], thus making them particularly suitable for implementing energy-autonomous microsystems.In this paper we present a photovoltaic energy harvesting power supply system for discrete-time-regime applications, realized in 0.35-μm CMOS technology. In particular, in the proposed system, a couple of integrated miniaturized solar cells are used as energy source and a power management circuit has been realized to handle the collected energy.The block diagram of the proposed system is shown in  Figure1. A first solar cell provides the power supply to an oscillator and to eight parallel Dickson charge pumps. In order to simplify the schematic, we reported only one charge pump. The storage capacitor CS is external, thus allowing us to choose the capacitance value, according to the operating time slot required by each application. The voltage across CS (VS) is monitored by a comparator followed by a level shifter. In particular, VS is divided and compared with a fixed reference voltage, generated by the second (auxiliary) solar cell. When CS is fully charged, the level shifter turns on the p-MOS switch MS, thus connecting the load, and the capacitor delivers the accumulated energy. In order to provide to the load a stabilized power supply, we realized on-chip also a linear voltage regulator (LDO). The LDO is connected between MS and the load and, therefore, it is supplied only when the load is connected. In  Section 2 we present the characterization of the photovoltaic energy harvesting element, while in  Section 3 we describe the oscillator and the charge pump used to elevate the solar cell voltage to a usable value.  Sections 4 and 5 discuss the power management system and the LDO, respectively. Finally, in  Section 6 the simulation and experimental results are presented.Figure 1
Block diagram of the proposed system.


## 2. Photovoltaic Energy Harvesting Elements

The photovoltaic energy harvesting elements, implemented on-chip, are based onp-n junctions.  Figure 2 shows the cross-section and the equivalent circuit of the integrated microsolar cell [9], whose area is 1 mm2. The cell is realized with an n-well enclosing a p-diffusion, implemented with a particular geometry [10, 11], in order to optimize the active area density. This is useful to improve the photo-generated current per unit area. In  Figure 2 it is possible to see also the equivalent circuit of the solar cell. Since each solar cell must be used as energy harvesting source for an integrated microsystem, realized on the same silicon substrate, it is not possible to exploit the photo-generated power of the deeper junction, since this would imply direct biasing of the junction between n-well and substrate, leading to a negative voltage at the n-well terminal with respect to the substrate. Furthermore, different cells cannot be connected in series, because they share the same substrate.  Figure 3 shows the power curve of the realized cell, obtained with 300-W/m2 illumination. As the substrate must be short-circuited with the n-well, the efficiency of the cell is, unfortunately, reduced by the recombination effect in the base of the parasitic pnp vertical transistor.Figure 2
Cross-detection and equivalent circuit of the integrated photovoltaic energy harvesting element.Figure 3
Output power curves of the integrated microsolar cell.In order to perform reliable simulations of the whole system, we developed the equivalent electrical model of the microsolar cell, shown in  Figure4, where Iph=12.28 μA, AD=100 μm2, PD=40 μm, Rsh=40 kΩ, and Rs=2.27 kΩ.Figure 4
Equivalent circuit model of the integrated microsolar cell.


## 3. Ring Oscillator and Charge Pump

The ring oscillator and the charge pump are shown in  Figure5. They represent the front-end block of the power management circuit. As the solar cell photo-generated voltage cannot exceed 500 mV, in order to obtain at least 4 V across the storage capacitor, a Dickson charge pump has been implemented. The circuit requires two nonoverlapping clock phases, Φ and Φ¯, with amplitude equal to the voltage produced by the microsolar cell Vph. The charge pump operates by moving charges along the diode chain, charging the capacitors to increasing voltages. The charge pump has been designed to obtain a voltage of about 5 V, starting from Vph≅500 mV, thus requiring 12 stages. A three stage ring oscillator provides the clock phases for the charge pump with a frequency equal to 29.5 kHz, which corresponds to the best trade-off between the time required to charge CS and the charge transfer rate. The performance of the system is limited by the supply voltage, which is equal to the open-circuit voltage Vph of the integrated microsolar cell, that forces all transistors to work in the subthreshold region. This circuit provides a very low current flow through each transistor, introducing an efficiency loss in terms of charge transfer and, hence, in terms of charging time. This efficiency loss, however, does not compromise the correct operation of the system, but just increases the charging time. In order to provide a constant voltage of 3.3 V to the load with a significant current for an established time slot, a storage capacitor is necessary. Therefore, the proposed system is only suitable for loads operated in discrete-time regime, such as sensor network nodes [12].Figure 5
Schematic of the ring oscillator and of the charge pump.


## 4. Power Management and Monitoring Circuit

The voltage across the storage capacitorCS (VS) is monitored with an hysteresis comparator, to verify the charging status. While the capacitor is charging and, hence, VS is lower than the threshold voltage VL, the load is disconnected. When VS is higher than the threshold voltage VH, the load is connected (VL<VH), until the capacitor is discharged. The schematic of the hysteresis comparator is shown in  Figure 6.Figure 6
Schematic of the hysteresis comparator.Hysteresis is required to achieve a rising threshold (VH) different from the falling threshold (VL). The hysteresis value of this circuit is proportional to the ratio α=βM4/βM3=βM5/βM6 between the geometries of transistors M4, M3, and M5, M6. Assume that initially the input voltage Vin is much lower than the reference voltage Vref. In this case, all the current of M12 flows through M2 and M5 (IM2=IM5=IM12), while M1, M3, and M4 are off (IM1=IM3=IM4=0) and, consequently, the output voltage V is high. Transistor M6 is also on, but no current is flowing in it (IM6=0). Initially, when Vin increases, nothing happens, until Vin≅Vref. At this point, some current starts to flow into M1 and M6, while the current in M2 starts to decrease. In these conditions, we can write (1)IM1=IM6=αIM5,IM1+IM2=IM12,
and, hence, (2)IM2+αrIM5=IM12.
If Vin increases further, M1 demands for more current, which can only come from M6. Since the current of M5 is decreasing and IM6=αIM5, at a certain point IM5 cannot any longer satisfy (2). Therefore, M4 turns on, thus providing the current M1 is asking for. At this point, the output voltage of the comparator becomes low. The last value of Vin for which (2) is satisfied represents the threshold voltage VH (VH>Vref). The value of VH is controlled by parameter α: the larger is α, the longer (2) is satisfied, and the higher is VH with respect to Vref. The comparator shows the same behavior symmetrically when Vin decreases, leading to a threshold voltage VL<Vref, which also depends on α.In order to drive properly the switchMS, which connects and disconnects the load, a voltage level shifter has been implemented at the output of the comparator. When the voltage across the storage capacitor (VS) reaches the desired value, the level shifter has to turn on MS, while, during the charging phase (VS lower than the desired value), MS has to be off, in order to disconnect the load and avoid the power consumption. The total power consumption of the power management system is about 500 pW, thus requiring, in principle, a small area for the auxiliary solar cell. The level shifter power consumption is negligible in steady state.


## 5. Voltage Regulator

In order to provide a fixed 3.3-V power supply to the actual load, a voltage regulator has been implemented. It consists of a bandgap circuit and an LDO circuit. The voltage regulator is supplied only when the voltage across the storage capacitor has reached the proper value.  Figure7 shows the schematic of the voltage regulator. The total current consumption of the circuit is less than 2 μA.Figure 7
Schematic of the voltage regulator.The bandgap circuit provides a voltage (Vbg), stable over temperature, as reference input of the LDO. It operates compensating the negative temperature coefficient of a p-n-junction voltage Vbe, with the positive temperature coefficient of the thermal voltage VT. The output voltage of the circuit is, hence, (3)Vbg=Vbe+mVT,
where m≅25. With the topology used, m is given by (4)m=R2R1ln⁡⁡[(WM1/LM1)(WM2/LM2)AQ2AQ1].
Even if the supply voltage follows the discharge curve of the storage capacitor, Vbg remains constant.The LDO provides a stable 3.3-V supply voltage with an input voltage ranging from 3.3 V to 4.8 V, allowing the actual load to operate properly. In particular, the output voltage is given by(5)Vout=VbgR4+R5R4.
Simulation results demonstrate that Vout achieves a maximum error of 0.3% over the whole input voltage range. In order to reduce the power dissipation, R4 and R5 are in the MΩ range. The total current consumption of the LDO is about 1 μA.


## 6. Simulation and Experimental Results

The storage capacitor is an external component, and, hence, its value can be chosen on the basis of the actual load power consumption. In particular, the charge transfer rate of the charge pump in the output voltage ranges from 3.8 V to 4.3 V is less than 10 nA. The charge pump efficiency is quite low, but this is not particularly important, because the system is able to store energy and provide it to the actual load only when it is enough to allow proper operation for an established time slot.  Figure8 shows a simulation of the storage capacitor voltage over a time slot of 7 s, obtained with a capacitance value of 10 nF.Figure 8
Simulation of the voltage across the storage capacitor withCS=10 nF.Figure9 shows the microphotograph of the chip. The chip area is 2.32mm×2.54mm. The power management circuit is shielded from light with a layer of metal, in order to avoid unwanted generation of current in the p-n junctions of the circuit itself. Therefore, in  Figure 9 we also reported the layout of the chip.Figure 9
Microphotograph and layout of the realized chip.Figure10 shows the measured voltage across the storage capacitor, acquired over a time slot of 15 s, obtained for different values of CS (47 nF, 100 nF, and 147 nF). The system is illuminated with a light source, delivering about 300 W/m2 and the load is a 10-MΩ resistor (1-μW power at 3.3 V). The maximum value of the voltage VS is adjustable by changing the value of the threshold voltage of the hysteresis comparator. The upper limit of the achievable voltage is a trade-off between the charge-pump transfer rate, the leakage current of the external capacitor, and the current that flows in the resistive string that provides the reference voltage to the comparator. The measurement results show that the system is actually more efficient than expected. Indeed, the time required to charge CS in the measurement with CS=47 nF (Figure 10) should be about five times larger than in the simulation with CS=10 nF (Figure 8), while we obtain almost the same value in the two cases. Actually, in the measurement the voltage drop on the storage capacitor when the load is connected is larger than in simulation, since the comparator threshold voltage in the measurement is set to a different value than in the simulation.Figure 10
Measurement of the voltage across the storage capacitor with different values ofCS (47 nF, 100 nF, and 147 nF).Figure11 shows the measured current through the 10-MΩ resistive load over a time slot of 30 s for different values of CS (47 nF, 100 nF, and 147 nF). The different peak values of the curves are due to the measurement setup sampling frequency. Depending on the capacitance value, the energy available for the load and, hence, the operation duty-cycle changes. With CS=147 nF, for example, the system provides the same current value as with CS=47 nF, but for a longer time slot.Figure 11
Measurement of the current through the 10-MΩ resistive load with different values ofCS (47 nF, 100 nF, and 147 nF).


## 7. Conclusions

In this paper we presented an integrated photovoltaic energy harvester, including two 1-mm2 microsolar cells and a power management circuit, consisting of a charge pump, a comparator, a level shifter, and a linear voltage regulator. The system accumulates energy in an external capacitor and delivers it to the load when the voltage across the capacitor is sufficiently high. The choice of the value of the capacitance determines the operating time slot of the load. The proposed solution is suitable for discrete-time-regime applications. The experimental results, obtained from a prototype of the system, realized with a 0.35-μm CMOS technology, demonstrate the feasibility of a fully integrated photovoltaic energy harvester.



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*Source: 349389-2010-12-01.xml*