# A Novel Power Electronic Inverter Circuit for Transformerless Photovoltaic Systems

Authors: Cao Hai-Yan
Journal: Active and Passive Electronic Components
 (2014)

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## Abstract

Capacitive leakage current is one of the most important issues for transformerless photovoltaic systems. In order to deal with the capacitive leakage current, a new power electronic inverter circuit is proposed in this paper. The inverter circuit consists of six switches and operates with constant common mode voltage. Theoretical analysis is conducted to clarify the circuit operation principle and the common mode characteristic. The performance evaluation test is carried out, and test results demonstrate that the capacitive leakage current can be significantly minimized with the proposed power electronic inverter circuit.


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## Body

## 1. Introduction

Photovoltaic (PV) power systems are very attractive and widely used in recent years. In order to integrate the PV systems into grid, a power electronic component should be required to convert DC energy source generated by PV arrays to AC component [1], which is fed into grid. In general, a transformer is installed between PV arrays and grid for galvanic isolation. The transformer is heavy with large volume, along with the copper and iron losses during transformer operation [2, 3]. Therefore, the transformerless PV system is popular and received more and more attention [4–12], due to its low cost, small size, and high efficiency. However, a technical challenge arises for transformerless PV systems. More specifically, the capacitive leakage current is generated between photovoltaic modules and the ground [13]. In practice, this capacitive leakage current is very difficult to handle, because the capacitance between photovoltaic modules and ground is usually highly unpredictable, and it varies significantly with temperature or humidity [14]. The presence of leakage currents is very harmful, since they could put the life of a photovoltaic module installer at risk if he touches the photovoltaic module [15]. Additionally, they will bring high-frequency harmonics, which may lead to problems with electromagnetic compatibility [16]. Therefore, it is important to deal with the capacitive leakage current problem in the transformerless PV system.The objective of this paper is to present a novel power electronic inverter circuit for transformerless photovoltaic system. The capacitive leakage current can be minimized with the proposed inverter circuit.


## 2. Circuit Description

The schematic diagram of the proposed power electronic inverter circuit is illustrated in Figure1. It should be noted that the parasitic capacitance between ground and positive terminal of dc bus point is one of the factors for the system stray capacitance. In this case, considering the entire stray capacitances of C
pv, the parasitic capacitance between ground and positive terminal of the inverter dc bus point will be C
pv
/
2 and so is the capacitance of ground-negative terminal, as shown in Figure 1. The capacitance value depends on the PV panel frame structure, weather conditions, humidity, and so on. Therefore, it is usually highly unpredictable. In order to clarify the capacitive leakage current minimization mechanism, the system’s common mode model is built, as shown in Figure 2, where U
cm is the common mode voltage and U
dm is defined as follows:
(1)
U
cm
=
U
an
+
U
bn
2
,
(2)
U
dm
=
U
a
b
(
L
a
-
L
b
)
2
(
L
a
+
L
b
)
,
(3)
L
a
b
=
L
a
L
b
L
a
+
L
b
.Figure 1
Schematic diagram of proposed power electronic inverter circuit.Figure 2
System’s common mode model [17].In practice, the filter inductorsL
a and L
b are designed with the equal value; that is, L
a
=
L
b. So, the differential mode voltage U
a
b does not contribute to the capacitive leakage current, as shown in (2) and Figure 2.On the other hand, if the common mode voltageU
cm is time varying, the capacitive leakage current will arise and flow in the loop, as shown in Figure 2.In order to deal with the capacitive leakage current, it is of great importance that the common mode voltageU
cm in Figure 2 should be kept constant. The following will present this objective achieved by the proposed power electronic inverter circuit.The proposed inverter circuit operates in four modes, as shown in Figure4 and Table 1.Table 1
Operation modes and voltages.
S
1
S
2
S
3
S
4
S
5
S
6
U
an
U
bn
U
cm
Mode 1
1
0
0
1
0
1
V
d
0
V
d/2
Mode 2
0
0
0
0
0
1
V
d/2
V
d/2
V
d/2
Mode 3
0
1
1
0
1
0
0
V
d
V
d/2
Mode 4
0
1
0
0
0
0
V
d/2
V
d/2
V
d/2In Mode 1, the switchesS
1, S
4, and S
6 are turned on, and other switches are turned off. The differential mode voltage U
a
b is V
d, while the common mode voltage can be expressed as
(4)
U
cm
=
1
2
(
U
an
+
U
bn
)
=
1
2
(
V
d
+
0
)
=
V
d
2
.In Mode 2, only the switchS
6 is turned on, and other switches are turned off. The current flows through S
6 and diode of S
2. In this case, the differential mode voltage U
a
b is 0, while the common mode voltage remains unchanged as
(5)
U
cm
=
1
2
(
U
an
+
U
bn
)
=
1
2
(
V
d
2
+
V
d
2
)
=
V
d
2
.In Mode 3, the switchesS
2, S
3, and S
5 are turned on, and other switches are turned off. The differential mode voltage U
a
b is -
V
d, while the common mode voltage can be expressed as
(6)
U
cm
=
1
2
(
U
an
+
U
bn
)
=
1
2
(
0
+
V
d
)
=
V
d
2
.In Mode 4, only the switchS
2 is turned on, and other switches are turned off. The current flows through S
2 and diode of S
6. In this case, the differential mode voltage U
a
b is 0, while the common mode voltage U
cm remains unchanged as
(7)
U
cm
=
1
2
(
U
an
+
U
bn
)
=
1
2
(
V
d
2
+
V
d
2
)
=
V
d
2
.In summary, the above analysis reveals that the common mode voltage can be kept constant asV
d
/
2 all the time. Therefore, the capacitive leakage current can be significantly minimized, according to theoretical analysis of Figure 2. The following will present the test results.


## 3. Performance Evaluation

In order to verify the effectiveness of the proposed power electronic inverter circuit, the inverter circuit is designed in MATLAB/Simulink. The circuit components and parameters are listed as follows: system power is 3 kW, dc bus voltageV
d is 400 V, grid voltage V
g is 220 Vac, grid frequency is 50 Hz, inverter circuit switching frequency is 10 kHz, circuit filter inductor L
a
=
L
b
=
3 mH, and parasitic capacitor C
PV
=
100 nF; see Figure 3.Figure 3
Switching state of the proposed inverter circuit.Operation modes of the proposed inverter.
(a)
Mode 1
(b)
Mode 2
(c)
Mode 3
(d)
Mode 4Figure5(a) shows the test waveform of the switch states; it can be observed that, at any given time, only two switches operate in high-frequency mode and the other four switches operate in low-frequency mode, so the high efficiency can be achieved. On the other hand, the inverter output voltage waveform is shown in Figure 5(b), where three-level output voltage is achieved. It is beneficial to the grid current ripple reduction. Figure 5(c) shows the grid current waveform and its spectrum analysis. It can be seen that the grid current is sinusoidal with the total harmonic distortion of 1.9%, which is well below 5% specified in IEEE Std. 929-2000 [18].Test results.
(a)
Switch states (from bottom to top:S
6, S
2, S
4, S
3, S
5, and S
1)
(b)
Inverter output voltageU
a
b
(c)
Grid current and spectrum
(d)
Capacitive leakage current and spectrumFigure5(d) shows the capacitive leakage current waveform and its spectrum analysis. It can be seen that the leakage current is well below 300 mA specified in VDE 0126-1-1, thanks to the proposed power electronic inverter.


## 4. Conclusion

This paper has presented a new power electronic inverter circuit. Its unique feature lies in that the proposed circuit can keep the system’s common mode voltage constant all the time, and thus the capacitive leakage current can be significantly minimized, which complies with the international standard IEEE Std. 929-2000 and VDE 0126-1-1. Therefore, it is attractive to the transformerless photovoltaic system applications. It should be noted that other different inverter circuits are also interesting and can be used for the transformerless photovoltaic system applications; please refer to [19, 20] for further reading.



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*Source: 329043-2014-05-26.xml*