# Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

Authors: Muhammad Ovais Akhter; Najam Muhammad Amin
Journal: Mathematical Problems in Engineering
 (2021)

---

## Abstract

This research proposed the design and calculations of ultra-low power (ULP) Doherty power amplifier (PA) using 65 nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. The operation has been performed in RF-nMOS subthreshold or triode region to achieve ultra-low power (ULP) and to improve the linearity of the overall power amplifier (PA). The novel design consumes a DC power of 2.1 mW, power-added efficiency (PAE) of 29.8%, operating at 2.4 GHz band, and output referred 1 dB compression point at 4.1dBm. The simulation results show a very good capability of drive current, high gain, and very low input and output insertion losses.


---

## Body

## 1. Introduction

We are living in a modern world where everyone has lesser time to recharge their handy devices along with usage of a larger number of applications including healthcare, smart offices, and homes [1]. Demand for long-lasting battery life is one of the major requirements these days. When we talk about transmitter components, the power amplifier is considered as the power-hungry block [2] and is the most challenging building block in RF transceiver chip [3]. While designing a power amplifier, efficiency and linearity become a trade-off with each other [4]. Achieving both at the same time along with a low power becomes a challenge. This research simulates the idea of designing an ultra-low power (ULP) power amplifier with 65 nm CMOS technology. The calculations have been shown in a very simple manner, making it easier to understand for a designer. Numerous methods are available in past research studies where equivalent lumped parameters have been designed using bipolar devices, but CMOS designs are still preferred as these are relatively cheap as compared to bipolar transistors [5–7].The Doherty power amplifier consists of two amplifiers: the carrier or main amplifier and the peaking amplifier [8]. These are usually prematched by a free scale. The two amplifiers operate at 90° out of phase. This is achieved by 90-degree output splitter such as a hybrid splitter or Wilkinson power divider [9]. Of course, the two signals have to be combined again after they are amplified. This is done by use of 90-degree transmission line at output of main amplifier [10]. The main amplifier is biased in class B (theoretically), but in practice we choose class AB to bias. The peaking amplifier is biased in class C [11]. When the signal level of the Doherty amplifier is slow (backoff mode), the peaking amplifier is off and only the main amplifier is operating, which means that the biasing point of class C is further slightly lower than the pinch-off point. This is the secret sauce to improve the efficiency of the Doherty amplifier. Another important component of the Doherty amplifier is the Doherty combiner or the power combiner circuit [12], which is implemented by another 90-degree transmission line which usually has a characteristic impedance of 50 ohms divided by a square root of 2. The function of the Doherty combiner is to transfer the impedance of 50 ohms load impedance to 25 ohms impedance at the Doherty combining node, which then connects the Doherty node to the main amplifier, which has an impedance of 100 ohms. The impedance level stays constant as long as the amplifier stays off. Another important thing is that the peaking amplifier represents a very high impedance to its combining nodes. If you consider that the signal level increases at the input of the main amplifier, the peaking amplifier starts to produce power, but on the other hand, it also increases the impedance at the output of the main amplifier, which is known as effect of load modulation [13].


## 2. Proposed Doherty Power Amplifier Model Using 65 nm TSMCTM CMOS Technology

The four sections of the power amplifier are separated with red dotted lines in Figure1. These include the power divider circuit, the main amplifier, the peaking amplifier, and power combiner circuit.Figure 1
Schematic of the Doherty power amplifier using 65 nm CMOS technology.


### 2.1. Wilkinson Power Divider Equivalent Model

Since a single band with power divider has been used, a perfect impedance matching is required. Both the main amplifier and the peaking amplifier are supposed to loadZo. Various designs have been proposed earlier where both equal and unequal power divider techniques were used to calculate the input impedance of transmission lines. Both symmetric and asymmetric lumped element power divider techniques were observed in [14–16]. Since the equal power divider model has been implemented for both main and peaking amplifiers. If we match the ports of Wilkinson power divider, it becomes a lossless model [17]. Using the same approach, an equivalent circuit is designed using this technology. The 90-degree phase shift at one of the ports is accomplished by p-network. Previously, this work was done on BiCMOS technology [18]. Power divider in Figure 1 shows an equivalent lumped circuit as a p-network to achieve 90-degree phase.SettingZo=50Ω for perfect matching, the distributed realization can be seen with parameters C, L, and R and a tuned frequency of 2.4 GHz as R=2Zo=100Ω, L=502/2π2.4GHz=4.689nH, and C=1/2π5022.4GHz=937.8fF.Figure2 shows a very low S11=−87.8dB, S22=S33=−96.1dB shows an almost perfect match, and S12=−3.01dB is an equal split of power divider. In addition, the following is valid for the insertion loss of nearly to ideal value of −3dB.(1)Insertion loss=10log10input poweroutput power=10log1012.Figure 2
Input return loss (S11), insertion loss (S12), and output return loss (S22) for power divider circuit.For our case, where we need to perfectly match at50Ω, the transmission line is λ/4=2Zo=2100=70.71Ω. Since this is a narrow band circuit, it avoided more cascading with factor <1 as seen in the traditional method [14]. The impedance of two ports can be calculated by first applying the transmission line theory (theoretical analysis), but using equal power division. As the admittance of transmission lines is equal, the overall admittance of Z1 and Z2 can be rewritten as Y1 and Y2, respectively [15]. It gives(2)Y1=Y2=YAcotθY0+YAtanθYAcotθ+jY0.To match the input, the condition will beY0=Y2+Y3. Under the condition of both input matching, the new condition becomesY1+Y2=Y0. Remember Z0 as 50 Ω, which is the port characteristic impedance for the calculation of input impedance. Reflection coefficient is maximum at 2.4 GHz center frequency. By using the value of S11 in Figure 3 and θ=π/2, we can find the value of Γ [19], as S11=20logΓ or Zin=Z01+Γ/1−Γ.Figure 3
(a) Impedance matching through the Smith chart for power combiner lumped parameters and (b) power divider lumped parameters. (c) Wilkinson power divider and (d) power combiner using equivalent RLC model.
(a)(b)(c)(d)As an alternative and to make it precise, we will observe the impedances on the Smith chart. With an operational frequency of 2.4 GHz, a frequency span of 0 MHz, and a characteristic impedance of 50 Ω, the measured results can be observed in Figure3 which are perfectly matched.Due to symmetry,S11=S22, S21=S12, and S13=S31. Figure 4 shows the parameters achieved using the tuned scale, which are perfectly matched.Figure 4
Small signal model for (a) main power amplifier and (b) peaking power amplifier operating in subthreshold region.
(a)(b)


## 2.1. Wilkinson Power Divider Equivalent Model

Since a single band with power divider has been used, a perfect impedance matching is required. Both the main amplifier and the peaking amplifier are supposed to loadZo. Various designs have been proposed earlier where both equal and unequal power divider techniques were used to calculate the input impedance of transmission lines. Both symmetric and asymmetric lumped element power divider techniques were observed in [14–16]. Since the equal power divider model has been implemented for both main and peaking amplifiers. If we match the ports of Wilkinson power divider, it becomes a lossless model [17]. Using the same approach, an equivalent circuit is designed using this technology. The 90-degree phase shift at one of the ports is accomplished by p-network. Previously, this work was done on BiCMOS technology [18]. Power divider in Figure 1 shows an equivalent lumped circuit as a p-network to achieve 90-degree phase.SettingZo=50Ω for perfect matching, the distributed realization can be seen with parameters C, L, and R and a tuned frequency of 2.4 GHz as R=2Zo=100Ω, L=502/2π2.4GHz=4.689nH, and C=1/2π5022.4GHz=937.8fF.Figure2 shows a very low S11=−87.8dB, S22=S33=−96.1dB shows an almost perfect match, and S12=−3.01dB is an equal split of power divider. In addition, the following is valid for the insertion loss of nearly to ideal value of −3dB.(1)Insertion loss=10log10input poweroutput power=10log1012.Figure 2
Input return loss (S11), insertion loss (S12), and output return loss (S22) for power divider circuit.For our case, where we need to perfectly match at50Ω, the transmission line is λ/4=2Zo=2100=70.71Ω. Since this is a narrow band circuit, it avoided more cascading with factor <1 as seen in the traditional method [14]. The impedance of two ports can be calculated by first applying the transmission line theory (theoretical analysis), but using equal power division. As the admittance of transmission lines is equal, the overall admittance of Z1 and Z2 can be rewritten as Y1 and Y2, respectively [15]. It gives(2)Y1=Y2=YAcotθY0+YAtanθYAcotθ+jY0.To match the input, the condition will beY0=Y2+Y3. Under the condition of both input matching, the new condition becomesY1+Y2=Y0. Remember Z0 as 50 Ω, which is the port characteristic impedance for the calculation of input impedance. Reflection coefficient is maximum at 2.4 GHz center frequency. By using the value of S11 in Figure 3 and θ=π/2, we can find the value of Γ [19], as S11=20logΓ or Zin=Z01+Γ/1−Γ.Figure 3
(a) Impedance matching through the Smith chart for power combiner lumped parameters and (b) power divider lumped parameters. (c) Wilkinson power divider and (d) power combiner using equivalent RLC model.
(a)(b)(c)(d)As an alternative and to make it precise, we will observe the impedances on the Smith chart. With an operational frequency of 2.4 GHz, a frequency span of 0 MHz, and a characteristic impedance of 50 Ω, the measured results can be observed in Figure3 which are perfectly matched.Due to symmetry,S11=S22, S21=S12, and S13=S31. Figure 4 shows the parameters achieved using the tuned scale, which are perfectly matched.Figure 4
Small signal model for (a) main power amplifier and (b) peaking power amplifier operating in subthreshold region.
(a)(b)


## 3. The Proposed Main and Peaking Power Amplifier Models with Interstage Capacitance

### 3.1. Input and Output Impedance Matching and Small Signal Model

Looking through the source path for the input impedance of the main power amplifier in Figure4,(3)Zin1=2gm1|ZC8+ZC6+ZL3|ZC5+ZC4.Similarly, for the peaking amplifier,(4)Zin2=1gm2|ZC15+ZC13+ZL5|ZC12+ZC11.Looking through the output of the main amplifier, the overall output impedance can be calculated as(5)ZOut2=ZC10||ZL4|rO1ZC9|1gm1‖ZC7.Similarly, for the peaking amplifier,(6)ZOut2=ZC19ZC18+ZL7+ZC17ZL6‖rO2|ZC16|1gm2‖ZC14,where Zin1 and Zin2 are the input impedances of the main amplifier and peaking amplifier, respectively, observed from their source to the power divider circuit. Zout1 and Zout2 are the output impedances of main amplifier and peaking amplifier, respectively, observed from the divider end to their drain. The impedances towards PA are measured to 50 Ω for perfect matching.C4 and C11 are placed in interstage capacitors between the divider of the main amplifier and peaking amplifier circuits to improve the PAE [20]. The before and after interstage capacitor effect can be seen in Figure 5. Similarly, L3||C5 and L5||L12 are placed to match and tune the fundamental frequency of 2.4 GHz. C6 and C13 block the DC bias (+Vb1 and +Vb2). M1 and M2 are operating in subthreshold region with gate-to-source voltage of 280 mV and 290 mV, respectively. C7, C8, C9, C14, C15, and C16 are placed to accommodate the unwanted parasitic capacitances. The impedance parameter values and very small variation in source impedance vary the result from the theoretical values. The design has fixed interstage capacitances unlike [21], where variable interstage capacitance has been observed due to broadband. Fixed interstage capacitances with perfect matching shows novel research contribution along with optimization.Figure 5
(a) The transient state before the interstage capacitor and (b) the transient state after the interstage capacitor of the main amplifier. (c) The result before the interstage state of the peaking amplifier and (d) its effect after the interstage capacitor as input power reaches −7 dBm.
(a)(b)(c)(d)


### 3.2. Subthreshold Operation in Triode Region

Figure6 shows the input operation for VGS operating at much lower pinch-off point. The output observed at the drain of the main amplifier M1 varies as the input varies from −20 dBm to −7 dBm. The input is applied at the gate of the main amplifier and the output is sensed at its drain. The gm/Id technique is used to relate the normalized drain current to the transconductance drain current, and the results are further optimized to achieve the power gain.Figure 6
(a) Subthreshold operation of the main amplifier and (b) the peaking amplifier with distinctive gm values, operating much lower than the pinch-off point. (c) The transient output voltage (red dotted line) and the transient output current (brown dotted line) at −20 dBm input voltage. (d) The same simulation results as seen in (c) for −7 dBm inputs.
(a)(b)(c)(d)


## 3.1. Input and Output Impedance Matching and Small Signal Model

Looking through the source path for the input impedance of the main power amplifier in Figure4,(3)Zin1=2gm1|ZC8+ZC6+ZL3|ZC5+ZC4.Similarly, for the peaking amplifier,(4)Zin2=1gm2|ZC15+ZC13+ZL5|ZC12+ZC11.Looking through the output of the main amplifier, the overall output impedance can be calculated as(5)ZOut2=ZC10||ZL4|rO1ZC9|1gm1‖ZC7.Similarly, for the peaking amplifier,(6)ZOut2=ZC19ZC18+ZL7+ZC17ZL6‖rO2|ZC16|1gm2‖ZC14,where Zin1 and Zin2 are the input impedances of the main amplifier and peaking amplifier, respectively, observed from their source to the power divider circuit. Zout1 and Zout2 are the output impedances of main amplifier and peaking amplifier, respectively, observed from the divider end to their drain. The impedances towards PA are measured to 50 Ω for perfect matching.C4 and C11 are placed in interstage capacitors between the divider of the main amplifier and peaking amplifier circuits to improve the PAE [20]. The before and after interstage capacitor effect can be seen in Figure 5. Similarly, L3||C5 and L5||L12 are placed to match and tune the fundamental frequency of 2.4 GHz. C6 and C13 block the DC bias (+Vb1 and +Vb2). M1 and M2 are operating in subthreshold region with gate-to-source voltage of 280 mV and 290 mV, respectively. C7, C8, C9, C14, C15, and C16 are placed to accommodate the unwanted parasitic capacitances. The impedance parameter values and very small variation in source impedance vary the result from the theoretical values. The design has fixed interstage capacitances unlike [21], where variable interstage capacitance has been observed due to broadband. Fixed interstage capacitances with perfect matching shows novel research contribution along with optimization.Figure 5
(a) The transient state before the interstage capacitor and (b) the transient state after the interstage capacitor of the main amplifier. (c) The result before the interstage state of the peaking amplifier and (d) its effect after the interstage capacitor as input power reaches −7 dBm.
(a)(b)(c)(d)


## 3.2. Subthreshold Operation in Triode Region

Figure6 shows the input operation for VGS operating at much lower pinch-off point. The output observed at the drain of the main amplifier M1 varies as the input varies from −20 dBm to −7 dBm. The input is applied at the gate of the main amplifier and the output is sensed at its drain. The gm/Id technique is used to relate the normalized drain current to the transconductance drain current, and the results are further optimized to achieve the power gain.Figure 6
(a) Subthreshold operation of the main amplifier and (b) the peaking amplifier with distinctive gm values, operating much lower than the pinch-off point. (c) The transient output voltage (red dotted line) and the transient output current (brown dotted line) at −20 dBm input voltage. (d) The same simulation results as seen in (c) for −7 dBm inputs.
(a)(b)(c)(d)


## 4. Simulation Findings Using 65 nm CMOS Technology

A few of the simulation findings have already been shown in the figures in previous sections. For standardVDD=1.2Vand defined VTH=450m and M1 operating as main amplifier at subthreshold value of VGS1=Vb1=280mV, the simulation findings observed are as follows: Id1=547.5uA, gm1=10.78m, gm1/Id1=19.74, and PDC1=985.1uW. For M2 operating as the peaking amplifier at subthreshold value of VGS2=Vb2=290mV, the simulation findings observed are as follows: Id2=663.5uA, gm2=12.64m, gm2/Id2=19.1, and PDC2=1.194mW (see Figure 6 for subthreshold operations).


### 4.1. Scheme for Linearization

Vb1 and Vb2 (gate-to-source voltages) are set to the levels observed in Figures 6(a) and 6(b) to reduce the strong nonlinear behavior. The Taylor expansion [22] expresses the maximum linearity in the circuit design to optimize the proper bias voltage for both amplifiers. If Ids1 and Ids2 represent the nonlinear drain-to-source currents in the main and power amplifier, respectively, the expansion is as follows:(7)Ids1=gm_1.Vb1+gm_12!Vb12+gm_33!Vb13+⋯,(8)Ids2=gm_1.Vb2+gm_12!Vb22+gm_33!Vb23+⋯,where the second and third harmonics are gm_2 and gm_3, respectively, which are further expressed as(9)Ids1.2w2−w1=34gm_3Vb1,w22.Vb1,w1,where gm_3 generates the third-order intermodulation which is almost neglected and considered nearly equal to zero.


## 4.1. Scheme for Linearization

Vb1 and Vb2 (gate-to-source voltages) are set to the levels observed in Figures 6(a) and 6(b) to reduce the strong nonlinear behavior. The Taylor expansion [22] expresses the maximum linearity in the circuit design to optimize the proper bias voltage for both amplifiers. If Ids1 and Ids2 represent the nonlinear drain-to-source currents in the main and power amplifier, respectively, the expansion is as follows:(7)Ids1=gm_1.Vb1+gm_12!Vb12+gm_33!Vb13+⋯,(8)Ids2=gm_1.Vb2+gm_12!Vb22+gm_33!Vb23+⋯,where the second and third harmonics are gm_2 and gm_3, respectively, which are further expressed as(9)Ids1.2w2−w1=34gm_3Vb1,w22.Vb1,w1,where gm_3 generates the third-order intermodulation which is almost neglected and considered nearly equal to zero.


## 5. Power Consumption Trade-Offs for Amplifiers

The bandwidth of WLAN application-based devices operates between 2.4 GHz and 2.48 GHz [23]. Figure 7 shows the thermal noise which can be observed between this range using the relation for drain thermal noise which is expressed as(10)idn2=4kToΔfγGdo,where k is Boltzmann's constant in joules per kelvin, To is temperature in kelvin, Δf is the bandwidth in Hz, and γ is an enhancement factor [24]. The above equation can be written as(11)v2R=4kToΔfγGdo,or(12)v=4kToΔfγGdoR,hence the difference between the output noise and input noise. Figure 8 shows the maximum levels of noise for both input and output ports. A change of 0.3 nV/Hz of noise levels was observed at the output port with respect to the input port.Figure 7
Comparative change in input vs. output noise innV/Hz from 2.3 GHz to 2.6 GHz range.Figure 8
(a) The comparison of PAE to the input power and (b) the comparison of PAE to the output power. (c) Proof of the DC power consumption at a maximum level of 2.1 mW.
(a)(b)(c)


## 6. DC Power Dissipation, Power-Added Efficiency (PAE), and Gate Biasing for Enhanced Power Backoff Efficiency

The DC power exponentially increases as the drain voltage increases. Figure8(a) shows the maximum value of 2.1 mW as the overall DC power consumption when VDD reaches its maximum value of 1.2 volts. Both M1 and M2 are operating in a triode with even low subthreshold values for DC operating current of ID [25]. The DC power consumption from both M1 and M2 can be summed up using the following equation:(13)Pdc=μnCox2W1L12Vb1−VTH1Vout1−Vout122ZL4+W2L22Vb2−VTH2Vout2−Vout222ZL6,where few of the individual parameters’ findings using simulation tool are already shown under the heading “Simulation findings using 65 nm CMOS technology.” Also, Vout1=Vout2=VDD as no voltage drop is observed across L4 and L6. The length L1=L2=60nm is a default set value for TSMC 65 nm technology. The width to adjust the DC can be found using the equation above. The transistor is turned on, and keeping fixed gate voltage and fixed threshold voltage values, the area under the curve will be estimated for the perfect width to achieve this DC power consumption [26]. For our case, W1/L1=W2/L2=30μm/60nm, showing the number of fingers equal to 5 and width per finger equal to 6μm. Each width can be theoretically estimated using the following equations:(14)W1=∫VoffVonID1dVout1,W2=∫VoffVonID2dVout2,W1=μnCoxVb1−VTH1∫VoffVonVout1dVout1−∫VoffVonVout12dVout1,W2=μnCoxVb2−VTH2∫VoffVonVout2dVout2−∫VoffVonVout22dVout2.The power-added efficiency (PAE) of the proposed HPA is 29.8%, which can be easily understood byη=Pout−Pin/Pdcx100, where Pin and Pout represent the input power and output power, respectively. Theoretically, only class F power amplifier has the ability to achieve 100% of PAE [27], which is not possible for the case of Doherty due to different classes of PA. However, both biasing voltages at subthreshold regions are optimized at perfect matching to achieve the backoff level at 29.8% PAE. This PAE can be found at 4 dB backoff point.


## 7. The Overall Input Return Loss and Gain

The input return loss (S11) and output gain (S21) can be observed in Figure 9. The PA has a maximum gain (S21) of 10.3 dB with an input reflection loss (S11) of −13.4 dB observed at 2.4 GHz. The input referred 1 dB compression point isequal to 4.1 dBm. The total power of PA is 2.1 mW.Figure 9
(a) The input return loss (S11). (b) The 1 dB compression point. (c) The DC power consumption ofM1 equals 985.1 uW when the input-referred drain current equals 547.5 uA. (d) The DC power consumption of M2 equals 1.194 mW when the input-referred drain current equals 663.5 uA.
(a)(b)(c)(d)Using interstage capacitances through the path of lumped parameters to main and auxiliary amplifiers, less than 10 dB of input power has been reflected to the Wilkinson divider path which shows perfect impedance matching towards the input end. Gate-to-drain insulation for bothM1 and M2 creates a negative conduction in reverse path. Similar perfect matching at the output enhances the gain even higher to 10 dB.Major simulation results can be observed in Figure10.Figure 10
(a) The input return loss (S11), insertion loss (S12), and output return loss (S22) power-divider circuit. (b) The input-referred 1 dB compression point. (c) The input reflection loss (S11). (d) The output gain (S21). (e) The power-added efficiency (PAE). (f) Validated software results with yellow line showing input noise and red showing the output noise. (g) Harmonic content and power contours.
(a)(b)(c)(d)(e)(f)(g)


## 8. Performance Parameters of 2.4 GHz RF ULP Power Amplifier

Table1 summarizes the performance of the proposed ULP-PA in comparison with other current state-of-the-art CMOS PAs. The parameter comparison does not include the post-layout design results.Table 1
Performance comparison of the proposed PA.
SpecificationThis work[28][29][30][31][32]Technology65 nm130 nm40 nm65 nm180 nm90 nmYear202120202019201820172013IEEE standard802.15.4802.15.4802.15.6802.15.4802.15.1802.15.4Frequency2.4 GHz2.4 GHz2.4 GHz2.4 GHz2.4 GHz2.4 GHzDC power consumption2.1 mW4.7 mW1.5 mW1.9 mW10 mWDC current consumption1.22 mA——9.2 mASupply voltages1.2 volts1.2 volts0.9 volts1 volt1.2 voltsIIP3−12dBmOutput power2 dBm0dBm−3.3dBm−3 dBm5 dBm0 dBm–4 dBm1 dB compression point4.1 dBm−1.36dBm————Input return loss (S11)−13.1 dB−10.3 dB————Gain (S21)10.3 dB———8 dB—General class of PADoherty PA with fixed interstage capacitancesClass AB with current re-useSwitched capacitor digital PA (SCDPA)PA-ADPLL all digital scaling—Load push-pullAll digital scalingEfficiency29.85%27%39%—16%—


## 9. Conclusion

In this study, the design and calculation of a ULP Doherty power amplifier using 65 nm CMOS technology were presented. The proposed method mentions equivalent lumped parameters for Wilkinson power divider and power combiner circuit along with interstage capacitances used before the main and peaking power amplifiers. The PA shows the peaking output power of 2 dBm with −7 dBm input. The measurement results are summarized in Table1. The design consumes significantly low power by consuming as low as 2.1 mW DC power on overall main and peaking amplifiers.


## 10. Future Enhancement

The TSMC technology is a well-developed library based on 65 nm CMOS IC design which is cheaper to manufacture on mass-level production. The future project includes fabricating and manufacturing the simulated design. The contribution in research will lead to production of PAs for short-range WPAN sensing and data transfer devices under the umbrella of IEEE 802.15.x standard.



---

*Source: 3364016-2021-11-19.xml*