# Carrier-Based Common Mode Voltage Control Techniques in Three-Level  Diode-Clamped Inverter

Authors: Pradyumn Chaturvedi; Shailendra Jain; Pramod Agarwal
Journal: Advances in Power Electronics
 (2012)

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## Abstract

Switching converters are used in electric drive applications to produce variable voltage, variable frequency supply which generates harmful largedv/dt and high-frequency common mode voltages (CMV). Multilevel inverters generate lower CMV as compared to conventional two-level inverters. This paper presents simple carrier-based technique to control the common mode voltages in multilevel inverters using different structures of sine-triangle comparison method such as phase disposition (PD), phase opposition disposition (POD) by adding common mode voltage offset signal to actual reference voltage signal. This paper also presented the method to optimize the magnitude of this offset signal to reduce CMV and total harmonic distortion in inverter output voltage. The presented techniques give comparable performance as obtained in complex space vector-based control strategy, in terms of number of commutations, magnitude, and rate of change of CMV and harmonic profile of inverter output voltage. Simulation and experimental results presented confirm the effectiveness of the proposed techniques to control the common mode voltages.


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## Body

## 1. Introduction

In the medium-voltage,  high-power adjustable speed drive (ASD) system, AC supply is first converted into DC (known as DC buffer stage) and then converting back this DC into variable voltage variable frequency AC supply using inverter (voltage source or current source type). Figure1 shows the general block diagram of AC-DC-AC induction motor drive system. The front-end converter may be uncontrolled or controlled voltage source or current source rectifier while the motor side converter can be conventional two-level or multilevel VSI, CSI. In VSI fed drive, the DC link capacitor Cd (C1 and C2) is sufficiently large and DC link inductor Ld is not required whereas in CSI fed drive, Ld is sufficiently large and Cd is not needed [1, 2].Figure 1
General block diagram of AC-DC-AC VSI or CSI fed ASD (onlyLd in CSI and only C1, C2 in VSI).The DC buffer stage consists of only large capacitor in the case of voltage source inverter and only large inductor in the case of current source inverter. This process involves switching power semiconductors to manipulate the magnitude and frequency of the output waveforms. The switching action of rectifiers and inverters results in common mode voltages which are essentially zero-sequence voltages superimposed with switching noise which will appear at rectifier, inverter, and motor terminals [1, 2]. If not mitigated, they appear on the neutral of the stator winding with respect to ground, which should be zero when the motor is powered by a three-phase balanced utility supply. Further, the motor line-to-ground voltage, which should be equal to the motor line-to-neutral (phase) voltage, can be substantially increased due to the common mode voltages, leading to premature failure of motor winding insulation system. As a consequence, the motor life expectancy is shortened. This phenomenon is different from the high dv/dt caused by the switching transients of the high-speed switches [3–6].Therefore, it is necessary to control/eliminate the common mode voltage magnitude and its rate of change. Common mode voltage reduction/elimination techniques, available in literature, can be classified as given below [1–6]:(A)
using some extra hardware circuitry such as isolation transformer, zero-sequence impedance (common mode choke), active and passive filters, dual bridge inverter, using four-leg (four-phase) inverter, or(B)
using modification in control strategy employed based on space vector PWM technique (SVPWM) or sinusoidal PWM technique (SPWM).Techniques mentioned in (A) above increases the system cost and complexity in control with reduced reliability. Techniques mentioned in (B) are commonly used. In SVPWM techniques, the switching state voltage vectors generating zero common mode voltage are only used [7, 8]. Various forms of SVPWM techniques are available to mitigate the common mode voltage problem, that is, nearest three vector selection (NTV) SVPWM, radial state SVPWM zero common mode voltage SVPWM, and so forth [8]. CMV reduction in adjustable speed drive system and its rate of change play an important role in designing electromagnetic interference (EMI) filters. SVPWM-based techniques for this purpose requires comparatively complex algorithm [7, 9–12].In industrial applications requiring variable voltage, variable frequency supply to fed three-phase induction motors at medium- and high-voltage levels, multilevel inverters (MLI) have been found better counterpart to conventional two-level inverters. MLI produce lower common mode voltage stress across converter and motor terminals. Carrierbased modulation techniques are most widely used in MLI, especially in neutral point clamped (NPC) inverter. For cascaded H-bridge inverters, phase shifted carrier-based modulation techniques are most widely used with some derived strategies for improved performance [6, 8]. However, research is going on SVPWM-based technique to solve some inherent problems in NPC inverters, carrier-based SPWM techniques remain widely adopted because of their simplicity and reduced computational requirements as compared to SVPWM technique. Recent work reported in [6, 13–17] shows that carrier-based SPWM and SVPWM techniques for MLI are equivalent. Due to inherent problem of unequal properties of two DC link capacitors, inverter voltage gets unbalanced which can be made balanced easily by using the technique presented in [17, 18].A current control strategy is presented in [19] to reduce the maximum common mode voltage levels of a three-phase inverter in adjustable speed drive applications. A hybrid selective harmonic elimination PWM scheme is given in [20] for common mode voltage reduction in three-level neutral-point-clamped inverter-based induction motor drive system. It automatically corrects the modulation index level to control the number of switching per cycle and also improves the load voltage and current waveform quality. Loh et al. presented the space vector PWM-based modulation techniques to reduce the common mode voltage in cascaded multilevel inverter [21]. The techniques used by Loh were phase disposition, phase opposition disposition, and alternate phase opposition disposition with phase shifting algorithm using space vector PWM.Holmes and others [14–16] presented analytical expressions for different voltages using FFT analysis for cascaded and hybrid multilevel inverters. The modulation technique used was alternate phase opposition disposition and phase shifted carrier PWM for 5-level cascaded and hybrid multilevel inverters. Simple SPWM-based techniques have been proposed in the presented work to control the CMV in AC-DC-AC ASD system. The proposed SPWM-based control techniques are based on phase disposition (PD) and phase opposition disposition (POD) concepts with addition of offset voltage signal to actual reference signal.The second section reviews the various common mode voltage control techniques and explains the proposed concept to control CMV. Simulation performance of the proposed control technique is given in section three. Experimental verification of proposed techniques is presented in section four. Section five gives conclusion.


## 2. Common Mode Voltage Control

Various common mode voltage reduction/elimination techniques can be classified as given below.(A)
Using some extra hardware circuitry such as
(i)
isolation transformer;(ii)
zero-sequence impedance (common mode choke);(iii)
active and passive filters;(iv)
dual bridge inverter;(v)
using four-leg (four-phase) inverter.(B)
Using modification in control strategy employed such as, based on
(i)
space vector PWM technique (SVPWM);(ii)
sinusoidal PWM technique (SPWM).The proper choice of common mode choke provides high impedance to common mode current and can eliminate the CMV. Further, any practice to eliminate CMV may increase the common mode current [9, 11]. Thus, investigation is required on this issue. The main issue is that the THD and switching losses increase with controlling the CMV. During the control pulse generation in multilevel inverters, some switching states produce reduced/zero common mode voltage across motor windings and inverter output terminals.In SVPWM techniques, the switching state voltage vectors generating zero common mode voltage are only used [7, 8]. Various forms of SVPWM techniques are available to mitigate the common mode voltage problem, that is, nearest three vector selection (NTV) SVPWM, radial state SVPWM, zero common mode voltage SVPWM, and so forth [8].In ASD system, magnitude and rate of change of CMV play an important role in designing EMI filters. SVPWM-based techniques for this purpose require comparatively complex algorithm [7, 9–12]. On the other hand, SPWM-based techniques require less complex algorithm with ease to implement.This section presents various simple SPWM-based techniques controlling the magnitude and rate of change of CMV. Different SPWM techniques can be classified as [14–16](i)
phase disposition (PD) method,(ii)
phase opposition Disposition (POD) method,(iii)
phase-shifted (PS) method,(iv)
hybrid (H) method,(v)
Third harmonic injection (THIPWM) method.Figure2 shows the schematic diagram of three-phase, three-level diode-clamped inverter. Figure 3 shows the principle of generation of control pulses for 3-level inverter with conventional PD SPWM technique. Fundamental frequency three-phase sinusoidal reference waves  Vr, Vy, and Vb are compared with two high-frequency triangular carrier waves “carrier 1” and “carrier 2”. Each intersection gives rise to the control pulses for switching devices of inverter. These reference sinusoidal waves, V(r,y,b) can be represented by(1)Vr=Vmsin(ωt),Vy=Vmsin(ωt-120°),Vb=Vmsin(ωt-240°).Figure 2
Schematic diagram of three-phase, three-level diode-clamped inverter.Figure 3
Generation of control pulses for 3-level inverter with PD SPWM technique.The control pulses generated by comparison of reference voltage wave with “carrier 1” are given to upper switches (Sa1, Sb1, Sc1) of inverter shown in Figure 2. The corresponding complementary signals of these pulses are given to (Sa1′, Sb1′, Sc1′). The control pulses generated by comparison of reference voltage wave with “carrier 2” are given to switches (Sa2, Sb2, Sc2). The corresponding complementary signals of these pulses are given to (Sa2′, Sb2′, Sc2′).


### 2.1. Proposed Method of CMV Control

Common mode voltage magnitude and its rate of change depend on the control pulse width, number of commutation, and its frequency which can be modified by adding some offset signal to reference voltage wave. Offset voltage plays an important role in modifying the modulating signal. This section gives the basic idea of adding the offset signal to PD and POD SPWM techniques. Common mode voltage or zero sequence voltage in output voltage of inverter can be represented by(2)Vcm=(Vr+Vy+Vb)3,
where, Vr, Vy, and Vb are the phase voltages of inverter. This voltage is around DC link voltage in conventional 2-level inverters and half of the DC link voltage in 3-level inverter. To reduce it, following common mode offset voltage is to be added
(3)Voff=-[min(Vr,Vy,Vb)+max(Vr,Vy,Vb)]2,
where min(Vr,Vy,Vb) and max(Vr,Vy,Vb) are the minimum and maximum functions of reference voltage wave. New reference or modulating wave can be calculated by adding this common mode offset voltage signal to original reference voltage wave as
(4)V*(r,y,b)=V(r,y,b)+Voff,
where, V(r,y,b) is given by (1). The “max”, “min”, one-phase voltage Vr and offset voltage signal, according to (1) to (4), are shown in Figure 4 for PD SPWM technique. This common mode voltage offset signal controls the CMV in inverter output. Figures 5 and 6 give the new 3-phase reference waves as obtained from (4) in PD and POD SPWM techniques. In POD SPWM technique, the two carrier signals are in phase opposition as shown in Figure 6.Figure 4
Signals “Vmax,” “Vmin,” “Vr,” and offset voltage “Voffset” in offset PD SPWM technique.Figure 5
Generation of pulses for 3-level inverter with offset PD SPWM technique.Figure 6
Generation of pulses for 3-level inverter with offset POD SPWM technique.


## 2.1. Proposed Method of CMV Control

Common mode voltage magnitude and its rate of change depend on the control pulse width, number of commutation, and its frequency which can be modified by adding some offset signal to reference voltage wave. Offset voltage plays an important role in modifying the modulating signal. This section gives the basic idea of adding the offset signal to PD and POD SPWM techniques. Common mode voltage or zero sequence voltage in output voltage of inverter can be represented by(2)Vcm=(Vr+Vy+Vb)3,
where, Vr, Vy, and Vb are the phase voltages of inverter. This voltage is around DC link voltage in conventional 2-level inverters and half of the DC link voltage in 3-level inverter. To reduce it, following common mode offset voltage is to be added
(3)Voff=-[min(Vr,Vy,Vb)+max(Vr,Vy,Vb)]2,
where min(Vr,Vy,Vb) and max(Vr,Vy,Vb) are the minimum and maximum functions of reference voltage wave. New reference or modulating wave can be calculated by adding this common mode offset voltage signal to original reference voltage wave as
(4)V*(r,y,b)=V(r,y,b)+Voff,
where, V(r,y,b) is given by (1). The “max”, “min”, one-phase voltage Vr and offset voltage signal, according to (1) to (4), are shown in Figure 4 for PD SPWM technique. This common mode voltage offset signal controls the CMV in inverter output. Figures 5 and 6 give the new 3-phase reference waves as obtained from (4) in PD and POD SPWM techniques. In POD SPWM technique, the two carrier signals are in phase opposition as shown in Figure 6.Figure 4
Signals “Vmax,” “Vmin,” “Vr,” and offset voltage “Voffset” in offset PD SPWM technique.Figure 5
Generation of pulses for 3-level inverter with offset PD SPWM technique.Figure 6
Generation of pulses for 3-level inverter with offset POD SPWM technique.


## 3. Simulation Results

The proposed CMV control techniques are now verified in simulation. The simulation parameters for common mode control are given in Table1 for medium voltage, 3-phase, squirrel cage induction motor.Table 1
Simulation parameters.
DC link voltage
10.16 kV
Load power
2.45 MW
Load voltage
6.6 kV
Load current
256 amps
Load power factor
0.84
Carrier frequency
2.2 kHzThe CMV in 2-level inverter is compared with CMV in 3-level SPWM techniques using the proposed offset voltage SPWM techniques. Figure7 shows the common mode voltages in 2-level and different 3-level SPWM techniques indicating the effect of adding the CMV offset signal. Figures 8 and 9 show the inverter output voltage and its harmonic spectrum with PD SPWM, Offset PD SPWM, POD SPWM, and offset POD SPWM.Common mode voltages in (a) 2-level inverter, (b) PD SPWM, (c) PD SPWM with offset voltage signal, (d) POD SPWM, and (e) POD with offset voltage signal.
(a)
(b)
(c)
(d)
(e)Inverter output voltage and its harmonic spectrum with (a) PD SPWM and (b) offset PD SPWM.
(a)
(b)Inverter output voltage and its harmonic spectrum with (a) POD SPWM and (b) offset POD SPWM.
(a)
(b)The magnitude of CMV is reduced as we move from 2-level to 3-level SPWM technique or from PD to POD SPWM technique as shown. The frequency of CMV is three times the fundamental frequency of inverter output voltage. POD with offset signal gives better CMV behavior but at the cost of increased voltage THD. While PD SPWM with offset signal gives much better voltage THD performance (7.81% without any filter) with reduced switching transients in CMV as compared to PD SPWM and other techniques.The magnitude, ripples, and number of commutations in CMV at inverter and load terminals in POD with offset signal are greatly reduced. Comparison of inverter voltage THD for these techniques is given in Figures8 and 9, respectively.The switching frequency is increased in PD with offset signal technique which can be controlled by the method proposed in [17]. However, the change in line voltage across switching devices is two times in POD and offset POD method as compared to PD and offset PD method as given in Figure 9. It compensates any increase in switching frequency because switching losses depend on instantaneous voltage and current across and through the switch, respectively. Table 2 provides comprehensive comparison of these techniques based on inverter voltage/current THD (without/with passive filter), average CMV, and average neutral point potential (NPP).Table 2
Comparison of CMV control techniques.
Without filter
With filter (L = 1.2 mH, C = 100 uF)
SPWM technique
Line voltage (kV)
Line current (amps)
Line voltage (kV)
Line current (amps)
Average NPP (Vnp) volts
Average CMV (Vcm) volts
V
1
ab
% THD
i
1
a
% THD
V
1
ab
% THD
i
1
a
% THD
PD
8.1
20.51
254
28.39
15.6
3.13
256
0.86
8.3
59.2
POD
8.1
25.97
250
32.57
15.6
2.92
254
0.78
16.1
69.1
PD + off-set voltage
8.0
7.81
254
18.16
15.6
3.24
258
0.85
1.4
25.3
POD + off-set voltage
8.1
35.63
257
43.43
15.6
3.39
259
0.77
8.3
59.6


## 4. Experimental Results

A laboratory prototype of three-phase, diode-clamped or neutral-point-clamped inverter has been developed for experimentation. The experimental parameters are listed in Table3. The dSPACE DS1104 has been used for real-time control of the inverter.Table 3
Experimental parameters.
DC link voltage
100 volts
DC link capacitor
2200μF (each)
Load resistance
45 Ω
Load inductance
5.2 mH
Carrier frequency
2 kHzThe inverter line voltages are shown in Figures10, 11, 12 and 13 for PD, POD, offset PD, and offset POD techniques, respectively. It is clearly shown that the frequency of switching per half cycle and the rate of change of switch voltage is different in each case. Slight unbalance in line voltage is due to no load operation. The DC link voltage balancing has been given in [17, 18] which not only balances the DC link voltages but also reduces the switching losses.Figure 10
Inverter output voltagesVab, Vbc, and Vca with PD SPWM technique (x-axis: 5 ms/div, y-axis: 50 V/div).Figure 11
Inverter output voltagesVab, Vbc, and Vca with POD SPWM technique (x-axis: 5 ms/div, y-axis: 50 V/div).Figure 12
Inverter output voltagesVab, Vbc, and Vca with offset PD SPWM technique (x-axis: 5 ms/div, y-axis: 50 V/div).Figure 13
Inverter output voltagesVab, Vbc, and Vca with offset POD SPWM technique (x-axis: 5 ms/div, y-axis: 50 V/div).Figure14 shows the frequency spectrums of inverter output line voltage (Vab) with (a) PD SPWM, and (b) POD SPWM techniques, respectively. Figure 15 shows the frequency spectrums of inverter output line voltage (Vab) with (a) offset PD SPWM, and (b) offset POD SPWM techniques, respectively. It is clearly shown that minimum THD occurs in offset PD SPWM technique and maximum fundamental load voltage is available in offset POD SPWM technique. Second-order harmonics is present in each case because of slight unbalance in DC link voltages which can be easily balanced by using the technique given in [18]. Figure 16 shows the waveforms of load voltages and load currents with PD SPWM techniques. Figure 17 shows the frequency spectrums of load voltage (Vab) and load current (ia) with PD SPWM technique. These experimental results are comparable with the simulation results presented in Figures 8 and 9.Frequency spectrums of inverter output line voltage (Vab) with (a) PD SPWM and (b) POD SPWM techniques.
(a)
(b)Frequency spectrums of inverter output line voltage (Vab) with (a) offset PD SPWM and (b) offset POD SPWM techniques.
(a)
(b)Figure 16
Load voltages and load currents PD SPWM technique (x-axis: 10 ms/div, y-axis: voltages-20 V/div, currents-5 A/div).Frequency spectrums of load voltage (Vab) and load current (ia) with PD SPWM technique.
(a)
(b)


## 5. Conclusion

This paper explored the opportunities of common mode voltage (CMV) control using simple sine-triangle comparison techniques for 3-level diode-clamped inverter. CMV at inverter terminals has been obtained and compared for 2-level, 3-level PD SPWM, and 3-level POD SPWM techniques. Further, a new method for reduction of CMV based on SPWM technique has been derived based on the addition of variable CMV offset signal to the original modulating wave.Simulation and experimental results show the effectiveness of the proposed techniques giving improved performance with the reduction of magnitude and number of commutations per cycle in CMV. It shows that offset PD SPWM gives drastically reduced voltage THD (7.81%) without using any filter. These values are much lower as compared to their counterpart 2-level (52.48%), 3-level PD SPWM (20.51%), and POD SPWM (25.97%). Average value of neutral point potential (NPP) and CMV are minimum in offset PD SPWM technique. The sharp edges in CMV with conventional SPWM technique are also reduced with the proposed method. Experimental results are comparable with the simulated results. The problem of slight unbalancing in DC link voltages as evident from experimental results can be solved by using the technique presented in [17, 18].



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