# Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology

Authors: Wu-Te Weng; Yao-Jen Lee; Horng-Chih Lin; Tiao-Yuan Huang
Journal: International Journal of Plasma Science and Engineering
 (2009)

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## Abstract

This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.


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## Body

## 1. Introduction

Researchers   first reported  plasma-induced damage (PID) in 1983 [1] using the plasma steps during the interconnect formation processes. PID is well known to degrade both gate dielectric and metal-oxide-semiconductor field-effect transistors (MOSFETs) reliability [2]. The silicon wafer manufacturing employs many plasma-processing steps, including gate electrode etching [3], high-density plasma chemical vapor deposition (HDP-CVD)  [4], metal interconnect etching [5], and photoresist ashing [6]. During plasma processing, charges (i.e., ions or electrons) accumulated from a large interconnect area cause a local imbalance in the surface potential across the gate dielectric  and cause current to flow through the gate electrode. The plasma damage current can potentially break the gate dielectric bonds with increasing gate dielectric leakage current or decreasing breakdown voltage. Moreover, the defects or weak points that PID creates in the bulk dielectric and the dielectric/Si-substrate interfaces can further degrade the transistor reliability after reliability stressing.However, SiO2 as the gate dielectric is now facing fundamental physical limitations, as film thickness comprises only a few atomic layers [7]. To solve this fundamental barrier, high-k/metal-gate transistors can be introduced into advanced complementary metal-oxide-semiconductor (CMOS) technology to replace SiO2/poly-gate transistors in suppressing the gate leakage current and eliminating poly depletion effect [8]. Therefore, the process of high-k/metal-gate fabrication must be compatible with current CMOS technology, and the electrical reliability of high-k/metal-gate transistor must be considered for long-term operation [9]. Previous studies on p-channel MOSFETs (PMOSFETs) have shown that positive charges become trapped in the SiO2/Si-substrate interface under negative gate bias, causing shifts in the threshold voltage (VTH) during prolonged device operation (i.e., negative bias temperature instability (NBTI) effect) [10]. In addition, for n-channel MOSFETs (NMOSFETs), electrons trapped in oxygen vacancies cause  a significant shift in VTH under positive gate bias stress (i.e., positive bias temperature instability (PBTI) effect)  [11]. Therefore, both NBTI and PBTI become important issues for high-k/metal-gate transistors and it is necessary to pay significant attention to the PID-enhanced transistor reliability degradation as CMOS technology continues to scale. Several studies reported PID impacts on high-k/metal-gate transistors [12, 13], but a comprehensive study on the antenna ratio dependence and gate dielectric thickness dependence in damage-enhanced gate dielectric failure and damage-enhanced transistor reliability degradation is still lacking.In this study we propose both damage mechanism and degradation models for high-k/metal-gate transistors  and compares the damage-enhanced degradations between high-k/metal-gate and conventional SiO2/poly-gate transistors. In addition to gate dielectric degradation, in this study we investigate the transistor reliability issues, including NMOSFETs’ PBTI and PMOSFETs’ NBTI by damage-enhanced electron trapping. For the first time, a universal relationship between PID and gate dielectric thickness scaling is unveiled. Further, this study demonstrates the power-law dependence between gate antenna ratio and the transistor’s reliability degradations. Researchers can use proposed models to accurately predict gate dielectric failure and transistor lifetime in the presence of PID for advanced high-k/metal-gate CMOS technology.


## 2. Experimental Procedure

### 2.1. Wafer Processing

Advanced high-k/metal-gate and conventional SiO2/poly-gate transistors processed with full layers of CMOS technology were investigated in this study. Many process steps including shallow trench isolation (STI)  and the formation of a triple well, shallow junction, and Co salicide were all integrated for high-performance circuit applications. The doping concentration of the substrate was about 5×1015 cm-3  and the concentration of the transistor’s well was around 4×1017 cm-3. For the conventional SiO2/poly-gate transistors, the gate oxide thickness ranged from 1.5 nm to 3.0 nm, while for the Hf-based high-k/metal-gate transistors, the equivalent oxide thickness (EOT) ranged from 1.5 nm to 2.0 nm (i.e., with physical thickness of approximately 3.0–5.0 nm). For high-k/metal-gate transistors, the dielectric consisted of a SiO2  interfacial layer (IL) and an HfSiO film, which were both treated with NH3 annealing. A rapid thermal annealing (RTA) at 1000°C for 5 seconds was performed for the source/drain activation. The ratio of Hf/(Hf+Si) of HfSiO film was 50%. After NH3  annealing, Hf–N bonds increase the crystallization temperature of high-k/metal-gate process, retaining the compatibility to conventional SiO2/poly-gate process with high-temperature RTA [14, 15]. A chemical oxide with thickness of 0.8 nm was used as the IL layer, and HfSiO layers with different physical thicknesses ranging from 2.0 to 4.0 nm were fabricated in this study. It is worth noting that the IL layer serves as a reaction barrier between high-k and Si-substrate [9]. Dual metal-gate structures (i.e., TaC for NMOSFET’s metal-gate and MoNx for PMOSFET’s metal-gate) were manufactured to meet high-speed performance requirements. The high-k and metal films were deposited using atomic-layer deposition (ALD) and physical vapor deposition (PVD) techniques, respectively.


### 2.2. Test Structure Design

Figure1(a) illustrates that plasma-induced damage can usually be detected using various antenna structures. These antenna structures include a transistor with a large gate antenna attached to its gate electrode, which amplifies the charging damage produced under plasma processing during the gate electrode formation process. Therefore, during metal-gate definition process in etching systems as well as postgate dielectric film deposition in HDP-CVD systems, plasma will attack the gate antenna area and damage the gate dielectric (Figure 1(b)). The gate antenna ratio, AR, is defined asSchematic diagrams of the transistor with its gate being connected to an antenna structure: (a) top view of the test structure, and (b) cross section.
(a)(b)(1)AR=Areaofgate antennaAreaofgateoxide.
In this study we have fabricated a set of test structures with various AR of 3X (i.e., undamaged transistors), 100X, 500X, 1000X, 5000X, and 10000X (i.e., significantly damaged transistors) to simulate the impact of the PID effects on real circuits during  various stages of plasma processing. The gate oxide area of the monitoring transistor used in our experiment was 1 μm2, and the transistor length and width were 0.2 μm and 5 μm, respectively.


### 2.3. Electrical Measurements

In this study we define the gate dielectric failure as a twofold increase in the dielectric leakage current compared to undamaged transistors. The gate dielectric leakage current was measured under an electric field of 7~9 MV/cm, and the gate dielectric breakdown voltage VBD was measured by the voltage ramp method. In this study we define the failure ratio of gate dielectric leakage current and gate dielectric breakdown as the percentage of failure out of the total measured samples. The measurements of  NBTI on PMOSFETs and PBTI on NMOSFETs were performed under an electric field of 10 MV/cm using an HP-4156 system at 125°C. The NBTI lifetime and PBTI lifetime were defined as the time until the transistor exhibited a 50 mV shift in threshold voltage. The EOT was extracted from the capacitance-voltage characteristics using an HP-4284 system at room temperature.


## 2.1. Wafer Processing

Advanced high-k/metal-gate and conventional SiO2/poly-gate transistors processed with full layers of CMOS technology were investigated in this study. Many process steps including shallow trench isolation (STI)  and the formation of a triple well, shallow junction, and Co salicide were all integrated for high-performance circuit applications. The doping concentration of the substrate was about 5×1015 cm-3  and the concentration of the transistor’s well was around 4×1017 cm-3. For the conventional SiO2/poly-gate transistors, the gate oxide thickness ranged from 1.5 nm to 3.0 nm, while for the Hf-based high-k/metal-gate transistors, the equivalent oxide thickness (EOT) ranged from 1.5 nm to 2.0 nm (i.e., with physical thickness of approximately 3.0–5.0 nm). For high-k/metal-gate transistors, the dielectric consisted of a SiO2  interfacial layer (IL) and an HfSiO film, which were both treated with NH3 annealing. A rapid thermal annealing (RTA) at 1000°C for 5 seconds was performed for the source/drain activation. The ratio of Hf/(Hf+Si) of HfSiO film was 50%. After NH3  annealing, Hf–N bonds increase the crystallization temperature of high-k/metal-gate process, retaining the compatibility to conventional SiO2/poly-gate process with high-temperature RTA [14, 15]. A chemical oxide with thickness of 0.8 nm was used as the IL layer, and HfSiO layers with different physical thicknesses ranging from 2.0 to 4.0 nm were fabricated in this study. It is worth noting that the IL layer serves as a reaction barrier between high-k and Si-substrate [9]. Dual metal-gate structures (i.e., TaC for NMOSFET’s metal-gate and MoNx for PMOSFET’s metal-gate) were manufactured to meet high-speed performance requirements. The high-k and metal films were deposited using atomic-layer deposition (ALD) and physical vapor deposition (PVD) techniques, respectively.


## 2.2. Test Structure Design

Figure1(a) illustrates that plasma-induced damage can usually be detected using various antenna structures. These antenna structures include a transistor with a large gate antenna attached to its gate electrode, which amplifies the charging damage produced under plasma processing during the gate electrode formation process. Therefore, during metal-gate definition process in etching systems as well as postgate dielectric film deposition in HDP-CVD systems, plasma will attack the gate antenna area and damage the gate dielectric (Figure 1(b)). The gate antenna ratio, AR, is defined asSchematic diagrams of the transistor with its gate being connected to an antenna structure: (a) top view of the test structure, and (b) cross section.
(a)(b)(1)AR=Areaofgate antennaAreaofgateoxide.
In this study we have fabricated a set of test structures with various AR of 3X (i.e., undamaged transistors), 100X, 500X, 1000X, 5000X, and 10000X (i.e., significantly damaged transistors) to simulate the impact of the PID effects on real circuits during  various stages of plasma processing. The gate oxide area of the monitoring transistor used in our experiment was 1 μm2, and the transistor length and width were 0.2 μm and 5 μm, respectively.


## 2.3. Electrical Measurements

In this study we define the gate dielectric failure as a twofold increase in the dielectric leakage current compared to undamaged transistors. The gate dielectric leakage current was measured under an electric field of 7~9 MV/cm, and the gate dielectric breakdown voltage VBD was measured by the voltage ramp method. In this study we define the failure ratio of gate dielectric leakage current and gate dielectric breakdown as the percentage of failure out of the total measured samples. The measurements of  NBTI on PMOSFETs and PBTI on NMOSFETs were performed under an electric field of 10 MV/cm using an HP-4156 system at 125°C. The NBTI lifetime and PBTI lifetime were defined as the time until the transistor exhibited a 50 mV shift in threshold voltage. The EOT was extracted from the capacitance-voltage characteristics using an HP-4284 system at room temperature.


## 3. Results and Discussion

### 3.1. Dielectric Degradation

#### 3.1.1. Damage-Enhanced Dielectric  Degradation

Dielectric breakdown of high-k/metal-gate transistor is due to the clusters of disconnected bonds. These clusters propagate through the dielectric film  and finally reach the high-k/metal-gate interface. It is generally believed that defects existing in the dielectric layers can produce weak spots or trap centers that trap charges. During plasma processing, the damage current flowing through the gate dielectric can be viewed as an equivalent voltage stress, Vst, or electric field stress, Est, across the gate dielectric.   Vst or Est is able to generate lots of defects in high-k/metal gate transistors [16]. Moreover, these PID effects can aggravate the degradations of the dielectric layer owing to the extra damage current paths generated by the Vst across the dielectric layers during the plasma processing. To simplify the analysis of damage impacts during the wafer fabrication, the dependence of the damage effect on AR is introduced in terms of the plasma damage current Iplasma to simulate the damage characterization.  By assuming a fixed AR under a given plasma process, the term Iplasma can be considered as a constant current source of “damage current’’ that passes through the high-k/metal-gate electrode. As the AR increases, the total plasma current passing through the gate dielectric increases proportionally to AR. Figure 2 shows the dielectric current-voltage curves of PMOSFETs with different gate dielectric thicknesses and values of  AR.   Iplasma can be expressed as Iplasma=P·AR, where P is the plasma damage current collected when AR=1  (i.e., an antenna ratio of unity). The P value is assumed to be a constant under a given plasma processing and is expected to exhibit a process dependence due to changes in ion density, electron temperature, and so forth, as the plasma processing changes [17]. During plasma processing, dielectric breakdown occurs at plasma current density of approximately 2–20 A/cm2[18]. Thus, the experiments in this study assume that the P value is approximately 2×10-10 A with 1 μm2  transistors size (i.e., for the damaged structures with antenna ratio AR  = 100X,  Iplasma=2 A/cm2, and for structure with AR=1000X, Iplasma=20 A/cm2). Figure 2 depicts the dielectric current-voltage curves of PMOSFETs with different gate dielectric thicknesses for both high-k/metal-gates and SiO2/poly-gates. This figure also indicates the plasma damage current simulated for various AR. Comparing the plasma current-voltage with dielectric current-voltage characteristics, Iplasma corresponds to a voltage stress, Vst, on the gate electrode during plasma processing. Aggravated dielectric degradation from PID results in an increase in the effective stress voltage  Vst  across the gate dielectric during plasma processing. Clearly, Vst  not only depends on AR  but is also influenced by EOT. Figure 3 shows that the Est, defined as Vst/EOT, is a function of AR. A larger AR results in a larger Est  and therefore much more severe degradation in dielectric reliability for EOT ranging from 1.5 nm to 3.0 nm for both SiO2/poly-gate and high-k/metal-gate transistors.Figure 2
Characteristics of gate dielectric current and simulated plasma damage current with respect to voltage. The gate dielectric current curves are measured at various gate oxide thicknesses ranging from 1.5 nm to 3.0 nm for SiO2/poly-gate PMOSFETs  and EOT ranging from 1.5 nm to 2.0 nm for high-k/metal-gate PMOSFETs. This study simulates the plasma damage current for gate antenna ratios AR of 1X, 10X, 100X, and 1000X.Figure 3
Estimated electric field stress (Est) during plasma processing as a function of EOT for different AR. The inset shows the Est  as a function of AR for different EOTs.Moreover,Est strongly depends on EOT. For example, for SiO2/poly-gate transistors with a gate oxide thickness of 3.0 nm, the tunneling mechanism of plasma current passing through the dielectric can be dominated by Fowler-Nordheim (FN) tunneling, and  Est  exhibits a greater antenna dependence during plasma process. In contrast, when the EOT is reduced to  1.5~2.0 nm for both high-k/metal-gate and SiO2/poly-gate transistors, the tunneling mechanism shifts from Fowler-Nordheim tunneling to direct tunneling. This in turn produces a lower antenna dependence of Est compared to SiO2/poly-gate transistors with a gate oxide thickness of 3.0 nm.


#### 3.1.2. Results for Damage-Enhanced Dielectric Degradation

Figure4 demonstrates   the failure ratios in terms of gate dielectric leakage current and breakdown voltage for a given AR of 5000X for both SiO2/poly-gate and high-k/metal-gate PMOSFETs with various EOTs. It is evident that SiO2/poly-gate transistors with a gate oxide thickness of 3.0 nm show significant gate oxide leakage distribution and a higher VBD failure ratio as the plasma current Iplasma  increases. Specifically, the failure ratios of gate dielectric leakage and  VBD  for SiO2/poly-gate MOSFETs with a gate oxide thickness of 3.0 nm increase by 26%. In contrast, for SiO2/poly-gate and high-k/metal-gate transistors with an EOT of approximately 1.5–2.0 nm, the oxide tunneling mechanism is dominated by direct tunneling. This in turn produces a smaller stress voltage Vst, on the gate electrode stacks during plasma process. Figure 4 shows that the failure ratio of gate dielectric leakage and  VBD degradation can be reduced to less than 6% by decreasing the EOT to below 2.0 nm.       In addition, Figure 5 demonstrates the dependence between failure ratios of gate leakage current and transistors’ EOTs ranging from 1.5 nm to 3.0 nm with different ARs of 100X, 500X, and 5000X. By reducing the EOT from 3.0 nm to 1.5 nm, the dielectric failure ratio of the antenna transistors connected to AR = 500X  can be decreased from 12% to nil, and the failure ratio of the transistors connected to AR = 5000X  can be further reduced to from 26% to 2%,  as Figure 5 indicates. These results confirm that the  Est   is linearly dependent on EOT  and can be decreased by reducing EOT from 3.0 nm to 1.5 nm as well as changing the test structure from SiO2/poly-gate to high-k/metal-gate transistors. In addition, the EOT dependence of damage-enhanced gate dielectric degradation is irrespective of the AR. The results of Figures 4 and 5 are consistent with the damage models proposed in this study and shown in Figures 2 and 3.  Clearly, a transistor with an EOT of approximately 3.0 nm shows a strong AR dependence of Est. Further, PID impact on gate dielectric degradation of high-k/metal-gate transistor is determined by EOT, rather than physical thickness. This study confirms that the strong dependence of dielectric EOT causes significant damage to the input/output transistors with a thicker EOT of approximately 3.0 nm both for high-k/metal-gate and SiO2/poly-gate transistors. Therefore, high-k/metal-gate transistors with a thinner EOT would be robust for PID, because damage-induced dielectric degradation is not a serious issue for the thinner gate dielectric high-k/metal-gate transistors needed to support the operation voltage in the core circuit design.Figure 4
Failure probability of gate dielectric leakage measured on PMOSFETs with EOTs ranging from 1.5 nm to 3.0 nm for SiO2/poly-gate transistors  and EOTs ranging from 1.5 nm to 2.0 nm for high-k/metal-gate PMOSFETs. The inset is the failure probability of VBD measured for the above transistors with EOTs greater than 2.0 nm. The AR attached to these transistors is 5000X.Figure 5
Failure percentages of gate leakage current as a function of EOT for both high-k/metal-gate and conventional SiO2/poly-gate PMOSFETs with EOTs ranging from 1.5 nm to 3.0 nm with ARs of 100X, 500X, and 5000X.


### 3.2. Damage-Enhanced Threshold Voltage Instability for High-k/Metal-Gate MOSFETs

#### 3.2.1. Damage-Enhanced PBTI Degradations for High-k/Metal-Gate NMOSFETs

The results in Figure4 show  that plasma-induced damage is usually evaluated by monitoring the gate dielectric leakage current  [19]   or breakdown voltage [20] with a given antenna ratio attached to the gate electrode. The occurrence of additional gate oxide leakage implies the existence of additional current paths within the gate dielectric layers. However, prior to the formation of a conductive path within the dielectric layers, sufficient damage (i.e., defects and traps) would have been accumulated to degrade transistor reliability [21]. In other words, the degradation of transistor reliability occurs before the gate leakage increases. Because the difference in PID-induced gate leakage current between damaged and undamaged transistors is small compared with the gate tunneling current, the conventional methods (i.e., monitor the increase of gate leakage current with applying high electric filed) may fail to detect PID, especially for transistors fabricated with a thinner EOT. Previous study shows that providing a constant voltage stress (CVS) on the gate electrode after wafer processing  and the traps created during plasma process can be revealed in the dielectric layers [22]. These traps can act as sites for assisting the electron tunneling from substrate to gate electrode (i.e., trap-assisted tunneling effect) resulting in an increase in the gate dielectric leakage, as shown in Figure 6. Moreover, the energy level of the traps can be calculated from the curve of stress-induced gate leakage current (i.e., SILC) by monitoring how the peak of the increase of SILC responds to the gate voltage [23]. This result indicates that the PID preferentially degrades the high-k film or the interfacial layer. Figure 6 shows that damaged high-k/metal gate transistor exhibits an obvious and significant increase of SILC with a peak at around Vg=0.9~1.0 V. The results are consistent with high-voltage stress on transistor’s well  causing substrate hot electron injection and generating defects in high-k film [23, 24]. Furthermore, based on previous studies [25, 26], it has been proposed that the charge state of oxygen vacancies could describe the energy signature of these traps and is responsible for the increase in SILC.Figure 6
The increase of SILC as a function of gate voltage sensed from-1.5 V to 1.5 V for a damaged and an undamaged high-k/metal-gate NMOSFET. The inset illustrates trap-assisted electron tunneling through high-k film for a damaged high-k/metal-gate NMOSFET.This study assumes that the PID effects in the gate dielectric of high-k/metal-gate transistors are similar to those caused by gate voltage stress,  Vst. Moreover, during the plasma process, the damage current flux  Iplasma breaks the weak Hf-based dielectric bonds, generating oxygen-vacancy-related defects (Od) in the high-k film. Note that the oxygen-vacancy-related defect bonds are located below the conduction band of the Hf-based dielectric, and oxygen vacancies,  Vo++,  are produced from the following reaction: Od→ Vo++ + 2e- + 1/2O2  [27, 28]. The oxygen-vacancy-related defects might not be evident after the plasma processing because the postmetallization annealing process passivates them [29]. However, further electrical stress, such as PBTI and NBTI, reveals their existence.Under plasma charging, a largeEst  stress on high-k film creates many oxygen-vacancy-related defects and oxygen vacancies within the high-k film. Applying PBTI stress to high-k/metal-gate NMOSFETs causes electrons in the inversion layer to gain sufficient energy to be injected into the dielectric layers. As a result, electrons are easily trapped in the oxygen vacancies within the high-k film [11, 21]. Figure 7 shows that all NMOSFETs (both damaged and undamaged transistors) exhibit PBTI degradations: however, the damaged transistors are likely to have a higher number of oxygen vacancies as evidenced by the larger ΔVTH  shift in the time dependence of threshold voltage instability. Figure 7 depicts the PBTI dependence of high-k/metal-gate NMOSFETs with an EOT of 2.0 nm for a damaged transistor with an AR of 10000X and an undamaged transistor with an AR of 3X. This figure shows that the damaged transistors exhibit larger ΔVTH shift than the undamaged transistors as the stress time progresses. Specifically, after 1000 seconds of PBTI stress, the ΔVTH  shift is only around 85 mV for the undamaged transistors, but nearly 100 mV for the damaged transistors. This is because the damage induces an increase in oxygen-vacancy-related defects, then electrons are captured in oxygen vacancies during PBTI stress. The increased degradation exhibited by damaged transistors shown in this study is consistent with the PBTI physical models demonstrated in previous literatures [11, 25, 26].Figure 7
PBTI-inducedΔVTH shift as a function of stress time for damaged and undamaged high-k/metal-gate NMOSFETs. The inset illustrates the mechanism difference between damaged and undamaged transistors during PBTI stress.


#### 3.2.2. Damage-Enhanced NBTI Degradations for High-k/Metal-Gate PMOSFETs

For high-k/metal-gate PMOSFETs experiencing NBTI stress, holes in the inversion layer gain sufficient energy to dissociate the weak Si–H bonds. This in turn generates interface states with holes (positive charges) trapping at the SiO2/Si-substrate interface [10]. Figure 8 shows that many oxygen-related defects and oxygen vacancies exist in the high-k film, and electrons injected from the metal-gate are captured by oxygen vacancies Vo++. Furthermore, the damaged transistors show less degradation because these transistors have higher concentrations of electron trapping (i.e., negative charges) in the high-k film, which mitigates the ΔVTH  shift of hole trapping (i.e., positive charge) during NBTI stress. Figure 8 depicts the ΔVTH   shift as a function of NBTI stress time for damaged and undamaged high-k/metal-gate PMOSFETs with an EOT of 2.0 nm. This figure shows that the damaged transistors exhibit less threshold voltage shift ΔVTH than the undamaged transistors as the stress time progresses. Specifically, after 1000 seconds of NBTI stress, the ΔVTH   shift is about 30 mV for the undamaged transistors, but only 25 mV for the damaged transistors.Figure 8
NBTI-inducedΔVTH  shift as a function of stress time for damaged and undamaged high-k/metal-gate PMOSFETs. The inset illustrates the difference between damaged and undamaged transistors during NBTI stress.To verify the NBTI models proposed in this study, current separation measurements were carried out after NBTI stress (Vg=-2 V, 1000 seconds). Figure 9 shows that after NBTI stress, the injected holes are monitored by the drain (source) current, while electrons are monitored by the substrate current. Further, to investigate the electron capturing effect, this study examined both high-k/metal-gate transistors and SiO2/Poly-gate PMOSFETs with an EOT of 2.0 nm. Figure 9 shows the ratio of electron current (Ie) over the total current (i.e., hole current (Ih) + electron (Ie)) as a function of the sweeping gate voltage. This figure shows that the damaged high-k/metal-gate transistor depicts the greatest ratio of Ie/(Ie + Ih) in all experiments. This suggests that, unlike the conventional SiO2/poly-gate PMOSFETs, the damage-induced electron trapping in the high-k film plays an important role in the NBTI characteristics of high-k/metal-gate PMOSFETs, as Figure 8 indicates. This is consistent with the damage model proposed in this study. In summary, the results of Figures  6–9 show that the transient nature of the damage-enhanced electron trapping in high-k film affects the NMOFETs’ PBTI and PMOSFETs’ NBTI performance in advanced high-k/metal-gate CMOS technology.Figure 9
The ratios of Ie/(Ie + Ih) as a function of sweeping gate voltage for damaged and undamaged PMOSFETs fabricated with high-k/metal-gate and conventional SiO2/poly-gate after NBTI stress (i.e., Vg=-2 V, and 1000 seconds). The inset illustrates the current separation method to identify the injection carriers within the gate dielectric.


### 3.3. The Model of Damage-Enhanced Instability for High-k/Metal-Gate MOSFETs Reliability

Figure10 compares the plasma damage with gate dielectric current-voltage characteristics for a high-k/metal NMOSFET with EOT = 2.0 nm, showing that Iplasma  corresponds to a voltage stress, Vst, on the transistor gate dielectric during processing. Instability of PBTI and NBTI resulting from PID therefore represents an increase in the effective stress voltage  ΔVst  across the gate dielectric during plasma processing. Furthermore, the relationship between AR and  ΔVst  can be expressed asFigure 10
The characteristics of measured dielectric current and simulated damage current as a function of voltage for various AR for high-k/metal-gate NMOSFETs with an EOT of 2.0 nm.(2)ln(AR)=CΔVst,
where C is the slope of the gate dielectric current-voltage characteristics in Figure 10  and is strongly dependent on the EOT, as Figure 2 indicates. During the plasma processing, defects or traps are generated when the damage-induced  Vst  or  Est  breaks the dipoles within the dielectric [30, 31]. Several previous studies have shown that the increase of defects or traps could be a function of voltage stress [32], and these studies depict an exponential relationship between trap generation and electric field stress across the gate dielectric [33, 34]. Thus, during the plasma process, an increase in the density of oxygen-vacancy-related traps within the high-k dielectric, ΔNOV, from the gate stress can be written as an increase of voltage  stress ΔVst  as(3)ΔNOV=Aexp(γpΔEst)=Aexp(γpΔVstEOT),
where A is a constant and γp is the electric field acceleration factor. Both of these terms are dependent on the plasma process and γp  is approximately 0.1~0.2  (Dec-cm/MV) for plasma processing [35].During PBTI or NBTI stress, the  model proposed in this study shows that the injected electrons which are trapped in oxygen vacancies cause an increase in the negative charge and instability in the transistor threshold voltage. All transistors, irrespective of their antenna ratio, exhibitΔVTH  shift under PBTI or NBTI stress. However, transistors with larger AR have higher concentrations of negative charge trapped within the high-k layer. For a constant EOT, the ΔVTH  instability resulting from the increase of negative charge trapped for antenna transistor can be modeled as(4)ΔVTH=HtnARα,
wheret is the duration of the NBTI or PBTI stress, n is approximately 0.16 for both NBTI and PBTI [36], and H is a constant. The parameter α can be expressed   as(5)α=γpEOT·C.
Note  that  α  for PBTI stress is positive (i.e., ΔVTH  increases with AR), while αfor NBTI stress is negative (i.e., ΔVTH decreases with AR). The failure time  tf, defined as the time required to reach the critical threshold voltage increase ΔVthc, is(6)tf=GΔVcAR-m,
where G is a constant for a given process,  ΔVC=(ΔVthc)1/n, and m =α/n.


### 3.4. The Effects of EOT on the Damage-Enhanced Instability for High-k/Metal-Gate MOSFETs Reliability

Figures11 and 12 plot the PBTI lifetime and NBTI lifetimes, respectively, as a function of antenna ratio for high-k/metal-gate transistors with an EOT of 2.0 nm. These figures indicate that the antenna dependence m follows the power-law relationship, consistent with   (6). Figure 11 shows the antenna dependence m is 0.07 for NMOSFETs’ PBTI lifetime. However, Figure 12 indicates a larger m of 0.15 for PMOSFETs’ NBTI lifetime. The difference in the antenna dependence is caused by the difference of dielectric current-voltage characteristics. For a plasma process with a given Iplasma, PMOSFETs experience a higher stress-voltage that leads to a higher oxygen vacancy generation rate than NMOSFETs. In addition, Figure 12 demonstrates a “reverse antenna effect’’ (i.e., the NBTI lifetime increases with AR) for high-k/metal-gate PMOSFETs. This effect is caused by damage-enhanced electron trapping within the high-k bulk film. This trend is contrary to previously observed results in thicker SiO2/poly-gate transistors, where damage-enhanced hole trapping within SiO2 film is dominant [37]. Furthermore, based on the power-law relationship demonstrated in this study, the reliability data obtained from existing antenna test structures can be extrapolated to the transistors with any antenna ratios used in the circuitry.Figure 11
PBTI lifetimes as a function of AR for high-k/metal-gate NMOSFETs with EOTs of 2.0 nm and 1.5 nm, respectively.Figure 12
NBTI lifetime as a function of AR for high-k/meta-gate PMOSFETs with EOTs of 2.0 nm and 1.5 nm, and conventional SiO2/poly-gate PMOSFETs with an EOT of 3.0 nm, respectively.Figure10 also shows that C can be determined by the oxide conduction mechanism, and the antenna dependence m in   (6) can be significantly reduced  with larger C for transistors with a thinner EOT. Figures 2 and 3 show that a smaller Vst  and  Est dependence suggests that the plasma damage effects are mitigated for high-k/metal-gate transistors. As a result, Figures 11 and 12 show that high-k/metal-gate transistors exhibit smaller antenna ratio dependence than SiO2/poly-gate PMOSFETs with a similar physical dielectric thickness of approximately 3.0 nm. For example, SiO2/poly-gate PMOSFETs with an EOT of 3.0 nm exhibit the greatest plasma damage and the largest value of m (i.e., 0.3) among all samples. Furthermore, as the EOT of the high-k/metal-gate transistor decreases from 2.0 nm to 1.5 nm, Figures 2 and 3 show that the stress voltage can be reduced to the operation voltage or below. Thus, the stress electric field Est  becomes insignificant, which in turn produces a lower failure ratio of gate leakage and dielectric breakdown, as Figures  4 and 5 indicate. Moreover, for damage-enhanced transistor reliability degradation, the increasing C value eliminates the oxygen-related defects introduced within the high-k film. This suppresses the antenna dependence in reliability. Figures 11 and 12 show that large Creduces the antenna dependence of PBTI lifetime and NBTI lifetime until it becomes almost negligible. The models proposed in this study are consistent with experimental results  and further confirm that damage-enhanced transistor reliability degradation is alleviated for advanced high-k/metal gate CMOS technology that employs ultra thin high-k film with an EOT smaller than 1.5 nm.


## 3.1. Dielectric Degradation

### 3.1.1. Damage-Enhanced Dielectric  Degradation

Dielectric breakdown of high-k/metal-gate transistor is due to the clusters of disconnected bonds. These clusters propagate through the dielectric film  and finally reach the high-k/metal-gate interface. It is generally believed that defects existing in the dielectric layers can produce weak spots or trap centers that trap charges. During plasma processing, the damage current flowing through the gate dielectric can be viewed as an equivalent voltage stress, Vst, or electric field stress, Est, across the gate dielectric.   Vst or Est is able to generate lots of defects in high-k/metal gate transistors [16]. Moreover, these PID effects can aggravate the degradations of the dielectric layer owing to the extra damage current paths generated by the Vst across the dielectric layers during the plasma processing. To simplify the analysis of damage impacts during the wafer fabrication, the dependence of the damage effect on AR is introduced in terms of the plasma damage current Iplasma to simulate the damage characterization.  By assuming a fixed AR under a given plasma process, the term Iplasma can be considered as a constant current source of “damage current’’ that passes through the high-k/metal-gate electrode. As the AR increases, the total plasma current passing through the gate dielectric increases proportionally to AR. Figure 2 shows the dielectric current-voltage curves of PMOSFETs with different gate dielectric thicknesses and values of  AR.   Iplasma can be expressed as Iplasma=P·AR, where P is the plasma damage current collected when AR=1  (i.e., an antenna ratio of unity). The P value is assumed to be a constant under a given plasma processing and is expected to exhibit a process dependence due to changes in ion density, electron temperature, and so forth, as the plasma processing changes [17]. During plasma processing, dielectric breakdown occurs at plasma current density of approximately 2–20 A/cm2[18]. Thus, the experiments in this study assume that the P value is approximately 2×10-10 A with 1 μm2  transistors size (i.e., for the damaged structures with antenna ratio AR  = 100X,  Iplasma=2 A/cm2, and for structure with AR=1000X, Iplasma=20 A/cm2). Figure 2 depicts the dielectric current-voltage curves of PMOSFETs with different gate dielectric thicknesses for both high-k/metal-gates and SiO2/poly-gates. This figure also indicates the plasma damage current simulated for various AR. Comparing the plasma current-voltage with dielectric current-voltage characteristics, Iplasma corresponds to a voltage stress, Vst, on the gate electrode during plasma processing. Aggravated dielectric degradation from PID results in an increase in the effective stress voltage  Vst  across the gate dielectric during plasma processing. Clearly, Vst  not only depends on AR  but is also influenced by EOT. Figure 3 shows that the Est, defined as Vst/EOT, is a function of AR. A larger AR results in a larger Est  and therefore much more severe degradation in dielectric reliability for EOT ranging from 1.5 nm to 3.0 nm for both SiO2/poly-gate and high-k/metal-gate transistors.Figure 2
Characteristics of gate dielectric current and simulated plasma damage current with respect to voltage. The gate dielectric current curves are measured at various gate oxide thicknesses ranging from 1.5 nm to 3.0 nm for SiO2/poly-gate PMOSFETs  and EOT ranging from 1.5 nm to 2.0 nm for high-k/metal-gate PMOSFETs. This study simulates the plasma damage current for gate antenna ratios AR of 1X, 10X, 100X, and 1000X.Figure 3
Estimated electric field stress (Est) during plasma processing as a function of EOT for different AR. The inset shows the Est  as a function of AR for different EOTs.Moreover,Est strongly depends on EOT. For example, for SiO2/poly-gate transistors with a gate oxide thickness of 3.0 nm, the tunneling mechanism of plasma current passing through the dielectric can be dominated by Fowler-Nordheim (FN) tunneling, and  Est  exhibits a greater antenna dependence during plasma process. In contrast, when the EOT is reduced to  1.5~2.0 nm for both high-k/metal-gate and SiO2/poly-gate transistors, the tunneling mechanism shifts from Fowler-Nordheim tunneling to direct tunneling. This in turn produces a lower antenna dependence of Est compared to SiO2/poly-gate transistors with a gate oxide thickness of 3.0 nm.


### 3.1.2. Results for Damage-Enhanced Dielectric Degradation

Figure4 demonstrates   the failure ratios in terms of gate dielectric leakage current and breakdown voltage for a given AR of 5000X for both SiO2/poly-gate and high-k/metal-gate PMOSFETs with various EOTs. It is evident that SiO2/poly-gate transistors with a gate oxide thickness of 3.0 nm show significant gate oxide leakage distribution and a higher VBD failure ratio as the plasma current Iplasma  increases. Specifically, the failure ratios of gate dielectric leakage and  VBD  for SiO2/poly-gate MOSFETs with a gate oxide thickness of 3.0 nm increase by 26%. In contrast, for SiO2/poly-gate and high-k/metal-gate transistors with an EOT of approximately 1.5–2.0 nm, the oxide tunneling mechanism is dominated by direct tunneling. This in turn produces a smaller stress voltage Vst, on the gate electrode stacks during plasma process. Figure 4 shows that the failure ratio of gate dielectric leakage and  VBD degradation can be reduced to less than 6% by decreasing the EOT to below 2.0 nm.       In addition, Figure 5 demonstrates the dependence between failure ratios of gate leakage current and transistors’ EOTs ranging from 1.5 nm to 3.0 nm with different ARs of 100X, 500X, and 5000X. By reducing the EOT from 3.0 nm to 1.5 nm, the dielectric failure ratio of the antenna transistors connected to AR = 500X  can be decreased from 12% to nil, and the failure ratio of the transistors connected to AR = 5000X  can be further reduced to from 26% to 2%,  as Figure 5 indicates. These results confirm that the  Est   is linearly dependent on EOT  and can be decreased by reducing EOT from 3.0 nm to 1.5 nm as well as changing the test structure from SiO2/poly-gate to high-k/metal-gate transistors. In addition, the EOT dependence of damage-enhanced gate dielectric degradation is irrespective of the AR. The results of Figures 4 and 5 are consistent with the damage models proposed in this study and shown in Figures 2 and 3.  Clearly, a transistor with an EOT of approximately 3.0 nm shows a strong AR dependence of Est. Further, PID impact on gate dielectric degradation of high-k/metal-gate transistor is determined by EOT, rather than physical thickness. This study confirms that the strong dependence of dielectric EOT causes significant damage to the input/output transistors with a thicker EOT of approximately 3.0 nm both for high-k/metal-gate and SiO2/poly-gate transistors. Therefore, high-k/metal-gate transistors with a thinner EOT would be robust for PID, because damage-induced dielectric degradation is not a serious issue for the thinner gate dielectric high-k/metal-gate transistors needed to support the operation voltage in the core circuit design.Figure 4
Failure probability of gate dielectric leakage measured on PMOSFETs with EOTs ranging from 1.5 nm to 3.0 nm for SiO2/poly-gate transistors  and EOTs ranging from 1.5 nm to 2.0 nm for high-k/metal-gate PMOSFETs. The inset is the failure probability of VBD measured for the above transistors with EOTs greater than 2.0 nm. The AR attached to these transistors is 5000X.Figure 5
Failure percentages of gate leakage current as a function of EOT for both high-k/metal-gate and conventional SiO2/poly-gate PMOSFETs with EOTs ranging from 1.5 nm to 3.0 nm with ARs of 100X, 500X, and 5000X.


## 3.1.1. Damage-Enhanced Dielectric  Degradation

Dielectric breakdown of high-k/metal-gate transistor is due to the clusters of disconnected bonds. These clusters propagate through the dielectric film  and finally reach the high-k/metal-gate interface. It is generally believed that defects existing in the dielectric layers can produce weak spots or trap centers that trap charges. During plasma processing, the damage current flowing through the gate dielectric can be viewed as an equivalent voltage stress, Vst, or electric field stress, Est, across the gate dielectric.   Vst or Est is able to generate lots of defects in high-k/metal gate transistors [16]. Moreover, these PID effects can aggravate the degradations of the dielectric layer owing to the extra damage current paths generated by the Vst across the dielectric layers during the plasma processing. To simplify the analysis of damage impacts during the wafer fabrication, the dependence of the damage effect on AR is introduced in terms of the plasma damage current Iplasma to simulate the damage characterization.  By assuming a fixed AR under a given plasma process, the term Iplasma can be considered as a constant current source of “damage current’’ that passes through the high-k/metal-gate electrode. As the AR increases, the total plasma current passing through the gate dielectric increases proportionally to AR. Figure 2 shows the dielectric current-voltage curves of PMOSFETs with different gate dielectric thicknesses and values of  AR.   Iplasma can be expressed as Iplasma=P·AR, where P is the plasma damage current collected when AR=1  (i.e., an antenna ratio of unity). The P value is assumed to be a constant under a given plasma processing and is expected to exhibit a process dependence due to changes in ion density, electron temperature, and so forth, as the plasma processing changes [17]. During plasma processing, dielectric breakdown occurs at plasma current density of approximately 2–20 A/cm2[18]. Thus, the experiments in this study assume that the P value is approximately 2×10-10 A with 1 μm2  transistors size (i.e., for the damaged structures with antenna ratio AR  = 100X,  Iplasma=2 A/cm2, and for structure with AR=1000X, Iplasma=20 A/cm2). Figure 2 depicts the dielectric current-voltage curves of PMOSFETs with different gate dielectric thicknesses for both high-k/metal-gates and SiO2/poly-gates. This figure also indicates the plasma damage current simulated for various AR. Comparing the plasma current-voltage with dielectric current-voltage characteristics, Iplasma corresponds to a voltage stress, Vst, on the gate electrode during plasma processing. Aggravated dielectric degradation from PID results in an increase in the effective stress voltage  Vst  across the gate dielectric during plasma processing. Clearly, Vst  not only depends on AR  but is also influenced by EOT. Figure 3 shows that the Est, defined as Vst/EOT, is a function of AR. A larger AR results in a larger Est  and therefore much more severe degradation in dielectric reliability for EOT ranging from 1.5 nm to 3.0 nm for both SiO2/poly-gate and high-k/metal-gate transistors.Figure 2
Characteristics of gate dielectric current and simulated plasma damage current with respect to voltage. The gate dielectric current curves are measured at various gate oxide thicknesses ranging from 1.5 nm to 3.0 nm for SiO2/poly-gate PMOSFETs  and EOT ranging from 1.5 nm to 2.0 nm for high-k/metal-gate PMOSFETs. This study simulates the plasma damage current for gate antenna ratios AR of 1X, 10X, 100X, and 1000X.Figure 3
Estimated electric field stress (Est) during plasma processing as a function of EOT for different AR. The inset shows the Est  as a function of AR for different EOTs.Moreover,Est strongly depends on EOT. For example, for SiO2/poly-gate transistors with a gate oxide thickness of 3.0 nm, the tunneling mechanism of plasma current passing through the dielectric can be dominated by Fowler-Nordheim (FN) tunneling, and  Est  exhibits a greater antenna dependence during plasma process. In contrast, when the EOT is reduced to  1.5~2.0 nm for both high-k/metal-gate and SiO2/poly-gate transistors, the tunneling mechanism shifts from Fowler-Nordheim tunneling to direct tunneling. This in turn produces a lower antenna dependence of Est compared to SiO2/poly-gate transistors with a gate oxide thickness of 3.0 nm.


## 3.1.2. Results for Damage-Enhanced Dielectric Degradation

Figure4 demonstrates   the failure ratios in terms of gate dielectric leakage current and breakdown voltage for a given AR of 5000X for both SiO2/poly-gate and high-k/metal-gate PMOSFETs with various EOTs. It is evident that SiO2/poly-gate transistors with a gate oxide thickness of 3.0 nm show significant gate oxide leakage distribution and a higher VBD failure ratio as the plasma current Iplasma  increases. Specifically, the failure ratios of gate dielectric leakage and  VBD  for SiO2/poly-gate MOSFETs with a gate oxide thickness of 3.0 nm increase by 26%. In contrast, for SiO2/poly-gate and high-k/metal-gate transistors with an EOT of approximately 1.5–2.0 nm, the oxide tunneling mechanism is dominated by direct tunneling. This in turn produces a smaller stress voltage Vst, on the gate electrode stacks during plasma process. Figure 4 shows that the failure ratio of gate dielectric leakage and  VBD degradation can be reduced to less than 6% by decreasing the EOT to below 2.0 nm.       In addition, Figure 5 demonstrates the dependence between failure ratios of gate leakage current and transistors’ EOTs ranging from 1.5 nm to 3.0 nm with different ARs of 100X, 500X, and 5000X. By reducing the EOT from 3.0 nm to 1.5 nm, the dielectric failure ratio of the antenna transistors connected to AR = 500X  can be decreased from 12% to nil, and the failure ratio of the transistors connected to AR = 5000X  can be further reduced to from 26% to 2%,  as Figure 5 indicates. These results confirm that the  Est   is linearly dependent on EOT  and can be decreased by reducing EOT from 3.0 nm to 1.5 nm as well as changing the test structure from SiO2/poly-gate to high-k/metal-gate transistors. In addition, the EOT dependence of damage-enhanced gate dielectric degradation is irrespective of the AR. The results of Figures 4 and 5 are consistent with the damage models proposed in this study and shown in Figures 2 and 3.  Clearly, a transistor with an EOT of approximately 3.0 nm shows a strong AR dependence of Est. Further, PID impact on gate dielectric degradation of high-k/metal-gate transistor is determined by EOT, rather than physical thickness. This study confirms that the strong dependence of dielectric EOT causes significant damage to the input/output transistors with a thicker EOT of approximately 3.0 nm both for high-k/metal-gate and SiO2/poly-gate transistors. Therefore, high-k/metal-gate transistors with a thinner EOT would be robust for PID, because damage-induced dielectric degradation is not a serious issue for the thinner gate dielectric high-k/metal-gate transistors needed to support the operation voltage in the core circuit design.Figure 4
Failure probability of gate dielectric leakage measured on PMOSFETs with EOTs ranging from 1.5 nm to 3.0 nm for SiO2/poly-gate transistors  and EOTs ranging from 1.5 nm to 2.0 nm for high-k/metal-gate PMOSFETs. The inset is the failure probability of VBD measured for the above transistors with EOTs greater than 2.0 nm. The AR attached to these transistors is 5000X.Figure 5
Failure percentages of gate leakage current as a function of EOT for both high-k/metal-gate and conventional SiO2/poly-gate PMOSFETs with EOTs ranging from 1.5 nm to 3.0 nm with ARs of 100X, 500X, and 5000X.


## 3.2. Damage-Enhanced Threshold Voltage Instability for High-k/Metal-Gate MOSFETs

### 3.2.1. Damage-Enhanced PBTI Degradations for High-k/Metal-Gate NMOSFETs

The results in Figure4 show  that plasma-induced damage is usually evaluated by monitoring the gate dielectric leakage current  [19]   or breakdown voltage [20] with a given antenna ratio attached to the gate electrode. The occurrence of additional gate oxide leakage implies the existence of additional current paths within the gate dielectric layers. However, prior to the formation of a conductive path within the dielectric layers, sufficient damage (i.e., defects and traps) would have been accumulated to degrade transistor reliability [21]. In other words, the degradation of transistor reliability occurs before the gate leakage increases. Because the difference in PID-induced gate leakage current between damaged and undamaged transistors is small compared with the gate tunneling current, the conventional methods (i.e., monitor the increase of gate leakage current with applying high electric filed) may fail to detect PID, especially for transistors fabricated with a thinner EOT. Previous study shows that providing a constant voltage stress (CVS) on the gate electrode after wafer processing  and the traps created during plasma process can be revealed in the dielectric layers [22]. These traps can act as sites for assisting the electron tunneling from substrate to gate electrode (i.e., trap-assisted tunneling effect) resulting in an increase in the gate dielectric leakage, as shown in Figure 6. Moreover, the energy level of the traps can be calculated from the curve of stress-induced gate leakage current (i.e., SILC) by monitoring how the peak of the increase of SILC responds to the gate voltage [23]. This result indicates that the PID preferentially degrades the high-k film or the interfacial layer. Figure 6 shows that damaged high-k/metal gate transistor exhibits an obvious and significant increase of SILC with a peak at around Vg=0.9~1.0 V. The results are consistent with high-voltage stress on transistor’s well  causing substrate hot electron injection and generating defects in high-k film [23, 24]. Furthermore, based on previous studies [25, 26], it has been proposed that the charge state of oxygen vacancies could describe the energy signature of these traps and is responsible for the increase in SILC.Figure 6
The increase of SILC as a function of gate voltage sensed from-1.5 V to 1.5 V for a damaged and an undamaged high-k/metal-gate NMOSFET. The inset illustrates trap-assisted electron tunneling through high-k film for a damaged high-k/metal-gate NMOSFET.This study assumes that the PID effects in the gate dielectric of high-k/metal-gate transistors are similar to those caused by gate voltage stress,  Vst. Moreover, during the plasma process, the damage current flux  Iplasma breaks the weak Hf-based dielectric bonds, generating oxygen-vacancy-related defects (Od) in the high-k film. Note that the oxygen-vacancy-related defect bonds are located below the conduction band of the Hf-based dielectric, and oxygen vacancies,  Vo++,  are produced from the following reaction: Od→ Vo++ + 2e- + 1/2O2  [27, 28]. The oxygen-vacancy-related defects might not be evident after the plasma processing because the postmetallization annealing process passivates them [29]. However, further electrical stress, such as PBTI and NBTI, reveals their existence.Under plasma charging, a largeEst  stress on high-k film creates many oxygen-vacancy-related defects and oxygen vacancies within the high-k film. Applying PBTI stress to high-k/metal-gate NMOSFETs causes electrons in the inversion layer to gain sufficient energy to be injected into the dielectric layers. As a result, electrons are easily trapped in the oxygen vacancies within the high-k film [11, 21]. Figure 7 shows that all NMOSFETs (both damaged and undamaged transistors) exhibit PBTI degradations: however, the damaged transistors are likely to have a higher number of oxygen vacancies as evidenced by the larger ΔVTH  shift in the time dependence of threshold voltage instability. Figure 7 depicts the PBTI dependence of high-k/metal-gate NMOSFETs with an EOT of 2.0 nm for a damaged transistor with an AR of 10000X and an undamaged transistor with an AR of 3X. This figure shows that the damaged transistors exhibit larger ΔVTH shift than the undamaged transistors as the stress time progresses. Specifically, after 1000 seconds of PBTI stress, the ΔVTH  shift is only around 85 mV for the undamaged transistors, but nearly 100 mV for the damaged transistors. This is because the damage induces an increase in oxygen-vacancy-related defects, then electrons are captured in oxygen vacancies during PBTI stress. The increased degradation exhibited by damaged transistors shown in this study is consistent with the PBTI physical models demonstrated in previous literatures [11, 25, 26].Figure 7
PBTI-inducedΔVTH shift as a function of stress time for damaged and undamaged high-k/metal-gate NMOSFETs. The inset illustrates the mechanism difference between damaged and undamaged transistors during PBTI stress.


### 3.2.2. Damage-Enhanced NBTI Degradations for High-k/Metal-Gate PMOSFETs

For high-k/metal-gate PMOSFETs experiencing NBTI stress, holes in the inversion layer gain sufficient energy to dissociate the weak Si–H bonds. This in turn generates interface states with holes (positive charges) trapping at the SiO2/Si-substrate interface [10]. Figure 8 shows that many oxygen-related defects and oxygen vacancies exist in the high-k film, and electrons injected from the metal-gate are captured by oxygen vacancies Vo++. Furthermore, the damaged transistors show less degradation because these transistors have higher concentrations of electron trapping (i.e., negative charges) in the high-k film, which mitigates the ΔVTH  shift of hole trapping (i.e., positive charge) during NBTI stress. Figure 8 depicts the ΔVTH   shift as a function of NBTI stress time for damaged and undamaged high-k/metal-gate PMOSFETs with an EOT of 2.0 nm. This figure shows that the damaged transistors exhibit less threshold voltage shift ΔVTH than the undamaged transistors as the stress time progresses. Specifically, after 1000 seconds of NBTI stress, the ΔVTH   shift is about 30 mV for the undamaged transistors, but only 25 mV for the damaged transistors.Figure 8
NBTI-inducedΔVTH  shift as a function of stress time for damaged and undamaged high-k/metal-gate PMOSFETs. The inset illustrates the difference between damaged and undamaged transistors during NBTI stress.To verify the NBTI models proposed in this study, current separation measurements were carried out after NBTI stress (Vg=-2 V, 1000 seconds). Figure 9 shows that after NBTI stress, the injected holes are monitored by the drain (source) current, while electrons are monitored by the substrate current. Further, to investigate the electron capturing effect, this study examined both high-k/metal-gate transistors and SiO2/Poly-gate PMOSFETs with an EOT of 2.0 nm. Figure 9 shows the ratio of electron current (Ie) over the total current (i.e., hole current (Ih) + electron (Ie)) as a function of the sweeping gate voltage. This figure shows that the damaged high-k/metal-gate transistor depicts the greatest ratio of Ie/(Ie + Ih) in all experiments. This suggests that, unlike the conventional SiO2/poly-gate PMOSFETs, the damage-induced electron trapping in the high-k film plays an important role in the NBTI characteristics of high-k/metal-gate PMOSFETs, as Figure 8 indicates. This is consistent with the damage model proposed in this study. In summary, the results of Figures  6–9 show that the transient nature of the damage-enhanced electron trapping in high-k film affects the NMOFETs’ PBTI and PMOSFETs’ NBTI performance in advanced high-k/metal-gate CMOS technology.Figure 9
The ratios of Ie/(Ie + Ih) as a function of sweeping gate voltage for damaged and undamaged PMOSFETs fabricated with high-k/metal-gate and conventional SiO2/poly-gate after NBTI stress (i.e., Vg=-2 V, and 1000 seconds). The inset illustrates the current separation method to identify the injection carriers within the gate dielectric.


## 3.2.1. Damage-Enhanced PBTI Degradations for High-k/Metal-Gate NMOSFETs

The results in Figure4 show  that plasma-induced damage is usually evaluated by monitoring the gate dielectric leakage current  [19]   or breakdown voltage [20] with a given antenna ratio attached to the gate electrode. The occurrence of additional gate oxide leakage implies the existence of additional current paths within the gate dielectric layers. However, prior to the formation of a conductive path within the dielectric layers, sufficient damage (i.e., defects and traps) would have been accumulated to degrade transistor reliability [21]. In other words, the degradation of transistor reliability occurs before the gate leakage increases. Because the difference in PID-induced gate leakage current between damaged and undamaged transistors is small compared with the gate tunneling current, the conventional methods (i.e., monitor the increase of gate leakage current with applying high electric filed) may fail to detect PID, especially for transistors fabricated with a thinner EOT. Previous study shows that providing a constant voltage stress (CVS) on the gate electrode after wafer processing  and the traps created during plasma process can be revealed in the dielectric layers [22]. These traps can act as sites for assisting the electron tunneling from substrate to gate electrode (i.e., trap-assisted tunneling effect) resulting in an increase in the gate dielectric leakage, as shown in Figure 6. Moreover, the energy level of the traps can be calculated from the curve of stress-induced gate leakage current (i.e., SILC) by monitoring how the peak of the increase of SILC responds to the gate voltage [23]. This result indicates that the PID preferentially degrades the high-k film or the interfacial layer. Figure 6 shows that damaged high-k/metal gate transistor exhibits an obvious and significant increase of SILC with a peak at around Vg=0.9~1.0 V. The results are consistent with high-voltage stress on transistor’s well  causing substrate hot electron injection and generating defects in high-k film [23, 24]. Furthermore, based on previous studies [25, 26], it has been proposed that the charge state of oxygen vacancies could describe the energy signature of these traps and is responsible for the increase in SILC.Figure 6
The increase of SILC as a function of gate voltage sensed from-1.5 V to 1.5 V for a damaged and an undamaged high-k/metal-gate NMOSFET. The inset illustrates trap-assisted electron tunneling through high-k film for a damaged high-k/metal-gate NMOSFET.This study assumes that the PID effects in the gate dielectric of high-k/metal-gate transistors are similar to those caused by gate voltage stress,  Vst. Moreover, during the plasma process, the damage current flux  Iplasma breaks the weak Hf-based dielectric bonds, generating oxygen-vacancy-related defects (Od) in the high-k film. Note that the oxygen-vacancy-related defect bonds are located below the conduction band of the Hf-based dielectric, and oxygen vacancies,  Vo++,  are produced from the following reaction: Od→ Vo++ + 2e- + 1/2O2  [27, 28]. The oxygen-vacancy-related defects might not be evident after the plasma processing because the postmetallization annealing process passivates them [29]. However, further electrical stress, such as PBTI and NBTI, reveals their existence.Under plasma charging, a largeEst  stress on high-k film creates many oxygen-vacancy-related defects and oxygen vacancies within the high-k film. Applying PBTI stress to high-k/metal-gate NMOSFETs causes electrons in the inversion layer to gain sufficient energy to be injected into the dielectric layers. As a result, electrons are easily trapped in the oxygen vacancies within the high-k film [11, 21]. Figure 7 shows that all NMOSFETs (both damaged and undamaged transistors) exhibit PBTI degradations: however, the damaged transistors are likely to have a higher number of oxygen vacancies as evidenced by the larger ΔVTH  shift in the time dependence of threshold voltage instability. Figure 7 depicts the PBTI dependence of high-k/metal-gate NMOSFETs with an EOT of 2.0 nm for a damaged transistor with an AR of 10000X and an undamaged transistor with an AR of 3X. This figure shows that the damaged transistors exhibit larger ΔVTH shift than the undamaged transistors as the stress time progresses. Specifically, after 1000 seconds of PBTI stress, the ΔVTH  shift is only around 85 mV for the undamaged transistors, but nearly 100 mV for the damaged transistors. This is because the damage induces an increase in oxygen-vacancy-related defects, then electrons are captured in oxygen vacancies during PBTI stress. The increased degradation exhibited by damaged transistors shown in this study is consistent with the PBTI physical models demonstrated in previous literatures [11, 25, 26].Figure 7
PBTI-inducedΔVTH shift as a function of stress time for damaged and undamaged high-k/metal-gate NMOSFETs. The inset illustrates the mechanism difference between damaged and undamaged transistors during PBTI stress.


## 3.2.2. Damage-Enhanced NBTI Degradations for High-k/Metal-Gate PMOSFETs

For high-k/metal-gate PMOSFETs experiencing NBTI stress, holes in the inversion layer gain sufficient energy to dissociate the weak Si–H bonds. This in turn generates interface states with holes (positive charges) trapping at the SiO2/Si-substrate interface [10]. Figure 8 shows that many oxygen-related defects and oxygen vacancies exist in the high-k film, and electrons injected from the metal-gate are captured by oxygen vacancies Vo++. Furthermore, the damaged transistors show less degradation because these transistors have higher concentrations of electron trapping (i.e., negative charges) in the high-k film, which mitigates the ΔVTH  shift of hole trapping (i.e., positive charge) during NBTI stress. Figure 8 depicts the ΔVTH   shift as a function of NBTI stress time for damaged and undamaged high-k/metal-gate PMOSFETs with an EOT of 2.0 nm. This figure shows that the damaged transistors exhibit less threshold voltage shift ΔVTH than the undamaged transistors as the stress time progresses. Specifically, after 1000 seconds of NBTI stress, the ΔVTH   shift is about 30 mV for the undamaged transistors, but only 25 mV for the damaged transistors.Figure 8
NBTI-inducedΔVTH  shift as a function of stress time for damaged and undamaged high-k/metal-gate PMOSFETs. The inset illustrates the difference between damaged and undamaged transistors during NBTI stress.To verify the NBTI models proposed in this study, current separation measurements were carried out after NBTI stress (Vg=-2 V, 1000 seconds). Figure 9 shows that after NBTI stress, the injected holes are monitored by the drain (source) current, while electrons are monitored by the substrate current. Further, to investigate the electron capturing effect, this study examined both high-k/metal-gate transistors and SiO2/Poly-gate PMOSFETs with an EOT of 2.0 nm. Figure 9 shows the ratio of electron current (Ie) over the total current (i.e., hole current (Ih) + electron (Ie)) as a function of the sweeping gate voltage. This figure shows that the damaged high-k/metal-gate transistor depicts the greatest ratio of Ie/(Ie + Ih) in all experiments. This suggests that, unlike the conventional SiO2/poly-gate PMOSFETs, the damage-induced electron trapping in the high-k film plays an important role in the NBTI characteristics of high-k/metal-gate PMOSFETs, as Figure 8 indicates. This is consistent with the damage model proposed in this study. In summary, the results of Figures  6–9 show that the transient nature of the damage-enhanced electron trapping in high-k film affects the NMOFETs’ PBTI and PMOSFETs’ NBTI performance in advanced high-k/metal-gate CMOS technology.Figure 9
The ratios of Ie/(Ie + Ih) as a function of sweeping gate voltage for damaged and undamaged PMOSFETs fabricated with high-k/metal-gate and conventional SiO2/poly-gate after NBTI stress (i.e., Vg=-2 V, and 1000 seconds). The inset illustrates the current separation method to identify the injection carriers within the gate dielectric.


## 3.3. The Model of Damage-Enhanced Instability for High-k/Metal-Gate MOSFETs Reliability

Figure10 compares the plasma damage with gate dielectric current-voltage characteristics for a high-k/metal NMOSFET with EOT = 2.0 nm, showing that Iplasma  corresponds to a voltage stress, Vst, on the transistor gate dielectric during processing. Instability of PBTI and NBTI resulting from PID therefore represents an increase in the effective stress voltage  ΔVst  across the gate dielectric during plasma processing. Furthermore, the relationship between AR and  ΔVst  can be expressed asFigure 10
The characteristics of measured dielectric current and simulated damage current as a function of voltage for various AR for high-k/metal-gate NMOSFETs with an EOT of 2.0 nm.(2)ln(AR)=CΔVst,
where C is the slope of the gate dielectric current-voltage characteristics in Figure 10  and is strongly dependent on the EOT, as Figure 2 indicates. During the plasma processing, defects or traps are generated when the damage-induced  Vst  or  Est  breaks the dipoles within the dielectric [30, 31]. Several previous studies have shown that the increase of defects or traps could be a function of voltage stress [32], and these studies depict an exponential relationship between trap generation and electric field stress across the gate dielectric [33, 34]. Thus, during the plasma process, an increase in the density of oxygen-vacancy-related traps within the high-k dielectric, ΔNOV, from the gate stress can be written as an increase of voltage  stress ΔVst  as(3)ΔNOV=Aexp(γpΔEst)=Aexp(γpΔVstEOT),
where A is a constant and γp is the electric field acceleration factor. Both of these terms are dependent on the plasma process and γp  is approximately 0.1~0.2  (Dec-cm/MV) for plasma processing [35].During PBTI or NBTI stress, the  model proposed in this study shows that the injected electrons which are trapped in oxygen vacancies cause an increase in the negative charge and instability in the transistor threshold voltage. All transistors, irrespective of their antenna ratio, exhibitΔVTH  shift under PBTI or NBTI stress. However, transistors with larger AR have higher concentrations of negative charge trapped within the high-k layer. For a constant EOT, the ΔVTH  instability resulting from the increase of negative charge trapped for antenna transistor can be modeled as(4)ΔVTH=HtnARα,
wheret is the duration of the NBTI or PBTI stress, n is approximately 0.16 for both NBTI and PBTI [36], and H is a constant. The parameter α can be expressed   as(5)α=γpEOT·C.
Note  that  α  for PBTI stress is positive (i.e., ΔVTH  increases with AR), while αfor NBTI stress is negative (i.e., ΔVTH decreases with AR). The failure time  tf, defined as the time required to reach the critical threshold voltage increase ΔVthc, is(6)tf=GΔVcAR-m,
where G is a constant for a given process,  ΔVC=(ΔVthc)1/n, and m =α/n.


## 3.4. The Effects of EOT on the Damage-Enhanced Instability for High-k/Metal-Gate MOSFETs Reliability

Figures11 and 12 plot the PBTI lifetime and NBTI lifetimes, respectively, as a function of antenna ratio for high-k/metal-gate transistors with an EOT of 2.0 nm. These figures indicate that the antenna dependence m follows the power-law relationship, consistent with   (6). Figure 11 shows the antenna dependence m is 0.07 for NMOSFETs’ PBTI lifetime. However, Figure 12 indicates a larger m of 0.15 for PMOSFETs’ NBTI lifetime. The difference in the antenna dependence is caused by the difference of dielectric current-voltage characteristics. For a plasma process with a given Iplasma, PMOSFETs experience a higher stress-voltage that leads to a higher oxygen vacancy generation rate than NMOSFETs. In addition, Figure 12 demonstrates a “reverse antenna effect’’ (i.e., the NBTI lifetime increases with AR) for high-k/metal-gate PMOSFETs. This effect is caused by damage-enhanced electron trapping within the high-k bulk film. This trend is contrary to previously observed results in thicker SiO2/poly-gate transistors, where damage-enhanced hole trapping within SiO2 film is dominant [37]. Furthermore, based on the power-law relationship demonstrated in this study, the reliability data obtained from existing antenna test structures can be extrapolated to the transistors with any antenna ratios used in the circuitry.Figure 11
PBTI lifetimes as a function of AR for high-k/metal-gate NMOSFETs with EOTs of 2.0 nm and 1.5 nm, respectively.Figure 12
NBTI lifetime as a function of AR for high-k/meta-gate PMOSFETs with EOTs of 2.0 nm and 1.5 nm, and conventional SiO2/poly-gate PMOSFETs with an EOT of 3.0 nm, respectively.Figure10 also shows that C can be determined by the oxide conduction mechanism, and the antenna dependence m in   (6) can be significantly reduced  with larger C for transistors with a thinner EOT. Figures 2 and 3 show that a smaller Vst  and  Est dependence suggests that the plasma damage effects are mitigated for high-k/metal-gate transistors. As a result, Figures 11 and 12 show that high-k/metal-gate transistors exhibit smaller antenna ratio dependence than SiO2/poly-gate PMOSFETs with a similar physical dielectric thickness of approximately 3.0 nm. For example, SiO2/poly-gate PMOSFETs with an EOT of 3.0 nm exhibit the greatest plasma damage and the largest value of m (i.e., 0.3) among all samples. Furthermore, as the EOT of the high-k/metal-gate transistor decreases from 2.0 nm to 1.5 nm, Figures 2 and 3 show that the stress voltage can be reduced to the operation voltage or below. Thus, the stress electric field Est  becomes insignificant, which in turn produces a lower failure ratio of gate leakage and dielectric breakdown, as Figures  4 and 5 indicate. Moreover, for damage-enhanced transistor reliability degradation, the increasing C value eliminates the oxygen-related defects introduced within the high-k film. This suppresses the antenna dependence in reliability. Figures 11 and 12 show that large Creduces the antenna dependence of PBTI lifetime and NBTI lifetime until it becomes almost negligible. The models proposed in this study are consistent with experimental results  and further confirm that damage-enhanced transistor reliability degradation is alleviated for advanced high-k/metal gate CMOS technology that employs ultra thin high-k film with an EOT smaller than 1.5 nm.


## 4. Conclusions

For both SiO2/poly-gate and high-k/metal-gate transistors, plasma-induced charging damage creates many defects and weakened interface bonds that can be easily damaged during reliability testing. Importantly, for high-k/metal-gate transistors, the damage current breaks the bonds of Hf-based dielectric and produces more oxygen vacancies to enhance the instability of NBTI and PBTI. This study develops a comprehensive model of the impact of plasma damage  and shows that the dielectric degradation and transistor instability are strongly dependent on the EOT and antenna ratio. Reducing the EOT suppresses the gate dielectric degradation, and the damage becomes minor when the EOT is smaller than 2.0 nm. In addition, the damage becomes negligible when the EOT is smaller than 1.5 nm. This study also discusses the power-law relationship between antenna ratio and transistor PBTI lifetime and NBTI lifetime. Furthermore, NBTI degradations for PMOSFETs can be mitigated with damaged-enhanced electron trapping in oxygen vacancy during NBTI stress, showing a “reverse antenna effect.” In summary, this study demonstrates that plasma-induced damage can be alleviated for advanced high-k/metal gate CMOS transistors fabricated with thin dielectric thickness.



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*Source: 308949-2009-12-14.xml*