# A Low-Power Voltage Limiter/Regulator IC in Standard Thick-Oxide 130 nm CMOS for Inductive Power Transfer Application

Authors: Stepan Lapshev; S. M. Rezaul Hasan
Journal: Advances in Power Electronics
 (2014)

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## Abstract

This paper presents a novel CMOS low-power voltage limiter/regulator circuit with hysteresis for inductive power transfer in an implanted telemetry application. The circuit controls its rail voltage to the maximum value of 3 V DC employing 100 mV of comparator hysteresis. It occupies a silicon area of only 127µm × 125 µm using the 130 nm IBM CMOS process. In addition, the circuit dissipated less than 1 mW and was designed using thick-oxide 3.6 V NMOS and PMOS devices available in the process library.


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## Body

## 1. Introduction and Circuit Description

Wireless inductive transfer of power across air gaps between loosely coupled inductors is of significant interest in remote pickup and telemetry. Voltage control using a limiter/regulator is an essential component of such a system. Also, hysteretic voltage control devices are frequently used in power converters [1, 2]. This paper discusses the design, fabrication, and testing of a hysteretic inductive power limiter/regulator for application in implantable telemetry devices. The schematic diagram of the overall wireless power transfer circuit is shown in Figure 1 with the proposed novel CMOS limiter bounded by the rectangular box. The purpose of the implemented integrated circuit is to control its inductively generated rectified rail-to-rail voltage attained through the wireless power transfer. The current induced on the wireless pickup coil is rectified using the Schottky diode bridge. The rectified current charges a capacitor (power supply capacitor) connected to the load. The voltages on the positive and negative sides of this capacitor are V
DD and V
SS, respectively, which also forms the rail voltages of the limiter/regulator. The integrated circuit limiter controls the V
DD voltage by periodically shorting both sides (terminals) of the pickup coil to the negative terminal of the capacitor (V
SS rail) using triode regime MOSFET switches. The MOSFET switches are driven by a novel hysteresis comparator. The maximum value of the controlled voltage is limited to 3 V by employing 100 mV of comparator hysteresis and a suitable reference voltage, V
ref. The comparator output is sufficiently buffered to drive the large shorting switches with reasonably small turn-on and turn-off delays. A capacitor is used at the noninverting terminal for shorting any spurious signal pickups. All transistor size values in all the figures are provided in micrometers. The top number and the bottom number adjacent to the transistors, respectively, denote the values for the channel width and the channel length.Figure 1
Schematic diagram of the overall circuit. The enclosed schematic is the integrated novel CMOS limiter circuit on a chip.Other power circuit components external to the limiter/regulator IC in Figure1 include inductive power transfer coils, L
S and L
P with 2 : 1 turns ratio, as well as a 22 μF power supply capacitor, C
L, across the variable load (with a nominal value of around 150 Ω). The power transferred depends on the mutual coupling factor, k, between the coils which varies with the air gap separation between the coils. In order to ensure maximum magnetic flux transition, the power transfer coils are terminated with parallel capacitors for LC resonance at a specified power transfer line frequency. The line frequency of power transfer was designed to be variable between 40 kHz and 600 kHz for the specific telemetry application. The primary coil is excited by a variable frequency sinusoidal oscillator using a 5 V DC supply. However, the induced input voltage at the secondary power transfer coil can vary considerably due to the possible orders of magnitude variation in the mutual coupling between the coils depending on their separation.


## 2. IC Design and Simulation

The limiter/regulator IC was designed and simulated on Mentor Graphics platform using the 130 nm IBM CMOS process technology. MOSFET devices with thick gate oxide were used throughout the design. These devices are able to operate with voltages up to 3.6 V. Simulation indicates that the power dissipation of the limiter/regulator IC is less than 1 mW.


### 2.1. Voltage Reference Circuit

The supply-independent voltage reference circuit as described in [3] was redesigned using the thick-oxide devices available in the 130 nm CMOS process to generate the suitably selected reference voltage V
ref
=
1.236
V. The schematic diagram of this implemented circuit is shown in Figure 2. Temperature independence is not required in this case, since the device is designed for implanted telemetry application, whereby its temperature will be equal to the body temperature. In addition, no start-up circuit is required for this reference circuit. Initially, the output voltage is equal to 0, which is set by C
3, and M
15 is off. The voltage at the gate of M
16 is also close to 0 and M
16 is off. What makes the circuit go out of this state is that the channels of M
15 and M
13 act as resistances. Since M
15 is 4 times wider than M
13 and the charge-carrier (electron) mobility in NMOS (M
15) is higher (by around 2.5 times) compared to hole mobility in PMOS (M
13) [4], the channel of M
15 has a smaller resistance than that of M
13. In this way, the voltage at the drain of M
13 and the gate of M
14 hovers toward 0 and M
14 turns on, which starts up the circuit. Figure 3(a) shows the simulated voltage reference signal V
ref with respect to the positive rail voltage V
DD. Supply-independence of V
ref can be clearly noticed after start-up. The charging to the supply rail voltage V
DD using a power supply capacitor, C
L, of 22 μF and 12 μF is shown, respectively, in Figures 3(a) and 3(b).Figure 2
Voltage reference circuit using thick-oxide 3.6 V MOSFET devices.Simulated start-up voltage signals: (a) the comparator input reference voltageV
ref and charging-to-rail voltage V
DD using a 22 μF power supply capacitor and (b) charging-to-rail voltage V
DD using a 12 μF power supply capacitor.
(a)
(b)


### 2.2. Comparator Circuit

The comparator is a three-stage single-ended differential amplifier. Its schematic diagram is shown in Figure4. The first stage is a single-ended differential pair with active current mirror load. The second stage is a PMOS common source amplifier with an NMOS current-source load. The third stage is a push-pull inverter amplifier. The NMOS current-source bias voltage V
bias for the tail current of the differential input stage and the NMOS load is generated by the diode-connected device M
8 and resistor R
4.Figure 4
Schematic diagram of the comparator circuit.Since there is positive feedback through the 400 K resistor in the overall circuit shown in Figure1, this is a closed loop amplifier system. Internal frequency compensation was thus employed within the comparator circuit using the series connection of C
2 and R
5 as shown in Figure 4 between two high impedance nodes. This arrangement provides enhanced Miller compensation through the use of the series connected resistance R
5.


### 2.3. Switching Levels

The negative terminal input to the comparator is the reference voltageV
ref, and the positive terminal input is the output from the composite voltage divider consisting of the resistors R
1, R
2, and R
3 with values of 14 K, 10 K, and 400 K, respectively. The hysteresis is implemented through novel use of the 400 K R
3 resistor: when the comparator’s output voltage is V
DD, the 400 K resistor is in parallel with the 14 K resistor, while when it is V
SS the 400 K resistor is in parallel with the 10 K resistor. This modifies the overall resistances in the voltage divider. In this way, when the output from the comparator is at V
SS, the circuit will switch on the shorting transistors for a value of V
DD given by
(1)
V
DD
SHORT
=
V
ref
×
(
R
2
×
R
3
)
/
(
R
2
+
R
3
)
+
R
1
(
R
2
×
R
3
)
/
(
R
2
+
R
3
)
.Using the values from Figure1, in this case,
(2)
V
DD
SHORT
≈
3.01
V
.While the shorting transistors are on, the comparator output sags downwards along withV
DD. The comparator output will change to V
SS and switch off these transistors when the value of V
DD reaches
(3)
V
DD
(
OPEN
)
=
V
ref
×
(
R
1
×
R
3
)
/
(
R
1
+
R
3
)
+
R
2
R
2
.Again, using the values from Figure1, in this case,
(4)
V
DD
(
OPEN
)
≈
2.91
V
.Figure5 shows the simulated output voltage of the comparator for the overall circuit with respect to V
DD. The output voltage indicates a comparator switching frequency of around 3.3 kHz in this case. The switching frequency will vary based on the induced voltage and the RC time constant at the output of the rectifier (due to load resistance and value of the power supply capacitor) as well as the set tripping points (switching levels).Figure 5
Simulated voltage signals: shorting control voltage (V
out) and V
DD.


## 2.1. Voltage Reference Circuit

The supply-independent voltage reference circuit as described in [3] was redesigned using the thick-oxide devices available in the 130 nm CMOS process to generate the suitably selected reference voltage V
ref
=
1.236
V. The schematic diagram of this implemented circuit is shown in Figure 2. Temperature independence is not required in this case, since the device is designed for implanted telemetry application, whereby its temperature will be equal to the body temperature. In addition, no start-up circuit is required for this reference circuit. Initially, the output voltage is equal to 0, which is set by C
3, and M
15 is off. The voltage at the gate of M
16 is also close to 0 and M
16 is off. What makes the circuit go out of this state is that the channels of M
15 and M
13 act as resistances. Since M
15 is 4 times wider than M
13 and the charge-carrier (electron) mobility in NMOS (M
15) is higher (by around 2.5 times) compared to hole mobility in PMOS (M
13) [4], the channel of M
15 has a smaller resistance than that of M
13. In this way, the voltage at the drain of M
13 and the gate of M
14 hovers toward 0 and M
14 turns on, which starts up the circuit. Figure 3(a) shows the simulated voltage reference signal V
ref with respect to the positive rail voltage V
DD. Supply-independence of V
ref can be clearly noticed after start-up. The charging to the supply rail voltage V
DD using a power supply capacitor, C
L, of 22 μF and 12 μF is shown, respectively, in Figures 3(a) and 3(b).Figure 2
Voltage reference circuit using thick-oxide 3.6 V MOSFET devices.Simulated start-up voltage signals: (a) the comparator input reference voltageV
ref and charging-to-rail voltage V
DD using a 22 μF power supply capacitor and (b) charging-to-rail voltage V
DD using a 12 μF power supply capacitor.
(a)
(b)


## 2.2. Comparator Circuit

The comparator is a three-stage single-ended differential amplifier. Its schematic diagram is shown in Figure4. The first stage is a single-ended differential pair with active current mirror load. The second stage is a PMOS common source amplifier with an NMOS current-source load. The third stage is a push-pull inverter amplifier. The NMOS current-source bias voltage V
bias for the tail current of the differential input stage and the NMOS load is generated by the diode-connected device M
8 and resistor R
4.Figure 4
Schematic diagram of the comparator circuit.Since there is positive feedback through the 400 K resistor in the overall circuit shown in Figure1, this is a closed loop amplifier system. Internal frequency compensation was thus employed within the comparator circuit using the series connection of C
2 and R
5 as shown in Figure 4 between two high impedance nodes. This arrangement provides enhanced Miller compensation through the use of the series connected resistance R
5.


## 2.3. Switching Levels

The negative terminal input to the comparator is the reference voltageV
ref, and the positive terminal input is the output from the composite voltage divider consisting of the resistors R
1, R
2, and R
3 with values of 14 K, 10 K, and 400 K, respectively. The hysteresis is implemented through novel use of the 400 K R
3 resistor: when the comparator’s output voltage is V
DD, the 400 K resistor is in parallel with the 14 K resistor, while when it is V
SS the 400 K resistor is in parallel with the 10 K resistor. This modifies the overall resistances in the voltage divider. In this way, when the output from the comparator is at V
SS, the circuit will switch on the shorting transistors for a value of V
DD given by
(1)
V
DD
SHORT
=
V
ref
×
(
R
2
×
R
3
)
/
(
R
2
+
R
3
)
+
R
1
(
R
2
×
R
3
)
/
(
R
2
+
R
3
)
.Using the values from Figure1, in this case,
(2)
V
DD
SHORT
≈
3.01
V
.While the shorting transistors are on, the comparator output sags downwards along withV
DD. The comparator output will change to V
SS and switch off these transistors when the value of V
DD reaches
(3)
V
DD
(
OPEN
)
=
V
ref
×
(
R
1
×
R
3
)
/
(
R
1
+
R
3
)
+
R
2
R
2
.Again, using the values from Figure1, in this case,
(4)
V
DD
(
OPEN
)
≈
2.91
V
.Figure5 shows the simulated output voltage of the comparator for the overall circuit with respect to V
DD. The output voltage indicates a comparator switching frequency of around 3.3 kHz in this case. The switching frequency will vary based on the induced voltage and the RC time constant at the output of the rectifier (due to load resistance and value of the power supply capacitor) as well as the set tripping points (switching levels).Figure 5
Simulated voltage signals: shorting control voltage (V
out) and V
DD.


## 3. Fabrication and Testing

The circuit was designed using high-performance MIM capacitors and polysilicon resistors with the largest resistorR
3 being a high-resistivity RR resistor and others being RP precision resistors [5]. This implementation provided accurate resistor ratios with reduced temperature sensitivity. The core circuit occupied an area of only 127 μm × 125 μm with the active area dominated by the shorting transistors and the passive area dominated by the capacitors. The two shorting NMOSFETS were 1200 μm × 0.4 μm devices, with each laid out in a compact multifinger array of eighty 15 μm × 0.4 μm devices. The threshold voltages for the thick-oxide devices were, respectively, 0.460
±
0.065 V for the NMOS device and −0.420
±
0.052 V for the PMOS device. The primary and secondary coils for the inductive power transfer were held at an air gap of several centimeters as intended in the final application.The inductive power transfer test jig was assembled using the fabricated IC and discrete primary and secondary component assemblies. Figure6 shows the layout of the circuit while Figure 7 shows the corresponding die photo of the CMOS limiter IC.Figure 6
Annotated layout of the circuit. Shorting inputs are provided for connection to the secondary coil as indicated in Figure1.Figure 7
Annotated voltage limiter chip photo.Several signals were measured for the inductive power transfer setup shown in Figure8 through oscilloscope trace capture. Figure 9 shows the measured shorting control voltage which is the output voltage of the comparator. The magnified version of the same signal for just one “on” cycle is shown in Figure 10. This figure shows that the transistors are switched on (secondary coil shorted) when the supply voltage is about 2.99 V and switched off when it is about 2.88 V. The measured signals are off by less than 1% compared to the desired design specifications. In addition, Figure 11 shows the measured rail voltage V
DD with respect to the circuit ground, V
SS. This is also the rectified voltage across the load. Also, Figure 12 shows an instance of the measured induced voltage for the circuit.Figure 8
Inductive power transfer test jig with the fabricated regulator IC mounted in the secondary assembly.Figure 9
Measured comparator output voltage controlling the shorting transistors.Figure 10
Measured comparator output voltage for one “on” cycle.Figure 11
Measured rail voltageV
DD with respect to the circuit ground, V
SS.Figure 12
An instance of the measured induced voltage with respect to the circuit ground.



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*Source: 317523-2014-12-18.xml*