# DVCCCTA-Based Implementation of Mutually Coupled Circuit

Authors: Neeta Pandey; Sakshi Arora; Rinku Takkar; Rajeshwari Pandey
Journal: ISRN Electronics
 (2012)

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## Abstract

This paper presents implementation of mutually coupled circuit using differential voltage current-controlled conveyor transconductance amplifier (DVCCCTA). It employs only two DVCCCTAs, one grounded resistor, and two grounded capacitors. The primary, secondary, and mutual inductances of the circuit can be independently controlled and tuned electronically. The effect of non-ideal behaviour of DVCCCTA on the proposed circuit is analyzed. The functionality of the proposed circuit is verified through SPICE simulation using 0.25μm TSMC CMOS technology parameters.


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## Body

## 1. Introduction

Since the beginning of current-mode circuit concept, a lot of research has been directed towards the development of active inductance and immittance simulator circuits. A limited literature is available on active realizations (simulators) of mutually coupled circuit (MCC). The MCC is characterized by primary inductance, secondary inductance, mutual inductance, and the coupling factor. The MCC simulators can be integrated easily and have reduced possibility of magnetic interference due to absence of inductive components. Also, there exists a possibility of tunability of inductance values along with the coupling coefficient. Considering this, some MCC simulators have recently been reported in literature that uses different active building blocks [1–8]. The study of MCC simulators [1–8] shows that the circuits reported in [1, 2, 7] are based on operational transconductance amplifier (OTA), [2–4] that uses second-generation current conveyors (CCII), [5, 6] employ second-generation current-controlled conveyors (CCCII), [7] uses differential voltage current conveyors (DVCC) and CCIIs, [8] and utilizes current-controlled current backward transconductance amplifier (CC-CBTA). Some of these implementations [1–7] realize grounded MCC whereas a floating MCC realization is reported in [8]. The OTA-based MCC [1, 2] employs eight OTAs and two grounded capacitors. The CCII-based structures [2–4] use four to eight active elements, four to six resistors, and two to four capacitors. The CCCII-based MCC [5] employs four CCCIIs, five resistors, and two capacitors [5]. Reference [6] reports another CCCII-based MCC that uses five CCCIIs, two capacitors, and an inductor. Two circuits are reported in [7], the first circuit uses four OTAs, two resistors, and two capacitors whereas the second circuit makes use of two DVCCs; two CCIIs, six resistors, and two capacitors. The recently reported MCC [8] uses three CC-CBTAs and three capacitors. The circuits reported in [1, 5–8] are electronically tunable MCC parameters.In this paper, a new DVCCCTA- [9] based MCC is proposed that uses Gorski Popiel Technique [10]. It is floating in nature and uses only two DVCCCTAs, one resistor, and two grounded capacitors. The primary inductance (L1), secondary inductance (L2), and mutual inductance (M) can be electronically and independently controlled. The effect of nonideal behaviour of DVCCCTA on the proposed circuit is discussed. The functionality of the proposed circuit is tested under open-circuit condition. Its performance is exhibited by connecting it as a double-tuned band pass filter by using two additional resistors and two capacitors. The theoretical proposition has been verified with SPICE simulations using the parameters of 0.25 μm TSMC CMOS Technology.


## 2. Circuit Description

### 2.1. DVCCCTA

The DVCCCTA [9] is based on differential voltage current conveyor transconductance amplifier (DVCCTA) [11] and consists of differential amplifier, translinear loop and transconductance amplifier. The port relationships of the DVCCCTA as shown in Figure 1 can be characterized by the following matrix:
(1)[IY1IY2VXIZIO]=[00000000001-1RX0000100000gm0][VY1VY2IXVZVO],
where RX is the intrinsic resistance at X terminal and gm is the transconductance from Z terminal to O terminal of the DVCCCTA.Figure 1
Circuit symbol of DVCCCTA.The CMOS-based internal circuit of DVCCCTA [9] in CMOS is depicted in Figure 2. The values of RX and gm depend on bias currents IB1 and IB2, respectively, which may be expressed as
(2)RX=1(2μnCox(W/L)18,19IB1+2μpCox(W/L)16,17IB1),(3)gm=μnCox(W/L)24,25IB2.Figure 2
CMOS implementation of DVCCCTA [9].


### 2.2. DVCCCTA-Based Floating Mutually Coupled Circuit

In this section, firstly the port equations for a floating MCC are stated. Then, Gorski Popiel technique is outlined which is followed by realieation of the proposed DVCCCTA-based floating mutually coupled circuit.


#### 2.2.1. Floating Mutually Coupled Circuit

A floating MCC is shown in Figure3(a) and is functionally represented as
(4)V1F=sLPI1+sM12I2+V3F,V2F=sM21I1+sLSI2+V3F,
where LP=L1+M11 and LS=L2+M22, and M12 and M21 represent mutual inductances of MCC.Pictorial representation of floating MCC.
(a)
(b)Alternately, (4) can be represented as
(5)V1F-V3F=s(L1+M11)I1+sM12I2,V2F-V3F=sM21I1+s(L2+M22)I2.
Representing the voltages V1F-V3F and V2F-V3F as V1D and V2D, respectively, (5) reduces to
(6)V1D=s(L1+M11)I1+sM12I2,V2D=sM21I1+s(L2+M22)I2.
Equation (6) can be represented pictorially in Figure 3(b) which can be realized using Gorski Popiel technique [10] described in the following section.


#### 2.2.2. Gorski Popiel Technique [10]

This technique is generalization of inductor simulation method and uses generalized impedance converter (GIC). The GICs are circuits whose input impedance can be changed by appropriate selection of components and load. A simplified pictorial representation of GIC is shown in Figure4. The characteristic equation of GIC may be written as
(7)V1=V2,I2=sTI1,
where T represents time constant of GIC. In Figure 5, a GIC connected to a resistor in input branch makes the input impedance inductive. The value of the inductance would be TR.Figure 4
Symbolic Representation of GIC.Figure 5
Inductance simulation using Gorski Popiel Technique.This technique implies that a resistive network embedded in GICs appears like an inductive network of same topology with the inductance matrixLi=TRi. Thus it allows replacement of complete inductor networks by similar resistive networks rather than treating each inductor separately. Thus, this technique can be easily applied to T-shaped resistive network to get the mutually coupled circuit as shown in Figure 6.MCC implementation using Gorski Popiel Technique. (a) Resistive network with GIC, (b) its equivalent network.
(a)
(b)


#### 2.2.3. Proposed Floating Mutually Coupled Circuit

The method outlined in preceding section can be used for floating MCC realization if the voltagesV1 and V2 (Figure 6) represent differential voltage as shown in Figure 7. The DVCCCTA, being capable of processing differential inputs through Y1 and Y2 terminals, can be used to implement floating mutually coupled circuit.Floating MCC implementation using Gorski Popiel Technique.
(a)
(b)The proposed floating MCC circuit is shown in Figure8 where each DVCCCTA realizes GIC block (sT : 1) and a series resistance. Thus the circuit uses X-port resistances of 1st and 2nd DVCCCTA for realization of inductances L1 and L2 whereas resistance RM provides mutual coupling. The analysis of the circuit in Figure 8 gives
(8)V1D=sC1(RX1+RM)gm1I1+sC2RMgm2I2,V2D=sC1RMgm1I1+sC2(RX2+RM)gm2I2,
where V1D=V1F-V3F, V2D=V2F-V3F, RXi and gmi represent intrinsic X-port resistance and transconductance of ith DVCCCTA.Figure 8
Proposed floating MCC circuit.Using (3) and (6), the values of various inductances L1, L2, M11, M22, M12, and M21 can be computed as
(9)L1=C1RX1gm1,L2=C2RX2gm2,M11=C1RMgm1,M12=C2RMgm2,M21=C1RMgm1,M22=C2RMgm2.
For symmetrical coupling, M12=M21=M. Assuming gm1=gm2=gm, and C1=C2=C, the inductances become
(10)L1=CRX1gm,L2=CRX2gm,M=CRMgm.
The coefficient of coupling (k) can be computed as
(11)k=RM(RX1+RM)(RX2+RM).
The resistance RM being grounded can easily be implemented with MOS transistor [12]. Thus, the inductances of MCC as well as coefficient of coupling can be electronically tuned.


### 2.3. Non-Ideal Analysis

The frequency performance of the proposed MCC may deviate from the ideal one due to non-idealities. The DVCCCTA nonidealities may be categorized in two groups. The first comes from nonunity internal current and voltage transfers in DVCCCTA. The modified port relationships may be written in matrix form as follows:(12)[IY1IY2VXIZIO]=[0000000000β1-β2RX0000α00000γgm0][VY1VY2IXVZVO],
where the voltage transfer functions β1=1-εv1 and β2=1-εv2. The εv1 and εv2 denote voltage tracking errors from Y1 and Y2 terminals to X terminal, respectively. The current transfer function α=1-εi, where εi denote current tracking error from X to Z terminal. The coefficient γ denotes current transfer function from Z terminal to O terminals. Considering these deviations in the voltage and current transfers, (9) modifies to
(13)L1=CRX1(αβγgm),L2=CRX2(αβγgm),M11=M12=M21=M22=CRM(αβγgm),
where equal values of α, β, and γ are assumed for both DVCCCTAs. Equation (9) clearly indicates that the nonunity voltage and current transfer functions of DVCCCTA affect various inductances. Apart from having non-unity values, the current and voltage transfer functions also have poles at high frequencies. Their effect on proposed MCC performance can however be ignored if the operating frequencies are chosen sufficiently smaller than voltage and current transfer pole frequencies of the DVCCCTA.The second group of nonidealities comes from parasitics of DVCCCTA comprising of resistances and capacitances connected in parallel at terminalsY1, Y2, Z, and O (i.e., RY1, CY1, RY2, CY2, RZ, CZ, RO, CO). The effects of these parasitics on filter response depend strongly on circuit topology. In the proposed structure, the external capacitor appears in parallel to the parasitic capacitor, the effect of these may be accommodated by preadjusting the external capacitor value.


## 2.1. DVCCCTA

The DVCCCTA [9] is based on differential voltage current conveyor transconductance amplifier (DVCCTA) [11] and consists of differential amplifier, translinear loop and transconductance amplifier. The port relationships of the DVCCCTA as shown in Figure 1 can be characterized by the following matrix:
(1)[IY1IY2VXIZIO]=[00000000001-1RX0000100000gm0][VY1VY2IXVZVO],
where RX is the intrinsic resistance at X terminal and gm is the transconductance from Z terminal to O terminal of the DVCCCTA.Figure 1
Circuit symbol of DVCCCTA.The CMOS-based internal circuit of DVCCCTA [9] in CMOS is depicted in Figure 2. The values of RX and gm depend on bias currents IB1 and IB2, respectively, which may be expressed as
(2)RX=1(2μnCox(W/L)18,19IB1+2μpCox(W/L)16,17IB1),(3)gm=μnCox(W/L)24,25IB2.Figure 2
CMOS implementation of DVCCCTA [9].


## 2.2. DVCCCTA-Based Floating Mutually Coupled Circuit

In this section, firstly the port equations for a floating MCC are stated. Then, Gorski Popiel technique is outlined which is followed by realieation of the proposed DVCCCTA-based floating mutually coupled circuit.


### 2.2.1. Floating Mutually Coupled Circuit

A floating MCC is shown in Figure3(a) and is functionally represented as
(4)V1F=sLPI1+sM12I2+V3F,V2F=sM21I1+sLSI2+V3F,
where LP=L1+M11 and LS=L2+M22, and M12 and M21 represent mutual inductances of MCC.Pictorial representation of floating MCC.
(a)
(b)Alternately, (4) can be represented as
(5)V1F-V3F=s(L1+M11)I1+sM12I2,V2F-V3F=sM21I1+s(L2+M22)I2.
Representing the voltages V1F-V3F and V2F-V3F as V1D and V2D, respectively, (5) reduces to
(6)V1D=s(L1+M11)I1+sM12I2,V2D=sM21I1+s(L2+M22)I2.
Equation (6) can be represented pictorially in Figure 3(b) which can be realized using Gorski Popiel technique [10] described in the following section.


### 2.2.2. Gorski Popiel Technique [10]

This technique is generalization of inductor simulation method and uses generalized impedance converter (GIC). The GICs are circuits whose input impedance can be changed by appropriate selection of components and load. A simplified pictorial representation of GIC is shown in Figure4. The characteristic equation of GIC may be written as
(7)V1=V2,I2=sTI1,
where T represents time constant of GIC. In Figure 5, a GIC connected to a resistor in input branch makes the input impedance inductive. The value of the inductance would be TR.Figure 4
Symbolic Representation of GIC.Figure 5
Inductance simulation using Gorski Popiel Technique.This technique implies that a resistive network embedded in GICs appears like an inductive network of same topology with the inductance matrixLi=TRi. Thus it allows replacement of complete inductor networks by similar resistive networks rather than treating each inductor separately. Thus, this technique can be easily applied to T-shaped resistive network to get the mutually coupled circuit as shown in Figure 6.MCC implementation using Gorski Popiel Technique. (a) Resistive network with GIC, (b) its equivalent network.
(a)
(b)


### 2.2.3. Proposed Floating Mutually Coupled Circuit

The method outlined in preceding section can be used for floating MCC realization if the voltagesV1 and V2 (Figure 6) represent differential voltage as shown in Figure 7. The DVCCCTA, being capable of processing differential inputs through Y1 and Y2 terminals, can be used to implement floating mutually coupled circuit.Floating MCC implementation using Gorski Popiel Technique.
(a)
(b)The proposed floating MCC circuit is shown in Figure8 where each DVCCCTA realizes GIC block (sT : 1) and a series resistance. Thus the circuit uses X-port resistances of 1st and 2nd DVCCCTA for realization of inductances L1 and L2 whereas resistance RM provides mutual coupling. The analysis of the circuit in Figure 8 gives
(8)V1D=sC1(RX1+RM)gm1I1+sC2RMgm2I2,V2D=sC1RMgm1I1+sC2(RX2+RM)gm2I2,
where V1D=V1F-V3F, V2D=V2F-V3F, RXi and gmi represent intrinsic X-port resistance and transconductance of ith DVCCCTA.Figure 8
Proposed floating MCC circuit.Using (3) and (6), the values of various inductances L1, L2, M11, M22, M12, and M21 can be computed as
(9)L1=C1RX1gm1,L2=C2RX2gm2,M11=C1RMgm1,M12=C2RMgm2,M21=C1RMgm1,M22=C2RMgm2.
For symmetrical coupling, M12=M21=M. Assuming gm1=gm2=gm, and C1=C2=C, the inductances become
(10)L1=CRX1gm,L2=CRX2gm,M=CRMgm.
The coefficient of coupling (k) can be computed as
(11)k=RM(RX1+RM)(RX2+RM).
The resistance RM being grounded can easily be implemented with MOS transistor [12]. Thus, the inductances of MCC as well as coefficient of coupling can be electronically tuned.


## 2.2.1. Floating Mutually Coupled Circuit

A floating MCC is shown in Figure3(a) and is functionally represented as
(4)V1F=sLPI1+sM12I2+V3F,V2F=sM21I1+sLSI2+V3F,
where LP=L1+M11 and LS=L2+M22, and M12 and M21 represent mutual inductances of MCC.Pictorial representation of floating MCC.
(a)
(b)Alternately, (4) can be represented as
(5)V1F-V3F=s(L1+M11)I1+sM12I2,V2F-V3F=sM21I1+s(L2+M22)I2.
Representing the voltages V1F-V3F and V2F-V3F as V1D and V2D, respectively, (5) reduces to
(6)V1D=s(L1+M11)I1+sM12I2,V2D=sM21I1+s(L2+M22)I2.
Equation (6) can be represented pictorially in Figure 3(b) which can be realized using Gorski Popiel technique [10] described in the following section.


## 2.2.2. Gorski Popiel Technique [10]

This technique is generalization of inductor simulation method and uses generalized impedance converter (GIC). The GICs are circuits whose input impedance can be changed by appropriate selection of components and load. A simplified pictorial representation of GIC is shown in Figure4. The characteristic equation of GIC may be written as
(7)V1=V2,I2=sTI1,
where T represents time constant of GIC. In Figure 5, a GIC connected to a resistor in input branch makes the input impedance inductive. The value of the inductance would be TR.Figure 4
Symbolic Representation of GIC.Figure 5
Inductance simulation using Gorski Popiel Technique.This technique implies that a resistive network embedded in GICs appears like an inductive network of same topology with the inductance matrixLi=TRi. Thus it allows replacement of complete inductor networks by similar resistive networks rather than treating each inductor separately. Thus, this technique can be easily applied to T-shaped resistive network to get the mutually coupled circuit as shown in Figure 6.MCC implementation using Gorski Popiel Technique. (a) Resistive network with GIC, (b) its equivalent network.
(a)
(b)


## 2.2.3. Proposed Floating Mutually Coupled Circuit

The method outlined in preceding section can be used for floating MCC realization if the voltagesV1 and V2 (Figure 6) represent differential voltage as shown in Figure 7. The DVCCCTA, being capable of processing differential inputs through Y1 and Y2 terminals, can be used to implement floating mutually coupled circuit.Floating MCC implementation using Gorski Popiel Technique.
(a)
(b)The proposed floating MCC circuit is shown in Figure8 where each DVCCCTA realizes GIC block (sT : 1) and a series resistance. Thus the circuit uses X-port resistances of 1st and 2nd DVCCCTA for realization of inductances L1 and L2 whereas resistance RM provides mutual coupling. The analysis of the circuit in Figure 8 gives
(8)V1D=sC1(RX1+RM)gm1I1+sC2RMgm2I2,V2D=sC1RMgm1I1+sC2(RX2+RM)gm2I2,
where V1D=V1F-V3F, V2D=V2F-V3F, RXi and gmi represent intrinsic X-port resistance and transconductance of ith DVCCCTA.Figure 8
Proposed floating MCC circuit.Using (3) and (6), the values of various inductances L1, L2, M11, M22, M12, and M21 can be computed as
(9)L1=C1RX1gm1,L2=C2RX2gm2,M11=C1RMgm1,M12=C2RMgm2,M21=C1RMgm1,M22=C2RMgm2.
For symmetrical coupling, M12=M21=M. Assuming gm1=gm2=gm, and C1=C2=C, the inductances become
(10)L1=CRX1gm,L2=CRX2gm,M=CRMgm.
The coefficient of coupling (k) can be computed as
(11)k=RM(RX1+RM)(RX2+RM).
The resistance RM being grounded can easily be implemented with MOS transistor [12]. Thus, the inductances of MCC as well as coefficient of coupling can be electronically tuned.


## 2.3. Non-Ideal Analysis

The frequency performance of the proposed MCC may deviate from the ideal one due to non-idealities. The DVCCCTA nonidealities may be categorized in two groups. The first comes from nonunity internal current and voltage transfers in DVCCCTA. The modified port relationships may be written in matrix form as follows:(12)[IY1IY2VXIZIO]=[0000000000β1-β2RX0000α00000γgm0][VY1VY2IXVZVO],
where the voltage transfer functions β1=1-εv1 and β2=1-εv2. The εv1 and εv2 denote voltage tracking errors from Y1 and Y2 terminals to X terminal, respectively. The current transfer function α=1-εi, where εi denote current tracking error from X to Z terminal. The coefficient γ denotes current transfer function from Z terminal to O terminals. Considering these deviations in the voltage and current transfers, (9) modifies to
(13)L1=CRX1(αβγgm),L2=CRX2(αβγgm),M11=M12=M21=M22=CRM(αβγgm),
where equal values of α, β, and γ are assumed for both DVCCCTAs. Equation (9) clearly indicates that the nonunity voltage and current transfer functions of DVCCCTA affect various inductances. Apart from having non-unity values, the current and voltage transfer functions also have poles at high frequencies. Their effect on proposed MCC performance can however be ignored if the operating frequencies are chosen sufficiently smaller than voltage and current transfer pole frequencies of the DVCCCTA.The second group of nonidealities comes from parasitics of DVCCCTA comprising of resistances and capacitances connected in parallel at terminalsY1, Y2, Z, and O (i.e., RY1, CY1, RY2, CY2, RZ, CZ, RO, CO). The effects of these parasitics on filter response depend strongly on circuit topology. In the proposed structure, the external capacitor appears in parallel to the parasitic capacitor, the effect of these may be accommodated by preadjusting the external capacitor value.


## 3. Simulation Results

To verify the functionality of the proposed DVCCCTA-based MCC, SPICE simulations have been carried out using TSMC 0.25μm CMOS process model parameters and power supplies of VDD=-VSS=1.25 V and VBB=0.8 V. The aspect ratios of various transistors of DVCCCTA (Figure 2) are listed in Table 1. Firstly, the proposed circuit is tested under the open-circuit condition, that is, I2=0, so the ratio between the secondary and the primary voltage can be expressed as
(14)VoutVin=RMRM+RX1.Table 1
Aspect ratios of CMOS transistors in DVCCCTA.
Transistors
Aspect ratio (W (μm)/L (μm))
M
1, M4, M9, M11–M15, M30-M31
3/0.25
M
2, M3, M5, M6
1/0.25
M
7-M8, M20–M23, M26, M28-M29
5/0.25
M
10
12.5/0.25
M
16-M17
8/0.25
M
18-M19
5/0.25
M
24-M25
5/0.25
M
27
4.35/0.25Equation (14) clearly shows that under the open-circuit condition the ratio between the output and input voltages will be frequency independent. The open circuit is tested for bias currents IB1 and IB2 taken as 10 μA and 160 μA, respectively, for both DVCCCTA. The values of C1, C2, and RM are 10 pF, 10 pF, and 1.33 kΩ, respectively. The simulation result as shown in Figure 9 confirms the relation between Vout and Vin.Figure 9
Simulated response of proposed MCC under open-circuit condition.To illustrate an application of proposed mutually coupled circuit, a double-tuned circuit is constructed as shown in Figure10. The primary and secondary side resonance frequencies (fP and fS) and quality factors (QP and QS) can be obtained as
(15)fP=1(2πCP(L1+M)),fS=1(2πCS(L2+M)),QP=2πfPRPCP,QS=2πfSRSCS.Figure 10
Double-tuned circuit.The performance of the double-tuned circuit is tested with following component values:RP=RS=11 kΩ; CP=CS=20 pF; for proposed MCC: RM=1.33 kΩ, C1=C2=10 pF. The bias current IB1 and IB2 are selected as 10 μA and 160 μA, respectively, so as to provide RX1=RX2 as 2 kΩ and 1/gm1=1/gm2 as 1.5 kΩ. The resulting values of inductances are L1=L2=30 μH and M11=M12=M21=M22=19.95 μH. This selection results in fP=fS=5.035 MHz and Qp=Qs=6.952. The ideal and simulated responses of a double-tuned circuit are shown in Figure 11. There is a close agreement between the ideal and simulated values. The electronic tunability is demonstrated by varying bias current IB2 of both the DVCCCTAs from 10 μA to 250 μA and the simulation results are shown in Figure 12.Figure 11
Simulated and ideal response of double-tuned circuit.Figure 12
Simulated filter response with varying bias currentIB2.To study the time domain behaviour of the double-tuned circuit (Figure10), a sinusoidal signal of 300 mV amplitude and frequency of 5.035 MHz is applied as input. The transient response is depicted in Figure 13 which shows that ideal and simulated responses are in close approximation. The power consumption of the circuit was 2.77 mW. The double-tuned circuit is also tested to judge the level of harmonic distortion at the output of the signal. The %THD result is shown in Figure 14 which shows that the output distortion is low and within 3% up to about 800 mV.Figure 13
Transient response of double-tuned circuit of Figure10.Figure 14
Variation of %THD with respect to input signal amplitude.


## 4. Conclusion

In this paper, DVCCCTA-based circuit for simulation of floating mutually coupled circuit has been presented. The proposed circuit uses only two DVCCCTAs, one grounded resistor, and two grounded capacitors. The primary and secondary inductances of the circuit can be independently controlled and tuned electronically via bias currents of DVCCCTAs whereas mutual coupling can be adjusted via grounded resistor. This resistor can be realized with MOS transistors. The nonideal analysis of circuit is included and as an application a double-tuned circuit is simulated.



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*Source: 303191-2012-09-24.xml*