# Integrated Sensory Throughput and Traffic-Aware Arbiter for High Productive Multicore Architectures

Authors: T. Venkata Sridhar; G. Chenchu Krishnaiah
Journal: Journal of Sensors
 (2022)

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## Abstract

The increasing demand for network and high-performance devices requires large data throughputs with minimal loss or repetition. Network on chips (NoC) provides excellent connectivity among multiple on-chip communicating devices with minimal loss compared with old bus systems. The motivation is to improve the throughput of the NoC that integrated on multicores for communication among cores by reducing the communication latency. The design of the arbiter in the crossbars switch of an NoC’s router has a vital role in judging the system’s speed and performance. Low latency and high-speed switching are possible with high performance and good switching equipment at the network level. One of the significant components in NoC under SoC design is the arbiter, which governs the system’s performance. Proper arbitrations can avoid network or traffic congestions like livelock and buffer waiting. The proposed work in this paper is to design an efficient and high productive arbiter for multicore chips, especially SoCs and CMPs. The proposed arbiter is showing good improvement in the throughput at higher data rates; an average of more than 10% throughput improvement is noticed at higher flit injection rates independent of the VCs implemented. Further, the critical delays are reduced to 15.84% with greater throughputs.


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## Body

## 1. Introduction

High-performance computing devices are the most regular devices at a compact level in the day-to-day lifestyle of humans in the present era. Recently, even large computing equipment becoming handy and lightweight requires the integration of larger hardware components at a large scale into compact modules resulting in an SoC (system on a chip). The design of an SoC [1, 2] is a common phenomenon in the modern manufacturing of major electronics. To meet the QoS (quality of service) of these manufacturing technologies at a scaling of nanometer level, factors like latency, power dissipation, error rate, and software error rates [3, 4] need to be appropriately managed [5]. Embedded SoC is application-oriented and requires an uncompromised communication interface for different environments on the chip, like processor(s), memory, control module, sometimes form firmware to the software. Due to the great demand in processing speed, the manufacturers had increased the number of processors integrated on a single chip considerably, starting from dual core to many cores [6]. MPSoC [7] are the new-generation manufacturing methods from the past one and a half-decade, giving a reasonable throughput for multitasking. Figure 1 shows a job run of a typical application-oriented MPSoC. Smart MPSoC contains integrated hardware [8].Figure 1
Job run of MPSoC.Before mapping the data to be handled by multiple processors, it is essential to configure and evaluate the requirements as per the specific task. To map different cores on a single chip, like processor(s), DRAM(s)/SRAM(s), DSP(s), video processors, and DMA, the established bus technology has many compromises.NoC is a simple solution for such compromises to overcome. An NoC reduces the burden of calculation from the transmission. An efficient NoC requires good routing, network interfacing, and switching. A crossbar with a well-structured arbiter design is inevitable. The major contribution of the work it to improve the throughput of the arbiter in critical traffic timings that was achieved through a flexible priority resolver. The proposed arbiter is tested under synthetic traffic (ST) and uniform random traffic (URT) conditions. For both conditions, improvement in the throughput was observed. If the communication latency between the cores is reduced, then the time taken for data traversal is reduced; hence, this method can produce more throughput in a small time.The major challenge in the existing models is handling the data when a network congestion occur, like a deadlock or a livelock. The existing model arbiter has fixed arbitrations for all the traffic conditions and is suffering if traffic conditions are unpredictable. The proposed model has a flexible priority resolver that can adjust the arbitrations according to the traffic. The proposed arbiter is showing good improvement in the throughput at higher data rates; an average of more than 10% throughput improvement is noticed at higher flit injection rates independent of the VCs implemented. Further, the critical delays are reduced to 15.84% with greater throughputs.The process of mapping is information exchange between multicores or processing elements in the specified architecture. An efficient rouging on the NoC will execute the same without any deadlock or livelock. In the proposed model, the NoC with a flexible priority arbiter is enabling efficient information exchange between all cores in MPSoC. Many deep learning and AI platforms are in urge for high data processing systems; hence, this paper aims for such design [9–11].Section2 presents multicore architecture design and NoC interconnections and problems in design. Section 3 covers NoC crossbar switching with a well-organized arbiter design. Section 4 includes simulations of the proposed work and analysis. Section 5 is the conclusion containing limitations and plans of the work.


## 2. Multicore Systems

Multicore architectures are the best inevitable design for high-performance computers to handle large and complex data. Its architecture and design provide all the rising performance needs. Figure2 illustrates the basic building blocks of heterogeneous SoC. And Figure 3 depicts device-level visualization.Figure 2
On-chip blocks of a multicore architecture.Figure 3
Device-level visualization of SoC.


### 2.1. Multiprocessor Architecture

The basic design of all multicore processors is to integrate the required data memories and instruction memories, i.e., L1 cache, secondary memories, i.e., L2 cache, on the chip itself. That is shown in Figure2.A proper link between different modules is required so that it should not degrade the performance of SoC. This is not achievable with the age-old bus systems. [3]. Either an SoC is general or application-specific; the NoC provides an exceptional solution for on-chip communication [12, 13].


### 2.2. The Communication Interface: NoC

As NoC is emerging as the leading solution to interface all on-chip devices in an SoC [14, 15], the design elements should be keenly followed. Like, choosing topology for implementation, maximum sustainable and error-free routing, and flow-control system [16, 17] are the vital elements in the design of an NoC. Figure 4 presents the basic block level understanding of the network on chip. Application-specific ONoCs (Optical NoCs) are even embedding the optics in microelectronics [18].Figure 4
Fundamental NoC structure.The aim of an NoC as the heart of SoC is to provide an efficient, mostly stand-off free, power, and throughput aware communication amidst different cores of the system on chip [19]. Modern SoC designs are coming with FinFETs, which can improve communication speed [20].


### 2.3. The NoC Architectonic

Network on chip architectonic contains many building blocks; among most important aretopology, interface, and routing selection, for an efficient communication establishment.


#### 2.3.1. Selection of Topology

The selection of the topology decides the area, power consumption, and speed of communication between the connected cores; it should be picked according to the need. That is as Application Specific (AS) or non-AS designs of SoC. Topologies like “Star,” “Mesh,” “Torus,” “Octagon,” “Spidergon,” and “Tree” in 2D and 3D [21–23]. Mesh and Torus (sometimes folded) are the regular in power considerations, shown in Figure 5. The average distance between cores should be minimum concerning a hop count.Figure 5
(a) A3×3 mesh in 2D with one core connected to one router. (b) A 3×3 torus in 2D with one core connected to one router.
(a)(b)


#### 2.3.2. Interface Design

An interface provides communication between the core and the network with an assured throughput. An NI (network interface) will do assemble and disassemble packets and communicate them with the core. Proper choosing of network topology and routing techniques will improve the efficiency of the network interface.


#### 2.3.3. Routing

The communication path from the source core to the destination core through NoC, without any congestions or blockages, is the aim of routing [24]. Defining a proper routing algorithm is needed to decide the latency in communication. Figure 6 illustrates a block diagram of the complete NoC architecture.Figure 6
Different cores of SoC connected using NoC.


### 2.4. Crossbar Switch

After finalizing the routing and packing, it is required to switch the data according to the algorithm defined by NoC. Each data packet is Muxed thoroughI×O crossbar (Figure 6). Per one cycle, one defined data packet can go through.Figure6 is a heterogeneous MPSoC architecture in which each tile contains different processing elements like memory block, DSP block, reduced instruction set computer, CPU, and graphic processor. An efficient networking architecture requires communicating data sharing among all the modules/processing elements. A single block of network interface/router is expanded in dotted line, which consists of a mechanism for data exchange in all four directions of connections. This is explained in section II-C: 2-3, D-E, respectively. The performance of the router directly depends on the efficiency of the crossbar switch and arbiter design. Hence, to achieve a low communication latency, these two are playing a very important role.


### 2.5. Arbiter

The arbitrations are dependent on the selection of virtual channels or the wormhole method. The arbiter is generally responsible for allowing the channel usage for all the inputs according to the routing strategies. Prioritization is more vital because it decides the speed of communication. In this research, we used a flexible priority such that livelock will be mostly avoided. Once all the input data reached the crossbar, the stages of the arbiter will be terminated accordingly.Kameda et al. [25] had proposed an SFQ design for validating the crossbar. The idea is to increase the throughput to a considerable level by avoiding collisions. The experiment is limited to the usage of frequency and is more accurate at 40 GHz. Prioritization is a parallel processing type. The RRA design leads to high speed with frequency limitation.Lee et al. [26] had reported a decentralized arbiter with high speed (HDRA). This design is aimed only at the most censorious path delays to minimize the production cost. The VOQs introduced in the design will reduce the blocking of the head of the line. HRDA is a derived version of PPA (O(log 4 N)structure), PRRA, and IPRRA as given in Figure 7.Figure 7
Decentralization tree of RRA.When the integration of the cores in SoC increases, the design suffers from a large amount of complexity to find all the decentralized nodes by NoC and end assembly will become an issue.Giorgos et al. [27] have suggested a simple design without much changes in the existing design, but with intelligent adoption. The approach is merging of the switching allocation, i.e., MARX which combines the multiplexer and arbiter as depicted in Figure 8. This design focuses majorly on the performance of the entire system, which increases the complexity in design. The Merged ARbiter and multipleXer (MARX) combines the architectures of an arbiter and multiplexer.Figure 8
MARX structure.


## 2.1. Multiprocessor Architecture

The basic design of all multicore processors is to integrate the required data memories and instruction memories, i.e., L1 cache, secondary memories, i.e., L2 cache, on the chip itself. That is shown in Figure2.A proper link between different modules is required so that it should not degrade the performance of SoC. This is not achievable with the age-old bus systems. [3]. Either an SoC is general or application-specific; the NoC provides an exceptional solution for on-chip communication [12, 13].


## 2.2. The Communication Interface: NoC

As NoC is emerging as the leading solution to interface all on-chip devices in an SoC [14, 15], the design elements should be keenly followed. Like, choosing topology for implementation, maximum sustainable and error-free routing, and flow-control system [16, 17] are the vital elements in the design of an NoC. Figure 4 presents the basic block level understanding of the network on chip. Application-specific ONoCs (Optical NoCs) are even embedding the optics in microelectronics [18].Figure 4
Fundamental NoC structure.The aim of an NoC as the heart of SoC is to provide an efficient, mostly stand-off free, power, and throughput aware communication amidst different cores of the system on chip [19]. Modern SoC designs are coming with FinFETs, which can improve communication speed [20].


## 2.3. The NoC Architectonic

Network on chip architectonic contains many building blocks; among most important aretopology, interface, and routing selection, for an efficient communication establishment.


### 2.3.1. Selection of Topology

The selection of the topology decides the area, power consumption, and speed of communication between the connected cores; it should be picked according to the need. That is as Application Specific (AS) or non-AS designs of SoC. Topologies like “Star,” “Mesh,” “Torus,” “Octagon,” “Spidergon,” and “Tree” in 2D and 3D [21–23]. Mesh and Torus (sometimes folded) are the regular in power considerations, shown in Figure 5. The average distance between cores should be minimum concerning a hop count.Figure 5
(a) A3×3 mesh in 2D with one core connected to one router. (b) A 3×3 torus in 2D with one core connected to one router.
(a)(b)


### 2.3.2. Interface Design

An interface provides communication between the core and the network with an assured throughput. An NI (network interface) will do assemble and disassemble packets and communicate them with the core. Proper choosing of network topology and routing techniques will improve the efficiency of the network interface.


### 2.3.3. Routing

The communication path from the source core to the destination core through NoC, without any congestions or blockages, is the aim of routing [24]. Defining a proper routing algorithm is needed to decide the latency in communication. Figure 6 illustrates a block diagram of the complete NoC architecture.Figure 6
Different cores of SoC connected using NoC.


## 2.3.1. Selection of Topology

The selection of the topology decides the area, power consumption, and speed of communication between the connected cores; it should be picked according to the need. That is as Application Specific (AS) or non-AS designs of SoC. Topologies like “Star,” “Mesh,” “Torus,” “Octagon,” “Spidergon,” and “Tree” in 2D and 3D [21–23]. Mesh and Torus (sometimes folded) are the regular in power considerations, shown in Figure 5. The average distance between cores should be minimum concerning a hop count.Figure 5
(a) A3×3 mesh in 2D with one core connected to one router. (b) A 3×3 torus in 2D with one core connected to one router.
(a)(b)


## 2.3.2. Interface Design

An interface provides communication between the core and the network with an assured throughput. An NI (network interface) will do assemble and disassemble packets and communicate them with the core. Proper choosing of network topology and routing techniques will improve the efficiency of the network interface.


## 2.3.3. Routing

The communication path from the source core to the destination core through NoC, without any congestions or blockages, is the aim of routing [24]. Defining a proper routing algorithm is needed to decide the latency in communication. Figure 6 illustrates a block diagram of the complete NoC architecture.Figure 6
Different cores of SoC connected using NoC.


## 2.4. Crossbar Switch

After finalizing the routing and packing, it is required to switch the data according to the algorithm defined by NoC. Each data packet is Muxed thoroughI×O crossbar (Figure 6). Per one cycle, one defined data packet can go through.Figure6 is a heterogeneous MPSoC architecture in which each tile contains different processing elements like memory block, DSP block, reduced instruction set computer, CPU, and graphic processor. An efficient networking architecture requires communicating data sharing among all the modules/processing elements. A single block of network interface/router is expanded in dotted line, which consists of a mechanism for data exchange in all four directions of connections. This is explained in section II-C: 2-3, D-E, respectively. The performance of the router directly depends on the efficiency of the crossbar switch and arbiter design. Hence, to achieve a low communication latency, these two are playing a very important role.


## 2.5. Arbiter

The arbitrations are dependent on the selection of virtual channels or the wormhole method. The arbiter is generally responsible for allowing the channel usage for all the inputs according to the routing strategies. Prioritization is more vital because it decides the speed of communication. In this research, we used a flexible priority such that livelock will be mostly avoided. Once all the input data reached the crossbar, the stages of the arbiter will be terminated accordingly.Kameda et al. [25] had proposed an SFQ design for validating the crossbar. The idea is to increase the throughput to a considerable level by avoiding collisions. The experiment is limited to the usage of frequency and is more accurate at 40 GHz. Prioritization is a parallel processing type. The RRA design leads to high speed with frequency limitation.Lee et al. [26] had reported a decentralized arbiter with high speed (HDRA). This design is aimed only at the most censorious path delays to minimize the production cost. The VOQs introduced in the design will reduce the blocking of the head of the line. HRDA is a derived version of PPA (O(log 4 N)structure), PRRA, and IPRRA as given in Figure 7.Figure 7
Decentralization tree of RRA.When the integration of the cores in SoC increases, the design suffers from a large amount of complexity to find all the decentralized nodes by NoC and end assembly will become an issue.Giorgos et al. [27] have suggested a simple design without much changes in the existing design, but with intelligent adoption. The approach is merging of the switching allocation, i.e., MARX which combines the multiplexer and arbiter as depicted in Figure 8. This design focuses majorly on the performance of the entire system, which increases the complexity in design. The Merged ARbiter and multipleXer (MARX) combines the architectures of an arbiter and multiplexer.Figure 8
MARX structure.


## 3. Arbiter Design

The significant component in NoC under SoC design is the arbiter, which governs the system’s performance. Proper arbitrations can avoid network or traffic congestions like livelock and buffer waiting with both synchronous and asynchronous communication [28]. The proposed work in this paper is to design an efficient and high productive arbiter for multicore chips, especially SoCs and CMPs. The switching of the arbiter is shown in Figure 9. The design is a mesh topology and can communicate in four directions with a local transfer, which deserves a buffer count of five.Figure 9
Data switching blocks.RR (round robin) arbiter model is the most commonly used method for NoC router design because of its ease and straightforwardness. Let us use RQn: request, GTn: grant, and PRn and PRn̂: priorities of current and immediate future cycle. Kinn and Koutn decide the priorities between arbiter buffer or cells. Then, according to RRA design, the grant will be issued only when PRn is 1 as follows:
(1)GTn=RQn·PRn+Kinn,(2)Ko¯utn=RQn·PRn+Kinn,(3)PRn∧=GTn−1+PRn·Kinn.Thus, the channel allocation for the next stage of traffic purely depends on the current running stage and followed by a subsequent request of existing channel using data. This is valid only if at least one present state exists. This drawback was modified with a priority resolver in our design, which estimates the density of the future traffic depending on the input requests to the router (possibly N:E:W:S direction) and load on previous router which directed the current transfer as shown in Figure10. It has two efficient prioritizations chosen dynamically as fixed or rotating [29–32].Figure 10
(a) Existing arbiter, (b) proposed flexible arbiter, and (c) arbitration simulation result.
(a)(b)(c)


### 3.1. VCA Arbiter

Congestion avoidance, like a deadlock and livelock, can be handled by the arbiter. Flit bifurcation in routing is done based on the size of the data, the head flit may be one, but the body flits are packet size-dependent. The count is calculated before it reaches the VC (virtual channel). The allocation unit of the VC is done with a head flit. VCA unit allocates the channel for the data packets to travel through different routers. The mechanism of the two stages is illustrated in Figure11.Figure 11
VCA arbitration.


### 3.2. Switching Arbiter

Once VC is allocated to the packets, the central part is to do switch allocation (SA), which leads to reaching the packet to the destination by competing with all the other VC allocated packets. Here, all the flits need to be allocated. To reduce the delay in communication to the destination, a flexible priority resolver is introduced in this proposed architecture. This reduced the computation complexity of allocation among all the VC allocations shown in Figure12. Switch traverse (ST) and link traverse (LT) will lead the granted allocation packets to reach the specified destination.Figure 12
FP switch allocator.


### 3.3. Proposed Arbiter

Most of the existing arbiter designs follow a round robin which rotates the output grants received and precedes the rest Figure10(a). This will increase the burden on the arbiter as the flits increase for large throughputs. The proposed arbiter has a flexible priority resolver which estimates the traffic/load on the arbiter about to come Figure 10(b). Unlike normal RRA, the specific rotation or fixed orientation is predefined here; hence, the time calculation of arbitrations can reduce, and throughput will increase.The priority resolver has flexibility depending on the traffic, like fixed, rotating. If traffic is less and the expected latency in switching is less, then fixed priority can be chosen; if not, rotating priority can be chosen to distribute equal priority to all switching flits. The structure of the algorithm is as follows.


### 3.4. Proposed Arbiter Algorithm

The algorithm below specifies the arbiter’s input request and grants according to flexible priority, depending on the load/traffic buffer channel rout calculation; VCA, SA, ST, and LT are the significant concerns in computing the travel delay. In the proposed arbiter, important computations are done in the stage of priority resolving hence expected low latency with high throughput. First, it verifies all allocated buffers in step 1, finds the density of the traffic load and enables the priority resolver if found large loads in steps 2-3, and assigns mapping of source and destinations by eliminating redundant allocations in steps 4-5. Check the transfer from lower end node to higher in the same process for finding multiple iterations; if all good, enable the transfer in steps 6–8.Algorithm 1
Step 1: check all input buffer requests.Step 2: is the load/traffic more than regular transfer with respect to previous router data.Step 3: chose to assign priority as rotation if traffic increases else, fixed.Step 4: map i/p-port to o/p-port of arbiter for packet transfer.Step 5: check for replication of the same packet assigned to various arbiters.Step 6: check packets of o/p-port mapping to i/p-port according to the assignment.Step 7: verify for the multiple iterations.Step 8: issue grant.Depending on the traffic conditions (load) of the preceding router, the flexible priority will be assigned. If a deadlock like conditions of multiple data packets path requests one channel then the priority resolver of arbiter decides the grant to which packets. So flexible priority-based dynamic arbitrations will be implemented. The initial conditions for the resolutions are to read all the requests of input ports that want grant for the same output port and then the arbiter encounters aK×K matrix developed by flexible priority resolver with bits arranged in a triangular array. The grant will be issued to the requested based on the highest priority resolved matrix to the same output port. The row in the matrix competes input requests and its priorities. The scheduling module will study the priorities of each input port request. The arbiter receives updated within the scheduling matrix when the maximum priority input is served by means of making the request which gets the earlier access. Row and column receive inversed for much less precedence for the next round of arbitration. The simulation end result for the arbitration is shown in Figure 10(c) which gives precedence with apropos to the grant generation. The arbiter is implemented using VHDL in Xilinx Vivado 2021.2.1 and simulated with Vivado-IDE.


## 3.1. VCA Arbiter

Congestion avoidance, like a deadlock and livelock, can be handled by the arbiter. Flit bifurcation in routing is done based on the size of the data, the head flit may be one, but the body flits are packet size-dependent. The count is calculated before it reaches the VC (virtual channel). The allocation unit of the VC is done with a head flit. VCA unit allocates the channel for the data packets to travel through different routers. The mechanism of the two stages is illustrated in Figure11.Figure 11
VCA arbitration.


## 3.2. Switching Arbiter

Once VC is allocated to the packets, the central part is to do switch allocation (SA), which leads to reaching the packet to the destination by competing with all the other VC allocated packets. Here, all the flits need to be allocated. To reduce the delay in communication to the destination, a flexible priority resolver is introduced in this proposed architecture. This reduced the computation complexity of allocation among all the VC allocations shown in Figure12. Switch traverse (ST) and link traverse (LT) will lead the granted allocation packets to reach the specified destination.Figure 12
FP switch allocator.


## 3.3. Proposed Arbiter

Most of the existing arbiter designs follow a round robin which rotates the output grants received and precedes the rest Figure10(a). This will increase the burden on the arbiter as the flits increase for large throughputs. The proposed arbiter has a flexible priority resolver which estimates the traffic/load on the arbiter about to come Figure 10(b). Unlike normal RRA, the specific rotation or fixed orientation is predefined here; hence, the time calculation of arbitrations can reduce, and throughput will increase.The priority resolver has flexibility depending on the traffic, like fixed, rotating. If traffic is less and the expected latency in switching is less, then fixed priority can be chosen; if not, rotating priority can be chosen to distribute equal priority to all switching flits. The structure of the algorithm is as follows.


## 3.4. Proposed Arbiter Algorithm

The algorithm below specifies the arbiter’s input request and grants according to flexible priority, depending on the load/traffic buffer channel rout calculation; VCA, SA, ST, and LT are the significant concerns in computing the travel delay. In the proposed arbiter, important computations are done in the stage of priority resolving hence expected low latency with high throughput. First, it verifies all allocated buffers in step 1, finds the density of the traffic load and enables the priority resolver if found large loads in steps 2-3, and assigns mapping of source and destinations by eliminating redundant allocations in steps 4-5. Check the transfer from lower end node to higher in the same process for finding multiple iterations; if all good, enable the transfer in steps 6–8.Algorithm 1
Step 1: check all input buffer requests.Step 2: is the load/traffic more than regular transfer with respect to previous router data.Step 3: chose to assign priority as rotation if traffic increases else, fixed.Step 4: map i/p-port to o/p-port of arbiter for packet transfer.Step 5: check for replication of the same packet assigned to various arbiters.Step 6: check packets of o/p-port mapping to i/p-port according to the assignment.Step 7: verify for the multiple iterations.Step 8: issue grant.Depending on the traffic conditions (load) of the preceding router, the flexible priority will be assigned. If a deadlock like conditions of multiple data packets path requests one channel then the priority resolver of arbiter decides the grant to which packets. So flexible priority-based dynamic arbitrations will be implemented. The initial conditions for the resolutions are to read all the requests of input ports that want grant for the same output port and then the arbiter encounters aK×K matrix developed by flexible priority resolver with bits arranged in a triangular array. The grant will be issued to the requested based on the highest priority resolved matrix to the same output port. The row in the matrix competes input requests and its priorities. The scheduling module will study the priorities of each input port request. The arbiter receives updated within the scheduling matrix when the maximum priority input is served by means of making the request which gets the earlier access. Row and column receive inversed for much less precedence for the next round of arbitration. The simulation end result for the arbitration is shown in Figure 10(c) which gives precedence with apropos to the grant generation. The arbiter is implemented using VHDL in Xilinx Vivado 2021.2.1 and simulated with Vivado-IDE.


## 4. Throughput Assessment

In this paper, the proposed arbiter is designed on a baseline router of NoC, where the RC, VC, and SA are not much modified. Prior prioritizations greatly reduce the burden of arbiter computation and competition for the allocations through a flexible priority resolver. To maximize the throughput, we used a3×3 2D mesh. Input ports of all routers have four buffers of 32-bit length. The network is implemented using VHDL in Xilinx Vivado 2020.2 and simulated with Vivado-IDE. To compute the load calculations, we used a URT and synthetic traffic pattern. The throughput is VC number dependent; as the number of VCs increases, the throughput increases as illustrated in Figures 13 and 14 for URT and synthetic traffic, respectively. The prioritized circuit verifies the traffic load in all interfacing directions and preestimates the best suitable path for transmitting the flits without locking them more time at the buffer. First, the system is tested with low flit injection ratio to high flit injection ratio with uniform random traffic (URT) and then with the synthetic traffic, with more than 10% throughput improvement noticed. Table 1 shows the flit injection ratio versus throughput of existing model and the proposed model. Flexible priority resolver usage in the proposed model has larger throughput at higher flit injection ratios with various traffic conditions. It is observed that there is around 3% to 30% throughput increase with respect to low FIR to high FIR.Figure 13
Throughput under URT. (a) FIR vs. throughput with two VCs, (b) FIR vs. throughput with four VCs, and (c) FIR vs. throughput with eight VCs, respectively.
(a)(b)(c)Figure 14
Throughput under synthetic traffic. (a) FIR vs. throughput with two VCs, (b) FIR vs. throughput with four VCs, and (c) FIR vs. throughput with eight VCs, respectively.
(a)(b)(c)Table 1
Flit injection ratio vs. throughput of existing model and proposed model for various test conditions (FIR and Tp are measured in flit per cycle).
URTSTExisting RRAProposed arbiterExisting RRAProposed arbiter2VCs4VCs8VCs2VCs4VCs8VCs2VCs4VCs8VCs2VCs4VCs8VCsFIRTpFIRTpFIRTpFIRTpFIRTpFIRTpFIRTpFIRTpFIRTpFIRTpFIRTpFIRTp0.000.00000.000.00000.000.00000.000.00000.000.00000.000.00000.000.00000.000.00000.000.00000.000.00000.000.00000.000.00000.010.00480.010.00580.010.00580.010.00510.010.00610.010.00610.010.00490.010.00590.010.00580.010.00550.010.00610.010.00600.020.00890.020.00920.020.00950.020.00910.020.01210.020.01010.020.00880.020.00920.020.00890.020.00920.020.01010.020.00910.030.01090.030.01150.030.01250.030.01120.030.01320.030.01300.030.01100.030.01170.030.01240.030.01130.030.01290.030.01300.040.01180.040.01310.040.01380.040.01230.040.01450.040.01510.040.01190.040.01300.040.01390.040.01240.040.01400.040.01510.050.01290.050.01350.050.01430.050.01370.050.01480.050.01550.050.01310.050.01370.050.01470.050.01390.050.01460.050.01560.060.01420.060.01400.060.01480.060.01460.060.01500.060.01600.060.01430.060.01380.060.01490.060.01480.060.01480.060.01610.070.01450.070.01440.070.01500.070.01490.070.01520.070.01670.070.01450.070.01410.070.01510.070.01500.070.01500.070.01630.080.01460.080.01480.080.01520.080.01520.080.01570.080.01710.080.01460.080.01480.080.01530.080.01530.080.01550.080.01710.090.01500.090.01510.090.01590.090.01590.090.01620.090.01780.090.01510.090.01500.090.01590.090.01600.090.01590.090.01790.100.01520.100.01570.100.01620.100.01620.100.01710.100.01830.100.01530.100.01510.100.01630.100.01630.100.01650.100.01830.110.01550.110.01610.110.01690.110.01650.110.01790.110.01900.110.01560.110.01550.110.01700.110.01670.110.01690.110.02050.120.01560.120.01630.120.01750.120.01670.120.01820.120.02010.120.01570.120.01610.120.01780.120.01690.120.01890.120.02320.130.01580.130.01640.130.01780.130.01690.130.01890.130.02190.130.01580.130.01700.130.01820.130.01700.130.02150.130.02520.140.01600.140.01650.140.01920.140.01740.140.01950.140.02330.140.01610.140.01810.140.02100.140.01750.140.02390.140.0279Table2 shows the synthesis results of the arbiter in comparison with the existing RRA arbiters, which offers a 12% less occupation of the area and a 15.81% reduction in critical latency.Table 2
Feature estimation of arbiter.
DesignArea occupation (μm2)Critical delay (ps)Existing RRA124.6456.4Proposed109.5384.2The future expansions in this model are to work for more throughputs at lower flit injection rates. Further, the area optimization techniques are expected to be implemented for better performance.


## 5. Conclusion

The main feature of the proposed model is to provide high throughput and efficient on-chip communications for multicore architectures. With the proposed arbiter design, it is observed that the area occupation of buffers and critical delays were considerably reduced; hence, the waiting time of the flits at the arbiter buffers will be less, and the total communication time will decrease. Further, as the priorities are resolved before the flits get granted to the arbiter, the load of the arbiter will significantly reduce, and communication will be efficient. Thus, the proposed model improves the throughput in multicore systems like SoC with an efficient arbiter at NoC. This work has a limitation, i.e., area occupation of the die and productivity (throughput) have no more remarkable improvement at low traffic/load in comparison with the existing models. The proposed arbiter is showing good improvement in the throughput at higher data rates; an average of more than 10% throughput improvement is noticed at higher flit injection rates independent of the VCs implemented. Further, the critical delays are reduced to 15.84% with greater throughputs. Besides, the design proves that at higher flit rates the throughput is increasing considerably. Hence, new hopes are increasing to do further research to accommodate more packets per cycle without compromising the system performance. The future design extensions of the proposed model are expected to handle the exceptions in data transmission over on-chip networks and reduce further latency.



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*Source: 2911777-2022-09-05.xml*