# Modeling of Current-Voltage Characteristics of the Photoactivated

Authors: Doron Abraham; Avraham Chelly; David Elbaz; Shimron Schiff; Michah Nabozny; Zeev Zalevsky
Journal: Active and Passive Electronic Components
 (2012)

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## Abstract

An analytical model of the silicon on insulator photoactivated modulator (SOI-PAM) device is presented in order to describe the concept of this novel device in which the information is electronic while the modulation command is optical. The model, relying on the classic Shockley’s analysis, is simple and useful for analyzing and synthesizing the voltage-current relations of the device at low drain voltage. Analytical expressions were derived for the output current as function of the input drain and gate voltages with a parameterization of the physical values such as the doping concentrations, channel and oxide thicknesses, and the optical control energy. A prototype SOI-PAM device having an area of 4μm × 3 μm with known parameters is used to experimentally validate and support the model. Finally, the model allows the understanding of the physical mechanisms inside the device for both dark and under illumination conditions, and it will be used to optimize and to find the performance limits of the device.


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## Body

## 1. Introduction

Silicon-based nanophotonic devices have attracted appreciable attention and effort because of their potential applications in silicon-integrated circuits. Although silicon may be not the ideal platform for optical devices, the usage of silicon is mandatory for the generation of optoelectronic integrated circuitry. The quality of commercial silicon on insulator (SOI) wafers driven by the microelectronics industry still continues to improve while the cost continues to decrease. Moreover, as previously mentioned the compatibility with silicon integrated circuits manufacturing is an important reason for this interest in silicon photonics [1].The optical capabilities are used to overcome some limits of the non optical devices. Those capabilities are high propagation velocity, reduced cross talks and absence of noise coupled by electrical inductance and capacitance [2–4]. Such devices can operate at very low operational power and have parallel processing capabilities [5, 6].In this paper, we present the first analytic model of the previously presented hybrid optical-electrical device, thesilicon on insulator photo-activated modulator (SOI-PAM) [7]. As deduced from its name, the device is controlled by optical command. like a junction field effect transistor (JFET), the information current flows between two terminals (source and drain) in a silicon channel. The device concept relays on the fact that the thickness of depletion layer in the channel, which affects the information current, can be controlled through external illumination and not only by applying a gate voltage.The model was developed for the linear domain of the channel (drain to source) current voltage characteristic and adapted to experimental measurements.In Section2, we describe the operation principle of the SOIPAM device. In Section 3, we present the general assumptions for the model. In Section 4, we derive the analytical model in the depletion mode and in Section 5, we develop unified lineal model and extract its parameters. Section 6 concludes the paper.


## 2. SOI-PAM Device

The device is based on a structure consisting of a thin n-type silicon layer (30 nm) on insulator above p-type substrate (SOI-bonded wafer) [8]. The n-type layer was obtained by compensation of the original low-doped p-type silicon layer using an ion implantation of phosphorus.As depicted in Figure1, the channel is delimited by source and drain ohmic contacts made of n+ doped polysilicon. The length of the channel is about few microns as fabricated in the prototype version of the device [8]. The information channel is insulated from the p-type substrate by a buried oxide layer having a thickness tox of 150 nm (SOI wafer). The device is insulated from the surrounding devices by a thicker thermal field oxide.Figure 1
Schematic cross section of the SOI-PAM device. Like in a field effect device the information current flows through silicon channel that is limited by two terminals (source and drain). The source is connected to ground. Gate voltageVG is applied at sufficient rate to bring the substrate into its deep depletion mode. An oblique illumination generates charges in the p-type substrate.In principle, when a given negative gate potentialVG is applied to the bottom side of the p-type substrate, a negatively charged depletion layer appears under the buried oxide layer. As a result, a positively charged depletion layer appears inside the n-type channel. Since the n-type doping level (donors concentration of Nd of about 1017 cm−3) of the channel is designed to be larger than the p-type substrate (acceptors concentration Na of 1015 cm−3), the thickness of the depletion layer in the n-type area is narrower than the depletion layer in the p-type region. Moreover, the device is designed in such a way that, in dark conditions, the depletion layer in the channel is smaller than the channel thickness so the device is partially depleted and can be considered as normally on, that is, moderately conducting under dark condition and zero gate voltage. Note that the gate voltage should be applied with a sufficiently high frequency (few kHz) or swept at a sufficient rate in order to bring the substrate into the “deep” depletion mode and consequently to avoid the inversion of the channel.If a short pulse of a visible laser illuminates the area under the oxide layer (oblique illumination), the photo generated electrons will accumulate at the bottom silicon-oxide interface and consequently increase the positively charged depletion layer in the channel. With a pulse of sufficient energy, the channel will be cut off. In a future version of the device, a sweeping potential will be added so that the modulation will be limited by the drift time of the photogenerated carriers in a micrometric region rather than by the time consuming recombination process. Assuming a saturation velocity of 107 cm/s and a one micron sweeping length, the drift time is expected to be as small as 10 ps, that is, achievable modulation rates can be as high as 100 GHz.


## 3. General Assumptions

In a similar way used for other field effect devices, the 2D-Poisson’s equation will be solved in one dimension (which is they axis that is being perpendicular to the plane of the Si-SiO2-Si interface) by assuming the Shockley’s Gradual Channel Approximation (GCA) [9]. For small drain voltage values, it is reasonable to assume that the electric field varies more rapidly in the y direction than the variations of the lateral field along the channel direction (x axis) due to the large ratio between the channel length and the buried oxide thickness.The geometry of the device is sketched in Figure1. The channel, having a length L of 3 μm, is assumed to be along the x direction. The thickness of the channel tn is 30 nm and is measured in the y direction. The width of the device W is 4 μm measured in the z direction. The channel potential V(x) is a function of the distance x along the channel.In order to derive an expression for the drain current, it is useful to make some simplifying assumptions.(1)
All the regions of the device are assumed to be uniformly doped.(2)
The current flow occurs only within the nondepleted (neutral) portion of the channel.(3)
The mobility of the carriers is not drain voltage dependent (low field mobility is mainly gate voltage dependent).(4)
The oxide is an ideal insulator such the oxide and interface charges are negligible.(5)
The contact series resistances are negligible.(6)
The generation current is negligible.


## 4. Derivation of the Analytic Model for the Depletion Mode

The Poisson’s equation is solved separately for each region of the SOI-PAM device structure composed by a p-n depleted junction separated by an oxide layer. As supposed in the GCA approximation, the channel voltageV(x) induced by the drain-source bias VDS is added to the applied negative gate voltage VGS according to the following equation: (1)Vn+Vp+Vox=VFB-VGS+V(x),
where Vn,Vp,Vox are the potentials in n-type depleted region, p-type depleted region and the oxide layer respectively. VFB is the Flat Band (FB) bias of the SOI-PAM device that includes the built-in bias of the p-n junction and the work function differences between the contact metals and the silicon regions (substrate and channel, resp.). Oxide and interface charges are considered to be negligible. Finally, we get from (1) that:(2)qNddn22εs+qNadp22εs+qNadptoxεox=VFB-VGS+V(x),
where dn and dp are the depletion thicknesses of the n and p-type areas respectively. εox,εs are the dielectric permittivities of silicon oxide and silicon, respectively. Then, the charge neutrality of the device is expressed in the following equation:(3)Nddn=Nadp.The channel depletion layer thickness,dn(x), can be solved accordingly:(4)dn(x)=α0tn(1+VFB-VGS+V(x)ϕ0-1),
where α0 is defined as the oxide coupling factor (dimensionless):(5)α0=(NaNa+Nd)εstoxεoxtn=0.148
and ϕ0 is the oxide coupling voltage defined as:(6)ϕ0=(NaNdNa+Nd)(εstoxεox)2q2εs=0.155V.We can easily check that the depleteddn is zero for VGS equals VFB, that is, the flat band voltage is the transition between accumulation and depletion modes as for MOS capacitor.The maximum value ofdn(x) equals to tn when the corresponding gate voltage VG, equals to the threshold (or cut off) voltage VT when taken without drain voltage (V(x)=0). Then from   (4) we obtain:(7)VT=VG(dn(x)=tn)|V(x)=0=VFB-ϕoα02(1+2α0)=VFB-φPO(1+2α0)=VFB-9.170V,
where φPO is the internal pinch off voltage for the device without oxide and at zero drain voltage as following:(8)φPO≡ϕoα02=Nd(1+NdNa)q2εstn2=7.076V.Assuming that the drain currentIDS, flowing in the neutral upper part of the depleted channel, is constant along the x axis, we can write that:(9)IDS=qNDWμn[tn-dn(x)]dVdx.By integrating the expression forV(x) between 0 and VDS we get the oxide-modified Shockley’s equation for drain current (as far as VDS<VGS-VT):(10)IDS=gmax⁡[VDS(1+α0)+23φPO{[ϕ0+VFB-VGS]3/2-[ϕ0+VFB-VGS+VDS]3/2}]
where gmax is the maximum value of the conductance (for undepleted channel).(11)gmax⁡=qNdWμnLtn.One can then derive the channel conductancegd of the SOI-PAM device from (10):(12)gd=∂IDS∂VDS=gmax⁡[1+α0-VFB+ϕ0-VGS+VDSφPO].In the depleted case (whereVDS≪VFB+ϕ0-VGS, that is, VGS≪VFB+ϕ0-VDS) the channel conductance does not longer depend on VDS but on VGS. So, according to (12) and (4), the conductance can be simply related to the closure of the channel by the depletion region entirely controlled by VGS as following:(13)gd=gmax⁡[tn-dn(VGS)tn].At the saturation point, for a givenVGS, the drain current reaches its maximum value, so that the saturation voltage VDS,sat is obtained by zeroing the channel conductance gd, in   (12), yielding:(14)VDS,sat⁡=ϕPO(1+2α0)-VFB+VG=VG-VT≡VGT.From (7) the threshold voltage VT is expected to be high in the device, so the saturation will not occurred for the relatively small values of VDS considered in the depletion mode.According the above equations, we can derive some qualitative expectations on the influence of material parameters on the conductancegd. According to (11) and (12)  gd is increased by increasing: the channel doping concentration Nd or the channel thickness tn or also the buried oxide thickness tox. Also, gd is increased by decreasing the substrate concentration Na. Finally, we can notice that for the limit case where the oxide layer vanishes (tox→0) both the silicon oxide coupling factor in  (5) and the silicon oxide coupling voltage in (6) vanish while VFB equals to the junction’s built-in voltage φi. So, the above expressions  (12)–(14) are reduced to those describing a classic JFET n-channel device (for which Na≫Nd).


## 5. The Unified Linear Model and Parameters Extraction

### 5.1.IDS-VGS Characteristics and Operation Modes

A prototype of the constructed SOI-PAM device was experimentally characterized using the Keithley SCS-4200 parameter analyzer. As seen in Figure2, the IDS-VGS characteristics are measured over [−4 V, 4 V] VGS range for several low VDS values (0.1–0.5 V) in order to get a linear relation between IDS and VDS.ExperimentalIDS-VGS characteristics: linear scale in (a) and semi-log in (b). The measurements are taken in dark conditions (solid lines) for several values of VDS between 0.1 V and 0.5 V. The dotted lines result from the calculated current according to the proposed unified model. For clarity, only results obtained for VDS=0.1 V and VDS=0.5 V are presented. The VGS  domains of the operation modes are specified in (b).
(a)(b)In this section we develop a unified model of theIDS-VGS characteristics based on the MESFET unified model [9] available for the three operation modes of the device and at low VDS values. A similar approach was used by Colinge for a SOI p-channel MOSFET [10].(1) Accumulation Mode (VGS>VFB>0)
The n-channel is conducting through the accumulation layer of majority carriers located at the top of the silicon-buried oxide interface. The electron concentration is determined byVGS-VFB.(2) Depletion Mode (VT<VGS<VFB)
The n-channel is partially depleted but is still conducting through the squeezed neutral region of the channel above the depletion region.(3) Diffusion Mode (VGS<VT)
The n-channel is fully depleted; there is a small diffusion current flowing from then+ source region through the n depleted channel. The current is controlled exponentially by the gate voltage as observed in MESFET devices [9]. The VGS sweep is performed quickly enough such the channel inversion is not achieved so the channel is considered in a “deep depletion” state.We will now express the drain current model for each one of those mode as following:(1) Accumulation Mode (VGS>VFB>0)
The linear drain current can be described by the following relation as observed in the pseudo-MOSFET device [11]:
(15)IDS=WLμnCox(VGS-VFB)VDS,
where Cox is the buried oxide capacitance per unit area, given by:
(16)Cox=εoxtox=23nF/cm2.
From the linear extrapolation at positive values ofVGS, we can extract the values of VFB (~0.1 V) and μn (~700 cm2/Vs) which are roughly constant with VDS. The extracted mobility value is found consistent with the similar thin pseudo SOI-MOSFET [11] having the same silicon film thickness and the doping concentration range of the n-channel (1017 cm−3). However due to the non uniformity of the ion implant process, the doping value is not precisely known for each device. Moreover due to the rapid variation of the mobility with doping concentration in this range (1017 cm−3), the doping concentration cannot be extracted accurately from the mobility.(2) Depletion Mode (VT<VGS<VFB)
The drain current in the partially depleted channel can be rewritten by the following relation [9]:
(17)IDSa=qnsaμnWLVDS
with nsa being the electron sheet density in the channel above the threshold voltage VT. This density is simply given by:
(18)nsa=Nd(tn-dn)
while dn is the thickness of the depleted region in the channel at low VDS so it is mainly a square root function of VGS as given by  (4).(3) Diffusion Mode (VGS<VT)
ForVDS positive values, the saturation condition (VDS>VGS-VT) is always satisfied in this mode, so the drain current in the fully depleted channel is being described as a saturated diffusion current (independent of VDS) according to [9]:
(19)IDSb=qnsbDnWL=qnsbμnWLVth,
where Vth  is the thermal voltage (25.6 mV at room temperature) and nsb is the electron sheet density in the channel below the threshold voltage VT.  For VDS larger than Vth, nsb is defined by a Boltzmann’s distribution like:
(20)nsb=n0exp⁡⁡(VGS-VTηVth)<n0
with n0 being the electron sheet density at VT [9]:
(21)n0=(CsiCoxCsi+Cox)ηVthq.AndCSi is the fully depleted silicon channel capacitance per unit area at VT, given by:(22)Csi=εsitn=345nF/cm2=15Cox,η is the ideality factor extracted from the slope of the sub-threshold exponential fit and is evaluated to be 11.5 as the mean value over several VDS values as seen in Figure 2(b). This value is comparable to the CSi/Cox ratio as also reported in the subthreshold current model for MOSFET devices [9].According to (19) and (20), the threshold voltage VT can be extracted as the departure point of the exponential fit [9] and is found to be −2.3 V as shown in Figure 2(b) for VDS equals 0.1 V. The corresponding threshold current IDsb,T is 25 nA which is the maximum diffusion current allowed in the channel.However, according to (7), the expected value of VT is −9 V. Actually, the measured current is not vanishing at −9 V. Moreover, the depletion current IDSa is a power law function of VGS while the diffusion current IDSb is an exponential decay with VGS below −2.3 V. So the diffusion is the limiting process in the subthreshold mode. Consequently, the measured drain current can be modeled by the following expression [9]:(23)IDS,depl=IDSaIDSbIDSa+IDSb.
Experimentally (see Figure 2(b)), IDSb is found to be slightly VDS dependent in spite of the saturation condition assumed above. In fact, we can link this dependence to those of VT with VDS at low VDS values. This is similar to the DIBL effect found in MOSFET’s devices [9]. The VT values are extracted from the threshold current IDSb,T fixed at 25 nA for each IDS-VGS from Figure 2(b). For instance, for VDS equals 0.5 V, the extracted VT value is −2.6 V. These values are used in the model.


### 5.2. Fine Tuning of the Doping Concentration

Due to the lack of accuracy of the doping concentration, this latter can be refined in order that  (23) will best fit the measured dain current in Figure 2(b) in particular at VDS=0.5 V. The matching value for Nd is found as 8 × 1016 cm−3, instead of the initial designed value of 1017 cm−3, but still reasonable in regard to the doping distribution. This tuning is performed according the mobility voltage-dependent model as presented below.


### 5.3. Mobility Voltage Dependence

The electron mobility can be evaluated from the extracted threshold voltageVT (−2.3 V) using (19) and (20) as follows:(24)μn(VT)=(qn0IDSb,TWLVth)=200cm2/Vs.This mobility value is found to be much lower than the value measured in the accumulation mode (700 cm2/Vs). This is not surprising since the low field mobility in the depletion mode is reported to increase rapidly for gate voltages above VT in MESFET devices [12]. This should be explained by the decreasing of the depletion layer while increasing VGS above VT. According to this reference, we can expect a linear relation of the mobility with VGS  in order to match the experimental IDS-VGS characteristics in the depletion mode like(25)μn(VGS)=μ0+θ(VGS-VT).Another assumption is necessary for the physical coherence of the proposed model. On the one hand, the mobility cannot vanish withVGS  so it should be pinned to the lower threshold limit value of 200 cm2/Vs even for VGS values below VT. On the other hand, for the continuity sake, the depletion current above VT,IDSa, should match the accumulation current voltage [11]. So  the current matching between the accumulation and the depletion current (for which dn~0) may occur at a specific “effective” flat band bias V̲FB defined as follows:(26)IDS,acc=WLμnCox(V̲FB-VFB)VDS=IDSa=qNdtnμnWLVDS,
the expression of V̲FB is consequently given by(27)V̲FB=VFB+qNDCoxtn=1.77V,
with: ND=8×1016 cm−3.This “effective” flat band biasV̲FB value actually defines the lower limit of VGS for which the accumulation current may be described by (15). Also, V̲FB defines the upper limit of VGS for which the depletion current may be described by  (10).The mobility variation withVGS can finally be modeled by using the following step function:(28)μn(VGS)={μ0≈200cm2/VS,VGS≤VT,θ(VGS-VT),θ≈175cm2/VS,VT≤VGS≤V̲FB,μn≈700cm2/VS,VGS≥V̲FB.The comparison between the experimental characterization and the unified model as described in this section shows a satisfying matching forVDS values of 0.1 V and 0.5 V as can be seen from Figures 2(a) and 2(b).


### 5.4.IDS-VDS Characteristics

In order to confirm and complete the current-voltage model of the SOI-PAM device, the measuredIDS-VDS characteristics are presented in Figure 3. The unified model is used to simulate these characteristics up to the saturation region for VGS equals −1, 0, 1, 2, and 3 V, respectively, and for positive VDS values up to 3 V. The linear behavior of the drain current in the saturation region can be interpreted as a drain-induced channel length modulation [9].Figure 3
ExperimentalIDS-VDS characteristics: the measurements are taken in dark conditions (solid lines) for several values of VGS between 3 V and −1 V. The dotted lines result from the calculated current according to the proposed unified model.ForVGS equals 3 V, the device is in the accumulation mode so the corresponding IDS-VDS characteristic is well fitted by   (15) by adding the parabolic term in VDS up to the saturation region as used for MOSFET device:(29)IDS=WLμnCox[(VGS-VFB)VDS-VDS22].The saturation voltage is then defined as(30)VDS,sat⁡=VGS-VFB
with VFB equals to 0.1 V.The measured saturation voltage (Figure3) matches the expected value (−2.9 V).ForVGS equals 2 V, the device is still in the accumulation mode, so the previous equation is valid till the VGS equals V̲FB, that is, 1.77 V as extracted from   (26). However, a small discrepancy is observed above 1 V near the saturation region. This may happen due to an enhancement of the channel length modulation effect as mentioned above [9].ForVGS equals 1 V, the device is now in the depletion mode, so (17) can be used to fit the corresponding characteristic by taking μn value of 577 cm2/Vs as estimated from   (28). The saturation voltage VDS,sat measured as 2.3 V on Figure 3, is overestimated by the modeled VGS-VT value (3.3 V from   (14)) may be due to the velocity saturation [9] that was not included in the present model.ForVGS equals 0 V, the contribution of the diffusion current is negligible and   (17) is still sufficient to fit the corresponding characteristic by taking μn value of 402 cm2/Vs as estimated from   (28) but with slight overestimation of the current value and of VDS,sat as noticed above.ForVGS equals −1 V, the contribution of the diffusion current is now not negligible and   (23) is used to fit the corresponding characteristic by taking μn value of 227 cm2/Vs as estimated from (28) but again with slight overestimation of the current value and of VDS,sat as noticed above.


### 5.5. Simulation of the Illumination Effect

By synchronously and directionally illuminating the p-type substrate, the free photogenerated electrons concentration can be significantly and instantly increased to build the inversion (negatively charged) layer under the silicon oxide. Consequently, the positively charged depletion layer in the n-type channel is widening and could fully deplete the channel.We can express the n-type drop voltage dependency by the amount of electrons that are generated by the applied illumination. The number of incident photonsNph is related to the total energy Eph as:(31)Eph=Nphhcλ,
where h is Planck’s constant, c is the speed of light and λ is the photon’s wavelength. The capacitances of the partially depleted silicon layer CSi and the buried oxide Cox are associated in series, so the total capacitance per unit area is(32)C=CoxCsiCox+Csi[F/cm2].Then, channel’s voltage drop, that is, the “illumination induced voltage” can be expressed by(33)Vph=QphCWL=qηλNphCWL,
where ηλ is the quantum efficiency of silicon for the given λ. So, for relatively low illumination levels, the thickness of the channel depletion layer dn(x) can be increased by the illumination-induced voltage Vph according to  (4)(34)dn(x)=α0tn(1+VFB-VGS+V(x)+Vphϕ0-1).Consequently, the depleted channel region will grow and the depletion mode currentIDSa will decrease when the illumination energy is increased, as expected from the operation principle of the device. For the actual device parameters, we can evaluate from (34) that the channel will be fully closed (for small VDS) by taking Vph equals 4.5 V, that is, by supplying 75,000 photons (assuming an ideal unity quantum efficiency). In terms of light power, taking for instance, a green diode laser (λ = 532 nm), it would be estimated to 2.8 mW per device for a 10 ps pulse. This value can be minimized by decreasing the size of the device and increasing the oxide thickness.Experimentally, by simply exposing the device to room (fluorescent) light, we can notice a slight positive shift of the wholeIDS-VGS characteristics as shown in Figure 4. This evidence roughly the light-induced decreasing of the drain current as expected from the present model.Figure 4
MeasuredIDS-VGS characteristics (semilog) taken at dark (solid line) and under room light illumination (dashed line). The dashed line is slightly shifted to more positive VGS values especially in the depletion and the diffusion modes (VGS<1.77 V).Of course, a more in depth measurements of this photoelectric modulation should be performed to validate the model more accurately and will be the object of further publication.


## 5.1.IDS-VGS Characteristics and Operation Modes

A prototype of the constructed SOI-PAM device was experimentally characterized using the Keithley SCS-4200 parameter analyzer. As seen in Figure2, the IDS-VGS characteristics are measured over [−4 V, 4 V] VGS range for several low VDS values (0.1–0.5 V) in order to get a linear relation between IDS and VDS.ExperimentalIDS-VGS characteristics: linear scale in (a) and semi-log in (b). The measurements are taken in dark conditions (solid lines) for several values of VDS between 0.1 V and 0.5 V. The dotted lines result from the calculated current according to the proposed unified model. For clarity, only results obtained for VDS=0.1 V and VDS=0.5 V are presented. The VGS  domains of the operation modes are specified in (b).
(a)(b)In this section we develop a unified model of theIDS-VGS characteristics based on the MESFET unified model [9] available for the three operation modes of the device and at low VDS values. A similar approach was used by Colinge for a SOI p-channel MOSFET [10].(1) Accumulation Mode (VGS>VFB>0)
The n-channel is conducting through the accumulation layer of majority carriers located at the top of the silicon-buried oxide interface. The electron concentration is determined byVGS-VFB.(2) Depletion Mode (VT<VGS<VFB)
The n-channel is partially depleted but is still conducting through the squeezed neutral region of the channel above the depletion region.(3) Diffusion Mode (VGS<VT)
The n-channel is fully depleted; there is a small diffusion current flowing from then+ source region through the n depleted channel. The current is controlled exponentially by the gate voltage as observed in MESFET devices [9]. The VGS sweep is performed quickly enough such the channel inversion is not achieved so the channel is considered in a “deep depletion” state.We will now express the drain current model for each one of those mode as following:(1) Accumulation Mode (VGS>VFB>0)
The linear drain current can be described by the following relation as observed in the pseudo-MOSFET device [11]:
(15)IDS=WLμnCox(VGS-VFB)VDS,
where Cox is the buried oxide capacitance per unit area, given by:
(16)Cox=εoxtox=23nF/cm2.
From the linear extrapolation at positive values ofVGS, we can extract the values of VFB (~0.1 V) and μn (~700 cm2/Vs) which are roughly constant with VDS. The extracted mobility value is found consistent with the similar thin pseudo SOI-MOSFET [11] having the same silicon film thickness and the doping concentration range of the n-channel (1017 cm−3). However due to the non uniformity of the ion implant process, the doping value is not precisely known for each device. Moreover due to the rapid variation of the mobility with doping concentration in this range (1017 cm−3), the doping concentration cannot be extracted accurately from the mobility.(2) Depletion Mode (VT<VGS<VFB)
The drain current in the partially depleted channel can be rewritten by the following relation [9]:
(17)IDSa=qnsaμnWLVDS
with nsa being the electron sheet density in the channel above the threshold voltage VT. This density is simply given by:
(18)nsa=Nd(tn-dn)
while dn is the thickness of the depleted region in the channel at low VDS so it is mainly a square root function of VGS as given by  (4).(3) Diffusion Mode (VGS<VT)
ForVDS positive values, the saturation condition (VDS>VGS-VT) is always satisfied in this mode, so the drain current in the fully depleted channel is being described as a saturated diffusion current (independent of VDS) according to [9]:
(19)IDSb=qnsbDnWL=qnsbμnWLVth,
where Vth  is the thermal voltage (25.6 mV at room temperature) and nsb is the electron sheet density in the channel below the threshold voltage VT.  For VDS larger than Vth, nsb is defined by a Boltzmann’s distribution like:
(20)nsb=n0exp⁡⁡(VGS-VTηVth)<n0
with n0 being the electron sheet density at VT [9]:
(21)n0=(CsiCoxCsi+Cox)ηVthq.AndCSi is the fully depleted silicon channel capacitance per unit area at VT, given by:(22)Csi=εsitn=345nF/cm2=15Cox,η is the ideality factor extracted from the slope of the sub-threshold exponential fit and is evaluated to be 11.5 as the mean value over several VDS values as seen in Figure 2(b). This value is comparable to the CSi/Cox ratio as also reported in the subthreshold current model for MOSFET devices [9].According to (19) and (20), the threshold voltage VT can be extracted as the departure point of the exponential fit [9] and is found to be −2.3 V as shown in Figure 2(b) for VDS equals 0.1 V. The corresponding threshold current IDsb,T is 25 nA which is the maximum diffusion current allowed in the channel.However, according to (7), the expected value of VT is −9 V. Actually, the measured current is not vanishing at −9 V. Moreover, the depletion current IDSa is a power law function of VGS while the diffusion current IDSb is an exponential decay with VGS below −2.3 V. So the diffusion is the limiting process in the subthreshold mode. Consequently, the measured drain current can be modeled by the following expression [9]:(23)IDS,depl=IDSaIDSbIDSa+IDSb.
Experimentally (see Figure 2(b)), IDSb is found to be slightly VDS dependent in spite of the saturation condition assumed above. In fact, we can link this dependence to those of VT with VDS at low VDS values. This is similar to the DIBL effect found in MOSFET’s devices [9]. The VT values are extracted from the threshold current IDSb,T fixed at 25 nA for each IDS-VGS from Figure 2(b). For instance, for VDS equals 0.5 V, the extracted VT value is −2.6 V. These values are used in the model.


## 5.2. Fine Tuning of the Doping Concentration

Due to the lack of accuracy of the doping concentration, this latter can be refined in order that  (23) will best fit the measured dain current in Figure 2(b) in particular at VDS=0.5 V. The matching value for Nd is found as 8 × 1016 cm−3, instead of the initial designed value of 1017 cm−3, but still reasonable in regard to the doping distribution. This tuning is performed according the mobility voltage-dependent model as presented below.


## 5.3. Mobility Voltage Dependence

The electron mobility can be evaluated from the extracted threshold voltageVT (−2.3 V) using (19) and (20) as follows:(24)μn(VT)=(qn0IDSb,TWLVth)=200cm2/Vs.This mobility value is found to be much lower than the value measured in the accumulation mode (700 cm2/Vs). This is not surprising since the low field mobility in the depletion mode is reported to increase rapidly for gate voltages above VT in MESFET devices [12]. This should be explained by the decreasing of the depletion layer while increasing VGS above VT. According to this reference, we can expect a linear relation of the mobility with VGS  in order to match the experimental IDS-VGS characteristics in the depletion mode like(25)μn(VGS)=μ0+θ(VGS-VT).Another assumption is necessary for the physical coherence of the proposed model. On the one hand, the mobility cannot vanish withVGS  so it should be pinned to the lower threshold limit value of 200 cm2/Vs even for VGS values below VT. On the other hand, for the continuity sake, the depletion current above VT,IDSa, should match the accumulation current voltage [11]. So  the current matching between the accumulation and the depletion current (for which dn~0) may occur at a specific “effective” flat band bias V̲FB defined as follows:(26)IDS,acc=WLμnCox(V̲FB-VFB)VDS=IDSa=qNdtnμnWLVDS,
the expression of V̲FB is consequently given by(27)V̲FB=VFB+qNDCoxtn=1.77V,
with: ND=8×1016 cm−3.This “effective” flat band biasV̲FB value actually defines the lower limit of VGS for which the accumulation current may be described by (15). Also, V̲FB defines the upper limit of VGS for which the depletion current may be described by  (10).The mobility variation withVGS can finally be modeled by using the following step function:(28)μn(VGS)={μ0≈200cm2/VS,VGS≤VT,θ(VGS-VT),θ≈175cm2/VS,VT≤VGS≤V̲FB,μn≈700cm2/VS,VGS≥V̲FB.The comparison between the experimental characterization and the unified model as described in this section shows a satisfying matching forVDS values of 0.1 V and 0.5 V as can be seen from Figures 2(a) and 2(b).


## 5.4.IDS-VDS Characteristics

In order to confirm and complete the current-voltage model of the SOI-PAM device, the measuredIDS-VDS characteristics are presented in Figure 3. The unified model is used to simulate these characteristics up to the saturation region for VGS equals −1, 0, 1, 2, and 3 V, respectively, and for positive VDS values up to 3 V. The linear behavior of the drain current in the saturation region can be interpreted as a drain-induced channel length modulation [9].Figure 3
ExperimentalIDS-VDS characteristics: the measurements are taken in dark conditions (solid lines) for several values of VGS between 3 V and −1 V. The dotted lines result from the calculated current according to the proposed unified model.ForVGS equals 3 V, the device is in the accumulation mode so the corresponding IDS-VDS characteristic is well fitted by   (15) by adding the parabolic term in VDS up to the saturation region as used for MOSFET device:(29)IDS=WLμnCox[(VGS-VFB)VDS-VDS22].The saturation voltage is then defined as(30)VDS,sat⁡=VGS-VFB
with VFB equals to 0.1 V.The measured saturation voltage (Figure3) matches the expected value (−2.9 V).ForVGS equals 2 V, the device is still in the accumulation mode, so the previous equation is valid till the VGS equals V̲FB, that is, 1.77 V as extracted from   (26). However, a small discrepancy is observed above 1 V near the saturation region. This may happen due to an enhancement of the channel length modulation effect as mentioned above [9].ForVGS equals 1 V, the device is now in the depletion mode, so (17) can be used to fit the corresponding characteristic by taking μn value of 577 cm2/Vs as estimated from   (28). The saturation voltage VDS,sat measured as 2.3 V on Figure 3, is overestimated by the modeled VGS-VT value (3.3 V from   (14)) may be due to the velocity saturation [9] that was not included in the present model.ForVGS equals 0 V, the contribution of the diffusion current is negligible and   (17) is still sufficient to fit the corresponding characteristic by taking μn value of 402 cm2/Vs as estimated from   (28) but with slight overestimation of the current value and of VDS,sat as noticed above.ForVGS equals −1 V, the contribution of the diffusion current is now not negligible and   (23) is used to fit the corresponding characteristic by taking μn value of 227 cm2/Vs as estimated from (28) but again with slight overestimation of the current value and of VDS,sat as noticed above.


## 5.5. Simulation of the Illumination Effect

By synchronously and directionally illuminating the p-type substrate, the free photogenerated electrons concentration can be significantly and instantly increased to build the inversion (negatively charged) layer under the silicon oxide. Consequently, the positively charged depletion layer in the n-type channel is widening and could fully deplete the channel.We can express the n-type drop voltage dependency by the amount of electrons that are generated by the applied illumination. The number of incident photonsNph is related to the total energy Eph as:(31)Eph=Nphhcλ,
where h is Planck’s constant, c is the speed of light and λ is the photon’s wavelength. The capacitances of the partially depleted silicon layer CSi and the buried oxide Cox are associated in series, so the total capacitance per unit area is(32)C=CoxCsiCox+Csi[F/cm2].Then, channel’s voltage drop, that is, the “illumination induced voltage” can be expressed by(33)Vph=QphCWL=qηλNphCWL,
where ηλ is the quantum efficiency of silicon for the given λ. So, for relatively low illumination levels, the thickness of the channel depletion layer dn(x) can be increased by the illumination-induced voltage Vph according to  (4)(34)dn(x)=α0tn(1+VFB-VGS+V(x)+Vphϕ0-1).Consequently, the depleted channel region will grow and the depletion mode currentIDSa will decrease when the illumination energy is increased, as expected from the operation principle of the device. For the actual device parameters, we can evaluate from (34) that the channel will be fully closed (for small VDS) by taking Vph equals 4.5 V, that is, by supplying 75,000 photons (assuming an ideal unity quantum efficiency). In terms of light power, taking for instance, a green diode laser (λ = 532 nm), it would be estimated to 2.8 mW per device for a 10 ps pulse. This value can be minimized by decreasing the size of the device and increasing the oxide thickness.Experimentally, by simply exposing the device to room (fluorescent) light, we can notice a slight positive shift of the wholeIDS-VGS characteristics as shown in Figure 4. This evidence roughly the light-induced decreasing of the drain current as expected from the present model.Figure 4
MeasuredIDS-VGS characteristics (semilog) taken at dark (solid line) and under room light illumination (dashed line). The dashed line is slightly shifted to more positive VGS values especially in the depletion and the diffusion modes (VGS<1.77 V).Of course, a more in depth measurements of this photoelectric modulation should be performed to validate the model more accurately and will be the object of further publication.


## 6. Conclusions

In this paper, we have derived a unified analytical model of theIDS-VGS and IDS-VDS characteristics for whole the operation modes of the SOI-PAM device matching the linear IDS-VGS domain.The analysis of the depletion mode is based on the classical Shockley’s model but originally adapted to the presence of buried oxide thickness between the n-type channel and the p-type substrate.The effect of the light on the channel current modulation could be simply expressed as a positive shift of the gate voltage, and a qualitative behavior of the modulation has been demonstrated.



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*Source: 276145-2012-04-04.xml*