# A Robust Low-Voltage On-Chip LDO Voltage Regulator in 180 nm

Authors: Sreehari Rao Patri; K. S. R. Krishna Prasad
Journal: VLSI Design
 (2008)

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## Abstract

This paper proposes a capacitor-less LDO with improved steady-state response and reduced transient overshoots and undershoots. The novelty in this approach is that the regulation is improved to a greater extent by the improved error amplifier in addition to improved transient response against five vital process corners. Also entire quiescent current required is kept below 100μA. This LDO voltage regulator provides a constant 1.2 V output voltage against all load currents from zero to 50 mA with a maximum voltage drop of 200 mV. It is designed and tested using Spectre, targeted to be fabricated on UMC 180 nm.


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## Body

## 1. Introduction

Exponential  increase in  the
usage of the  portable hand-held battery-operated devices led the designers to focus  on the power management techniques. The
low-dropout (LDO) linear  regulator is widely used  in power management due to
its low noise, precision output, and fast transient response. Due  to the ever increasing demand for low
power consumption, the regulators’ specification is  to be modified with very
low dropout, low quiescent, and fast transient responses. Also “fully integrable
system” or “system on chip” has been the most desirable aspect of any design
solutions. High current efficiency is one of the major
factors as it leads to improvement of battery life. All these factors motivate
the designers towards the fully integrable LDO voltage regulators.Conventional LDOs are inherently
unstable at no load currents. A large output capacitor and its equivalent
series resistance (ESR) are required to achieve the dominant pole compensation
and insert a zero to cancel the nondominant pole. This method has two drawbacks:
first, the large off-chip capacitor
increases pin count, and
it occupies large board space, thus increasing cost. Thus it is not
suitable for SOC. Compensation usingRESR is disadvantageous as it
varies with temperature, and RESR does not have wide range of
values. The second drawback
is that increasing RESR increases overshoot while decreasing RESR moves zero to high frequency, decreasing phase margin. Figure 1 illustrates the
process.Figure 1
Conventional LDO regulator
compensation.The capacitor-less LDO [1] as
shown in Figure 2, on the other hand, maintains good stability and transient
response at low load currents. A fast transient path is required since the
system gain bandwidth was relatively low in frequency. This paper concentrates
on the design of the regulator with 180 nm as against 0.35 micrometer in [1].
The proposed regulator design not only overcomes the stability issues in migrating
from 0.35 micron process to 180 nm, but also improves line regulation and load
regulation by improving the error amplifier.Figure 2
Basic capacitor-less LDO concept.


## 2. Design Issues

Major issues involved in the design of LDO
voltage regulator are stability and transient response.


## 2.1. Stability

Presence of multiple poles definitely degrades the stability of any
closed loop system. The uncompensated capacitor-less LDO consists of two major
poles, namely, one at the output of the error amplifierP1 and the
other is the LDO output pole (P2) which solely depends on the load
current. In general, the error amplifier
individually has at least one pole at high frequency. The pole at low frequency
depends on the output  impedance of the error  amplifier. The equivalent pass
transistor gate to source capacitance along with the CGD which is
multiplied by the gain of the pass transistor (miller effect) pulls the error
amplifier pole to low frequencies. Thus location of pole P1 is given
by (1)P1=1R1.(C1+CGS+ApassCGD), where R1, C1 are the
error amplifier output resistance and capacitance, respectively, and Apass is the gain of the pass transistor. The values of CGS and CGD are
in the range of a few tens of picofarads. The value of R1 is to be chosen to be
relatively large to yield
large DC gain in order to facilitate better regulation. Though the gain of the
pass transistor  varies with load current causing the P1 to vary, it
is less sensitive to load current variation when compared to the output pole (P2).
Pass transistor transconductance Gmp increases with load current whereas RDS decreases
with the same current. This implies that Apass does not change significantly with load
current while P2, which depends mainly on RDS, is very
sensitive to load current variations.
Therefore, when load current is low, the pole P2 will be
pushed well below the unity gain frequency. Eventually, the capacitor-less LDO
tends to be stable at no load condition. In addition, the CGD introduces an RHP zero Z1(=Gmp/CGD). This
also degrades stability, since this feed forward zero reduces the phase margin.
The RHP zero attracts complex poles to the right-hand side of the S-plane which
degrades the loop stability. Hence, RHP zero should be located at high
frequencies relative to unity gain frequency. This demands the pole P1 at the error amplifier output to be made more dominant. This paves the way for
the unity gain frequency to be pulled away from the RHP zero.


## 2.2. Transient Response

Transient response consists of two parts: undershoots/overshoots
and settling time.While there is a change in load current
demand, error amplifier cannot change the pass transistor gate input voltage
quickly due to limited current (power consumption) and large gate capacitance. So
the pass transistor cannot supply instantaneously the load current demanded. Had
there been a large external capacitor, it would have supplied the demanded
current instantaneously that smoothes out the ripple to a major extent. But the
on-chip LDO cannot
have the luxury of large capacitor. Consequently, output voltage overshoots or
dips in response to sudden decrement or increment of load current,
respectively.


## 3. Architecture Tailor-Made for On-Chip LDO

The major design issues of the capacitor-less
LDO as mentioned in the previous section are as follows. One is to contain the
magnitude of overshoots and undershoots. The second one is to improve the
regulator’s stability. The stability issue is addressed by pushing the pole at
the error amplifier output towards the origin. If the error amplifier output
impedance is made large, it can be conveniently pushed towards origin. Folded
cascode amplifier is proposed to be used as an error amplifier against the
conventional two-stage
amplifier proposed in [1] for this purpose. Usage of the folded cascode
has several benefits. It provides large output resistance for the error
amplifier as desired. Also the large gain offered by it improves regulation
characteristic. In addition, it also yields better stability relative to
multistage (multipole) amplifier. Stabilization is further improved by the usage
of the technique [2]. The corresponding architecture is shown in Figure 3.Figure 3
The architecture of the proposed LDO.


## 3.1. Error Amplifier Design

The
proposed architecture employs an optimally designed gain boosting topology for
the error amplifier as shown in Figure4. Requisite gain is deduced from
steady state specifications which is evaluated be 70 dB for a line regulation
of 0.01%. The transconductance of the driving ransistor gm1 is
calculated from the gain bandwidth specification which is chosen to be 200 KHz
for satisfactory transient response using GBW=gm1/CL,
where CL=40pF (pass transistor gate capacitance). The output
resistance Rout is calculated from gain. Bias current for this stage
is chosen to be 20μA. Divide the current in the ratio IDM1:IDM6=3:1. Sizes of M6 and M7 are calculated from Rout and ID6. Sizes of the remaining transistors are calculated to
maintain the appropriate biasing currents.Figure 4
Schematic
of error amplifier.


## 3.2. Pass Transistor Design

The size of the  pass transistor is
decided from the dropout voltage by making use of the relation(2)Vdropout=VDSAT=2⋅IMAXμp⋅Cox⋅(W/L). The dropout voltage is chosen as
200 mV and
maximum load current is 50 mA. Substitution of UMC180 nm model parameters yields W/L=65,000.


## 3.3. Fast Path Design

A differentiator serving as a fast path [1]
is employed (last section of Figure 3) that charges or discharges the gate
capacitor of pass transistor along with the error amplifier. This decreases the
response time for the pas transistor of LDO to react with load current changes,
which in turn reduces the undershoot and overshoot. The capacitor CF connected between output of LDO and gate of pass transistor serves
as a differentiator. The value of CF can be calculated using (3)CF=ΔIloadΔVoutCGSgm,pass,with CGS=15pF, GMP=300μA/V,  ΔVOUT=100mV, ILoad=50mA, and CF=25nF.The requiredCF is apparently
large and it moves the RHP zero to lower frequencies which effects stability, since new RHP zero=GMP/(CGD+CF).
This capacitor value is further reduced by making use of a simple auxiliary
circuit that consists of simple resistor and an amplifier (Gmf). The
resistor Rz converts the capacitive current to voltage and the Gmf converts this current back to current. It is assumed that the parasitic pole
1/RZCf is located at a very high frequency. Thus, this
arrangement increases the effect of Cf since the effective Cf is equal to
GmfRzCf. Thus, the required value of Cf can be reduced by the factor ofGmfRz and the feed forward path created by the Cf is
eliminated.


## 3.4. Bandgap Reference and Biasing Circuits

The
LDO requires a voltage reference as shock voltage is compared and correction is
made accordingly. Hence the voltage reference should be carefully designed to
provide a 600 mV constant voltage against process and
temperature variations. So a low-voltage BGR is designed with the architecture
shown in Figure5. In this architecture, an op-amp [1] is designed with input
common mode range 650 mV which is generated using voltage VBE across
diode connected BJTs.  The gain bandwidth GBW is chosen to
be greater than 1 MHz for this op-amp that keeps the settling time on the order
of microsecond(s). The corresponding circuit is shown in Figure 6. In this
circuit, R2a=R2a is calculated taking quiescent current
into consideration, and  then R2a/R1 ratio is adjusted for making reference voltage
less dependent on temperature. The
resistor R3 is scaled to get the required reference voltage. The
different bias voltages required for the entire system are obtained from the
bias circuit [3] shown in Figure 7 which provides constant required voltages
against temperature variations.Figure 5
Low-voltage bandgap reference circuit.Figure 6
Low-voltage BGR internal op-amp.Figure 7
Circuit that generates requisite bias voltages constant
against temperature and process variations.The temperature
and supply independent constantgm biasing circuit [3] is designed
by taking VDSAT drawn from the dropout voltage specification which is
200 mV and
bias current for this section is allocated to be 2.5μA from power considerations. The various
transistor dimensions that
yield the requisite bias voltages are chosen as follows.For PMOS,(W/L)P,i with i=1,2,3,4,5,6 are chosen to have identical values while (W/L)P7<0.25*(W/L)P1. Similarly for NMOS,  (W/L)N,i with i=1,2,3,5,6 are chosen to be
identical whereas (W/L)N4=4*(W/L)N1, RBIAS=1/GM1, and (W/L)N7<0.25*(W/L)N1. Various salient design parameters
are listed in Table 1.Table 1
Salient design parameters.
Design parametersError amplifierBias circuitTransistor sizing (units in microns unless otherwise specified)M1: 25/.5M7: 4/1MN1 1/2MP1 20/1M2: 25/.5M8: 15/1MN2 1/2MP2 20/1M3: 3.7/1M9: 15/1MN3 1/2MP3 20/1M4: 3.7/1M10: 15/1MN4 2/1MP4 20/1M5: 100/.5M11: 15/1MN5 1/2MP5 20/1M6: 4/1MN6 1/2MP6 20/1MN7 1/8.75MP7 3.1/1Amplifier gain70 dBGBW200 KHz


## 3.5. Layout Issues

The proposed LDO is designed using
UMC 180 nm twin well process. But it is found that  layout versus schematic (LVS)
mismatch occurs when both NMOS and PMOS transistors are drawn with the above
technology and substrate connection of NMOS is connected to source in order to
avoid body bias. Hence triple-well NMOS from the same technology is chosen for
NMOS transistors which are sensitive to body bias. The corresponding layout is
shown in Figure8. The triple-well process allows a P-well to be placed
inside an N-well, resulting in three types of well structures. This third type
of well is useful for isolating circuitry within it from other sections on the
chip by the reverse bias between the N-well and the P-substrate. For mixed-signal
designs, where noise injection can be a problem, the analog sections can be
completely isolated from the digital section by using this third type of well
structure. There is no resistive path between the analog and digital
circuit, since the P-well connected to the analog VSS is isolated fromthe
digital VSS/ground by a reverse biased N-well. The triple-well also
significantly reduces the capacitive coupling between the analog VSS and
digital VSS/ground. Consequently, a high degree of isolation is achieved for
sensitiveanalog circuits from detrimental digital noise sources.Figure 8
Layout of the proposed LDO.It can be observed that most of the
chip area is occupied by the capacitor and pass transistor. The total chip area
is544μm×377μm while area of the control circuitry is only
181μm×94μm.


## 4. Testing and Results

The proposed LDO is simulated on Spectre
targeted to be fabricated in UMC 180 nm. Results are tested at five different
process corners. Line regulation, load regulation, transient response is
evaluated at slow-slow (SS), typical-typical (TT), fast-fast (FF), slow N-fast
P(SNFP), fast N-slow P(FNSP).The transient
response is obtained by applying load current pulse of 0–50 mA with 1
microsecond rise and fall times. The corresponding results are tabulated in Table2. The table clearly shows that the proposed capacitor-less LDO with folded
cascode error amplifier exhibits better line and load regulations relative to
the reported architecture [1]. A worst-case settling time of 13.1 microseconds
is observed against 15 microseconds [1]. Corresponding plots for the process
corner TT are shown in Figures 9(a)–9(d). The AC
response for different load currents is shown in Figure 10. It can be observed that deviation in phase margin
is negligible for all load currents from 50 mA to 1 mA. Also the gain is found
to be in the vicinity of 75 dB for all load currents.Table 2
Performance measures of the
proposed simulated LDO
at various process corners.
Process cornerOvershoot mVUndershoot mVSettling time (μs)Line regulation
%Load
regulation Ppm/mATT938613.1.0832FF1118312.4.0848SS808513.5632SNFP868212.2.1632FNSP1028913.2.0816(a)
Load regulation (zoomed) of LDO for a variation of load current from 0 mA to 50 mA for TT
process corner(b)
Line regulation (zoomed) of LDO for a variation supply voltage from 1.4 V to 1.8 V for TT
process corner(c)
Transient response of LDO for a variation of load current from 0 mA to 50 mA for TT
process corner. Maximum overshoot is1293−1.2=93mV, while maximum undershoot
is 1.2−1.114=86mV(d)
Settling time demonstration of the proposed LDO for variation of load
current from 0 mA to 50 mA
at 1 microsecond rise and fall timesFigure 10
Open loop frequency
response of LDO for varying load current.Power supply ripple rejection ratio (PSRR) is a
measure of how well a circuit rejects ripple coming from the input power supply
at various frequencies. One of the
dominant internal sources of PSRR in an LDO is the bandgap reference. Any
ripple that makes its way onto the reference will be amplified and sent to the
output. The power
supply rejection ratio is defined asPSRR=20log⁡rippleinputrippleoutput. The PSRR is
measured by super imposing a sine wave on VDD or by simply setting
AC=1 for VDD settings. The larger the open loop gain, the better the
PSRR is. Enough care is taken while designing the error amplifier so that any
external circuitry for improving PSRR is avoided. Thus quiescent current budget
is minimized. The PSRR is depicted in Figure 11. It can be observed that PSRR
of 45.5 dB is achieved till 10 KHz which is apt for digital baseband section of
the receiver. It can also be noticed that the PSRR begins to worsen beyond 0.1 MHz as the operating
frequency drift beyond the unity  gain frequency, where feedback has  little
control.(a)
Band gap reference output voltage variation with temperature(b)
PSRR of the LDO regulator proposed


## 5. Conclusions

The  proposed   LDO
which is simulated using 180 nm, 1.8 V supply  voltage exhibits better line and
load regulations against different process corners, while consuming a quiescent
current of100μA. It is found to exhibit
load regulation (even under worst case) of 48 ppm/mA and transient
response reveals that when the load current is varied from 0 mA to 50 mA, then
the undershoot is limited to a maximum value of 1.05 V and overshoot is
observed to a maximum value of 1.3 V and the settling time is found to be 13.1
microseconds. These above results along with the fact that it is designed to
operate with a dropout voltage of 200 mV on 180 nm will make the design a robust
deep submicron on-chip LDO voltage regulator.



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*Source: 259281-2008-12-21.xml*