# A High-Efficiency, Low-Cost Solution for On-Board Power Converters

Authors: V. Boscaino; G. Capponi
Journal: Advances in Power Electronics
 (2012)

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## Abstract

Wide-input, low-voltage, and high-current applications are addressed. A single-ended isolated topology which improves the power efficiency, reduces both switching and conduction losses, and heavily lowers the system cost is presented. During each switching cycle, the transformer core reset is provided. The traditional tradeoff between the maximum allowable duty-cycle and the reset voltage is avoided and the off-voltage of active switches is clamped to the input voltage. Therefore, the system cost is heavily reduced and the converter is well suited for wide-input applications. Zero-voltage switching is achieved for active switches, and the power efficiency is greatly improved. In the output mesh, an inductor is included making the converter suitable for high-current, low-voltage applications. Since the active clamp forward converter is the closest competitor of the proposed converter, a comparison is provided as well. In this paper, the steady-state and small-signal analysis of the proposed converter is presented. Design examples are provided for further applications. Simulation and experimental results are shown to validate the great advantages brought by the proposed topology.


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## Body

## 1. Introduction

On-board power converter technology has extensively matured over the last two years. Until recently, the industry was manufacturing converters from 5 W of power to, at most, 30 W. Today, converter power levels are increasing to 50, 100, 300, and even 400 W in miniature sizes. These are rather dramatic improvements in a relatively short period of time. High-power converters are physically much smaller than their predecessors, achieving energy density levels of 50 W per cubic inch without the required external heat sink. Recently, distributed power architectures for telecommunications and data-computing systems have received a great deal of attention. With the spread of wide-input, low-voltage, and high-current applications, many topologies have been proposed to improve the efficiency, power density, and cost of the whole system.The well-known forward converter is still the most suitable topology for medium power levels, well-suited for low-voltage and high-current applications [1, 2]. Yet, in forward converters an external circuit is required to achieve the core reset. By adding an auxiliary winding, the energy stored in the transformer could be recycled to the input rail but increasing the cost and complexity of the power supply. Otherwise, the energy is lost in the reset circuit, as in the Resistor-Capacitor-Diode (RCD) network [3–5]. The active clamp is actually the best-suited and most effective reset technique. A resonant path is provided and the transformer energy is firstly stored in the resonant path and then returned back to the transformer primary side [6, 7].Despite several techniques have been proposed, reduced efficiency and increasing cost are unavoidable drawbacks of an external core reset. A tradeoff between the off-voltage of active switches and the maximum duty-cycle is introduced by each reset technique: if a wider duty-cycle range is required, the off-voltage of active switches will increase. Note that in a traditional forward topology widening the duty-cycle range is the only way to meet wide-input applications requirements. Since the cost of active switches is mainly determined by the off-voltage, at worst the forward converter will not be suited for wide-input, low-voltage applications thus loosing the chance of a high-efficiency, inexpensive and low parts count solution.This paper proposes a single-ended single-stage isolated converter which overcomes all drawbacks emphasizing all benefits of the traditional forward topology. The converter is a low-cost, high-performance solution for wide-input low-voltage applications. The converter features high-efficiency, high power density and low electromagnetic interference. The core reset is achieved without external circuits and the tradeoff between the duty-cycle range and the off-voltage is definitively avoided. Zero-voltage switching is achieved thus improving the power efficiency. The converter is intrinsically well-suited for wide-input applications. Since high-current applications are targeted, the continuous conduction mode is assumed. The steady-state and dynamic analysis are carried out and a comparison with the active clamp forward converter is provided as well. Simulation and experimental results are shown to test the efficiency of the proposed solution.


## 2. The Active Clamp Forward Converter

Figure1 shows the well-known active clamp forward converter topology. A detailed analysis is provided in [8, 9]. Yet, for the sake of clarity main features are summed up in this section. The reset capacitor is connected in series with the auxiliary MOSFET in order to achieve the core reset. The auxiliary and the main MOSFETs are driven out of phase. The output capacitances of M1, D1, D2 and the transformer winding capacitance are collected in the Cx1 capacitor, also called lump capacitor.Figure 1
The active clamp forward converter.During the on-time, M1 is turned on and the magnetizing inductance stores energy from the input rail. During the off-time, the auxiliary MOSFET M2 is switched on to achieve the core reset. The magnetizing current is diverted in the reset path. A resonance occurs between the magnetizing inductor and the equivalent resonant capacitor which consists of the reset capacitorCcl and the lump capacitor. The active clamp technique forces a “reverse” magnetizing current to flow through the transformer for a small portion of the timing period, storing energy in the primary inductance. When released, this energy is used to position the main switch voltage to zero by discharging the MOSFETs output capacitance just prior to it turning on. This alignment to zero drain voltage will automatically occur each switching cycle, provided that enough inductive energy is stored to overcome the opposing capacitive energy requirements of the circuit and power MOSFETs. Zero voltage transitions can be forced over a wide range of input voltage and load current values. The core reset is extended throughout the off-time, allowing self-driven synchronous rectification on the secondary-side. The voltage conversion ratio is given by
(1)Vout=NVinD,
where N is the transformer turns ratio (Ns/Np), Vin the input voltage and the steady-state duty-cycle.As highlighted by (1), if the input voltage range is doubled, the duty-cycle range will be doubled too to keep constant the output voltage. Therefore, extending the duty-cycle range of forward converters is the only way to meet wide-input, low-voltage applications. At steady-state, the output inductor current ripple is given by
(2)ΔILo=VinND(1-D)LoFsw,
where Lo is the output inductor and Fsw the switching frequency. The output voltage ripple is given by
(3)ΔV=ΔILo8CoFsw,
where Co is the output capacitor. On the magnetizing inductance, the volts-second balance is expressed as
(4)VinTon=VclToff,
where Ton is the on-time and Toff the off-time. Introducing the duty-cycle D, the reset voltage Vcl across the reset capacitor Ccl is given by
(5)Vcl=VinD1-D.
The off-voltage of both MOSFETs is given by
(6)Voff,main=Vin+Vcl.
Replacing the (5) in the (6), the (7) is given. 						(7)Voff,main=Vin1-D.
On the secondary-side, the off-voltage of D2 diode is given by
(8)Voff,D2=NVin.
The off-voltage of the D1 diode is given by
(9)Voff,D1=NVcl=NVinD1-D.
If compared with existing demagnetization circuits, the active clamp technique extends the reset interval to the whole off-time. Therefore, a self-driven synchronous rectification on the secondary-side is allowed, as shown in Figure 2.Figure 2
The active clamp forward converter with self-driven synchronous rectification on the secondary side.The power conversion efficiency is heavily improved by replacing diodes with active switches. Conduction losses are heavily lowered and drivers on the secondary-side are avoided by the self-driven configuration. Improved efficiency and zero-voltage switching are the most important advantages brought by the active clamp technique. Yet, if the duty-cycle approaches unity, the voltage stress on the reset capacitor as well as on active switches will increase to infinity. The cost of the power supply system is heavily affected by the cost of active switches and passive components. As a common rule, the duty cycle value of active clamp forward converters is usually limited to 70%. Therefore, wide-input low-voltage applications are really critical for a successful design of forward converters. At worst, the transformer, active switches, and then the whole power supply will be too expensive and the forward converter will not be suited any more. Designers aims at keeping all advantages brought by the forward topology such as low parts count, low cost and high efficiency, making the converter suitable for incoming applications as well.


## 3. The Proposed Single-Ended Topology

Figure3 shows the proposed converter. Apparently, the proposed converter is just derived from the conventional active clamp forward converter by connecting the reset capacitor Ccl in series with the transformer primary windings. Really, the capacitor plays a quite different role in the proposed converter. The capacitor is not limited to the core reset function but is involved in the input-output energy transfer.Figure 3
The proposed converter topology.In the conventional active clamp forward converter, during the on-time the input-output energy transfer occurs while during the off-time the transformer is reset. In the active clamp forward converter, during the on-time the auxiliary net and thus the capacitor are disconnected from the primary windings. The series capacitor is not involved in the input-output energy transfer. In the proposed converter, the capacitor is always connected to the primary windings and the input-output energy transfer is heavily affected by the series capacitor. For these reasons, the proposed topology is presented as a new topology and not as a mere modification of existing converters. Several advantages are brought by moving the capacitor from the auxiliary to the primary net. The M2 drain terminal is tied to the input terminal. So, if M1 is switched on, the source terminal of the M2 is tied to ground. Therefore, the off-voltage of the auxiliary MOSFET is equal to the input voltage under any working condition. Vice versa, since the source terminal of M1 is tied to primary ground, if the auxiliary MOSFET is switched on, the drain terminal of M1 is tied to the input connections. Therefore, the off-voltage of M1 is equal to the input voltage under any working condition. After all, the off-voltage of both power switches is intrinsically limited by the input voltage rail. The cost of both power switches, which is mainly affected by the breakdown voltage value, is heavily reduced. The conventional tradeoff between the maximum allowable duty-cycle value and the power switches off-voltage is cancelled. Theoretically, the duty-cycle could be pushed up to unit value. As will be further discussed, the advantages brought by self-driven configuration are still preserved. The proposed topology is a low-cost, high performance solution which offers all the advantages of the conventional active clamp forward but still overcomes its drawbacks.


## 4. Steady-State Analysis

### 4.1. Voltage Conversion Ratio

Since high-current applications are addressed, a continuous conduction mode is assumed. The converter is firstly modelled by ideal elements. The main switch M1 is closed for a timeTon out of the switching period Tsw. The main and the auxiliary MOSFETs are synchronously driven out of phase. Dead-time intervals are actually introduced to avoid the simultaneous conduction of both primary MOSFETs. During the dead time, neither M1 nor M2 are on and the conduction is committed to body-diodes. Yet, dead-time intervals are neglected for the steady-state analysis thus assuming ideal gate drive signals. In order to perform the steady-state analysis, it is nearly always a good approximation to assume that the magnitude of the switching component is much smaller than the dc component of the output voltage and that the input voltage, the load current, and the voltage across the series capacitor are constant during the switching period Tsw.If M1 is turned on, assuming positive polarity atVin connections, the voltage drop across the primary windings during is given by
(10)VLm,on=Vin-Vcl,
where Vcl is the voltage across the series capacitor, assuming positive polarity at primary windings connections. During Toff, M1 is off while M2 is driven into conduction. Therefore, the voltage across primary windings is equal to
(11)VLm,off=-Vcl.
To avoid the magnetic core saturation, the volts-second balance should be met during each switching cycle. The volts-second applied to the magnetizing inductance during the on-time must equal the volt-second across the magnetizing inductance during the off-time, as highlighted by
(12)Vs1+Vs2=0,
where Vs1 corresponds to the on-time volt-second product, whereas Vs2 represents the off-time volt-second product. Since
(13)Vs1=(Vin-Vcl)Ton=(Vin-Vcl)DTsw,(14)Vs2=-VclToff=-Vcl(1-D)Tsw,
the volts-second balance (15) is obtained:
(15)(Vin-Vcl)DTsw-Vcl(1-D)Tsw=0.
Rearranging, (15) and (16) is obtained
(16)Vcl=VinD,Vcl is a positive voltage related to the input voltage by means of the system duty-cycle D and then lower than the input voltage.Assuming positive polarity at diode connections, the on-time voltage across the output inductorLo is given by
(17)VLo,on=Vsec,on-Vout=(Vin-Vcl)N-Vout,
where N is the power transformer turn-ratio Nsec/Npr.At steady-state, during the on-time the voltage across the output inductor is constant. The inductor current slope is constant and it is given by(18)SLo,on=VLo,onLo=[(Vin-VinD)N-VinND(1-D)]Lo.
Manipulating (18) and the (19) is obtained.
(19)SLo,on=NVin(1-D)2Lo.
On the falling edge of the gate drive signal, M1 is turned off. The voltage across the magnetizing inductance immediately reverses and the diode D1 is switched off. The output inductor opposes the current break trying to maintain the previously established current. The voltage polarity across it immediately reverses, forcing the diode D2 into conduction. The cathode node is thus clamped to the secondary ground. The output inductor voltage is now reversed and the inductor current is entirely carried on by the diode D2. Therefore, during the off-time the voltage across the output inductor is given by
(20)VLo,off=-Vout,
where Vout is the output voltage.At steady-state, during the off-time the voltage across the output inductor is constant. The inductor current slope is constant and it is given by(21)SLo,off=VLo,offLo=-VoutLo.
Manipulating (21),
(22)SLo,off=-VinND(1-D)Lo.
Applying the volt-second balance to the output inductor results in
(23)[(Vin-Vcl)N-Vout]DTsw-Vout(1-D)Tsw=0.
Rearranging the (23) and replacing Vcl by (16),  (24) is obtained. 								(24)Vout=NVinD(1-D).
The normalized voltage conversation ratio is given by
(25)M=VoutNVin=D(1-D).
At steady-state the output inductor current ripple could be expressed as
(26)ΔILo=SLo,onTon=SLo,onDTsw.
From (19) and (26),
(27)ΔILo=NVinD(1-D)2LoFsw.
Note that in the traditional active clamp forward converter, the output inductor current ripple is given by (2). By comparing (27) and (2),
(28)ΔILo=ΔILo,ACF(1-D).
Therefore, a decrease in the output inductor current is achieved. Being the same specifications, the cost of the output inductor as well as the volume of the entire power supply system could be easily reduced by the means of the proposed converter.In traditional forward converters, if the input voltage range is doubled, the duty-cycle range is doubled too in order to keep constant the output voltage nominal value. Increasing the duty-cycle value leads to an increase of the off-voltage of active switches. Therefore, a practical limit for wide-input applications is fixed by the tradeoff between the cost of active switches and the maximum allowable duty-cycle value. In the proposed converter, during each switching cycle, the transformer core reset is achieved avoiding the traditional tradeoff between the off-voltage of active switches and the system duty-cycle. The cost of active switches is thus heavily reduced.The normalized voltage conversion ratioM is a nonlinear function of the duty-cycle, as shown in Figure 3. The maximum value of the normalized voltage conversion ratio is equal to 0.25 corresponding to a duty-cycle D=50%. If compared with the conventional forward converter, equal N results in a lower conversion ratio making the converter suitable for low-voltage applications. By selecting the desired conversion ratio, two duty-cycle values which are symmetrical to 50% are obtained. In traditional forward converters, doubling the input range results in doubling the duty-cycle range as well. If a 36 V–72 V input voltage range is addressed, the maximum duty-cycle value is twice the minimum value. Since a 70% limit is fixed, at worst the forward converter will not be suited anymore. The proposed converter is well suited for wide-input applications since the duty-cycle range is narrowed and the tradeoff between the maximum duty-cycle and the system cost is avoided. For example, if a 36 V–72 V range is addressed and a 0.95 maximum duty-cycle value is set, a 0.89 minimum value is obtained by (16) keeping constant the output voltage, as shown in Figure 4. The minimum duty-cycle value is almost 93% of the maximum duty-cycle value. The advantage over the active clamp forward converter is emphasized if the steady-state duty-cycle is close to unity. If the steady state duty-cycle is less than 50%, increasing the duty-cycle leads to an increase of the voltage conversion ratio. Otherwise, increasing the system duty-cycle forces a decrease of the voltage conversion ratio. Therefore, two duty-cycle regions which are limited by 50% value are identified. The small-signal behaviour of the proposed system is heavily affected by the steady-state duty-cycle region, as will be further discussed.Figure 4
The normalized conversion ratio versus the system duty-cycle.Key waveforms of the proposed converter topology are plotted. Figure5 shows, from top to bottom, the magnetizing inductance current, the ideal primary windings current, the effective primary current, the primary MOSFET current, the auxiliary MOSFET current, the output inductor current, the free-wheeling diode current, and the forward diode current.Figure 5
Key waveforms of the proposed converter topology.


### 4.2. Voltage and Current Stress

During the on-time, the voltage across the secondary windings is given by(29)Vsec,on=(Vin-Vcl)N=NVin(1-D),
where Vcl is the series capacitor voltage and N the transformer turns ratio.Therefore, the diode D1 is turned on while the diode D2 is switched off. The output inductor current is entirely carried on by the diode D1. During the on-time, the load current is supplied by the primary windings and then by the input rail.The voltage across the diode D2 is given by(30)VD2,on=-Vsec,on.
Therefore, if the duty-cycle value approaches the unit value, the voltage stress across the freewheeling diode will be reduced.On the primary side, during the off-time, the main MOSFET is off while the auxiliary MOSFET is turned on. The switching node is clamped at the input connections by the auxiliary MOSFET and the voltage across the main MOSFET is equal to the input voltage. The voltage across the primary windings is given by(31)Vpr,off=-Vcl.
During the off-time, the diode D1 is turned off and the free-wheeling diode is forced into conduction and the switching node on the secondary side is thus clamped at ground connections.The voltage across the diode D1 is given by(32)VD1,off=NVpr,off=-NVcl=-NVinD.
Therefore, if the duty-cycle value is lowered, the voltage stress across the diode D2 will be reduced.If compared with traditional active clamp forward converters, the voltage stress on the secondary-side diodes is anyway reduced independently of the working duty-cycle region.During the on-time, the series capacitorCcl is charged by the primary current. Under steady-state conditions, during the off-time the series capacitor should be discharged. Since the secondary current is almost zero during the off-time, the capacitor is discharged by the magnetizing current only. By applying the charge balance to the series capacitance,
(33)iCcl,onD+iCcl,off(1-D)=0.
During the on-time, the capacitor current is given by
(34)icl,on=iLm,on+ipr,on′,
where ILm is the magnetizing current and ipr is the secondary current reflected to the primary windings.During the off-time the series capacitor current is thus given by(35)iCcl,off=iLm,off.
By replacing (34) and (35) in (33), (36) is obtained. 								(36)iLm=-ipr,on′D,
where Ipr,on′=IoN.Therefore, the average magnetizing current is given by(37)ILm=-IoND.
Since at steady-state the average current through the output capacitor is null, the average current through the output inductor is equal to the load current. The ac component of the inductor current flows through the parallel connection between load and capacitor. Commonly, the capacitor is large enough to assume that its impedance at the switching frequency is much smaller than the load resistance. Hence, nearly all the inductor current ripple flows through the capacitor. The ac-current flowing into the load could be reasonably neglected. A continuous conduction mode is preferred in high-current applications since lower and lower conduction power losses are involved. The inductor is thus sufficiently large to neglect the current ripple with respect to the average inductor current. The voltage ripple across the output capacitor is given by
(38)ΔVout=qCo=ΔILTsw8Co.


### 4.3. Zero-Voltage Switching

Zero-voltage switching (ZVS) of both primary switches is achieved by the energy stored in the leakage inductor. Therefore, the energy stored in the leakage inductor must dischargeCds,M1 to zero-voltage level before switch M1 is turned on. In the other dead time, the energy stored in the leakage inductor must discharge Cds,M2 before the switch M2 is turned on. At the beginning of the first dead-time, the capacitor Cds,M2 is charged at Vcl voltage. Therefore, the energy required to achieve ZVS in the first dead-time is given by
(39)Ereq=12·Ct·(Vcl)2.
The energy stored in the leakage inductor, at the very beginning of the first dead-time, is given by
(40)Estored=12·Llk·I2pk,Llk,
where Ipk,Llk is the leakage inductor peak current value. At the beginning of the first dead-time, the leakage inductor current is given by the difference between the secondary current reflected to the primary and the magnetizing current. The peak value of the leakage inductor current is therefore given by
(41)Ipk,Llk=Ipk,Lo+ΔILoN-(|ILm¯|-ΔILm2).
Condition (42) is required to achieve zero-voltage switching of M2 switch:
(42)12·Llk·I2pk,Llk≥12·Ct·(Vcl)2.
At the beginning of the second dead-time, the capacitor Cds,M1 is charged at (Vin-Vcl). The energy required to achieve ZVS of M1 is therefore
(43)Ereq=12·Ct·(Vin-Vcl)2.
The energy stored in the leakage inductor is given by:
(44)Estored=12·Llk·I2pk,Llk.
At the beginning of the second dead-time, the leakage inductor current is be equal to the magnetizing inductor current since the diode D1 is not yet turned on. Therefore, the leakage inductor peak current is now given
(45)|Ipk,Llk|=|ILm¯|+ΔILm2.
Condition (46) is required to achieve zero-voltage switching of M1 switch:
(46)12·Llk·I2pk,Llk≥12·Ct·(Vcl)2.
In the traditional active clamp, the zero-voltage switching of the main Mosfet is achieved by the energy stored in the leakage inductor. By the same analysis, the condition to achieve ZVS of the main Mosfet is given by
(47)Llk≥Ct·(Vin)2(ΔILm/2)2.


### 4.4. Self-Driven Synchronous Rectification

The system efficiency could be heavily improved by self-driven synchronous rectification on the secondary-side. Both diodes could be replaced by two MOSFETs, as shown in Figure6.Figure 6
The proposed converter with secondary-side self-driven synchronous rectification.The free-wheeling diode is now replaced by M4 and appears in the return path. When the main MOSFET is turned on, the M4 gate jumps toN(Vin-Vcl) thus ensuring proper biasing during the on-time. When the on-time ends, M3 is forced into conduction as long as a voltage appears across its gate-source connection. As well as in the active clamp forward converter, the core demagnetization is extended to the whole off-time and the free-wheeling MOSFET Vgs exists for the whole off-time duration. The system efficiency is heavily improved by the proposed architecture.


## 4.1. Voltage Conversion Ratio

Since high-current applications are addressed, a continuous conduction mode is assumed. The converter is firstly modelled by ideal elements. The main switch M1 is closed for a timeTon out of the switching period Tsw. The main and the auxiliary MOSFETs are synchronously driven out of phase. Dead-time intervals are actually introduced to avoid the simultaneous conduction of both primary MOSFETs. During the dead time, neither M1 nor M2 are on and the conduction is committed to body-diodes. Yet, dead-time intervals are neglected for the steady-state analysis thus assuming ideal gate drive signals. In order to perform the steady-state analysis, it is nearly always a good approximation to assume that the magnitude of the switching component is much smaller than the dc component of the output voltage and that the input voltage, the load current, and the voltage across the series capacitor are constant during the switching period Tsw.If M1 is turned on, assuming positive polarity atVin connections, the voltage drop across the primary windings during is given by
(10)VLm,on=Vin-Vcl,
where Vcl is the voltage across the series capacitor, assuming positive polarity at primary windings connections. During Toff, M1 is off while M2 is driven into conduction. Therefore, the voltage across primary windings is equal to
(11)VLm,off=-Vcl.
To avoid the magnetic core saturation, the volts-second balance should be met during each switching cycle. The volts-second applied to the magnetizing inductance during the on-time must equal the volt-second across the magnetizing inductance during the off-time, as highlighted by
(12)Vs1+Vs2=0,
where Vs1 corresponds to the on-time volt-second product, whereas Vs2 represents the off-time volt-second product. Since
(13)Vs1=(Vin-Vcl)Ton=(Vin-Vcl)DTsw,(14)Vs2=-VclToff=-Vcl(1-D)Tsw,
the volts-second balance (15) is obtained:
(15)(Vin-Vcl)DTsw-Vcl(1-D)Tsw=0.
Rearranging, (15) and (16) is obtained
(16)Vcl=VinD,Vcl is a positive voltage related to the input voltage by means of the system duty-cycle D and then lower than the input voltage.Assuming positive polarity at diode connections, the on-time voltage across the output inductorLo is given by
(17)VLo,on=Vsec,on-Vout=(Vin-Vcl)N-Vout,
where N is the power transformer turn-ratio Nsec/Npr.At steady-state, during the on-time the voltage across the output inductor is constant. The inductor current slope is constant and it is given by(18)SLo,on=VLo,onLo=[(Vin-VinD)N-VinND(1-D)]Lo.
Manipulating (18) and the (19) is obtained.
(19)SLo,on=NVin(1-D)2Lo.
On the falling edge of the gate drive signal, M1 is turned off. The voltage across the magnetizing inductance immediately reverses and the diode D1 is switched off. The output inductor opposes the current break trying to maintain the previously established current. The voltage polarity across it immediately reverses, forcing the diode D2 into conduction. The cathode node is thus clamped to the secondary ground. The output inductor voltage is now reversed and the inductor current is entirely carried on by the diode D2. Therefore, during the off-time the voltage across the output inductor is given by
(20)VLo,off=-Vout,
where Vout is the output voltage.At steady-state, during the off-time the voltage across the output inductor is constant. The inductor current slope is constant and it is given by(21)SLo,off=VLo,offLo=-VoutLo.
Manipulating (21),
(22)SLo,off=-VinND(1-D)Lo.
Applying the volt-second balance to the output inductor results in
(23)[(Vin-Vcl)N-Vout]DTsw-Vout(1-D)Tsw=0.
Rearranging the (23) and replacing Vcl by (16),  (24) is obtained. 								(24)Vout=NVinD(1-D).
The normalized voltage conversation ratio is given by
(25)M=VoutNVin=D(1-D).
At steady-state the output inductor current ripple could be expressed as
(26)ΔILo=SLo,onTon=SLo,onDTsw.
From (19) and (26),
(27)ΔILo=NVinD(1-D)2LoFsw.
Note that in the traditional active clamp forward converter, the output inductor current ripple is given by (2). By comparing (27) and (2),
(28)ΔILo=ΔILo,ACF(1-D).
Therefore, a decrease in the output inductor current is achieved. Being the same specifications, the cost of the output inductor as well as the volume of the entire power supply system could be easily reduced by the means of the proposed converter.In traditional forward converters, if the input voltage range is doubled, the duty-cycle range is doubled too in order to keep constant the output voltage nominal value. Increasing the duty-cycle value leads to an increase of the off-voltage of active switches. Therefore, a practical limit for wide-input applications is fixed by the tradeoff between the cost of active switches and the maximum allowable duty-cycle value. In the proposed converter, during each switching cycle, the transformer core reset is achieved avoiding the traditional tradeoff between the off-voltage of active switches and the system duty-cycle. The cost of active switches is thus heavily reduced.The normalized voltage conversion ratioM is a nonlinear function of the duty-cycle, as shown in Figure 3. The maximum value of the normalized voltage conversion ratio is equal to 0.25 corresponding to a duty-cycle D=50%. If compared with the conventional forward converter, equal N results in a lower conversion ratio making the converter suitable for low-voltage applications. By selecting the desired conversion ratio, two duty-cycle values which are symmetrical to 50% are obtained. In traditional forward converters, doubling the input range results in doubling the duty-cycle range as well. If a 36 V–72 V input voltage range is addressed, the maximum duty-cycle value is twice the minimum value. Since a 70% limit is fixed, at worst the forward converter will not be suited anymore. The proposed converter is well suited for wide-input applications since the duty-cycle range is narrowed and the tradeoff between the maximum duty-cycle and the system cost is avoided. For example, if a 36 V–72 V range is addressed and a 0.95 maximum duty-cycle value is set, a 0.89 minimum value is obtained by (16) keeping constant the output voltage, as shown in Figure 4. The minimum duty-cycle value is almost 93% of the maximum duty-cycle value. The advantage over the active clamp forward converter is emphasized if the steady-state duty-cycle is close to unity. If the steady state duty-cycle is less than 50%, increasing the duty-cycle leads to an increase of the voltage conversion ratio. Otherwise, increasing the system duty-cycle forces a decrease of the voltage conversion ratio. Therefore, two duty-cycle regions which are limited by 50% value are identified. The small-signal behaviour of the proposed system is heavily affected by the steady-state duty-cycle region, as will be further discussed.Figure 4
The normalized conversion ratio versus the system duty-cycle.Key waveforms of the proposed converter topology are plotted. Figure5 shows, from top to bottom, the magnetizing inductance current, the ideal primary windings current, the effective primary current, the primary MOSFET current, the auxiliary MOSFET current, the output inductor current, the free-wheeling diode current, and the forward diode current.Figure 5
Key waveforms of the proposed converter topology.


## 4.2. Voltage and Current Stress

During the on-time, the voltage across the secondary windings is given by(29)Vsec,on=(Vin-Vcl)N=NVin(1-D),
where Vcl is the series capacitor voltage and N the transformer turns ratio.Therefore, the diode D1 is turned on while the diode D2 is switched off. The output inductor current is entirely carried on by the diode D1. During the on-time, the load current is supplied by the primary windings and then by the input rail.The voltage across the diode D2 is given by(30)VD2,on=-Vsec,on.
Therefore, if the duty-cycle value approaches the unit value, the voltage stress across the freewheeling diode will be reduced.On the primary side, during the off-time, the main MOSFET is off while the auxiliary MOSFET is turned on. The switching node is clamped at the input connections by the auxiliary MOSFET and the voltage across the main MOSFET is equal to the input voltage. The voltage across the primary windings is given by(31)Vpr,off=-Vcl.
During the off-time, the diode D1 is turned off and the free-wheeling diode is forced into conduction and the switching node on the secondary side is thus clamped at ground connections.The voltage across the diode D1 is given by(32)VD1,off=NVpr,off=-NVcl=-NVinD.
Therefore, if the duty-cycle value is lowered, the voltage stress across the diode D2 will be reduced.If compared with traditional active clamp forward converters, the voltage stress on the secondary-side diodes is anyway reduced independently of the working duty-cycle region.During the on-time, the series capacitorCcl is charged by the primary current. Under steady-state conditions, during the off-time the series capacitor should be discharged. Since the secondary current is almost zero during the off-time, the capacitor is discharged by the magnetizing current only. By applying the charge balance to the series capacitance,
(33)iCcl,onD+iCcl,off(1-D)=0.
During the on-time, the capacitor current is given by
(34)icl,on=iLm,on+ipr,on′,
where ILm is the magnetizing current and ipr is the secondary current reflected to the primary windings.During the off-time the series capacitor current is thus given by(35)iCcl,off=iLm,off.
By replacing (34) and (35) in (33), (36) is obtained. 								(36)iLm=-ipr,on′D,
where Ipr,on′=IoN.Therefore, the average magnetizing current is given by(37)ILm=-IoND.
Since at steady-state the average current through the output capacitor is null, the average current through the output inductor is equal to the load current. The ac component of the inductor current flows through the parallel connection between load and capacitor. Commonly, the capacitor is large enough to assume that its impedance at the switching frequency is much smaller than the load resistance. Hence, nearly all the inductor current ripple flows through the capacitor. The ac-current flowing into the load could be reasonably neglected. A continuous conduction mode is preferred in high-current applications since lower and lower conduction power losses are involved. The inductor is thus sufficiently large to neglect the current ripple with respect to the average inductor current. The voltage ripple across the output capacitor is given by
(38)ΔVout=qCo=ΔILTsw8Co.


## 4.3. Zero-Voltage Switching

Zero-voltage switching (ZVS) of both primary switches is achieved by the energy stored in the leakage inductor. Therefore, the energy stored in the leakage inductor must dischargeCds,M1 to zero-voltage level before switch M1 is turned on. In the other dead time, the energy stored in the leakage inductor must discharge Cds,M2 before the switch M2 is turned on. At the beginning of the first dead-time, the capacitor Cds,M2 is charged at Vcl voltage. Therefore, the energy required to achieve ZVS in the first dead-time is given by
(39)Ereq=12·Ct·(Vcl)2.
The energy stored in the leakage inductor, at the very beginning of the first dead-time, is given by
(40)Estored=12·Llk·I2pk,Llk,
where Ipk,Llk is the leakage inductor peak current value. At the beginning of the first dead-time, the leakage inductor current is given by the difference between the secondary current reflected to the primary and the magnetizing current. The peak value of the leakage inductor current is therefore given by
(41)Ipk,Llk=Ipk,Lo+ΔILoN-(|ILm¯|-ΔILm2).
Condition (42) is required to achieve zero-voltage switching of M2 switch:
(42)12·Llk·I2pk,Llk≥12·Ct·(Vcl)2.
At the beginning of the second dead-time, the capacitor Cds,M1 is charged at (Vin-Vcl). The energy required to achieve ZVS of M1 is therefore
(43)Ereq=12·Ct·(Vin-Vcl)2.
The energy stored in the leakage inductor is given by:
(44)Estored=12·Llk·I2pk,Llk.
At the beginning of the second dead-time, the leakage inductor current is be equal to the magnetizing inductor current since the diode D1 is not yet turned on. Therefore, the leakage inductor peak current is now given
(45)|Ipk,Llk|=|ILm¯|+ΔILm2.
Condition (46) is required to achieve zero-voltage switching of M1 switch:
(46)12·Llk·I2pk,Llk≥12·Ct·(Vcl)2.
In the traditional active clamp, the zero-voltage switching of the main Mosfet is achieved by the energy stored in the leakage inductor. By the same analysis, the condition to achieve ZVS of the main Mosfet is given by
(47)Llk≥Ct·(Vin)2(ΔILm/2)2.


## 4.4. Self-Driven Synchronous Rectification

The system efficiency could be heavily improved by self-driven synchronous rectification on the secondary-side. Both diodes could be replaced by two MOSFETs, as shown in Figure6.Figure 6
The proposed converter with secondary-side self-driven synchronous rectification.The free-wheeling diode is now replaced by M4 and appears in the return path. When the main MOSFET is turned on, the M4 gate jumps toN(Vin-Vcl) thus ensuring proper biasing during the on-time. When the on-time ends, M3 is forced into conduction as long as a voltage appears across its gate-source connection. As well as in the active clamp forward converter, the core demagnetization is extended to the whole off-time and the free-wheeling MOSFET Vgs exists for the whole off-time duration. The system efficiency is heavily improved by the proposed architecture.


## 5. Small-Signal Analysis

Parasitic components of passive elements are included in the small-signal analysis. The resistancercl is the equivalent series resistance of the primary-side capacitor, rs,trasf of the transformer, rL of the output inductor, and rc of the output capacitor.The small-signal model of the proposed converter is derived assuming continuous conduction mode of operation. The small-signal model on the secondary side is shown in Figure7. The Gvo transfer function is usually defined as
(48)Gvo=(voutd)Vin=cost,Iout=const.
During the on-time, the secondary voltage is equal to
(49)vsec=N(vin-vcl).
During the on-time, the Vsec voltage is applied to the output filter since D1 is forced into conduction. During the off-time, the free-wheeling diode is turned off and the switching node is clamped to ground connections. Therefore the vs signal could be expressed as
(50)vsec=N(vin-vcl)d.
According to the state-space averaging method, all variables are split with a dc term imposing the operating point, and an ac modulating signal which is sufficiently small in amplitude to keep the system linear. Hence,
(51)d=D+d^vin=Vin+v^in.
Assuming Vin constant and perturbing the duty-cycle variable around the operating point,
(52)v^Lo-Co=[(Vin-Vcl)·d^-v^cl·D]N.
(52) could be expressed as
(53)v^Lo-Co=NVin·[(1-D)-FI(s)·DVin]·d^,
where FI(s) is defined as:
(54)FI(s)=v^cld^.
Hence, the small-signal transfer function Gvo of the proposed converter is obtained by the small-signal model shown at the left in Figure 7 while the small-signal model of a traditional forward converter is shown at the right in Figure 7.Figure 7
At the left, the small-signal model of the proposed converter. At the right, the traditional forward converter model.Hence,(55)v^0d^=[(1-D)-FI(s)DVin]·Fo(s),
where Fo(s) is the output to duty-cycle transfer function of the traditional forward converter.TheFI(s) transfer function is obtained by the small-signal model of the primary side. Assuming constant the output current and assuming zero-ripple approximation, the ac term of the output inductor current could be neglected for the small-signal analysis.During the on-time, the full load current flows through the secondary windings. During the off-time, since the diode D1 is turned-off, the load current flows through the free-wheeling diode D2 and no current flows through the secondary windings. The secondary windings current signal is given by(56)is=Io·d,
where d is the duty-cycle signal and Io the load current. Splitting the duty-cycle variable with a dc and an ac term,
(57)Is+i^s=Io·(D+d^).
According to the steady-state analysis
(58)Is=Io·D.
Therefore, from (57)
(59)i^s=Io·d^.
According to (59), the primary side small-signal model is shown in Figure 8. The secondary-side circuit is replaced by the current generator i^s and reflected to the primary side.Figure 8
Primary-side small-signal model.Note that the small-signal model shown in Figure8 is the small-signal model of a buck converter whose output inductor is Lm and output capacitor is Ccl. Taking advantages by similarities, the FI(s) transfer function could be easily derived by the small-signal circuit. The model shown in Figure 8 is linear and the superposition principle could be applied. Neglecting the current source, (60) is obtained by circuit analysis:
(60)(v^cld^)V=Vin·(1+s·Ccl·rt)s2·(Lm·Ccl)+s·(Ccl·rt)+1,
where rt is defined as
(61)rt=rcl+rs,trasf.
Neglecting the voltage source, the system response is obtained:
(62)(v^cld^)I=NIo·s·Lm·(1+s·Ccl·rt)s2·(Lm·Ccl)+s·(Ccl·rt)+1.
The FI(s) is given by (63)FI(s)=v^cld^=(v^cld^)V+(v^cld^)I=Vin·s2·(Ccl·Io·Lm·rt/N·Vin)+s·(Ccl·rt+Io·Lm/N·Vin)+1s2·(Lm·Ccl)+s·(Ccl·rt)+1.The GVo,d transfer function of the proposed converter is obtained by replacing (63) in (55) (64)GVo,d=NVin·(s·Co·rC+1)s2·(Co·Lo)+s·Co(rc+rl)+1·s2CclLm(1-D)+sCclrt(1-D)(IoLmD/NVin)+(1-2D)(s2·Ccl·Lm+s·Ccl·rt+1).The output filter introduces a zero and a complex pole, as given by
(65)wz=1rcCo,wp=1LoCo,ζp=(rc+rL)2CoLo.
The proposed architecture introduced an LC filter made up of the magnetizing inductance of the transformer and the series capacitor. The dynamic behaviour of the proposed converter is heavily affected by the input filter in different ways depending on the duty-cycle region. The analysis is carried on in both regions and criteria for region selection are provided for further applications. The input filter introduces a couple of complex poles:
(66)wp,in=1LmCcl,ζp=rt2CclLm.
Yet, a right half plane zero (RHPZ) is introduced by the input filter in the higher duty-cycle region. As highlighted by (64), the numerator constant term is given by (1-2D) which is negative in the higher duty-cycle region, meaning that almost one root is located in the right-half s-plane. Depending on the converter design, the RHPZ lies within the frequency range of interest thus limiting the maximum achievable bandwidth. In the lower duty-cycle region, no RHPZ is introduced by the proposed topology.


## 6. Design Example

According to the proposed analysis, choosing the duty-cycle region is a critical step which heavily depends on the addressed application. The higher duty-cycle region is the most suitable for wide-input, low-voltage, high-current applications. If on-board applications are addressed, the higher duty-cycle region will be the most suitable.Since no RHPZ is introduced, the lower duty-cycle region features the highest achievable bandwidth. The lower region is the most suitable for wide-bandwidth, low-voltage, high-current applications. If point-of-load applications are addressed, the lower region will be the most suitable.If wide-input, low-voltage, high-current applications are addressed, the proposed converter features higher performances than the traditional active clamp forward converter. Moreover, the cost of the whole power supply system is heavily reduced by the proposed architecture. Further improvements are provided by an accurate selection of the working duty-cycle region.A laboratory prototype of the proposed converter for on-board applications has been designed and tested. The efficiency of the proposed architecture is shown by simulation and experimental results. Design criteria are discussed for further implementations. The telecom standard range of 36 V–72 V is the targeted input voltage range. A 50 W, 2.5 V, 20 A converter is designed and a PWM voltage-mode control at 250 kHz is implemented. Since on-board applications are addressed, the higher duty-cycle region is the most suitable. The transformer turns-ratio is designed by selecting the maximum duty-cycle value. By the proposed architecture, ideally the duty-cycle value could be pushed up to unit value. Yet, the off-time must be ensured to allow the core reset. A maximum duty-cycle of 0.9 is therefore a good selection. The maximum duty-cycle value corresponds to the maximum input voltage. Therefore, the turns ratio is designed according(67)N≥NsNp=VoDmax·(1-Dmax)·Vin,max=12.59.
An integer turns-ratio of 1 : 3 is chosen for the proposed application. The maximum and minimum duty-cycle values are 0.88 and 0.7, respectively. Since zero-ripple approximations were made on the magnetizing inductance value, the magnetizing inductor is designed to ensure that the magnetizing ripple current is lower than the average magnetizing current by a factor of 20%. By the transformer turns-ratio, magnetizing inductance and maximum magnetizing current, the transformer could be selected. In the proposed prototype, a Coiltronics VP5-0083R reconfigurable transformer is used.The series capacitor value is designed according to the steady-state and dynamic analysis. At steady-state, during each switching cycle the voltage across the series capacitor should be rather constant to ensure proper core reset. Yet, the capacitor value should be as low as possible to ensure adequate bandwidth. The capacitor value has been designed to ensure a maximum ripple on the capacitor voltage of about the 10% of the minimum average series capacitor voltage.On the secondary side, the output inductor is designed to ensure small-ripple approximation on the output mesh. The output capacitor value should be as high as possible to limit the over- and undershoots of the output voltage under load transients. Therefore, a unit damping factor for the output filter is designed. The system has been modeled in PSIM environment. The model is shown in Figure9.Figure 9
PSIM simulation model.Three subsystems are highlighted: the converter, the control loop, and the driver model. Parasitic elements of passive components are included in the simulation model to improve the accuracy of simulation results. Self-driven synchronous rectification is implemented on the secondary-side. The driver section models are all available functions of the National Semiconductor LM5104 driver: high-side and low side MOSFETs are driven and adaptive time-delay is provided to prevent shoot-through.In the feedback loop, galvanic isolation is provided by the optocoupler PS2701. Since low-voltage applications are addressed, the classical TL431 solution could not be adopted. The cathode node of the emitting diode is tied to ground. A common-emitter configuration is implemented and the optocoupler is driven by the error amplifier. The LED current is limited by the resistorRk while the saturation current of the optocoupler bipolar transistor is limited by the resistor Rc. A type 3 compensation action is designed to achieve stability and adequate bandwidth. A 0.6 V reference voltage is obtained by MAX8515. The error to output voltage transfer function is given by
(68)VerrVout=CTR·RCR1·(Rk+RD)·(C2+C3)·(1+s·R1·C1)·(1+s·R3·C3)s·(1+s·Rc·Cc)·(1+s·R3·(C2·C3/(C2+C3))),
where CTR is the optocoupler current transfer ratio. The efficiency of the proposed architecture is shown by simulation and experimental results.


## 7. Simulation and Experimental Results

In Figure10 steady-state waveforms are shown. A 36 V input voltage and 2 A load current are set. At the top gate drive signals, at the bottom drain-source voltages of primary-side switches under 36 V input voltage are shown. The leakage inductor is included in the PSIM model, according to the selected transformer ratings. ZVS is achieved for both MOSFETs.Figure 10
Primary-side steady-state waveforms under 36 V input voltage and 2 A load current.In Figure11, the input voltage is now set at 72 V and 20 A load current is drawn. At the top the drain-source voltages of both main (Vds1) and auxiliary (Vds2) MOSFETs, at the bottom gate voltages of both, Vgs1 and Vgs2, respectively, are shown. The off-voltage of both primary MOSFET is clamped at the input voltage, as shown by simulation results.Figure 11
Primary-side waveforms under 72 V input voltage and 20 A load current.If a 36–72 V active clamp forward converter is designed, at least 150 V breakdown voltage will be required for power MOSFETs. By the proposed topology, 80 V breakdown voltages are required being the same input voltage range. The cost of active switches is heavily reduced.Experimental results under steady state conditions are shown in Figure12. The input voltage is fixed at 36 V and the load current is equal to 2 A. The drain voltage of the main switch Vsw is shown on Ch1 (10 V/div). The voltage at the transformer-capacitor connections Vint is shown on Ch2 (10 V/div). The transformer primary current is shown on Ch3 (2 A/div). Time base is set at 2 μsec/div. Note that the drain-source voltage of the auxiliary MOSFET M2 is obtained as the difference between the input voltage and the switching node voltage. The voltage across the series capacitor is obtained as the difference between Ch2 and Ch1 waveforms. As shown in Figure 12, the off-voltage of both active switches is clamped to the input voltage value, independently of the actual working conditions. According to (16), the measured average voltage across the series capacitor is equal to 25 V.Figure 12
Experimental results on the primary side under 36 V input voltage and 2 A load current.In Figure13 secondary-side waveforms under 3 A load current are shown. On Ch1 (5 V/div) the secondary-side switching node voltage, on Ch2 (2 V/div) the output voltage, on Ch4 (2 A/div) the output inductor current waveforms are shown. Time base is set at 2 μsec/div. As shown by experimental results, system stability is achieved and the output voltage is regulated at the nominal value of 2.5 V.Figure 13
Secondary-side experimental waveforms at 36 V, 3 A.In Figure14 the output voltage (Ch2, 1 V/div) and the output inductor current (Ch3, 1 A/div) waveforms under 5.8 A load current are shown. Time base is set at 10 μsec/div. Stability is achieved under each working condition.Figure 14
Experimental results at 26 V, 6 A.


## 8. Conclusion

In this paper, a single-ended isolated topology for wide-input, low-voltage, and high-current applications has been proposed. The topology improves the power efficiency, reduces both switching and conduction losses, and heavily reduces the system cost. The transformer core reset is provided during each switching cycle not requiring additional circuits. The converter steady-state and dynamic analysis has been carried out and a comparison of the system performances in both allowable duty-cycle regions is extensively performed. A 50 W@2.5 V, 20 A converter has been realized and tested. The traditional tradeoff between the maximum allowable duty-cycle and the reset voltage is avoided. Independently of the actual working condition, the off-voltage of active switches is intrinsically clamped to the input voltage. Therefore, the cost of the whole system is heavily reduced. Zero-voltage switching is achieved for active switches and the power efficiency is greatly improved. As shown by simulation and experimental results, all advantages brought by the conventional active clamp forward converter are still preserved overcoming all its drawbacks. The converter is well suited for wide-input, low-voltage applications thus providing a cost-effective and high-performance solution.



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*Source: 259756-2012-11-25.xml*