# Design of an Interleaved High Step-Up DC-DC Converter with Multiple Magnetic Devices for Renewable Energy Systems Applications

Authors: Marzieh Mohammadi Jouzdani; Mahdi Shaneh; Tohid Nouri
Journal: International Transactions on Electrical Energy Systems
 (2022)

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## Abstract

An interleaved high step-up converter topology based on the coupled inductor (CI) and built-in transformer (BIT) is proposed in this study to provide high step-up voltage gain and high efficiency with a low number of power electronic components for renewable energy applications. The voltage gain is increased by both of the turns’ ratio of CI and BIT, so there is no need to extend duty ratio to obtain high voltage gain. The proposed topology is much more flexible than those with only either CI or BIT. Moreover, the voltage stress across semiconductor devices can be relatively decreased by adjusting the turns’ ratio of the CI and BIT. In addition, the input current ripple can be reduced when the interleaved structure is applied at the input of this converter. Furthermore, turned-OFF and turned-ON zero current switching (ZCS) conditions for the diodes and power MOSFETs are achieved, respectively, thanks to the leakage inductances of the magnetic devices. Hence, due to the control of the falling current rate of the diodes by the leakage inductances, reverse recovery problem is alleviated. Moreover, the energy of the leakage inductances is recycled by the clamp capacitors avoiding high spikes across MOSFETs. As a result, according to the abovementioned advantages of the proposed converter, MOSFETs with low ON-state resistance and diodes with low forward voltage drop can be used to decrease the conduction losses. A 600 W laboratory prototype with 27–400 V voltage conversion at switching frequency 50 kHz is built to verify the performance of the proposed converter. Experimental results confirm the theoretical analysis. The efficiency reaches to 94.6% at full load which is close to the calculated of 95.8%.


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## Body

## 1. Introduction

Renewable energy sources, such as photovoltaic (PV) and fuel cell (FC), have been receiving more attention in recent years as a result of a substantial increase in demand for clean energy, concerns related to electricity generation based on FC, and environmental effects of greenhouse gas (GHG) emissions [1]. The output voltage of FCs and PV panels are relatively less than the required amount. In isolated converters, high voltage gain can be achieved by adjusting the transformer ratio. In [2, 3], isolated LLC resonant converters have been proposed. Introduced configuration in [2, 3] not only reduces the voltage stress across MOSFETs to half of the input voltage in the low voltage side but also makes the converter suitable for high power applications. Moreover, high operation frequency, high energy density, and wide output ranges are advantages of such converters. Meanwhile, nonisolated converters are typically used to increase the output voltage of PV panels and FCs. The conventional boost converter (CBC) with a simple structure and low cost can be used as a fundamental solution [4]. As a result, appropriate voltage levels can be reached for the inverter-fed AC utility when connecting to the electricity grid. However, the CBC should operate in a high duty ratio to achieve high step-up voltage gain, leading to problems such as the increased voltage rate of power MOSFETs and high peak currents. Consequently, power MOSFETs with higher on-state resistance should be selected, increasing conduction losses, reducing performance operation, and decreasing conversion efficiency [5]. In [6], a quadratic boost converter is used to increase the voltage step-up gain. Although it does not call for a high duty ratio, this structure still suffers from the high voltage stress across power MOSFET. Switched capacitor (SC) and switched inductor (SI) topologies (known as transformer-less converters) are presented in [7–11] to increase voltage gain. However, SI-based structures suffer from problems such as high voltage stress across semiconductor devices. To deal with this problem, voltage multiplier cell (VMC) converters are introduced [12–14]. These converters can achieve high voltage gain while reducing cost, voltage stress, and duty ratio. By increasing the number of VMCs, voltage gain can be boosted. However, the more the number of VMC is, the more the circuit complexity will be. High switching losses and reverse recovery due to operating under hard switching conditions are other issues associated with these converters. Coupled inductors (CI) are other structures to obtain high step-up voltage gain [15–22]. They can provide zero current switching (ZCS) turn-on for MOSFETs thanks to the leakage inductances of the CI, which will decrease switching losses and attenuate the reverse recovery problem. Nevertheless, voltage spike during switching transition due to the leakage inductor is the main disadvantage of CI-based converters. Passive clamp circuits can be implemented to recycle the leakage-inductor energy and avoid efficiency degradation. To decrease voltage stress across semiconductor devices, improve efficiency, and recycle the leakage-inductor energy, CIs can be implemented with VMCs [23–26]. A high step-up converter is developed in [23] with low voltage stress across the main power switch, in which voltage gain is increased by applying one CI and two VMCs. Moreover, a capacitor is being charged during the switch-off period using the energy stored in the CI, increasing the voltage transfer gain. The energy stored in the leakage inductance is recycled using a passive clamp circuit, reducing voltage spike during switching transition. In addition, a built-in transformer (BIT) can be utilized with CI to improve voltage gain further. Due to the zero average current of the primary windings of the BIT, the RMS current is also reduced. Thus, a low volume core can be selected when fabricating the BIT. Nevertheless, the single-phase nature of these converters restricts them to low power levels. To use high voltage gain converters at high power, minimize the input current ripple, and increase reliability, interleaved converters have been introduced. The abovementioned structures (i.e., SC, CI, and VMC) are adopted to interleaved topologies to achieve high step-up voltage gain [27–39]. An interleaved boost converter with a bi-fold Dickson voltage multiplier is presented in [40], in which several diodes and capacitors are employed to increase the overall voltage gain. However, the added number of diodes and capacitors increases losses and reduces efficiency. Another interleaved boost converter using two CIs and a VMC is developed in [41], achieving a very high step-up voltage gain without a high turn ratio. The voltage stress across the semiconductor switches and the passive components is reduced to lower than the output voltage. Interleaved high step-up converter presented in [42] uses BIT and VMC to have more flexible voltage gain. This topology delivers benefits such as high voltage gain, low voltage stress across the power MOSFETs, a low number of components, and low input current ripple. To reduce the size and improve transient response, switching frequency should be increased, leading to increased switching losses. Interleaved boost converter in [43] utilises the clamp capacitors and integrates the secondary winding of the BIT. Nevertheless, the voltage gain is low and can be increased when adding CI structure.In this study, a new interleaved topology is proposed by locating the secondary windings of the CI between the main MOSFETs and the primary winding of the BIT. In such a topology, the voltage gain is proportional to the multiplication of the turn ratios of CI and BIT. The proposed converter delivers the following advantages:(1)
High voltage gain (as a result of windings of the BIT and CI)(2)
Low voltage stress across MOSFETs and diodes(3)
Low input current ripple(4)
Zero current switching (ZCS) turned-OFF condition for diodes(5)
Zero current switching (ZCS) turned-ON condition for MOSFETs(6)
Alleviated reverse recovery problem of the diodes(7)
High conversion efficiency(8)
Low number of componentsThe rest of this study is organized as follows. The proposed converter and its operational principle are presented in Section2. The performance analysis of the proposed converter is studied in Section 3. Performance comparison and numerical design are discussed in Section 4 and 5, respectively. The experimental results are given in Section 6. Finally, conclusions are drawn in Section 7.


## 2. Operational Principle of the Proposed Converter

The abstract model of the proposed converter is illustrated in Figure1. As can be seen, the built-in transformer (BIT) and coupled inductor (CI) structures are utilized in this converter. This converter can achieve high voltage gain by adjusting the turns’ ratio of the BIT and CI. Two main power MOSFETs (S1 and S2), four diodes (D1,D2,D3,D4), and three capacitors (C1,C2,C3) are some other components of this converter. Lm1 and Lm2 also represent the leakage and magnetizing inductances of the CIs, respectively. BIT consists of primary, secondary, and tertiary windings with N1, N2, and N3 number of turns. LLKb also indicates its leakage inductor. Turns’ ratios of the CI and BIT are defined as n=n2/n1 and N=N2/N1=N3/N1, respectively. The proposed converter has 10 main operating modes in a single switching period. However, due to the symmetrical feature of the topology, only five operating modes are analyzed in detail in the following. The key waveforms of the proposed converter and the related equivalent circuits in each mode are depicted in Figure 2 and Figure 3, respectively.Figure 1
The abstract model of the proposed converter.Figure 2
The key waveforms of the proposed converter.Figure 3
Equivalent circuits of the proposed converter. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4. (e) Mode 5.
(a)(b)(c)(d)(e)


### 2.1. Mode 1 [t0−t1]

During this mode, both power MOSFETSS1 and S2 are in ON-state, and all the diodes are reverse-biased. The magnetizing inductances of the CIs are linearly charged by the input voltage, and the output capacitor supplies the output load:(1)ILm1t=iLK1t=iS1t=VinLm1+LLK1t−t0+ILm1t0,(2)ILm2t=iLK2t=iS2t=VinLm2+LLK2t−t0+ILm2t0.


### 2.2. Mode 2 [t1−t2]

Att1, S2 is turned-OFF. During this mode, the parallel capacitor CS2 is being linearly charged by the current of iLm2. The voltage across the switch S2 is given by(3)vDS2t=ILm2t1CS2t−t1.


### 2.3. Mode 3 [t2−t3]

Att2, the diodes D2 and D4 are turned-ON. In this mode, the leakage inductance LLK2 is discharged into the clamp capacitor C1. A positive voltage is applied across the primary winding of the BIT. The output load is supplied by the output capacitor and the secondary winding of the BIT:(4)ILm2t=iD2t+Nn+1+1iD4t,(5)iLKbt=NiD4t,(6)iDS1t=ILm1t+iD2t+Nn+1iD4t,(7)iD4t=Nn+1+1VC1+VC2−VOn2LLK1+LLK2+N2LLKbt−t2.


### 2.4. Mode 4 [t3−t4]

Att3, the current of diode D2 reaches to zero, and it is turned-OFF with ZCS. During this mode, the clamp capacitor voltage VC1 is equal to the voltage across power MOSFET S2. The current flowing through D4 is proportional to the leakage inductor’s current iLKb. At the end of this mode, the turn-ON pulse is applied to S2 and turns it ON with ZCS performance:(8)ILm2t=Nn+1+1iD4t,(9)iDS1t=ILm1t+Nn+1iD4t.


### 2.5. Mode 5 [t4−t5]

Att4, S2 is in ON-state. During this mode, the current through LLKb is decreasing. At the end of this mode, the current flowing through LLKb reches to zero. In addition, the current through D4 decreases and its falling rate is controlled by the leakage inductances:(10)diD4tdt=VC2−VOn2LLK1+LLK2+N2LLKb.


## 2.1. Mode 1 [t0−t1]

During this mode, both power MOSFETSS1 and S2 are in ON-state, and all the diodes are reverse-biased. The magnetizing inductances of the CIs are linearly charged by the input voltage, and the output capacitor supplies the output load:(1)ILm1t=iLK1t=iS1t=VinLm1+LLK1t−t0+ILm1t0,(2)ILm2t=iLK2t=iS2t=VinLm2+LLK2t−t0+ILm2t0.


## 2.2. Mode 2 [t1−t2]

Att1, S2 is turned-OFF. During this mode, the parallel capacitor CS2 is being linearly charged by the current of iLm2. The voltage across the switch S2 is given by(3)vDS2t=ILm2t1CS2t−t1.


## 2.3. Mode 3 [t2−t3]

Att2, the diodes D2 and D4 are turned-ON. In this mode, the leakage inductance LLK2 is discharged into the clamp capacitor C1. A positive voltage is applied across the primary winding of the BIT. The output load is supplied by the output capacitor and the secondary winding of the BIT:(4)ILm2t=iD2t+Nn+1+1iD4t,(5)iLKbt=NiD4t,(6)iDS1t=ILm1t+iD2t+Nn+1iD4t,(7)iD4t=Nn+1+1VC1+VC2−VOn2LLK1+LLK2+N2LLKbt−t2.


## 2.4. Mode 4 [t3−t4]

Att3, the current of diode D2 reaches to zero, and it is turned-OFF with ZCS. During this mode, the clamp capacitor voltage VC1 is equal to the voltage across power MOSFET S2. The current flowing through D4 is proportional to the leakage inductor’s current iLKb. At the end of this mode, the turn-ON pulse is applied to S2 and turns it ON with ZCS performance:(8)ILm2t=Nn+1+1iD4t,(9)iDS1t=ILm1t+Nn+1iD4t.


## 2.5. Mode 5 [t4−t5]

Att4, S2 is in ON-state. During this mode, the current through LLKb is decreasing. At the end of this mode, the current flowing through LLKb reches to zero. In addition, the current through D4 decreases and its falling rate is controlled by the leakage inductances:(10)diD4tdt=VC2−VOn2LLK1+LLK2+N2LLKb.


## 3. Performance Analysis

### 3.1. Voltage Gain Expression

The voltage acrossLm1 is equal to Vin and Vin−VC2 for the switch S1 being in ON- and OFF-state, respectively. By applying the volt-second balance principle to Lm1, the voltage across the capacitor C2 can be calculated as(11)VC2=Vin1−D.The voltage acrossLm2 is equal to Vin and Vin−VC1 for S2 being in ON- and OFF-state, respectively. By applying the volt-second balance principle to Lm2, the voltage across the capacitor C1 can be obtained as(12)VC1=Vin1−D.Using the average currents of the diodes and equations (4) and (8), the curring passing through them diodes can be calculated as(13)iD1,Ave=ILm12D78=Iout2,(14)iD2,Ave=ILm22D23=Iout2,(15)iD3,Ave=ILm12Nn+1+12−2D−D78=Iout2,(16)iD4,Ave=ILm22Nn+1+12−2D−D23=Iout2,(17)D23=D78=21−DNn+1+2,where D23 and D78 are normalized time durations of mode 3 and mode 8, respectively. Using (13)–(17), the average currents of the magnetizing inductances can be obtained as(18)ILm=ILm1=ILm2=Nn+1+221−DIout.According to Figure2, the following equation is obtained:(19)ΔiD4Δt=ILmNn+1+1D23TS,By considering the leakage inductances in the steady-state analysis, the voltage conversion ratio is derived as(20)M=VOVin=Nn+1+21−D1+QNn+1+22/4Nn+1+11−D2,where Q=n2LLK1+LLK2+N2LLKb/RTS.ForQ=0, the ideal voltage gain of the proposed converter can be calculated as(21)M=VoutVin=Nn+1+21−D.The effect of the leakage inductance on the voltage gain is shown in Figure4. As can be seen, the voltage gain of the proposed converter is decreased by increasing the leakage inductances.Figure 4
Voltage gain of the proposed converter.


### 3.2. Voltage Stress Analysis of the Semiconductor

From the mode 3, voltage stress of the power MOSFETs can be expressed as(22)VDS1=VDS2=Vin1−D=VoutNn+1+2.The voltage stress across diodes are given by(23)VD1=VD2=2VoutNn+1+2,(24)VD3=VD4=Vout2Nn+1+1Nn+1+2.Figure5 shows the normalized voltage stress across the semiconductor devices. As seen, the voltage across MOSFETs is decreased when increasing the turns’ ratio of the CI.Figure 5
Normalized voltage stress across semiconductor devices.


### 3.3. Current Stress of the Components

According to Figure2 and the steady-state analysis, the current stresses of the MOSFETs and diodes are obtained as(25)iS1,rms=iS2,rms=IoutNn+1+221−D2D−1+2Nn+1+121−DNn+1+12,(26)iD1,rms=iD2,rms=IoutNn+1+261−D,(27)iD3,rms=iD4,rms=IoutNn+1+221−DNn+1+11−D2+3Nn+13Nn+1+2,(28)iC1,rms=iD2,rms2+iD3,rms2.From (26) and (27), the RMS currents through the capacitors C1, C2, and CO are derived as(29)iC2,rms=iD1,rms2+iD4,rms2,(30)iCO=iD3,rms2+iD4,rms2−Iout2.CurrentiLK1 (iLK2) is equal to ILm1−NiC2,rms (ILm2+NiC2,rms), so using (29), its RMS value can be expressed as(31)iLk1,rms=iLk2,rms=ILm2+N2iD1,rms2+iD4,rms2.The RMS value ofiLKb can be derived using (27) as below:(32)iLKb,rms=N2iD3,rms2+N2iD4,rms2.


### 3.4. Input Current Ripple

The input current ripple of the proposed converter is given by(33)ΔIin=2D−11−DNn+1+2×VoutLmfS.The normalized input current ripple with the base value ofVout/LmfS is shown in Figure 6. As shown, the input current ripple is decreased by the turns’ ratio of the BIT and CI.Figure 6
Normalized input current ripple.


### 3.5. Efficiency Estimation

Figure7 shows the equivalent circuit of the proposed converter together with its parasitic resistances. In fact, the effects of ON-state resistances of MOSFETs and diodes, forward voltage drops of the diodes, switching losses, resistances of the windings of the magnetic devices, and equivalent series resistance (ESR) of the capacitors should be considered to calculate the efficiency.Figure 7
The equivalent circuit of the proposed converter considering the parasitic resistances.Due to the ZCS turn-ON condition for MOSFETs, the total power losses in the MOSFETs relates to conduction losses and the switching losses during turning OFF:(34)PMOSFETs=rDS1iS1,rms2+rDS2iS2,rms2+fS2VDS1iS1t6tOFF1+VDS2iS2t1tOFF2,with rDS1 and rDS2 being the ON-state resistances of S1 and S2, respectively.ON-state resistance (rD) and forward voltage drop (vFD) of the diodes can also contribute to power losses as below:(35)PD=∑i=14rDiiDi,rms2+vFDiiDi,Ave.The windings’ losses, including total CI and BIT losses, are given by(36)PWire=rL11iLK1,rms2+rL12iLKb,rms2+rL21iLLK2,rms2+rL22iLKb,rms2CI+rb1iLKb,rms2+rb2iD3,rms2+rb3iD4,rms2BIT.The power losses related to equivalent series resistance (ESR) of the capacitors can be written as(37)PC=rC1iC1,rms2+rC2iC2,rms2+rCOiCO,rms2.The core losses are given by(38)Pcore=AfSαBβVe,where Ve is the volume of core, B is maximum flux density, A, α, and β are the Steinmetz parameters given in datasheet of the selection core. The calculated core losses for each of the CIs are about 2.25 W, where it is about 1.5 W for the BIT. Therefore, the total dissipations of the cores is about 6 W.Total power losses of the proposed converter can be written as(39)PLoss=PMOSFETs+PD+PC+PWire+Pcore.Finally, the efficiency and the voltage gain of the proposed converter can be obtained as(40)η=PoutPout+PLoss.By calculating the RMS currents through the circuit components in Section3.3, the power losses related to these components can be calculated. The components specifications of the fabricated prototype in Table 1 are assumed to be as(41)rDS1=rDS2=7.5mΩ,rC1=rC2=20mΩ,rCO=100mΩ,rDi=12mΩ,fori=1,2,3,4,vFDj=1.2V,forj=1,2,3,4,rL11=rL21=12mΩ,rL12=rL22=rb1=rb2=rb3=24mΩ.Table 1
Specifications of the proposed converter.
ComponentsParametersOutput power (pout)600 WInput-output voltages (Vin − Vout)27V–400 VSwitching frequency (fs)50 kHZPower MOSFETs (S1,S2)IPP076N12N3Clamp diodes (D1,D2)MUR880Output diodes (D3,D4)MUR1560Clamp capacitors (C1,C2)5μFOutput capacitor (Cout)5μFCoupled inductorFerrite core EE55,n = 1, Lm = 168 μH, and n1 = n2 = 19 turnsBuilt-in transformerFerrite core EE55,N = 2, Lm = 800 μH, and N2 = N3 = 2N1 = 32 turnsThe conversion efficiency and the voltage gain of the proposed converter are plotted in Figure8. As shown, at a given voltage gain, by implementing of higher turns’ ratios, the duty ratio can be decreased.Figure 8
Voltage gain (M) and efficiency (%) of the proposed converter.


## 3.1. Voltage Gain Expression

The voltage acrossLm1 is equal to Vin and Vin−VC2 for the switch S1 being in ON- and OFF-state, respectively. By applying the volt-second balance principle to Lm1, the voltage across the capacitor C2 can be calculated as(11)VC2=Vin1−D.The voltage acrossLm2 is equal to Vin and Vin−VC1 for S2 being in ON- and OFF-state, respectively. By applying the volt-second balance principle to Lm2, the voltage across the capacitor C1 can be obtained as(12)VC1=Vin1−D.Using the average currents of the diodes and equations (4) and (8), the curring passing through them diodes can be calculated as(13)iD1,Ave=ILm12D78=Iout2,(14)iD2,Ave=ILm22D23=Iout2,(15)iD3,Ave=ILm12Nn+1+12−2D−D78=Iout2,(16)iD4,Ave=ILm22Nn+1+12−2D−D23=Iout2,(17)D23=D78=21−DNn+1+2,where D23 and D78 are normalized time durations of mode 3 and mode 8, respectively. Using (13)–(17), the average currents of the magnetizing inductances can be obtained as(18)ILm=ILm1=ILm2=Nn+1+221−DIout.According to Figure2, the following equation is obtained:(19)ΔiD4Δt=ILmNn+1+1D23TS,By considering the leakage inductances in the steady-state analysis, the voltage conversion ratio is derived as(20)M=VOVin=Nn+1+21−D1+QNn+1+22/4Nn+1+11−D2,where Q=n2LLK1+LLK2+N2LLKb/RTS.ForQ=0, the ideal voltage gain of the proposed converter can be calculated as(21)M=VoutVin=Nn+1+21−D.The effect of the leakage inductance on the voltage gain is shown in Figure4. As can be seen, the voltage gain of the proposed converter is decreased by increasing the leakage inductances.Figure 4
Voltage gain of the proposed converter.


## 3.2. Voltage Stress Analysis of the Semiconductor

From the mode 3, voltage stress of the power MOSFETs can be expressed as(22)VDS1=VDS2=Vin1−D=VoutNn+1+2.The voltage stress across diodes are given by(23)VD1=VD2=2VoutNn+1+2,(24)VD3=VD4=Vout2Nn+1+1Nn+1+2.Figure5 shows the normalized voltage stress across the semiconductor devices. As seen, the voltage across MOSFETs is decreased when increasing the turns’ ratio of the CI.Figure 5
Normalized voltage stress across semiconductor devices.


## 3.3. Current Stress of the Components

According to Figure2 and the steady-state analysis, the current stresses of the MOSFETs and diodes are obtained as(25)iS1,rms=iS2,rms=IoutNn+1+221−D2D−1+2Nn+1+121−DNn+1+12,(26)iD1,rms=iD2,rms=IoutNn+1+261−D,(27)iD3,rms=iD4,rms=IoutNn+1+221−DNn+1+11−D2+3Nn+13Nn+1+2,(28)iC1,rms=iD2,rms2+iD3,rms2.From (26) and (27), the RMS currents through the capacitors C1, C2, and CO are derived as(29)iC2,rms=iD1,rms2+iD4,rms2,(30)iCO=iD3,rms2+iD4,rms2−Iout2.CurrentiLK1 (iLK2) is equal to ILm1−NiC2,rms (ILm2+NiC2,rms), so using (29), its RMS value can be expressed as(31)iLk1,rms=iLk2,rms=ILm2+N2iD1,rms2+iD4,rms2.The RMS value ofiLKb can be derived using (27) as below:(32)iLKb,rms=N2iD3,rms2+N2iD4,rms2.


## 3.4. Input Current Ripple

The input current ripple of the proposed converter is given by(33)ΔIin=2D−11−DNn+1+2×VoutLmfS.The normalized input current ripple with the base value ofVout/LmfS is shown in Figure 6. As shown, the input current ripple is decreased by the turns’ ratio of the BIT and CI.Figure 6
Normalized input current ripple.


## 3.5. Efficiency Estimation

Figure7 shows the equivalent circuit of the proposed converter together with its parasitic resistances. In fact, the effects of ON-state resistances of MOSFETs and diodes, forward voltage drops of the diodes, switching losses, resistances of the windings of the magnetic devices, and equivalent series resistance (ESR) of the capacitors should be considered to calculate the efficiency.Figure 7
The equivalent circuit of the proposed converter considering the parasitic resistances.Due to the ZCS turn-ON condition for MOSFETs, the total power losses in the MOSFETs relates to conduction losses and the switching losses during turning OFF:(34)PMOSFETs=rDS1iS1,rms2+rDS2iS2,rms2+fS2VDS1iS1t6tOFF1+VDS2iS2t1tOFF2,with rDS1 and rDS2 being the ON-state resistances of S1 and S2, respectively.ON-state resistance (rD) and forward voltage drop (vFD) of the diodes can also contribute to power losses as below:(35)PD=∑i=14rDiiDi,rms2+vFDiiDi,Ave.The windings’ losses, including total CI and BIT losses, are given by(36)PWire=rL11iLK1,rms2+rL12iLKb,rms2+rL21iLLK2,rms2+rL22iLKb,rms2CI+rb1iLKb,rms2+rb2iD3,rms2+rb3iD4,rms2BIT.The power losses related to equivalent series resistance (ESR) of the capacitors can be written as(37)PC=rC1iC1,rms2+rC2iC2,rms2+rCOiCO,rms2.The core losses are given by(38)Pcore=AfSαBβVe,where Ve is the volume of core, B is maximum flux density, A, α, and β are the Steinmetz parameters given in datasheet of the selection core. The calculated core losses for each of the CIs are about 2.25 W, where it is about 1.5 W for the BIT. Therefore, the total dissipations of the cores is about 6 W.Total power losses of the proposed converter can be written as(39)PLoss=PMOSFETs+PD+PC+PWire+Pcore.Finally, the efficiency and the voltage gain of the proposed converter can be obtained as(40)η=PoutPout+PLoss.By calculating the RMS currents through the circuit components in Section3.3, the power losses related to these components can be calculated. The components specifications of the fabricated prototype in Table 1 are assumed to be as(41)rDS1=rDS2=7.5mΩ,rC1=rC2=20mΩ,rCO=100mΩ,rDi=12mΩ,fori=1,2,3,4,vFDj=1.2V,forj=1,2,3,4,rL11=rL21=12mΩ,rL12=rL22=rb1=rb2=rb3=24mΩ.Table 1
Specifications of the proposed converter.
ComponentsParametersOutput power (pout)600 WInput-output voltages (Vin − Vout)27V–400 VSwitching frequency (fs)50 kHZPower MOSFETs (S1,S2)IPP076N12N3Clamp diodes (D1,D2)MUR880Output diodes (D3,D4)MUR1560Clamp capacitors (C1,C2)5μFOutput capacitor (Cout)5μFCoupled inductorFerrite core EE55,n = 1, Lm = 168 μH, and n1 = n2 = 19 turnsBuilt-in transformerFerrite core EE55,N = 2, Lm = 800 μH, and N2 = N3 = 2N1 = 32 turnsThe conversion efficiency and the voltage gain of the proposed converter are plotted in Figure8. As shown, at a given voltage gain, by implementing of higher turns’ ratios, the duty ratio can be decreased.Figure 8
Voltage gain (M) and efficiency (%) of the proposed converter.


## 4. Performance Comparison

A performance comparison is made between the proposed converter and the previously presented interleaved converters in [28, 31, 35, 38–41, 43]. The results are provided in Table 2 and Figure 9. According to Figure 9(a), the voltage gain of the proposed converter with n=N=1 is higher than the proposed converters in [38,43]. The presented converters in [28, 35] have higher voltage gain than the proposed converter; however, as shown in Table 2, these converters have more number of components than the proposed converter. Moreover, Figure 9(b) shows the voltage stress across semiconductor devices versus different turns’ ratio. As can be seen, the proposed converter has resulted in the lowest voltage stress across power MOSFETs among all other converters for the turns’ ratios more than 3. Moreover, as shown in Table 2, measured efficiency of the proposed converter is 94.6%. According to the output voltage 400 V, output power 600 W, and switching frequency 50 kHz, measured efficiency of the proposed converter is a reasonable and acceptable value. Furthermore, the voltage gain and the voltage stress across the semiconductors in the proposed converter can be controlled by the turns’ ratio of the CI and BIT, making the design more flexible than its similar competitors.Table 2
Performance comparison of the proposed converter.
ConvertersTechniquesVout/VinVDS/VoutVD/VoutNumber of componentsMeasured efficiencyS∗/D∗/C∗/W∗/C∗∗/T∗[28]CI∗ + BIT∗ + VMC∗2Nn+2N+2/1−D1/2Nn+2N+22Nn+1+1/2Nn+1+12/6/3/7/5/23η=97%VIN=28V,VOUT=400VD=60%,fS=50kHzPOUT=600W[31]CI∗ + VMC∗3N+1/1−D1/3N+12N/3N+12/5/2/4/4/17η=97%VIN=40V,VOUT=400VD=62%,fS=50kHzPOUT=400W[35]CI∗ + BIT∗ + SC∗4+4n+2N/1−D1/4+4n+2N1+2n+N/2+2n+N2/5/3/7/5/22η=95.53%VIN=16V,VOUT=400VD=60%,fS=50kHzPOUT=200W[38]CI∗ + VMC∗n1+D+2−D/1−D1/n1+D+2−Dn+1/n1+D+2−D2/6/2/6/5/21η=92.6%VIN=48V,VOUT=380VD=60%,fS=50kHzPOUT=2KW[39]CI∗2+2N/1−D1/2+2N1+2N/2+2N2/6/2/6/5/21η=94%VIN=30V,VOUT=400VD=70%,fS=50kHzPOUT=500W[40]VMC∗2K∗/1−D1/2K∗1/K∗2/4/2/2/4/14η=96%VIN=20V,VOUT=400VD=70%,fS=50kHzPOUT=200W[41]VMC∗ + CI∗2N+2/1−D1/2N+21/N+12/7/2/4/7/22η=96.7%VIN=32V,VOUT=800VD=68%,fS=118kHzPOUT=400W[43]BIT∗n+2/1−D1/n+212/4/3/5/3/17η=94.7%VIN=48V,VOUT=380VD=62%,fS=50kHzPOUT=3.5KWProposedCI∗ + BIT∗Nn+1+2/1−D1/Nn+1+22Nn+1+1/Nn+1+22/4/3/7/3/19η=94.6%VIN=27V,VOUT=400VD=61%,fS=50kHzPOUT=600WCI∗, coupled inductor; BIT∗, built-in transformer; VMC∗, voltage multiplier cell; SC∗, switched capacitor; K∗, number of VMC; S∗, switch; D∗, diode; C∗, core; W∗, winding; C∗∗, capacitor; T∗, total.Figure 9
Performance comparison: (a) voltage gain, (b) normalized voltage stress across MOSFETs, and (c) normalized voltage stress across diodes.
(a)(b)(c)


## 5. Numerical Design

In this study, the circuit components are designed based on the following values:(42)Vin=27V,Vout=400V,fS=50kHZ,Pout=600W,Iin=23.15A,D=0.61%.In addition, the turns’ ratios of the CI and BIT are assumed to ben=1 and N=2, respectively.


### 5.1. CI and BIT Design

The magnetizing inductors of the CI are designed based on the input current ripple, which is considered 3% of input current:(43)Lm1=Lm2=2D−11−DNn+1+2×VoutΔIinfS=2×0.61−1×1−0.61×4006×0.03×23.8×50000=160μH.EE55 ferrite cores are chosen for CI. The cross-sectional areaAC and the maximum flux density Bsat are 354mm2 and 320mT, respectively. n1 is obtained as(44)n1=LmILm,MaxBMaxAC=LmILm+DVin/2LmfSBMaxAC.The value ofn1 can be obtained as(45)n1=160×10−6×11.53+0.61×27/2×160×10−6×50000300×10−3×354×10−6=18.9Turns,where BMAX=300mT is the maximum allowed swing of the flux density.During mode 3, whenS1 is in ON-sate and S2 is in OFF-state, the voltage across the primary winding of the BIT can be obtained as(46)VP,Built−InTransformer=n+1Vin1−D=N1ΔBAC1−DTs.EE55 ferrite cores are chosen for BIT. The cross-sectional areaAC and the variation of the magnetic flux density ΔB are 354mm2 and 200mT, respectively. N1 is calculated by(47)N1=n+1VinTsΔBAC=2×27×2×10−5200×10−3×354×10−6=15.25Turns.


### 5.2. Design of Capacitors

The capacitors are designed based on their voltage ripplex% (which can be extracted according to section 3). The voltage across the capacitors C1=C2 and Cout are 69.2V and 400V, respectively.By assuming the voltage ripples asx%VC1,2=8%VC1,2 and x%VCout=3%Vout, the capacitors’ values are obtained as follows:(48)C1=C2=PoutVoutΔVCfS=PoutNn+1+2x%Vout2fS=600×60.08×4002×50000=5.6μF,(49)Cout=PoutVoutΔVCoutfS=Poutx%Vout2fS=6000.03×4002×50000=2.5μF.


### 5.3. Selection of Semiconductor Devices

The semiconductor devices are selected according to their voltage stress and the currents flowing through them (the maximum and RMS values). Thus, (25)–(27) can be used to select appropriate semiconductor devices.


## 5.1. CI and BIT Design

The magnetizing inductors of the CI are designed based on the input current ripple, which is considered 3% of input current:(43)Lm1=Lm2=2D−11−DNn+1+2×VoutΔIinfS=2×0.61−1×1−0.61×4006×0.03×23.8×50000=160μH.EE55 ferrite cores are chosen for CI. The cross-sectional areaAC and the maximum flux density Bsat are 354mm2 and 320mT, respectively. n1 is obtained as(44)n1=LmILm,MaxBMaxAC=LmILm+DVin/2LmfSBMaxAC.The value ofn1 can be obtained as(45)n1=160×10−6×11.53+0.61×27/2×160×10−6×50000300×10−3×354×10−6=18.9Turns,where BMAX=300mT is the maximum allowed swing of the flux density.During mode 3, whenS1 is in ON-sate and S2 is in OFF-state, the voltage across the primary winding of the BIT can be obtained as(46)VP,Built−InTransformer=n+1Vin1−D=N1ΔBAC1−DTs.EE55 ferrite cores are chosen for BIT. The cross-sectional areaAC and the variation of the magnetic flux density ΔB are 354mm2 and 200mT, respectively. N1 is calculated by(47)N1=n+1VinTsΔBAC=2×27×2×10−5200×10−3×354×10−6=15.25Turns.


## 5.2. Design of Capacitors

The capacitors are designed based on their voltage ripplex% (which can be extracted according to section 3). The voltage across the capacitors C1=C2 and Cout are 69.2V and 400V, respectively.By assuming the voltage ripples asx%VC1,2=8%VC1,2 and x%VCout=3%Vout, the capacitors’ values are obtained as follows:(48)C1=C2=PoutVoutΔVCfS=PoutNn+1+2x%Vout2fS=600×60.08×4002×50000=5.6μF,(49)Cout=PoutVoutΔVCoutfS=Poutx%Vout2fS=6000.03×4002×50000=2.5μF.


## 5.3. Selection of Semiconductor Devices

The semiconductor devices are selected according to their voltage stress and the currents flowing through them (the maximum and RMS values). Thus, (25)–(27) can be used to select appropriate semiconductor devices.


## 6. Experimental Verification

To validate the practical feasibility of the proposed topology a 600 W, 27 V input to 400 V output laboratory prototype with the specifications provided in Table1 is fabricated. The photograph of the prototype is illustrated in Figure 10. The duty ratio is approximately 0.61. In Figure 11(a), the experimental results of the input current and the currents through the leakage inductances of the CI are shown. As shown in this figure, according to the symmetrical configuration, input current phases are equal and also the input current ripple is small. Therefore, due to the equal current sharing between two phases, the ripple cancellation is obtained. Figure 11(b) shows the output voltage and the output current. In Figure 11(c) and Figure 11(d), the experimental results of the voltage and current waveforms of the main switches S1 and S2 are illustrated. As can be observed, ZCS turn-on condition is provided for both switches. Figure 12(a) and Figure 12(b) show the experimental results of the voltage and current of clamp diodes D1 and D2. Also, Figure 12(c) and Figure 12(d) show the experimental results of the voltage and current of the output diodes D3 and D4. From the theoretical analysis in (23) and (24), the voltage stress of diodes are obtained VD1=VD2=133.3V and VD3=VD4=600V. As it clearly shows, ZCS turn-off condition is achieved for all of diodes. So, the reverse recovery problem of the diodes is alleviated. Dynamic response is shown in Figure 12(e).Figure 10
Photograph of the prototype.Figure 11
Experimental waveforms of (a) input current and the currents of the leakage inductances of the CI, (b) output voltage and output current, (c) the voltage stress and current of switchS1, and (d) the voltage stress and current of switch S2.
(a)(b)(c)(d)Figure. 12
Experimental waveforms of (a) the voltage stress and current of diodeD1, (b) the voltage stress and current of diode D2, (c) the voltage stress and current of diode D3, (d) the voltage stress and current of diode D4 {R4-7}, and (e) dynamic response.
(a)(b)(c)(d)(e)Measured and calculated efficiency curve of the proposed converter is illustrated in Figure13(a). The maximum efficiency of 96.5% is occurred at 500 W. Measured efficiency under full-load condition (600 W) is 94.6% which is almost close to the calculated of 97%.Figure 13
(a) Measured and calculated efficiency of the proposed converter; (b) pie graph of the losses distribution at full load.
(a)(b)Figure13(b) shows pie graph of the losses distribution at full load (600 W) which is 18.51 W. Power losses due to windings, cores, diodes, MOSFETs, and capacitors are 4.95 W, 6 W, 3.81 W, 3.36 W, and 0.39 W. It is seen the calculated and measured conversion efficiencies are almost close and confirm each other.


## 7. Conclusion

An interleaved high step-up converter topology based on the coupled inductor (CI) and built-in transformer (BIT) is proposed in this study. The proposed converter has the following features:(1)
By using BIT and CI, high voltage gain without extreme duty ratio is achieved.(2)
The proposed converter is much more flexible than the converters with only one of this magnetic means because of having an extra degree of freedom with simultaneous implementation.(3)
By increased turns’ ratio of CI and BIT, the voltage stress across MOSFETs relatively is decreased which facilitates the utilization of low voltage-rated MOSFETs with low ON-state resistance.(4)
Due to the interleaved structure at the input of this converter, the input current ripple is minimized(5)
The leakage inductances of the BIT and CI provide turned-OFF and turned-ON ZCS conditions for all the diodes and power MOSFETs, respectively.(6)
The energy of the leakage inductances is recycled by the clamp capacitors avoiding high spikes across MOSFETs. Moreover, the reverse recovery problem of the diodes is attenuated due to the leakage inductances of CI.It is worth noting that the voltage stress across output diodes is higher than the output voltage which is the main advantage of the proposed converter. Finally, a laboratory prototype with 27 V–400 V voltage conversion with the conversion efficiency of 94.6% at full load (600 W) has been implemented and tested to demonstrate performance of the proposed converter. As a result, the proposed converter is suitable for renewable energy system applications.



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*Source: 2645938-2022-06-06.xml*