# Proportional-Type Output Voltage-Tracking Controller for Interleaved DC/DC Boost Converter with Performance Recovery Property

Authors: Seok-Kyoon Kim
Journal: Mathematical Problems in Engineering
 (2018)

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## Abstract

This paper proposes an offset-free proportional-type output voltage-tracking algorithm embedding the disturbance observers (DOBs) for theN-phase interleaved DC/DC boost converter through a systematical multivariable approach. The contributions of this article fall into two parts. The first one is to design the first-order nonlinear DOBs for exponentially estimating the disturbances caused by the model-plant mismatches. The second one is to prove that the proposed proportional-type controller equipped with the DOBs guarantees the performance recovery property as well as the offset-free property. The performance of the proposed method is evaluated through simulations and experiments using a 3-kW four-phase interleaved DC/DC boost converter, comparing the proposed and feedback linearizing (FL) methods.


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## Body

## 1. Introduction

The DC/DC converters have been widely utilized to supply a high quality DC power despite the disturbances for a variety of industrial applications such as uninterruptible power supply and solar photovoltaic systems [1–6]. In these applications, the DC/DC converters are required to be controlled their current and output voltage with a satisfactory closed-loop performance for a wide range of operating region in the presence of the converter parameter and unexpected load variations.The cascade output voltage control strategy [7] has been commonly adopted to adjust the output voltage of the DC/DC converters where the inner and outer-loop controllers were designed to control the current and output voltage in a cascade manner. The proportional-integral (PI) controller equipped with nonlinearity cancellation terms has been mainly used for implementing both inner-loop and outer-loop controllers [7, 8], which can be interpreted as an feedback linearizing (FL) method in the control theoretical point of view. The corresponding control gains were determined for the resulting closed-loop error dynamics to be the desired low-pass filter (LPF) behavior using the converter parameters such as inductance and capacitance values. However, it is questionable that their closed-loop performance would be remaining satisfactory for the various load conditions despite the parameter uncertainties.There have been many alternative solutions based on the novel control strategy for the inner loop to attain a better closed-loop performance, which includes the deadbeat controllers [9], predictive controllers [10], sliding mode controllers [11], adaptive controllers [12], model predictive controllers [13], and robust controllers [14]. Aside from the adaptive technique, however, these novel schemes require using the converter true parameter values so as to guarantee the closed-loop stability and performance. The adaptive and sliding mode schemes were built using the true inductance value that can be dramatically decreased with increasing the inductor current. The disturbance observer (DOB) based methods were proposed for the robot manipulation [15] and the DC motor control applications [16]. Unlike [16], it is rigorously proved that the proposed proportional-type controller with the DOBs guarantees to not only exponentially recover the target output voltage-tracking performance, but also remove the steady state errors, which means that the tracking error integrators can be eliminated as well as the corresponding antiwindup algorithms.This article presents a robust output voltage-tracking algorithm based on a systematical multi-variable approach without tracking error integrators for theN-phase interleaved DC/DC boost converter, considering a planet-model mismatch such as parameter and load variations. The novelties of the proposed method are twofold; the exponentially convergent DOBs are constructed for the current and output voltage loops, and the proportional-type nonlinear controller is developed with the exponential performance recovery property and the proof of the offset-free property. These two novelties simplify the implementations of the control algorithm by eliminating the use of tracking error integrators with the anti-windup parts as well as the gain scheduling algorithms, which is the sharp contrast to the above mentioned existent methods such as model predictive and adaptive methods. The simulations and experimental results using a 3-kW four-phase interleaved DC/DC boost converter show the effectiveness of the proposed method, comparing it with the FL method.


## 2. Averaged Dynamics of Interleaved DC/DC Boost Converter

This section briefly describes the dynamical equations of the synchronous-typeN-phase interleaved DC/DC boost converter depicted in Figure 1, where the duty ratio of Di∈[0,1], i=1,2,…,N, is considered as the control action to be applied, and the phase inductor current of iL,i(t), i=1,2,…,N, and the capacitor voltage of vout(t) are treated as the state variables. Unlike the traditional single-phase boost converter, a low voltage drop switch is used as the upper-side diode and is alternatively operated with a lower-side switch, and this type of converter never enters the discontinuous conduction mode (DCM) for all time [17]. Note that the duty ratio of Di, i=1,2,…,N, produces the switching command by performing the pulse width modulation (PWM) operation. For example, the duty ratio of Di∈(0,1) renders the switch to be turned on for a period DiTs and the switch to be turned off for a period (1-Di)Ts, with Ts denoting the PWM period. Due to these operations, the averaged converter dynamics are obtained as(1)LdiL,itdt=-1-uitvdct+vin,i=1,2,…,N,Cdvdctdt=∑i=1N1-uitiL,it-iLoadt,∀t≥0, where the input source voltage is given as vin, ui(t)≔Di∈(0,1) and iLoad(t) denotes the load current. See [6, 7, 18, 19] for a detailed derivation of the averaged dynamical equations of (1).Figure 1
Interleaved DC/DC boost converter circuit.Due to an abrupt load current variation and the parameter uncertainties, such as inductance and capacitance values, the converter dynamics of (1) are rewritten regarding to the nominal parameters as(2)L0diL,itdt=-1-uitvdct+vin,0+wL,i,ot,i=1,2,…,N,(3)C0dvdctdt=∑i=1N1-uitiL,it+wv,ot,∀t≥0, with the nominal inductance and capacitance values of L0, C0, and the initial input voltage vin,0, where wL,i,o(t), wv,o(t) denote the unknown lumped disturbances caused from the parameter mismatch, unmodelled dynamics, and load uncertainties.


## 3. Output Voltage Controller Design

LetVdc∗(s) and Vdc,ref(s) be the Laplace transforms of desired output voltage behavior vdc∗(t) and its reference vdc,ref(t), respectively. The objective of this section is to construct the control law for rendering the closed-loop output voltage dynamics to be(4)Vdc∗sVdc,refs=ωvcs+ωvc,∀s∈C,with ωvc being the assignable cut-off frequency as a design parameter, while guaranteeing the current-tracking property:(5)limt→∞iL,it=iL,i,reft,i=1,…,N.In order to achieve the control objective of (4), consider the time domain expression of the target dynamics of (4) given by(6)v˙dc∗t=ωvcvdc,reft-vdc∗t,∀t≥0,and define the output voltage-tracking error as v~dc∗(t)≔vdc∗(t)-vdc(t), ∀t≥0, which gives the output voltage-tracking error dynamics using (3):(7)C0v~˙dc∗t=C0v˙dc∗t-C0v˙dct=-∑i=1N1-uitiL,it+wvt=-∑i=1N1-uitiL,i,reft+∑i=1N1-uiti~L,it+wvt,∀t≥0,where wv(t)≔C0v˙dc∗(t)-wv,o(t), i~L,i(t)≔iL,i,ref(t)-iL,i(t), ∀t≥0. An inductor current reference signal is proposed as a stabilizing solution to the output voltage-tracking error dynamics of (7):(8)iL,i,reft=1N11-uitC0λvv~dc∗t+w^vt,i=1,…,N, ∀t≥0, where λv>0 denotes a tuning parameter; the estimated disturbance w^v(t) is given by(9)w^vt≔ζvt+lvC0v~dc∗t,∀t≥0,and ζv(t) stands for the state of the nonlinear observer:(10)ζ˙vt=-lvζvt-lv2C0v~dc∗t+lv∑i=1N1-uitiL,it,∀t≥0,with lv>0 being the observer gain. For the rest of this article, the combination of two equations of (10) and (9) is called the output voltage disturbance observer (DOB).The substitution of the inductance current reference of (8) to the output voltage-tracking error dynamics of (7) leads to(11)C0v~˙dc∗t=-C0λvv~dc∗t+Δwvt+∑i=1N1-uiti~L,it,∀t≥0,where Δwv(t)≔wv(t)-w^v(t), ∀t≥0. Lemma 1 derives the closed-loop property of (11), which is used for analyzing the whole closed-loop stability analysis.Lemma 1.
Assuming that the disturbance ofwv(t) converges to its steady state value wv0, exponentially, that is, there is a positive constant of kv>0 such that(12)w~˙v0t=-kvw~v0t,∀t>0,where w~v0(t)≔wv0-wv(t), ∀t≥0, then, a specified design parameter of λv>0 with the DOB gains of(13)lv=34C0λv+1+ηv,ηv>0gives the strict passivity for the input-output mapping of(14)∑i=1N1-uii~L,i⟼v~dc∗.In [20], the strict passivity and L2 stability are formally defined, and it is proved that the strict passivity implies that L2 stability. The result of Lemma 1 indicates that the output voltage of vdc(t) converges to the target output voltage trajectory of vdc∗(t), exponentially, as the inductor current errors of i~L,i(t) vanish, exponentially. For the proof of Lemma 1, a positive definite function is defined as(15)Vvt≔C02v~dc∗t2+12w~v2t+γv2w~v0t2,∀t≥0.Then, the proof can be completed by showing that(16)V˙vt≤-αvVvt+v~dc∗t∑i=1N1-uiti~L,it,∀t≥0,for some constant αv>0 where w~v(t)≔w^v0-w^v(t), ∀t≥0, and w^v0 denotes a steady state value of w^v(t), ∀t≥0. See Appendix for details.For deriving the final control action, write the inductor current-tracking error dynamics using (2) as(17)L0i~˙L,it=L0i˙L,i,reft-L0i˙L,it=L0i˙L,i,reft+1-uitvdct-vin,0-wL,i,ot=1-uitvdct-vin,0+wL,it=-vdc∗tuit+vdc∗t-1-uitv~dc∗t-vin,0+wL,it,∀t≥0,with wL,i(t)≔L0i˙L,i,ref(t)-wL,i,o(t), i=1,…,N, ∀t≥0. Then, the stabilization can be accomplished by the proposed stabilizing control law for the duty ratio ui(t) as(18)uit=1vdc∗tL0λLi~L,it+vdc∗t-vin,0+w^L,it,i=1,…,N,∀t≥0,where the inductor current references iL,i,ref(t) come from (8), λL>0 denotes a tuning parameter, and the estimated disturbances w^L,i(t) are given by(19)w^L,it≔ζL,it+lL,iL0i~L,it,i=1,…,N,∀t≥0,and ζL,i(t) stand for the state of the dynamical equations:(20)ζ˙L,it=-lL,iζL,it-lL,i2L0i~L,it+lL,i-1-uitvdct+vin,0,i=1,…,N,∀t≥0,with lL,i>0 being the observer gains. For the rest of this article, the combination of two equations of (20) and (19) is called the inductor current DOB. The proposed controller structure is visualized in Figure 2.Figure 2
Proposed controller structure.The substitution of the proposed control law of (18) to the inductor current error dynamics of (17) yields that(21)L0i~˙L,it=-L0λLi~L,it+ΔwL,it-1-uitv~dc∗t,i=1,…,N,∀t≥0,where ΔwL,i(t)≔wL,i(t)-w^L,i(t), i=1,…,N, ∀t≥0. Lemma 2 gives the closed-loop property of (21), which is used for analyzing the closed-loop stability.Lemma 2.
Assuming that the disturbance ofwL,i(t) converges to its steady state value wL,i0, exponentially, that is, there are constants of kL,i>0 such that(22)w~˙L,i0t=-kL,iw~L,i0t,i=1,…,N,∀t>0,where w~L,i0(t)≔wL,i0-wL,i(t), ∀t≥0, then, a specified design parameter of λL>0 with the DOB gains of(23)lL,i=34L0λL+1+ηL,i,ηL,i>0,i=1,…,Ngives the strict passivity for the input-output mapping of(24)-1-uitv~dc∗t⟼i~L,it,i=1,…,N.Lemma2 shows that the inductor current-tracking error of i~L,i(t) vanishes exponentially if the output voltage-tracking error of v~dc∗(t) does so. For the proof, a positive definite function is defined as(25)VLt≔L02∑i=1Ni~L,i2t+∑i=1N12w~L,i2t+∑i=1NγL,i2w~L,i0t2,∀t≥0.The proof can be completed by showing that(26)V˙Lt≤-αLVLt-∑i=1Ni~L,i1-uitv~dc∗t,∀t≥0,for some constant αL>0 where(27)w~Lt≔w^L0-w^Lt,∀t≥0,where w^L0 denotes a steady state value of w^L(t), ∀t≥0. See Appendix for details.Finally, Theorem3 asserts that the proposed control algorithm forces the output voltage trajectory to be exponentially convergent to the target output voltage trajectory coming from the LPF dynamics of (6). The two resulting inequalities of (16) and (26) given by Lemmas 1 and 2 play the crucial role of proving Theorem 3, and the proof is given in Appendix.Theorem 3.
Assuming that the assumptions of Lemmas1 and 2 hold true, then, the proposed control law of (8), (18) with the DOBs of (9), (10), (19), and (20) forces the closed-loop system to recover the target output voltage-tracking performance of (6), exponentially; that is,(28)v~dc∗t≤κe-α/2t,∀t≥0,for some positive constants κcl and αcl.Note that, interestingly, although the proposed proportional-type control law of (8) and (18) with the DOBs of (9), (10), (19), and (20) does not include the tracking error integrators, it ensures the offset-free property, which is a practical advantage of this article. See Theorem 4 for details, and the proof is included in Appendix.Theorem 4.
The closed-loop system always eliminates the offset errors of the output voltage in the steady state. That is,(29)vdc0=vdc,ref0,where vdc0 and vdc,ref0 represent the steady-state of vdc(t) and vdc,ref(t), respectively.Remark 5.
The current and output voltage DOB dynamics can be described in a first-order LPF form (for details, see Appendix):(30)w^˙vt=lvwvt-w^vt,w^˙L,it=lL,iwL,it-w^L,it,i=1,…,N,∀t≥0.The corresponding transfer functions are given by(31)W^vsWvs=lvs+lv,W^L,isWL,is=lL,is+lL,i,i=1,…,N,∀s∈C,which implies that the DOB gains of lv,lL,i>0, i=1,…,N, can be adjusted for a cut-off frequency (rad/s) of the transfer functions of (31).


## 4. Simulations

This section evaluates the output voltage-tracking performance between the proposed and FL methods using the PowerSIM (PSIM) software with the DLL block embedding the control algorithms in the C-language. To this end, a four-phase interleaved DC/DC boost converter was considered with the parameters(32)L=40μH,C=1650μF. The input DC source voltage was set to be vin=50V, and pulse-width modulation (PWM) and the control frequencies were both chosen as 20 kHz. In order to take the parameter uncertainties into account, the nominal parameters of the converter were assumed to be(33)
L
0
=
28
μ
H
=
0.7
L
,
C
0
=
2145
μ
F
=
1.3
C
,which are adopted to constitute the control algorithms. Figure 3 visualizes the implementation of the closed-loop system.Figure 3
Implementation of the closed-loop system.The FL controller in [7] was used for a comparison given as(34)uit=1vdct-RdciL,it+L0ωcci~L,it+Rdcωcc∫0ti~L,iτdτ+vdct-vin,iL,i,reft=14-Rdvvdct+C0ωvcv~dct+Rdvωvc∫0tv~dcτdτ,i=1,…,4,∀t≥0,which yields the closed-loop transfer functions of the inner and outer-loops through the pole-zero cancellations: Vdc(s)/Vdc,ref(s)=ωvc/(s+ωvc), IL,i(s)/IL,i,ref(s)=ωcc/(s+ωcc), i=1,…,4, ∀s∈C with the adjustable active damping coefficients Rdc>0, Rdv>0, and the cut-off frequencies ωvc>0, ωcc>0. The corresponding fvc, fcc were tuned to be fvc=15Hz, fcc=1000Hz so that ωvc=2πfvc=94.2rad/s, ωcc=2πfcc=6280rad/s, and the active damping coefficients were selected as Rdc=Rdv=0.1. Note that the output voltage error decay ratio parameter λv of the proposed method was set to be the same as ωvc, and the design parameter λL was also let to be the same as the cut-off frequency of ωcc for a fair comparison because the inductor current error dynamics of (21) can be approximately given as a first-order LPF form: i˙L,i(t)=-λL(iL,i(t)-iL,i,ref(t)), i=1,…,N, ∀t≥0, for a slowly time varying inductor current reference signal of iL,i,ref(t). The DOB gains were tuned as lv=lL,i=1256rad/s, i=1,…,N, for the cut-off frequency of the corresponding transfer functions in (31) to be 200 Hz, which also meets the assumptions of (13)–(23).In the first stage, the evaluation of the output voltage-tracking performance with the resistive load ofRL=20Ω was performed where the output voltage reference was increased from 100V to 150V, and it was decreased to 120V. From the simulation results depicted in Figure 4, the proposed method successfully maintains the closed-loop performance to be the desired first-order LPF characteristic despite the parameter mismatches. Figure 5 presents the state behaviors of the DOBs.Figure 4
Output voltage-tracking performance comparison between proposed and FL methods with resistive load ofRL=20Ω.Figure 5
Disturbance estimation behaviors.In the second stage, the evaluation of the closed-loop robustness was carried out through investigating the output voltage-tracking performance variations under the same output voltage reference with the different resistive loads,RL=7.5,20,30Ω. As can be seen from the results given in Figure 6, the proposed method effectively reduces the voltage-tracking performance changes for several different loads. This is a sharp contrast to the FL method.Figure 6
Output voltage-tracking performance comparison between proposed and FL methods at three resistive loads,RL=7.5,20,30Ω.In this simulation setting, the closed-loop tracking performance was quantitatively compared for the resistive loads,RL=50,30,20,10Ω, using the two cost functions defined as(35)Jint≔∫0∞vdc∗t-vdctdt,Jmax⁡≔max⁡vdc∗t-vdct,∀t≥0,which implies that the best controller would guarantee the two cost functions of (35) to be minimized for all operating points. The resulting table is given in Table 1, which shows that the proposed method offers a better tracking performance than the FL method at least two times for these four operating points.Table 1
Quantitative output voltage-tracking performance comparison for resistive loads,RL=50,30,20,10Ω.
Load resistance value R L = 50  Ω R L = 30  Ω R L = 20  Ω R L = 10  Ω Proposed Method Jint 23281 7700 4558 1722 Jmax⁡ 10 7 5 4 Classical Method Jint 83654 58191 16325 29917 Jmax⁡ 35 35 11 8In the last stage, the evaluation of the output voltage regulation performance was conducted by using the pulse resistive load fromRL=15Ω to RL=7.5Ω at the 150 V operation mode. Figure 7 depicts the output voltage regulation comparison results with the corresponding inductor current, which implies that the proposed method effectively reduces the over/under shoots caused by the load variation, comparing the FL method.Figure 7
Output voltage regulation performance comparison between proposed and FL methods at the output voltage 150 V with the pulse resistive load fromRL=15Ω to RL=7.5Ω.


## 5. Experimental Results

This section experimentally verifies the performance of the proposed method by comparing it with the FL technique used in the previous section. In this experiment, a3-kW four-phase interleaved DC/DC converter shown in Figure 1 was utilized with the input DC source voltage level of vin=50 V, and the digital signal processor (DSP) of TMS320F28335 was used for implementing the proposed and FL control algorithms with the control and PWM periods of Ts=50μs. The experimental setup is shown in Figure 8.Figure 8
Experimental setup.Except for design parameters ofωvc, ωcc, λv, and λL, the control parameters of two controllers were left the same as that in the simulation section. These four parameters were selected as ωvc=31.4rad/s(fvc=5Hz), ωcc=2512rad/s(fcc=400Hz), and λv=ωvc, λL=ωcc.In the first stage, the evaluation of the output voltage-tracking performance was experimentally performed with an increasing output voltage reference from75V to 100V under the resistive loads of RL=6.6,20Ω. From Figures 9 and 10, as, intended, the proposed controller successfully forces the output voltage dynamics to be the desired trajectory coming from (6) for the different operation modes.Figure 9
Experimental results of output voltage-tracking performance comparison between proposed method and FL methods with resistive loadRL=6.6Ω.Figure 10
Experimental results of output voltage-tracking performance comparison between proposed and FL methods with resistive loadRL=20Ω.The second stage examines the output voltage regulation performance regarding two step load changes; the resistive load was changed from20Ω to 10Ω and from 10Ω to 6.6Ω, in a sequential manner. The resulting waveforms are shown in Figures 11 and 12, which demonstrates that the proposed method effectively enhances the output voltage regulation performance through a reduction of the undershoot originated from the abrupt load variation.Figure 11
Experimental results of output voltage regulation performance comparison between proposed and FL methods regarding to resistive load variation fromRL=20Ω to RL=10Ω.Figure 12
Experimental results of output voltage regulation performance comparison between proposed and FL methods regarding to resistive load variation fromRL=10Ω to RL=6.6Ω.From these simulation and experimental results, it can be concluded that the proposed method has the two practical merits:(1)
The proposed method would suggest an almost same closed-loop performance for various operating ranges without any gain scheduling method.(2)
The proposed method simplifies the control algorithms by getting rid of the use of the tracking error integrators with the antiwindup algorithms.


## 6. Conclusions

This paper suggests a performance recovery output voltage-tracking controller for an unknownN-phase interleaved DC/DC boost converter. Taking the parameter and load current uncertainties into account, the proposed control law was devised for the output voltage dynamics to converge to the desired behavior coming from a LPF despite the parameter and load uncertainties. Various simulation and experimental evidences confirmed that the proposed technique would provide a better closed-loop performance for several industrial applications.



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