# One Clock-Cycle Response 0.5μm CMOS Dual-Mode ΣΔ DC-DC Bypass Boost Converter Stable over Wide RESRLC Variations

Authors: Neeraj A. Keskar; Gabriel A. Rincón-Mora
Journal: Advances in Power Electronics
 (2010)

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## Abstract

Power supplies in portable applications must not only conform and adapt to their highly integrated on-chip and in-package environments but also, more intrinsically, respond quickly to fast load dumps to achieve and maintain high accuracy. The frequency-compensation network, however, limits speed and regulation performance because it must cater to all combinations of filter capacitorCO, inductor L, and CO's equivalent series resistance
RESR
resulting from tolerance and modal design targets. As such, it must compensate the worst-case condition and therefore restrain the performance of all other possible scenarios, even if the likelihood of occurrence of the latter is considerably high and the former substantially low. Sigma-delta (ΣΔ) control, which addresses this issue in buck converters by easing its compensation requirements and offering one-cycle transient response, has not been able to simultaneously achieve high bandwidth, high accuracy, and wide RESRLC compliance in boost converters. This paper presents a dual-mode ΣΔ boost bypass converter, which by using a high-bandwidth bypass path only during transient load-dump events was experimentally 1.41 to 6 times faster than the state of the art in current-mode ΣΔ boost supplies, and this without any compromise in RESRLC compliance range (0–50 mΩ, 1–30 μH, and 1–350 μF).


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## Body

## 1. Introduction

In portable applications like cellular phones, PDAs, and the like, integrated BiCMOS and CMOS switching dc-dc supply circuits reduce cost, size, component count, and design complexity (from a user’s perspective). One of the critical bottlenecks in obtaining a fully integrated solution, however, is the frequency-compensation circuit, which is designed around off-chip power LC filter devices to obtain optimal performance [1]. The fact is mode-rich state-of-the-art applications, manufacturing tolerances, and parameter drifts expose dc-dc converter integrated circuits (ICs) to wide variations in output capacitance CO, power inductance L, and CO’s equivalent series resistance RESR, inducing considerable changes in loop-gain and transient response, compromising feedback stability or transient response. As a result, to guarantee stability and high bandwidth with a fixed on-chip frequency-compensation circuit, the design necessarily constrains RESRLC values within a narrow target range [1]. This is especially detrimental in compact high-performance multiple input-output converters [2, 3], where the on-chip or in-package LC filter is variable by design to dynamically accommodate the diverse loading conditions of the system.Unclocked or asynchronous sigma-delta (ΣΔ) buck converters [4–8] are self-compensating and free of the speed-stability tradeoffs of most dc-dc converters because the control loop in these converters resembles current-mode control by indirectly sensing the inductor current ripple via the ripple voltage it drops across CO’s RESR. In other words, the ESR voltage mostly sets the terminal ripple voltage of CO, impressing the inductor ripple current information on the output voltage and achieving current-mode-like control. The resulting single-pole-like response yields higher bandwidth and more explicit control over the output ripple voltage [7].Extending this technique and its benefits to boost converters, which are popular in portable electronics for boosting battery voltages to 3.3–5 V, is not straightforward because the inductor current does not fully flow toCO. Consequently, in realizing ΣΔ control in boost converters, the feedback circuit must explicitly sense and mix inductor current with the sensed output voltage [9]. Such techniques, however, resurrect the limiting speed-stability tradeoffs ΣΔ control averted in buck converters in the first place, forcing the designer to adjust current and voltage gains thereby reducing the loop bandwidth in order to accommodate largeRESRLC filter values.This paper presents a dual-mode boostΣΔ bypass controller IC that overcomes the aforementioned speed-stability compromise by introducing a high-speed bypass mode (and circuit) that engages only during transient load-dump events, achieving both high bandwidth and wide RESRLC compliance. To this end, Section 2 first reviews and discusses the stability requirements of ΣΔ converters and their resulting transient response to fast load dumps. Section 3 then describes the proposed dual-mode technique and the design of its IC-prototype embodiment, followed by experimental results in Section 4; Section 5 draws relevant conclusions.


## 2.ΣΔ Converters

### 2.1.ΣΔ Control in Buck Converters

AΣΔbuck converter, as shown in Figure 1, controls the frequency and duty cycle of PMOS switch SM by comparing rippling output voltage vO via sensed voltage vS against dc reference VREF with comparator CPV. Operationally, ac inductor ripple current il flows into CO and its RERS (which is relatively large in these converters at 100–250 mΩ to ensure its voltage —vesr— overwhelms ac capacitor voltage vc) [7] as capacitor displacement current ic, forcing ac output ripple voltage vo to mimic il (vo≈vesr=ilRESR). As a result, in regulating vo, the converter also regulates il, which in the process simplifies the frequency response of the converter to that of a single-pole system, as in current-mode control, guaranteeing stability, irrespective of RESRLC values.Figure 1
Circuit schematic of a switchingΣΔbuck converter.In a positive load-step transient event, when load currentiO suddenly rises, comparator CPV detects the voltage droop the now larger iO induces on vO and consequently switches SM on indefinitely (i.e., at 100% duty cycle) until vO returns within CPV’s predefined hysteretic window limits, that is, within an acceptably low margin of VREF. During SM’s on time, the inductor voltage being nearly constant at VIN − VO, inductor current iL slews in a single switching cycle until it fully supplies iO and recharges CO back to VREF [8]. In other words, only the inductor and capacitor slew-rate limits and second-order delays across the comparator and switch set the response time (effective bandwidth) of the system. Note a negative load dump undergoes a similar but reversed response.


### 2.2.ΣΔ Control in Boost Converters

Unlike buck converters, ac inductor ripple currentil in boost converters does not flow completely to output capacitor CO because reverse-biased diode D (shown in Figure 2) temporarily disconnects L from vO (and CO) when switch SM conducts all of iL to ground. The resulting ac ripple voltage in vO does not fully reflect the behavior of il, as it does in buck converters with nonnegligible RESRvalues, which means that ΣΔ control in boost converters cannot rely on vO alone [9]. The negative feedback loop in a boosting supply must therefore sense, scale, and mix iL with vO explicitly (e.g., mix iLRIgmi and vOgmv into RS as scaled sum vSUM) to achieve current-mode-like control characteristics. A hysteretic comparator then modulates SM’s frequency and duty cycle based on how the scaled sum (vSUM) of the ripples compares against a user-defined hysteresis window. Note the voltage feedback loop modulates the effective inductor reference current vI.REF/RI, which is also the average inductor current IL (or low-pass filtered —LPF— version of iL) to whatever is necessary to fully supply iO.Figure 2
Circuit schematic of a switchingΣΔ boost converter.Within the context of averaged small-signal analysis, the relatively high-gain, low-bandwidth voltage control loop (V Loop) of the system effectively embeds a higher bandwidth, lower gain current loop (ILoop), as shown Figure 3 [10]. At low frequencies, below low-pass filter pole pLPF, iLRI nearly equals vI.REF and the gain of the current loop is practically zero, but increasing with frequency until reaching its highest possible gain at frequencies past pLPF. The current loop’s gain again drops at high frequencies, past the complex LC double poles, when the ac voltage across L decreases. Given that iL is, for all practical purposes, regulated to higher frequencies and therefore is a current source to the outer voltage loop at moderate-to-high frequencies, CO and effective load resistance RO set the dominant low-frequency pole of the system while L and RO invoke right-half plane zero zRHP [11].Figure 3
Small-signal equivalent control diagram of switchingΣΔ boost converter at moderate-to-high frequencies.For stable conditions to prevail, the unity-gain frequency of the voltage loop (i.e., the system —fV.0dB—) must fall below zRHP and iL must remain a current source (i.e., current loop must stay closed with considerable loop gain) for the frequency range of interest to the voltage loop [10]. As such, fV.0dB must stay below both zRHP and current-loop bandwidth fI.0dB:(1)f0dBV≈gmvDM′2πRIgmiCO<<f0dBI≈RIgmiRSMVO2πL,(2)f0dBV≈gmvDM′2πRIgmiCO<zRHP=DM′VO2πLIL,
or
(3)LILVOCO=LIOCOVODM′<RIgmigmv,
where DM is the duty-cycle of SM, DM′ is (1-DM), and M is the modulator gain. Note that zRHP and fI.0dB shift to lower frequencies with increasing inductance values, which means that fV.0dB must also decrease accordingly, in an ideal case. LPF pole pLPF, whose location indicates the lowest frequency at which the current loop is closed, must also be below the worst-case value of fV.0dB to ensure there is enough gain for iL to remain a current source:(4)pLPF<~fV.0dB|min=DM′2VO2πLIL.
Ultimately, the system responds to a load dump at the speed of the voltage loop, whose bandwidth is fV.0dB, allowing switch SM to cycle multiple times before restoring vO back to its target window. LPF pole pLPF limits the extent to which iL naturally responds to a load dump by allowing moderate-to-high frequency ac error-correcting signals through the current loop. In other words, the current loop limits (while attempting to regulate) the rising and falling rates of average iL below iL’s maximum possible slew-rates of VIN/L and (vO – VIN)/L. Because fV.0dB and pLPFboth decrease with increasing L, with the former also decreasing with decreasing CO, the worst-case LC combination, from the perspective of stability, occurs at the highest L and lowest CO, the condition for which gains RIgmiRS and gmvRS and pole pLPF are adjusted and transient-response performance over the entire LC filter range is sacrificed.


## 2.1.ΣΔ Control in Buck Converters

AΣΔbuck converter, as shown in Figure 1, controls the frequency and duty cycle of PMOS switch SM by comparing rippling output voltage vO via sensed voltage vS against dc reference VREF with comparator CPV. Operationally, ac inductor ripple current il flows into CO and its RERS (which is relatively large in these converters at 100–250 mΩ to ensure its voltage —vesr— overwhelms ac capacitor voltage vc) [7] as capacitor displacement current ic, forcing ac output ripple voltage vo to mimic il (vo≈vesr=ilRESR). As a result, in regulating vo, the converter also regulates il, which in the process simplifies the frequency response of the converter to that of a single-pole system, as in current-mode control, guaranteeing stability, irrespective of RESRLC values.Figure 1
Circuit schematic of a switchingΣΔbuck converter.In a positive load-step transient event, when load currentiO suddenly rises, comparator CPV detects the voltage droop the now larger iO induces on vO and consequently switches SM on indefinitely (i.e., at 100% duty cycle) until vO returns within CPV’s predefined hysteretic window limits, that is, within an acceptably low margin of VREF. During SM’s on time, the inductor voltage being nearly constant at VIN − VO, inductor current iL slews in a single switching cycle until it fully supplies iO and recharges CO back to VREF [8]. In other words, only the inductor and capacitor slew-rate limits and second-order delays across the comparator and switch set the response time (effective bandwidth) of the system. Note a negative load dump undergoes a similar but reversed response.


## 2.2.ΣΔ Control in Boost Converters

Unlike buck converters, ac inductor ripple currentil in boost converters does not flow completely to output capacitor CO because reverse-biased diode D (shown in Figure 2) temporarily disconnects L from vO (and CO) when switch SM conducts all of iL to ground. The resulting ac ripple voltage in vO does not fully reflect the behavior of il, as it does in buck converters with nonnegligible RESRvalues, which means that ΣΔ control in boost converters cannot rely on vO alone [9]. The negative feedback loop in a boosting supply must therefore sense, scale, and mix iL with vO explicitly (e.g., mix iLRIgmi and vOgmv into RS as scaled sum vSUM) to achieve current-mode-like control characteristics. A hysteretic comparator then modulates SM’s frequency and duty cycle based on how the scaled sum (vSUM) of the ripples compares against a user-defined hysteresis window. Note the voltage feedback loop modulates the effective inductor reference current vI.REF/RI, which is also the average inductor current IL (or low-pass filtered —LPF— version of iL) to whatever is necessary to fully supply iO.Figure 2
Circuit schematic of a switchingΣΔ boost converter.Within the context of averaged small-signal analysis, the relatively high-gain, low-bandwidth voltage control loop (V Loop) of the system effectively embeds a higher bandwidth, lower gain current loop (ILoop), as shown Figure 3 [10]. At low frequencies, below low-pass filter pole pLPF, iLRI nearly equals vI.REF and the gain of the current loop is practically zero, but increasing with frequency until reaching its highest possible gain at frequencies past pLPF. The current loop’s gain again drops at high frequencies, past the complex LC double poles, when the ac voltage across L decreases. Given that iL is, for all practical purposes, regulated to higher frequencies and therefore is a current source to the outer voltage loop at moderate-to-high frequencies, CO and effective load resistance RO set the dominant low-frequency pole of the system while L and RO invoke right-half plane zero zRHP [11].Figure 3
Small-signal equivalent control diagram of switchingΣΔ boost converter at moderate-to-high frequencies.For stable conditions to prevail, the unity-gain frequency of the voltage loop (i.e., the system —fV.0dB—) must fall below zRHP and iL must remain a current source (i.e., current loop must stay closed with considerable loop gain) for the frequency range of interest to the voltage loop [10]. As such, fV.0dB must stay below both zRHP and current-loop bandwidth fI.0dB:(1)f0dBV≈gmvDM′2πRIgmiCO<<f0dBI≈RIgmiRSMVO2πL,(2)f0dBV≈gmvDM′2πRIgmiCO<zRHP=DM′VO2πLIL,
or
(3)LILVOCO=LIOCOVODM′<RIgmigmv,
where DM is the duty-cycle of SM, DM′ is (1-DM), and M is the modulator gain. Note that zRHP and fI.0dB shift to lower frequencies with increasing inductance values, which means that fV.0dB must also decrease accordingly, in an ideal case. LPF pole pLPF, whose location indicates the lowest frequency at which the current loop is closed, must also be below the worst-case value of fV.0dB to ensure there is enough gain for iL to remain a current source:(4)pLPF<~fV.0dB|min=DM′2VO2πLIL.
Ultimately, the system responds to a load dump at the speed of the voltage loop, whose bandwidth is fV.0dB, allowing switch SM to cycle multiple times before restoring vO back to its target window. LPF pole pLPF limits the extent to which iL naturally responds to a load dump by allowing moderate-to-high frequency ac error-correcting signals through the current loop. In other words, the current loop limits (while attempting to regulate) the rising and falling rates of average iL below iL’s maximum possible slew-rates of VIN/L and (vO – VIN)/L. Because fV.0dB and pLPFboth decrease with increasing L, with the former also decreasing with decreasing CO, the worst-case LC combination, from the perspective of stability, occurs at the highest L and lowest CO, the condition for which gains RIgmiRS and gmvRS and pole pLPF are adjusted and transient-response performance over the entire LC filter range is sacrificed.


## 3. Proposed Dual-ModeΣΔ Controller IC

The proposedΣΔ boost controller IC in Figure 4 overcomes the transient-response degradation associated with the worst-case LC combination by bypassing the main voltage loop (and its fV.0dB) with a fast (and lower low-frequency loop gain) feed-forward path only during transient events. The stability requirements of the main loop set the acceptable RESRLC range for the system while the high-bandwidth bypass path allows the system to respond in one cycle at the maximum possible inductor current slew rate, the response of which is similar to ΣΔ buck converters. The transient improvement is achieved on chip (i.e., without an off-chip frequency compensation circuit) and without sacrificing LC compliance.Figure 4
Simplified schematic of the proposed dual-modeΣΔ boost converter.


### 3.1. Steady-State and Bypass Operation

The basic objective of the bypass mode is to override nominal equivalent average inductor current referenceIL(nom) (vI.REF/RI) to a higher value almost instantly only during load dumps and allow the bypass voltage loop to control and limit how much of the extra current in L flows to vO. Initially, during steady-state conditions, the bypass circuit is inactive and load current iO and SM’s average off duty cycle DM′ (i.e., one minus SM’s average on duty cycle DM) set the nominal average inductor current IL(nom) required to support a given iO, which is higher than iO because SM steers a portion of iL away from vO to ground according to DM:(5)IL(nom)=IODM′=IO1-DM.
In the bypass mode, however, independent loops regulate iL to a value higher than IL(nom) and sensed output voltage vS to VREF, as depicted in the equivalent circuit of  Figure 5.Figure 5
Equivalent circuit of the proposedΣΔconverter in the bypass mode.The current loop, which modulates switching frequencyfSW and SM’s duty cycle dM, has higher bandwidth and appears as a current source for frequencies of interest to the lower bandwidth bypass voltage loop controlling auxiliary switchSA. In the bypass mode, inductor current iL is regulated at a value IPK or VPK/RI that is greater than IL(nom) (i.e., IL required to support IO). This means, unless otherwise limited, average diode current ID is now higher than IO, as a result of which CO recharges quickly. Once vO is back within the hysteretic window limit of bypass comparator CPB and about to surpass its upper boundary, CPB andSA divert excess current away from D throughSA until iO again discharges vO to CPB’s lower window limit. The switching cycle repeats as average inductor current IL gradually drops back to IL(nom), at which point the bypass loop stops switching andSA remains open. Note as long as IL exceeds IL(nom), the bypass voltage loop, by independently regulating vO with higher loop gain than the current loop, ensures that the voltage inputs of summing comparator CPS are virtually short-circuited (i.e., vS≈VREF), as shown in Figure 6, allowing CPS to regulate iL exclusively.Figure 6
Simplified conceptual circuit schematic of the dual-modeΣΔ converter in bypass mode, as the bypass loop virtually shorts vS and VREF and the current loop regulates iL to vI.REF/RI.With respect to stability, as already mentioned, the unity-gain frequency of the current loop (fI.0dB) must exceed that of the bypass voltage loop (fB.0dB) so the inductor appears as a current source in the voltage loop, eliminating the complex conjugate pair associated with LC in the voltage loop [12]. Because the unity-gain bandwidth of a ΣΔ loop is its switching frequency, SM’s switching frequency (fI.0dB) must exceed that ofSA (fB.0dB). Therefore, since fI.0dB depends on the rising and falling rates of iLRI as it traverses CPS’s hysteretic current window HI,(6)fI.0dB=(HIRI)-1(LVIN+LVO-VIN)-1=VIN(VO-VIN)RIVOHIL
and fB.0dB on how fast excess iD (i.e., DM′IL – ID) and IO charge and discharge output capacitor CO between CPB’s hysteretic voltage window HV,(7)fB.0dB=(HV(R1+R2)R2)-1(COIO+CO(DM′IL-IO))-1,
to force fI.0dB to be greater than fB.0dB, CO must exceed
(8)CO≥(HIHV)(IOLVORIDM′)(R2R1+R2)≡CO(min),
where the R1-R2 divider represents the effect of the resistive feedback factor on HV and CO(min)the minimum stable output capacitance.


### 3.2. Transient Response and Mode Transition

During a positive load-dump event, whenIO suddenly rises and vO droops in response, as shown in Figure 7, the dual-mode converter enters its bypass mode, raising iL to peak value IPK (or VPK/RI) in a single switching cycle of SM. Subsequently vO (or vS) is pulled back to VREF (R1+R2)/R2 (or VREF) in a single switching cycle of SA. Transient-detect comparator CPT in Figure 4 perceives the load dump and engages the bypass mode by sensing whenvS drops below VREF by a preset threshold value of ΔVBP (e.g., 2.5% of VREF) (after the delay the comparator requires to switch: td). Then, CPT clamps vI.REF to peak voltage VPK, the value of which sets the maximum current the circuit can drive. Switch SM therefore remains closed (tt.M(on)) until iL reaches VPK/RI (IPK), the new value of vI.REF/RI. After SM resumes switching and regulating iL about IPK, SA remains open and allows all diode current iD to flow to vO until CO recharges to (VREF+HV/2)·(R1+R2)/R2. Beyond this point, CPB and SA regulate vS about VREF by switching SA, in other words, by steering excess inductor current away from CO.Figure 7
Transient-response performance when presented with fast load-steps (positive and negative).Ultimately, output voltagevO droops in response to load dump ΔiO until iL reaches IPK. First, excess current ΔiO discharges CO during delay td while vS reaches VREF-ΔVBP. Then, while SM raises iL from iL(avg) (or VREF/RI or IL(nom)1) to IPK(or VPK/RI), iD is zero and full load current IO discharges CO, yielding a total variation (ΔvO) of(9)ΔvO=ΔVBP+(IOCO)tt.M(on)=ΔVBP+(IOCO)[(IPK-IL(nom)1)LVIN]=ΔVBP+(IOCO)(VPK-vI.REF)LRIVIN.
Note that the ratio of L and CO sets the dominant part of ΔvO.Once sensed output voltagevS is within the hysteretic voltage window of CPB, to transition back to steady state, iL(avg) must somehow fall back to whatever value (IL(nom)) is necessary to sustain IO, reducing to zero the amount of excess current iL that bypass comparator CPB steers away from vO through SA. To that end, introducing a series negative offset voltage VI.OS, as shown in Figure 8, ensures that iL is always above its target (i.e., iL(avg)is greater than vI.REF/RI), forcing the loop to gradually decrease both iL(avg) and the excess current. Finally, when iL is low enough to be able to fully supply iO, and the excess current (DM′IL–IO) is zero, the bypass loop stops switching (i.e., disengages), which means that the main voltage loop now regulates vO via SM (Figure 4) to its target. In other words, henceforth, iL(avg) equals IL(nom). Note that the transition is continuous, allowing SA to stop switching without incurring irregularities in SM.Figure 8
Equivalent converter circuit in bypass mode with added offset voltageVI.OS to ensure that vI.REF/RI is slightly below iL(avg).During a negative load dump, wheniO suddenly drops, as also shown in Figure 7, iL(avg) automatically exceeds its new steady-state target and vO rises above its target. As a result, bypass comparator CPB engages and diverts current away from vO until vS again drops to VREF–HV/2 (in one cycle of SA). The circuit gradually transitions back to steady state in the same manner as described earlier, through VI.OS.


## 3.1. Steady-State and Bypass Operation

The basic objective of the bypass mode is to override nominal equivalent average inductor current referenceIL(nom) (vI.REF/RI) to a higher value almost instantly only during load dumps and allow the bypass voltage loop to control and limit how much of the extra current in L flows to vO. Initially, during steady-state conditions, the bypass circuit is inactive and load current iO and SM’s average off duty cycle DM′ (i.e., one minus SM’s average on duty cycle DM) set the nominal average inductor current IL(nom) required to support a given iO, which is higher than iO because SM steers a portion of iL away from vO to ground according to DM:(5)IL(nom)=IODM′=IO1-DM.
In the bypass mode, however, independent loops regulate iL to a value higher than IL(nom) and sensed output voltage vS to VREF, as depicted in the equivalent circuit of  Figure 5.Figure 5
Equivalent circuit of the proposedΣΔconverter in the bypass mode.The current loop, which modulates switching frequencyfSW and SM’s duty cycle dM, has higher bandwidth and appears as a current source for frequencies of interest to the lower bandwidth bypass voltage loop controlling auxiliary switchSA. In the bypass mode, inductor current iL is regulated at a value IPK or VPK/RI that is greater than IL(nom) (i.e., IL required to support IO). This means, unless otherwise limited, average diode current ID is now higher than IO, as a result of which CO recharges quickly. Once vO is back within the hysteretic window limit of bypass comparator CPB and about to surpass its upper boundary, CPB andSA divert excess current away from D throughSA until iO again discharges vO to CPB’s lower window limit. The switching cycle repeats as average inductor current IL gradually drops back to IL(nom), at which point the bypass loop stops switching andSA remains open. Note as long as IL exceeds IL(nom), the bypass voltage loop, by independently regulating vO with higher loop gain than the current loop, ensures that the voltage inputs of summing comparator CPS are virtually short-circuited (i.e., vS≈VREF), as shown in Figure 6, allowing CPS to regulate iL exclusively.Figure 6
Simplified conceptual circuit schematic of the dual-modeΣΔ converter in bypass mode, as the bypass loop virtually shorts vS and VREF and the current loop regulates iL to vI.REF/RI.With respect to stability, as already mentioned, the unity-gain frequency of the current loop (fI.0dB) must exceed that of the bypass voltage loop (fB.0dB) so the inductor appears as a current source in the voltage loop, eliminating the complex conjugate pair associated with LC in the voltage loop [12]. Because the unity-gain bandwidth of a ΣΔ loop is its switching frequency, SM’s switching frequency (fI.0dB) must exceed that ofSA (fB.0dB). Therefore, since fI.0dB depends on the rising and falling rates of iLRI as it traverses CPS’s hysteretic current window HI,(6)fI.0dB=(HIRI)-1(LVIN+LVO-VIN)-1=VIN(VO-VIN)RIVOHIL
and fB.0dB on how fast excess iD (i.e., DM′IL – ID) and IO charge and discharge output capacitor CO between CPB’s hysteretic voltage window HV,(7)fB.0dB=(HV(R1+R2)R2)-1(COIO+CO(DM′IL-IO))-1,
to force fI.0dB to be greater than fB.0dB, CO must exceed
(8)CO≥(HIHV)(IOLVORIDM′)(R2R1+R2)≡CO(min),
where the R1-R2 divider represents the effect of the resistive feedback factor on HV and CO(min)the minimum stable output capacitance.


## 3.2. Transient Response and Mode Transition

During a positive load-dump event, whenIO suddenly rises and vO droops in response, as shown in Figure 7, the dual-mode converter enters its bypass mode, raising iL to peak value IPK (or VPK/RI) in a single switching cycle of SM. Subsequently vO (or vS) is pulled back to VREF (R1+R2)/R2 (or VREF) in a single switching cycle of SA. Transient-detect comparator CPT in Figure 4 perceives the load dump and engages the bypass mode by sensing whenvS drops below VREF by a preset threshold value of ΔVBP (e.g., 2.5% of VREF) (after the delay the comparator requires to switch: td). Then, CPT clamps vI.REF to peak voltage VPK, the value of which sets the maximum current the circuit can drive. Switch SM therefore remains closed (tt.M(on)) until iL reaches VPK/RI (IPK), the new value of vI.REF/RI. After SM resumes switching and regulating iL about IPK, SA remains open and allows all diode current iD to flow to vO until CO recharges to (VREF+HV/2)·(R1+R2)/R2. Beyond this point, CPB and SA regulate vS about VREF by switching SA, in other words, by steering excess inductor current away from CO.Figure 7
Transient-response performance when presented with fast load-steps (positive and negative).Ultimately, output voltagevO droops in response to load dump ΔiO until iL reaches IPK. First, excess current ΔiO discharges CO during delay td while vS reaches VREF-ΔVBP. Then, while SM raises iL from iL(avg) (or VREF/RI or IL(nom)1) to IPK(or VPK/RI), iD is zero and full load current IO discharges CO, yielding a total variation (ΔvO) of(9)ΔvO=ΔVBP+(IOCO)tt.M(on)=ΔVBP+(IOCO)[(IPK-IL(nom)1)LVIN]=ΔVBP+(IOCO)(VPK-vI.REF)LRIVIN.
Note that the ratio of L and CO sets the dominant part of ΔvO.Once sensed output voltagevS is within the hysteretic voltage window of CPB, to transition back to steady state, iL(avg) must somehow fall back to whatever value (IL(nom)) is necessary to sustain IO, reducing to zero the amount of excess current iL that bypass comparator CPB steers away from vO through SA. To that end, introducing a series negative offset voltage VI.OS, as shown in Figure 8, ensures that iL is always above its target (i.e., iL(avg)is greater than vI.REF/RI), forcing the loop to gradually decrease both iL(avg) and the excess current. Finally, when iL is low enough to be able to fully supply iO, and the excess current (DM′IL–IO) is zero, the bypass loop stops switching (i.e., disengages), which means that the main voltage loop now regulates vO via SM (Figure 4) to its target. In other words, henceforth, iL(avg) equals IL(nom). Note that the transition is continuous, allowing SA to stop switching without incurring irregularities in SM.Figure 8
Equivalent converter circuit in bypass mode with added offset voltageVI.OS to ensure that vI.REF/RI is slightly below iL(avg).During a negative load dump, wheniO suddenly drops, as also shown in Figure 7, iL(avg) automatically exceeds its new steady-state target and vO rises above its target. As a result, bypass comparator CPB engages and diverts current away from vO until vS again drops to VREF–HV/2 (in one cycle of SA). The circuit gradually transitions back to steady state in the same manner as described earlier, through VI.OS.


## 4. Experimental Results and Discussion

### 4.1. IC Design

The proposed dual-modeΣΔ bypass converter was designed, fabricated, and evaluated using a 0.5μm, 5 V CMOS process. The circuit embodiment of the converter, as shown in Figure 9, employs a differential-signal processing scheme to attenuate the effects of substrate noise on the high-bandwidth ΣΔ loops [10]. For simplicity, series resistor RI senses iL with the understanding more power efficient techniques are possible and recommended [13]. Current-sense amplifier ADI, which monitors the voltage across RI, includes an internal RC filter that generates differential current reference vI.REF. Differential preamplifier ADV buffers and amplifies sensed output voltage vS by 5V/V to decrease the effects of offsets and hysteretic window limits in posterior amplifiers and comparators on vS and vO (i.e., improve accuracy); ADV drives differential summing amplifier ADS, bypass hysteretic comparator CPB, and transient-detect hysteretic comparator CPB.Figure 9
0.5μm CMOS circuit embodiment of the proposed dual-mode ΣΔ bypass boost converter.For ease of design and reliability, main, bypass, and transient-detect comparators CPM, CPB, and CPT adopt the same circuit architecture, which is designed to yield a hysteretic window of 140 mV. The bypass threshold voltage (ΔVBP) is composed of half the comparator hysteretic window plus an additional offset of 50 mV (VV.OS) that is added between CPB and CPT. Differential current-sense amplifier ADI includes a 40 mV offset voltage (VI.OS) at its output to ensure iL is below its target by VI.OS/RI during the bypass mode, to gradually transition back to steady state after a load dump. The designed offsets are sufficiently large to dwarf the transistor mismatch-induced offsets in ADI, CPB, and CPT and ensure that the polarities of VV.OS and VI.OS remain unchanged across process and temperature corners.In the absence of deep-N or buried layer isolation structures, the bulk of a single PMOS transistor serving the function of auxiliary switchSA could not be connected to the highest potential (vO) because of latch-up concerns. Whenever the switching node flies above vO following the turn-off of SM, SA’s body diode can conduct engaging the parasitic vertical PNP transistor present, channeling considerable current to the substrate. A second PMOS device is therefore added in series to use its reverse-biased body diode to block the foregoing current. And during normal operating conditions, when vO is higher than VIN, as the body diode of the first blocks the current of the second.The proposedΣΔ controller 0.5μm IC was designed to supply power from a 2.7–4.2 V Li-Ion battery and drive a 0-1 A load at 5V ± 5% with as wide an RESRLC range as possible (0–50 mΩ, 1–30μH, and 1–350μL was achieved). The total silicon surface area the IC occupied was 1.9×2.6 mm (Figure 10). The peak efficiency of the converter was 93% at 0.4A with a biasing quiescent current of 1.5 mA. The total output voltage variation of the converter in response to a 0.1–1A load dump (ΔiO) with 5 mΩ, 5.6 μH, and 53 μF of RESRLC was 200 mV, which constitutes a 4x improvement over its nonbypassed counterpart under similar conditions (800 mV).Figure 10
Die photograph and performance summary.


### 4.2. LC Compliance

The measuredRESRLC space for which the converter was stable is 0–50 mΩ, 1–30μH, and 1–350μF, as illustrated in Figure 11. This range was determined by subjecting the converter to 0.1–1A load dumps with 100 nanoseconds rise and fall times. The stability limit was observed as a loss of regulation for the proposedΣΔ converter in the bypass mode, as the bypass loop was no longer able to control the loop, and subharmonic oscillations for the nonbypassed (state-of-the-art) ΣΔ boost converter [14].Figure 11
Nominal steady-state snapshot of inductor currentiL and output voltage vO ripples (inset) for the proposed solution and experimental RESRLC stability space for both the proposed dual- and state-of-the-art single-mode boost ΣΔ converters.The stability limits for both converters, with and without the bypass path, are reached when their respective current-loop bandwidths (fI.0dB) approach their voltage-loop counterparts (fB.0dB and fV.0dB), as that is whenLceases to be a current source for the voltage loop, be the main loop, or the bypass loop. As a result, because fV.0dB and fB.0dB increase with decreasing CO and increasing IO and fI.0dB and RHP zero zRHP decrease with increasingLand decreasing VIN, the highest L-IO(30 μH–1A) and lowest CO-VIN (12 μF-2.7 V) combination constitutes worst-case conditions. Since RESRessentially introduces a left-half plane zero in the voltage loop, increasing RESRalso increases fV.0dB and fB.0dB, which means that the above-mentioned limits along with the highest RESRvalue (50 mΩ) describe the worst-case stability point of the converter. In other words, CO(min) increases with increasing L, IO, and RESRand decreasing VIN.The maximum capacitance was limited to 350μF as a practical limit for the intended portable application space (the circuit is stable at higher CO values). Similarly, the maximum RESRvalue was limited to 50 mΩ to keep the output voltage ripple acceptably low under a 1 A load. Under these conditions and constraints, the stability spaces for the proposed and the state-of-the-art converters are approximately equal in “volume.”


### 4.3. Transient Load-Dump Performance

As shown in Figure12(a), the transient-response variation of vO (ΔvO) in response to 0.1–1A load dumps (ΔiO) with 100 nanoseconds rise and fall times under 2.7 V, 5.6 μH, 53μF, and 5 mΩ of VIN, L, CO, and RESRwas 200 mV for the proposed dual-mode scheme and 800 mV for its single-mode state-of-the-art counterpart. While the proposed converter responds by increasing iL above its target (to IPK or VPK/RI) in one switching cycle of SM, the state-of-the-art circuit increasesiL gradually, pullingvO back to regulation in several cycles of SM, which is why the proposed solution exhibits a fourfold improvement over its predecessor. In a negative load-step (Figure 12(b)), while the excess inductor current is immediately bypassed by switch SA in the proposed converter keeping the output voltage overshoot low (<75 mV), the excess inductor energy causes a large voltage overshoot (600 mV) in the state-of-the-art converter.Measured transient performance of the proposed dual-mode and state-of-the-art single-modeΣΔboost converters in response to (a) 0.1–1 A and (b) 1–0.1 A load steps.
(a)(b)Decreasing (increasing)L increases (decreases) the rate at which iL responds to a load dump, as shown in Figure 13, thereby decreasing (increasing) the time vO slews (reducing ΔvO). Similarly, increasing (decreasing) CO decreases (increases) vO’s droop rate in response to a load dump (Figure 14). Note that increasing (decreasing) CO also increases (decreases) the delay time between the load step and the onset of bypass threshold voltage ΔVBP(td)(Figure 7), which is why the onset of iL rising shifts with CO.Figure 13
Measured effects ofLon the transient performance of the proposed dual-mode ΣΔ bypass boost in response to 0.1–1 A load dumps, CO=53μF.Figure 14
Measured effects ofCO on the transient performance of the proposed dual-mode ΣΔ bypass boost converter in response to 0.1–1 A load dumps.Although transient-response performance for the proposed dual-mode scheme improves with decreasingL, the same is not true for the single-mode converter whose iL response time is limited by the bandwidth of the loop, not L’s slew rate. As a result, as illustrated in Figure 15, the percentage improvement that the dual-mode enjoys over its single-mode counterpart increases with decreasing L: 6- and 1.43-fold improvement at 1μH–36μF and 30μH–36μF, respectively.Figure 15
Measured transient output voltage variationΔvO under various LC combinations in response to 0.1–1 A load dumps (ΔiO) for the proposed dual-mode and state-of-the-art single-mode ΣΔ converters.IncreasingCO decreases vO’s transient droop in both converter cases, except that bypass threshold voltage ΔVBP effectively limits the extent to which a larger CO decreases ΔvO  in the proposed scheme. In the limit, increasing CO to such an extent that ΔvO is less than ΔVBP would prevent the bypass mode from ever engaging. As a result, the performance improvement in ΔvO  is lower between the proposed and state-of-the-art solutions at higher CO values: ΔvO  for the proposed and state of the art asymptotically converge as CO increases.


### 4.4. Mode Transition

Figures16 and 17 illustrate how the proposed dual-mode ΣΔ bypass boost converter transitions from steady state to bypass mode and back in response to positive and negative 0.1–0.6A load dumps with an LC combination of 15μH and 53 μF. As designed, the bypass mode ripple is larger at ±70 mV (±(HV/2)·(R1+R2)/(R2ADV) ≈±140 mV/2) or ±1.4% than the steady-state counterpart, which is at ±15 mV or ±0.3%. During a positive load dump (Figure 16), when iO suddenly rises, a load-induced drop in vO exceeding the ΔVBP limit engages the bypass mode and increases iL to 2.5 A (IPK) in one switching cycle of SM. As determined by offset VI.OS, the circuit then takes approximately 2.5 ms to gradually decrease  iL back to its new target of roughly 1.3A, at which pointSA stops switching and the converter is back in steady state. During a negative load dump (Figure 17), iL is automatically above its target and SA consequently starts diverting some of  iL back to VIN almost immediately, until 2.5 ms later, when  iL drops to its new target.Figure 16
Measured steady state to bypass and back transitions in response to positive 0.1–0.6 A load dumps (positiveΔiO).Figure 17
Measured steady state to bypass and back transitions in response to negative 0.6–0.1 A load dumps (negativeΔiO).The main drawbacks of the auxiliary bypass path are the silicon real estate, power, and switching noise associated with power switchSA. The latter two shortcomings, however, are more often than not inconsequential because they only occur during transient events, which are typically sporadic, short, and seldom occur without significantly affecting the steady-state power efficiency (Figure 18). The prominent disadvantage of the proposed solution is therefore additional silicon real estate forSA because it carries substantial current. The transient-performance benefits of SA  and the bypass path that drives it, however, offset this cost.Figure 18
Measured steady-state efficiencyVs. Load current IO for the proposed converter.


## 4.1. IC Design

The proposed dual-modeΣΔ bypass converter was designed, fabricated, and evaluated using a 0.5μm, 5 V CMOS process. The circuit embodiment of the converter, as shown in Figure 9, employs a differential-signal processing scheme to attenuate the effects of substrate noise on the high-bandwidth ΣΔ loops [10]. For simplicity, series resistor RI senses iL with the understanding more power efficient techniques are possible and recommended [13]. Current-sense amplifier ADI, which monitors the voltage across RI, includes an internal RC filter that generates differential current reference vI.REF. Differential preamplifier ADV buffers and amplifies sensed output voltage vS by 5V/V to decrease the effects of offsets and hysteretic window limits in posterior amplifiers and comparators on vS and vO (i.e., improve accuracy); ADV drives differential summing amplifier ADS, bypass hysteretic comparator CPB, and transient-detect hysteretic comparator CPB.Figure 9
0.5μm CMOS circuit embodiment of the proposed dual-mode ΣΔ bypass boost converter.For ease of design and reliability, main, bypass, and transient-detect comparators CPM, CPB, and CPT adopt the same circuit architecture, which is designed to yield a hysteretic window of 140 mV. The bypass threshold voltage (ΔVBP) is composed of half the comparator hysteretic window plus an additional offset of 50 mV (VV.OS) that is added between CPB and CPT. Differential current-sense amplifier ADI includes a 40 mV offset voltage (VI.OS) at its output to ensure iL is below its target by VI.OS/RI during the bypass mode, to gradually transition back to steady state after a load dump. The designed offsets are sufficiently large to dwarf the transistor mismatch-induced offsets in ADI, CPB, and CPT and ensure that the polarities of VV.OS and VI.OS remain unchanged across process and temperature corners.In the absence of deep-N or buried layer isolation structures, the bulk of a single PMOS transistor serving the function of auxiliary switchSA could not be connected to the highest potential (vO) because of latch-up concerns. Whenever the switching node flies above vO following the turn-off of SM, SA’s body diode can conduct engaging the parasitic vertical PNP transistor present, channeling considerable current to the substrate. A second PMOS device is therefore added in series to use its reverse-biased body diode to block the foregoing current. And during normal operating conditions, when vO is higher than VIN, as the body diode of the first blocks the current of the second.The proposedΣΔ controller 0.5μm IC was designed to supply power from a 2.7–4.2 V Li-Ion battery and drive a 0-1 A load at 5V ± 5% with as wide an RESRLC range as possible (0–50 mΩ, 1–30μH, and 1–350μL was achieved). The total silicon surface area the IC occupied was 1.9×2.6 mm (Figure 10). The peak efficiency of the converter was 93% at 0.4A with a biasing quiescent current of 1.5 mA. The total output voltage variation of the converter in response to a 0.1–1A load dump (ΔiO) with 5 mΩ, 5.6 μH, and 53 μF of RESRLC was 200 mV, which constitutes a 4x improvement over its nonbypassed counterpart under similar conditions (800 mV).Figure 10
Die photograph and performance summary.


## 4.2. LC Compliance

The measuredRESRLC space for which the converter was stable is 0–50 mΩ, 1–30μH, and 1–350μF, as illustrated in Figure 11. This range was determined by subjecting the converter to 0.1–1A load dumps with 100 nanoseconds rise and fall times. The stability limit was observed as a loss of regulation for the proposedΣΔ converter in the bypass mode, as the bypass loop was no longer able to control the loop, and subharmonic oscillations for the nonbypassed (state-of-the-art) ΣΔ boost converter [14].Figure 11
Nominal steady-state snapshot of inductor currentiL and output voltage vO ripples (inset) for the proposed solution and experimental RESRLC stability space for both the proposed dual- and state-of-the-art single-mode boost ΣΔ converters.The stability limits for both converters, with and without the bypass path, are reached when their respective current-loop bandwidths (fI.0dB) approach their voltage-loop counterparts (fB.0dB and fV.0dB), as that is whenLceases to be a current source for the voltage loop, be the main loop, or the bypass loop. As a result, because fV.0dB and fB.0dB increase with decreasing CO and increasing IO and fI.0dB and RHP zero zRHP decrease with increasingLand decreasing VIN, the highest L-IO(30 μH–1A) and lowest CO-VIN (12 μF-2.7 V) combination constitutes worst-case conditions. Since RESRessentially introduces a left-half plane zero in the voltage loop, increasing RESRalso increases fV.0dB and fB.0dB, which means that the above-mentioned limits along with the highest RESRvalue (50 mΩ) describe the worst-case stability point of the converter. In other words, CO(min) increases with increasing L, IO, and RESRand decreasing VIN.The maximum capacitance was limited to 350μF as a practical limit for the intended portable application space (the circuit is stable at higher CO values). Similarly, the maximum RESRvalue was limited to 50 mΩ to keep the output voltage ripple acceptably low under a 1 A load. Under these conditions and constraints, the stability spaces for the proposed and the state-of-the-art converters are approximately equal in “volume.”


## 4.3. Transient Load-Dump Performance

As shown in Figure12(a), the transient-response variation of vO (ΔvO) in response to 0.1–1A load dumps (ΔiO) with 100 nanoseconds rise and fall times under 2.7 V, 5.6 μH, 53μF, and 5 mΩ of VIN, L, CO, and RESRwas 200 mV for the proposed dual-mode scheme and 800 mV for its single-mode state-of-the-art counterpart. While the proposed converter responds by increasing iL above its target (to IPK or VPK/RI) in one switching cycle of SM, the state-of-the-art circuit increasesiL gradually, pullingvO back to regulation in several cycles of SM, which is why the proposed solution exhibits a fourfold improvement over its predecessor. In a negative load-step (Figure 12(b)), while the excess inductor current is immediately bypassed by switch SA in the proposed converter keeping the output voltage overshoot low (<75 mV), the excess inductor energy causes a large voltage overshoot (600 mV) in the state-of-the-art converter.Measured transient performance of the proposed dual-mode and state-of-the-art single-modeΣΔboost converters in response to (a) 0.1–1 A and (b) 1–0.1 A load steps.
(a)(b)Decreasing (increasing)L increases (decreases) the rate at which iL responds to a load dump, as shown in Figure 13, thereby decreasing (increasing) the time vO slews (reducing ΔvO). Similarly, increasing (decreasing) CO decreases (increases) vO’s droop rate in response to a load dump (Figure 14). Note that increasing (decreasing) CO also increases (decreases) the delay time between the load step and the onset of bypass threshold voltage ΔVBP(td)(Figure 7), which is why the onset of iL rising shifts with CO.Figure 13
Measured effects ofLon the transient performance of the proposed dual-mode ΣΔ bypass boost in response to 0.1–1 A load dumps, CO=53μF.Figure 14
Measured effects ofCO on the transient performance of the proposed dual-mode ΣΔ bypass boost converter in response to 0.1–1 A load dumps.Although transient-response performance for the proposed dual-mode scheme improves with decreasingL, the same is not true for the single-mode converter whose iL response time is limited by the bandwidth of the loop, not L’s slew rate. As a result, as illustrated in Figure 15, the percentage improvement that the dual-mode enjoys over its single-mode counterpart increases with decreasing L: 6- and 1.43-fold improvement at 1μH–36μF and 30μH–36μF, respectively.Figure 15
Measured transient output voltage variationΔvO under various LC combinations in response to 0.1–1 A load dumps (ΔiO) for the proposed dual-mode and state-of-the-art single-mode ΣΔ converters.IncreasingCO decreases vO’s transient droop in both converter cases, except that bypass threshold voltage ΔVBP effectively limits the extent to which a larger CO decreases ΔvO  in the proposed scheme. In the limit, increasing CO to such an extent that ΔvO is less than ΔVBP would prevent the bypass mode from ever engaging. As a result, the performance improvement in ΔvO  is lower between the proposed and state-of-the-art solutions at higher CO values: ΔvO  for the proposed and state of the art asymptotically converge as CO increases.


## 4.4. Mode Transition

Figures16 and 17 illustrate how the proposed dual-mode ΣΔ bypass boost converter transitions from steady state to bypass mode and back in response to positive and negative 0.1–0.6A load dumps with an LC combination of 15μH and 53 μF. As designed, the bypass mode ripple is larger at ±70 mV (±(HV/2)·(R1+R2)/(R2ADV) ≈±140 mV/2) or ±1.4% than the steady-state counterpart, which is at ±15 mV or ±0.3%. During a positive load dump (Figure 16), when iO suddenly rises, a load-induced drop in vO exceeding the ΔVBP limit engages the bypass mode and increases iL to 2.5 A (IPK) in one switching cycle of SM. As determined by offset VI.OS, the circuit then takes approximately 2.5 ms to gradually decrease  iL back to its new target of roughly 1.3A, at which pointSA stops switching and the converter is back in steady state. During a negative load dump (Figure 17), iL is automatically above its target and SA consequently starts diverting some of  iL back to VIN almost immediately, until 2.5 ms later, when  iL drops to its new target.Figure 16
Measured steady state to bypass and back transitions in response to positive 0.1–0.6 A load dumps (positiveΔiO).Figure 17
Measured steady state to bypass and back transitions in response to negative 0.6–0.1 A load dumps (negativeΔiO).The main drawbacks of the auxiliary bypass path are the silicon real estate, power, and switching noise associated with power switchSA. The latter two shortcomings, however, are more often than not inconsequential because they only occur during transient events, which are typically sporadic, short, and seldom occur without significantly affecting the steady-state power efficiency (Figure 18). The prominent disadvantage of the proposed solution is therefore additional silicon real estate forSA because it carries substantial current. The transient-performance benefits of SA  and the bypass path that drives it, however, offset this cost.Figure 18
Measured steady-state efficiencyVs. Load current IO for the proposed converter.


## 5. Conclusion

A dual-modeΣΔ bypass boost dc-dc controller 0.5μm CMOS IC that is stable for an RESRLC filter range of 0–50 mΩ, 1–30 μH, and 1–350 μF and responds to positive and negative load dumps in one switching cycle has been proposed, designed, fabricated, and evaluated. The driving feature of the foregoing solution is a robust on-chip (i.e., smooth transitioning) ΣΔ bypass path that responds only during transient load dumps. While the converter increases inductor current iL in one switching cycle in response to a sudden rise in load current iO and uses it to quickly slew output capacitor CO back to its target, it also limits how much of iL flows to CO in the case of a negative load dump, when iO drops, limiting the total transient variation of output voltage vO and therefore improving accuracy performance. The transient-response benefits of the proposed scheme, as compared to state-of-the-art single-mode ΣΔ converters, are the highest at low values of L (e.g., 6x at 1μH and 1.41x or 40% improvement at 30μH) because L limits how fast iL rises and falls to its targets. The main drawback of the proposed technique is the additional silicon real estate required for auxiliary power switch SA, which is partially (and often completely) offset by its improved accuracy performance. In summary, the proposed dual-mode ΣΔ bypass boost converter is fast, widely LC compliant (robust), and easily implementable.



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*Source: 253508-2010-05-11.xml*