# An Improved Topology of Isolated Bidirectional Resonant DC-DC Converter Based on Wide Bandgap Transistors for Electric Vehicle Onboard Chargers

Authors: Md. Tanvir Shahed; A. B. M. Harun-Ur Rashid
Journal: International Transactions on Electrical Energy Systems
 (2023)

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## Abstract

This article proposes an improved topology for an isolated bidirectional resonant DC-DC converter for electric vehicle (EV) onboard chargers. As opposed to the conventional capacitor-inductor-inductor-inductor-capacitor (CLLLC) resonant converter, the proposed converter’s resonant circuit is composed of a capacitor-inductor-inductor-inductor (CLLL) structure, whose inductances, except the capacitor, can be fully integrated with the leakage and mutual inductances of the high-frequency transformer (HF). Therefore, this offers a smaller size, lower costs, minimal power loss, and eventually higher efficiency. Again, the proposed converter design is based on wide bandgap (WBG) transistor switches that operate at MHz-level switching frequency to achieve high power density, high efficiency, and high compactness. A discrete-time proportional integral derivative (PID) controller has been designed using the phase-shifted pulse width modulation (PSPWM) technique to assure closed-loop control of the proposed CLLL converter. The PID controller parameters have been optimized using both the genetic algorithm (GA) and particle swarm optimization (PSO) algorithm and a comparative analysis has been presented between the two algorithms. To achieve fast switching with very little switching loss, the converter is simulated with several wide bandgap (WBG) switching devices. A performance comparison with conventional Si-based switching devices is also provided. A precise power loss model of the semiconductor switches has been devised from the manufacturer’s datasheet to achieve a perfect thermal design for the converter. A 5 kW CLLL converter with an input range of 400–460 V direct current (DC) and an output range of 530–610 V DC, and a switching frequency of 1 MHz has been designed and investigated under various loading scenarios. Gallium nitride (GaN) switching device-based designs achieved the highest levels of efficiency among the switching devices. The efficiency of this device is 97.40 percent in charging mode and 96.67 percent in discharging mode.


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## Body

## 1. Introduction

Bidirectional DC-DC converters (BDCs) are used in a wide range of applications that require bidirectional power transmissions, such as electric vehicles (EVs), renewable energy systems, industrial systems, DC power distribution systems, aerospace power supplies, more electric aircraft (MEA) power supplies, uninterruptible power supplies (UPS), and fuel cell and battery energy storage systems (BESS) [1–8]. These types of high-power high gain BDCs are capable of achieving both DC voltage variation and electrical isolation. Figure 1 shows a schematic illustration of a standard EV onboard battery charger system, which contains an AC-DC power factor correction (PFC) stage and a bidirectional DC-DC converter (BDC) [9]. The PFC stage is connected to the AC power grid through an EMI filter and a DC link capacitor to achieve unity PFC and AC to pure DC conversion. The BDC connects an EV battery pack with the DC link capacitor to achieve current and voltage regulation as well as galvanic isolation which is essential for V2G applications. These BDCs can power EV battery loads while also providing power feedback to the power grid. Dual active bridge (DAB) [10, 11] and CLLLC [12–16] converters are among the current BDC topologies that have drawn a lot of focus because of the high-frequency (HF) transformers’ simplistic and symmetrical architecture on both sides, high efficiency, high conversion ratio, and high power density.Figure 1
Schematic illustration of a standard EV onboard battery charger system.The main benefit of a DAB resonant BDC over a CLLLC resonant BDC is the lack of resonant capacitors that need to endure high voltage strains. Contrarily, the CLLLC resonant BDC can soft switch in almost any loading situation. With no auxiliary circuit required, these converter’s semiconductor switches can achieve zero voltage switchings (ZVS) on the inverter side and zero current switchings (ZCS) on the rectification side, allowing them to use higher switching frequencies.Several research studies have been carried out to improve the performance of CLLLC resonant BDCs for various applications because of the CLLLC resonant converter’s current popularity and broad application prospects. For instance, Wang et al. [17] developed a novel paralleled CLLLC converter technique that distributes system load evenly among the parallel CLLLC units. As a consequence, the system power handling capability and power density can be enhanced. In [16], an innovative operation mode analysis was developed to determine the optimum tank parameters for a specific set of circumstances. To build high-power-density resonant converters, it is shown in [18] that increasing the switching frequency from 65 kHz to 1 MHz reduces the overall size of resonant components by almost half. Zong et al. [19] established a double voltage rectification modulation approach that provides a step-up voltage gain to widen the operating voltage range of resonant BDCs. A technique to lessen the electromagnetic interference (EMI) noise generated by the common-mode (CM) CLLLC BDCs was put forth by Chu et al. [20]. Consequently, CM chokes can be reduced in size, while the converter power density can be increased. In [15], a WBG switching device-based CLLLC converter was designed and evaluated. GaN switching devices have been proven to be the most efficient. The PID controller parameters, nevertheless, are not optimized in this work. However, in symmetrical bidirectional topologies, such as the CLLLC converter [12–16], there are at least five resonant elements, whereas, in asymmetric bidirectional topologies, such as the proposed CLLL converter, there are only four resonant elements, which thus helps in reducing the difficulty of parameter design. It also minimizes the design’s size and cost. This proposed CLLL resonant network combines all of the advantages of a lower-order resonant converter, by absorbing all parasitic components, and enabling operation at high switching frequencies with minimal switching losses. The resonant inductors can be synthesized from the HF transformer’s leakage inductance and can be fully integrated with the HF transformer. By altering the air gap between the windings and core halves, the leakage inductance can be changed. The loss and the core volume of the converter will be reduced as a result of this integrated transformer. As a result, asymmetric bidirectional topologies are thought to be more flexible and efficient. However, no breakthroughs in the field of asymmetric bidirectional topologies research have been made since it is challenging to develop a parameter design procedure that equips the converter with a similar bidirectional operating characteristic.Furthermore, passive resonant components account for a sizable portion of the total space of switching converters. The most obvious method for lowering the size of passive components is unquestionably the use of higher switching frequencies. Nonetheless, even partial hard-switching at a higher switching frequency at any switching device can result in significant switching losses, thus degrading the efficiency noticeably and thereby adding to the burden of thermal management. Because of this, this article, which focuses on EV onboard battery charger application areas, uses the CLLL resonant structure as a more practical choice for HF DC/DC conversion without no extra control complexity needed to facilitate soft switching.Additionally, because of the advancement of recent semiconductor technologies, third-generation WBG semiconductor switching devices such as silicon carbide (SiC) and GaN switching devices have been developed to help BDCs achieve a relatively high switching frequency, high efficiency, and high power density by displacing conventional devices such as silicon MOSFETs and silicon IGBTs. An overall view of the few key material characteristics of these devices is given in [21]. GaN material is a great option for high-voltage and high-frequency applications because it has the highest breakdown voltage, energy bandgap, and electron velocity characteristics, according to the comparative data presented in [21]. Additionally, GaN switching devices feature lower gate charges and on-resistance than Si and SiC switching devices, resulting in lower switching charges and rapid switching transition. Furthermore, rapid switching transition leads to less switching loss. Besides that, GaN switching devices offer a lesser output capacitance, which results in reduced switching loss and makes it simpler to implement ZVS. Other Si and SiC-based switching devices require an antiparallel diode, but GaN 2D electron gas (2DEG) does not require one because it can operate in the third quadrant. It consequently has no reverse recovery loss, which lowers switching loss and reduces EMI noise. Despite having less thermal conductivity than SiC, GaN switching devices can provide high power densities with efficient cooling approaches. GaN switching devices are therefore capable of maintaining high efficiency during the high-frequency operation among the semiconductor switching devices that are currently available [15].In this regard, this research focuses on developing a high-performance 5 kW 400–460 V DC input 530–610 V DC output 1 MHz bidirectional isolated asymmetric CLLL resonant DC-DC converter utilizing various switching devices. Efficiency calculations were performed using an exact switching device power loss model. A PSPWM-baseddiscrete-time PID controller has been created to control the output voltage and supervise the bidirectional power conversions. The PSO and GA-based optimization techniques have been used to optimize the PID coefficients. The developed converter was evaluated for different switching devices from major manufacturers during the simulation, with the E-mode GaN high electron mobility transistor (HEMT) offering the highest efficiency when compared to the other semiconductor switches.


## 2. Proposed Bidirectional CLLL Converter Operation Principle

The schematic of the proposed isolated bidirectional asymmetric resonant CLLL converter is shown in Figure2. As can be seen, it employs fewer passive elements than conventional CLLLC converters [15]. This results in high efficiency and power density, which are discussed in detail in the section “Results and Discussions.”Figure 2
Schematic of the proposed isolated bidirectional CLLL resonant DC-DC converter.Both charging (G2V, or grid to vehicle) and discharging (V2G, or vehicle to grid) modes are possible with the converter. Two full-bridge converters with four switches each make up this CLLL converter. To accomplish inversion, the S14, as well as S23 switches, are activated in the forward direction at 50% duty cycle. S58 and S67 will achieve rectification with their antiparallel diodes. GaN transistors have inherent reverse conduction capabilities, hence antiparallel diodes are not necessary when using them as switching devices. Only the reverse conduction of Si, SiC MOSFET, and IGBT transistors necessitates antiparallel diodes. In one operation period, the proposed CLLL resonant converter has six stages. The driving circuit’s operational scenarios are identical in both forward and backward directions; only the resonant components differ. As a result, the converter’s operating principles are essentially identical in both directions, and only one operating direction needs to be investigated. The forward operation principle is discussed in detail in [22], so it will not be discussed further in this paper. Following a thorough examination of the operational procedures, it is revealed that the CLLL resonant DC-DC converter can achieve ZVS on primary-side semiconductor switches as well as ZCS on secondary-side semiconductor switches.


## 3. Design of the Proposed Isolated Bidirectional CLLL Resonant Converter

The converter design includes finding the turns ratio of the transformer (n), formulating the magnetizing inductance Lm, capacitances C1, and inductances L1andL2, as well as developing a PSPWM-baseddiscrete-time PID controller.


### 3.1. Transformer’s Turns Ratio Design

Resonant BDCs are most efficient at the self-resonant frequency,fr. As a result, the converter ought to operate at this frequency under typical operating circumstances. The transformer’s turns ratio can then be determined as(1)n=N1N2=Vin_nomVo_nom,where N1,N2,Vin_nom,andVo_nom represent the transformer’s primary and secondary turns ratios, and nominal input and output voltages, respectively.


### 3.2. Resonant Components Design

Figure3 displays the CLLL converter’s equivalent circuit model in both directions. The components of the resonant tanks are L1, L2, Lm, and C1. When the converter is operating at its self-resonant frequency, the total impedance is pure resistance. As a result, at self-resonant frequency, the converter’s reactive impedance should be zero. The following equation can be derived from Figure 3:(2)−j1ωrC1+jωrL1+jωrLmn2L2Lm+n2L2=0.Figure 3
Schematic of the proposed converter’s equivalent circuit model in (a) forward power flow mode and (b) reverse power flow mode.
(a)(b)By simplifying equation (2), the self-resonant frequency can be obtained, as shown in the following equation:(3)fr=12πC1L1+Lmn2L2/Lm+n2L2.LetRe,L2′ be the corresponding equivalent Ro,L2 of the CLLL converters and here, Ro stands for the converter’s output load resistance. It is possible to calculate the equivalent load resistance by using the fundamental harmonic approximation (FHA) technique. For the G2V (battery charging) mode, L2′ and Re,c of the converter can be calculated as follows [15]:(4)L2′=n2L2,Re,c=8n2π2Ro.The parameters for the V2G (battery discharging) mode will be the same, and they are as follows [15]:(5)L2′=L2n2,Re,d=8n2π2Ro.By keeping the current flowing through primary-side switches negative at the time of turn-on, ZVS in these switches can be ensured. The primary current of the converter ought to be able to completely charge and discharge the output capacitors of the primary switches during the dead timetdead. The magnetizing inductance Lm and the length of the dead time determine the amount of this current. Therefore, the primary side switches’ ZVS is controlled by the magnetizing inductance Lm, output capacitance of switching devices Coss, operating frequency, and dead time tdead. This converter performs in dead time such as an LLC resonant DC-DC converter [23]. This allows the magnetizing inductance to be expressed in a manner that is similar to that of the full-bridge LLC resonant DC-DC converter. Thus, the expression [15] is(6)Lm≤tdead16Cossfs,max,where fs,max denotes the highest switching frequency of the proposed converter.Under various load conditions, a relatively low magnetizing inductanceLm guarantees ZVS in primary-side switching devices. On the other hand, Lm can never be set too low. Too little Lm would cause the magnetizing current to be extremely high, which would result in significant conduction losses, higher primary-side capacitor peak voltage requirements, and higher apparent power requirements for switching devices. A low magnetizing current is produced by a high magnetizing inductance, but the converter’s voltage gain is constrained. Consequently, the magnetizing inductance Lm should not be too high.The dead timetdead between switching devices has an impact on the ZVS range as well. ZVS will be easier to achieve for a broad range of input and output voltages with long dead time tdead. Additionally, by uplifting the inductance with a lengthy dead time tdead, the magnetizing current could be decreased. On the other hand, a relatively high dead time tdead will cause a high primary RMS current because there will be no transfer of energy during the dead-time duration. All of these issues must be kept in mind when designing the magnetizing inductance, Lm of the proposed converter.Figure4 depicts the fluctuation of the converter voltage gain over a range of normalized frequencies (fr/fs ratio) with varied loading circumstances, i.e., different quality factors, Q=L1/C1/Re. As a result, the output voltage can be regulated by modifying the converter’s switching frequency fs. Within a suitable switching frequency range, the converter can function in the inductive area (as illustrated in Figure 4), where the switch voltage leads the tank current waveform, ensuring that the voltage returns to zero before the current rises and so ensuring ZVS.Figure 4
Gain waveforms of CLLL converter for different loading conditions.


### 3.3. PSPWM-BasedDiscrete-Time PID Controller Design

The proposed discrete-time PID controller’s block schematic, which is based on PSPWM, is provided in the following Figure5.The three main components of the controller are the “ZOH” (zero order hold) block, the “discrete-time PID controller transfer function” block, and the “phase shift PWM ” block. The difference signal between the reference and actual output voltage levels is sampled by the “ZOH” block and stored there. The output voltage is then stabilized and regulated by the “discrete-time PID controller transfer function” block using proportional, integral, and derivative control. The following equation can be used to represent the transfer function of the discrete-time PID controller in theZ domain [15]:(7)Cz=Kp+KiTszz−1+KdNz−11+NTsz−1,where Kp,Ki,andKd denote the proportional, integral, and derivative gains of the proposed PID controller, respectively, Ts denotes the sampling period, and N denotes the parameter of the first-order filter on the derivative term.Once more, equation (7) can be changed to yield the following [15] expression:(8)Cz=b0+b1z−1+b2z−2a0+a1z−1+a2z−2,which has the following coefficients:(9)b0=Kp1+NTs+KiTs1+NTs+KdN,b1=−Kp2+NTs+KiTs+2KdN,b2=Kp+KdN,a0=1+NTs,a1=−2+NTs,a2=1.However, the PID controller gains in [15] are determined by trial and error, which is not an optimized process. As a result, the converter is incapable of effectively stabilizing and regulating the output voltage. Because of this, efforts have been made in this work to optimize the PID controller gains. Two optimization techniques, genetic algorithm (GA) [24, 25] and particle swarm optimization (PSO) [26–28], were used to optimize the PID controller gains. Their step responses were also compared for the stability analysis. Because PLECS excels at the power electronics system level simulation and MATLAB is required for controller optimization, MATLAB and PLECS co-simulation were used in this work. In the GA, the search for the optimal solution space mimics the way natural selection drives biological evolution. It repeatedly adjusts a population of individual solutions and, at each step, picks people from the current population to be parents and utilizes them to generate offspring for the upcoming generation. The population progresses toward an optimal solution over subsequent generations by achieving the best fitness value. ITAE (integral of time weighted absolute error) is employed as the fitness function in this case. The pseudocode for the GA algorithm (see Algorithm1) is as follows:Algorithm 1: Pseudocode of the genetic algorithm [24].
(1)
Initialize random population;(2)
Evaluate the population;(3)
Generation = 0;(4)
While the termination criterion is not satisfied do(5)
Generation = generation + 1;(6)
Select elite individuals with lower fitness scores;(7)
Perform crossover with probability crossover;(8)
Perform mutation with probability mutation;(9)
Evaluate the population;(10)
End while(11)
Return the best individual during the evolution;Figure6 shows the minimum observed fitness value as the genetic algorithm solver progresses. The optimized controller parameter by the genetic algorithm is given as(10)Kp=11.0956,Ki=−12.7484,Kd=−3.8236,N=3.0057.Figure 5
Block schematic for the proposed PID controller [15].PSO, like GA, is a population-based algorithm. The main advantage of the PSO is that it can find the best solution with the least amount of computation. This PSO algorithm is inspired by the swarming flocks of birds or insects. Based on an objective function, each particle is drawn to some extent to the best place it has located this far, as well as the best location found by any member of the swarm. After a few iterations, the population may congregate around a single site, a few spots, or continue to migrate.The pseudocode for the PSO algorithm (see Algorithm2) is as follows:Algorithm 2: Pseudocode of the PSO algorithm [26].
(1)
Initialize the size of the particle swarm and other parameters;(2)
Randomly initialize the position and velocity of particles;(3)
While the termination criterion is not satisfied do(4)
Fori = 1 to the number of particles do(5)
Calculate the fitness function;(6)
Update the personal and global best of each particle;(7)
Update the velocity of the particle;(8)
Update the position of the particle;(9)
End for(10)
End while(11)
Return the position of the best particle;Figure7 shows the minimum observed fitness value as the genetic algorithm solver progresses. The optimized controller parameter by the genetic algorithm is given as(11)Kp=−0.7053e04,Ki=−0.0555e04,Kd=0.2595e04,N=−0.0664e04.Figure 6
Fitness value of the genetic algorithm optimization.The step response performance of these two optimization algorithms is compared in Table1. According to Table 1, both optimization techniques performed similarly and satisfactorily. In some aspects, the GA PID controller performed better than the PSO PID controller, which converged faster with less computation. As a result, when it comes to fast computation, the PSO PID controller outperforms the GA PID controller.Table 1
Step response performance of the GA and the PSO PID controller.
Step response characteristicsPlant with GA PID controllerPlant with PSO PID controllerRise time1.5265e−051.5260e−05Transient time8.2185e−058.2388e−05Settling time8.2185e−058.2388e−05Settling min480.4168480.4168Settling max648.2221648.2221Overshoot22.012322.0997Undershoot00Peak648.2221648.2221Peak time3.0107e−053.0107e−05ITAE4.448e−072.9662e −07As shown in Figure5, the “Phase Shift PWM” block uses the PSPWM technique in the output signal of the PID controller. It sends the pulse signal that switching devices require in order to stabilize and regulate the output voltage signal. Figure 8 shows the block diagram of the PWM subsystem. The PID output signal is compared with the other two sawtooth PWM carrier signals with a 180-degree phase shift between them to generate the phase-shifted PWM control signal waveform for the switches. The final gate signals for the switches are generated by the SR flip-flop block. The internal block diagram of the SR flip-flop is shown in Figure 9. It was built with a pair of cross-coupled NOR logic gates.Figure 7
Fitness value of the PSO algorithm.Figure 8
Phase shift PWM block diagram.Figure 9
SR flip-flop block diagram.In the G2V (battery charging) mode of the proposed converter, the input voltage range is 400–460 V, while the output voltage range is 530–610 V. Correspondingly, in the V2G (battery discharging) mode, the input voltage range is 530–610 V, while the output voltage range is 400–460 V. The nominal operating frequency in the charging and discharging modes is 1 MHz. The resonant frequency is set at 1 MHz. To step up the input voltage, the transformer turns ratio,n is set to 400/530≅0.8 according to equation (1). Load resistance can be calculated from the equation Vo2/P equation, where Vo and P is the expected output voltage and power, respectively. From equations (3)–(6), the resonant parameters L1, L2, Lm, C1, and C2 can be determined, producing the following results:(12)L1=3.49μH,L2=4.62μH,Lm=21.5μH,C1=3.91nF.


## 3.1. Transformer’s Turns Ratio Design

Resonant BDCs are most efficient at the self-resonant frequency,fr. As a result, the converter ought to operate at this frequency under typical operating circumstances. The transformer’s turns ratio can then be determined as(1)n=N1N2=Vin_nomVo_nom,where N1,N2,Vin_nom,andVo_nom represent the transformer’s primary and secondary turns ratios, and nominal input and output voltages, respectively.


## 3.2. Resonant Components Design

Figure3 displays the CLLL converter’s equivalent circuit model in both directions. The components of the resonant tanks are L1, L2, Lm, and C1. When the converter is operating at its self-resonant frequency, the total impedance is pure resistance. As a result, at self-resonant frequency, the converter’s reactive impedance should be zero. The following equation can be derived from Figure 3:(2)−j1ωrC1+jωrL1+jωrLmn2L2Lm+n2L2=0.Figure 3
Schematic of the proposed converter’s equivalent circuit model in (a) forward power flow mode and (b) reverse power flow mode.
(a)(b)By simplifying equation (2), the self-resonant frequency can be obtained, as shown in the following equation:(3)fr=12πC1L1+Lmn2L2/Lm+n2L2.LetRe,L2′ be the corresponding equivalent Ro,L2 of the CLLL converters and here, Ro stands for the converter’s output load resistance. It is possible to calculate the equivalent load resistance by using the fundamental harmonic approximation (FHA) technique. For the G2V (battery charging) mode, L2′ and Re,c of the converter can be calculated as follows [15]:(4)L2′=n2L2,Re,c=8n2π2Ro.The parameters for the V2G (battery discharging) mode will be the same, and they are as follows [15]:(5)L2′=L2n2,Re,d=8n2π2Ro.By keeping the current flowing through primary-side switches negative at the time of turn-on, ZVS in these switches can be ensured. The primary current of the converter ought to be able to completely charge and discharge the output capacitors of the primary switches during the dead timetdead. The magnetizing inductance Lm and the length of the dead time determine the amount of this current. Therefore, the primary side switches’ ZVS is controlled by the magnetizing inductance Lm, output capacitance of switching devices Coss, operating frequency, and dead time tdead. This converter performs in dead time such as an LLC resonant DC-DC converter [23]. This allows the magnetizing inductance to be expressed in a manner that is similar to that of the full-bridge LLC resonant DC-DC converter. Thus, the expression [15] is(6)Lm≤tdead16Cossfs,max,where fs,max denotes the highest switching frequency of the proposed converter.Under various load conditions, a relatively low magnetizing inductanceLm guarantees ZVS in primary-side switching devices. On the other hand, Lm can never be set too low. Too little Lm would cause the magnetizing current to be extremely high, which would result in significant conduction losses, higher primary-side capacitor peak voltage requirements, and higher apparent power requirements for switching devices. A low magnetizing current is produced by a high magnetizing inductance, but the converter’s voltage gain is constrained. Consequently, the magnetizing inductance Lm should not be too high.The dead timetdead between switching devices has an impact on the ZVS range as well. ZVS will be easier to achieve for a broad range of input and output voltages with long dead time tdead. Additionally, by uplifting the inductance with a lengthy dead time tdead, the magnetizing current could be decreased. On the other hand, a relatively high dead time tdead will cause a high primary RMS current because there will be no transfer of energy during the dead-time duration. All of these issues must be kept in mind when designing the magnetizing inductance, Lm of the proposed converter.Figure4 depicts the fluctuation of the converter voltage gain over a range of normalized frequencies (fr/fs ratio) with varied loading circumstances, i.e., different quality factors, Q=L1/C1/Re. As a result, the output voltage can be regulated by modifying the converter’s switching frequency fs. Within a suitable switching frequency range, the converter can function in the inductive area (as illustrated in Figure 4), where the switch voltage leads the tank current waveform, ensuring that the voltage returns to zero before the current rises and so ensuring ZVS.Figure 4
Gain waveforms of CLLL converter for different loading conditions.


## 3.3. PSPWM-BasedDiscrete-Time PID Controller Design

The proposed discrete-time PID controller’s block schematic, which is based on PSPWM, is provided in the following Figure5.The three main components of the controller are the “ZOH” (zero order hold) block, the “discrete-time PID controller transfer function” block, and the “phase shift PWM ” block. The difference signal between the reference and actual output voltage levels is sampled by the “ZOH” block and stored there. The output voltage is then stabilized and regulated by the “discrete-time PID controller transfer function” block using proportional, integral, and derivative control. The following equation can be used to represent the transfer function of the discrete-time PID controller in theZ domain [15]:(7)Cz=Kp+KiTszz−1+KdNz−11+NTsz−1,where Kp,Ki,andKd denote the proportional, integral, and derivative gains of the proposed PID controller, respectively, Ts denotes the sampling period, and N denotes the parameter of the first-order filter on the derivative term.Once more, equation (7) can be changed to yield the following [15] expression:(8)Cz=b0+b1z−1+b2z−2a0+a1z−1+a2z−2,which has the following coefficients:(9)b0=Kp1+NTs+KiTs1+NTs+KdN,b1=−Kp2+NTs+KiTs+2KdN,b2=Kp+KdN,a0=1+NTs,a1=−2+NTs,a2=1.However, the PID controller gains in [15] are determined by trial and error, which is not an optimized process. As a result, the converter is incapable of effectively stabilizing and regulating the output voltage. Because of this, efforts have been made in this work to optimize the PID controller gains. Two optimization techniques, genetic algorithm (GA) [24, 25] and particle swarm optimization (PSO) [26–28], were used to optimize the PID controller gains. Their step responses were also compared for the stability analysis. Because PLECS excels at the power electronics system level simulation and MATLAB is required for controller optimization, MATLAB and PLECS co-simulation were used in this work. In the GA, the search for the optimal solution space mimics the way natural selection drives biological evolution. It repeatedly adjusts a population of individual solutions and, at each step, picks people from the current population to be parents and utilizes them to generate offspring for the upcoming generation. The population progresses toward an optimal solution over subsequent generations by achieving the best fitness value. ITAE (integral of time weighted absolute error) is employed as the fitness function in this case. The pseudocode for the GA algorithm (see Algorithm1) is as follows:Algorithm 1: Pseudocode of the genetic algorithm [24].
(1)
Initialize random population;(2)
Evaluate the population;(3)
Generation = 0;(4)
While the termination criterion is not satisfied do(5)
Generation = generation + 1;(6)
Select elite individuals with lower fitness scores;(7)
Perform crossover with probability crossover;(8)
Perform mutation with probability mutation;(9)
Evaluate the population;(10)
End while(11)
Return the best individual during the evolution;Figure6 shows the minimum observed fitness value as the genetic algorithm solver progresses. The optimized controller parameter by the genetic algorithm is given as(10)Kp=11.0956,Ki=−12.7484,Kd=−3.8236,N=3.0057.Figure 5
Block schematic for the proposed PID controller [15].PSO, like GA, is a population-based algorithm. The main advantage of the PSO is that it can find the best solution with the least amount of computation. This PSO algorithm is inspired by the swarming flocks of birds or insects. Based on an objective function, each particle is drawn to some extent to the best place it has located this far, as well as the best location found by any member of the swarm. After a few iterations, the population may congregate around a single site, a few spots, or continue to migrate.The pseudocode for the PSO algorithm (see Algorithm2) is as follows:Algorithm 2: Pseudocode of the PSO algorithm [26].
(1)
Initialize the size of the particle swarm and other parameters;(2)
Randomly initialize the position and velocity of particles;(3)
While the termination criterion is not satisfied do(4)
Fori = 1 to the number of particles do(5)
Calculate the fitness function;(6)
Update the personal and global best of each particle;(7)
Update the velocity of the particle;(8)
Update the position of the particle;(9)
End for(10)
End while(11)
Return the position of the best particle;Figure7 shows the minimum observed fitness value as the genetic algorithm solver progresses. The optimized controller parameter by the genetic algorithm is given as(11)Kp=−0.7053e04,Ki=−0.0555e04,Kd=0.2595e04,N=−0.0664e04.Figure 6
Fitness value of the genetic algorithm optimization.The step response performance of these two optimization algorithms is compared in Table1. According to Table 1, both optimization techniques performed similarly and satisfactorily. In some aspects, the GA PID controller performed better than the PSO PID controller, which converged faster with less computation. As a result, when it comes to fast computation, the PSO PID controller outperforms the GA PID controller.Table 1
Step response performance of the GA and the PSO PID controller.
Step response characteristicsPlant with GA PID controllerPlant with PSO PID controllerRise time1.5265e−051.5260e−05Transient time8.2185e−058.2388e−05Settling time8.2185e−058.2388e−05Settling min480.4168480.4168Settling max648.2221648.2221Overshoot22.012322.0997Undershoot00Peak648.2221648.2221Peak time3.0107e−053.0107e−05ITAE4.448e−072.9662e −07As shown in Figure5, the “Phase Shift PWM” block uses the PSPWM technique in the output signal of the PID controller. It sends the pulse signal that switching devices require in order to stabilize and regulate the output voltage signal. Figure 8 shows the block diagram of the PWM subsystem. The PID output signal is compared with the other two sawtooth PWM carrier signals with a 180-degree phase shift between them to generate the phase-shifted PWM control signal waveform for the switches. The final gate signals for the switches are generated by the SR flip-flop block. The internal block diagram of the SR flip-flop is shown in Figure 9. It was built with a pair of cross-coupled NOR logic gates.Figure 7
Fitness value of the PSO algorithm.Figure 8
Phase shift PWM block diagram.Figure 9
SR flip-flop block diagram.In the G2V (battery charging) mode of the proposed converter, the input voltage range is 400–460 V, while the output voltage range is 530–610 V. Correspondingly, in the V2G (battery discharging) mode, the input voltage range is 530–610 V, while the output voltage range is 400–460 V. The nominal operating frequency in the charging and discharging modes is 1 MHz. The resonant frequency is set at 1 MHz. To step up the input voltage, the transformer turns ratio,n is set to 400/530≅0.8 according to equation (1). Load resistance can be calculated from the equation Vo2/P equation, where Vo and P is the expected output voltage and power, respectively. From equations (3)–(6), the resonant parameters L1, L2, Lm, C1, and C2 can be determined, producing the following results:(12)L1=3.49μH,L2=4.62μH,Lm=21.5μH,C1=3.91nF.


## 4. Results and Discussions

To validate the proposed system, simulations using the PLECS Standalone software and MATLAB/Simulink were performed. Figure10 depicts the peak efficiency curves of the proposed CLLL converter using GaN E-HEMT devices under varying load conditions for both G2V and V2G modes. The proposed CLLL converter has a higher efficiency in the charging or G2V mode than in the discharging or V2G mode. In both charging and discharging modes, the proposed converter has good efficiency over a wide load range.Figure 10
Efficiency curves of CLLL converter utilizing GaN devices under varying load conditions.Figure11 depicts the peak efficiency, output voltage, and output current vs. switching frequency for the proposed converter in both G2V and V2G modes. The peak efficiency was achieved at 1 MHz switching frequency since it is the resonant frequency and accomplishes ZVS turn-on at this frequency. That is why it has the highest efficiency at this frequency. The peak efficiency of the converter began to drop below or above this switching frequency. Because of the same reason, the output voltage and output current are at their peak at 1 MHz frequency and then begin to decline below or above that level.Figure 11
Peak efficiency, output voltage, and output current versus operating switching frequency for the converter operating in the G2V and V2G mode.While utilizing automotive standard switching devices built with GaN, SiC, and Si, the performance of the proposed converter was also assessed. PLECS device models, including turn-on loss, turn-off loss, conduction loss, and thermal impedance data, were obtained from various manufacturers’ datasheets for practical loss and efficiency calculations. The subsections that follow describe the performance of these devices using this converter.


### 4.1. E-Mode GaN HEMT-Based CLLL Converter from GaN Systems Inc [29]

In this work, a GaN switching device made by GaN Systems Inc., the GS-065-150-1-D2 [29], has been used. The GS-065-150-1-D2 is a 650 V, 150 A, and 10 mΩ on-resistanceenhancement-mode GaN-on-silicon power transistor. It offers zero reverse recovery loss and an extremely high switching frequency (>10 MHz) [29]. In charging mode, the converter’s simulated waveforms are shown in Figure 12. It is clear that the switches turn on ZVS. The ripple in the output voltage is almost zero. The circuit yields comparable outcomes in discharging mode.Figure 12
E-mode GaN HEMT enabled converter simulated waveforms.


### 4.2. E-Mode Planar SiC MOSFET-Based CLLL Converter from Cree Inc [30]

For this work, the SiC switching device was an n-channel enhancement planar MOSFET with the model number C3M0060065D manufactured by Cree Inc [30]. This 650 V and 29 A SiC MOSFET has a fast intrinsic diode with a small reverse recovery (Qrr), fast switching with small capacitances, and high blocking voltage with low on-resistance (60 mΩ) [30]. Figure 13 displays the simulated waveforms for this SiC device’s charging mode.Figure 13
Simulated waveforms of the proposed converter with planar SiC device.The waveforms show the ZVS of the switching device. In comparison to the prior GaN device, the output voltage and output current both are marginally lower. Like the GaN switching device, the output voltage ripple is almost zero. The proposed converter’s discharging mode results in waveshapes similar to those of the GaN.


### 4.3. Trench Structure SiC MOSFET-Based CLLL Converter from ROHM Semiconductor [31]

A trench gate SiC MOSFET with a 650 V, 39 A, and 60 mΩ operating voltage that is designed for high-efficiency server power supplies, renewable energy systems, and EV chargers is the SCT3060AR from ROHM Semiconductors [31]. The first company to mass-producetrench-type MOSFETs, with increased efficiency while consuming less power than traditional SiC MOSFETs, was ROHM, a SiC technology pioneer and market leader. The performance of the converter with this device in charging mode is shown in Figure 14. It is obvious from the waveforms that this device also displays a ZVS turn-on. In comparison to the previous planar SiC device, the output voltage and current are higher. The trench SiC device performs better than the previous planar SiC device as a result. Additionally, this device’s output voltage and current closely resemble those of the previous GaN device. Similar outcomes are produced by the converter in discharging mode.Figure 14
Simulated waveforms of the converter with trench SiC device.


### 4.4. Si Power Transistor-Based CLLL Converter from Infineon Technologies [32]

The SPP20N60C3 [32] Si power transistor from Infineon Technologies has a voltage rating of 650 V, a current rating of 20.7 A, and an on-resistance of 190 mΩ. This device has better transconductance, a higher peak current capability, and a very low gate charge than other Si power transistors [32]. When using this device in charging mode, the performance of the designed converter is shown in Figure 15. The output voltage has almost no ripple. The switching device offers a ZVS turn-on in this instance as well. The converter’s performance is similar in discharging mode.Figure 15
Simulated waveforms for the Si power transistor-based converter.


### 4.5. Field Stop Trench Si IGBT-Based CLLL Converter from ROHM Semiconductor [33]

The RGW60TS65DHR [33] from ROHM Semiconductor is a 650 V 30 A Si field stop trench IGBT. This device has a fast recovery diode (FRD) built in for reverse conduction, low collector-emitter saturation voltage, and a low switching loss [33]. The converter’s operation with the device in charging mode is shown in Figure 16. The output voltage is also free from a ripple in this instance. It guarantees that ZVS is activated as well. Also, the converter functions similarly when discharging.Figure 16
Simulated waveforms of the proposed converter with trench IGBT devices.


## 4.1. E-Mode GaN HEMT-Based CLLL Converter from GaN Systems Inc [29]

In this work, a GaN switching device made by GaN Systems Inc., the GS-065-150-1-D2 [29], has been used. The GS-065-150-1-D2 is a 650 V, 150 A, and 10 mΩ on-resistanceenhancement-mode GaN-on-silicon power transistor. It offers zero reverse recovery loss and an extremely high switching frequency (>10 MHz) [29]. In charging mode, the converter’s simulated waveforms are shown in Figure 12. It is clear that the switches turn on ZVS. The ripple in the output voltage is almost zero. The circuit yields comparable outcomes in discharging mode.Figure 12
E-mode GaN HEMT enabled converter simulated waveforms.


## 4.2. E-Mode Planar SiC MOSFET-Based CLLL Converter from Cree Inc [30]

For this work, the SiC switching device was an n-channel enhancement planar MOSFET with the model number C3M0060065D manufactured by Cree Inc [30]. This 650 V and 29 A SiC MOSFET has a fast intrinsic diode with a small reverse recovery (Qrr), fast switching with small capacitances, and high blocking voltage with low on-resistance (60 mΩ) [30]. Figure 13 displays the simulated waveforms for this SiC device’s charging mode.Figure 13
Simulated waveforms of the proposed converter with planar SiC device.The waveforms show the ZVS of the switching device. In comparison to the prior GaN device, the output voltage and output current both are marginally lower. Like the GaN switching device, the output voltage ripple is almost zero. The proposed converter’s discharging mode results in waveshapes similar to those of the GaN.


## 4.3. Trench Structure SiC MOSFET-Based CLLL Converter from ROHM Semiconductor [31]

A trench gate SiC MOSFET with a 650 V, 39 A, and 60 mΩ operating voltage that is designed for high-efficiency server power supplies, renewable energy systems, and EV chargers is the SCT3060AR from ROHM Semiconductors [31]. The first company to mass-producetrench-type MOSFETs, with increased efficiency while consuming less power than traditional SiC MOSFETs, was ROHM, a SiC technology pioneer and market leader. The performance of the converter with this device in charging mode is shown in Figure 14. It is obvious from the waveforms that this device also displays a ZVS turn-on. In comparison to the previous planar SiC device, the output voltage and current are higher. The trench SiC device performs better than the previous planar SiC device as a result. Additionally, this device’s output voltage and current closely resemble those of the previous GaN device. Similar outcomes are produced by the converter in discharging mode.Figure 14
Simulated waveforms of the converter with trench SiC device.


## 4.4. Si Power Transistor-Based CLLL Converter from Infineon Technologies [32]

The SPP20N60C3 [32] Si power transistor from Infineon Technologies has a voltage rating of 650 V, a current rating of 20.7 A, and an on-resistance of 190 mΩ. This device has better transconductance, a higher peak current capability, and a very low gate charge than other Si power transistors [32]. When using this device in charging mode, the performance of the designed converter is shown in Figure 15. The output voltage has almost no ripple. The switching device offers a ZVS turn-on in this instance as well. The converter’s performance is similar in discharging mode.Figure 15
Simulated waveforms for the Si power transistor-based converter.


## 4.5. Field Stop Trench Si IGBT-Based CLLL Converter from ROHM Semiconductor [33]

The RGW60TS65DHR [33] from ROHM Semiconductor is a 650 V 30 A Si field stop trench IGBT. This device has a fast recovery diode (FRD) built in for reverse conduction, low collector-emitter saturation voltage, and a low switching loss [33]. The converter’s operation with the device in charging mode is shown in Figure 16. The output voltage is also free from a ripple in this instance. It guarantees that ZVS is activated as well. Also, the converter functions similarly when discharging.Figure 16
Simulated waveforms of the proposed converter with trench IGBT devices.


## 5. Comparative Analyses

The loss comparison of the proposed converter in terms of total conduction loss and total switching loss across the primary and secondary switches using the GaN, SiC, and Si-based switching devices is shown in Table2. According to Table 2, the GaN System’s E-mode GaN HEMT switch outperformed the other Si and SiC-based switching devices in terms of total switching loss across the primary and secondary switches.Table 2
Loss comparison of the proposed converter.
Utilized switching deviceTotal conduction loss (W)Total switching loss (W)E-mode GaN HEMT by GaN Systems Inc [29]167.798.85E-mode planar SiC MOSFET by Cree Inc [30]182.8261.88Trench structure SiC MOSFET by ROHM Semiconductor [31]124.98121.55Si power MOSFET by Infineon Technologies [32]158.4058.70Field stop trench Si IGBT by ROHM Semiconductor [33]73.40305.64Si IGBT performed better than the other GaN, Si, and SiC-based switching devices in terms of total conduction loss, but it performed the worst in terms of total switching loss,which is equal to 305.64 W. So, when we consider the two losses of the switches, we can clearly see that the GaN System’s E-mode GaN HEMT is the best switching device because its total conduction and switching loss sums to 176.64 W (167.79 W + 8.85 W = 176.64 W), which is significantly lower than the other switching devices. As a result, among the SiC and Si-based semiconductor switching devices, E-mode GaN HEMT made by GaN Systems Inc. is the best choice as a switching device for the proposed CLLL converter.The overall effectiveness of the proposed CLLL converter using various switching devices is summarized in Figure17. The designed CLLL converter, which uses a GaN E-mode HEMT as a switching device, has the highest G2V efficiency (97.4%), as shown in Figure 17(a). GaN devices perform better than SiC and Si MOSFET-based designs, but Si IGBT-based designs perform the worst. According to Figure 17(b), the situation in battery charging mode (G2V) is comparable to that in battery discharging (V2G) mode. When different switching devices are used, the designed converter’s output current is shown in Figure 17(c). The lowest and highest output currents were attained by Cree Inc.’s SiC and ROHM Semiconductor’s IGBT, respectively. To sum up, an optimized converter solution can be provided by GaN-based switches made by GaN Systems Inc.Figure 17
Comparative analysis of the proposed converter in terms of (a) highest G2V (charging) mode efficiency, (b) highest V2G (discharging) mode efficiency, and (c) output load current.
(a)(b)(c)Moreover, as shown in Table3, in terms of the highest G2V (battery charging mode) efficiency (%), highest V2G (battery discharging mode) efficiency (%), and peak output power (kW), this converter outperforms the GaN-based CLLLC resonant DC-DC converter proposed in [15], the GaN-based CLLC resonant DC-DC converter proposed in [34], the GaN-basedmulti-CLLC resonant DC-DC converter proposed in [35], and the GaN-based asymmetric CLLC resonant DC-DC converter suggested in [36]. The highest G2V efficiency (97.4%) and highest V2G efficiency (96.67%) of the suggested converter are both mostly higher than those of the findings presented in [15, 34–36]. The proposed converter surpasses [34–36] by achieving a peak output power of 5 kW. The designed converter ensures a high switching frequency (1 MHz), which is higher than that of [34, 36] and leads to high efficiency and high compactness. To minimize the converter’s size and cost, a lower number of resonant elements were chosen for the converter design. In comparison to the proposed converter, [15, 34, 35] utilized a higher number of resonant elements. Additionally, in the resonant elements of the proposed converter, without the capacitance, the two resonant inductances can be integrated with the HF transformer’s leakage inductances. Therefore, the proposed converter can result in a more compact design than the converter presented in [15, 34–36]. The GaN-based switching devices were used in all of the converter structures. Only the structure of the resonant converter differs. Furthermore, an optimized PID controller based on PSO and GA algorithms is proposed in the designed CLLL converter, which improves the converter’s ability to effectively stabilize and regulate output voltages in the presence of noise disturbances compared to the work presented in [15]. Therefore, it is possible to infer that the proposed isolated bidirectional CLLL resonant converter structure is superior to those discussed in [15, 34–36] in terms of performance.Table 3
Performance comparison with existing topologies.
Criteria[15][34][35][36]This workMaxVbus (V)465540400400610Switch technologyGaNGaNGaNGaNGaNSwitching frequency (MHz)10.39110.51Resonant elements55844Highest G2V efficiency (%)97.295.292.297.0297.4Highest V2G efficiency (%)9795.79295.9696.67Peak output power (kW)510.40.45


## 6. Conclusion

This article describes the detailed design process for an improved isolated bidirectional resonant converter that uses a CLLL resonant structure. In comparison to the conventional isolated bidirectional CLLLC resonant converter, this resonant converter provides better performance and a more compact design. The converter’s input and output voltage ranges are 400–460 V DC and 530–610 V DC, respectively, at a switching frequency of 1 MHz, and it has been developed and tested with a 5 kW rated power. This converter makes it possible to transfer power in both directions while also operating at high frequencies and high efficiency. The switching loss in this MHz scenario is significantly reduced by this CLLL converter architecture, which guarantees soft switching of both primary and secondary semiconductor switching devices. The PSO and GA-based algorithms are used to design the optimal PID controller that is suggested in this paper. The proposed converter is examined in-depth in this paper, along with a comparison of the high voltage, high current, and low on-resistance semiconductor switching devices that can be used with it. Because GaN switching devices have low switching loss and zero reverse recovery loss, the proposed CLLL converter employing GaN-based switching devices from GaN Systems Inc. has the highest converter efficiency of any switching device currently on the market. The least efficient designs are those based on Si, followed by SiC-based designs. This GaN-based CLLL converter has peak efficiencies of 97.40 percent for charging and 96.67 percent for discharging at full load. The proposed converter operates at a high frequency (1 MHz), which results in minimal passive resonant component sizes. As a result, this proposed converter can achieve a higher power density. Therefore, this isolated bidirectional asymmetric CLLL resonant DC-DC converter based on the GaN switching devices can be very effective for the EV onboard charger systems due to its high performance and compact design.



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*Source: 2609168-2023-03-02.xml*