# A Survey on True Random Number Generators Based on Chaos

Authors: Fei Yu; Lixiang Li; Qiang Tang; Shuo Cai; Yun Song; Quan Xu
Journal: Discrete Dynamics in Nature and Society
 (2019)

---

## Abstract

With the rapid development of communication technology and the popularization of network, information security has been highly valued by all walks of life. Random numbers are used in many cryptographic protocols, key management, identity authentication, image encryption, and so on. True random numbers (TRNs) have better randomness and unpredictability in encryption and key than pseudorandom numbers (PRNs). Chaos has good features of sensitive dependence on initial conditions, randomness, periodicity, and reproduction. These demands coincide with the rise of TRNs generating approaches in chaos field. This survey paper intends to provide a systematic review of true random number generators (TRNGs) based on chaos. Firstly, the two kinds of popular chaotic systems for generating TRNs based on chaos, including continuous time chaotic system and discrete time chaotic system are introduced. The main approaches and challenges are exposed to help researchers decide which are the ones that best suit their needs and goals. Then, existing methods are reviewed, highlighting their contributions and their significance in the field. We also devote a part of the paper to review TRNGs based on current-mode chaos for this problem. Finally, quantitative results are given for the described methods in which they were evaluated, following up with a discussion of the results. At last, we point out a set of promising future works and draw our own conclusions about the state of the art of TRNGs based on chaos.


---

## Body

## 1. Introduction

In recent years, with the rapid development of the Internet, the requirements for information security in various fields are getting higher and higher, and the security issues are getting more and more attention [1–5]. In the field of information security, encryption algorithm, and key generation are important factors of encryption system; they must be unpredictable [6–9]. In most cryptographic algorithms, random number is an indispensable element, and random number generator (RNG) has important applications in the field of information security, such as generating parameters of public key cryptosystems (such as ECC, RSA) or image encryption [10–12].According to the different random sequence generated, random numbers can be divided into two categories, namely pseudo-random numbers (PRNs) and true random numbers (TRNs), as shown in Figure1. PRNs [13, 14] refer to the extension of one seed into another long output sequence by a determined algorithm, which are generally repeatable, so they are widely used in the field of simulation and testing. Unlike PRNs, TRNs [15, 16] cannot be generated by pure mathematical random algorithms, but only by random physical processes. Compared with PRNs, TRNs not only have good statistical characteristics but also have good unpredictability. They could be used in systems with high security requirements.Figure 1
The architecture of random numbers generator.The typical TRNG structure can be divided into five modules: (1) analog random signal is obtained from the entropy source; (2) sampling and quantifying the random signal; (3) analog-to-digital conversion of the analog signal to output the random number sequence; (4) the sequence obtained at this time does not necessarily satisfy the uniform distribution, and it needs to be processed; and (5) through random number test suite, as shown in Figure2.Figure 2
The typical TRNG structure.In true random number generators (TRNGs), there are three main types of entropy sources: thermal noise on resistors and capacitors [17, 18], phase jitter of oscillating signals [19–21], chaos [22–24] and others, as shown in Figure 1. For the TRNGs based on thermal noise, the resistance noise is amplified to a suitable range by an ideal amplifier, and then processed by a comparator to compare the amplified noise voltage with the reference level to obtain a digital random signal [17]. In practice, due to the influence of some nonideal factors, such as the limited bandwidth of the amplifier, misalignment, periodic noise of the power supply coupled to the system, the randomness of the random number sequence generated by the system will be affected [18]. For the oscillator-based TRNGs, the random source is the phase jitter noise in the ring oscillator in Complementary Metal Oxide Semiconductor (CMOS) circuit [20]. The quality of the random sequence generated by the true random number generator is largely determined by the root mean square (RMS) value of the phase jitter of the low frequency oscillator [21]. But the disadvantage is that it is not suitable for full custom integrated circuit (IC), and the randomness of circuit implementation is low. Compared with the former two methods, the characteristics of chaos, such as nonperiodicity, wide spectrum, unpredictability, and sensitivity to initial conditions [25–28], are in good agreement with the properties of random numbers. Therefore, chaotic theory opens up broad prospects for the design and implementation of TRNGs.The main contributions of our work are as follows: (1) we provide a broad survey of generating methods that might be useful for TRNGs with chaos; (2) an in-depth and organized review of the most significant methods that use chaos for TRNGs, their origins, and their contributions; (3) we have conducted a comprehensive performance evaluation, which collects quantitative indicators. For example, power, output bit rate, energy and technology, etc.; and (4) a discussion about the above results, and a list of possible future works that may determine the course of upcoming advances, as well as a conclusion summarizing the state of the art of the field.The remainder of this paper is organized as follows. Firstly, Section2 describes existing TRNG methods based on chaos, challenges, and benchmarks. It reviews existing methods following two kinds of popular chaotic systems based on their contributions. The TRNGs based on current-mode chaos is described. Other background concepts such as common chaotic model definitions are also reviewed. This section focuses on describing the design techniques and highlights of those methods rather than performing a quantitative evaluation. Then, Section 3 presents a brief discussion on the presented methods based on their quantitative results on the aforementioned TRNGs. In addition, future research directions are also laid out. At last, Section 4 summarizes the paper and draws conclusions about this work and the state of the art of the field.


## 2. Overview of TRNGs Based on Chaos

Up to date, there are a lot of TRNG structures based on chaos. In this section, we supply a brief introduction about the two most popular and fundamental structures in of TRNG structures based on chaos. Both of them are presented according to a well thought taxonomy of the research completed in the area. We also devote a part of this section to review TRNG based on current-mode chaos for this problem.


### 2.1. TRNGs Based on Continuous Time Chaotic System

Continuous time chaotic system is a chaotic system based on observation time series, and its state is time-dependent. The mathematical model of continuous time chaotic dynamic system is as follows:(1)
x
˙
=
f
x
,
t
,wherex
∈
R
n is the state variable and f
:
R
n
×
R
n
→
R
n. Common continuous time chaotic systems like Lorenz system [29], Chua’s circuit system [30], Jerk system [31], chaotic oscillator [32–34], and many hyperchaotic systems have been proposed [35–37]. Throughout the years, continuous time chaotic systems have been mostly focused on neural network, synchronization, secure communication [38–42], and other fields, especially the design of TRNGs. For that reason, continuous time chaotic circuits are the most abundant ones. In this section, we describe the most popular continuous time chaotic circuits for TRNGs design, considering continuous time chaotic systems that contain any kind of continuous time chaotic circuits representation such as Chua’s circuit, Jerk circuit, various chaotic oscillators, and FPGA.


#### 2.1.1. Chua’s System

Chua’s system is a classical nonlinear electronic circuit, which can show the standard double scroll chaotic dynamic behavior. It was published by Professor Shaotang Cai in 1983. Blaszczyk and Guinee [43] proposed a TRNG which was employed by Chua’s circuit and used a simple temperature dependent control resistor in the oscillator circuit and optimal voltage threshold settings. The randomness attributes of the generator were confirmed via PSpice simulation, by the NIST tests for statistical validation. Moqadasi and Ghaznavi-Ghoushchi [44] proposed a TRNG which based on a new Chua’s circuit that its negative resistor was a monolithic CMOS based circuit with 12 transistors. This proposed system also consisted of a sample and hold block, an analog to digital converter (ADC) block and a linear feedback shift register (LFSR) block which scrambles generated bit stream and increases randomness, as shown in Figure 3. When the number of LFSR bits changed from 6 to 32, the experiments confirmed that the 6 bits length was optimum for LFSR which was better than previous works.Figure 3
True random number generation from the Chua’s circuit core proposed by Moqadasi and Ghaznavi-Ghoushchi.


#### 2.1.2. Jerk System

American scholar Sprott [45] proposed the Jerk system x
⃛
=
F
x
¨
,
x
˙
,
x, where x
˙
=
d
x
/
d
t is the first derivative of position, x
¨
=
d
2
x
/
d
t
2 call acceleration, x
⃛
=
d
3
x
/
d
t
3 call Jerk. Its generalized dimensionless equation of state is:(2)
d
x
/
d
t
=
y
,
d
y
/
d
t
=
z
,
d
y
/
d
t
=
z
,wherex
,
y
,
z are the state variable, α
,
β are the system parameters, f
x is a nonlinear term. In (2), the transformation system of x
,
y
,
z
→
−
x
,
−
y
,
−
z can remain unchanged. The system is symmetrical about the origin. Jerk system is characterized by concise equation form and easy circuit realization.In 2018, Wannaboon et al. [46] presented a fully customized design of TRNG which implemented on a 0.18 µm CMOS technology with unique composition of three major components, chaotic jerk oscillator, Δ
∑ modulator, and simple pre/post-processing. The block diagram of the proposed TRNG is shown in Figure 4. The chaotic Jerk circuit provided chaotic signals with strong robustness and randomness, and exhibited the unique characteristics of smoothly balanced-to-unbalanced alternation of double scroll attractors. In order to improve the resolution of random bit sequence, the continuous time second-order Δ
∑ modulator was introduced as the mixed signal interface without additional clock. The simple structure of shift-registers was implemented as a post-processing process. The bit sequence of the proposed TRNG successfully passed all statistical tests of NIST SP800-22 test suite, and the final output bit rate was 50 Mbps. However, the slight uncertainty of the initial conditions, which is unavoidable in IC implementation, leads to a very large uncertainty after very short time. Because of this, the system behavior can only be predicted for a short time period.Figure 4
Block diagram of the TRBG with sigma-delta modulation of chaotic jerk signals proposed by Wannaboon et al.


#### 2.1.3. Boolean Chaotic Oscillator

Boolean chaos [47] is a phenomenon in an autonomous network which shows nonrepeating chaotic oscillations, exponential sensitivity to initial conditions, and has a broadband power spectrum. Boolean chaotic oscillator includes Boolean-like state transitions with a fast transition time, and a feedback loop with incommensurate delay inputs. The dynamics of nodes network is described by:(3)
x
n
t
=
f
n
t
,
x
1
t
−
τ
n
1
,
…
,
x
n
t
−
τ
n
n
,whereτ
n
m is the delay time from the nth node to the mth node, x
n
t is the Boolean logic state at the nth node at time t, and f
n is the logic function for the nth node. Park et al. [48] reported on a TRNG whose randomness derived from a Boolean chaotic oscillator, as shown in Figure 5. Using a CMOS 0.35 µm process, the paper built a CMOS Boolean chaotic oscillator, which consisted of a core chaotic oscillator and a source follower buffer. The generated random bit sequences passed the widely accepted statistical tests used for evaluating cryptographic random number generators.Figure 5
Schematic diagram of random number generation using CMOS Boolean chaotic oscillator.


#### 2.1.4. Jitter Booster Circuit

The nonperiodicity of a chaotic signal implies that the signal has irregular temporal zero crossings as in the case of highly jittered oscillations. The idea of using chaos for enhancing jitter can be an alternative to the multiring oscillator sampling approach. Çiçek and Dündar [49] presented a chaos based integrated jitter booster circuit for multiple oscillator sampling TRNG architecture. The proposed circuit provided an alternative method for enhancing jitter using the chaotic dynamics produced by nonlinear coupling of two ring oscillators, which required fewer components.


#### 2.1.5. Coupled Chaotic Oscillator

Coupled chaotic oscillators are very suitable for monolithic implementation and capable of operating at very high frequencies when appropriate design considerations and experience are exercised. In [50], two integrated continuous-time chaotic oscillators based on cross-coupled −
g
m oscillators were presented and their application to random bit generation was described. In [51], a TRNG design was proposed which employed a dual coupled oscillator architecture. This structure improved the output throughput and solved the external interference problems. The frequency of a slower clock modulated the chaotic oscillator output signal, and with the rising edge of the chaotic modulation clock, a faster clock was sampled. The proposed design fulfilled the tests used in both the FIPS-140-2 and the NIST-800-22 random number test suites.


#### 2.1.6. FPGA-Based

Considering technologies mentioned above, the highest performance could be obtained from IC-based chaotic generators. However, IC-based implementations do not promise a flexible use. In addition, the cost of prototyping and testing such systems will be high. FPGA chips are able to run concurrently and have relatively flexible architecture. The cost of design and test cycles of FPGA chips is particularly low [52]. Because of its high-speed and high-quality random generation, FPGA has become a popular platform for implementing random generators or complete cryptographic schemes. Koyuncu and Ozcerit [53] modeled Sundarapandian-Pehlivan chaotic system and simulated in three distinct platforms to show the advantages of FPGA-based chaotic oscillator with respect to alternative solutions. The chaotic system was modeled by the Runge-Kutta (RK4) in hardware description language (VHDL) and the model was synthesized and tested on Xilinx Virtex-6 FPGA chip, the block diagram of an FPGA based TRNG designed is illustrated in Figure 6. The designed chaotic oscillator was tested by TRNG and the maximum operating frequency was 293 MHz with a speed of 58.76 Mbit/s. Akgul et al. [54] used the 3D chaotic system without equilibrium points as the source of entropy built the chaotic system model with FPGA, then designed and implemented the chaotic oscillator with VHDL and RK-4 algorithm, and finally chose the most complex bits of binary numbers to generate random numbers.Figure 6
Block diagram of FPGA-based chaotic TRNG.


### 2.2. TRNGs Based on Discrete Time Chaotic System

Discrete time chaotic systems also exist widely in the field of nonlinear science, such as physics, biology, and chemistry [55], especially in the generation of TRNs. One-dimensional discrete time nonlinear dynamical systems are defined as follows:(4)
x
k
+
1
=
τ
x
k
,wherex
k
,
k
=
0
,
1
,
2
,
⋯, are state. And τ is a mapping that mapping the current state x
k to the next state x
k
+
1. If we start with an initial x
0 value and apply τ repeatedly, we get a sequence x
k
,
k
=
0
,
1
,
2
,
⋯. This sequence is called a trajectory of the discrete time dynamic system. Classical discrete time chaotic systems include logistic mapping, tent mapping, Bernoulli mapping, and so on. FPGAs can be used to implement discrete time systems as well, but as far as the author knows, there are few literatures about the realization of TRNGs based on discrete time chaotic systems by using FPGA, so there is no detailed introduction here.


#### 2.2.1. Logistic Mapping

A very simple but widely studied dynamical system is logistic mapping, which originates from the insect population model. Its definition has many forms: (1)x
k
+
1
=
μ
x
k
1
−
x
k, when 3.5699456
⋯
≤
μ
≤
4, logistic mapping works in chaotic state; (2) x
k
+
1
=
1
−
γ
x
k
2, when γ
∈
1.5437
,
2, logistic mapping works in chaotic state; (3) x
k
+
1
=
μ
x
k
−
x
k
2, when μ
∈
3.5699
,
4, logistic mapping works in chaotic state. It can be seen that logistic mapping is actually a first-order equation, which requires initialization conditions and control parameters. Therefore, it is easy to implement in hardware, and people often use this mapping to design TRNGs.In 2015, Avaroğlu et al. [56] used logistic map in post-processing to ensure that numbers generated by RO-based TRNG were of high quality. In order to observe the influences of the logistic map, four different scenarios considering RO-based TRNG structure were studied. [57] proposed a TRNGs with graphics processing units as the source of entropy, unpredictable behavior of which was managed by computing logistic maps, and high throughput achieved 447.83 Mbit/s. Tuncer [58] applied the random challenges from the logistic map to physical unclonable functions based on ring oscillator (RO-PUF) to generate random numbers in real time in FPGA, which prevented the PUF from being attacked (cracked) and improved the randomness of the random numbers. Because the value distribution of logistic mapping points is too centralized and blank bands appear in other regions, the uniform distribution characteristics of the mapping points are poor, so that logistic mapping needs post-processing (Von Neumann corrector [59], XOR correctors [60], one-way hash function [61], etc.) to achieve uniform distribution. At the same time, logistic mapping reduces the speed of generating random numbers and has a higher tolerance for the performance of the FPGA.


#### 2.2.2. Tent Mapping

Tent mapping is a piecewise linear one-dimensional mapping with uniform probability density function (PDF), power spectral density (PSD). And the iteration speed of tent mapping is faster than that of Logistic mapping. Angulo et al. [62] constructed a discrete chaotic oscillator with tent mapping, buffer and clock generator, and then generated random numbers by 8 bit LFSR corrector. A low power real random number generator based on discrete-time chaos was designed and implemented using standard CMOS AMS 0.35 µm process. Cicek et al. [63] used a one-dimensional discrete-time skew tent map as the entropy source to design TRNGs. A practical information measurement method was used to determine the maximum allowable parameter range, and a current mode skew tent circuit was designed to verify the method. Teh and Samsudin [64] proposed a new AEAD (authenticated encryption with associated data) scheme that was implemented with true random number generators based on the chaotic tent map. However, there were small periodic and unstable periodic points in the tent iteration sequence, it would degrade the random performance and reduce the security.


#### 2.2.3. Bernoulli Mapping

Bernoulli mapping is a linear mapping consisting of two piecewise linear parts, which are separated by discontinuous points and are often used in random number generators. In 2014, Cicek et al. [65] proposed a dual entropy core TRNG architecture, by using Bernoulli mapping as the entropy source, and using FPGA to successfully design and implement the proposed architecture. Compared with the single entropy core, this architecture has a wide range of control parameter values, and the stochastic performance is better. However, the single Lyapunov index and limited entropy of bernoulli mapping leads to higher cost. In 2019, Hsueh and Chen [66] proposed an ultra-low voltage chaos-based true random number generator for IoT applications. The authors used folded Bernoulli mapping to generate random numbers. In the switched-capacitor chaotic circuits, bulk-driven amplifiers were used to alleviate gate leakage issue, two-stage comparators were used to increase voltage headroom.


#### 2.2.4. Piece-Wise Affine Markov (PWAM) Mapping

PWAM mapping is piecewise one-dimensional Markov mapping which has infinite folding property with uniform distribution in finite intervals to enhance robustness in simulation implementation. The state interval−
1
,
1 of an exact extensible mapping M
:
−
1
,
1
→
−
1
,
1 is divided into n sub-intervals X
i
,
i
=
1
,
2
,
⋯
,
n. For any interval X
i and X
j, or M
X
i
∩
X
j
=
∅ or X
i
⊂
X
j, then the mapping M is also called the PWAM mapping of the piecewise interval. Milos and Pavol [67] proposed PWAM mapping to the switched capacitor based hybrid signal PSoC devices to reduce the impact of circuit imperfections on the quality of random bit streams. Pareschi et al. [68] proposed two methods of rearranging a pipelined ADC to generate random bit stream using discrete chaotic circuit as entropy source. The two methods were compared with the traditional methods. The CMOS technology of 0.35 µm and 0.18 µm were used to realize the two methods, respectively. PWAM mapping is better than traditional mappings in security, randomness, and other aspects, but its equations and implementation are more complex than traditional mappings.


#### 2.2.5. Discrete Time Chaotic Oscillator

Discrete time chaotic oscillator is one of the most interesting topics of research and the designing of the circuit been extensively studied for many decades. A common structure of discrete time chaotic oscillator is shown in Figure7. It can be seen that this chaotic oscillator consisted of three parts of circuit, a nonlinear circuit to represents the chaotic map, two sample-and-hold circuits (S/H) to track and store the signals as a memory and the buffer to carry signals to the next stage implemented by a two-stage operational amplifier (op-amp). Dhanuskodi et al. [69] had proposed a TRNG based on chaotic ring oscillator. In order to pass the statistical test, XOR was used to post-process the random number generated by the chaotic ring oscillator. The output bitstream of TRNG implemented in 45 nm CMOS process was tested by NIST test suite and it passed 11 tests with throughput of 127 MB/s. Jiteurtragool et al. [70] proposed a TRNG for discrete time chaotic oscillator based on 0.18 µm CMOS technology. A chaotic oscillator was designed by using three transistor mapping circuits and approximating V-shaped mapping as a chaotic nonlinear function. In order to improve the randomness of the output signal, the double oscillator and XOR were used to sample the random signal generated by the chaotic oscillator. The random number generated by the processing technology was evenly distributed, and the final output bit rate was 23 MB/s.Figure 7
A common structure of discrete-time chaotic oscillator.


### 2.3. TRNGS Based on Current-Mode Chaos

One of the main drawbacks of chaotic RNG integrated circuits is the robustness of the system. Chaotic nonlinear finite difference equation (FDE) is very sensitive to the coefficients of the equation [71]. Therefore, the circuit for realizing chaotic FDE must be very precise and have narrower boundaries than other analog applications. Small variations in coefficients can also be attributed to external effects, such as power supply voltage, temperature, and process variations [72].Many chaotic circuits are implemented in switched capacitor voltage-mode. Contrary to current-mode, voltage-mode circuits require large capacitors and high gain amplifiers, which consume both power and area [73]. In addition, in sub-100 nm technology, the leakage current of the capacitor is larger, and its capacitance value has higher dispersion, which reduces the robustness of voltage mode design [74–77]. In recent years, the realization of chaotic oscillation circuits by current mode devices has become a new research direction, such as current followers (CF) [78], second-generation current conveyor (CCII) [79], current controlled current conveyor (CCCII) [80], current-feedback operational amplifier (CFOA) [81], Operational Transconductance Amplifier (OTA) [82] and unity-gain cells (UGCs) [83], etc. Katz et al. [84] proposed a robust TRNG based on a differential current-mode chaos which was implemented on 90 nm CMOS-SOI technology. The differential design also showed excellent robustness to power supply voltage, temperature and process changes. In order to verify that the circuit could be used as a white noise generator, according to the suggestion of Federal Information Processing Standard (FIPS), the simulation results were tested and verified on hardware.


## 2.1. TRNGs Based on Continuous Time Chaotic System

Continuous time chaotic system is a chaotic system based on observation time series, and its state is time-dependent. The mathematical model of continuous time chaotic dynamic system is as follows:(1)
x
˙
=
f
x
,
t
,wherex
∈
R
n is the state variable and f
:
R
n
×
R
n
→
R
n. Common continuous time chaotic systems like Lorenz system [29], Chua’s circuit system [30], Jerk system [31], chaotic oscillator [32–34], and many hyperchaotic systems have been proposed [35–37]. Throughout the years, continuous time chaotic systems have been mostly focused on neural network, synchronization, secure communication [38–42], and other fields, especially the design of TRNGs. For that reason, continuous time chaotic circuits are the most abundant ones. In this section, we describe the most popular continuous time chaotic circuits for TRNGs design, considering continuous time chaotic systems that contain any kind of continuous time chaotic circuits representation such as Chua’s circuit, Jerk circuit, various chaotic oscillators, and FPGA.


### 2.1.1. Chua’s System

Chua’s system is a classical nonlinear electronic circuit, which can show the standard double scroll chaotic dynamic behavior. It was published by Professor Shaotang Cai in 1983. Blaszczyk and Guinee [43] proposed a TRNG which was employed by Chua’s circuit and used a simple temperature dependent control resistor in the oscillator circuit and optimal voltage threshold settings. The randomness attributes of the generator were confirmed via PSpice simulation, by the NIST tests for statistical validation. Moqadasi and Ghaznavi-Ghoushchi [44] proposed a TRNG which based on a new Chua’s circuit that its negative resistor was a monolithic CMOS based circuit with 12 transistors. This proposed system also consisted of a sample and hold block, an analog to digital converter (ADC) block and a linear feedback shift register (LFSR) block which scrambles generated bit stream and increases randomness, as shown in Figure 3. When the number of LFSR bits changed from 6 to 32, the experiments confirmed that the 6 bits length was optimum for LFSR which was better than previous works.Figure 3
True random number generation from the Chua’s circuit core proposed by Moqadasi and Ghaznavi-Ghoushchi.


### 2.1.2. Jerk System

American scholar Sprott [45] proposed the Jerk system x
⃛
=
F
x
¨
,
x
˙
,
x, where x
˙
=
d
x
/
d
t is the first derivative of position, x
¨
=
d
2
x
/
d
t
2 call acceleration, x
⃛
=
d
3
x
/
d
t
3 call Jerk. Its generalized dimensionless equation of state is:(2)
d
x
/
d
t
=
y
,
d
y
/
d
t
=
z
,
d
y
/
d
t
=
z
,wherex
,
y
,
z are the state variable, α
,
β are the system parameters, f
x is a nonlinear term. In (2), the transformation system of x
,
y
,
z
→
−
x
,
−
y
,
−
z can remain unchanged. The system is symmetrical about the origin. Jerk system is characterized by concise equation form and easy circuit realization.In 2018, Wannaboon et al. [46] presented a fully customized design of TRNG which implemented on a 0.18 µm CMOS technology with unique composition of three major components, chaotic jerk oscillator, Δ
∑ modulator, and simple pre/post-processing. The block diagram of the proposed TRNG is shown in Figure 4. The chaotic Jerk circuit provided chaotic signals with strong robustness and randomness, and exhibited the unique characteristics of smoothly balanced-to-unbalanced alternation of double scroll attractors. In order to improve the resolution of random bit sequence, the continuous time second-order Δ
∑ modulator was introduced as the mixed signal interface without additional clock. The simple structure of shift-registers was implemented as a post-processing process. The bit sequence of the proposed TRNG successfully passed all statistical tests of NIST SP800-22 test suite, and the final output bit rate was 50 Mbps. However, the slight uncertainty of the initial conditions, which is unavoidable in IC implementation, leads to a very large uncertainty after very short time. Because of this, the system behavior can only be predicted for a short time period.Figure 4
Block diagram of the TRBG with sigma-delta modulation of chaotic jerk signals proposed by Wannaboon et al.


### 2.1.3. Boolean Chaotic Oscillator

Boolean chaos [47] is a phenomenon in an autonomous network which shows nonrepeating chaotic oscillations, exponential sensitivity to initial conditions, and has a broadband power spectrum. Boolean chaotic oscillator includes Boolean-like state transitions with a fast transition time, and a feedback loop with incommensurate delay inputs. The dynamics of nodes network is described by:(3)
x
n
t
=
f
n
t
,
x
1
t
−
τ
n
1
,
…
,
x
n
t
−
τ
n
n
,whereτ
n
m is the delay time from the nth node to the mth node, x
n
t is the Boolean logic state at the nth node at time t, and f
n is the logic function for the nth node. Park et al. [48] reported on a TRNG whose randomness derived from a Boolean chaotic oscillator, as shown in Figure 5. Using a CMOS 0.35 µm process, the paper built a CMOS Boolean chaotic oscillator, which consisted of a core chaotic oscillator and a source follower buffer. The generated random bit sequences passed the widely accepted statistical tests used for evaluating cryptographic random number generators.Figure 5
Schematic diagram of random number generation using CMOS Boolean chaotic oscillator.


### 2.1.4. Jitter Booster Circuit

The nonperiodicity of a chaotic signal implies that the signal has irregular temporal zero crossings as in the case of highly jittered oscillations. The idea of using chaos for enhancing jitter can be an alternative to the multiring oscillator sampling approach. Çiçek and Dündar [49] presented a chaos based integrated jitter booster circuit for multiple oscillator sampling TRNG architecture. The proposed circuit provided an alternative method for enhancing jitter using the chaotic dynamics produced by nonlinear coupling of two ring oscillators, which required fewer components.


### 2.1.5. Coupled Chaotic Oscillator

Coupled chaotic oscillators are very suitable for monolithic implementation and capable of operating at very high frequencies when appropriate design considerations and experience are exercised. In [50], two integrated continuous-time chaotic oscillators based on cross-coupled −
g
m oscillators were presented and their application to random bit generation was described. In [51], a TRNG design was proposed which employed a dual coupled oscillator architecture. This structure improved the output throughput and solved the external interference problems. The frequency of a slower clock modulated the chaotic oscillator output signal, and with the rising edge of the chaotic modulation clock, a faster clock was sampled. The proposed design fulfilled the tests used in both the FIPS-140-2 and the NIST-800-22 random number test suites.


### 2.1.6. FPGA-Based

Considering technologies mentioned above, the highest performance could be obtained from IC-based chaotic generators. However, IC-based implementations do not promise a flexible use. In addition, the cost of prototyping and testing such systems will be high. FPGA chips are able to run concurrently and have relatively flexible architecture. The cost of design and test cycles of FPGA chips is particularly low [52]. Because of its high-speed and high-quality random generation, FPGA has become a popular platform for implementing random generators or complete cryptographic schemes. Koyuncu and Ozcerit [53] modeled Sundarapandian-Pehlivan chaotic system and simulated in three distinct platforms to show the advantages of FPGA-based chaotic oscillator with respect to alternative solutions. The chaotic system was modeled by the Runge-Kutta (RK4) in hardware description language (VHDL) and the model was synthesized and tested on Xilinx Virtex-6 FPGA chip, the block diagram of an FPGA based TRNG designed is illustrated in Figure 6. The designed chaotic oscillator was tested by TRNG and the maximum operating frequency was 293 MHz with a speed of 58.76 Mbit/s. Akgul et al. [54] used the 3D chaotic system without equilibrium points as the source of entropy built the chaotic system model with FPGA, then designed and implemented the chaotic oscillator with VHDL and RK-4 algorithm, and finally chose the most complex bits of binary numbers to generate random numbers.Figure 6
Block diagram of FPGA-based chaotic TRNG.


## 2.1.1. Chua’s System

Chua’s system is a classical nonlinear electronic circuit, which can show the standard double scroll chaotic dynamic behavior. It was published by Professor Shaotang Cai in 1983. Blaszczyk and Guinee [43] proposed a TRNG which was employed by Chua’s circuit and used a simple temperature dependent control resistor in the oscillator circuit and optimal voltage threshold settings. The randomness attributes of the generator were confirmed via PSpice simulation, by the NIST tests for statistical validation. Moqadasi and Ghaznavi-Ghoushchi [44] proposed a TRNG which based on a new Chua’s circuit that its negative resistor was a monolithic CMOS based circuit with 12 transistors. This proposed system also consisted of a sample and hold block, an analog to digital converter (ADC) block and a linear feedback shift register (LFSR) block which scrambles generated bit stream and increases randomness, as shown in Figure 3. When the number of LFSR bits changed from 6 to 32, the experiments confirmed that the 6 bits length was optimum for LFSR which was better than previous works.Figure 3
True random number generation from the Chua’s circuit core proposed by Moqadasi and Ghaznavi-Ghoushchi.


## 2.1.2. Jerk System

American scholar Sprott [45] proposed the Jerk system x
⃛
=
F
x
¨
,
x
˙
,
x, where x
˙
=
d
x
/
d
t is the first derivative of position, x
¨
=
d
2
x
/
d
t
2 call acceleration, x
⃛
=
d
3
x
/
d
t
3 call Jerk. Its generalized dimensionless equation of state is:(2)
d
x
/
d
t
=
y
,
d
y
/
d
t
=
z
,
d
y
/
d
t
=
z
,wherex
,
y
,
z are the state variable, α
,
β are the system parameters, f
x is a nonlinear term. In (2), the transformation system of x
,
y
,
z
→
−
x
,
−
y
,
−
z can remain unchanged. The system is symmetrical about the origin. Jerk system is characterized by concise equation form and easy circuit realization.In 2018, Wannaboon et al. [46] presented a fully customized design of TRNG which implemented on a 0.18 µm CMOS technology with unique composition of three major components, chaotic jerk oscillator, Δ
∑ modulator, and simple pre/post-processing. The block diagram of the proposed TRNG is shown in Figure 4. The chaotic Jerk circuit provided chaotic signals with strong robustness and randomness, and exhibited the unique characteristics of smoothly balanced-to-unbalanced alternation of double scroll attractors. In order to improve the resolution of random bit sequence, the continuous time second-order Δ
∑ modulator was introduced as the mixed signal interface without additional clock. The simple structure of shift-registers was implemented as a post-processing process. The bit sequence of the proposed TRNG successfully passed all statistical tests of NIST SP800-22 test suite, and the final output bit rate was 50 Mbps. However, the slight uncertainty of the initial conditions, which is unavoidable in IC implementation, leads to a very large uncertainty after very short time. Because of this, the system behavior can only be predicted for a short time period.Figure 4
Block diagram of the TRBG with sigma-delta modulation of chaotic jerk signals proposed by Wannaboon et al.


## 2.1.3. Boolean Chaotic Oscillator

Boolean chaos [47] is a phenomenon in an autonomous network which shows nonrepeating chaotic oscillations, exponential sensitivity to initial conditions, and has a broadband power spectrum. Boolean chaotic oscillator includes Boolean-like state transitions with a fast transition time, and a feedback loop with incommensurate delay inputs. The dynamics of nodes network is described by:(3)
x
n
t
=
f
n
t
,
x
1
t
−
τ
n
1
,
…
,
x
n
t
−
τ
n
n
,whereτ
n
m is the delay time from the nth node to the mth node, x
n
t is the Boolean logic state at the nth node at time t, and f
n is the logic function for the nth node. Park et al. [48] reported on a TRNG whose randomness derived from a Boolean chaotic oscillator, as shown in Figure 5. Using a CMOS 0.35 µm process, the paper built a CMOS Boolean chaotic oscillator, which consisted of a core chaotic oscillator and a source follower buffer. The generated random bit sequences passed the widely accepted statistical tests used for evaluating cryptographic random number generators.Figure 5
Schematic diagram of random number generation using CMOS Boolean chaotic oscillator.


## 2.1.4. Jitter Booster Circuit

The nonperiodicity of a chaotic signal implies that the signal has irregular temporal zero crossings as in the case of highly jittered oscillations. The idea of using chaos for enhancing jitter can be an alternative to the multiring oscillator sampling approach. Çiçek and Dündar [49] presented a chaos based integrated jitter booster circuit for multiple oscillator sampling TRNG architecture. The proposed circuit provided an alternative method for enhancing jitter using the chaotic dynamics produced by nonlinear coupling of two ring oscillators, which required fewer components.


## 2.1.5. Coupled Chaotic Oscillator

Coupled chaotic oscillators are very suitable for monolithic implementation and capable of operating at very high frequencies when appropriate design considerations and experience are exercised. In [50], two integrated continuous-time chaotic oscillators based on cross-coupled −
g
m oscillators were presented and their application to random bit generation was described. In [51], a TRNG design was proposed which employed a dual coupled oscillator architecture. This structure improved the output throughput and solved the external interference problems. The frequency of a slower clock modulated the chaotic oscillator output signal, and with the rising edge of the chaotic modulation clock, a faster clock was sampled. The proposed design fulfilled the tests used in both the FIPS-140-2 and the NIST-800-22 random number test suites.


## 2.1.6. FPGA-Based

Considering technologies mentioned above, the highest performance could be obtained from IC-based chaotic generators. However, IC-based implementations do not promise a flexible use. In addition, the cost of prototyping and testing such systems will be high. FPGA chips are able to run concurrently and have relatively flexible architecture. The cost of design and test cycles of FPGA chips is particularly low [52]. Because of its high-speed and high-quality random generation, FPGA has become a popular platform for implementing random generators or complete cryptographic schemes. Koyuncu and Ozcerit [53] modeled Sundarapandian-Pehlivan chaotic system and simulated in three distinct platforms to show the advantages of FPGA-based chaotic oscillator with respect to alternative solutions. The chaotic system was modeled by the Runge-Kutta (RK4) in hardware description language (VHDL) and the model was synthesized and tested on Xilinx Virtex-6 FPGA chip, the block diagram of an FPGA based TRNG designed is illustrated in Figure 6. The designed chaotic oscillator was tested by TRNG and the maximum operating frequency was 293 MHz with a speed of 58.76 Mbit/s. Akgul et al. [54] used the 3D chaotic system without equilibrium points as the source of entropy built the chaotic system model with FPGA, then designed and implemented the chaotic oscillator with VHDL and RK-4 algorithm, and finally chose the most complex bits of binary numbers to generate random numbers.Figure 6
Block diagram of FPGA-based chaotic TRNG.


## 2.2. TRNGs Based on Discrete Time Chaotic System

Discrete time chaotic systems also exist widely in the field of nonlinear science, such as physics, biology, and chemistry [55], especially in the generation of TRNs. One-dimensional discrete time nonlinear dynamical systems are defined as follows:(4)
x
k
+
1
=
τ
x
k
,wherex
k
,
k
=
0
,
1
,
2
,
⋯, are state. And τ is a mapping that mapping the current state x
k to the next state x
k
+
1. If we start with an initial x
0 value and apply τ repeatedly, we get a sequence x
k
,
k
=
0
,
1
,
2
,
⋯. This sequence is called a trajectory of the discrete time dynamic system. Classical discrete time chaotic systems include logistic mapping, tent mapping, Bernoulli mapping, and so on. FPGAs can be used to implement discrete time systems as well, but as far as the author knows, there are few literatures about the realization of TRNGs based on discrete time chaotic systems by using FPGA, so there is no detailed introduction here.


### 2.2.1. Logistic Mapping

A very simple but widely studied dynamical system is logistic mapping, which originates from the insect population model. Its definition has many forms: (1)x
k
+
1
=
μ
x
k
1
−
x
k, when 3.5699456
⋯
≤
μ
≤
4, logistic mapping works in chaotic state; (2) x
k
+
1
=
1
−
γ
x
k
2, when γ
∈
1.5437
,
2, logistic mapping works in chaotic state; (3) x
k
+
1
=
μ
x
k
−
x
k
2, when μ
∈
3.5699
,
4, logistic mapping works in chaotic state. It can be seen that logistic mapping is actually a first-order equation, which requires initialization conditions and control parameters. Therefore, it is easy to implement in hardware, and people often use this mapping to design TRNGs.In 2015, Avaroğlu et al. [56] used logistic map in post-processing to ensure that numbers generated by RO-based TRNG were of high quality. In order to observe the influences of the logistic map, four different scenarios considering RO-based TRNG structure were studied. [57] proposed a TRNGs with graphics processing units as the source of entropy, unpredictable behavior of which was managed by computing logistic maps, and high throughput achieved 447.83 Mbit/s. Tuncer [58] applied the random challenges from the logistic map to physical unclonable functions based on ring oscillator (RO-PUF) to generate random numbers in real time in FPGA, which prevented the PUF from being attacked (cracked) and improved the randomness of the random numbers. Because the value distribution of logistic mapping points is too centralized and blank bands appear in other regions, the uniform distribution characteristics of the mapping points are poor, so that logistic mapping needs post-processing (Von Neumann corrector [59], XOR correctors [60], one-way hash function [61], etc.) to achieve uniform distribution. At the same time, logistic mapping reduces the speed of generating random numbers and has a higher tolerance for the performance of the FPGA.


### 2.2.2. Tent Mapping

Tent mapping is a piecewise linear one-dimensional mapping with uniform probability density function (PDF), power spectral density (PSD). And the iteration speed of tent mapping is faster than that of Logistic mapping. Angulo et al. [62] constructed a discrete chaotic oscillator with tent mapping, buffer and clock generator, and then generated random numbers by 8 bit LFSR corrector. A low power real random number generator based on discrete-time chaos was designed and implemented using standard CMOS AMS 0.35 µm process. Cicek et al. [63] used a one-dimensional discrete-time skew tent map as the entropy source to design TRNGs. A practical information measurement method was used to determine the maximum allowable parameter range, and a current mode skew tent circuit was designed to verify the method. Teh and Samsudin [64] proposed a new AEAD (authenticated encryption with associated data) scheme that was implemented with true random number generators based on the chaotic tent map. However, there were small periodic and unstable periodic points in the tent iteration sequence, it would degrade the random performance and reduce the security.


### 2.2.3. Bernoulli Mapping

Bernoulli mapping is a linear mapping consisting of two piecewise linear parts, which are separated by discontinuous points and are often used in random number generators. In 2014, Cicek et al. [65] proposed a dual entropy core TRNG architecture, by using Bernoulli mapping as the entropy source, and using FPGA to successfully design and implement the proposed architecture. Compared with the single entropy core, this architecture has a wide range of control parameter values, and the stochastic performance is better. However, the single Lyapunov index and limited entropy of bernoulli mapping leads to higher cost. In 2019, Hsueh and Chen [66] proposed an ultra-low voltage chaos-based true random number generator for IoT applications. The authors used folded Bernoulli mapping to generate random numbers. In the switched-capacitor chaotic circuits, bulk-driven amplifiers were used to alleviate gate leakage issue, two-stage comparators were used to increase voltage headroom.


### 2.2.4. Piece-Wise Affine Markov (PWAM) Mapping

PWAM mapping is piecewise one-dimensional Markov mapping which has infinite folding property with uniform distribution in finite intervals to enhance robustness in simulation implementation. The state interval−
1
,
1 of an exact extensible mapping M
:
−
1
,
1
→
−
1
,
1 is divided into n sub-intervals X
i
,
i
=
1
,
2
,
⋯
,
n. For any interval X
i and X
j, or M
X
i
∩
X
j
=
∅ or X
i
⊂
X
j, then the mapping M is also called the PWAM mapping of the piecewise interval. Milos and Pavol [67] proposed PWAM mapping to the switched capacitor based hybrid signal PSoC devices to reduce the impact of circuit imperfections on the quality of random bit streams. Pareschi et al. [68] proposed two methods of rearranging a pipelined ADC to generate random bit stream using discrete chaotic circuit as entropy source. The two methods were compared with the traditional methods. The CMOS technology of 0.35 µm and 0.18 µm were used to realize the two methods, respectively. PWAM mapping is better than traditional mappings in security, randomness, and other aspects, but its equations and implementation are more complex than traditional mappings.


### 2.2.5. Discrete Time Chaotic Oscillator

Discrete time chaotic oscillator is one of the most interesting topics of research and the designing of the circuit been extensively studied for many decades. A common structure of discrete time chaotic oscillator is shown in Figure7. It can be seen that this chaotic oscillator consisted of three parts of circuit, a nonlinear circuit to represents the chaotic map, two sample-and-hold circuits (S/H) to track and store the signals as a memory and the buffer to carry signals to the next stage implemented by a two-stage operational amplifier (op-amp). Dhanuskodi et al. [69] had proposed a TRNG based on chaotic ring oscillator. In order to pass the statistical test, XOR was used to post-process the random number generated by the chaotic ring oscillator. The output bitstream of TRNG implemented in 45 nm CMOS process was tested by NIST test suite and it passed 11 tests with throughput of 127 MB/s. Jiteurtragool et al. [70] proposed a TRNG for discrete time chaotic oscillator based on 0.18 µm CMOS technology. A chaotic oscillator was designed by using three transistor mapping circuits and approximating V-shaped mapping as a chaotic nonlinear function. In order to improve the randomness of the output signal, the double oscillator and XOR were used to sample the random signal generated by the chaotic oscillator. The random number generated by the processing technology was evenly distributed, and the final output bit rate was 23 MB/s.Figure 7
A common structure of discrete-time chaotic oscillator.


## 2.2.1. Logistic Mapping

A very simple but widely studied dynamical system is logistic mapping, which originates from the insect population model. Its definition has many forms: (1)x
k
+
1
=
μ
x
k
1
−
x
k, when 3.5699456
⋯
≤
μ
≤
4, logistic mapping works in chaotic state; (2) x
k
+
1
=
1
−
γ
x
k
2, when γ
∈
1.5437
,
2, logistic mapping works in chaotic state; (3) x
k
+
1
=
μ
x
k
−
x
k
2, when μ
∈
3.5699
,
4, logistic mapping works in chaotic state. It can be seen that logistic mapping is actually a first-order equation, which requires initialization conditions and control parameters. Therefore, it is easy to implement in hardware, and people often use this mapping to design TRNGs.In 2015, Avaroğlu et al. [56] used logistic map in post-processing to ensure that numbers generated by RO-based TRNG were of high quality. In order to observe the influences of the logistic map, four different scenarios considering RO-based TRNG structure were studied. [57] proposed a TRNGs with graphics processing units as the source of entropy, unpredictable behavior of which was managed by computing logistic maps, and high throughput achieved 447.83 Mbit/s. Tuncer [58] applied the random challenges from the logistic map to physical unclonable functions based on ring oscillator (RO-PUF) to generate random numbers in real time in FPGA, which prevented the PUF from being attacked (cracked) and improved the randomness of the random numbers. Because the value distribution of logistic mapping points is too centralized and blank bands appear in other regions, the uniform distribution characteristics of the mapping points are poor, so that logistic mapping needs post-processing (Von Neumann corrector [59], XOR correctors [60], one-way hash function [61], etc.) to achieve uniform distribution. At the same time, logistic mapping reduces the speed of generating random numbers and has a higher tolerance for the performance of the FPGA.


## 2.2.2. Tent Mapping

Tent mapping is a piecewise linear one-dimensional mapping with uniform probability density function (PDF), power spectral density (PSD). And the iteration speed of tent mapping is faster than that of Logistic mapping. Angulo et al. [62] constructed a discrete chaotic oscillator with tent mapping, buffer and clock generator, and then generated random numbers by 8 bit LFSR corrector. A low power real random number generator based on discrete-time chaos was designed and implemented using standard CMOS AMS 0.35 µm process. Cicek et al. [63] used a one-dimensional discrete-time skew tent map as the entropy source to design TRNGs. A practical information measurement method was used to determine the maximum allowable parameter range, and a current mode skew tent circuit was designed to verify the method. Teh and Samsudin [64] proposed a new AEAD (authenticated encryption with associated data) scheme that was implemented with true random number generators based on the chaotic tent map. However, there were small periodic and unstable periodic points in the tent iteration sequence, it would degrade the random performance and reduce the security.


## 2.2.3. Bernoulli Mapping

Bernoulli mapping is a linear mapping consisting of two piecewise linear parts, which are separated by discontinuous points and are often used in random number generators. In 2014, Cicek et al. [65] proposed a dual entropy core TRNG architecture, by using Bernoulli mapping as the entropy source, and using FPGA to successfully design and implement the proposed architecture. Compared with the single entropy core, this architecture has a wide range of control parameter values, and the stochastic performance is better. However, the single Lyapunov index and limited entropy of bernoulli mapping leads to higher cost. In 2019, Hsueh and Chen [66] proposed an ultra-low voltage chaos-based true random number generator for IoT applications. The authors used folded Bernoulli mapping to generate random numbers. In the switched-capacitor chaotic circuits, bulk-driven amplifiers were used to alleviate gate leakage issue, two-stage comparators were used to increase voltage headroom.


## 2.2.4. Piece-Wise Affine Markov (PWAM) Mapping

PWAM mapping is piecewise one-dimensional Markov mapping which has infinite folding property with uniform distribution in finite intervals to enhance robustness in simulation implementation. The state interval−
1
,
1 of an exact extensible mapping M
:
−
1
,
1
→
−
1
,
1 is divided into n sub-intervals X
i
,
i
=
1
,
2
,
⋯
,
n. For any interval X
i and X
j, or M
X
i
∩
X
j
=
∅ or X
i
⊂
X
j, then the mapping M is also called the PWAM mapping of the piecewise interval. Milos and Pavol [67] proposed PWAM mapping to the switched capacitor based hybrid signal PSoC devices to reduce the impact of circuit imperfections on the quality of random bit streams. Pareschi et al. [68] proposed two methods of rearranging a pipelined ADC to generate random bit stream using discrete chaotic circuit as entropy source. The two methods were compared with the traditional methods. The CMOS technology of 0.35 µm and 0.18 µm were used to realize the two methods, respectively. PWAM mapping is better than traditional mappings in security, randomness, and other aspects, but its equations and implementation are more complex than traditional mappings.


## 2.2.5. Discrete Time Chaotic Oscillator

Discrete time chaotic oscillator is one of the most interesting topics of research and the designing of the circuit been extensively studied for many decades. A common structure of discrete time chaotic oscillator is shown in Figure7. It can be seen that this chaotic oscillator consisted of three parts of circuit, a nonlinear circuit to represents the chaotic map, two sample-and-hold circuits (S/H) to track and store the signals as a memory and the buffer to carry signals to the next stage implemented by a two-stage operational amplifier (op-amp). Dhanuskodi et al. [69] had proposed a TRNG based on chaotic ring oscillator. In order to pass the statistical test, XOR was used to post-process the random number generated by the chaotic ring oscillator. The output bitstream of TRNG implemented in 45 nm CMOS process was tested by NIST test suite and it passed 11 tests with throughput of 127 MB/s. Jiteurtragool et al. [70] proposed a TRNG for discrete time chaotic oscillator based on 0.18 µm CMOS technology. A chaotic oscillator was designed by using three transistor mapping circuits and approximating V-shaped mapping as a chaotic nonlinear function. In order to improve the randomness of the output signal, the double oscillator and XOR were used to sample the random signal generated by the chaotic oscillator. The random number generated by the processing technology was evenly distributed, and the final output bit rate was 23 MB/s.Figure 7
A common structure of discrete-time chaotic oscillator.


## 2.3. TRNGS Based on Current-Mode Chaos

One of the main drawbacks of chaotic RNG integrated circuits is the robustness of the system. Chaotic nonlinear finite difference equation (FDE) is very sensitive to the coefficients of the equation [71]. Therefore, the circuit for realizing chaotic FDE must be very precise and have narrower boundaries than other analog applications. Small variations in coefficients can also be attributed to external effects, such as power supply voltage, temperature, and process variations [72].Many chaotic circuits are implemented in switched capacitor voltage-mode. Contrary to current-mode, voltage-mode circuits require large capacitors and high gain amplifiers, which consume both power and area [73]. In addition, in sub-100 nm technology, the leakage current of the capacitor is larger, and its capacitance value has higher dispersion, which reduces the robustness of voltage mode design [74–77]. In recent years, the realization of chaotic oscillation circuits by current mode devices has become a new research direction, such as current followers (CF) [78], second-generation current conveyor (CCII) [79], current controlled current conveyor (CCCII) [80], current-feedback operational amplifier (CFOA) [81], Operational Transconductance Amplifier (OTA) [82] and unity-gain cells (UGCs) [83], etc. Katz et al. [84] proposed a robust TRNG based on a differential current-mode chaos which was implemented on 90 nm CMOS-SOI technology. The differential design also showed excellent robustness to power supply voltage, temperature and process changes. In order to verify that the circuit could be used as a white noise generator, according to the suggestion of Federal Information Processing Standard (FIPS), the simulation results were tested and verified on hardware.


## 3. Discussion

In the previous section we reviewed the existing TRNGs based on chaos from a literary and qualitative point of view, i.e., Figure8 shows a graph of the reviewed methods for the TRNGs based on chaos. In this Section we are going to discuss the merits and demerits of TRNGs based on chaos.Figure 8
A graph of the reviewed methods for the TRNGs based on chaos.Discrete time chaos has long been used in TRNG, but recent studies have shown that continuous time oscillators can also be used in TRNG. The application of discrete time chaos is well known, but there are few experimental reports on integrated circuits, most of them use FPGA to realize TRNGs. Continuous time chaos is easy to integrate, but it needs to be discretized before sampling. TRNG based on discrete time chaos dynamically controls the evolution and bit generation speed by adjusting the clock signal. Table1 summarizes the implementation methods of chaos-based TRNGs in recent years.Table 1
Summary of TRNGs methods based on chaos.
Classification
Author and reference
Area (mm2)
Power (mW)
Out bit rate (speed) (Mbit/s)
Energy (PJ/bit)
Post processing
Test suite
Technology
Chua’s system
Moqadasi [44]
N/A
N/A
2.02
N/A
6 bit LFSR
FIPS 140-1
0.18µm CMOS
Jerk system
Wannaboon [46]
0.037689
1.32
50
26.4
Von Neumann
NIST SP800-22 and TestU01
0.18µm CMOS
Boolean chaotic oscillator
Park [48]
0.057
26.1
300
87
XOR
NIST
0.35µm CMOS
Coupled chaotic oscillator
Ozoguz [51]
N/A
N/A
2
N/A
Von Neumann
FIPS 140-1 and NIST
0.35µm CMOS
FPGA-based
Akgul [54]
N/A
N/A
4.59
N/A
XOR
FIPS 140-1 and NIST SP800-22
FPGA
Logistic mapping
Avaroglu [56]
N/A
N/A
20
N/A
RO and inverter number
NIST SP800-22 and TestU01
FPGA
Logistic mapping
Teh [57]
N/A
N/A
447.83
N/A
XOR and32-bit addition
NIST SP 800-22
CPU
Tent mapping
Angulo [62]
0.07
0.15
0.25
800
8 bit LFSR
NIST
0.35µm CMOS
Bernoulli mapping
Cicek [65]
N/A
125
1.5
83300
N/A
NIST SP800-22
FPGA
PWAM mapping
Pareschi [68]
0.752
29
40
0.725
N/A
NIST SP800-22
0.35µm CMOS
Discrete-timechaotic oscillator
Dhanuskodi [69]
93.1
1.0967
127
8
XOR
NIST
0.45µm CMOS
Current-modechaos
Katz [80]
0.02
0.8
25
32
N/A
FIPS 140-2
0.09µm CMOSAccording to the random bit rate requirement of output per second, it can be defined as:(5)
Bit
Rate
=
Power
Dissipation
mW
E
b
nJ
/
bit
.As can be seen from Table1, by comparing the output bit rates of all continuous time chaotic oscillators, it can be seen that the speed of Boolean chaotic oscillator in [48] is much higher than that of other TRNGs based on continuous time chaotic oscillators. Meanwhile, the power of Boolean chaotic oscillator in [48] is much larger than that in [47]. Because of the low frequency and narrow bandwidth of chaos, TRNG is based on the traditional chaotic oscillator as the source of entropy, such as Chua’s circuit [44], Jerk circuit [46], no-equilibrium chaotic system [54], etc. By comparing the output bit rates of all TRNGs based on discrete time chaos, we can see that the speed of [57] is much faster than that of other chaotic output bits, because it is realized by CPU. In addition, [67] provides higher throughput than most designs in lower regions, reaching 127 Mbit/s. In [69], besides the inherent chaos, the oscillator also collects physical noise, and uses the combination of two light sources to improve the output speed of the oscillator. Compared with the TRNG’s area of the same CMOS process, under 0.35 µm CMOS process in [48, 62, 69], the largest area is [69]. The reason is that the authors used eight-stage pipeline ADC and two-stage pipeline ADC to design circuits. ADC is often used to design chaotic maps to generate random numbers, speed is better, but it takes up a large area.


## 4. Conclusion and Future Work

To identify the state-of-the-art in the area of TRN and to find out what we know about TRNGs based on chaos, we conducted and presented in this article a systematic literature mapping. The purpose of this article is to help readers (including practitioners and researchers) conduct the most comprehensive survey in the field of TRNG based on chaos. In the end, the research results are discussed, which provides useful insights for future research directions and open issues in this field. From this study, we can draw a general conclusion that TRNGs based on chaos has obtained many successful cases, but it is still an open problem, and its solution will prove very useful for wide application.By classifying the entire body of knowledge, this survey paper “mapped” the body of knowledge on TRNGs based on chaos. We systematically classified a large set of 85 papers and investigated several review structures under three groups. The first group investigated the contribution as well as the TRNGs based on continuous time chaotic systems. The second group investigated the mappings for TRNGs based on discrete time chaotic systems. The third group investigated the TRNGs based on current-mode chaos.In recent years, it has been proved that continuous time chaotic systems can be used in the design of TRNGs. Because the number of positive Lyapunov exponents of entropy sources is limited, so hyperchaotic systems used in TRNGs is one of the important development directions in the future. It can be seen that PRNGs based on discrete-time chaos have developed from one-dimensional to two-dimensional and multi-dimensional, so the design of TRNGs using multi-dimensional discrete-time chaotic map is also the future research direction.The current-mode devices have good frequency gain characteristics and the bandwidth of these kind of devices are almost independent of gain, so there are no need to weigh the gain and bandwidth in the design circuit, which can improve the working frequency of the circuit. Therefore, using current mode devices to realize TRNGs have gradually become a new research direction.Recently, a TRBG based on a memristive chaotic circuit was proposed in [85]. The proposed TRBG structure used a memristive canonical Chua’s oscillator and a logistic mapping as the entropy source, while the XOR function was used for post-processing. It can be seen that TRBGs based on memristive chaotic system and multi-entropy sources will be an important development direction in the future.As future work, we are committed to improving the out bit rate, randomness and development cost of TRNG solutions and applications. There are three very important research groups, many of which are under development based on chaos of current mode devices or memristive chaotic system or multi-entropy sources, like combination of continuous-time chaotic system and discrete-time chaotic system. We are currently analysing how to study different solutions and other suggestions in these approaches.



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*Source: 2545123-2019-12-20.xml*