# Investigation on V2O5 Thin Films for Field Effect Transistor Applications

Authors: S. K. Suresh Babu; D. Jackuline Moni; D. Gracia; Amsalu Gosu Adigo
Journal: Advances in Materials Science and Engineering
 (2021)

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## Abstract

V2O5 thin films are analyzed for the substitution of SiO2 to reduce the leakage current in devices when SiO2 becomes ultrathin in submicron technology. Vanadium pentoxide (V2O5) has a high-k dielectric constant of 25 and can be replaced as a gate oxide in the field-effect transistor. V2O5 is deposited using pulsed laser deposition (PLD) in the oxygen (O2) environment at room temperature and characterized. The films surface morphology has been examined by scanning electron microscopy. The capacitance, dielectric constant, and dielectric loss are analyzed for fabricated metal oxide semiconductor (MOS) structure using Solartron SI-1260 impedance analyzer. The transfer characteristic of the fabricated device is analyzed using National Instruments NI-PXI 4110. The ION/IOFF ratio of 106 and threshold voltage (VTH) of 0.6 V is obtained.


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## Body

## 1. Introduction

Thin film technology has a vital role in electronic industries. The active thin film transistor (TFT) is a part of thin film technology which is a composition of various thin layers to form the MOSFET. These layers can be formed by a device either over silicon or a glass substrate. The replacement of silicon dioxide (SiO2) with other materials is becoming a great challenge in the community. Many developments have occurred with SiO2, but still the current leakage in a device has not been controlled in the transistor. This current leakage leads a battery to drain in minutes in the gadgets and also reduces the efficiency by producing an enormous amount of heat. So, in order to solve this problem, material with high dielectric constant (k) of more than 3.9 has to be used [1]. Pulsed laser deposition techniques have been reported to fabricate V2O5 thin films [2–7]. The paper deals with the preparation of V2O5 using pulsed laser deposition, and its performance as a gate dielectric in MOSFET.V2O5 is reported as the best rare Earth materials in terms of good thermodynamic stability and high quality interface with silicon. Hence, these materials are studied for silicon FET.


## 2. Experimental

Many deposition techniques are available in the literature for coating the thin films. Pulsed laser deposition (PLD) technique is used for its uniform and stoichiometry deposition [8–12]. Nd-YAG laser at 355 nm is used to deposit a thin film onto the substrate, and the deposition is carried out in a chamber at oxygen (O2) atmosphere [13–20]. The base pressure maintained during deposition is about 3.8 × 10−6 torr. The V2O5 (Sigma-Aldrich, 99.999%) target is placed in a sample holder which will rotate at a rate of 10 rotations per minute (rpm) during deposition. V2O5 thin films are deposited on the glass and silicon substrate in room temperature [21–25]. The confirmation of V2O5 phase angle is done using XRD. The thin films’ surface morphology is studied by scanning electron microscope (JEOL model JSM-6390), and amorphous nature of V2O5 films is found using X-ray diffractometer (Shimadzu model XRD-6000). The optical properties of the thin films were studied using ultraviolet spectroscopy (Shimadzu UV-240) and photoluminescence spectroscopy. The electrical properties were studied using an impedance analyzer (Solartron SI-1260) by varying the frequency. The transfer I–V characteristics of fabricated MOSFET were carried out with National Instrument PXI 4110.


## 3. Results and Discussion

V2O5 film (at R.T.) is deposited using PLD for gate dielectric.V2O5 thin films are deposited at room temperature and 400°C using PLD, as shown in Figure 1. These deposited films are analyzed for the selection of the best film for the gate dielectric of FET.Figure 1
V2O5 thin film deposition using PLD.


### 3.1. Structural Analysis

The structural characterization, done by interpreting the XRD peak data, gives an insight about the crystallinity and phase changing behavior of the film when annealed at different temperatures. From the XRD plot, as in Figure2, it is clearly shown that, as the temperature increases, the amorphous nature of the film is revealed. Deposition of the film is carried out at 400°C and subjected to vacuum annealing and then annealed at 400°C, wherein an increase in its crystalline nature is observed. The peak is observed at 17 (2theta value) for 400°C, and its (hkl Miller indices) values correspond to (002), and the system observed is orthorhombic in structure. The small peak is observed at 32.8 (2theta value) for the silicon substrate and verified from the JCPDS (78–0250), and its values corresponds to (111).Figure 2
XRD plot of V2O5 at room temperature.Grain size can be determined, with the Scherrer formula as(1)D=λ∗0.94βcosθ,where λ is the wavelength, θ is the Bragg angle, and β as the line broadening (Table 1).Table 1
The grain size of the thin films.
SampleD (nm)As deposited134400°c185The XRD pattern of V2O5 at room temperature, shown in Figure 2, reveals that the amorphous nature and the same film is annealed at 400°C and obtained at 2 θ at 17°. Also, the more amorphous nature of the thin film ensures a high-k dielectric value which marks its application in the fabrication of FET devices as gate dielectric.The energy dispersive X-ray spectrum is shown in Figure3. The observation of peaks further confirms the presence of vanadium dioxide in the deposited thin film.Figure 3
V2O5 EDAX spectra.


### 3.2. Surface Topography Analysis

Figure4 gives the SEM image of V2O5 at room temperature and illustrates a granular nature. The porosity increases the diffusion barrier properties and will have a high-resistance effect on the layer, which can be more suitable for the gate dielectric layer.Figure 4
V2O5 SEM image of at room temperature.


### 3.3. Film Morphology Analysis Using AFM

AFM image (Figure5) shows the small step layer deposition at maximum peak difference as 833 nm over z-axis of the deposited film. It is observed for the 20 μm × 20 μm size of the placed sample. From the histogram graph, as shown in Figure 6, it is clearly observed that very few points are noted at higher peaks and all other points are almost uniformly deposited.Figure 5
V2O5 AFM image at room temperature.Figure 6
Histogram graph of the AFM image of V2O5.Observations carried out from the AFM characterization are given in Table2. The root mean square roughness is about 125 nm and maximum peak is observed at 832 nm may be due to the ion implantation in the silicon substrate. The roughness average is noted as 96 nm which shows the smooth deposition obtained using PLD and is more suitable for the thin film transistor. The average height is 329 nm and proves the smooth deposition of the V2O5 thin film.Table 2
V2O5 parameter analysis using AFM.
RMS roughness (nm)Maximum value (nm)Average roughness (nm)Average height (nm)12583296329


### 3.4. Capacitance, Dielectric Constant, and Dielectric Loss Analysis

Solartron SI-1260 is used for the analysis of capacitance, dielectric constant, and dielectric loss of V2O5 deposited at room temperature. Metal oxide semiconductor (MOS) structure is deposited over the N-Type silicon using the PLD technique, as shown in Figure 7. Gold is coated over the deposited film as terminals for electrodes. From equation (2), the capacitance of the MOS structure is calculated and plotted in Figure 8:Figure 7
MOS structure of the V2O5 thin film.(2)C=k.ε.Ad.Figure 8
Capacitance vs. frequency analysis of the V2O5 thin film prepared at room temperature.From Figure8, it is observed that the capacitance (in microfarad) of the MOS gradually decreases with the increase in the frequency; the amorphous state of the film has a good charging value till kilo Hz. This configured film can be more suitable for the low-frequency applications:From equation (3) and (4), the obtain dielectric loss is(5)tanδ=ε″ε′,where t is thickness of the film, ω is angular frequency, Z′ is the real part of impedance, Z″ is the imaginary part of impedance, ε0 is permittivity of free space, and A is the area of the film.The dielectric constant for the deposited film is observed high at low frequency and decreases with increase in frequency, as shown in Figure9. These changes happen because of larger grain boundaries of amorphous film at the applied electric filed [23].Figure 9
Dielectric constant and dielectric loss vs. log frequency of the V2O5 thin film prepared at room temperature.(3)ε′=tωAε0.Z″Z′2+Z″2,(4)ε″=tωAε0.Z′Z′2+Z″2.With these capacitance, dielectric constant, and dielectric loss results, the V2O5 thin film deposited at room temperature is more stable at low frequency and can be a better gate dielectric layer in the replacement of conventional SiO2 in MOSFET.


## 3.1. Structural Analysis

The structural characterization, done by interpreting the XRD peak data, gives an insight about the crystallinity and phase changing behavior of the film when annealed at different temperatures. From the XRD plot, as in Figure2, it is clearly shown that, as the temperature increases, the amorphous nature of the film is revealed. Deposition of the film is carried out at 400°C and subjected to vacuum annealing and then annealed at 400°C, wherein an increase in its crystalline nature is observed. The peak is observed at 17 (2theta value) for 400°C, and its (hkl Miller indices) values correspond to (002), and the system observed is orthorhombic in structure. The small peak is observed at 32.8 (2theta value) for the silicon substrate and verified from the JCPDS (78–0250), and its values corresponds to (111).Figure 2
XRD plot of V2O5 at room temperature.Grain size can be determined, with the Scherrer formula as(1)D=λ∗0.94βcosθ,where λ is the wavelength, θ is the Bragg angle, and β as the line broadening (Table 1).Table 1
The grain size of the thin films.
SampleD (nm)As deposited134400°c185The XRD pattern of V2O5 at room temperature, shown in Figure 2, reveals that the amorphous nature and the same film is annealed at 400°C and obtained at 2 θ at 17°. Also, the more amorphous nature of the thin film ensures a high-k dielectric value which marks its application in the fabrication of FET devices as gate dielectric.The energy dispersive X-ray spectrum is shown in Figure3. The observation of peaks further confirms the presence of vanadium dioxide in the deposited thin film.Figure 3
V2O5 EDAX spectra.


## 3.2. Surface Topography Analysis

Figure4 gives the SEM image of V2O5 at room temperature and illustrates a granular nature. The porosity increases the diffusion barrier properties and will have a high-resistance effect on the layer, which can be more suitable for the gate dielectric layer.Figure 4
V2O5 SEM image of at room temperature.


## 3.3. Film Morphology Analysis Using AFM

AFM image (Figure5) shows the small step layer deposition at maximum peak difference as 833 nm over z-axis of the deposited film. It is observed for the 20 μm × 20 μm size of the placed sample. From the histogram graph, as shown in Figure 6, it is clearly observed that very few points are noted at higher peaks and all other points are almost uniformly deposited.Figure 5
V2O5 AFM image at room temperature.Figure 6
Histogram graph of the AFM image of V2O5.Observations carried out from the AFM characterization are given in Table2. The root mean square roughness is about 125 nm and maximum peak is observed at 832 nm may be due to the ion implantation in the silicon substrate. The roughness average is noted as 96 nm which shows the smooth deposition obtained using PLD and is more suitable for the thin film transistor. The average height is 329 nm and proves the smooth deposition of the V2O5 thin film.Table 2
V2O5 parameter analysis using AFM.
RMS roughness (nm)Maximum value (nm)Average roughness (nm)Average height (nm)12583296329


## 3.4. Capacitance, Dielectric Constant, and Dielectric Loss Analysis

Solartron SI-1260 is used for the analysis of capacitance, dielectric constant, and dielectric loss of V2O5 deposited at room temperature. Metal oxide semiconductor (MOS) structure is deposited over the N-Type silicon using the PLD technique, as shown in Figure 7. Gold is coated over the deposited film as terminals for electrodes. From equation (2), the capacitance of the MOS structure is calculated and plotted in Figure 8:Figure 7
MOS structure of the V2O5 thin film.(2)C=k.ε.Ad.Figure 8
Capacitance vs. frequency analysis of the V2O5 thin film prepared at room temperature.From Figure8, it is observed that the capacitance (in microfarad) of the MOS gradually decreases with the increase in the frequency; the amorphous state of the film has a good charging value till kilo Hz. This configured film can be more suitable for the low-frequency applications:From equation (3) and (4), the obtain dielectric loss is(5)tanδ=ε″ε′,where t is thickness of the film, ω is angular frequency, Z′ is the real part of impedance, Z″ is the imaginary part of impedance, ε0 is permittivity of free space, and A is the area of the film.The dielectric constant for the deposited film is observed high at low frequency and decreases with increase in frequency, as shown in Figure9. These changes happen because of larger grain boundaries of amorphous film at the applied electric filed [23].Figure 9
Dielectric constant and dielectric loss vs. log frequency of the V2O5 thin film prepared at room temperature.(3)ε′=tωAε0.Z″Z′2+Z″2,(4)ε″=tωAε0.Z′Z′2+Z″2.With these capacitance, dielectric constant, and dielectric loss results, the V2O5 thin film deposited at room temperature is more stable at low frequency and can be a better gate dielectric layer in the replacement of conventional SiO2 in MOSFET.


## 4. MOSFET Fabrication

Figure10 shows the fabrication steps of V2O5 thin film gate dielectric-based Si-MOSFET. In this device, P-type silicon is used as the channel and also as a base layer for the proposed device. It is well cleaned and processed for the device fabrication. Inside the PLD chamber, the prepared V2O5 pellet is fixed as the target. With prepared stainless steel (SS) mask, the V2O5 thin film is deposited at 330 nm at room temperature as a gate dielectric layer. The thickness is measured using AFM. By using sputtering as the source, drain and gate are deposited with gold (Au) with the designed SS-mask.Figure 10
Fabrication steps involved in the V2O5 film gate dielectric-based Si-MOSFET.The electrical characterization of fabricated MOSFET is carried out using National Instruments NI-4100. With the designed LabVIEW platform, the output and transfer characteristics are analyzed. Figure11 shows the output characteristics of V2O5 gate dielectric-based Si-MOSFET.Figure 11
Output characteristics of V2O5 thin film gate dielectric of Si-MOSFET.In output characteristics, VDS is varied between 0 and 20 Volts with various constant gate voltage (0, 2.5 V, and 5 V), and the corresponding drain current ID is noted. Kink in the I–V characteristics is because of the sudden rise in the applied voltage (randomly set by the program), which causes this effect.From Figure12, the threshold voltage VTH is found to be 0.6 V [26–29]. The ION/IOFF ratio of fabricated MOSFET is calculated from the transfer characteristics results which are shown in Figure 13. The ION/IOFF current ratio can be calculated by plotting the obtained drain current in the log scale; by measuring the maximum point in graph to minimum point of drain current gives the value of the ION/IOFF current ratio as 106.Figure 12
Transfer characteristics of V2O5 thin film gate dielectric of Si-MOSFET (square root of drain current vs. VGS).Figure 13
Transfer characteristics of V2O5 thin film gate dielectric of Si-MOSFET (log. of drain current vs. VGS).The results show that the fabricated MOSFET has less leakage current from the observed ION/IOFF current and V2O5 thin film is more suitable for the gate dielectric of MOSFET.


## 5. Conclusion

The various characteristics of V2O5 is analyzed and reported. The replacement of SiO2 dielectric in MOSFET is due to its large leakage current in submicron technology; the MOS structure of the V2O5 thin film is studied, and its capacitance, dielectric constant, and dielectric loss at low frequency are analyzed. The results revealed that the V2O5 thin film deposited at room temperature can be used as the gate dielectric of MOSFET. The Si-MOSFET is fabricated with V2O5 thin film as the gate dielectric by using PLD. It is also observed that the good ION/IOFF current ratio is 106 and threshold voltage (VTH) is 0.6 V. This ION/IOFF ratio shows less leakage current with stable threshold voltage, and henceforth, the V2O5 thin film can be a good replacement of SiO2 in MOSFET [30–36].



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