# Meta-Algorithms for Scheduling a Chain of Coarse-Grained Tasks on an Array of Reconfigurable FPGAs

Authors: Dinesh P. Mehta; Carl Shetters; Donald W. Bouldin
Journal: VLSI Design
 (2013)

---

## Abstract

This paper considers the problem of scheduling a chain ofn coarse-grained tasks on
a linear array of k reconfigurable FPGAs with the objective of primarily minimizing
reconfiguration time. A high-level meta-algorithm along with two detailed meta-algorithms
(GPRM and SPRM) that support a wide range of problem formulations and cost functions
is presented. GPRM, the more general of the two schemes, reduces the problem to
computing a shortest path in a DAG; SPRM, the less general scheme, employs dynamic
programming. Both meta algorithms are linear in n and compute optimal solutions.
GPRM can be exponential in k but is nevertheless practical because k is typically a small
constant. The deterministic quality of this meta algorithm and the guarantee of optimal
solutions for all of the formulations discussed make this approach a powerful alternative
to other metatechniques such as simulated annealing and genetic algorithms.


---

## Body

## 1. Introduction

In this paper, we consider the problem of scheduling a chain of coarse-grained tasks on a linear array of reconfigurable FPGAs. This scheduling problem arose in the development of the CHAMPION software environment for mapping image processing applications onto an adaptive computing system (ACS). CHAMPION [1], which was developed at the University of Tennessee, maps a high-level data-flow diagram developed using the Cantata graphical programming software [2, 3] onto an ACS. CHAMPION maps the workspace to a netlist and performs data width matching and synchronization, followed by partitioning. Each resulting subnet-list is translated into structural VHDL which is merged with VHDL files specifying the ACS architecture and synthesized using commercial synthesis tools. The partitioning step which is described in detail in [4] takes as input a directed acyclic graph (DAG) and computes a partition P={P1,P2,…,Pn} such that each Pi can be implemented on a single target FPGA. The partition algorithm must consider (1) the capacity of the partition (2) the number of I/O pins, and (3) the limit on RAM access modules. If n is greater than the number of FPGAs on board (k), multiple configurations of the FPGA (i.e., temporal partitioning) will be necessary. To reduce design complexity, a design decision was made to use a constrained configuration of the boards such that all signals pass in one direction along the array of FPGAs. The signal flow must accordingly be unidirectional from P1 to Pn on the task chain. The input DAG can be linearized easily using topological sorting. However, the partitioning step must maintain the unidirectional signal flow when it allocates multiple DAG nodes to individual tasks on the task chain. The DARPA image processing application was successfully mapped onto the Wildforce-XL, the SLAAC, and MSP FPGA boards. Examples of commercial boards with multiple state-of-the-art Xilinx and Altera FPGAs can be found at  http://www.dinigroup.com/new/products.php. The number of FPGAs on these boards is typically six or less although the DN7020K10 and DNDPBS327 boards have 20 and 27 FPGAs, respectively.The result of the partitioning algorithm described above (and the input to the formulations described in this paper) is a directed chain of coarse-grained tasks such that exactly one task fits on an FPGA. The objective of this paper is to design scheduling meta-algorithms that optimally map tasks to FPGAs under some measure of cost. Our two algorithmic schemes are general purpose reconfiguration meta-algorithm (GPRM) and the special purpose reconfiguration meta-algorithm (SPRM). Both are meta-algorithms in that they can each address several design scenarios. (The meta-algorithm concept is discussed in more detail in Section2.)Our focus in this paper is primarily on minimizing reconfiguration time (although it is possible to incorporate execution time into our cost formulations) because they typically dominate execution times by several orders of magnitude. For example, Natarajan et al. [1] reported that the hardware execution time to process one image using an ACS implementation of ATR, an automatic target recognition algorithm, was 33 milliseconds, as compared to nearly seven seconds needed for the entire execution. Gajjala Purna and Bhatia [5] reported that the hardware execution time for a set of four applications was on the order of tens of microseconds, while a single reconfiguration requires 242 milliseconds on the RACE architecture. More recently, Birla and Vikram [6] reported that an integral image computation was executed in 12.36 μs with reconfiguration times ranging from 3.309 to 52.944 ms (depending on the configuration clock frequency). A feature extraction and classification computation had an execution time of 8.66 μs with reconfiguration times ranging from 3.392 to 54.268 ms.Although the original motivation for this work was to configure a board with several FPGAs, the underlying abstraction employed by our meta-algorithms can also, in principle, capture partial reconfiguration that allows “specific regions of the FPGA to be reprogrammed with new functionality while applications continue to be run in the remainder of the device.” [7]. The performance of partial reconfiguration continues to be an active area of research, with recent work being focused on developing cost models that characterize reconfiguration times accurately [8–10]. Accurate cost models provide reconfiguration time data that is vital to scheduling algorithms such as SPRM and GPRM presented in this paper.Section3 formulates the problem and relates it to existing research. In Sections 4 and 5, respectively, we present the SPRM and GPRM meta-algorithms along with several specific instantiations. Section 6 combines the individual formulations into detailed SPRM and GPRM meta-algorithms. Section 7 contains experimental results and Section 8 concludes the paper.


## 2. New Algorithmic Techniques Used

A meta-algorithm is a high-level algorithmic strategy that is somewhat independent of the detailed algorithms used for solving precise instantiations of the problem. One may view techniques such as simulated annealing and genetic algorithms as meta-algorithms. These techniques have to be customized to the precise problem being solved. For example, simulated annealing may be customized by instantiating the concept ofstate, cost, and move for a given problem. Because of their stochastic nature (the use of randomness is an integral component of these techniques), simulated annealing and genetic algorithms have been widely used to solve a very large and diverse set of problems. However, the stochastic nature of these techniques leads to some difficulties in their deployment: (1) experimental results are not guaranteed to be reproducible and (2) the selection of parameters (such as the cooling factor in simulated annealing) has an appreciable impact on the runtime of the algorithm and the quality of solution. Although there are guidelines and best practices on choosing parameters, the practitioner does not know a priori what parameters will work well; considerable effort has to be expended in trial-and-error. It is also possible that different parameters are needed for different inputs.The idea of a meta-algorithm can also refer to high-level strategies for aspecific problem such as hierarchical web caching [11]: this paper experiments with challenging the high-level implicit strategy used in hierarchical caching that “a hit for a document at an l-level cache leads to the caching of the document in all intermediate caches (levels l-1,…,1) on the path towards the leaf cache that received the initial request.” These alternative strategies for being more selective in choosing the caches that store a local copy of the requested document are considered to be meta-algorithms because they operate independently of the actual replacement algorithm running in each individual cache.Another scenario where meta-algorithms can be useful is when there are several detailed algorithms available to solve different variations of a problem. In this case, the meta-algorithm provides a procedure that navigates the available options and chooses which detailed algorithm to deploy. A simple example of this occurs when a difficult problem might be solved using an exhaustive algorithm for small input sizes (e.g.,n<20) and a heuristic or an approximation algorithm for large input sizes (e.g., n≥20). In this case, the (simple) meta-algorithm chooses which detailed algorithm to deploy. If a better heuristic or approximation algorithm is discovered for n≥20, the original one can be replaced without impacting the meta-algorithm. This approach has been used to assist a user to automatically select most suited algorithms during data mining model building process [12].To the best of our knowledge, the use of meta-algorithms in VLSI design automation (and in configuration minimization problems, in particular) is novel.There are two respects in which we describe meta-algorithms for this problem.(1)
This paper describes two algorithms (SPRM and GPRM) to minimize reconfiguration time of a sequence of coarse-grained tasks that are to be executed in a linear array of FPGAs. SPRM is based on dynamic programming while GPRM is based on a shortest-paths formulation. SPRM is faster but is concerned with a special case of the problem (where cost is a function of adjacent tasks in the chain), while GPRM is concerned with the general case (where cost is a function of all tasks in adjacent configurations). The SPRM and GPRM methods are themselves meta-algorithms that can be customized to address several detailed problem formulations and cost specifications. These formulations include reconfiguration time minimization, dynamic task generation, repeated and similar tasks, implementation libraries, and limited cycles, all of which are discussed later.(2)
Along with Ghiasi et al. [13] and Bondalapati and Prasanna [14], SPRM and GPRM represent a novel use of these techniques in the configuration of coarse-grained tasks with the goal of minimizing reconfiguration time on reconfigurable logic. Following the approach of Fan and Lei [12], we present a framework within which these algorithmic techniques can be deployed. We present a metaheuristic (Algorithm 1) that provides a high-level framework for choosing an appropriate algorithm based on the task, implementation, and cost models being considered.Algorithm 1:Metaheuristic that provides a high-level framework for choosing an appropriate algorithm based on the task, implementation, and cost models being considered.
INPUT: Task Model T, Implementation Model I, Cost Model C
//I refers to the configuration of the underlying FPGA hardware
(1)if (T is a Dag and I is unstructured)
(2)then Use optimal LIU-based algorithm [13]
(3)else if (T is a Chain or a Loop and I is a single unit/unstructured)
(4)then Use Dynamic Programming [14]
(5)else if (T is a Chain and I is a Linear Array)
(6)then if (C is a function of adjacent tasks)
(7)   Use SPRM
(8)else // C is a function of all tasks in a configuration
(9) Use GPRM.
end


## 3. Previous Work and Problem Formulation

### 3.1. Previous Work

Some of the key differences between the work presented in this paper and early dynamic reconfiguration algorithms [5, 15–19] are that (1) our tasks are more coarse-grained, whereas the previous algorithms operate at the netlist level. (2) We assume that an array of FPGAs is available, whereas the previous work assumes that there is a single dynamically reconfigurable FPGA. (3) Finally, we assume that the application represented by a directed acyclic graph (DAG) of tasks has been converted into a linear chain of tasks in a precomputation step. The mapping of a DAG to a linear chain and the rationale and implications of working with linear chains are discussed in the next subsection.In addition, there are two relatively recent papers that consider coarse-grained tasks. However, neither of these allows for a linear array of FPGAs. We describe their work in greater detail below.Bondalapati and Prasanna [14] consider a formulation where a chain of tasks is implemented on a single configurable logic unit. A single task is executed on the configurable logic unit at a time. When its execution is complete, the logic unit is reconfigured to execute the next task in the list and so on. Each task can be implemented using multiple configurations. The choice of configurations for consecutive tasks affects the reconfiguration time. A dynamic programming algorithm optimizes the total reconfiguration time in O(nc2) time, where n is the number of tasks and c is the number of configurations for each task. Our formulation fundamentally differs from theirs in that our chain of tasks will be implemented on a linear pipelined array of k configurable logic units. Indeed, their dynamic programming solution may be viewed as a special case of our shortest-paths solution to our GPRM formulation when k=1. (We note that Bondalapati and Prasanna further consider the case where their chain of tasks is contained in a loop requiring repeated execution and unrolling, which is outside the scope of our work.)Ghiasi et al. [13] consider a formulation where a directed acyclic graph (DAG) of tasks has to be scheduled and executed on partially reconfigurable hardware with capacity k; that is, at most k tasks may be allocated at a time. Different tasks in the DAG may be identical, so savings in reconfiguration time may be obtained by caching a task in the partially reconfigurable hardware (PRH). Their algorithms are based on extending solutions to paging problems. This is possible because, in their formulation, any task can be placed in any of theklocations in the PRH, which gives them much more flexibility. Our tasks must be placed on a linear pipelined array in the order in which they appear in the chain to facilitate signal flow. Further, they do not address some of the formulations addressed in the paper (such as dynamic task generation and implementation libraries).


### 3.2. Discussion of Design Context

In this section we discuss the rationale and implications for the following design decisions.(1)
Model of computation: the DAG has traditionally been used as a general model of computation in the literature. As described earlier, our approach is to preprocess the DAG, transforming it into a linear chain of tasks and then applying our algorithms to the task chain. In principle, this preprocessing can be achieved by performing a topological sort on the DAG. Edges connecting vertices that are not adjacent in the chain can be accommodated by including simple tasks in the intermediate chain vertices that facilitate the passing-through of the data. The existence of many such edges will add overhead, possibly making this approach impractical. Other considerations during this transformation are discussed in [4].(2)
Implementation model: FPGA boards contain a routing switch which permits a portion of the I/O of any FPGA to be interconnected to a portion of the I/O of any other FPGA on the board. In this work, we are using a constrained configuration of the boards such that signals flow in one direction along the array of FPGAs.The rationale for these decisions is that many applications (e.g., image processing) can be naturally decomposed into a linear sequence of steps which map directly into a chain. For these applications, the linear flow of data results in communication paths between all of the FPGAs that are identical and predictable. This greatly simplifies system design and makes it more amenable to automation.Some of the implications and consequences of these decisions are listed below.(1)
The traditional advantage of using a DAG computation model over a linear chain is that it permits tasks to be executed in parallel on different processors. In current FPGA systems, the response time is dominated by FPGA reconfiguration delays and not computation time [1, 5, 6]. This, along with the limited number of FPGAs available on a board, minimizes the traditional advantage of working directly with a DAG. Note, however, that our approach does not preclude the use of fine-grained parallelism in the implementation of a task. In other words, the implementation of that task in an FPGA could require several control logic blocks (CLBs) to execute in parallel. In the event that computation time is significant, our approach permits reconfigurating earlier FPGAs in parallel with ongoing computations in later FPGAs [20] and also permits reconfiguring FPGAs in parallel.(2)
Since FPGA technology results in fast execution times for complex algorithms, it is important to ensure that the scheduling algorithm itself does not consume an excessive amount of time. An advantage of linear chains is that scheduling algorithms are significantly faster than those for DAGs.(3)
A linear chain implementation of an algorithm makes it more amenable to pipelining. Thus, several images can be pipelined through an FPGA board configuration and the partial results stored. The board can then be reconfigured and the partial results pipelined through a new board configuration. This amortizes reconfiguration time over several images.


### 3.3. Consolidated Problem Formulation

As mentioned previously, the meta-algorithms described here capture several scenarios. Each such scenario will require a subtly different problem formulation. We begin by presenting two abstracted formulations that capture the essence of the problems solved by SPRM and GPRM: we describe (1) input, (2) output, and (3) an abstracted cost function.Input is a chain of tasks labeled 1 through n as shown in Figure 1 and an integer k denoting the number of FPGAs on a board.Figure 1
Input task chain.Output is an optimal assignment of each task i to a temporal board configuration and an FPGA denoted by (Bi,Fi). Bi is an integer between 1 and t (the total number of board configurations) that denotes the temporal board configuration that Task i is assigned to. Fi is an integer between 1 and k (the number of FPGAs on the board) that denotes the FPGA that Task i is assigned to. The output may be visualized as the two-dimensional array R shown in Algorithm 1. In this example, B5=2 and F5=3 because Task 5 is assigned to FPGA 3 in Board Configuration 2. Note that some entries may be left blank (e.g., (1, 4) and (2, 1) in Table 1) in the optimal solution found by our algorithms. As we will see later, this could happen as a result of scheduling repeated tasks on the same FPGA in consecutive board configurations in order to minimize reconfiguration time.Table 1
Two-dimensional arrayR representing the assignment of tasks to FPGAs and board configurations. Each row represents a board configuration and each column represents an FPGA. (Thus, Task 5 is assigned to FPGA 3 in Configuration 2.) Note that tasks are listed in row major order but are not necessarily consecutive. Note also that t the number of temporal board configurations is not known a priori.
Board config no.
FPGAs on board
1
2
3
4
1
1
2
3
2
4
5
6
3
7
8
9
10
⋮
⋮
t
n
-
1
nLinear Task Order Constraint. Any pair of tasks i and j with i<j must satisfy the following constraints: either Bi<Bj (i.e., task i appears in an earlier board configuration than task j) or Bi=Bj and Fi<Fj (i.e., tasks i and j appear in the same board configuration but i is assigned to an FPGA that appears earlier in the pipeline than the FPGA allocated to j).We have not yet defined optimality. We consider two cost scenarios that lead to a fundamental distinction between the SPRM and GPRM strategies.(1)
The cost to reconfigure from board Configurationc to board Configuration c+1 is purely a function f of the last task denoted Lc in Configuration c (highest numbered task appearing in Row c of the output table) and the first task in Configuration c+1 (lowest numbered task appearing in Row c+1 of the output table), which is Lc+1. In the example, the cost to reconfigure from Configuration 1 to Configuration 2 would be f(3,4) because Task 3 is the last task in Configuration 1 and Task 4 is the first task in Configuration 2. In this restricted model, the other tasks allocated to the configurations such as Task 2 in Configuration 1 and Task 5 in Configuration 2 are assumed to have no bearing on the cost. This scenario arises when reconfiguration time is dominated by the time needed to store intermediate results between two adjacent configurations.The total cost is formally defined as ∑c=1t-1‍f(Lc,Lc+1). The SPRM scheme computes an optimal solution for this scenario.(2)
Cost to reconfigure from Configurationc to Configuration c+1 is a function g of  all of the tasks assigned to Configurations c and c+1. This captures the scenario when CLB reconfiguration dominates reconfiguration time. In this scenario, repeated tasks placed on the same FPGA in consecutive configurations result in significant savings.The total cost is formally defined as ∑c=1t-1‍g(R[c,·],R[c+1,·]), where R[c,·] denotes all tasks in Configuration c (i.e., Row c in the output table R). Note that this scenario subsumes the SPRM scenario. The GPRM scheme is used to compute an optimal solution for this more general scenario.


## 3.1. Previous Work

Some of the key differences between the work presented in this paper and early dynamic reconfiguration algorithms [5, 15–19] are that (1) our tasks are more coarse-grained, whereas the previous algorithms operate at the netlist level. (2) We assume that an array of FPGAs is available, whereas the previous work assumes that there is a single dynamically reconfigurable FPGA. (3) Finally, we assume that the application represented by a directed acyclic graph (DAG) of tasks has been converted into a linear chain of tasks in a precomputation step. The mapping of a DAG to a linear chain and the rationale and implications of working with linear chains are discussed in the next subsection.In addition, there are two relatively recent papers that consider coarse-grained tasks. However, neither of these allows for a linear array of FPGAs. We describe their work in greater detail below.Bondalapati and Prasanna [14] consider a formulation where a chain of tasks is implemented on a single configurable logic unit. A single task is executed on the configurable logic unit at a time. When its execution is complete, the logic unit is reconfigured to execute the next task in the list and so on. Each task can be implemented using multiple configurations. The choice of configurations for consecutive tasks affects the reconfiguration time. A dynamic programming algorithm optimizes the total reconfiguration time in O(nc2) time, where n is the number of tasks and c is the number of configurations for each task. Our formulation fundamentally differs from theirs in that our chain of tasks will be implemented on a linear pipelined array of k configurable logic units. Indeed, their dynamic programming solution may be viewed as a special case of our shortest-paths solution to our GPRM formulation when k=1. (We note that Bondalapati and Prasanna further consider the case where their chain of tasks is contained in a loop requiring repeated execution and unrolling, which is outside the scope of our work.)Ghiasi et al. [13] consider a formulation where a directed acyclic graph (DAG) of tasks has to be scheduled and executed on partially reconfigurable hardware with capacity k; that is, at most k tasks may be allocated at a time. Different tasks in the DAG may be identical, so savings in reconfiguration time may be obtained by caching a task in the partially reconfigurable hardware (PRH). Their algorithms are based on extending solutions to paging problems. This is possible because, in their formulation, any task can be placed in any of theklocations in the PRH, which gives them much more flexibility. Our tasks must be placed on a linear pipelined array in the order in which they appear in the chain to facilitate signal flow. Further, they do not address some of the formulations addressed in the paper (such as dynamic task generation and implementation libraries).


## 3.2. Discussion of Design Context

In this section we discuss the rationale and implications for the following design decisions.(1)
Model of computation: the DAG has traditionally been used as a general model of computation in the literature. As described earlier, our approach is to preprocess the DAG, transforming it into a linear chain of tasks and then applying our algorithms to the task chain. In principle, this preprocessing can be achieved by performing a topological sort on the DAG. Edges connecting vertices that are not adjacent in the chain can be accommodated by including simple tasks in the intermediate chain vertices that facilitate the passing-through of the data. The existence of many such edges will add overhead, possibly making this approach impractical. Other considerations during this transformation are discussed in [4].(2)
Implementation model: FPGA boards contain a routing switch which permits a portion of the I/O of any FPGA to be interconnected to a portion of the I/O of any other FPGA on the board. In this work, we are using a constrained configuration of the boards such that signals flow in one direction along the array of FPGAs.The rationale for these decisions is that many applications (e.g., image processing) can be naturally decomposed into a linear sequence of steps which map directly into a chain. For these applications, the linear flow of data results in communication paths between all of the FPGAs that are identical and predictable. This greatly simplifies system design and makes it more amenable to automation.Some of the implications and consequences of these decisions are listed below.(1)
The traditional advantage of using a DAG computation model over a linear chain is that it permits tasks to be executed in parallel on different processors. In current FPGA systems, the response time is dominated by FPGA reconfiguration delays and not computation time [1, 5, 6]. This, along with the limited number of FPGAs available on a board, minimizes the traditional advantage of working directly with a DAG. Note, however, that our approach does not preclude the use of fine-grained parallelism in the implementation of a task. In other words, the implementation of that task in an FPGA could require several control logic blocks (CLBs) to execute in parallel. In the event that computation time is significant, our approach permits reconfigurating earlier FPGAs in parallel with ongoing computations in later FPGAs [20] and also permits reconfiguring FPGAs in parallel.(2)
Since FPGA technology results in fast execution times for complex algorithms, it is important to ensure that the scheduling algorithm itself does not consume an excessive amount of time. An advantage of linear chains is that scheduling algorithms are significantly faster than those for DAGs.(3)
A linear chain implementation of an algorithm makes it more amenable to pipelining. Thus, several images can be pipelined through an FPGA board configuration and the partial results stored. The board can then be reconfigured and the partial results pipelined through a new board configuration. This amortizes reconfiguration time over several images.


## 3.3. Consolidated Problem Formulation

As mentioned previously, the meta-algorithms described here capture several scenarios. Each such scenario will require a subtly different problem formulation. We begin by presenting two abstracted formulations that capture the essence of the problems solved by SPRM and GPRM: we describe (1) input, (2) output, and (3) an abstracted cost function.Input is a chain of tasks labeled 1 through n as shown in Figure 1 and an integer k denoting the number of FPGAs on a board.Figure 1
Input task chain.Output is an optimal assignment of each task i to a temporal board configuration and an FPGA denoted by (Bi,Fi). Bi is an integer between 1 and t (the total number of board configurations) that denotes the temporal board configuration that Task i is assigned to. Fi is an integer between 1 and k (the number of FPGAs on the board) that denotes the FPGA that Task i is assigned to. The output may be visualized as the two-dimensional array R shown in Algorithm 1. In this example, B5=2 and F5=3 because Task 5 is assigned to FPGA 3 in Board Configuration 2. Note that some entries may be left blank (e.g., (1, 4) and (2, 1) in Table 1) in the optimal solution found by our algorithms. As we will see later, this could happen as a result of scheduling repeated tasks on the same FPGA in consecutive board configurations in order to minimize reconfiguration time.Table 1
Two-dimensional arrayR representing the assignment of tasks to FPGAs and board configurations. Each row represents a board configuration and each column represents an FPGA. (Thus, Task 5 is assigned to FPGA 3 in Configuration 2.) Note that tasks are listed in row major order but are not necessarily consecutive. Note also that t the number of temporal board configurations is not known a priori.
Board config no.
FPGAs on board
1
2
3
4
1
1
2
3
2
4
5
6
3
7
8
9
10
⋮
⋮
t
n
-
1
nLinear Task Order Constraint. Any pair of tasks i and j with i<j must satisfy the following constraints: either Bi<Bj (i.e., task i appears in an earlier board configuration than task j) or Bi=Bj and Fi<Fj (i.e., tasks i and j appear in the same board configuration but i is assigned to an FPGA that appears earlier in the pipeline than the FPGA allocated to j).We have not yet defined optimality. We consider two cost scenarios that lead to a fundamental distinction between the SPRM and GPRM strategies.(1)
The cost to reconfigure from board Configurationc to board Configuration c+1 is purely a function f of the last task denoted Lc in Configuration c (highest numbered task appearing in Row c of the output table) and the first task in Configuration c+1 (lowest numbered task appearing in Row c+1 of the output table), which is Lc+1. In the example, the cost to reconfigure from Configuration 1 to Configuration 2 would be f(3,4) because Task 3 is the last task in Configuration 1 and Task 4 is the first task in Configuration 2. In this restricted model, the other tasks allocated to the configurations such as Task 2 in Configuration 1 and Task 5 in Configuration 2 are assumed to have no bearing on the cost. This scenario arises when reconfiguration time is dominated by the time needed to store intermediate results between two adjacent configurations.The total cost is formally defined as ∑c=1t-1‍f(Lc,Lc+1). The SPRM scheme computes an optimal solution for this scenario.(2)
Cost to reconfigure from Configurationc to Configuration c+1 is a function g of  all of the tasks assigned to Configurations c and c+1. This captures the scenario when CLB reconfiguration dominates reconfiguration time. In this scenario, repeated tasks placed on the same FPGA in consecutive configurations result in significant savings.The total cost is formally defined as ∑c=1t-1‍g(R[c,·],R[c+1,·]), where R[c,·] denotes all tasks in Configuration c (i.e., Row c in the output table R). Note that this scenario subsumes the SPRM scenario. The GPRM scheme is used to compute an optimal solution for this more general scenario.


## 4. SPRM

We present three formulations of the SPRM problem. The first is a basic formulation, the second permits dynamic task generation, and the third permits limited use of bidirectional edges and cycles. The three scenarios are quite different, but all of them share the property that the problem is fully specified by specifying costs between adjacent tasks in the chain.


### 4.1. SPRM Formulation 1: Basic

Given a chain ofn tasks and a cost Ci+1=f(i,i+1) of separating tasks i and i+1 into different configurations, compute a set of cuts of minimum total cost such that each configuration (represented by the tasks between adjacent cuts) has k or less tasks.Application. In a chain of tasks, data is propagated along the pipeline from task i to the next task i+1. When these tasks belong to FPGAs in the same board configuration, the transfer can take place directly. However, when they are not in the same board configuration, the data must be stored in memory by task i and read from memory by task i+1 after the board is reconfigured so that task i+1 may proceed with its computation. Ci+1 denotes this cost and could be substantial in case the data consists of images or video.Consider the following simple example withn=14 and k=4. The costs Ci associated with each pair of consecutive tasks are shown in Figure 2.Figure 2
Initial task list with reconfiguration costs.The optimal solution consists of making cuts at edges 2, 6, and 10 with costs 3, 50, and 5, respectively, resulting in a cost of 58. The cuts are shown in Figure3.Figure 3
Task list with optimum cuts.The dynamic programming algorithm is described below. We employ two one-dimensional arrayscost and firstCut of size n (where n is the number of tasks in the chain). The element cost[l] will, upon completion of the algorithm, contain the cost of an optimal set of cuts separating the tasks in the subchain from l to n-1. Note that this value will be zero if n-l≤k, since no cuts are required to separate a chain consisting of k or less tasks. The element firstCut[l] will contain the location of the first cut in the subchain from l to n-1 in an optimal solution. The algorithm is outlined in Algorithm 2.Algorithm 2:SPRM (Straight-Cut) algorithm.
COST(n)
{Compute minimum cost using dynamic programming}
(1)forl=n-1down to0do// n is number of tasks in chain
(2)cost[l]=∞
(3)if(n-l)≤kthen//Base case
(4)cost[l]=0
(5)firstCut[l]=n
(6)else// General case
(7)fori in [0,k-1]do// Try k cuts, determine which is best
(8)tempCost=cost[l+i+1]+Cl+i+1
(9)iftempCost<cost[l]then
(10)cost[l]=tempCost
(11)firstCut[l]=l+i+1
endThe elements of thecost and firstCut arrays are computed in reverse order. Lines 3 and 4 consider the case where the task chain from l to n-1 contains k or less tasks, whereas lines 5–9 consider the general case. The general case is addressed by considering all the ways in which the first cut in the subchain starting at l can be made. For each possibility, we use the value of cost [l+i+1] that was computed in a previous iteration and Cl+i+1.Thecost array upon completion of execution of the algorithm on the input of Figure 2 is shown in Table 2 and the firstCut  array in Table 3.Table 2
Contents of arraycost on completion of algorithm.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
58
58
55
55
55
55
5
5
5
5
0
0
0
0Table 3
Contents of arrayfirst cut on completion of algorithm.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
2
2
6
6
6
6
10
10
10
10
14
14
14
14Theorem 1.
Algorithm COST (Algorithm2) computes an optimal solution to SPRM Formulation 1.Proof.
Clearly, the algorithm returns the correct value (zero) whenn-l≤k, since all the tasks can be accommodated in one configuration and there is no need to incur reconfiguration costs. If n-l>k, it must be the case that at least one cut is needed. Our dynamic programming solution considers all k possibilities for the leftmost cut and uses previously computed optimal cost values for the subchains.Theorem 2.
Algorithm COST has time complexityO(nlogk) and space complexity O(n).Proof.
There areO(n) elements in the cost array, each of which is computed in O(k) time. This results in a complexity of O(nk). We note that this can be improved to O(nlogk) as follows: observe that in order to compute any element cost[l], we obtain the minimum from a set of k quantities of the form cost[l+i+1]+Cl+i+1. Also, observe that in the computation of cost[l-1], k-1 of these quantities are identical to those used for cost[k]. Thus, it is possible to use a min-heap data structure in combination with a queue of pointers to elements in the min-heap to (1) compute the minimum, (2) delete one element, and (3) insert one element per iteration. Each of these can be accomplished in O(logk) time, giving the result.The algorithm to output cuts is given in Algorithm3.Algorithm 3:Output-Cuts algorithm.
CUTS(n) // The traceback step
(1)next = 0
(2)whilenext<ndo
(3)outputfirstCut[next]
(4)next=firstCut[next]
end


### 4.2. SPRM Formulation 2: Dynamic Task Generation

The dynamic task generation problem is a modification of the formulation described above. As before, the input is a linear chain of tasks. However, in addition to theCi+1 costs associated with each edge, a boolean parameter is also associated with each node. If this parameter is set to true a cut on either side of this node, this will require the creation of an additional node. This additional node will occupy one of the available FPGAs and therefore directly affects the calculation of the optimum cost and cut-set in the algorithm.Application. When a task is placed in the first FPGA in a configuration, it will need to read intermediate data from memory. Similarly, when a task is placed in the last FPGA in a configuration, it will need to write intermediate data to memory. This additional read/write functionality must be implemented on the FPGA. However, if the additional logic required does not fit on the FPGA or if the existing functionality on the FPGA already contains memory accesses and more memory accesses are not permitted by the architecture, an additional task must be created and accommodated on another FPGA.We use the same example as before, except that along with the reconfiguration cost there is a boolean flag associated with each vertex (Figure4).Figure 4
Initial task list with reconfiguration costs and boolean flag.Our algorithm obtains cuts at 3, 5, 6, and 10 of costs 10, 4, 50, and 5 resulting in an optimal cost of 69. Note that the addition of extra task nodes affects the cut location and therefore the overall cost. The optimum cuts would break the task list as can be seen in Figure5.Figure 5
Task list with optimum cuts and additional node locations.The cost function, which is the main modification to the Straight-Cut algorithm, is displayed in Algorithm4.Algorithm 4:SPRM (dynamic-node generation) algorithm.
COST(n)
{Compute minimum cost using dynamic programming}
(1)forl=n-1 down to 0do// n is number of tasks in chain
(2)cost[l]=∞
(3)if(n-l)≤k-b[l]-b[n-1]then//Base case
(4)cost[l]=0
(5)firstCut[l]=n
(6)else// General case
(7)fori in [0,k-1-b[l]]do// try all cuts, determine best one
(8)ifi<k-1-b[l]orb[l+i]=0then// checks whether additional task needed
(9)tempCost=cost[l+i+1]+Cl+i+1
(10)iftempCost<cost[l]then
(11)cost[l]=tempCost
(12)firstCut[l]=l+i+1
endThe main difference between the dynamic task and the straight cut versions is that configurations are analyzed to determine how many of their end-nodes are marked (i.e., an additional node is required if the cut is at this location). This quantity (0, 1, or 2) is subtracted from the possible number of FPGAs available for a configuration.


### 4.3. SPRM Formulation 3: Linear Chain with Limited Cycles

Recall that the partitioning algorithm of [4] partitions a DAG into a chain of n tasks such that the signal flows from left to right. However, this may not be possible or advantageous in some applications and may result in bidirectional edges or cycles as shown in Figure 6.Allocating multiple DAG nodes to a task can lead to a bidirectional edge: (a) original DAG, (b) allocation of DAG nodes to FPGA tasks, (c) bidirectional edge resulting from node merging.
(a)
(b)
(c)The interconnect on FPGA boards can be configured to permit bidirectional or cyclic signal flow, so the only limitation is that all tasks involved in this type of signal flow must be placed in the same board configuration. (Otherwise, a task in an earlier board configuration will need data produced by a task in the future.) Although SPRM is designed for a linear chain with a unidirectional signal flow, it can be modified for situations with alimited number of bidirectional edges or cycles. This constraint can be accommodated by assigning a large cost M to each bidirectional edge and to all edges in a cycle as shown in Figure 7. This will discourage our dynamic programming algorithm from cutting these edges forcing the algorithm to place the relevant tasks on the same board, provided this is feasible.(a) task chain with one cycle and one bidirectional edge. (b) Cost M assigned to each bidirectional or cycle edge.
(a)
(b)


## 4.1. SPRM Formulation 1: Basic

Given a chain ofn tasks and a cost Ci+1=f(i,i+1) of separating tasks i and i+1 into different configurations, compute a set of cuts of minimum total cost such that each configuration (represented by the tasks between adjacent cuts) has k or less tasks.Application. In a chain of tasks, data is propagated along the pipeline from task i to the next task i+1. When these tasks belong to FPGAs in the same board configuration, the transfer can take place directly. However, when they are not in the same board configuration, the data must be stored in memory by task i and read from memory by task i+1 after the board is reconfigured so that task i+1 may proceed with its computation. Ci+1 denotes this cost and could be substantial in case the data consists of images or video.Consider the following simple example withn=14 and k=4. The costs Ci associated with each pair of consecutive tasks are shown in Figure 2.Figure 2
Initial task list with reconfiguration costs.The optimal solution consists of making cuts at edges 2, 6, and 10 with costs 3, 50, and 5, respectively, resulting in a cost of 58. The cuts are shown in Figure3.Figure 3
Task list with optimum cuts.The dynamic programming algorithm is described below. We employ two one-dimensional arrayscost and firstCut of size n (where n is the number of tasks in the chain). The element cost[l] will, upon completion of the algorithm, contain the cost of an optimal set of cuts separating the tasks in the subchain from l to n-1. Note that this value will be zero if n-l≤k, since no cuts are required to separate a chain consisting of k or less tasks. The element firstCut[l] will contain the location of the first cut in the subchain from l to n-1 in an optimal solution. The algorithm is outlined in Algorithm 2.Algorithm 2:SPRM (Straight-Cut) algorithm.
COST(n)
{Compute minimum cost using dynamic programming}
(1)forl=n-1down to0do// n is number of tasks in chain
(2)cost[l]=∞
(3)if(n-l)≤kthen//Base case
(4)cost[l]=0
(5)firstCut[l]=n
(6)else// General case
(7)fori in [0,k-1]do// Try k cuts, determine which is best
(8)tempCost=cost[l+i+1]+Cl+i+1
(9)iftempCost<cost[l]then
(10)cost[l]=tempCost
(11)firstCut[l]=l+i+1
endThe elements of thecost and firstCut arrays are computed in reverse order. Lines 3 and 4 consider the case where the task chain from l to n-1 contains k or less tasks, whereas lines 5–9 consider the general case. The general case is addressed by considering all the ways in which the first cut in the subchain starting at l can be made. For each possibility, we use the value of cost [l+i+1] that was computed in a previous iteration and Cl+i+1.Thecost array upon completion of execution of the algorithm on the input of Figure 2 is shown in Table 2 and the firstCut  array in Table 3.Table 2
Contents of arraycost on completion of algorithm.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
58
58
55
55
55
55
5
5
5
5
0
0
0
0Table 3
Contents of arrayfirst cut on completion of algorithm.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
2
2
6
6
6
6
10
10
10
10
14
14
14
14Theorem 1.
Algorithm COST (Algorithm2) computes an optimal solution to SPRM Formulation 1.Proof.
Clearly, the algorithm returns the correct value (zero) whenn-l≤k, since all the tasks can be accommodated in one configuration and there is no need to incur reconfiguration costs. If n-l>k, it must be the case that at least one cut is needed. Our dynamic programming solution considers all k possibilities for the leftmost cut and uses previously computed optimal cost values for the subchains.Theorem 2.
Algorithm COST has time complexityO(nlogk) and space complexity O(n).Proof.
There areO(n) elements in the cost array, each of which is computed in O(k) time. This results in a complexity of O(nk). We note that this can be improved to O(nlogk) as follows: observe that in order to compute any element cost[l], we obtain the minimum from a set of k quantities of the form cost[l+i+1]+Cl+i+1. Also, observe that in the computation of cost[l-1], k-1 of these quantities are identical to those used for cost[k]. Thus, it is possible to use a min-heap data structure in combination with a queue of pointers to elements in the min-heap to (1) compute the minimum, (2) delete one element, and (3) insert one element per iteration. Each of these can be accomplished in O(logk) time, giving the result.The algorithm to output cuts is given in Algorithm3.Algorithm 3:Output-Cuts algorithm.
CUTS(n) // The traceback step
(1)next = 0
(2)whilenext<ndo
(3)outputfirstCut[next]
(4)next=firstCut[next]
end


## 4.2. SPRM Formulation 2: Dynamic Task Generation

The dynamic task generation problem is a modification of the formulation described above. As before, the input is a linear chain of tasks. However, in addition to theCi+1 costs associated with each edge, a boolean parameter is also associated with each node. If this parameter is set to true a cut on either side of this node, this will require the creation of an additional node. This additional node will occupy one of the available FPGAs and therefore directly affects the calculation of the optimum cost and cut-set in the algorithm.Application. When a task is placed in the first FPGA in a configuration, it will need to read intermediate data from memory. Similarly, when a task is placed in the last FPGA in a configuration, it will need to write intermediate data to memory. This additional read/write functionality must be implemented on the FPGA. However, if the additional logic required does not fit on the FPGA or if the existing functionality on the FPGA already contains memory accesses and more memory accesses are not permitted by the architecture, an additional task must be created and accommodated on another FPGA.We use the same example as before, except that along with the reconfiguration cost there is a boolean flag associated with each vertex (Figure4).Figure 4
Initial task list with reconfiguration costs and boolean flag.Our algorithm obtains cuts at 3, 5, 6, and 10 of costs 10, 4, 50, and 5 resulting in an optimal cost of 69. Note that the addition of extra task nodes affects the cut location and therefore the overall cost. The optimum cuts would break the task list as can be seen in Figure5.Figure 5
Task list with optimum cuts and additional node locations.The cost function, which is the main modification to the Straight-Cut algorithm, is displayed in Algorithm4.Algorithm 4:SPRM (dynamic-node generation) algorithm.
COST(n)
{Compute minimum cost using dynamic programming}
(1)forl=n-1 down to 0do// n is number of tasks in chain
(2)cost[l]=∞
(3)if(n-l)≤k-b[l]-b[n-1]then//Base case
(4)cost[l]=0
(5)firstCut[l]=n
(6)else// General case
(7)fori in [0,k-1-b[l]]do// try all cuts, determine best one
(8)ifi<k-1-b[l]orb[l+i]=0then// checks whether additional task needed
(9)tempCost=cost[l+i+1]+Cl+i+1
(10)iftempCost<cost[l]then
(11)cost[l]=tempCost
(12)firstCut[l]=l+i+1
endThe main difference between the dynamic task and the straight cut versions is that configurations are analyzed to determine how many of their end-nodes are marked (i.e., an additional node is required if the cut is at this location). This quantity (0, 1, or 2) is subtracted from the possible number of FPGAs available for a configuration.


## 4.3. SPRM Formulation 3: Linear Chain with Limited Cycles

Recall that the partitioning algorithm of [4] partitions a DAG into a chain of n tasks such that the signal flows from left to right. However, this may not be possible or advantageous in some applications and may result in bidirectional edges or cycles as shown in Figure 6.Allocating multiple DAG nodes to a task can lead to a bidirectional edge: (a) original DAG, (b) allocation of DAG nodes to FPGA tasks, (c) bidirectional edge resulting from node merging.
(a)
(b)
(c)The interconnect on FPGA boards can be configured to permit bidirectional or cyclic signal flow, so the only limitation is that all tasks involved in this type of signal flow must be placed in the same board configuration. (Otherwise, a task in an earlier board configuration will need data produced by a task in the future.) Although SPRM is designed for a linear chain with a unidirectional signal flow, it can be modified for situations with alimited number of bidirectional edges or cycles. This constraint can be accommodated by assigning a large cost M to each bidirectional edge and to all edges in a cycle as shown in Figure 7. This will discourage our dynamic programming algorithm from cutting these edges forcing the algorithm to place the relevant tasks on the same board, provided this is feasible.(a) task chain with one cycle and one bidirectional edge. (b) Cost M assigned to each bidirectional or cycle edge.
(a)
(b)


## 5. GPRM

Recall that GPRM is designed for situations where the cost of reconfiguring Configurationc into Configuration c+1 is a function of all tasks assigned to those two configurations whereas SPRM is designed for situations where the reconfiguration cost is a function of the last task assigned to c and the first task assigned to c+1, while ignoring all of the other tasks in the two configurations. Thus GPRM subsumes SPRM and can handle all of the cases discussed in the previous section. In this section, we present six formulations of the GPRM problem. The first three consider scenarios where reconfiguration time can be saved by reusing logic through partial reconfiguration. The fourth and fifth consider dynamic task generation and linear chains with limited cycles (which can be handled by SPRM Formulations 2 and 3, resp.), while the sixth describes how cost metrics can be extended to include execution time.


### 5.1. GPRM Formulation 1: Repeating Tasks

To illustrate the GPRM strategy, we consider an example consisting of a board withk=5 FPGAs and a task chain with n=9 tasks, some of which are repeated. (Tasks can repeat if the same image processing transformation or the same memory management step is used several times in the computation.) The task chain consists of the tasks A, B, C, C, A, B, D, E, and C. Repeating tasks are represented by using the same letter of the alphabet. Table 4 shows four possible configuration sequences. Within each of the four sequences, a row represents a configuration and indicates which task is placed in each FPGA in that configuration.Table 4
Four possible solutions to GPRM sample problem: The first row shows the initially empty configurations. The second row shows the FPGAs with their initially loaded tasks (with the cost of loading included in the cost column in Row 2). We describe the example in detail for Solution 1: The cost of Row 2 is 3 because 3 of the 5 empty FPGAs are loaded with tasks while the other 2 remain empty. The cost of reconfiguring Row 2 into Row 3 is 4 (four FPGAs go from loaded to empty or vice versa while FPGA 3 retains the same task C). The cost of reconfiguring Row 3 into Row 4 is 4 (again four FPGAs either go from loaded to empty or vice versa while FPGA 3 continues to retain task C). We ignore the cost of emptying out the FPGAs at the end, giving a total cost of3+4+4=11. Solutions 3 and 4 are the best, each with a total cost of 6.
Solution 1
Solution 2
Solution 3
Solution 4
1
2
3
4
5
$
1
2
3
4
5
$
1
2
3
4
5
$
1
2
3
4
5
$
—
—
—
—
A
B
C
3
A
B
C
C
4
A
B
C
C
4
A
B
C
C
4
C
A
B
4
A
B
D
E
C
3
A
B
D
E
C
2
A
B
D
E
C
2
D
E
C
4
—
—
—
Total cost
11
Total cost
7
Total cost
6
Total cost
6To further simplify the presentation, we assume that the cost of reconfiguring an FPGA is 1 or 0 depending on the tasks that are allocated to the FPGA in consecutive configurations. The cost is 0 in the following two cases. (1) The FPGA remains empty in consecutive configurations. (2) The FPGA contains the same task in consecutive configurations. The cost is 1 in the following three cases. (1) The FPGA is empty in one configuration and occupied by a task in the next configuration. (2) The FPGA is occupied in one configuration and empty in the next configuration (reconfiguration is needed to prevent unwanted side effects). (3) The FPGA contains different tasks in the two consecutive configurations. Note that the reconfiguration cost is afunction of ALL tasks in consecutive configurations, which is precisely when the GPRM strategy is applicable. Note also that the SPRM strategy would not apply in this scenario.Our GPRM strategy consists of modeling the problem as a shortest-path problem in a directed acyclic graph with nonnegative costs assigned to the edges of the dag. Each node in the graph represents a possible configuration, that is, an assignment of tasks to FPGAs. Nodes of the graph are denoted by[l,b1b2⋯bk], where l denotes the index of the first task included in the configuration and bi, 1≤i≤k, is a bit which is set to 1 if FPGA i is occupied by a task and 0 if it is left unoccupied. Thus, we refer to b1b2⋯bk as the occupancy bit string. The total number of tasks included in a configuration is ∑i=1k‍bi and the index m of the last task in the configuration is l+∑i=1k‍bi-1. Note that empty configurations (∑i=1k‍bi=0) or configurations where m>n need not be considered. (Recall that n is the total number of tasks.)Configuration node[l,b1b2⋯bk] has an out-edge to all nodes of the form [m+1,*], where m denotes the index of the last task node in [l,b1b2⋯bk] and * denotes any occupancy bit pattern that represents a valid configuration. Edges connect every possible pair of consecutive configurations. We assign a cost to each edge which denotes the cost of reconfiguring the FPGA array with the new set of tasks. Since this quantity is a function of the two configurations joined by the edge, it can be easily computed. We also include a dummy source and a dummy sink node to facilitate the shortest-path computation. The source represents an “empty” configuration and has an out-edge to all nodes of the form [1,*]. The cost of the out-edge is the cost of initially configuring the FPGA array and is trivially computed. All nodes representing a configuration that contains task n have an out-edge to the sink node of cost 0.The DAG corresponding to our example is partially shown in Figure8.Figure 8
DAG example.The four configuration sequences of Table4 correspond to four different paths from source to sink in the DAG. Thus, Solution 1 contains the following sequence of intermediate nodes (using our notation for nodes) ([1,11100],[4,00111],[7,11100]) while Solution 4 contains the sequence ([1,11011],[5,11111]). There are two sequences that give a minimum cost and therefore an optimum solution.The three steps of the shortest-paths technique are summarized in Algorithm5.Algorithm 5:Shortest paths in DAG algorithm.
GPRM
(1)Create Dag
(2)Compute Reconfiguration Cost for each Dag edge
(3)Compute Least Cost Source-Sink Path in Dag
endLemma 3.
The total number of configuration nodes for a chain ofn tasks on an array of k FPGAs is bounded by n2k.Proof.
The variablel can take on n values and each of the k elements of the occupancy string can take on one of two values. Multiplying these quantities gives the desired result.Lemma 4.
The total number of edges for a chain ofn tasks on an array of k FPGAs is bounded by O(n4k).Proof.
There areO(n2k) nodes, each of which has at most 2k out edges, yielding the desired result.Theorem 5.
The shortest-paths in DAG algorithm (Algorithm5) computes an optimal cost solution to GPRM Formulation 1.Proof.
Note that the only constraint is that the chain of tasks must be executed in order. Any path from source to sink in our dag gives a valid sequence of configurations since nodes are only joined by edges if they contain consecutive task sequences. Similarly, any valid sequence of configurations is represented by a path in our graph since each valid configuration is represented by a node and since edges are constructed for all possible pairs of consecutive configurations. The total cost for a path is the sum of the cost of the edges, which represent individual reconfiguration costs. Consequently, the shortest-path from source to sink gives an optimal-cost sequence of configurations.Theorem 6.
GPRM requiresO(nk4k) time and O(n2k) space.Proof.
The number of nodes in the dag isO(n2k) and the number of edges is O(n4k). Edge costs are computed in O(k) time per edge since a pair of tasks needs to be examined for each of k FPGAs on the board. Thus, the total time for graph creation is O(nk4k). A topological ordering based technique can be used to compute the shortest source-sink path since the graph is a dag in O(n4k) time. Thus, the total time complexity is O(nk4k). The space required by the graph is proportional to the number of edges and is O(n4k). Next, we propose a data structure to represent the DAG that reduces the memory requirements of GPRM to (n2k). We use an n×2k 2-dimensional array to represent the nodes of the DAG. The element in position (i,j) corresponds to the node [i,j1j2⋯jk], where the bit string j1j2⋯jk is the binary representation of j. Note that it is not necessary to explicitly maintain the edges leading out of the node corresponding to element (i,j). These edges can be implicitly computed during the topological traversal of the DAG as there will be an outgoing edge to each of the 2k nodes of the form (i+∑l=1kjl,*). This reduces the storage complexity to O(n2k).An anonymous referee asked us to consider how we might modify GPRM when the FPGA interconnection network permits signals between any pair of FPGAs leading to the observation that the linear task order constraint assumed in Table1 need not be satisfied. While this is beyond the scope of the current paper, we briefly mention how this could be achieved. Our notation of [4,01110] currently means that tasks 4, 5, and 6 must be assigned to FPGAs 2, 3 and 4, respectively. Under the referee's assumption any permutation of the three tasks would also be acceptable, leading to 3!=6 configurations. The notation could be modified by replacing the “1”s in the bit string with the appropriate permutation information. Thus, [4,01230] would mean that Tasks 4, 5, and 6 are placed in FPGAS 2, 3, and 4, respectively, as before, while [4,02310] would mean that Tasks 4, 5, and 6 are placed in FPGAs 4, 2, and 3, respectively. In the worst case, this will expand the number of nodes in the DAG by a factor of k! and the number of edges by a factor of k!2.


### 5.2. GPRM Formulation 2: Similar Tasks

Formulation 1 assigned a reconfiguration time of 0 if the identical task was allocated to an FPGA in consecutive configurations. In Formulation 2, we consider the scenario where two tasks are not identical, but are similar, because some subtasks are identical (Figure9). Specifically, if two tasks located in the same FPGA in consecutive configurations have identical subtasks in the same subareas of the FPGA, it may be possible to obtain the second configuration from the first by partially reconfiguring the FPGA. This would consume less time than a full reconfiguration and can be modeled by the DAG construction as described in the previous section by simply modifying edge costs before executing the shortest-path algorithm. Note that actual reconfiguration costs can be modeled fairly accurately using approaches discussed in [8–10].Figure 9
Similar Tasks Illustration: subtask D is repeated, giving a 25% similarity or a 0.75 partial reconfiguration cost instead of a full reconfiguration cost of 1.


### 5.3. GPRM Formulation 3: Implementation Libraries

A task can be implemented in several ways in an FPGA depending on how its subtasks are laid out within the FPGA. This gives rise to several implementations of a task that can be stored in a library. An intelligent scheduler would choose task implementations from the library that minimize reconfiguration cost. We illustrate these ideas in Figure10. Suppose that an FPGA originally contains a task consisting of subtasks {A,B,C,D}. Suppose this FPGA is to be reconfigured with a task consisting of subtasks {C,D,E,F}. The figure shows three implementations of this task. Clearly, the choice of an implementation affects the reconfiguration cost. For example, implementation 1 results in a 0% match (and therefore a complete reconfiguration), while implementation 2 results in a 25% match (and therefore a partial reconfiguration cost of 75%), and implementation 3 results in a partial reconfiguration cost of 50%.Figure 10
Implementation libraries illustration.Assume that the maximum number of implementations of any task that are available in an implementation library isα. Then, we can construct a graph consisting of nodes of the form [l,c1c2⋯ck], where l denotes the index of the first task included in the configuration and ci, 1≤i≤k, is an integer which is set to 0 if FPGA i is unoccupied or to j, 1≤j≤α if FPGA i is occupied by implementation number j of a task.Configuration node[l,c1c2⋯ck] has an out-edge to all nodes of the form [m+1,*], where m denotes the index of the last task node in [l,c1c2⋯ck] and * denotes any occupancy pattern that represents a valid configuration. As before, dummy source and sink nodes are added to the graph. The source has an out-edge to all nodes of the form [1,*]. All nodes representing a configuration that contains task n have an out-edge to the sink node of cost 0.As before, the shortest-path from source to sink results in an optimal configuration schedule.Lemma 7.
The total number of nodes in the graph is bounded byn(α+1)k.Proof.
The variablel can take on n values and each of the k elements of the occupancy string can take on one of α+1 values. Multiplying these quantities gives the desired result.Lemma 8.
The total number of edges for a chain ofn tasks on an array of k FPGAs is bounded by n(α+1)2k.


### 5.4. GPRM Formulation 4: Dynamic Task Generation

Recall that additional functionality may be required in the first and last FPGAs to, respectively, read in and write out data in each configuration. This additional functionality may not fit in an FPGA when combined with the task assigned to that FPGA from the task chain. Recall also that this was addressed by the SPRM Formulation 2. Since GPRM is a generalization of SPRM, we expect to be able to capture this formulation within the framework of GPRM. The GPRM algorithm can be modified by simply deleting all nodes (and incident edges) in the graph that contain tasks in the first or last FPGA that cannot accommodate the additional functionality. A shortest-path computation on the remainder of the graph deftly solves this formulation.


### 5.5. GPRM Formulation 5: Linear Chain with Limited Cycles

We again consider the situation described in SPRM Formulation 3 and depicted in Figure7 (task chain with a limited number of bidirectional edges and small cycles). In SPRM, this was addressed by imposing a large cost on bidirectional edges or between adjacent tasks that were part of a cycle. This was done to prevent the scenario where a board configuration requires the results of a future configuration. The same approach can be used in GPRM: if there are a pair of consecutive configurations (represented by vertices joined by a directed edge in the shortest-path graph) such that the output of a task in the later configuration is the input of a task in an earlier configuration, the cost of the directed edge connecting the two configurations is made arbitrarily large. The shortest-path algorithm used to compute the optimal schedule will find a path that (implicitly) ignores the high-cost edge.


### 5.6. GPRM Formulation 6: Alternative Cost Functions

Although the preceding discussion has focused on minimizing reconfiguration time, our model can handle alternative cost formulations that (1) include execution time and (2) systems where reconfiguration of the FPGAs may be sequential or parallel. To make this concrete, we consider the two scenarios shown in Figure11. In both scenarios, each of the four FPGA tasks is decomposed into a reconfiguration component (R) and an execution component (E). An arrow from the reconfiguration component to the execution component of each task is the dependency resulting from the observation that a task can only be executed after it is configured. In (a), the four reconfigurations are assumed to be sequential—this is denoted by the arrows from Ra to Rb to Rc to Rd. In (b) the four reconfigurations are assumed to be carried out in parallel. Thus, there are no arrows among Ra, Rb, Rc, and Rd. In both cases we assume that there is a sequential dependency between the executions (so there are arrows from Ea to Eb to Ec to Ed).Both scenarios include execution time. (a) assumes sequential reconfiguration and (b) assumes parallel reconfiguration.
(a)
(b)Example. Assume that reconfiguration times Ra, Rb, Rc, and Rd are 100 units each and that execution times Ea, Eb, Ec, and Ed are 5, 7, 3, and 10 units, respectively. Since execution times are smaller than reconfiguration times, the total cost of the formulation in Figure 11(a) is 400 (4 sequential reconfigurations) + 10 (execution time of Ed) = 410. The cost of the formulation in Figure 11(b) is 100 (to configure the FPGAs in parallel) + 25 (the sum of the execution times) = 125. More generally, the formal cost function that captures the dependency in Figure 11(b) is max(max(max(R1+E1,R2)+E2,R3)+E3,R4)+E4. Substituting, we can confirm that this is evaluated to be max(max(max(100+5,100)+7,100)+3,100)+10=125. The formal cost function for Figure 11(a) is max(Ra+Rb+Rc+Rd,max(Ra+Rb+Rc,max(Ra+Ea,Ra+Rb)+Eb)+Ec)+Ed, which is evaluated to be 410 as expected. Both cost functions are critical path computations that model the particular reconfiguration/execution dependencies.Both of these are functions of the tasks in the board configuration and fall under the framework of the GPRM model. In the GPRM shortest-path formulation, incoming edges to the vertex corresponding to this board configuration can be assigned costs computed as above. Other complex cost functions involving reconfiguration and execution times can also be similarly captured by our cost model.


## 5.1. GPRM Formulation 1: Repeating Tasks

To illustrate the GPRM strategy, we consider an example consisting of a board withk=5 FPGAs and a task chain with n=9 tasks, some of which are repeated. (Tasks can repeat if the same image processing transformation or the same memory management step is used several times in the computation.) The task chain consists of the tasks A, B, C, C, A, B, D, E, and C. Repeating tasks are represented by using the same letter of the alphabet. Table 4 shows four possible configuration sequences. Within each of the four sequences, a row represents a configuration and indicates which task is placed in each FPGA in that configuration.Table 4
Four possible solutions to GPRM sample problem: The first row shows the initially empty configurations. The second row shows the FPGAs with their initially loaded tasks (with the cost of loading included in the cost column in Row 2). We describe the example in detail for Solution 1: The cost of Row 2 is 3 because 3 of the 5 empty FPGAs are loaded with tasks while the other 2 remain empty. The cost of reconfiguring Row 2 into Row 3 is 4 (four FPGAs go from loaded to empty or vice versa while FPGA 3 retains the same task C). The cost of reconfiguring Row 3 into Row 4 is 4 (again four FPGAs either go from loaded to empty or vice versa while FPGA 3 continues to retain task C). We ignore the cost of emptying out the FPGAs at the end, giving a total cost of3+4+4=11. Solutions 3 and 4 are the best, each with a total cost of 6.
Solution 1
Solution 2
Solution 3
Solution 4
1
2
3
4
5
$
1
2
3
4
5
$
1
2
3
4
5
$
1
2
3
4
5
$
—
—
—
—
A
B
C
3
A
B
C
C
4
A
B
C
C
4
A
B
C
C
4
C
A
B
4
A
B
D
E
C
3
A
B
D
E
C
2
A
B
D
E
C
2
D
E
C
4
—
—
—
Total cost
11
Total cost
7
Total cost
6
Total cost
6To further simplify the presentation, we assume that the cost of reconfiguring an FPGA is 1 or 0 depending on the tasks that are allocated to the FPGA in consecutive configurations. The cost is 0 in the following two cases. (1) The FPGA remains empty in consecutive configurations. (2) The FPGA contains the same task in consecutive configurations. The cost is 1 in the following three cases. (1) The FPGA is empty in one configuration and occupied by a task in the next configuration. (2) The FPGA is occupied in one configuration and empty in the next configuration (reconfiguration is needed to prevent unwanted side effects). (3) The FPGA contains different tasks in the two consecutive configurations. Note that the reconfiguration cost is afunction of ALL tasks in consecutive configurations, which is precisely when the GPRM strategy is applicable. Note also that the SPRM strategy would not apply in this scenario.Our GPRM strategy consists of modeling the problem as a shortest-path problem in a directed acyclic graph with nonnegative costs assigned to the edges of the dag. Each node in the graph represents a possible configuration, that is, an assignment of tasks to FPGAs. Nodes of the graph are denoted by[l,b1b2⋯bk], where l denotes the index of the first task included in the configuration and bi, 1≤i≤k, is a bit which is set to 1 if FPGA i is occupied by a task and 0 if it is left unoccupied. Thus, we refer to b1b2⋯bk as the occupancy bit string. The total number of tasks included in a configuration is ∑i=1k‍bi and the index m of the last task in the configuration is l+∑i=1k‍bi-1. Note that empty configurations (∑i=1k‍bi=0) or configurations where m>n need not be considered. (Recall that n is the total number of tasks.)Configuration node[l,b1b2⋯bk] has an out-edge to all nodes of the form [m+1,*], where m denotes the index of the last task node in [l,b1b2⋯bk] and * denotes any occupancy bit pattern that represents a valid configuration. Edges connect every possible pair of consecutive configurations. We assign a cost to each edge which denotes the cost of reconfiguring the FPGA array with the new set of tasks. Since this quantity is a function of the two configurations joined by the edge, it can be easily computed. We also include a dummy source and a dummy sink node to facilitate the shortest-path computation. The source represents an “empty” configuration and has an out-edge to all nodes of the form [1,*]. The cost of the out-edge is the cost of initially configuring the FPGA array and is trivially computed. All nodes representing a configuration that contains task n have an out-edge to the sink node of cost 0.The DAG corresponding to our example is partially shown in Figure8.Figure 8
DAG example.The four configuration sequences of Table4 correspond to four different paths from source to sink in the DAG. Thus, Solution 1 contains the following sequence of intermediate nodes (using our notation for nodes) ([1,11100],[4,00111],[7,11100]) while Solution 4 contains the sequence ([1,11011],[5,11111]). There are two sequences that give a minimum cost and therefore an optimum solution.The three steps of the shortest-paths technique are summarized in Algorithm5.Algorithm 5:Shortest paths in DAG algorithm.
GPRM
(1)Create Dag
(2)Compute Reconfiguration Cost for each Dag edge
(3)Compute Least Cost Source-Sink Path in Dag
endLemma 3.
The total number of configuration nodes for a chain ofn tasks on an array of k FPGAs is bounded by n2k.Proof.
The variablel can take on n values and each of the k elements of the occupancy string can take on one of two values. Multiplying these quantities gives the desired result.Lemma 4.
The total number of edges for a chain ofn tasks on an array of k FPGAs is bounded by O(n4k).Proof.
There areO(n2k) nodes, each of which has at most 2k out edges, yielding the desired result.Theorem 5.
The shortest-paths in DAG algorithm (Algorithm5) computes an optimal cost solution to GPRM Formulation 1.Proof.
Note that the only constraint is that the chain of tasks must be executed in order. Any path from source to sink in our dag gives a valid sequence of configurations since nodes are only joined by edges if they contain consecutive task sequences. Similarly, any valid sequence of configurations is represented by a path in our graph since each valid configuration is represented by a node and since edges are constructed for all possible pairs of consecutive configurations. The total cost for a path is the sum of the cost of the edges, which represent individual reconfiguration costs. Consequently, the shortest-path from source to sink gives an optimal-cost sequence of configurations.Theorem 6.
GPRM requiresO(nk4k) time and O(n2k) space.Proof.
The number of nodes in the dag isO(n2k) and the number of edges is O(n4k). Edge costs are computed in O(k) time per edge since a pair of tasks needs to be examined for each of k FPGAs on the board. Thus, the total time for graph creation is O(nk4k). A topological ordering based technique can be used to compute the shortest source-sink path since the graph is a dag in O(n4k) time. Thus, the total time complexity is O(nk4k). The space required by the graph is proportional to the number of edges and is O(n4k). Next, we propose a data structure to represent the DAG that reduces the memory requirements of GPRM to (n2k). We use an n×2k 2-dimensional array to represent the nodes of the DAG. The element in position (i,j) corresponds to the node [i,j1j2⋯jk], where the bit string j1j2⋯jk is the binary representation of j. Note that it is not necessary to explicitly maintain the edges leading out of the node corresponding to element (i,j). These edges can be implicitly computed during the topological traversal of the DAG as there will be an outgoing edge to each of the 2k nodes of the form (i+∑l=1kjl,*). This reduces the storage complexity to O(n2k).An anonymous referee asked us to consider how we might modify GPRM when the FPGA interconnection network permits signals between any pair of FPGAs leading to the observation that the linear task order constraint assumed in Table1 need not be satisfied. While this is beyond the scope of the current paper, we briefly mention how this could be achieved. Our notation of [4,01110] currently means that tasks 4, 5, and 6 must be assigned to FPGAs 2, 3 and 4, respectively. Under the referee's assumption any permutation of the three tasks would also be acceptable, leading to 3!=6 configurations. The notation could be modified by replacing the “1”s in the bit string with the appropriate permutation information. Thus, [4,01230] would mean that Tasks 4, 5, and 6 are placed in FPGAS 2, 3, and 4, respectively, as before, while [4,02310] would mean that Tasks 4, 5, and 6 are placed in FPGAs 4, 2, and 3, respectively. In the worst case, this will expand the number of nodes in the DAG by a factor of k! and the number of edges by a factor of k!2.


## 5.2. GPRM Formulation 2: Similar Tasks

Formulation 1 assigned a reconfiguration time of 0 if the identical task was allocated to an FPGA in consecutive configurations. In Formulation 2, we consider the scenario where two tasks are not identical, but are similar, because some subtasks are identical (Figure9). Specifically, if two tasks located in the same FPGA in consecutive configurations have identical subtasks in the same subareas of the FPGA, it may be possible to obtain the second configuration from the first by partially reconfiguring the FPGA. This would consume less time than a full reconfiguration and can be modeled by the DAG construction as described in the previous section by simply modifying edge costs before executing the shortest-path algorithm. Note that actual reconfiguration costs can be modeled fairly accurately using approaches discussed in [8–10].Figure 9
Similar Tasks Illustration: subtask D is repeated, giving a 25% similarity or a 0.75 partial reconfiguration cost instead of a full reconfiguration cost of 1.


## 5.3. GPRM Formulation 3: Implementation Libraries

A task can be implemented in several ways in an FPGA depending on how its subtasks are laid out within the FPGA. This gives rise to several implementations of a task that can be stored in a library. An intelligent scheduler would choose task implementations from the library that minimize reconfiguration cost. We illustrate these ideas in Figure10. Suppose that an FPGA originally contains a task consisting of subtasks {A,B,C,D}. Suppose this FPGA is to be reconfigured with a task consisting of subtasks {C,D,E,F}. The figure shows three implementations of this task. Clearly, the choice of an implementation affects the reconfiguration cost. For example, implementation 1 results in a 0% match (and therefore a complete reconfiguration), while implementation 2 results in a 25% match (and therefore a partial reconfiguration cost of 75%), and implementation 3 results in a partial reconfiguration cost of 50%.Figure 10
Implementation libraries illustration.Assume that the maximum number of implementations of any task that are available in an implementation library isα. Then, we can construct a graph consisting of nodes of the form [l,c1c2⋯ck], where l denotes the index of the first task included in the configuration and ci, 1≤i≤k, is an integer which is set to 0 if FPGA i is unoccupied or to j, 1≤j≤α if FPGA i is occupied by implementation number j of a task.Configuration node[l,c1c2⋯ck] has an out-edge to all nodes of the form [m+1,*], where m denotes the index of the last task node in [l,c1c2⋯ck] and * denotes any occupancy pattern that represents a valid configuration. As before, dummy source and sink nodes are added to the graph. The source has an out-edge to all nodes of the form [1,*]. All nodes representing a configuration that contains task n have an out-edge to the sink node of cost 0.As before, the shortest-path from source to sink results in an optimal configuration schedule.Lemma 7.
The total number of nodes in the graph is bounded byn(α+1)k.Proof.
The variablel can take on n values and each of the k elements of the occupancy string can take on one of α+1 values. Multiplying these quantities gives the desired result.Lemma 8.
The total number of edges for a chain ofn tasks on an array of k FPGAs is bounded by n(α+1)2k.


## 5.4. GPRM Formulation 4: Dynamic Task Generation

Recall that additional functionality may be required in the first and last FPGAs to, respectively, read in and write out data in each configuration. This additional functionality may not fit in an FPGA when combined with the task assigned to that FPGA from the task chain. Recall also that this was addressed by the SPRM Formulation 2. Since GPRM is a generalization of SPRM, we expect to be able to capture this formulation within the framework of GPRM. The GPRM algorithm can be modified by simply deleting all nodes (and incident edges) in the graph that contain tasks in the first or last FPGA that cannot accommodate the additional functionality. A shortest-path computation on the remainder of the graph deftly solves this formulation.


## 5.5. GPRM Formulation 5: Linear Chain with Limited Cycles

We again consider the situation described in SPRM Formulation 3 and depicted in Figure7 (task chain with a limited number of bidirectional edges and small cycles). In SPRM, this was addressed by imposing a large cost on bidirectional edges or between adjacent tasks that were part of a cycle. This was done to prevent the scenario where a board configuration requires the results of a future configuration. The same approach can be used in GPRM: if there are a pair of consecutive configurations (represented by vertices joined by a directed edge in the shortest-path graph) such that the output of a task in the later configuration is the input of a task in an earlier configuration, the cost of the directed edge connecting the two configurations is made arbitrarily large. The shortest-path algorithm used to compute the optimal schedule will find a path that (implicitly) ignores the high-cost edge.


## 5.6. GPRM Formulation 6: Alternative Cost Functions

Although the preceding discussion has focused on minimizing reconfiguration time, our model can handle alternative cost formulations that (1) include execution time and (2) systems where reconfiguration of the FPGAs may be sequential or parallel. To make this concrete, we consider the two scenarios shown in Figure11. In both scenarios, each of the four FPGA tasks is decomposed into a reconfiguration component (R) and an execution component (E). An arrow from the reconfiguration component to the execution component of each task is the dependency resulting from the observation that a task can only be executed after it is configured. In (a), the four reconfigurations are assumed to be sequential—this is denoted by the arrows from Ra to Rb to Rc to Rd. In (b) the four reconfigurations are assumed to be carried out in parallel. Thus, there are no arrows among Ra, Rb, Rc, and Rd. In both cases we assume that there is a sequential dependency between the executions (so there are arrows from Ea to Eb to Ec to Ed).Both scenarios include execution time. (a) assumes sequential reconfiguration and (b) assumes parallel reconfiguration.
(a)
(b)Example. Assume that reconfiguration times Ra, Rb, Rc, and Rd are 100 units each and that execution times Ea, Eb, Ec, and Ed are 5, 7, 3, and 10 units, respectively. Since execution times are smaller than reconfiguration times, the total cost of the formulation in Figure 11(a) is 400 (4 sequential reconfigurations) + 10 (execution time of Ed) = 410. The cost of the formulation in Figure 11(b) is 100 (to configure the FPGAs in parallel) + 25 (the sum of the execution times) = 125. More generally, the formal cost function that captures the dependency in Figure 11(b) is max(max(max(R1+E1,R2)+E2,R3)+E3,R4)+E4. Substituting, we can confirm that this is evaluated to be max(max(max(100+5,100)+7,100)+3,100)+10=125. The formal cost function for Figure 11(a) is max(Ra+Rb+Rc+Rd,max(Ra+Rb+Rc,max(Ra+Ea,Ra+Rb)+Eb)+Ec)+Ed, which is evaluated to be 410 as expected. Both cost functions are critical path computations that model the particular reconfiguration/execution dependencies.Both of these are functions of the tasks in the board configuration and fall under the framework of the GPRM model. In the GPRM shortest-path formulation, incoming edges to the vertex corresponding to this board configuration can be assigned costs computed as above. Other complex cost functions involving reconfiguration and execution times can also be similarly captured by our cost model.


## 6. Detailed SPRM and GPRM Meta heuristics

We have previously shown a high-level metaheuristic in Algorithm1 that uses the cost model to determine whether to use SPRM or GPRM. We have also argued that, since the GPRM cost model subsumes the SPRM cost model, any formulation that can be addressed by SPRM can also be solved using GPRM. However SPRM is faster making it the better choice when either approach can be used.For ease of presentation, we described three SPRM and six GPRM formulations separately in the preceding sections. However, in some cases these formulations can be combined with each other in complex ways. This is illustrated in Algorithms6 and 7.Algorithm 6:Detailed SPRM Metaheuristic showing that SPRM 1 and SPRM 2 are mutually exclusive, but both can be combined with SPRM 3.
SPRM Meta Algorithm
(1)if(Dynamic Task Generation Needed)
(2)thenAlgorithm = SPRM 2
(3)else Algorithm = SPRM 1
(4)if(Task Chain Has Cycles)
(5)thenIncorporate SPRM 3 Cost Model
endAlgorithm 7:Detailed GPRM metaheuristic: this elaborates on the GPRM outline provided in Algorithm 5 by first determining the appropriate DAG structure. It then computes the correct cost model, which can be a combination of any of the cost models used in SPRM 1, GPRM 1, GPRM 2, GPRM 5, and GPRM 6.
GPRM Meta Algorithm
(1)if(Implementation Libraries Used)
(2)then DAG_Structure = Basic DAG Structure defined in GPRM 3
(3)elseDAG_Structure = Basic DAG Structure defined in GPRM 1
(4)if(Dynamic Task Generation Needed)
(5)Update DAG Structure as described in GPRM 4
(6)Cost_Model = SPRM 1 Cost Model// baseline cost model
(7)If (Repeated Tasks Present)
(8)thenUpdate Cost_Model as described in GPRM 1
(9)If (Similar Tasks Present)
(10)thenUpdate Cost_Model as described in GPRM 2
(11)If (Limited Cycles Present)
(12)thenUpdate Cost_Model as described in GPRM 5
(13)If (Alternative Cost Functions Needed )
(14)thenModify Cost_Model as described in GPRM 6
(15)Run Shortest Paths Algorithm.endFinally, we note that although we have only proved optimality for SPRM Formulation 1 and GPRM Formulation 1, all of the scenarios described in the previous sections including the combinations described in Algorithms6 and 7 can be solved optimally by using appropriate extensions of SPRM and GPRM.


## 7. Experimental Results

All algorithms were implemented in the C programming language on a 500 Mhz Dell OptiPlex GX1 with 256 MB of RAM. The automatic target recognition algorithm (ATR) that was implemented on CHAMPION was the only application that required board reconfigurations. Our algorithms obtained an identical (optimal) solution to that of the manual cut.In addition to this, we designed some examples to “stress-test” our code. The results are presented below. The results for GPRM Formulation 1 (repeated tasks) with cost functions as defined in Section5.1 are shown in Table 5. Elapsed time was reported in seconds using the clock( ) function. A naive heuristic that was used for comparison purposes simply made cuts at regular intervals of k tasks along the task chain. Note that in all cases the runtime was not more than a few seconds. The runtime for the heuristic was less than the significant digits reported. The average cost reduction between the GPRM technique and the simple heuristic is 21%.Table 5
GPRM versus heuristic.
Nodes
FPGAs
GPRM
Heuristic
n
k
Cost
Time
Cost
Time
100
4
59
0.11
72
0.00
100
5
59
0.33
74
0.00
500
4
298
0.33
377
0.00
500
5
294
1.37
384
0.00
1000
4
600
0.82
744
0.00
1000
5
590
3.13
757
0.00The results for SPRM Formulation 1 (the Straight-Cut version) as defined in Section4.1 with integer costs chosen randomly in [1,100] are shown in Table 6. Increasing the FPGA size from 4 to 6 lowered the cost substantially. The Straight Cut SPRM algorithm results in an average cost reduction of 50% relative to the naive heuristic.Table 6
Straight-Cut SPRM versus naive heuristic.
Nodes
FPGAs
SPRM
Heuristic
n
k
Cost
Cost
100
4
560
965
100
5
415
962
100
6
371
724
175
4
1067
1782
175
5
811
1884
175
6
683
1469The results for SPRM Formulation 2 (dynamic-node generation) as defined in Section4.2 are shown in Table 7. We used the same data as for SPRM Formulation 1.      Increasing the FPGA size from 4 to 6 did lower the cost substantially. The average cost reduction relative to the naive heuristic is 46%. The naive heuristic was modified to add task nodes depending on the values of the Boolean flag associated with each node. (If the flag is true, the task is not permitted to be placed in the first or last FPGA; instead it is placed in the next available FPGA.) (An anonymous reviewer suggested using a greedy heuristic for the SPRM problem formulations that could traverse the task chain, greedily making a cut at the smallest cost arc from among the next k arcs at each stage. We expect that this will perform much better than the naive heuristic. However, we note that this greedy approach cannot guarantee optimal costs and moreover will have essentially the same linear runtime as our dynamic programming algorithm for small constant k.)Table 7
Dynamic SPRM versus heuristic.
Nodes
FPGAs
SPRM
Heuristic
n
k
Cost
Cost
100
4
921
1810
100
5
514
1053
100
6
375
922
175
4
2082
3323
175
5
1181
2056
175
6
813
1685


## 8. Discussion and Conclusion

This paper presented a high-level meta-algorithm and detailed meta-algorithms for SPRM and GPRM for scheduling FPGA board configurations. This is a powerful strategy that encapsulates a wide range f problem formulations (including combinations of problem formulations) and algorithms into a single framework. The deterministic quality of this meta-algorithm and the guarantee of optimal solutions for all of the formulations discussed make this a viable alternative to traditional stochastic meta-algorithms such as simulated annealing and genetic algorithms.



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*Source: 249592-2013-12-25.xml*