# Design of Digital Control System for DC/DC Converter of On-Board Charger

Authors: Haijun Tao; Guopeng Zhang; Zheng Zheng; Changshun Du
Journal: Journal of Advanced Transportation
 (2019)

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## Abstract

Vehicle charging power supply is widely used because of its small size and portability. Aiming at the problems of slow dynamic response, subharmonic, oscillation and limited soft-switching range of phase-shifted full-bridge DC/DC converter, the paper proposed a modified PSFB converter by introducing clamp diodes at the primary side of the transformer to suppress voltage oscillation of the transformer’s secondary side. Also, digital peak current phase-shifting control and slope compensation are introduced to avoid subharmonic oscillation. Dynamic dead-time control technology introduced adjust the dead-time in different load ranges through the dead-time adjustment subroutine. Finally, an experimental platform of on-board charging phase-shifted full-bridge DC/DC converter is established. The experimental results show that the power supply eliminates subharmonic oscillation, achieves a wide range of soft-switching, improves the dynamic performance and antiinterference ability of the system, and optimizes the power efficiency.


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## Body

## 1. Introduction

The electric vehicle has many advantages, such as high energy utilization rate, no pollution, and so on [1]. EV batteries are connected to the power grid through charging power supply. There are two main types of on-board charging power supply: one is uncontrolled rectifier isolated DC/DC converter, which has high harmonic and power factor which cannot meet the requirements. The other is an isolated DC/DC converter with active power factor correction, in which AC/DC converter is a boost type, which can realize power factor correction and improve the power density of the system. DC/DC converter has the key energy conversion part of vehicle charging power which directly affects its efficiency [2]. Phase Shift Full Bridge (PSFB) topology is widely used in the field of vehicle charging power supply because of its high efficiency, high power density, and easy realization of Zero Voltage Switch (ZVS) [3].At present, there are many charging modes, such as constant current-constant voltage charging, variable current intermittent charging, and multistage constant current charging [4]. Constant-current-voltage constant-charge, first large current constant-current, and then constant-voltage charge, not only avoids the phenomenon of current overcharge but also reduces the amount of gas evolution. In constant voltage mode, the output current of the converter gradually decreases from full load to zero. In order to maintain good soft-switching characteristics, the dead time Td between the drive signals of the bridge arm should be shortened accordingly. Although the voltage-controlled PSFB DC/DC converter has simple control mode, it has some problems such as slow regulation speed and limited soft-switching range [5]. It has the advantages of fast dynamic response, simple transformer bias, and overload protection circuit [6]. When duty cycle D>0.5, subharmonic oscillation will occur, which can be solved by introducing slope compensation [7].The analog control chip has some shortcomings such as the temperature drift, fixed control parameters, and slow response speed. The configuration of digital control parameters is flexible and the dead-timeTd can be adjusted by software, which avoids the difficulty of soft-switching in light load due to the fixed dead-time under analog control conditions. As for digital control, single voltage loop of digital control is analyzed and designed in the literature [8]. The average current mode phase-shifted full-bridge soft switch with digital control is proposed in the literature [9], which has good antinoise performance, but it is very complex to debug the two sets of parameters of voltage inner loop and outer loop. The peak current control is given in the literature [10]. Phase-shifted full-bridge scheme, but there is no dead-time research.Therefore, a new PSFB DC/DC ZVS PWM converter is designed in this paper. The clamp diode is added to the primary side of the transformer and the synchronous rectification technology is used to the secondary side. The digital peak current phase-shifting control and slope compensation are introduced to avoid subharmonic oscillation. The implementation mechanism of digital PWM is analyzed, and dynamic dead-time control technology is proposed, that is, to adjust the dead-time in different load ranges through the automatic dead-time adjustment subroutine. Finally, the driving circuit and sampling circuit are designed. It realizes a wide range of soft-switching, improves the dynamic performance, and antiinterference ability of the system, and improves the power supply efficiency.


## 2. DC/DC Converter of Vehicle Charging Power Supply

### 2.1. Main Circuit of DC/DC Converter

Figure1 shows the main circuit topology of a novel PSFB ZVS PWM DC/DC converter with clamping diodes. The input voltage is Vin and the switching frequency is fs=100 kHz. The full-bridge switches Q1–Q4are composed of MOSFET. Lr is a resonant inductor, C1–C6 is divided into junction capacitors on Q1–Q6; Lf and Cf form output filters; N is the ratio of the transformer; the advantage of this topology is that clamping diodes D5 and D6 are added to the original side of the transformer to suppress voltage oscillation of the transformer’s secondary side; at the same time, the Synchronous Rectification (SR) technology is introduced into the transformer’s secondary side. The SR tubes Q5 and Q6 are composed of MOSFET, which reduces the conduction loss of the rectifier.Figure 1
Main circuit of PSFB DC/DC converter.


### 2.2. Subharmonic Oscillation

The peak current-mode control is to determine the output PWM wave by comparing the actual inductance current with the output of the voltage outer loop. However, when duty cycleD>0.5, the disturbance of current ip on the primary side of the transformer increases with the increase of period, and eventually produces oscillation. The oscillation frequency of this disturbance is half of the switching frequency, so it is called subharmonic oscillation. For this reason, the slope compensation technology is introduced to suppress subharmonic oscillation.


### 2.3. Limited Soft-Switching Range of PSFB DC/DC Converter

The switching process of PSFB DC/DC converter is realized by resonance, so it is not instantaneous to decrease the voltageVds from Vin to 0. If the dead time Td between the driving signals of the bridge arm switch is too short, the Vds will not be switched on before it is reduced to zero, and the switch will lose its soft-switching characteristic; if the dead time Td is too long, the two switches will be switched on. When the terminal voltage Vds drops to 0, the switch fails to turn on in time. The Vds rises again through resonance, and the switch also loses its soft-switching characteristic. Thus, the soft-switching range of vehicle charging power supply is severely limited under the condition of constant voltage charging mode and wide load current variation. Therefore, an automatic dead-time control technology is proposed to realize a wide range of soft-switching.


## 2.1. Main Circuit of DC/DC Converter

Figure1 shows the main circuit topology of a novel PSFB ZVS PWM DC/DC converter with clamping diodes. The input voltage is Vin and the switching frequency is fs=100 kHz. The full-bridge switches Q1–Q4are composed of MOSFET. Lr is a resonant inductor, C1–C6 is divided into junction capacitors on Q1–Q6; Lf and Cf form output filters; N is the ratio of the transformer; the advantage of this topology is that clamping diodes D5 and D6 are added to the original side of the transformer to suppress voltage oscillation of the transformer’s secondary side; at the same time, the Synchronous Rectification (SR) technology is introduced into the transformer’s secondary side. The SR tubes Q5 and Q6 are composed of MOSFET, which reduces the conduction loss of the rectifier.Figure 1
Main circuit of PSFB DC/DC converter.


## 2.2. Subharmonic Oscillation

The peak current-mode control is to determine the output PWM wave by comparing the actual inductance current with the output of the voltage outer loop. However, when duty cycleD>0.5, the disturbance of current ip on the primary side of the transformer increases with the increase of period, and eventually produces oscillation. The oscillation frequency of this disturbance is half of the switching frequency, so it is called subharmonic oscillation. For this reason, the slope compensation technology is introduced to suppress subharmonic oscillation.


## 2.3. Limited Soft-Switching Range of PSFB DC/DC Converter

The switching process of PSFB DC/DC converter is realized by resonance, so it is not instantaneous to decrease the voltageVds from Vin to 0. If the dead time Td between the driving signals of the bridge arm switch is too short, the Vds will not be switched on before it is reduced to zero, and the switch will lose its soft-switching characteristic; if the dead time Td is too long, the two switches will be switched on. When the terminal voltage Vds drops to 0, the switch fails to turn on in time. The Vds rises again through resonance, and the switch also loses its soft-switching characteristic. Thus, the soft-switching range of vehicle charging power supply is severely limited under the condition of constant voltage charging mode and wide load current variation. Therefore, an automatic dead-time control technology is proposed to realize a wide range of soft-switching.


## 3. Peak Current Mode Slope Compensation Analysis

### 3.1. Slope Compensation Technology

Subharmonic oscillation can be avoided by introducing slope compensation. That is to say, the slope signal with slopem is subtracted from the current loop control Ve. The change of ip disturbance of the primary current of the transformer with slope compensation is shown in Figure 2. The solid line represents its steady-state waveform and the dotted line represents the waveform after disturbance.Figure 2
Waveform of primary currentip  of the transformer before and after disturbance.As can be seen from Figure2, when there is a current disturbance, its variation is(1)ΔIn+1ΔIn=m2−mm1−2m2−mfm+m3mf+m1,where,ΔIn is the nth current disturbance at the end of the natural flow. m1=Vin/Lr; m2=VD+Vmos/Lr (VD and Vmos are on-voltage drop of diode and MOS respectively); m3=Vin−NVo/N2Lr+Lr; mf=Vo/NLf;m is slope of slope compensation current.When there is a current disturbance, the necessary condition for system stability is(2)ΔIn+1ΔIn<1.According to expression (1), (2), when m=0–2m2, the disturbance can be suppressed, and when m=2m2, the current disturbance can be completely suppressed.


### 3.2. Small-Signal Model of PSFB DC/DC Converter

The small-signal modeling of PSFB DC/DC converter has been done by foreign scholars. Two important transfer functions are given in reference [11].The transfer function of the control variabled̂s to the output voltage v̂os is(3)Gvds=Vin/Ns2LfCf+sLf/R+RdCf+Rd/R+1.The transfer function of the control variabled̂s to the sampling current îLs is(4)Gids=s2LfCf+sLf/R+RCf+1Vin/NRs2LfCf+sLf/R+RdCf+Rd/R+1,where,Rd=2Lrfr/Ns2,fr=Ts/2.


### 3.3. Feedback Loop Transfer Function

In the peak current control mode, the duty cycle changes caused by the disturbance of the original current and output voltage errors of the transformer with slope compensation are shown in Figures3 and 4, respectively.Figure 3
Duty cycle change caused by primary current disturbance.Figure 4
Duty cycle change caused by output voltage error disturbance.The duty cycle of the transformer caused by current disturbanceΔIL is ΔD, Fis is defined as the current loop feedback function, and Rs is the equivalent sampling resistance.(5)Fis=D̂ÎL=ΔDΔIL=Rsfsm+m3.The change in the duty cycle caused by the disturbanceΔVe of error voltage Ve is ΔD. FVs can be obtained from Figure 5.(6)FVs=D̂V̂e=ΔDΔV=fsm+m3.Figure 5
Block diagram of peak current mode control system.DefineFV′(s) as feedback function of voltage loop, and Gcs as transfer function of voltage loop compensation network, then(7)FV′s=fsm+m3Gcs.


### 3.4. Transfer Function of Control System

The small-signal model of peak current mode control system with slope compensation is shown in Figure5. Kvof is the output voltage feedback coefficient.PI regulator is used in the voltage outer loop, that is, the transfer function of compensation networkGcs is(8)GCs=Kpi+Kiis.The open-loop transfer functionGos of peak current control is obtained as follows(9)Gos=FVsGCsKvof·Gvds1+FisGids.After substituting the parameters in Table1, the PI coefficients are calculated as Kpi=0.524 and Kii=11900 according to the requirements of the open-loop frequency characteristics of the control system. Figure 6 shows BODE diagrams before and after current open-loop transfer function compensation. The open-loop cut-off frequency before compensation is much larger than the switching frequency, and the open-loop amplitude-frequency characteristic passes through the zero decibel line with −40dB/dec, so the system is very unstable. After compensation, the open-loop amplitude-frequency characteristic passes through the zero decibel line with −20dB/dec, the cut-off frequency is 10.22 kHz, and the phase margin is 164-degree stable.Table 1
Design parameters of DC/DC converters.
Parameter
Value
Rated input voltageVin/V
300–500
Output voltageVo/V
12
Output currentIo/A
50
Transformer ratioN
21
Resonant inductanceLr/μH
26
Resonant capacitorCf/nF
7.5
Output filter inductorLf/μH
2
Switching frequencyfs/kHz
100Figure 6
BODE diagram before and after compensation.By using trapezoidal summation approximate integral link and the difference between two points approximate differential link, the analog PID controller is discretized to digital PID controller, and the digital PI control of voltage loop is realized by calling CNTL_ 2P2Z macromodule of DSP TMS320F28027. The macro module realizes second-order control by using bipolar and bi-zero points.


## 3.1. Slope Compensation Technology

Subharmonic oscillation can be avoided by introducing slope compensation. That is to say, the slope signal with slopem is subtracted from the current loop control Ve. The change of ip disturbance of the primary current of the transformer with slope compensation is shown in Figure 2. The solid line represents its steady-state waveform and the dotted line represents the waveform after disturbance.Figure 2
Waveform of primary currentip  of the transformer before and after disturbance.As can be seen from Figure2, when there is a current disturbance, its variation is(1)ΔIn+1ΔIn=m2−mm1−2m2−mfm+m3mf+m1,where,ΔIn is the nth current disturbance at the end of the natural flow. m1=Vin/Lr; m2=VD+Vmos/Lr (VD and Vmos are on-voltage drop of diode and MOS respectively); m3=Vin−NVo/N2Lr+Lr; mf=Vo/NLf;m is slope of slope compensation current.When there is a current disturbance, the necessary condition for system stability is(2)ΔIn+1ΔIn<1.According to expression (1), (2), when m=0–2m2, the disturbance can be suppressed, and when m=2m2, the current disturbance can be completely suppressed.


## 3.2. Small-Signal Model of PSFB DC/DC Converter

The small-signal modeling of PSFB DC/DC converter has been done by foreign scholars. Two important transfer functions are given in reference [11].The transfer function of the control variabled̂s to the output voltage v̂os is(3)Gvds=Vin/Ns2LfCf+sLf/R+RdCf+Rd/R+1.The transfer function of the control variabled̂s to the sampling current îLs is(4)Gids=s2LfCf+sLf/R+RCf+1Vin/NRs2LfCf+sLf/R+RdCf+Rd/R+1,where,Rd=2Lrfr/Ns2,fr=Ts/2.


## 3.3. Feedback Loop Transfer Function

In the peak current control mode, the duty cycle changes caused by the disturbance of the original current and output voltage errors of the transformer with slope compensation are shown in Figures3 and 4, respectively.Figure 3
Duty cycle change caused by primary current disturbance.Figure 4
Duty cycle change caused by output voltage error disturbance.The duty cycle of the transformer caused by current disturbanceΔIL is ΔD, Fis is defined as the current loop feedback function, and Rs is the equivalent sampling resistance.(5)Fis=D̂ÎL=ΔDΔIL=Rsfsm+m3.The change in the duty cycle caused by the disturbanceΔVe of error voltage Ve is ΔD. FVs can be obtained from Figure 5.(6)FVs=D̂V̂e=ΔDΔV=fsm+m3.Figure 5
Block diagram of peak current mode control system.DefineFV′(s) as feedback function of voltage loop, and Gcs as transfer function of voltage loop compensation network, then(7)FV′s=fsm+m3Gcs.


## 3.4. Transfer Function of Control System

The small-signal model of peak current mode control system with slope compensation is shown in Figure5. Kvof is the output voltage feedback coefficient.PI regulator is used in the voltage outer loop, that is, the transfer function of compensation networkGcs is(8)GCs=Kpi+Kiis.The open-loop transfer functionGos of peak current control is obtained as follows(9)Gos=FVsGCsKvof·Gvds1+FisGids.After substituting the parameters in Table1, the PI coefficients are calculated as Kpi=0.524 and Kii=11900 according to the requirements of the open-loop frequency characteristics of the control system. Figure 6 shows BODE diagrams before and after current open-loop transfer function compensation. The open-loop cut-off frequency before compensation is much larger than the switching frequency, and the open-loop amplitude-frequency characteristic passes through the zero decibel line with −40dB/dec, so the system is very unstable. After compensation, the open-loop amplitude-frequency characteristic passes through the zero decibel line with −20dB/dec, the cut-off frequency is 10.22 kHz, and the phase margin is 164-degree stable.Table 1
Design parameters of DC/DC converters.
Parameter
Value
Rated input voltageVin/V
300–500
Output voltageVo/V
12
Output currentIo/A
50
Transformer ratioN
21
Resonant inductanceLr/μH
26
Resonant capacitorCf/nF
7.5
Output filter inductorLf/μH
2
Switching frequencyfs/kHz
100Figure 6
BODE diagram before and after compensation.By using trapezoidal summation approximate integral link and the difference between two points approximate differential link, the analog PID controller is discretized to digital PID controller, and the digital PI control of voltage loop is realized by calling CNTL_ 2P2Z macromodule of DSP TMS320F28027. The macro module realizes second-order control by using bipolar and bi-zero points.


## 4. Software Design of Digital PSFB DC/DC Converter

### 4.1. Digital Control System of Peak Current

The microcontroller uses TI’s TMS320F28027 because it has advanced on-chip control peripherals including enhanced ADC, on-chip analog comparator, DAC and high precision PWM generator. In addition, it also has a unique programmable on-chip slope compensator, which can provide slope compensation of at least 0.04 V/μs. At the same time, the software can adjust the dead time Td to achieve a wide range of soft-switching.The digital peak current control system is shown in Figure7. By sampling output voltage Voand primary current ip of transformer by ADC, the difference between output voltage Vo and reference voltage Vref are entered into the digital PI controller, slope compensation is added into DAC, compared with the primary current ip of transformer by analog comparator, PWM generator generate PWM signals to drive Q1–Q6. EPWM1A and ePWM1B drive switches Q1 and Q4; ePWM2A and ePWM2B drive switches Q2 and Q3; ePWM4A and ePWM4B drive SR tubes Q5 and Q6.Figure 7
Digital peak current control system.


### 4.2. Automatic Dead Zone Control Technology

Figure8 shows the half-cycle operating waveform of the proposed PSFB DC/DC converter, which is in turn the driving waveform of switch Q1–Q4, the primary current ip, the resonant inductance current iLr, the voltage VAB between the neutral points of the primary two arms, and the secondary voltage Vr. The dead time between the driving signals of the same bridge arm is Td.Figure 8
Operating waveforms of DC/DC converter.The equivalent circuit att0,t1 is shown in Figure 9. At t0, the switch Q1 is switched off. At this time, the resonant inductance Lr, the junction capacitor C1 of switch Q1, the junction capacitor C4 of switch Q4, and the junction capacitor C6 of SR Q6 resonate, C1 charges, and C4 and C6 discharge. The primary current ip and resonant inductance current iLr of transformer begin to decrease.Figure 9
The equivalent circuit att0,t1.At this point, the voltageVC1 of the switch Q1 junction capacitor C1 is(10)VC1t=Io′2C1+C6′t+C6′2C12C1+C6′Io′ω0sinω0,where,Io′ and C6′ are the equivalent values of output current Io and junction capacitance C6 of SR tube Q6 on the original side of transformer, respectively.(11)
ω
0
=
2
C
1
+
C
6
′
2
C
1
C
6
′
L
f
.Att1, the resonance ends, and at this time VC1=Vin, the resonance process time Tr is obtained by substitution (10). The larger Io′ and the smaller Tr, the shorter the dead time Td.Therefore, the dead-timeTd can be adjusted according to the load current Io, so that the switch can achieve a wide range of soft-switching, which is called automatic dead-time technology. Figure 10 is the automatic dead-zone task flow chart. First, the dead zone auto-adjustment flag auto_DB is detected, and if it is 1, the program is executed. The output current sampling is connected with ADC channel 9, and result register for ADC channel 9 is read to obtain the current load. The load range is divided into 12 cases according to the switch-case statement, corresponding to the leading-leg dead-time count value T_lead and the lagging-leg dead-time count value T_lag, respectively. By assigning T_lead (T_lag) to the rising-edge delay register DBRED and the falling-edge delay register DBFED of ePWM1 (ePWM2) module respectively, the dead-time of the leading-lag (lagging-leg) can be automatically adjusted.Figure 10
Automated dead zone task flow chart.


### 4.3. Implementation Mechanism of Digital PWM

The generation mechanism of the phase-shifted PWM signal is shown in Figure11. The on-chip analog comparator compares the primary current of the transformer with the peak current reference of slope compensation. The comparator output is connected to the PWM generator. The ePWM1 module is set up to run in the incremental and subtractive counting mode, while the other PWM modules run in the incremental counting mode.Figure 11
Implementation mechanism of digital PWM.After the interruption, the counting mode of the time-base control register TBCTL of the ePWM1 module is detected. When TBCTL is detected to be incremental mode, ePWM2A is forced to reset and ePWM2B is placed after the automatic dead time. When TBCTL is in the decrement mode, ePWM2B is forced to reset and ePWM2A is set after the automatic dead time. In this way, the phase shift control of ePWM2 module relative to the ePWM1 module is realized.The driving signal ofQ5Q6 of SR transistor is obtained by “or” logic from the driving signal of Q4Q1 of leading-leg and Q2Q3 of lagging-leg, so that the load current flows through the SR tube channel for the highest proportion of time, and the overall conduction loss is minimized.


## 4.1. Digital Control System of Peak Current

The microcontroller uses TI’s TMS320F28027 because it has advanced on-chip control peripherals including enhanced ADC, on-chip analog comparator, DAC and high precision PWM generator. In addition, it also has a unique programmable on-chip slope compensator, which can provide slope compensation of at least 0.04 V/μs. At the same time, the software can adjust the dead time Td to achieve a wide range of soft-switching.The digital peak current control system is shown in Figure7. By sampling output voltage Voand primary current ip of transformer by ADC, the difference between output voltage Vo and reference voltage Vref are entered into the digital PI controller, slope compensation is added into DAC, compared with the primary current ip of transformer by analog comparator, PWM generator generate PWM signals to drive Q1–Q6. EPWM1A and ePWM1B drive switches Q1 and Q4; ePWM2A and ePWM2B drive switches Q2 and Q3; ePWM4A and ePWM4B drive SR tubes Q5 and Q6.Figure 7
Digital peak current control system.


## 4.2. Automatic Dead Zone Control Technology

Figure8 shows the half-cycle operating waveform of the proposed PSFB DC/DC converter, which is in turn the driving waveform of switch Q1–Q4, the primary current ip, the resonant inductance current iLr, the voltage VAB between the neutral points of the primary two arms, and the secondary voltage Vr. The dead time between the driving signals of the same bridge arm is Td.Figure 8
Operating waveforms of DC/DC converter.The equivalent circuit att0,t1 is shown in Figure 9. At t0, the switch Q1 is switched off. At this time, the resonant inductance Lr, the junction capacitor C1 of switch Q1, the junction capacitor C4 of switch Q4, and the junction capacitor C6 of SR Q6 resonate, C1 charges, and C4 and C6 discharge. The primary current ip and resonant inductance current iLr of transformer begin to decrease.Figure 9
The equivalent circuit att0,t1.At this point, the voltageVC1 of the switch Q1 junction capacitor C1 is(10)VC1t=Io′2C1+C6′t+C6′2C12C1+C6′Io′ω0sinω0,where,Io′ and C6′ are the equivalent values of output current Io and junction capacitance C6 of SR tube Q6 on the original side of transformer, respectively.(11)
ω
0
=
2
C
1
+
C
6
′
2
C
1
C
6
′
L
f
.Att1, the resonance ends, and at this time VC1=Vin, the resonance process time Tr is obtained by substitution (10). The larger Io′ and the smaller Tr, the shorter the dead time Td.Therefore, the dead-timeTd can be adjusted according to the load current Io, so that the switch can achieve a wide range of soft-switching, which is called automatic dead-time technology. Figure 10 is the automatic dead-zone task flow chart. First, the dead zone auto-adjustment flag auto_DB is detected, and if it is 1, the program is executed. The output current sampling is connected with ADC channel 9, and result register for ADC channel 9 is read to obtain the current load. The load range is divided into 12 cases according to the switch-case statement, corresponding to the leading-leg dead-time count value T_lead and the lagging-leg dead-time count value T_lag, respectively. By assigning T_lead (T_lag) to the rising-edge delay register DBRED and the falling-edge delay register DBFED of ePWM1 (ePWM2) module respectively, the dead-time of the leading-lag (lagging-leg) can be automatically adjusted.Figure 10
Automated dead zone task flow chart.


## 4.3. Implementation Mechanism of Digital PWM

The generation mechanism of the phase-shifted PWM signal is shown in Figure11. The on-chip analog comparator compares the primary current of the transformer with the peak current reference of slope compensation. The comparator output is connected to the PWM generator. The ePWM1 module is set up to run in the incremental and subtractive counting mode, while the other PWM modules run in the incremental counting mode.Figure 11
Implementation mechanism of digital PWM.After the interruption, the counting mode of the time-base control register TBCTL of the ePWM1 module is detected. When TBCTL is detected to be incremental mode, ePWM2A is forced to reset and ePWM2B is placed after the automatic dead time. When TBCTL is in the decrement mode, ePWM2B is forced to reset and ePWM2A is set after the automatic dead time. In this way, the phase shift control of ePWM2 module relative to the ePWM1 module is realized.The driving signal ofQ5Q6 of SR transistor is obtained by “or” logic from the driving signal of Q4Q1 of leading-leg and Q2Q3 of lagging-leg, so that the load current flows through the SR tube channel for the highest proportion of time, and the overall conduction loss is minimized.


## 5. Digital PSFB DC/DC Converter Hardware Design

### 5.1. Drive Circuit Design

The source of the SR transistors Q5 and Q6 is connected to the output voltage GND, so GND is used as the reference driving circuit. The driver chip is selected as UCC27324, which can provide high peak current for capacitive load. The synchronous rectifier driver circuit is shown in Figure12. UCC27324 provides up to 4 A current in the Miler flat area during MOS switch switching. The full-bridge switch tube on the original side of the transformer is also driven by UCC27324, but transformer isolation must be provided.Figure 12
Synchronous rectification drive circuit schematic.


### 5.2. Sampling Circuit Design

The primary current ip of the transformer passes through the current transformer and is sampled by the resistor to obtain a voltage signal, which is sent to the AD sampling port. The current transformer adopts PE63587 with turn ratio of 1 : 100. Figure13 is the primary current sampling circuit of the transformer.Figure 13
Transformer primary current sampling circuit.The output voltage sampling circuit is shown in Figure14. The LV25-P of LEM company is selected as the voltage sensor. The current rating of the primary side of the sensor is l0 mA. When the rated output voltage Vo = 12 V and two 1 K/6 W current limiting resistors are connected in series on the primary side of the sensor, the current In1 = 6 mA on the primary side of the sensor is converted to the current In2 =15 mA on the secondary side of the sensor. Controller A/D detection range is 0–3.3 V, sampling resistance R3 =3 V/15 mA = 200. The poststage circuit is connected with a voltage tracker whose amplification factor is 1, and the operational amplifier chip adopts OP27GS. The output voltage of 12 V passes through DC resistance voltage divider and voltage tracker, and finally, the input value of AD sampling of 2.472 V is obtained.Figure 14
Output voltage sampling circuit.


## 5.1. Drive Circuit Design

The source of the SR transistors Q5 and Q6 is connected to the output voltage GND, so GND is used as the reference driving circuit. The driver chip is selected as UCC27324, which can provide high peak current for capacitive load. The synchronous rectifier driver circuit is shown in Figure12. UCC27324 provides up to 4 A current in the Miler flat area during MOS switch switching. The full-bridge switch tube on the original side of the transformer is also driven by UCC27324, but transformer isolation must be provided.Figure 12
Synchronous rectification drive circuit schematic.


## 5.2. Sampling Circuit Design

The primary current ip of the transformer passes through the current transformer and is sampled by the resistor to obtain a voltage signal, which is sent to the AD sampling port. The current transformer adopts PE63587 with turn ratio of 1 : 100. Figure13 is the primary current sampling circuit of the transformer.Figure 13
Transformer primary current sampling circuit.The output voltage sampling circuit is shown in Figure14. The LV25-P of LEM company is selected as the voltage sensor. The current rating of the primary side of the sensor is l0 mA. When the rated output voltage Vo = 12 V and two 1 K/6 W current limiting resistors are connected in series on the primary side of the sensor, the current In1 = 6 mA on the primary side of the sensor is converted to the current In2 =15 mA on the secondary side of the sensor. Controller A/D detection range is 0–3.3 V, sampling resistance R3 =3 V/15 mA = 200. The poststage circuit is connected with a voltage tracker whose amplification factor is 1, and the operational amplifier chip adopts OP27GS. The output voltage of 12 V passes through DC resistance voltage divider and voltage tracker, and finally, the input value of AD sampling of 2.472 V is obtained.Figure 14
Output voltage sampling circuit.


## 6. Experiment

According to the design requirements of the vehicle charging power supply, the experimental platform of PSFB DC/DC converter is built. The main experimental parameters are shown in Table1. The driving circuit, the detecting circuit, and the main circuit are as shown in Figure 15. The primary H-bridge of the transformer adopts the MOSFET module of the Infineon model SPP20N60CFD, and the SR tube adopts MOSFET module of the Fairchild Semiconductor model FDP032N08. Figure 16 shows the control board using Piccolo TMS320F28027.Figure 15
Driving circuit, detection circuit, and main circuit.Figure 16
Control circuit board.Figure17 shows the drain-source voltage VDS and driving voltage VGS waveforms of the lagging arm Q3 before and after dead-time Td adjustment under light load. It is difficult to turn on zero voltage for lagging leg Q3 when the dead time is 1 μs, as shown in Figure 17(a) . When the dead time is increased to 2 μs, the switch can achieve zero-voltage switching better, as shown in Figure 17(b). It shows that the soft switch with wide range can be realized by adding automatic dead-zone technology.Figure 17
The soft-switching waveform comparison of lagging armQ3 before and after dead-time Td adjustment under light load. (a) Td =1 μs and (b) Td =2 μs.
(a)
(b)In the case of rated input voltageVin = 400 V, Figure 18(a) is the waveforms of output voltage and output current when the load changes from 0% to 80%, and Figure 18(b) is the waveforms of output voltage and output current when the load changes from 80% to 0%. From the analysis in the figure, it can be seen that for the step change of 80% in the load, the output peak deviation can be less than 3% of the rated output, and the stabilization time is about 240 μs, which has good dynamic performance and antiinterference ability.Figure 18
Output voltage and output current waveforms when the load is abrupt. (a) 0–80% load mutation and (b) 80–0% load mutation.
(a)
(b)The relationship between load and efficiency under different input voltages are shown in Figure19. It can be seen that when the maximum input voltage is 500 V, the rated voltage is 400 V, and the minimum input voltage is 300 V, the system efficiency is above 95% in the range of 10−100% load, which can achieve a wide output range of load current and is affected by the change of input voltage very little, and meets the charging requirements of the vehicle charging power supply.Figure 19
Relationship between load and efficiency at different input voltages.


## 7. Conclusion

Aiming at the problems of DC/DC converter, which is the core part of the electric vehicle charging power supply, a digital control system of PSFB DC/DC converter is designed, which adopts peak current mode control, introduces slope compensation to eliminate the subharmonic oscillation. Dynamic dead-time control technology is proposed, which realizes a wide range of soft-switching, reduces switching losses and improves power supply efficiency. Experiments show that system efficiency is above 95% in the range of 10–100% load. The digital phase-shifting control based on TMS320F28027 is used to realize the step change of 80% in load, the peak deviation of output is less than 3% of rated output, and the stabilization time is less than 240 s, which improves the dynamic response speed and antiinterference ability of the digital control system.



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*Source: 2467307-2019-12-24.xml*