# A Novel TRNG Based on Traditional ADC Nonlinear Effect and Chaotic Map for IoT Security and Anticollision

Authors: Gang Li; Haoyang Sun; Peiqi Wu; Yuedan Zhou; Xiaochuan Fang; Zhenbing Li; Jian Li; Yongjun Huang; Guangjun Wen
Journal: Security and Communication Networks
 (2021)

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## Abstract

In the rapidly developing Internet of Things (IoT) applications, how to achieve rapid identification of massive devices and secure the communication of wireless data based on low cost and low power consumption is the key problem to be solved urgently. This paper proposes a novel true random number generator (TRNG) based on ADC nonlinear effect and chaotic map, which can be implemented by traditional processors with built-in ADCs, such as MCU, DSP, ARM, and FPGA. The processor controls the ADC to sample the changing input signal to obtain the digital signalDADC and then extracts some bits of DADC to generate the true random number (TRN). At the same time, after a delay based on DADC, the next time ADC sampling is carried out, and the cycle continues until the processor stops generating the TRN. Due to the nonlinear effect of ADC, the DADC obtained from each sampling is stochastic, and the changing input signal will sharply change the delay time, thus changing the sampling interval (called random interval sampling). As the input signal changes, DADC with strong randomness is obtained. The whole operation of the TRNG resembles a chaotic map, and this method also eliminates the pseudorandom property of chaotic map by combining the variable input signal (including noise) with the nonlinear effect of ADC. The simulation and actual test data are verified by NIST, and the verification results show that the random numbers generated by the proposed method have strong randomness and can be used to implement TRNG. The proposed TRNG has the advantages of low cost, low power consumption, and strong compatibility, and the rate of generating true random number is more than 1.6 Mbps (determined by ADC sampling rate and processor frequency), which is very suitable for IoT sensor devices for security encryption algorithms and anticollision.


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## Body

## 1. Introduction

In recent years, random numbers (RNs) have been widely used in the fields of encryption algorithm, wireless communication, statistical analysis, and radio frequency identification (RFID) [1–10]. RNs can be divided into pseudorandom numbers (PRNs) [11] and true random numbers (TRNs) [12]. PRNs are realized by deterministic algorithms, which have periodic behaviors and can be completely repeated. Their randomness is determined by the complexity and computational accuracy of the algorithm [13]. TRNs are often derived from physical phenomena (such as thermal noise and scintillation noise) and realized by combining certain algorithms and postprocessing, which have truly unpredictable characteristics [14].With the rapid development of IoT technology, wireless sensor networks (WSNs) have been deeply studied and widely applied in various fields [15–21]. Due to the explosive growth of wireless communication equipment, the communication security has attracted more and more attention [22, 23]. It is known that the encryption algorithm can effectively improve the security performance of wireless communication system, and RNs play a very important role in the encryption algorithm [24]. Although PRNs do not require external circuits, as for deterministic algorithms, PRNs are very vulnerable to malicious attacks. Also, in WSNs, especially in wearable and implantable systems, the design of low-power and low-resource consuming structures is crucial, because it can extend the longevity of batteries or lengthen the distance of wireless communication between passive sensing nodes. To improve the security performance of the wireless communication in an effective method, it is obligatory to design a special true random number generator (TRNG) applied to sensing nodes.The noise of analog circuit is used as the entropy source, making TRNG extremely susceptible to noise. According to the manifestation form of noise, the structure of TRNG can be divided into three categories, as shown in Figure1: (1) comparison structure based on thermal noise [25–27]; (2) beat frequency detection (BFD) structure based on clock jitter [28–32]; (3) ADC residual recycling structure [33–39], also known as chaotic map. In Figure 1, the red dotted part can be omitted.Figure 1
Architecture of TRNG. (a) Comparing the noise, (b) beat frequency detect, and (c) ADC chaotic map.
(a)(b)(c)The noise comparison structure harvests the random information of the entropy source (resistance thermal noise) with comparators (equivalent to 1-bit ADC) and converts the noise signal into a random sequence. The noise must be amplified to a certain level to meet the accuracy requirements of the comparator/ADC. In order to make the amplified noise output as white as possible, a high-gain and wide-bandwidth amplifier is required. This amplifier has high power and cost, and it is not suitable for low power or low cost equipment.The BFD structure harvests the random information of an entropy source (clock jitter noise of an oscillator) with a register, which is a common method to realize TRNs. This method requires the use of custom chip or Field Programmable Gate Array (FPGA) [40–44]. BFD is a more reliable noise sampling technique compared to noise comparison. However, due to the oscillator jitter is insufficient, the generated data is not random enough. Moreover, two continuously oscillating clocks are energy engulfing, resulting in the increase of the power consumption of the system. Furthermore, the structure also requires special chips or FPGA. In other words, it not only increases the cost and power consumption of the system, but also has finite applications, as it cannot be used in MCU, DSP, ARM, and other traditional microprocessors.The ADC based on residual recycling structure takes the quantization error of the ADC as its next input signal. After several iterations, the RNs of the ADC output show completely different characteristics. This is exactly the property of chaotic map—a small change of the input signal leads to an utterly distinctive output. Therefore, the structure based on ADC nonlinear chaotic map, which has been widely investigated, can be a desirous alternative for the generation of TRNs. Literature [1] proposed the use of SAR ADC and dynamic residual amplifiers to achieve TRNG. This method reduces the power consumption of the system through selective activation of the fine-SAR ADC by coarse-SAR ADC. Literature [26] proposed a method to realize TRNG by combining resistive thermal noise, oscillator sampling, and discrete time chaotic systems, and its performance is better than the TRNG realized by these three methods alone. In [33–36], multiple ADCs were proposed to realize TRNG using pipeline architecture. In each level, ADC used a resolution of 1.5 bits, and the residual signal output of the previous level becomes its new input. In literature [37], after the completion of the SAR ADC, the comparator was used to continue to compare the lowest bit (residual) of the ADC output once, and the comparison result was regarded as TRNs, so that the analog-to-digital conversion function and the TRNG can be completed at the same time. Pipeline ADC was also adopted in [2] in the realization of TRNG. Compared with [1, 33–35], a dynamic residual amplifier with a gain of less than 2 (1.9 for simulation) was used to avoid system oscillation. In addition, the bit shuffling technique was employed to replace the shift register so as to improve the statistical characteristics of the generated sequence.The previously mentioned methods of realizing TRNG based on ADC chaotic map are relatively complex to implement and requires special circuit structures. Its application for dedicated chips complexes the design and increases the expense of the system. Literature [25] introduces an approach to generate TRNs by the voltage value of ADC sampling resistance divider circuit using traditional MCU. The approach relies unduly on the resistance and the thermal noise of the circuit. If the thermal noise is low, and the ADC precision is not high enough, the ADC sampling output data shows slight or no changes, which makes it difficult to generate TRNs. Fortunately, literatures [38, 39] present a method to realize TRNG using a structure of combined traditional microprocessor and pipeline ADC. This is a typical example of realizing TRNG based on ADC chaotic map with microprocessors (as shown in Figure 1(c)). However, its structure is too complex to be used in low-power devices.To solve the above problems, this paper proposes a novel method for TRNG based on ADC nonlinear effect and chaotic map, which can be realized by either custom chips including programmable logic devices with ADC, such as FPGA, or traditional microprocessors such as MCU, DSP, and ARM. An RC circuit and the sensor circuit with RC function are used as the entropy source of TRNG. The processor controls the working state of the entropy source circuit (on or off), so that the entropy source circuit can output varying voltage signalVADC. The processor then controls the ADC to sample the VADC to obtain the digital signal DADC, which is used to generate TRNs. At the same time, the processor delays some time based on DADC, then continues to control ADC to obtain DADC, and generate TRNs afterwards. This cycle goes on until enough TRNs are generated. Because of the randomness of circuit noise, DADC also has a certain randomness, and the nonlinear effect of ADC can further increase the randomness of DADC. These two factors add great uncertainty to the proposed TRNG. Furthermore, changing input voltage (excluding noise) makes DADC change as well, and therefore, the sampling interval of ADC also has randomness based on the delay of DADC. In short, because of the changing input voltage VADC, random interval sampling further improves the randomness of DADC. The circuit noise and the nonlinear effect of ADC are used as the entropy source for the proposed TRNG, and the changing input voltage and the random interval sampling resemble a chaotic map, which further accelerates the changing process of the input signal, making DADC with extremely high randomness.The main innovation of this paper lies in the proposition of a mechanism with the combination of variable analog input signals and ADC random interval sampling, which is very suitable for low-power application scenarios, especially with WSN nodes. Wireless sensor network nodes need ADC to collect data and directly use the sensor circuit as the entropy source circuit of TRNG, which do not need to add any additional circuit. This results in an enormous reduction on the system design and manufacturing costs, as well as the power consumption.The rest of this paper is arranged as follows. Section2 analyzes chaotic systems. Section 3 elaborates in detail the mathematical model and implementation method of TRNG based on ADC. Section 4 introduces the simulation and verification of the proposed mathematical model. Section 5 proposed TRNG implementation and verification. Section 6 discusses TRNG applications. Section 7 concludes the papers with the value and the prospect of the work.


## 2. Random Analysis of Chaotic Map

In the chaotic map system, even if the initial conditions are slightly different, the system can produce completely different output results after multiple iterations [45]. Among the methods to implement chaotic map, the most widely used is the chaotic map based on 1D linear piecewise affine Markov (PWAM) [34, 46, 47]. To achieve a 1D linear PWAM map, the conditions in equation (1) must be satisfied [34]:(1)Xn+1=fXn,n=0,1,2,3,…,where n is the number of time steps (number of iterations), X0 is the initial state of the system, and Xn is the state of the system after n steps of iteration. And the domain of f (x) is the same as its range. A typical example to further explain how PWAM works can be illustrated as follows, where f (x) is defined as in(2)fx=3x+2.00001,if−1≤x<−12,x+1,if−12≤x<0,−2x+1.00001,if0≤x≤1.The definition domain off (x) is within [−1, 1], and 0.00001 in the map can avoid the situation, where the simulation data is always equal to the boundary value (similar to overflow of an actual circuit. It will lead to the degradation of the random quality of the system. Therefore, special treatment is needed to avoid the overflow). In the process of research, two slightly different initial values are used to observe how the output Xn of the PWAM map varies with the number of iterations. The first operated initial value X0 is 0.5, and the second X0 = 0.50001. The difference between the two initial values is 0.00001, and the number of iterations of each run is n = 100. The results of the two runs are shown in Figure 2.Figure 2
Sensitivity of chaotic maps to initial values.As can be seen, after 7 iterations,Xn starts to show obvious differences, and the differences become increasingly big as the number of iterations increases. This is sufficient to indicate that, even without noise, due to the limited precision of the system, long time of iterations entails the unpredictable characteristics of PWAM chaotic map, which is exactly what RNs featured by. Specifically, there are three essential criteria for RNs [48]:(1)
It looks random and can pass the random statistical tests.(2)
It is unrepeatable. Its next bit is an uncertainty between being 0 or 1, even if the algorithm that produces the sequence and any already produced number of sequences are known.(3)
It is unrepeatable. The obtained sequence is diverse, even with entirely identical input, under the circumstance of the same algorithm and hardware circuit.Compared with PRNs, which only require the first of the above criteria to be satisfied, TRNs demand all the listed three criterions to be simultaneously satisfied. Briefly speaking, the next symbol of a random number must be independent of the previously generated symbol, which is similar to a Markov process. This further illustrates that random number generators can be implemented by 1D linear PWAM chaotic map. In terms of PWAM chaotic maps, Bernoulli shift map is one of the most extensively used ones. It can be represented by equation (3), whose definition domain ranges between [0, 2]. When Nnoise = 0, its corresponding map is shown in Figure 3(a). When the initial value x0 is different, varying output sequences will be generated. In addition, the system has only two states, S0 and S1, and the state jump probability is 0.5, resembling the fair coin toss, as demonstrated in Figure 3(b), which corresponds to a true random system [35].(3)fxn=2xn+Nnoise,if0≤xn<1,2xn−2+Nnoise,if1≤xn≤2.Figure 3
Linear Markov map. (a) Corresponding linear Markov map; (b) Markov chain of the toss of an unbiased coin.
(a)(b)What must be noted is that TRNs cannot be achieved using PWAM alone, because PWAM is a deterministic system. In response, an unpredictable initial state for PWAM shall be provided. In real circuits, a common approach to provide the entropy source information for PWAM is to add some analog devices, such as diodes and transistors. The behavior of these analog devices might bring some minor changes under the influence of noise. It happens because PWAM is very sensitive to small inputs. Therefore, the combination of these analog devices and PWAM empowers the system to generate truly unpredictable behaviors, thus achieving TRNG. In equation (3), PWAM based on Bernoulli shift map can be employed to implement TRNG when Nnoise is not zero, and the noise comes from the circuit.In the 1D linear PWAM described above, its constraint range (domain) is [−1, 1] and [0, 2]. But in actual circuits, the output can easily exceed the constraint range, because of the influence of noises, which makes it difficult for the chaotic map to return to the normal map range, resulting in the degradation of the randomness quality of the system [49]. However, providing sufficient redundancy for the system state can effectively remove the constraint problem. A prevalent method is to implement Bernoulli shift map to eliminate the constraint problem by ADC [1, 2, 25, 26, 33, 35, 37–39]. However, previously described methods require special integrated circuits [1, 2, 26, 33, 35, 37], the addition of complex circuit structures to microprocessors [38, 39], or the input of noise with statistical characteristics [25]. All these methods would bring great limitations to the application of TRNG. Fortunately, to overcome the above challenges, this paper proposes a common circuit architecture of simple structure and low cost, which can be implemented either on a custom chip or on a traditional microprocessor (with embedded ADC).


## 3. The Structure of Proposed TRNG

The architecture of the proposed TRNG based on ADC nonlinear effect and chaotic map is shown in Figure4. It consists of an entropy source circuit and a microprocessor, where the microprocessor includes an ADC, a Memory, a True Random Number Generator Control (TRNGC) module, and configurable pins.Figure 4
The proposed true number generator based on ADC.The core of the entropy source circuit is an RC circuit (any other circuits with the same function of RC circuit can also be used), which is used to realize a changeable voltage signal.Vpower is controlled by TRNGC, and when Vpower is high (VCC), the RC circuit realizes charging function; when Vpower is low (Gnd), the RC circuit realizes discharging function. Therefore, by controlling Vpower, TRNGC controls the RC circuit to produce a constantly changing output voltage. ADC is also controlled by TRNGC in order to sample the produced changing output voltage signal, and because the sampling interval is random, the digital data has strong randomness. The biggest advantage of this architecture is that it can be used as a TRNG and a sensor information collecting (the entropy source circuit seen as the sensor circuit). As a result, when this method is used in sensor equipment of IoT, it is not necessary to add any hardware circuits, because the sensor equipment normally has general-purpose devices such as ADCs and sensors. Therefore, the TRNG proposed in this paper has strong compatibility and can be used in traditional circuit structures.


### 3.1. TRNG Working Principle

For a single-stage ADC withN-bit rounding-down, when the input signal is within the ideal conversion range, the output is(4)DADC=ADCV=2NVCCVADC,where DADC represents the digital output signal after ADC conversion, ADC⋅ represents ADC conversion function, ⋅ represents rounding-down operation, VCC represents the reference voltage of ADC, and VADC represents the input voltage of ADC. Equation (4) is the working principle of traditional ADC, and in this paper, the proposed TRNG implemented is based on traditional ADC, RC circuit, and random interval sampling mechanism. The following equation is used to express the map between the input and output of the entire system:(5)xn+1=Mxn,where M⋅ represents the map function of the proposed system, xn represents the input signal, and xn+1 represents the output signal of the map. Next, the expression of the map function of the proposed TRNG will be derived and discussed.In Figure4, assuming that when Vpower is high or low, the entropy source circuit realizes a simple RC charging or discharging function, and then the output voltage can be calculated as follows:(6)VADC=V0+Vpower−V0∗1−e−t/RC+Vnoise,Charge,V0∗e−t/RC+Vnoise,Discharge,where VADC represents the output voltage of the entropy source circuit, which is also the input voltage of ADC, Vpower represents the output voltage of MCU pin, RC represents the product of the equivalent resistance and equivalent capacitance of the entropy source circuit, and Vnoise represents the noise of the circuit. When t = 0, VADC = Vpower + Vnoise, thus VADC only changes with noise. When t ≥ 5RC, VADC output is stable, and if it is a charging process, VADC = Vpower + Vnoise; if it is a discharging process, VADC = Vnoise. The entropy source circuit can be treated as a resistor divider circuit when t = 0 or t ≥ 5RC (resistance is infinitely large and infinitely small). However, the entropy source information of the system input is only decided by noise [25], causing weak randomness (the traditional low precision ADC is hard to identify noises). Therefore, in order to improve the randomness, it is necessary to ensure that, during the ADC sampling process, the charge and discharge states must be switched for every 5RC duration. Another problem is that the value of RC changes in the actual circuit; thus, the charging and discharging time cannot be accurately controlled. Therefore, in order to prevent VADC from remaining a stable state, two thresholds are set: a high threshold (DHT) and a low threshold (DLT). When VADC surpasses DHT, the RC circuit begins to discharge, and when VADC reaches a value below DLT, the RC circuit begins to charge. The following equation can be used to express the state of the system after a long-time operation:(7)VADCk+1=VADCk+VADCpower−VADCk∗1−e−t/RC+VADCnoise,Charge,VADCk∗e−t/RC+VADCnoise,Discharge,where k represents the number of sampling times. From (7), it can be seen that VADCk+1 is affected by noise, as well as k and t. In other words, after the RC circuit starts charging or discharging, even if the initial VADC is unchanged (noise is ignored), the randomness of VADCk+1 can be improved through TRNG by controlling the value of Vpower and ADC sampling interval (time t). Additionally, with the increase of the number of iteration times k, a completely different data set VADCk+1,k>0 can be obtained, making the system have certain chaotic map characteristics. The microprocessor then converts VADCk+1 into a digital signal DADCk+1 through ADC and generates TRNs with high randomness using each converted DADCk+1. Furthermore, in (7), the randomness of the system can be further improved by controlling the charge and discharge conditions (charge and discharge threshold).


### 3.2. TRNG Implementation

In order to improve the performance of the proposed TRNG to generate TRNs, random numbers are used to generate threshold voltagesDHT and DLT. Moreover, a cyclic shift is performed on DADCk+1, and the lower 4 bits of the shifted data are used to generate TRNGs, which effectively improves the production efficiency of TRNG. The steps of implementation of the proposed TRNG to generate TRNs are as follows:(1)
Firstly, RNs, representing the number of digits of the random numbers to be generated, are determined,Vpower is set to high, and RN_sum is cleared. Then, TRN0, representing the last stored true random number, is extracted from a specific address to generate an initial random delay t0 based on (9).(2)
After the initial random delay,DADCk (firstly 0) is compared with DHT and DLT. When it is greater than DHT, set Vpower to 0, and the entropy source circuit starts to discharge; when it is less than DLT, set Vpower to 1, and the entropy source circuit starts to charge.(3)
Next, the true random number TRNDADC is extracted from memory using the lower 8 bits of DADCk as the relative address. Then, using TRNDADC, a random interval delay tr is generated based on (10).(4)
After the random interval delay,VADC signal is sampled using ADC to obtain digital data DADCk+1. Based on DADCk+1, three generated TRNs are extracted from the memory, whose LSBs are then used to form 3-bit data, represented as SBS. Then, an SBS-bit cyclic shift is performed on DADCk+1 to obtain DADCSBS, and the last 4 bits are extracted to generate the TRNs(5)
Steps (3) and (4) 4 are repeated four times to obtain a 16-bit TRN before it is written to memory. The address of TRN is automatically added by 1 and copied to a specific address.(6)
Finally, whether to continue generating a new map is determined. If yes, skip to step 2; otherwise, the generated TRN is sent to the application module.The detailed workflow of the proposed TRNG is shown in Figure5, where RN_M is the number of cyclic sampling (here set to 4), and RN is the TRN from memory, used to generate DHT and DLT, which enables a changeable threshold function, resulting in effectively improved randomness of TRN.Figure 5
Flow chart for generating map.


### 3.3. Proposed TRNG Performance Analysis

In Figure5, the unit time of the initial random delay and random interval delay is the clock cycle of the microprocessor, and the initial random delay t0 is determined by the last generated TRN. The initial random delay follows the equation(8)t0=1fPTRN0&const1,where fP represents the frequency of the microprocessor, & represents the bitwise AND, and const1 represents a constant number. For example, const1 = 15 (indicating F in hexadecimal notation). Therefore, TRN0 & const1 represents the extraction of the last four digits of TRN0.Similarly, the random interval delay follows the equation(9)tr=1fPTRNDADC&const2,where DADC represents the output signal after ADC sampling, whose lowest 8 bits are used as the relative address to extract the TRN of the corresponding address in the memory (indicated by TRNDADC), and const2 represents a constant, similar to const1.Before and after ADC sampling, the microprocessor needs a certain amount of timetp to process data (determined by the working frequency and the number of clock cycles). Assuming that the microprocessor takes cnt clock cycles in total to process data, then(10)tP=cntfP.Therefore, according to (5)∼(11), and taking k = 0 into consideration, the equation of VADCk+1 with ADC sampling times can be obtained as follows:(11)VADCk+1=MVADCk=VADCpower1−e−t0+tr+tp/RC+VADCnoise,if∗1,VADCkl+VADCpower−VADCkl1−e−∑i=k1+1ktri+ts+tp/RC+VADCnoise,if∗2,VADCkh∗e−∑i=kh+1ktri+ts+tp/RC+VADCnoise,if∗3,where ts represents the time consumed by ADC to achieve digital-to-analog conversion, ∗1 represents k = 0, ∗2 represents DADCkl<DLT & DADCk<DHT, and ∗3 represents DADCkh>DHT&DADCk>DLT⋅VADCkl and VADCkh represent the input voltage values of ADC when DADCkl<DLT and DADCkh>DHT, respectively. Equation (11) shows the map relationship between VADCk+1 and VADCk (DADCk+1 and DADCk in the microprocessor), which is similar to 1D linear piecewise affine Markov. Noise Vnoise directly affects DADCk+1, and the randomness of DADCk+1 is further improved by Vnoise through the parameters t0, tr, VLTandVHT. Furthermore, from the character of ADC and (4), it can be derived that DADC, the output signal of ADC, has certain nonlinear characteristics and quantization errors, which will also increase the randomness of DADCk+1. Therefore, using the map in (11) to implement TRNG has more randomness than using the periodic sampling level fixed in ADC [25] (only noise changes).According to (11), the time required for ADC to sample k times is(12)t=t0+k∗tr+tp+ts.Taking TMS320F2803x, a microprocessor on the market, for example, its sampling frequency can reach 3 MHz, and its main frequency can reachfp = 60 MHz (other microprocessors, such as DSP and ARM, have higher sampling frequencies and main frequencies that can further improve the efficiency of TRNG to generate map). The processing consumes about 60 clock cycles, and after testing, when const1 = const2 = 63, the randomness basically meets the requirements. When the lowest 6 bits of TRN0 and TRNDADC are 1, the time consumed is the longest, which takes 16 clock cycles. Then, the time can be calculated as(13)t=63fp+k∗63fp+60fp+1fs=6360+k∗6360+1+13.Whenk = 1, the result is 3.43 us, which is 0.29 Mbps. That is, the slowest rate of the generating map is 0.29 Mbps. Similarly, the average rate of generating map is calculated to be 0.42 Mbps (TRN0 and TRNDADC both take half of their maximum value). Every time a 4-bit true random number is generated for each sampling (Section 5 will verify its feasibility), it can be obtained that the proposed TRNG generates a true random number at a rate of about 1.68 Mbps.


## 3.1. TRNG Working Principle

For a single-stage ADC withN-bit rounding-down, when the input signal is within the ideal conversion range, the output is(4)DADC=ADCV=2NVCCVADC,where DADC represents the digital output signal after ADC conversion, ADC⋅ represents ADC conversion function, ⋅ represents rounding-down operation, VCC represents the reference voltage of ADC, and VADC represents the input voltage of ADC. Equation (4) is the working principle of traditional ADC, and in this paper, the proposed TRNG implemented is based on traditional ADC, RC circuit, and random interval sampling mechanism. The following equation is used to express the map between the input and output of the entire system:(5)xn+1=Mxn,where M⋅ represents the map function of the proposed system, xn represents the input signal, and xn+1 represents the output signal of the map. Next, the expression of the map function of the proposed TRNG will be derived and discussed.In Figure4, assuming that when Vpower is high or low, the entropy source circuit realizes a simple RC charging or discharging function, and then the output voltage can be calculated as follows:(6)VADC=V0+Vpower−V0∗1−e−t/RC+Vnoise,Charge,V0∗e−t/RC+Vnoise,Discharge,where VADC represents the output voltage of the entropy source circuit, which is also the input voltage of ADC, Vpower represents the output voltage of MCU pin, RC represents the product of the equivalent resistance and equivalent capacitance of the entropy source circuit, and Vnoise represents the noise of the circuit. When t = 0, VADC = Vpower + Vnoise, thus VADC only changes with noise. When t ≥ 5RC, VADC output is stable, and if it is a charging process, VADC = Vpower + Vnoise; if it is a discharging process, VADC = Vnoise. The entropy source circuit can be treated as a resistor divider circuit when t = 0 or t ≥ 5RC (resistance is infinitely large and infinitely small). However, the entropy source information of the system input is only decided by noise [25], causing weak randomness (the traditional low precision ADC is hard to identify noises). Therefore, in order to improve the randomness, it is necessary to ensure that, during the ADC sampling process, the charge and discharge states must be switched for every 5RC duration. Another problem is that the value of RC changes in the actual circuit; thus, the charging and discharging time cannot be accurately controlled. Therefore, in order to prevent VADC from remaining a stable state, two thresholds are set: a high threshold (DHT) and a low threshold (DLT). When VADC surpasses DHT, the RC circuit begins to discharge, and when VADC reaches a value below DLT, the RC circuit begins to charge. The following equation can be used to express the state of the system after a long-time operation:(7)VADCk+1=VADCk+VADCpower−VADCk∗1−e−t/RC+VADCnoise,Charge,VADCk∗e−t/RC+VADCnoise,Discharge,where k represents the number of sampling times. From (7), it can be seen that VADCk+1 is affected by noise, as well as k and t. In other words, after the RC circuit starts charging or discharging, even if the initial VADC is unchanged (noise is ignored), the randomness of VADCk+1 can be improved through TRNG by controlling the value of Vpower and ADC sampling interval (time t). Additionally, with the increase of the number of iteration times k, a completely different data set VADCk+1,k>0 can be obtained, making the system have certain chaotic map characteristics. The microprocessor then converts VADCk+1 into a digital signal DADCk+1 through ADC and generates TRNs with high randomness using each converted DADCk+1. Furthermore, in (7), the randomness of the system can be further improved by controlling the charge and discharge conditions (charge and discharge threshold).


## 3.2. TRNG Implementation

In order to improve the performance of the proposed TRNG to generate TRNs, random numbers are used to generate threshold voltagesDHT and DLT. Moreover, a cyclic shift is performed on DADCk+1, and the lower 4 bits of the shifted data are used to generate TRNGs, which effectively improves the production efficiency of TRNG. The steps of implementation of the proposed TRNG to generate TRNs are as follows:(1)
Firstly, RNs, representing the number of digits of the random numbers to be generated, are determined,Vpower is set to high, and RN_sum is cleared. Then, TRN0, representing the last stored true random number, is extracted from a specific address to generate an initial random delay t0 based on (9).(2)
After the initial random delay,DADCk (firstly 0) is compared with DHT and DLT. When it is greater than DHT, set Vpower to 0, and the entropy source circuit starts to discharge; when it is less than DLT, set Vpower to 1, and the entropy source circuit starts to charge.(3)
Next, the true random number TRNDADC is extracted from memory using the lower 8 bits of DADCk as the relative address. Then, using TRNDADC, a random interval delay tr is generated based on (10).(4)
After the random interval delay,VADC signal is sampled using ADC to obtain digital data DADCk+1. Based on DADCk+1, three generated TRNs are extracted from the memory, whose LSBs are then used to form 3-bit data, represented as SBS. Then, an SBS-bit cyclic shift is performed on DADCk+1 to obtain DADCSBS, and the last 4 bits are extracted to generate the TRNs(5)
Steps (3) and (4) 4 are repeated four times to obtain a 16-bit TRN before it is written to memory. The address of TRN is automatically added by 1 and copied to a specific address.(6)
Finally, whether to continue generating a new map is determined. If yes, skip to step 2; otherwise, the generated TRN is sent to the application module.The detailed workflow of the proposed TRNG is shown in Figure5, where RN_M is the number of cyclic sampling (here set to 4), and RN is the TRN from memory, used to generate DHT and DLT, which enables a changeable threshold function, resulting in effectively improved randomness of TRN.Figure 5
Flow chart for generating map.


## 3.3. Proposed TRNG Performance Analysis

In Figure5, the unit time of the initial random delay and random interval delay is the clock cycle of the microprocessor, and the initial random delay t0 is determined by the last generated TRN. The initial random delay follows the equation(8)t0=1fPTRN0&const1,where fP represents the frequency of the microprocessor, & represents the bitwise AND, and const1 represents a constant number. For example, const1 = 15 (indicating F in hexadecimal notation). Therefore, TRN0 & const1 represents the extraction of the last four digits of TRN0.Similarly, the random interval delay follows the equation(9)tr=1fPTRNDADC&const2,where DADC represents the output signal after ADC sampling, whose lowest 8 bits are used as the relative address to extract the TRN of the corresponding address in the memory (indicated by TRNDADC), and const2 represents a constant, similar to const1.Before and after ADC sampling, the microprocessor needs a certain amount of timetp to process data (determined by the working frequency and the number of clock cycles). Assuming that the microprocessor takes cnt clock cycles in total to process data, then(10)tP=cntfP.Therefore, according to (5)∼(11), and taking k = 0 into consideration, the equation of VADCk+1 with ADC sampling times can be obtained as follows:(11)VADCk+1=MVADCk=VADCpower1−e−t0+tr+tp/RC+VADCnoise,if∗1,VADCkl+VADCpower−VADCkl1−e−∑i=k1+1ktri+ts+tp/RC+VADCnoise,if∗2,VADCkh∗e−∑i=kh+1ktri+ts+tp/RC+VADCnoise,if∗3,where ts represents the time consumed by ADC to achieve digital-to-analog conversion, ∗1 represents k = 0, ∗2 represents DADCkl<DLT & DADCk<DHT, and ∗3 represents DADCkh>DHT&DADCk>DLT⋅VADCkl and VADCkh represent the input voltage values of ADC when DADCkl<DLT and DADCkh>DHT, respectively. Equation (11) shows the map relationship between VADCk+1 and VADCk (DADCk+1 and DADCk in the microprocessor), which is similar to 1D linear piecewise affine Markov. Noise Vnoise directly affects DADCk+1, and the randomness of DADCk+1 is further improved by Vnoise through the parameters t0, tr, VLTandVHT. Furthermore, from the character of ADC and (4), it can be derived that DADC, the output signal of ADC, has certain nonlinear characteristics and quantization errors, which will also increase the randomness of DADCk+1. Therefore, using the map in (11) to implement TRNG has more randomness than using the periodic sampling level fixed in ADC [25] (only noise changes).According to (11), the time required for ADC to sample k times is(12)t=t0+k∗tr+tp+ts.Taking TMS320F2803x, a microprocessor on the market, for example, its sampling frequency can reach 3 MHz, and its main frequency can reachfp = 60 MHz (other microprocessors, such as DSP and ARM, have higher sampling frequencies and main frequencies that can further improve the efficiency of TRNG to generate map). The processing consumes about 60 clock cycles, and after testing, when const1 = const2 = 63, the randomness basically meets the requirements. When the lowest 6 bits of TRN0 and TRNDADC are 1, the time consumed is the longest, which takes 16 clock cycles. Then, the time can be calculated as(13)t=63fp+k∗63fp+60fp+1fs=6360+k∗6360+1+13.Whenk = 1, the result is 3.43 us, which is 0.29 Mbps. That is, the slowest rate of the generating map is 0.29 Mbps. Similarly, the average rate of generating map is calculated to be 0.42 Mbps (TRN0 and TRNDADC both take half of their maximum value). Every time a 4-bit true random number is generated for each sampling (Section 5 will verify its feasibility), it can be obtained that the proposed TRNG generates a true random number at a rate of about 1.68 Mbps.


## 4. Simulation and Verification

The sources of randomness of the proposed TRNG in this paper mainly include (1) circuit noise, (2) ADC nonlinearity, (3) random interval sampling, and (4) varying input voltage (noise not included). Among them, circuit noise and ADC nonlinearity add uncertainty to the system, while random interval sampling and varying input voltage provide the system with the characteristics of chaotic map. The combination of the two can achieve high-performance TRNG. Since the ADC nonlinearity is an inherent characteristic of the chip (during simulation, only the quantization error of ADC is considered), we mainly simulate the performance of the proposed chaotic map and the performance of TRNG based on the map.


### 4.1. Performance Analysis of the Varied Input and Random Intervals

To simplify the analysis, a linear input signal with the slope of 1 is used to replace the RC circuit, and four different situations are simulated in order to analyze the performance of the proposed chaotic map. On the one hand, the four situations are divided into two by the input signal of ADC:(1)
A 1 V constant voltage superimposed with a 1 mV average noise,(2)
A linearly rising voltage with slope is 1 superimposed with a 1 mV average noise.On the other hand, the four situations are divided into two by the sampling frequency:(1)
ADC performs periodic sampling,(2)
ADC performs sampling at random intervals.In other words, the 4 simulation situations are as follows: (1)VADC = 1 + noise (without random intervals), (2) VADC = 1 + noise (with random intervals), (3) VADC = t + noise (without random intervals), and (4) VADC = t + noise (with random intervals). The lowest bit of DADC is used to generate random numbers, and 4∗106 bits of data are produced for each simulation situation. Finally, the randomness of the generated random numbers is verified using the U.S. National Institute of Standards and Technology (NIST) [50] test suite, and the results are shown in Table 1 (P≥0.01 indicates that the test is passed, “Pass” indicates that all subcases pass the test, and “Fail” is the opposite of pass). It can be seen from the table that when VADC = 1 + noise, the NIST verification result is very poor regardless of whether random intervals are added between ADC samples. When VADC = t + noise, and no random interval is added between ADC samples, the NIST verification result is also very poor, but the results are much better than those of the former situation. Furthermore, when VADC = t + noise, by adding random intervals between ADC samples, the results verified by NIST indicate the effectiveness of our proposed chaotic map in improving randomness.Table 1
True random number simulation verification results.
NIST- sts-2.1.2, randomness testVADC = 1 + noise (without random interval)VADC = 1 + noise (with random interval)VADC = t + noise (without random interval)VADC = t + noise (with random interval)Proposed TRNGP valueProp.P valueProp.P valueP valueProp.P valueProp.P valueFrequency<0.010/10<0.010/10<0.016/100.2133110/100.53414610/10Block frequency<0.015/10<0.013/100.35048510/100.73991810/100.12232510/10Cumulative sums 0<0.010/10<0.010/10<0.016/100.73991810/100.12232510/10Cumulative sums 1<0.010/10<0.010/10<0.016/100.91141310/100.5341469/10Runs<0.010/10<0.010/100.21330910/100.53414610/100.91141310/10Longest run<0.010/10<0.010/100.73991810/100.35048510/100.53414610/10Rank0.35048510/100.91141310/100.53414610/100.73991810/100.7399189/10FFT0.35048510/100.12232510/100.73991810/100.91141310/100.21330910/10Nonoverlapping templateFailFailFailFailFailPassPassPassPassPassOverlapping template<0.013/10<0.014/100.73991810/100.73991810/100.53414610/10Universal0.35048510/100.73991810/100.12232510/100.35048510/100.01791210/10Approximate entropy<0.010/10<0.010/100.35048510/100.73991810/100.53414610/10Random excursionsFailFailFailFail—Pass—Pass—PassRandom excursions variantFailFailFailFail—Pass—Pass—PassSerial 00.1223258/100.2133098/100.53414610/100.91141310/100.53414610/10Serial 10.12232510/100.35048510/100.3504859/100.06688210/100.91141310/10Linear complexity0.35048510/100.01791210/100.21330910/100.21330910/100.01791210/10In (1) and (2), because the input signal is fixed, only the circuit noise changes. However, the noise in the circuit is so small that the accuracy of the 12-bit ADC is not enough to sample the noise directly. As a result, the DADC sampled by ADC is almost fixed. In (3), because the input is changing, the nonlinear effect of ADC can result in a certain degree of randomness in DADC. From the results, it can be seen that the randomness in (3) is better than that in (1) and (2). However, because the input voltage is linearly changing in (3), it is difficult to drastically change the time interval of ADC sampling just relying on noise and nonlinear characteristics of ADC. Consequently, the interval of each ADC sampling does not change much, resulting in low randomness of DADC. In (4), a random interval is added, which can further influence the sampling interval based on DADC, so that the data of each sampled DADC is completely different, and true random numbers can be generated.


### 4.2. Performance Analysis of the Proposed TRNG

In the previous section, we have verified that the proposed chaotic map can effectively improve the system’s performance in generating random numbers. However, only the LSB output from ADC is used to generate random numbers (1 bit of random number is extracted after each ADC sampling), which is less efficient. In this section, the entropy source circuit of the proposed TRNG can use an RC circuit to obtain more than a simple linear function, and the randomness of the RC output signal is also improved by controlling it to constantly charge and discharge. In addition, this paper proposes to use cyclic shift to processDADC during postprocessing, and the lowest 4 bits of the processed data are used to generate the true random number, which can improve the efficiency of the TRNG greatly.In traditional data interaction, most of the methods use integer multiples of bytes for data interaction. In order to achieve generality, integers multiples of 16 bits are generated each time when true random numbers are generated. Since the lowest 4 bits ofDADC of each ADC sampling data are used to generate true random numbers, four times of ADC sampling is required to obtain a true random number of 4∗4 = 16 bits. The TRNG represented by (11) is simulated here, and its flow is shown in Figure 5, where m represents the number of ADC cycles, and RNs mean that at least bits true random number is generated each time. In Figure 5, sets m = 4 and RNs = 16, and the simulation algorithm is shown in Algorithm 1.Algorithm 1: TRNG simulation algorithm based on ADC nonlinear effect and chaotic map.
Input:m, RNs, const1, const2, SNR = 10^6Output: TRNs(1)
SetVpower high, for charging input voltage VADC(2)
Get TRN0 and calculate t0 based on (8)(3)
Dealy_function (t0) for initial delay(4)
Get RN base onDADC(5)
CalculateVHTandVLT based on RN, which is compared with DADC for charge or discharge VADC(6)
Get TRNDADC based on DADC, and calculate tr based on (9)(7)
Dealy_function (tr) for random delay(8)
ADC samples,DADC=⌊2NVin/Vcc⌋(9)
Get three RNs for SBS, andNADC right shift SBS bits(10)
Extract 4 LSBs from shiftedNADC for generating TRN(11)
If RN_M = mThenWrite TRN to memory and Jump to step 12ElseJump to step 6End If(12)
If RNs > RN_sum ThenExitElseJump to step 4End IfUnder the same initial conditions, which means that the inputVADC of ADC is 0, and the DADC0 [3 : 0] obtained from the first sampling of ADC are 0 and 3, respectively. Two simulations are conducted on Algorithm 1, each iterated 100 times. Figure 6 shows the lowest 4 bits of DADC. It can be seen from the figure that the output data of the two simulations are different, which implies that the proposed TRNG architecture has nonrepeatable characteristics. That is, even if the initial conditions are the same, DADC will be completely different due to circuit noise and ADC nonlinear characteristics. Furthermore, the simulation generated a 4∗106 bits random number, and the random numbers are verified using NIST. The verification results are shown in the “proposed TRNG” column in Table 1, which suggests that the proposed TRNG has good performance on the randomness of its output.Figure 6
Comparison ofDADC [3 : 0] between two simulations.It can be seen from the simulation results of Section4.1 and Section 4.2 that the changing input voltage and random interval sampling have the characteristics of chaotic map. Moreover, combining them with circuit noise and ADC nonlinearity can achieve high-performance and high-efficiency TRNG.


## 4.1. Performance Analysis of the Varied Input and Random Intervals

To simplify the analysis, a linear input signal with the slope of 1 is used to replace the RC circuit, and four different situations are simulated in order to analyze the performance of the proposed chaotic map. On the one hand, the four situations are divided into two by the input signal of ADC:(1)
A 1 V constant voltage superimposed with a 1 mV average noise,(2)
A linearly rising voltage with slope is 1 superimposed with a 1 mV average noise.On the other hand, the four situations are divided into two by the sampling frequency:(1)
ADC performs periodic sampling,(2)
ADC performs sampling at random intervals.In other words, the 4 simulation situations are as follows: (1)VADC = 1 + noise (without random intervals), (2) VADC = 1 + noise (with random intervals), (3) VADC = t + noise (without random intervals), and (4) VADC = t + noise (with random intervals). The lowest bit of DADC is used to generate random numbers, and 4∗106 bits of data are produced for each simulation situation. Finally, the randomness of the generated random numbers is verified using the U.S. National Institute of Standards and Technology (NIST) [50] test suite, and the results are shown in Table 1 (P≥0.01 indicates that the test is passed, “Pass” indicates that all subcases pass the test, and “Fail” is the opposite of pass). It can be seen from the table that when VADC = 1 + noise, the NIST verification result is very poor regardless of whether random intervals are added between ADC samples. When VADC = t + noise, and no random interval is added between ADC samples, the NIST verification result is also very poor, but the results are much better than those of the former situation. Furthermore, when VADC = t + noise, by adding random intervals between ADC samples, the results verified by NIST indicate the effectiveness of our proposed chaotic map in improving randomness.Table 1
True random number simulation verification results.
NIST- sts-2.1.2, randomness testVADC = 1 + noise (without random interval)VADC = 1 + noise (with random interval)VADC = t + noise (without random interval)VADC = t + noise (with random interval)Proposed TRNGP valueProp.P valueProp.P valueP valueProp.P valueProp.P valueFrequency<0.010/10<0.010/10<0.016/100.2133110/100.53414610/10Block frequency<0.015/10<0.013/100.35048510/100.73991810/100.12232510/10Cumulative sums 0<0.010/10<0.010/10<0.016/100.73991810/100.12232510/10Cumulative sums 1<0.010/10<0.010/10<0.016/100.91141310/100.5341469/10Runs<0.010/10<0.010/100.21330910/100.53414610/100.91141310/10Longest run<0.010/10<0.010/100.73991810/100.35048510/100.53414610/10Rank0.35048510/100.91141310/100.53414610/100.73991810/100.7399189/10FFT0.35048510/100.12232510/100.73991810/100.91141310/100.21330910/10Nonoverlapping templateFailFailFailFailFailPassPassPassPassPassOverlapping template<0.013/10<0.014/100.73991810/100.73991810/100.53414610/10Universal0.35048510/100.73991810/100.12232510/100.35048510/100.01791210/10Approximate entropy<0.010/10<0.010/100.35048510/100.73991810/100.53414610/10Random excursionsFailFailFailFail—Pass—Pass—PassRandom excursions variantFailFailFailFail—Pass—Pass—PassSerial 00.1223258/100.2133098/100.53414610/100.91141310/100.53414610/10Serial 10.12232510/100.35048510/100.3504859/100.06688210/100.91141310/10Linear complexity0.35048510/100.01791210/100.21330910/100.21330910/100.01791210/10In (1) and (2), because the input signal is fixed, only the circuit noise changes. However, the noise in the circuit is so small that the accuracy of the 12-bit ADC is not enough to sample the noise directly. As a result, the DADC sampled by ADC is almost fixed. In (3), because the input is changing, the nonlinear effect of ADC can result in a certain degree of randomness in DADC. From the results, it can be seen that the randomness in (3) is better than that in (1) and (2). However, because the input voltage is linearly changing in (3), it is difficult to drastically change the time interval of ADC sampling just relying on noise and nonlinear characteristics of ADC. Consequently, the interval of each ADC sampling does not change much, resulting in low randomness of DADC. In (4), a random interval is added, which can further influence the sampling interval based on DADC, so that the data of each sampled DADC is completely different, and true random numbers can be generated.


## 4.2. Performance Analysis of the Proposed TRNG

In the previous section, we have verified that the proposed chaotic map can effectively improve the system’s performance in generating random numbers. However, only the LSB output from ADC is used to generate random numbers (1 bit of random number is extracted after each ADC sampling), which is less efficient. In this section, the entropy source circuit of the proposed TRNG can use an RC circuit to obtain more than a simple linear function, and the randomness of the RC output signal is also improved by controlling it to constantly charge and discharge. In addition, this paper proposes to use cyclic shift to processDADC during postprocessing, and the lowest 4 bits of the processed data are used to generate the true random number, which can improve the efficiency of the TRNG greatly.In traditional data interaction, most of the methods use integer multiples of bytes for data interaction. In order to achieve generality, integers multiples of 16 bits are generated each time when true random numbers are generated. Since the lowest 4 bits ofDADC of each ADC sampling data are used to generate true random numbers, four times of ADC sampling is required to obtain a true random number of 4∗4 = 16 bits. The TRNG represented by (11) is simulated here, and its flow is shown in Figure 5, where m represents the number of ADC cycles, and RNs mean that at least bits true random number is generated each time. In Figure 5, sets m = 4 and RNs = 16, and the simulation algorithm is shown in Algorithm 1.Algorithm 1: TRNG simulation algorithm based on ADC nonlinear effect and chaotic map.
Input:m, RNs, const1, const2, SNR = 10^6Output: TRNs(1)
SetVpower high, for charging input voltage VADC(2)
Get TRN0 and calculate t0 based on (8)(3)
Dealy_function (t0) for initial delay(4)
Get RN base onDADC(5)
CalculateVHTandVLT based on RN, which is compared with DADC for charge or discharge VADC(6)
Get TRNDADC based on DADC, and calculate tr based on (9)(7)
Dealy_function (tr) for random delay(8)
ADC samples,DADC=⌊2NVin/Vcc⌋(9)
Get three RNs for SBS, andNADC right shift SBS bits(10)
Extract 4 LSBs from shiftedNADC for generating TRN(11)
If RN_M = mThenWrite TRN to memory and Jump to step 12ElseJump to step 6End If(12)
If RNs > RN_sum ThenExitElseJump to step 4End IfUnder the same initial conditions, which means that the inputVADC of ADC is 0, and the DADC0 [3 : 0] obtained from the first sampling of ADC are 0 and 3, respectively. Two simulations are conducted on Algorithm 1, each iterated 100 times. Figure 6 shows the lowest 4 bits of DADC. It can be seen from the figure that the output data of the two simulations are different, which implies that the proposed TRNG architecture has nonrepeatable characteristics. That is, even if the initial conditions are the same, DADC will be completely different due to circuit noise and ADC nonlinear characteristics. Furthermore, the simulation generated a 4∗106 bits random number, and the random numbers are verified using NIST. The verification results are shown in the “proposed TRNG” column in Table 1, which suggests that the proposed TRNG has good performance on the randomness of its output.Figure 6
Comparison ofDADC [3 : 0] between two simulations.It can be seen from the simulation results of Section4.1 and Section 4.2 that the changing input voltage and random interval sampling have the characteristics of chaotic map. Moreover, combining them with circuit noise and ADC nonlinearity can achieve high-performance and high-efficiency TRNG.


## 5. Implementation and Validation

The structure of the proposed TRNG in this paper is very simple and has strong compatibility. It is especially suitable for sensing equipment, in which the sensor circuit can be directly used as the entropy source circuit without adding any additional circuit. In order to demonstrate its compatibility and advantages in the field of WSN for the IoT, we implemented two proposed TRNG based on RFID tags of separated components:(1)
The entropy source circuit adopts a pure RC circuit, which is a general structure for the proposed TRNG. RC can be adjusted freely to improve the performance of the proposed, and its structure is shown in Figure7(a).(2)
The entropy source circuit adopts sensor circuit, which is a special structure by the proposed TRNG and is mainly used in sensing devices of the IoT. No additional circuit is needed, which greatly reduces the cost of TRNG, and its structure is shown in Figure7(b).Figure 7
The structure of the proposed TRNG. (a) The general structure of proposed TRNG. (b) A special general structure of proposed TRNG.
(a)(b)The TRNG, whose entropy source is based on RC circuit, is specially used to generate true random numbers (no other functions). The value of RC can be arbitrarily adjusted in order to get TRNG with good performance. The TRNG based on sensing circuit as entropy source is generally used in scenarios compatible with sensor functions. In such case, the sensor circuit is mainly used for sensing functions, while the TRNG is an incidental function, which can generate true random numbers without occupying any hardware resources, and with lower cost and simpler design.In this paper, the microprocessor MSP430 (embedded 12-bits ADC) [51] is used to implement the RFID Protocol and realize the software control of the TRNG. LDO provides a stable voltage to the sensor circuit, AMP is used to amplify the output signal of the sensor, TRNGC is the control module, and MEM is the built-in memory of the MSP430.The hardware object of the proposed TRNG is shown in Figure8, Figures 8(a) and 8(b) show the general RC structure and the sensor circuit for entropy source circuit, respectively. Here, Figure 8(b) is a special structure of the proposed TRNG, which can not only realize TRNG, but also realize the function of information sensing. Moreover, the true random number can be used to increase the reliability of the encryption algorithm, so as to further improve the communication security of wireless sensor network.Figure 8
The TRNG is based on RFID sensor tag. (a) Entropy source is RC circuit. (b) Entropy source is sensor circuit.
(a)(b)For TRNG based on sensor circuit, because the adjustable range of sensor circuit is small in order to realize sensing function, we use 1 bit of each ADC sample to realize the TRN, such as the 1st LSB, 2nd LSB, 3rd LSB, and 4th LSB of ADC output. In each case, random numbers of4∗106 bits are generated. The NIST verification results are shown in the column of the proposed TRNG (sensor circuit) in Table 2. It can be seen from the test results that the random numbers generated by the four situations have strong randomness. The verification results of the Approximate Entropy of the random number generated by 4th LSB are not good, which can also indicate that the randomness of the generated random number begins to weaken from the fourth bit of the ADC output. At the same time, we also implemented TRNG based on RC structure and adopted the proposed TRNGC process in III-B. The ADC is sampled once to generate 4 bits of true random numbers (which is more efficient than the sensor structure), and a total of 3∗107 bits of random numbers were generated. The results of NIST are shown in the column of the proposed TRNG (RC) in Table 2. It can be seen from the results that the proposed TRNG meets all the requirements of NIST test, indicating that the proposed method can be used to realize TRNG.Table 2
True random number test results.
NIST- sts-2.1.2, randomness testProposed TRNG (sensor circuit)Proposed TRNG (RC)1st LSB2nd LSB3rd LSB4th LSB1st∼4th-LSBs1st LSBP valueProp.P valueProp.P valueP valueProp.P valueProp.P valueFrequency0.73991810.96429510.63711910.53414610.6371191Block frequency0.1223250.80.73991810.53414610.91141310.1626061Cumulative sums 00.12232510.73991810.43727410.53414610.9114131Cumulative sums 10.5341460.90.43727410.53414610.73991810.2133091Runs0.5341460.90.27570910.43727410.21330910.0179120.95Longest run0.35048510.6371190.950.96429510.35048510.8343081Rank0.53414610.83430810.9114130.90.12232510.9642951FFT0.53414610.73991810.53414610.73991810.0251931Nonoverlapping templatePassPassPassPassPassPassPassPassPassPassOverlapping template0.35048510.83430810.3504850.90.73991810.5341461Universal0.9114130.90.21330910.83430810.35048510.0351740.95Approximate entropy0.12232510.12232510.4372741<0.010.90.0351740.9Random excursions—Pass—Pass—Pass—PassPassPassRandom excursions variant—Pass—Pass—Pass—PassPassPassSerial 00.53414610.63711910.16260610.73991810.0487161Serial 10.53414610.0909360.950.73991810.35048510.2757091Linear complexity0.06688210.43727410.21330910.35048510.7399181Table3 lists the performance comparison of a variety of TRNGs, as well as their compatibility in mainstream microprocessors such as MCU, DSP, ARM, and FPGA. It can be seen from the table that the proposed TRNG in this paper occupies the least resources, has low power consumption, and is very compatible. That is, it can be implemented in various processors or through simple dedicated chips. The proposed TRNG has great advantages in low power consumption, low cost, miniaturization, and strictly time-required application scenarios. Moreover, it is particularly suitable to be used in wireless sensor network sensor equipment without occupying additional circuit resources.Table 3
Performance comparison.
ParameterThis work[25][34][12][43][40][41]ResourcesRCRMulti ADCs836μm2141∼2387 LUT-FF300 ROs5 CLBsPower levelmAmAμAμAAAAMCUYesYesNoNoNoNoNoDSPYesYesNoNoNoNoNoARMYesYesNoNoNoNoNoFPGAYesYesNoNoYesYesYesChipYesYesYesYesYesYesYesNIST testPassN/APassPassPassPassPass∗RC is resistance and capacitance circuits; R is resistance. LUT-FF is Look Up, RO is ring oscillator, and CLB is configurable logical block.From the above equations, simulations, test results, and performance comparison, it can be seen that, based on the ADC nonlinear chaotic map method proposed in this paper, it can realize a TRNG, and compared with other existing TRNG, it has great advantages in terms of low power consumption, low cost, and strong compatibility.


## 6. Discussion

The proposed TRNG in this paper has the characteristics of low power consumption, low design complexity, and strong compatibility, which can be very convenient to be used in the field of security encryption and anticollision, especially in the passive sensor tags of the Internet of Things, which has the lowest power consumption.The proposed TRNG is used in secure encryption to improve secure communication performance of IoT. Taking an encryption algorithm for example, an initial F operation is shown in Figure9(a), where the F operation divides the input 16-bit data into four 4 bits and then performing four sub-F operations.Figure 9
F operation structure: (a) originalF operation; (b) improved F operation.
(a)(b)In order to improve the performance of the encryption algorithm, the input data and 16-bit TRNs are combined to perform a simple logical operation before F operation, as shown in Figure9(b), where 16-bit TRNs are generated by the proposed TRNG. TRN performs logical operation with 16-bit raw data to generate logic data, and function selection is used to select different logical operation operations. For example, if the logical operation is XOR operation, when TRN ≠ 0, logic data is different from raw data, which will result in cryptograph data being completely different from the original cryptograph data. However, when TRNs = 0, the original data is the same as logic data (raw data XOR 0). Therefore, the improved encryption algorithm in Figure 9(b) can not only improve the encryption performance, but also be compatible with the original encryption algorithm, with huge flexibility.The proposed TRNG can also be used in the anticollision field of RFID to improve the efficiency of multitag identification. For example, in ISO/IEC 18000-6 Type C Standard [52], the tag needs to implement pseudorandom number/true random number to implement the anticollision algorithm based on Q value, as shown in Figure 10.Figure 10
Structure of anticollision algorithm based on the proposed TRNG.The commands related to the anticollision algorithm include Query, QueryAdjust, and QueryRep. At the beginning of each inventory, the reader needs to send Query command to determine an initial Q value, and the tag uses the proposed TRNG in this paper to generate a 16-bit random number and intercept the Q-bits generating Ns. Finally, whether to return data can be determined according to whether the intercepted Q-bits data is 0, and when the intercepted Q-bits data is not zero, the reader needs to send QueryAdjust and QueryRep commands to control the tag to return the response data. Meanwhile, in the RFID protocol, QueryRep command has the least bits, so its time is the shortest but greater than 25μs. Since the proposed TRNG can generate true random numbers at a rate greater than 1.68 Mbps, the proposed TRNG can generate at least 42 bits of true random number in 25 μs. Also, in RFID protocol, there is a requirement to delay between T1 and T2, which can also be used to generate more TRNs with TRNG. As a result, the process meets the requirement to produce multiple RNGs needed for RFID communication.


## 7. Conclusion

This paper introduces the feasibility of using ADC to realize TRNG and analyzes the shortcomings of existing TRNG based on ADC. A novel TRNG based on ADC nonlinear effect and chaotic map is proposed, which can be realized by using traditional processors with ADC. When the ADC sampling frequency in the processor is 3 MHz, and the main frequency is 60 MHz, the proposed TRNG can generate TRNs at a rate of about 1.68 Mbps. The proposed TRNG for sensor tag does not need any additional circuit, which greatly reduces the cost and power consumption of the system. The simulation results show that the proposed structure can effectively improve the randomness of the system. From the test results of the two proposed TRNG, it can be seen that the proposed TRNG not only improves the versatility of the ADC-based TRNG, but also reduces the complexity of the system design, and therefore, it has a very high practical value. In future work, the proposed TRNG in this paper can be integrated into the RFID technology-based sensor tag (chip), which can speed up the construction of communication security in the IoT.



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*Source: 2439427-2021-10-23.xml*