# DC Performance Variations of SOI FinFETs with Different Silicide Thickness

Authors: Jun-Sik Yoon
Journal: Advances in Condensed Matter Physics
 (2018)

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## Abstract

DC performance and the variability ofn-type silicon-on-insulator dopant-segregated FinFETs with different silicide thickness (Tsili) are analyzed. DC parameters including threshold voltage, low-field-mobility-related coefficient, and parasitic resistance are extracted from Y-function method for the comparison of DC performance and variability, and the correlation analysis. All the devices show similar subthreshold characteristics, but the devices with thicker Tsili have greater threshold voltages. The devices with thicker Tsili suffer from the DC performance degradation and its greater variations because the Schottky barrier height at the NiSi/Si interface increases and fluctuates greatly. This effect is validated by greater threshold voltages, larger parasitic resistances, and high correlations among all the DC parameters for the thicker Tsili. The devices with thicker Tsili also have higher low-frequency noise because of larger parasitic resistances and their correlated mobility degradations. Therefore, the device with relatively thin Tsili is expected to have better DC performance and variability concerns.


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## Body

## 1. Introduction

Silicon-on-insulator (SOI) MOSFETs maintain short channel immunity successfully due to the absence of substrate leakage current [1]. SOI-based devices having fin-shaped [2], ultra-thin-body [3], or gate-all-around [4] channel regions attain great scalability without short channel degradation. Meanwhile, dopant-segregated SOI MOSFETs have been considered as one of the promising candidates due to their several advantages over the planar bulk MOSFETs: low Schottky barrier height (SBH) at the silicide/semiconductor interface, possibility of low-temperature process, and near-abrupt junction formation [5–9]. Not only MOSFETs but also tunneling FETs also utilize abrupt doping profile to enhance the band-to-band tunneling transport at the source/channel junction [10, 11].Two-step annealing process during silicidation was suggested to decrease the lateral excursion of silicide into the channel region [12]. The influence of NiPt thickness prior to silicidation on the DC performance of SOI MOSFETs has been studied [13]. Increasing the NiPt thickness increased the contact resistance due to the decreased interfacial area between silicide and semiconductor but decreased the variations of sheet resistance due to its full silicidation. In this regard, it is necessary to analyze both DC performance and its variability in the perspective of the silicidation for the nanoscale dopant-segregated SOI MOSFETs.Thus, DC performance and variations of SOI FinFETs with different silicide thickness (Tsili) were investigated. Then, the variability sources inducing the drain current (Ids) variations were studied using the correlation analysis. Low-frequency noise was also measured for the detailed analysis of the devices with different Tsili.


## 2. Materials and Methods

(100) undoped SOI with 140-nm-thick buried oxide (BOX) and 20-nm-thick top Si region was prepared. BOX overetching process was performed to define omega-shaped fin structure as shown in Figure 1(b) of [13]. After the formation of gate stack (HfO2, TiN, amorphous-Si), Arsenic dopants were implanted at extension regions to reduce the underlap resistance. After defining nitride spacer regions with the spacer length (Lsp) of 20 nm, low-energy implantation and annealing at 1070°C and 1.5 s were done for the source/drain (S/D) regions. Different from [13] where the NiPt with different thickness of 5 or 10 nm was deposited, the same 10-nm-thick NiPt (4% Pt) was deposited and annealed under two-step rapid thermal process (RTP) conditions to remove the unreacted NiPt in the middle. Instead, different RTP temperature and time conditions were used to form the NiSi with different Tsili of 8 and 10 nm. Otherwise, all the measured devices have the equivalent number of fins (Nfin) of 2, fin width (Wfin) of 40 nm, fin height (Hfin) of 20 nm, extension length (Lext) of 80 nm, and gate length (Lg) of 40 nm. The detailed process flow and device geometry are shown in [13].All the devices have the active regions with equivalent size and structure, so the differences of DC performances and the variations are induced mostly by differentTsili. Figure 1 shows the possible variability sources of the S/D regions. Uneven NiSi/Si interface [14] and random dopant fluctuation (RDF) [15, 16] can also fluctuate the contact resistivity and thus induce the DC performance variations. Different NiSi/Si contact area by different Tsili would also affect the DC performance and variations because typical transfer lengths, defined as the distances that carriers below the contact travel before entering into the contact, of SOI devices are in the order of 100 nm [17, 18], which is longer than Lext. Different RTP conditions involved with different Tsili can vary the device performance by statistical piping effect [19] or lateral encroachment of NiSi into the S/D extension regions [20]. To understand DC performance and its variations for different Tsili, their transfer characteristics were measured using Keithley 4200 semiconductor characterization system, whereas low-frequency noise was measured using HP 89410A vector signal analyzer.Figure 1
3D schematic diagram of the SOI FinFETs. Geometrical parameters such as gate length (Lg), spacer length (Lsp), extension length (Lext), and silicide thickness (Tsili) are also specified. Top left figure describes the real device structure, and red-colored phrases indicate the possible variability sources.


## 3. Results and Discussion

### 3.1. DC Performance and Variations at Different Silicide Thickness

I d s and transconductance (gm) of the 50 measured devices each with different Tsili of 8 and 10 nm are shown in Figure 2. Each wafer has a different Tsili, and the measured devices with each Tsili are at the same position of each wafer to minimize the die-to-die variations between two different Tsili. Gate voltage (Vgs) is swept from 0.0 to 1.3 V in steps of 0.02 V, and drain voltages (Vds) are 0.05 and 1.0 V. Red lines indicate the averages of Ids and gm for each Tsili. In both linear and saturation regimes, the devices with Tsili of 8 nm have greater DC performance by showing higher on-state currents (Ion), while the subthreshold characteristics for Tsili of 8 and 10 nm are similar. Figure 2(c) shows that all the devices with Tsili of 8 and 10 nm do not have ambipolar effects at high Vds of 1.0 V near the off-state, validating the absence of Schottky contact [13].Figure 2
DC performance and variations of the SOI FinFETs with theTsili of (a) 8 and (b) 10 nm at drain voltage (Vds) of 0.05 V and (c) 1.0 V. The number of measured devices is 50 for each Tsili.
(a) (b) (c)R o n   ( = V d s / I o n ) values of the 20 measured devices each with different Wfin and Tsili are shown in Figure S1. Ion are extracted at the gate overdrive voltage (Vgs-Vth_CCM) of 1.0 V, where Vth_CCM is the threshold voltage (Vth) extracted from constant current method (CCM) at Ith=Weff/Lg·10-7 A (Weff=Nfin·(2Hfin+Wfin)). The devices with Tsili of 8 nm have smaller Ron for all Wfin. But the difference of Ron between two different Tsili is smaller for greater Wfin because the ratio of the NiSi/Si contact area between two different Tsili decreases. Additionally, raised S/D structure would be beneficial to improve the DC performance by increasing the NiSi/Si contact area. But for raised S/D structure, likewise, thicker Tsili also decreases the contact area, increases the contact resistance, and thus degrades the DC performance [21].Several parameters from the transfer characteristics are extracted to analyze the DC performance variations:Vth, low-field-mobility-related coefficient (X0), and parasitic resistance (Rsd). Vth values are extracted using CCM or Y-function method [16, 22]. Vth_CCM is measured at Ith=Weff/Lg·10-8 A, whereas Vth from Y-function method (Vth_y) is extracted from the x-axis intercept of the linearly extrapolated curve as shown in Figure 3.Figure 3
Y-function variations of the SOI FinFETs with Tsili of 8 and 10 nm. Almost all the Y-functions satisfy the linearity condition in the strong inversion regime.The simple and general expression ofIds at low Vds in the strong inversion regime is given by(1)Ids=X0·Vgs-Vth_y·Vds-IdsRsd,where X0 is defined as μeff·Cox·Weff/Lg (μeff is effective mobility and Cox is oxide capacitance). Y-function is simply expressed as(2)Y≡Idsgm=X0·Vds-IdsRsd·Vgs-Vth_y.According to (2), Y-function is linear in the strong inversion regime if X0 or μeff does not depend on Vgs. In other words, the Y-function does not satisfy the linearity condition if the devices suffer from surface roughness scattering greatly [22]. Another assumption is that Ids·Rsd is almost invariant to Vgs and smaller than Vds in the strong inversion regime, which is satisfied in this study. Almost all the measured devices also meet the linearity condition at Vds of 0.05 V (Figure 3) because all the devices have omega-shaped structure with ultra-thin fin channel, which induces volume inversion and thus attenuates the surface roughness scattering.Figure4 shows Vth_y, X0, and Rsd of the measured devices at Vds of 0.01, 0.02, 0.03, 0.04, and 0.05 V extracted from Y-function method. Average X0 and Rsd are independent of Vds, whereas Vth_y increases slightly as Vds increases. Vth_y includes the band-bending by gate voltage as well as the body-effect expressed by m/2·Vds, where m is the body-effect coefficient (m is simply approximated as 1 for fully depleted devices), thus showing a slight increase of Vth_y with the slope of Vds/2 as Vds increases [23]. The devices with Tsili of 8 nm show greater X0 and smaller Rsd due to greater NiSi/Si contact area.Figure 4
Average and standard deviations of dc parameters for the SOI FinFETs withTsili of 8 nm (black) and 10 nm (red) at different Vds: Vth_y, X0, and Rsd.The devices withTsili of 10 nm have greater variations of Vth_y, X0, and Rsd (Figure 4). Standard deviations (σ) of X0 and Rsd for Tsili of 10 nm increase by 62.4 and 48.5%, respectively, with respect to those for Tsili of 8 nm. Not only Vth_y but also Vth_CCM variations are severer for Tsili of 10 nm (σ=45 mV) than for Tsili of 8 nm (σ=22 mV) at all different Vds.


### 3.2. DC Performance Variability Analysis

To investigate why the devices withTsili of 10 nm suffer from smaller DC performance and greater variations, correlation analysis of Ion with off-state currents (Ioff), Vth_y, X0, and Rsd is done in Figure 5. Spearman’s correlation is used to calculate the correlation coefficient (ρ) [15]. Ioff values are Ids at Vgs of 0.0 V, whereas all the Ion values are extracted at the gate overdrive voltage (Vgs-Vth_y) of 0.8 V (Ion_y) to neglect the Vth_y effect [24]. Since all the devices have similar SS and no gate-induced drain leakages, Ioff is mostly determined by Vth_y  (ρ=-0.781 and −0.907 for Tsili of 8 and 10 nm, resp.). Due to these perspectives, therefore, a slight correlation between Ion_y and Ioff along with Vth_y is expected.Figure 5
Scatter plots ofIon_y at (Vgs-Vth_y) of 0.8 V with respect to the DC parameters (Ioff, Vth_y, X0, and Rsd) for the SOI FinFETs at Vds of 0.05 V. All the linear regressions indicate the sensitivity of Ion_y with respect to the DC parameters.Nonetheless, there are correlations betweenIoff, Vth_y, and Ion_y for Tsili of 10 nm (left of Figure 5). In addition, Vth_y for Tsili of 10 nm is correlated with X0(ρ=-0.530) and Rsd(ρ=0.491), whereas Vth_y for Tsili of 8 nm is independent of X0(ρ=-0.077) and Rsd(ρ=0.200) at all different Vds. X0 is also correlated with Rsd for Tsili of 10 nm (ρ=-0.581), whereas the correlation is small for Tsili of 8 nm (ρ=-0.162).These high correlations among all the DC parameters (Ioff, Vth_y, X0, Rsd) and Ion_y for Tsili of 10 nm are related to the high SBH at the NiSi/Si interface. Higher SBH for thicker Tsili is expected due to greater lateral encroachment of NiSi into the S/D extension regions [19, 25]. Greater Vth_CCM (or Vth_y) and larger Rsd for Tsili of 10 nm are the indicatives of higher SBH according to equation (2) in [26] and higher contact resistivity [27], respectively. Higher SBH for thicker Tsili requires much band-bending for the carrier injection from source (related with Ioff and Vth_y) and impedes carrier flow under operation (related with X0, Rsd, and thus Ion_y) [28]. For the low-SBH devices, the SBH variations induce the on-state performance variations, not the Vth variations [26]. Therefore, the Vth variations for Tsili of 8 nm are dominantly induced by other variability sources (gate work function (WF) variation [24], RDF [15], and interface traps [29]) except the SBH. And that is why Vth_y for Tsili of 8 nm is not correlated with X0, Rsd, and Ion_y.Greater variations of all the DC parameters forTsili of 10 nm can also explain the increased SBH and its variations. The Rsd variations for SOI FinFETs are dominantly affected by NiSi/Si contact resistance [20, 27]. The NiSi/Si interface consists of NiSi crystal grains having different WF and surface roughness [14]. The extension regions suffer from RDF [15] along with the WF variations, having different SBH at each of NiSi crystal grains and also for each of the devices. And this induces the SBH variations greatly for Tsili of 10 nm due to smaller contact area.Figure6 shows the relative contributions to the Ion_y variations with respect to the DC parameters each. When the DC parameters are correlated with each other, the contributions to the variations of Ion_y for the correlated portion are calculated using the correlation coefficient, sensitivity (the slope of scatter plots in Figure 5), and standard deviations [24]. All the correlated portions are presented as the shaded area. All the three DC parameters are correlated with each other and the X0 variations affect the Ion_y variations greatly for Tsili of 10 nm, whereas they are independent and the Rsd variations affect the Ion_y variations greatly for Tsili of 8 nm.Figure 6
I o n _ y variations and variations of the dc parameters (Vth_y, X0, and Rsd) contributing to the Ion_y variations for Tsili of 8 and 10 nm.


### 3.3. Low-Frequency Noise Analysis

Low-frequency noise was measured atVds of 0.05 V and at the overdrive voltage (Vov=Vgs-Vth_CCM) of 0.3 V (Figure 7). Frequency range was from 1 to 1000 Hz, and the 10 devices each with Tsili of 8 and 10 nm, closest to the average Ids, were measured. All the results follow the 1/f trend except at the frequency near 1 Hz where Lorentzian-type noise plateau is observed due to the small-area devices. The devices with Tsili of 10 nm have greater average SIds for all the frequency range.Figure 7
Drain current noise spectral density (SIds) measured at Vds of 0.05 V and the overdrive voltage (Vov=Vgs-Vth_CCM) of 0.3 V for Tsili of (a) 8 and (b) 10 nm. The number of measured devices, close to the average Ids, is 10 each.
(a) (b)Figure8 shows SIds normalized by Ids2 of the devices with different Tsili at Vov from 0.1 to 0.6 V in steps of 0.1 V measured at 10 Hz. In case of Vov from 0.3 to 0.6 V, the normalized SIds values are almost independent of Vov, where the noise induced by Rsd(SRsd) is dominant to the device [30]. The noise within the channel (SRch) is from the Si/SiO2 interface and the channel itself, whereas SRsd is from the S/D contact at NiSi/Si interface. But the quality of Si/SiO2 interface is almost similar for all the devices because the only difference is RTP, performed under low temperature around 300~450°C [13, 19, 20, 31, 32] enough not to induce the Si/SiO2 interface damage. In spite of that, the devices with Tsili of 10 nm have greater SRch because high SBH close to the lightly doped extension region decreases X0 (related to μeff) which is correlated with Rsd. Greater SRch for Tsili of 10 nm is also explained by the lateral encroachment of NiSi into the S/D extension regions. More lateral encroachment of NiSi for thicker Tsili induces higher SBH, which impedes the carrier flow and decreases the channel length [33]. These physical phenomena increase SRch according to equation (3) of [30]; thus the greater SRch for Tsili of 10 nm is obtained (Figure 8). As a result, the devices with Tsili of 10 nm have greater normalized SIds for all Vov.Figure 8
NormalizedSIds at 10 Hz with respect to Ids at different Vov.


## 3.1. DC Performance and Variations at Different Silicide Thickness

I d s and transconductance (gm) of the 50 measured devices each with different Tsili of 8 and 10 nm are shown in Figure 2. Each wafer has a different Tsili, and the measured devices with each Tsili are at the same position of each wafer to minimize the die-to-die variations between two different Tsili. Gate voltage (Vgs) is swept from 0.0 to 1.3 V in steps of 0.02 V, and drain voltages (Vds) are 0.05 and 1.0 V. Red lines indicate the averages of Ids and gm for each Tsili. In both linear and saturation regimes, the devices with Tsili of 8 nm have greater DC performance by showing higher on-state currents (Ion), while the subthreshold characteristics for Tsili of 8 and 10 nm are similar. Figure 2(c) shows that all the devices with Tsili of 8 and 10 nm do not have ambipolar effects at high Vds of 1.0 V near the off-state, validating the absence of Schottky contact [13].Figure 2
DC performance and variations of the SOI FinFETs with theTsili of (a) 8 and (b) 10 nm at drain voltage (Vds) of 0.05 V and (c) 1.0 V. The number of measured devices is 50 for each Tsili.
(a) (b) (c)R o n   ( = V d s / I o n ) values of the 20 measured devices each with different Wfin and Tsili are shown in Figure S1. Ion are extracted at the gate overdrive voltage (Vgs-Vth_CCM) of 1.0 V, where Vth_CCM is the threshold voltage (Vth) extracted from constant current method (CCM) at Ith=Weff/Lg·10-7 A (Weff=Nfin·(2Hfin+Wfin)). The devices with Tsili of 8 nm have smaller Ron for all Wfin. But the difference of Ron between two different Tsili is smaller for greater Wfin because the ratio of the NiSi/Si contact area between two different Tsili decreases. Additionally, raised S/D structure would be beneficial to improve the DC performance by increasing the NiSi/Si contact area. But for raised S/D structure, likewise, thicker Tsili also decreases the contact area, increases the contact resistance, and thus degrades the DC performance [21].Several parameters from the transfer characteristics are extracted to analyze the DC performance variations:Vth, low-field-mobility-related coefficient (X0), and parasitic resistance (Rsd). Vth values are extracted using CCM or Y-function method [16, 22]. Vth_CCM is measured at Ith=Weff/Lg·10-8 A, whereas Vth from Y-function method (Vth_y) is extracted from the x-axis intercept of the linearly extrapolated curve as shown in Figure 3.Figure 3
Y-function variations of the SOI FinFETs with Tsili of 8 and 10 nm. Almost all the Y-functions satisfy the linearity condition in the strong inversion regime.The simple and general expression ofIds at low Vds in the strong inversion regime is given by(1)Ids=X0·Vgs-Vth_y·Vds-IdsRsd,where X0 is defined as μeff·Cox·Weff/Lg (μeff is effective mobility and Cox is oxide capacitance). Y-function is simply expressed as(2)Y≡Idsgm=X0·Vds-IdsRsd·Vgs-Vth_y.According to (2), Y-function is linear in the strong inversion regime if X0 or μeff does not depend on Vgs. In other words, the Y-function does not satisfy the linearity condition if the devices suffer from surface roughness scattering greatly [22]. Another assumption is that Ids·Rsd is almost invariant to Vgs and smaller than Vds in the strong inversion regime, which is satisfied in this study. Almost all the measured devices also meet the linearity condition at Vds of 0.05 V (Figure 3) because all the devices have omega-shaped structure with ultra-thin fin channel, which induces volume inversion and thus attenuates the surface roughness scattering.Figure4 shows Vth_y, X0, and Rsd of the measured devices at Vds of 0.01, 0.02, 0.03, 0.04, and 0.05 V extracted from Y-function method. Average X0 and Rsd are independent of Vds, whereas Vth_y increases slightly as Vds increases. Vth_y includes the band-bending by gate voltage as well as the body-effect expressed by m/2·Vds, where m is the body-effect coefficient (m is simply approximated as 1 for fully depleted devices), thus showing a slight increase of Vth_y with the slope of Vds/2 as Vds increases [23]. The devices with Tsili of 8 nm show greater X0 and smaller Rsd due to greater NiSi/Si contact area.Figure 4
Average and standard deviations of dc parameters for the SOI FinFETs withTsili of 8 nm (black) and 10 nm (red) at different Vds: Vth_y, X0, and Rsd.The devices withTsili of 10 nm have greater variations of Vth_y, X0, and Rsd (Figure 4). Standard deviations (σ) of X0 and Rsd for Tsili of 10 nm increase by 62.4 and 48.5%, respectively, with respect to those for Tsili of 8 nm. Not only Vth_y but also Vth_CCM variations are severer for Tsili of 10 nm (σ=45 mV) than for Tsili of 8 nm (σ=22 mV) at all different Vds.


## 3.2. DC Performance Variability Analysis

To investigate why the devices withTsili of 10 nm suffer from smaller DC performance and greater variations, correlation analysis of Ion with off-state currents (Ioff), Vth_y, X0, and Rsd is done in Figure 5. Spearman’s correlation is used to calculate the correlation coefficient (ρ) [15]. Ioff values are Ids at Vgs of 0.0 V, whereas all the Ion values are extracted at the gate overdrive voltage (Vgs-Vth_y) of 0.8 V (Ion_y) to neglect the Vth_y effect [24]. Since all the devices have similar SS and no gate-induced drain leakages, Ioff is mostly determined by Vth_y  (ρ=-0.781 and −0.907 for Tsili of 8 and 10 nm, resp.). Due to these perspectives, therefore, a slight correlation between Ion_y and Ioff along with Vth_y is expected.Figure 5
Scatter plots ofIon_y at (Vgs-Vth_y) of 0.8 V with respect to the DC parameters (Ioff, Vth_y, X0, and Rsd) for the SOI FinFETs at Vds of 0.05 V. All the linear regressions indicate the sensitivity of Ion_y with respect to the DC parameters.Nonetheless, there are correlations betweenIoff, Vth_y, and Ion_y for Tsili of 10 nm (left of Figure 5). In addition, Vth_y for Tsili of 10 nm is correlated with X0(ρ=-0.530) and Rsd(ρ=0.491), whereas Vth_y for Tsili of 8 nm is independent of X0(ρ=-0.077) and Rsd(ρ=0.200) at all different Vds. X0 is also correlated with Rsd for Tsili of 10 nm (ρ=-0.581), whereas the correlation is small for Tsili of 8 nm (ρ=-0.162).These high correlations among all the DC parameters (Ioff, Vth_y, X0, Rsd) and Ion_y for Tsili of 10 nm are related to the high SBH at the NiSi/Si interface. Higher SBH for thicker Tsili is expected due to greater lateral encroachment of NiSi into the S/D extension regions [19, 25]. Greater Vth_CCM (or Vth_y) and larger Rsd for Tsili of 10 nm are the indicatives of higher SBH according to equation (2) in [26] and higher contact resistivity [27], respectively. Higher SBH for thicker Tsili requires much band-bending for the carrier injection from source (related with Ioff and Vth_y) and impedes carrier flow under operation (related with X0, Rsd, and thus Ion_y) [28]. For the low-SBH devices, the SBH variations induce the on-state performance variations, not the Vth variations [26]. Therefore, the Vth variations for Tsili of 8 nm are dominantly induced by other variability sources (gate work function (WF) variation [24], RDF [15], and interface traps [29]) except the SBH. And that is why Vth_y for Tsili of 8 nm is not correlated with X0, Rsd, and Ion_y.Greater variations of all the DC parameters forTsili of 10 nm can also explain the increased SBH and its variations. The Rsd variations for SOI FinFETs are dominantly affected by NiSi/Si contact resistance [20, 27]. The NiSi/Si interface consists of NiSi crystal grains having different WF and surface roughness [14]. The extension regions suffer from RDF [15] along with the WF variations, having different SBH at each of NiSi crystal grains and also for each of the devices. And this induces the SBH variations greatly for Tsili of 10 nm due to smaller contact area.Figure6 shows the relative contributions to the Ion_y variations with respect to the DC parameters each. When the DC parameters are correlated with each other, the contributions to the variations of Ion_y for the correlated portion are calculated using the correlation coefficient, sensitivity (the slope of scatter plots in Figure 5), and standard deviations [24]. All the correlated portions are presented as the shaded area. All the three DC parameters are correlated with each other and the X0 variations affect the Ion_y variations greatly for Tsili of 10 nm, whereas they are independent and the Rsd variations affect the Ion_y variations greatly for Tsili of 8 nm.Figure 6
I o n _ y variations and variations of the dc parameters (Vth_y, X0, and Rsd) contributing to the Ion_y variations for Tsili of 8 and 10 nm.


## 3.3. Low-Frequency Noise Analysis

Low-frequency noise was measured atVds of 0.05 V and at the overdrive voltage (Vov=Vgs-Vth_CCM) of 0.3 V (Figure 7). Frequency range was from 1 to 1000 Hz, and the 10 devices each with Tsili of 8 and 10 nm, closest to the average Ids, were measured. All the results follow the 1/f trend except at the frequency near 1 Hz where Lorentzian-type noise plateau is observed due to the small-area devices. The devices with Tsili of 10 nm have greater average SIds for all the frequency range.Figure 7
Drain current noise spectral density (SIds) measured at Vds of 0.05 V and the overdrive voltage (Vov=Vgs-Vth_CCM) of 0.3 V for Tsili of (a) 8 and (b) 10 nm. The number of measured devices, close to the average Ids, is 10 each.
(a) (b)Figure8 shows SIds normalized by Ids2 of the devices with different Tsili at Vov from 0.1 to 0.6 V in steps of 0.1 V measured at 10 Hz. In case of Vov from 0.3 to 0.6 V, the normalized SIds values are almost independent of Vov, where the noise induced by Rsd(SRsd) is dominant to the device [30]. The noise within the channel (SRch) is from the Si/SiO2 interface and the channel itself, whereas SRsd is from the S/D contact at NiSi/Si interface. But the quality of Si/SiO2 interface is almost similar for all the devices because the only difference is RTP, performed under low temperature around 300~450°C [13, 19, 20, 31, 32] enough not to induce the Si/SiO2 interface damage. In spite of that, the devices with Tsili of 10 nm have greater SRch because high SBH close to the lightly doped extension region decreases X0 (related to μeff) which is correlated with Rsd. Greater SRch for Tsili of 10 nm is also explained by the lateral encroachment of NiSi into the S/D extension regions. More lateral encroachment of NiSi for thicker Tsili induces higher SBH, which impedes the carrier flow and decreases the channel length [33]. These physical phenomena increase SRch according to equation (3) of [30]; thus the greater SRch for Tsili of 10 nm is obtained (Figure 8). As a result, the devices with Tsili of 10 nm have greater normalized SIds for all Vov.Figure 8
NormalizedSIds at 10 Hz with respect to Ids at different Vov.


## 4. Conclusions

DC performance and variability of the dopant-segregated SOI FinFETs with differentTsili are analyzed in terms of the DC parameters extracted from Y-function method and Spearman correlation, respectively. Thicker Tsili degrades DC performance by decreasing Ion and gm,max and fluctuates Vth, X0, Rsd, and Ion greatly because the SBH increases greatly and varies along with WF variation and RDF at the S/D region. In addition, the devices with Tsili of 10 nm suffer from large low-frequency noise due to high SBH, which is caused by greater lateral encroachment of NiSi into the S/D extension regions and related to greater variations and correlations of Vth_y, X0, Rsd, and Ion_y. Therefore, the device with relatively thin Tsili is promising to improve DC performance and minimize the variation.This variability study would be helpful to design nanoscale devices having a few dopants and small contact area because the SBH values and variations of the devices depend onTsili greatly.



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*Source: 2426863-2018-05-17.xml*