# FPGA Implementation of an Amplitude-Modulated Continuous-Wave Ultrasonic Ranger Using Restructured Phase-Locking Scheme

Authors: P. Sumathi; P. A. Janakiraman
Journal: VLSI Design
 (2010)

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## Abstract

An accurate ultrasonic range finder employing Sliding Discrete Fourier Transform (SDFT) based restructured phase-locked loop (RPLL), which is an improved version of the recently proposed integrated phase-locking scheme (IPLL), has been expounded. This range finder principally utilizes amplitude-modulated ultrasonic waves assisted by an infrared (IR) pilot signal. The phase shift between the envelope of the reference IR pilot signal and that of the received ultrasonic signal is proportional to the range. The extracted envelopes are filtered by SDFT without introducing any additional phase shift. A new RPLL is described in which the phase error is driven to zero using the quadrature signal derived from the SDFT. Further, the quadrature signal is reinforced by another cosine signal derived from a lookup table (LUT). The pulse frequency of the numerically controlled oscillator (NCO) is extremely accurate, enabling fine tuning of the SDFT and RPLL also improves the lock time for the 50 Hz input signal to 0.04 s. The percentage phase error for the range 0.6 m to 6 m is about 0.2%. The VHDL codes generated for the various signal processing steps were downloaded into a Cyclone FPGA chip around which the ultrasonic ranger had been built.


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## Body

## 1. Introduction

Ultrasonic sensors find applications generally in distance measurement, indoor mobile robot control, for environment information, gleaning, localization, and map building, vibration measurements, and safety systems like intelligent airbag control [1–4]. Many range-finding techniques are found in the literature, based on either the time of flight (TOF) or the continuous wave method [5–7]. A variety of continuous wave methods have been reported; notable among them are based on the multifrequency and amplitude-modulated (AM) schemes [8, 9]. The significant advantages of the AM continuous-wave method over the TOF were presented in [10]. The phase shift observed in the ultrasonic wave with respect to the distance traveled can be used to measure the range. For a 40 kHz sound wave, the maximum measurable range using phase shift is only 8.6 mm. In the present work, to enhance the measurable range to 6.86 m, the ultrasonic signal is amplitude  modulated by a 50 Hz signal, which is more appropriate for mobile robot localization and navigation in indoor applications.In this scheme, a low-frequency-modulated Infrared (IR) is used as a pilot signal. Another ultrasonic signal (US) modulated by the same low-frequency signal is utilized for estimating the range. A novel procedure using Sliding Discrete Fourier transform (SDFT) can be employed to extract the fundamental component of the envelope of the received ultrasonic signal [11]. The sampling pulse frequency of the SDFT block is tuned precisely by an integrated phase-locked loop so that exactly one full period of the envelope signal can be accommodated in a window of width 128 [12]. Two such PLL’s, one for the extraction of the sinusoidal envelope of the infrared pilot signal, and another for ultrasonic signal are employed in the range-finding equipment. The PLL is basically a feedback circuit minimizing the phase error by correlating the given envelope signal with the quadrature signal derived from the SDFT block. The envelope of the IR signal is the reference, against which the phase shift of the extracted envelope of the amplitude-modulated ultrasonic signal is compared. The integrated phase-locking scheme discussed in [12] shows a steady residual error in the NCO output frequency. The primary focus of the present paper is to describe the restructured phase-locking scheme, which makes use of a look up table to assist the quadrature signal derived from the SDFT block mainly to reduce the residual phase error. The hardware realization of the restructured phase-locking scheme which is implemented in an FPGA chip has also been described. The DSP builder tool, has been applied extensively for simulation and practical realization of an ultrasonic range finder.The restructured phase locking scheme and its components have been described in Section2. The proposed ultrasonic range measurement scheme based on RPLL, built using the DSP builder tool has been explicated in Section 3. The simulation and experimental results obtained using Cyclone FPGA have been presented in Section 4 and Section 5, respectively. The major conclusions are drawn in Section 6.The schematic of the proposed ultrasonic range finder is shown in Figure1(a). This consists of a transmitter and a receiver unit. The transmitter unit sends an IR pilot signal as well as an ultrasonic signal, both simultaneously modulated by a low-frequency sine wave. The receiver unit contains an IR receiver and an ultrasonic receiver. On the transmitter side a 40 kHz signal had been used to generate the ultrasonic carrier and a 50 Hz sinusoidal signal for amplitude-modulation. The 50 Hz sine wave is converted into square wave using a limiter circuit for modulating the IR pilot signal to serve as the instantaneous reference signal. An ultrasonic transducer transmits the amplitude modulated 40 kHz signal. Figure 1(b) shows the transmitted reference IR signal, ultrasonic signal, and the received ultrasonic signal. On the receiver side, the ultrasonic signal is amplified, rectified, and processed by an SDFT-based restructured phase-locking scheme to extract the sinusoidal envelope. The received reference IR signal is also processed using another SDFT based RPLL for extracting the fundamental component of the envelope. The detailed explanation of this scheme is presented in the next section.(a) Schematic of the proposed Ultrasonic Range Finder and (b) IR reference signal, transmitted ultrasonic signal, and received ultrasonic signal.
(a)(b)


## 2. Restructured Phase-Locking Scheme

The operation of the restructured phase locked-loop (RPLL) based on SDFT is briefly explained here. The detailed block diagram of RPLL scheme is shown in Figure2. When a periodic input signal is passed through a sliding DFT block tuned to a particular frequency, two distinct output signals are obtained. The first signal is basically the fundamental component of the incoming periodic signal, which may, however, be slightly shifted in phase, whenever the frequency of the incoming signal deviates from the frequency for which the SDFT block is tuned [12]. The SDFT block yields another signal, which is in quadrature with the first output signal. The correlation between the input signal and the quadrature signal from the SDFT can be made use of, for adjusting the frequency of the numerically controlled oscillator (NCO) which provides the sampling pulses to the SDFT block, resulting in the phase lock of the SDFT output [12]. Under these conditions, the enabling or the sampling frequency fs=fN, where f is the cyclic frequency of the periodic input signal and N is the number of samples per cycle. Small phase errors may still persist which can be greatly reduced by the addition of an LUT-based pure quadrature signal. Essentially, this scheme differs from the simple integrated phase-locking scheme presented in [12]; in that, the quadrature signal output of the SDFT block is supplemented by a cosine wave from a lookup table accessed by an address counter which in turn is driven by NCO pulses. The added cosine signal from the LUT reduces the steady residual error present in the control signal of the NCO [13]. The modification results in the NCO output frequency becoming very accurate compared to the simple integrated phase-locking scheme (IPLL), and hence provides fine phase locking with the fundamental component of the input signal.Figure 2
Block diagram of restructured phase-locking scheme.


### 2.1. DSP Builder-Quartus-II Tool

The MATLAB/Simulink-DSP builder software had been used for realizing the proposed Sliding DFT-based RPLL scheme. DSP Builder signal compiler block reads Simulink model files (.mdl) which are built using DSP builder and MegaCore blocks and generates VHDL files and Tool command languages (.Tcl) scripts for synthesis [14], hardware implementation, and simulation. The synthesis flow of the DSP builder tool and Quartus-II to generate the VHDL codes is shown in Figure 3. The generated VHDL codes can be downloaded into FPGA from PC through JTAG cable for processing.Figure 3
Synthesis flow of Matlab/Simulink-DSP builder and Quartus-II.


### 2.2. Sliding DFT

The SDFT transfer function including the damping factor “r” can be expressed as(1)Hk(z)=(1-rNz-N)z-1(rej2πk/N)1-rej2πk/Nz-1,r<1,[k=0,1,2,3,…,N-1],
where k is the bin index, which can vary from 0 to N-1, and N is the window width. The damping factor r<1 is introduced in the SDFT transfer function [15] to avoid numerical instability. The in-phase and quadrature signals can be obtained from SDFT block. For k = 1, the SDFT can extract the fundamental component present in the received signal. The real and imaginary parts of the SDFT transfer function can be written as(2)Re[H1(z)]=(1-rNz-N)z-1(rcos(2π/N)-r2z-1)1-2rcos(2π/N)z-1+r2z-2,Im[H1(z)]=(1-rNz-N)z-1(rsin(2π/N))1-2rcos(2π/N)z-1+r2z-2.
The block diagram realization of the SDFT transfer function given in equation in (1) is shown in Figure 4(a). A comb filter and a resonator are connected in cascade in the SDFT structure. For the sake of clarity, bus-width and port symbols were removed in the realization diagram shown in Figure 4(a). The SDFT transfer function has N number of zeros and a single pole lying on the unit circle in the z-plane. For k = 1, the single pole at z=ej2π/N cancels the zero corresponding to that location. The SDFT is a tuned filter, which passes only fundamental frequency present in the input signal and rejects all other harmonics and d.c. The pole-zero diagram of the SDFT is shown in Figure 4(b). The damping factor r is chosen as 0.9997. For maintaining the accuracy, a floating-point bit format of [2:18] (bus width) has been used for the variables in the SDFT block. The magnitude of the input signal is chosen small enough to avoid over-flow.(a) Structure of Sliding DFT transfer functionHk(z) for the kth bin and (b) pole-zero diagram of the SDFT.
(a)(b)


### 2.3. Moving Averager

The phase error signal is obtained from the phase detector basically by multiplying the input signal with the quadrature signal generated by the SDFT block, and the Moving averager provides the average of the resultant product. The Moving Averager hasN number of zeros and a pole at z=1 on the unit circle. This arrangement results in the cancellation of the zero at k=0 location, passing only the d.c. signal while filtering the fundamental and all other harmonics from the given periodic input signal. The block diagram realization and the pole-zero diagram of Moving Averager is shown in Figures 5(a) and 5(b), respectively.(a) Block diagram realization of the Moving Averager and (b) pole-zero diagram of Moving Averager.
(a)(b)


### 2.4. PI Controller and Limiter

A PI controller processes the output from the Moving Averager. The PI controller is intended for reducing the steady residual phase error. The block diagram realization of PI controller is shown in Figure6. The output of the PI controller is limited to ±1.Figure 6
Block diagram realization of the PI controller and saturation.


### 2.5. Numerically Controlled Oscillator

The NCO provides the sampling pulses required by the SDFT block and the Moving averager. The difference equation of NCO [16] can be expressed as(3)[x1(n+1)x2(n+1)]=[αα-1α+1α][x1(n)x2(n)],x1(0)=1,x2(0)=0,
where α = cos(Ψ) and Ψ = 2πfs/fena0; fs is the frequency of oscillation and fena0 is the enabling (triggering) frequency of the delay elements. The block diagram realization of the difference equation of the simple NCO is shown in Figure 7. A nonlinear automatic feedback gain control is suggested for stabilizing the amplitude of NCO [16]. The enabling frequency of delay elements for the NCO is fixed at 25.6 kHz to get the sampling frequency of SDFT as 6.4 kHz so that a 50 Hz fundamental frequency signal is sampled 128 times per cycle. The comparison of NCO pulse frequency obtained from the IPLL and RPLL schemes is given in Table 1. For example, a cyclic frequency of 40 Hz and the window width N=128, the bin index k=1, f=kfs/N, and the exact sampling frequency required by SDFT block being 5120 Hz are also given. From the entries in Table 1 it is seen that the design based on IPLL gives only 5115 sampling pulses per second resulting in an error of 5 pulses per second in the NCO output frequency. The RPLL scheme supplies the very accurate sampling pulse rate of 5120.Table 1
Comparison of NCO frequency.
S. no.Input signal frequency (Hz)IPLL NCO frequency (Hz)RPLL NCO frequency (Hz)1405115512024557545760350639464004557033704056076727680Figure 7
Block diagram realization of simple NCO.


### 2.6. Cosine LUT, Counter, and Multiplier

The addition of cosine LUT has the effect of another PI controller, which acts in parallel to the existing PI controller in the RPLL scheme [17]. The increase in Cosine LUT magnitude improves the lock time of the PLL exhibiting overshoots in the response. The input signal to Cosine LUT ratio has been fixed as 0.5/0.25, for the simulation and experimental studies.


## 2.1. DSP Builder-Quartus-II Tool

The MATLAB/Simulink-DSP builder software had been used for realizing the proposed Sliding DFT-based RPLL scheme. DSP Builder signal compiler block reads Simulink model files (.mdl) which are built using DSP builder and MegaCore blocks and generates VHDL files and Tool command languages (.Tcl) scripts for synthesis [14], hardware implementation, and simulation. The synthesis flow of the DSP builder tool and Quartus-II to generate the VHDL codes is shown in Figure 3. The generated VHDL codes can be downloaded into FPGA from PC through JTAG cable for processing.Figure 3
Synthesis flow of Matlab/Simulink-DSP builder and Quartus-II.


## 2.2. Sliding DFT

The SDFT transfer function including the damping factor “r” can be expressed as(1)Hk(z)=(1-rNz-N)z-1(rej2πk/N)1-rej2πk/Nz-1,r<1,[k=0,1,2,3,…,N-1],
where k is the bin index, which can vary from 0 to N-1, and N is the window width. The damping factor r<1 is introduced in the SDFT transfer function [15] to avoid numerical instability. The in-phase and quadrature signals can be obtained from SDFT block. For k = 1, the SDFT can extract the fundamental component present in the received signal. The real and imaginary parts of the SDFT transfer function can be written as(2)Re[H1(z)]=(1-rNz-N)z-1(rcos(2π/N)-r2z-1)1-2rcos(2π/N)z-1+r2z-2,Im[H1(z)]=(1-rNz-N)z-1(rsin(2π/N))1-2rcos(2π/N)z-1+r2z-2.
The block diagram realization of the SDFT transfer function given in equation in (1) is shown in Figure 4(a). A comb filter and a resonator are connected in cascade in the SDFT structure. For the sake of clarity, bus-width and port symbols were removed in the realization diagram shown in Figure 4(a). The SDFT transfer function has N number of zeros and a single pole lying on the unit circle in the z-plane. For k = 1, the single pole at z=ej2π/N cancels the zero corresponding to that location. The SDFT is a tuned filter, which passes only fundamental frequency present in the input signal and rejects all other harmonics and d.c. The pole-zero diagram of the SDFT is shown in Figure 4(b). The damping factor r is chosen as 0.9997. For maintaining the accuracy, a floating-point bit format of [2:18] (bus width) has been used for the variables in the SDFT block. The magnitude of the input signal is chosen small enough to avoid over-flow.(a) Structure of Sliding DFT transfer functionHk(z) for the kth bin and (b) pole-zero diagram of the SDFT.
(a)(b)


## 2.3. Moving Averager

The phase error signal is obtained from the phase detector basically by multiplying the input signal with the quadrature signal generated by the SDFT block, and the Moving averager provides the average of the resultant product. The Moving Averager hasN number of zeros and a pole at z=1 on the unit circle. This arrangement results in the cancellation of the zero at k=0 location, passing only the d.c. signal while filtering the fundamental and all other harmonics from the given periodic input signal. The block diagram realization and the pole-zero diagram of Moving Averager is shown in Figures 5(a) and 5(b), respectively.(a) Block diagram realization of the Moving Averager and (b) pole-zero diagram of Moving Averager.
(a)(b)


## 2.4. PI Controller and Limiter

A PI controller processes the output from the Moving Averager. The PI controller is intended for reducing the steady residual phase error. The block diagram realization of PI controller is shown in Figure6. The output of the PI controller is limited to ±1.Figure 6
Block diagram realization of the PI controller and saturation.


## 2.5. Numerically Controlled Oscillator

The NCO provides the sampling pulses required by the SDFT block and the Moving averager. The difference equation of NCO [16] can be expressed as(3)[x1(n+1)x2(n+1)]=[αα-1α+1α][x1(n)x2(n)],x1(0)=1,x2(0)=0,
where α = cos(Ψ) and Ψ = 2πfs/fena0; fs is the frequency of oscillation and fena0 is the enabling (triggering) frequency of the delay elements. The block diagram realization of the difference equation of the simple NCO is shown in Figure 7. A nonlinear automatic feedback gain control is suggested for stabilizing the amplitude of NCO [16]. The enabling frequency of delay elements for the NCO is fixed at 25.6 kHz to get the sampling frequency of SDFT as 6.4 kHz so that a 50 Hz fundamental frequency signal is sampled 128 times per cycle. The comparison of NCO pulse frequency obtained from the IPLL and RPLL schemes is given in Table 1. For example, a cyclic frequency of 40 Hz and the window width N=128, the bin index k=1, f=kfs/N, and the exact sampling frequency required by SDFT block being 5120 Hz are also given. From the entries in Table 1 it is seen that the design based on IPLL gives only 5115 sampling pulses per second resulting in an error of 5 pulses per second in the NCO output frequency. The RPLL scheme supplies the very accurate sampling pulse rate of 5120.Table 1
Comparison of NCO frequency.
S. no.Input signal frequency (Hz)IPLL NCO frequency (Hz)RPLL NCO frequency (Hz)1405115512024557545760350639464004557033704056076727680Figure 7
Block diagram realization of simple NCO.


## 2.6. Cosine LUT, Counter, and Multiplier

The addition of cosine LUT has the effect of another PI controller, which acts in parallel to the existing PI controller in the RPLL scheme [17]. The increase in Cosine LUT magnitude improves the lock time of the PLL exhibiting overshoots in the response. The input signal to Cosine LUT ratio has been fixed as 0.5/0.25, for the simulation and experimental studies.


## 3. The Ultrasonic Range Measurement System Based on RPLL

The block diagram of the RPLL-based ultrasonic range measurement system is shown in Figure8. This system comprises of the two channels, one for the reference IR pilot signal and the other for the ultrasonic signal. Both the IR and delayed ultrasonic signals are received at a targeted distance, and processed in the respective RPLL’s. The phase shift between the IR and ultrasonic signals, which is proportional to the range, is computed using Park Transform. The realization of the proposed ultrasonic range measurement scheme is shown in Figure 9, which comprises of two RPLL’s and Park transform blocks.Figure 8
Block diagram of the RPLL-based range measurement scheme.Figure 9
Realization of RPLL-based range measurement scheme.


### 3.1. The PARK Transform

In the amplitude-modulated continuous-wave method, the phase shift information is measured at steady state, which is proportional to the range being measured.The RPLL output corresponding to the block SDFT1 shown in Figure 8 yields the reference IR in-phase and quadrature signals while the RPLL output of the SDFT2 block gives the ultrasonic in-phase and quadrature signals.The reference signals coming out from unit sine and cosine LUT’s of RPLL of the IR channel aresin(ωt)andcos(ωt), and those from the ultrasonic RPLL block are sin(ωt-Δϕ) and cos(ωt-Δϕ). The Park transform procedure can be applied to compute the phase shift between the IR reference and the delayed ultrasonic signal, which can be written as(4)[yx]=[cos(ωt)sin(ωt)-sin(ωt)cos(ωt)][cos(ωt-Δϕ)sin(ωt-Δϕ)],
where
(5)[yx]=[cos(Δϕ)-sin(Δϕ)].
The signals y and x obtained from (5) are steady d.c. signals.The phase shift can be computed using the atan2 function as(6)Δϕ=atan2(x,y).
The realization of the Park transform equations is shown in Figure 10.Figure 10
Realization of the Park Transform.


### 3.2. Hardware Resource Utilization

The hardware resource utilization and the corresponding logic block details of the entire range measurement scheme have been listed in Table2. The proposed algorithm demands only 56% of the total chip area. The Cyclone II chip contains 516 Logic Array Blocks (LABs) with each LAB containing 16 Logic Elements (LEs), 18 Embedded multipliers (18 × 18) or 36 multipliers (9 × 9), 36 soft multipliers (16 × 16), and memory bits of 1,65,888 (4608 RAM bits × M4K RAM blocks). Table 2 indicates that 100% of the embedded multipliers are used. The synthesizer tool handles the available resources for optimum utilization and performance of the given algorithm. Among the available resources, first, the embedded multipliers are exhausted; the multipliers present in the remaining part of the algorithm had been realized using logic elements. The unusual bus width of 20 bits, not divisible by 9, in the algorithm, increases the multiplier utilization. Hence only 56% of the FPGA hardware space is used for the entire range finder. This summary in Table 2 contains the two RPLL schemes, one for the IR and another for ultrasonic envelope and a phase shift computation block. All the utilized resources like total logic elements and embedded multipliers are simultaneously operating in the FPGA. The signals from IR and ultrasonic sensors are sent to the FPGA by A/D converters. The processed digital signals from FPGA are converted into analog signals by D/A converters.Table 2
Hardware resource utilization and logic blocks of the entire range measurement algorithm.
FPGA: Cyclone-IIDevice: EP2C8T144C8Total logic elements: 4,659/8,256 (56%)Combinational with no register4148Register only1Combinational with a register510Total registers: 511/8256 (6%)LC registers511Embedded multiplier 9-bit elements: 36/36 (100%)DSP elements36DSP 9× 90DSP 18× 1818Total pins: 62/85 (72%)Total memory bits: 20,320/165,888 (12%)


## 3.1. The PARK Transform

In the amplitude-modulated continuous-wave method, the phase shift information is measured at steady state, which is proportional to the range being measured.The RPLL output corresponding to the block SDFT1 shown in Figure 8 yields the reference IR in-phase and quadrature signals while the RPLL output of the SDFT2 block gives the ultrasonic in-phase and quadrature signals.The reference signals coming out from unit sine and cosine LUT’s of RPLL of the IR channel aresin(ωt)andcos(ωt), and those from the ultrasonic RPLL block are sin(ωt-Δϕ) and cos(ωt-Δϕ). The Park transform procedure can be applied to compute the phase shift between the IR reference and the delayed ultrasonic signal, which can be written as(4)[yx]=[cos(ωt)sin(ωt)-sin(ωt)cos(ωt)][cos(ωt-Δϕ)sin(ωt-Δϕ)],
where
(5)[yx]=[cos(Δϕ)-sin(Δϕ)].
The signals y and x obtained from (5) are steady d.c. signals.The phase shift can be computed using the atan2 function as(6)Δϕ=atan2(x,y).
The realization of the Park transform equations is shown in Figure 10.Figure 10
Realization of the Park Transform.


## 3.2. Hardware Resource Utilization

The hardware resource utilization and the corresponding logic block details of the entire range measurement scheme have been listed in Table2. The proposed algorithm demands only 56% of the total chip area. The Cyclone II chip contains 516 Logic Array Blocks (LABs) with each LAB containing 16 Logic Elements (LEs), 18 Embedded multipliers (18 × 18) or 36 multipliers (9 × 9), 36 soft multipliers (16 × 16), and memory bits of 1,65,888 (4608 RAM bits × M4K RAM blocks). Table 2 indicates that 100% of the embedded multipliers are used. The synthesizer tool handles the available resources for optimum utilization and performance of the given algorithm. Among the available resources, first, the embedded multipliers are exhausted; the multipliers present in the remaining part of the algorithm had been realized using logic elements. The unusual bus width of 20 bits, not divisible by 9, in the algorithm, increases the multiplier utilization. Hence only 56% of the FPGA hardware space is used for the entire range finder. This summary in Table 2 contains the two RPLL schemes, one for the IR and another for ultrasonic envelope and a phase shift computation block. All the utilized resources like total logic elements and embedded multipliers are simultaneously operating in the FPGA. The signals from IR and ultrasonic sensors are sent to the FPGA by A/D converters. The processed digital signals from FPGA are converted into analog signals by D/A converters.Table 2
Hardware resource utilization and logic blocks of the entire range measurement algorithm.
FPGA: Cyclone-IIDevice: EP2C8T144C8Total logic elements: 4,659/8,256 (56%)Combinational with no register4148Register only1Combinational with a register510Total registers: 511/8256 (6%)LC registers511Embedded multiplier 9-bit elements: 36/36 (100%)DSP elements36DSP 9× 90DSP 18× 1818Total pins: 62/85 (72%)Total memory bits: 20,320/165,888 (12%)


## 4. Simulation Results

The RPLL-based range measurement scheme has been simulated in MATLAB/Simulink-DSP builder environment. The simulation was carried out at a sampling frequency of 51.282 kHz. A 50 Hz sine wave with 128 samples per cycle had been chosen for simulation studies. Figure11 shows the realization of the RPLL structure. When the range is about 86.25 cm, the phase shift quantifies to 45°. The signals from the sine LUT of the IR reference RPLL and the sine LUT of the received ultrasonic RPLL are shown in Figure 12. The corresponding unit cosine signals from the IR loop and the ultrasonic loop are shown in Figure 13. These four signals are processed by the Park Transform to yield the phase shift. Significantly, the unit sine and cosine signals from the LUT’s present in the PLL make the computation of phase shift independent of the received signal magnitude. Additionally, the signals derived from LUT’s make the NCO pulse frequency quite accurate. Also this improves the lock time for the 50 Hz input signal to 0.04 s whereas IPLL takes 0.15 s for the same 50 Hz input frequency.Figure 11
Realization of restructured phase-locking scheme.Figure 12
Reference and ultrasonic signals obtained from IR Sine LUT and US Sine LUT for45° phase shift (Simulation).Figure 13
Reference and ultrasonic signals obtained from IR Cos LUT and US Cos LUT for45° phase shift (Simulation).


## 5. Experimental Results

The bimorph-type ultrasonic transducer used in the experiments can be tuned to antiresonance around 37± 2 kHz. Hence the carrier frequency was fixed at its maximum value of 39 kHz. In the simulation studies a 40 kHz carrier signal was used, which is close enough to 39 kHz. The envelope frequency could be chosen as 50 Hz or 25 Hz. With 50 Hz, the measurable range could be 6.86 m while the use of 25 Hz envelope enhances the range to 13.72 m. The envelope frequency of 51.2 Hz (≈50 Hz) has been chosen for modulation process and testing the proposed RPLL scheme.These two signals were generated using two Wien bridge oscillators. The amplitude-modulated ultrasonic signal and the IR signals were sent and received at targeted distance by the matching receivers. The restructured phase-locking scheme had been employed for the IR and ultrasonic channels. The received IR reference square wave and extracted ultrasonic envelope from SDFT at a distance of 42 cm are shown in Figure14. The reference square wave and unit sine obtained from the LUT present in the RPLL of the ultrasonic channel are shown in Figure 15. The unit sine obtained from LUT is comparatively purer than the envelope extracted from the SDFT, which makes the phase shift computation more accurate. The received rectified ultrasonic signal along with the corresponding LUT generated unit sine wave, which is very much equivalent to the extracted ultrasonic envelope is shown in Figure 16.Figure 14
Reference square wave and extracted envelope using SDFT for 42 cm range showing 22 deg phase shift (Experiment).Figure 15
Reference square wave and unit sine from LUT equivalent to extracted envelope for 42 cm range showing 22 deg phase shift (Experiment).Figure 16
Received rectified, AM ultrasonic signal and the unit sine from LUT (Experiment).


### 5.1. Hardware-In-Loop Test

The Hardware-In-Loop (HIL) [18] test was conducted for calibrating the ultrasonic range-finding equipment built around the Cyclone FPGA. The algorithm was developed in MATLAB-Simulink-Altera-DSP builder. In this environment the developed *.mdl files are converted to VHDL codes using Quartus-II software. The generated VHDL codes from PC are downloaded into the FPGA using JTAG cable. For conducting this test, first of all, the received IR and ultrasonic signals have been passed into the FPGA using suitable interfaces and the computed signals cos(Δϕ) and sin(-Δϕ) from the Park transform block are transferred through JTAG cable to the PC, where the phase shift is computed in the MATLAB environment using the atan2 function. The HIL test helps in computing the numerical value of phase shift in the same MATLAB environment. Adding the Hardware in the Loop (HIL) block to Simulink model allows cosimulating of a Quartus-II software design with a physical FPGA board implementing most of the design. A simple JTAG acts as interface between Simulink and the FPGA board. Figure 17 shows the block diagram of the HIL test configuration. The real time signals are accepted through ADC and processed in the FPGA. The processed signals are passed through the DAC for the displaying of the waveforms. The HIL loop operates between the Matlab/simulink environment and FPGA using JTAG interface.Figure 17
Block diagram of the MATLAB/Simulink-FPGA board for HIL test.The calibration graph is shown in Figure18, proving that the phase shift and the range are linearly related. The percentage error obtained from calibration data is around 3% at closer distances (30 cm) and it reduces to 0.2% at larger distances (0.6 m to 6 m). At closer distance the observed percentage error is 3%. This is because the phase shift is very small and the quantization error in the [2] : [18] format becomes noticeable. A larger bit size for the variables (say [2] : [24]) reduces such errors. Phase errors are also observed due to finite (N=128) timewise discretization of the period of the envelope signal. A larger bit size and a wider window (N=256) may reduce maximum possible phase errors, demanding, however, extra hardware space.Figure 18
Distance versus phase shift (Experiment).Most of the commercially available range finders are based on the Time-Of-Flight (TOF) principle useing either single pulse or burst of ultrasonic waves. The comparison factors involve maximum measurable range, data update rate, hardware complexity, accuracy, cost, and performance in cluttered environment.Literature shows that the available range finders have conflict among these parameters and are yet to be categorized. However, in TOF procedure, the measurable range appears to be 2 m to 10 m and the accuracy based on maximum distances is 1%. For example, the commercial ultrasonic ranger Maxsonar uses the ultrasonic bursts for target detection and the resolution is found to be 1 cm in the measurable range of 20 cm to 6.5 m. The reflected amplitude-modulated continuous wave method [9] with a 150 Hz envelope can, however, be compared with the proposed scheme. In this method, a range of 2 m and an accuracy of 2 mm for a 1.5 m distance have been reported.


### 5.2. Power Dissipation Analysis

The power planning is an important consideration when the circuit design turns out to be larger. The power dissipation analysis [19] for the design using DSP builder blocks had been carried out in the Quartus-II environment on the generated equivalent VHDL code. The signal activity file (.saf) corresponding to the VHDL code had been generated using the default toggle rates for the input signal. The summary obtained from the power dissipation analysis using the Quartus-II power analyzer tool is listed in Table 3.Table 3
Power dissipation analysis.
Total thermal power dissipation = 44.56 mWDynamic thermal power dissipation = 1.03 mWStatic thermal power dissipation = 43.53 mWThe block thermalRouting thermalThe block thermalRouting thermalDynamic power (mW)Dynamic power (mW)Static power (mW)Static power (mW)Logic cell registers0.28Clock control blocks0.29Pins5.95Resistors formed by routing37.58Pins0.02——————Memory bits0.44——————0.740.295.9537.58Total dynamic thermal powerTotal static thermal powerDissipation = 0.74 + 0.29 = 1.03 mWDissipation = 5.95 + 37.58 = 43.53 mWTotal thermal power dissipation  = 1.03 + 43.53 = 44.56 mWBlock average toggle rate (millions of transitions/sec)Pins0.271Clock control blocks2.667From Table3 total thermal power dissipation is sum of the dynamic and static power dissipation. Routing plays an important role in power dissipation. Routing is formed by the combination of resistors and capacitors. The resistors dissipate static power but the capacitors consume dynamic power.Dynamic power is dissipated in the resources utilized as blocks in the algorithm and routing. The logic cell registers, pins loaded with capacitance, and memory bits consume thermal dynamic power of 0.74 mW. The dynamic power dissipated in clock control blocks due to routing is 0.29 mW. The total dynamic power dissipation amounts to be 1.03 mW.Similarly, the static power is dissipated in pins if they are used as terminated I/O’s and in routing the algorithm. From Table3, the pins consume 5.95 mW and the resistors formed during routing dissipate 37.58 mW. The total static power dissipation quantifies to be 43.53 mW.The power analyzer examines the algorithm for the total power dissipation as heat in the FPGA device, and the estimation was found to be 44.56 mW.


### 5.3. Application of the Proposed Range Finder

The proposed range measurement system is very much suitable for localization and navigation of mobile robots in an indoor environment [20]. The IR and the US transmitters could be located in the ceiling or high on the wall of a room. The number of IR and US transmitters could be positioned at the required specific locations. The receiver unit could be mounted on the mobile robot to receive the signals transmitted by the sensors on the ceiling. The signals received by the sensors fixed on the mobile robot are processed for the distance information, which helps in position determination of mobile robot localization. The received signals in this direct path scheme are less prone to noise than reflected or indirect method also enables to get quicker measurement readings.


## 5.1. Hardware-In-Loop Test

The Hardware-In-Loop (HIL) [18] test was conducted for calibrating the ultrasonic range-finding equipment built around the Cyclone FPGA. The algorithm was developed in MATLAB-Simulink-Altera-DSP builder. In this environment the developed *.mdl files are converted to VHDL codes using Quartus-II software. The generated VHDL codes from PC are downloaded into the FPGA using JTAG cable. For conducting this test, first of all, the received IR and ultrasonic signals have been passed into the FPGA using suitable interfaces and the computed signals cos(Δϕ) and sin(-Δϕ) from the Park transform block are transferred through JTAG cable to the PC, where the phase shift is computed in the MATLAB environment using the atan2 function. The HIL test helps in computing the numerical value of phase shift in the same MATLAB environment. Adding the Hardware in the Loop (HIL) block to Simulink model allows cosimulating of a Quartus-II software design with a physical FPGA board implementing most of the design. A simple JTAG acts as interface between Simulink and the FPGA board. Figure 17 shows the block diagram of the HIL test configuration. The real time signals are accepted through ADC and processed in the FPGA. The processed signals are passed through the DAC for the displaying of the waveforms. The HIL loop operates between the Matlab/simulink environment and FPGA using JTAG interface.Figure 17
Block diagram of the MATLAB/Simulink-FPGA board for HIL test.The calibration graph is shown in Figure18, proving that the phase shift and the range are linearly related. The percentage error obtained from calibration data is around 3% at closer distances (30 cm) and it reduces to 0.2% at larger distances (0.6 m to 6 m). At closer distance the observed percentage error is 3%. This is because the phase shift is very small and the quantization error in the [2] : [18] format becomes noticeable. A larger bit size for the variables (say [2] : [24]) reduces such errors. Phase errors are also observed due to finite (N=128) timewise discretization of the period of the envelope signal. A larger bit size and a wider window (N=256) may reduce maximum possible phase errors, demanding, however, extra hardware space.Figure 18
Distance versus phase shift (Experiment).Most of the commercially available range finders are based on the Time-Of-Flight (TOF) principle useing either single pulse or burst of ultrasonic waves. The comparison factors involve maximum measurable range, data update rate, hardware complexity, accuracy, cost, and performance in cluttered environment.Literature shows that the available range finders have conflict among these parameters and are yet to be categorized. However, in TOF procedure, the measurable range appears to be 2 m to 10 m and the accuracy based on maximum distances is 1%. For example, the commercial ultrasonic ranger Maxsonar uses the ultrasonic bursts for target detection and the resolution is found to be 1 cm in the measurable range of 20 cm to 6.5 m. The reflected amplitude-modulated continuous wave method [9] with a 150 Hz envelope can, however, be compared with the proposed scheme. In this method, a range of 2 m and an accuracy of 2 mm for a 1.5 m distance have been reported.


## 5.2. Power Dissipation Analysis

The power planning is an important consideration when the circuit design turns out to be larger. The power dissipation analysis [19] for the design using DSP builder blocks had been carried out in the Quartus-II environment on the generated equivalent VHDL code. The signal activity file (.saf) corresponding to the VHDL code had been generated using the default toggle rates for the input signal. The summary obtained from the power dissipation analysis using the Quartus-II power analyzer tool is listed in Table 3.Table 3
Power dissipation analysis.
Total thermal power dissipation = 44.56 mWDynamic thermal power dissipation = 1.03 mWStatic thermal power dissipation = 43.53 mWThe block thermalRouting thermalThe block thermalRouting thermalDynamic power (mW)Dynamic power (mW)Static power (mW)Static power (mW)Logic cell registers0.28Clock control blocks0.29Pins5.95Resistors formed by routing37.58Pins0.02——————Memory bits0.44——————0.740.295.9537.58Total dynamic thermal powerTotal static thermal powerDissipation = 0.74 + 0.29 = 1.03 mWDissipation = 5.95 + 37.58 = 43.53 mWTotal thermal power dissipation  = 1.03 + 43.53 = 44.56 mWBlock average toggle rate (millions of transitions/sec)Pins0.271Clock control blocks2.667From Table3 total thermal power dissipation is sum of the dynamic and static power dissipation. Routing plays an important role in power dissipation. Routing is formed by the combination of resistors and capacitors. The resistors dissipate static power but the capacitors consume dynamic power.Dynamic power is dissipated in the resources utilized as blocks in the algorithm and routing. The logic cell registers, pins loaded with capacitance, and memory bits consume thermal dynamic power of 0.74 mW. The dynamic power dissipated in clock control blocks due to routing is 0.29 mW. The total dynamic power dissipation amounts to be 1.03 mW.Similarly, the static power is dissipated in pins if they are used as terminated I/O’s and in routing the algorithm. From Table3, the pins consume 5.95 mW and the resistors formed during routing dissipate 37.58 mW. The total static power dissipation quantifies to be 43.53 mW.The power analyzer examines the algorithm for the total power dissipation as heat in the FPGA device, and the estimation was found to be 44.56 mW.


## 5.3. Application of the Proposed Range Finder

The proposed range measurement system is very much suitable for localization and navigation of mobile robots in an indoor environment [20]. The IR and the US transmitters could be located in the ceiling or high on the wall of a room. The number of IR and US transmitters could be positioned at the required specific locations. The receiver unit could be mounted on the mobile robot to receive the signals transmitted by the sensors on the ceiling. The signals received by the sensors fixed on the mobile robot are processed for the distance information, which helps in position determination of mobile robot localization. The received signals in this direct path scheme are less prone to noise than reflected or indirect method also enables to get quicker measurement readings.


## 6. Conclusion

A phase-locking scheme has been presented which essentially uses the Sliding Discrete Fourier Transform block. The basic PLL built around the SDFT block had been restructured, by introducing an LUT to assist the quadrature signal of the SDFT. This restructured phase-locking arrangement has been found to reduce the errors in the phase measurement, basically by making the sampling frequency provided by the NCO very accurate simultaneously reducing the lock time. These restructured PLL’s yield pure equivalent unit sinusoidal signals corresponding to the IR pilot signal and the envelope of the ultrasonic signal. These signals have enabled the measurement of the phase shift via the well-known Park transform procedure. The experimental results have validated the simulation of the proposed range finder. The extraction of the envelopes is carried out under steady state using the accurate RPLL scheme and the measurement ignores any portion of the ultrasonic signals missed initially. These factors lead to percentage errors as low as 0.2% at larger distances in the range of 0.6 m to 6 m in controlled environments. Interestingly, the summary of hardware resource utilization gives a convincing proof that the proposed ultrasonic-IR range measurement system can be accommodated in a single Cyclone-II FPGA chip.



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*Source: 213043-2010-03-11.xml*