# Tunable First-Order Resistorless All-Pass Filter with Low Output Impedance

Authors: Parveen Beg
Journal: The Scientific World Journal
 (2014)

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## Abstract

This paper presents a voltage mode cascadable single active element tunable first-order all-pass filter with a single passive component. The active element used to realise the filter is a new building block termed as differential difference dual-X current conveyor with a buffered output (DD-DXCCII). The filter is thus realized with the help of a DD-DXCCII, a capacitor, and a MOS transistor. By exploiting the low output impedance, a higher order filter is also realized. Nonideal and parasitic study is also carried out on the realised filters. The proposed DD-DXCCII filters are simulated using TSMC the 0.25µm technology.


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## Body

## 1. Introduction

Analog first-order filter design using a variety of active building blocks has been the focus of research for the past several decades. Operational amplifier was the active element of choice during the earlier stages of development. Later, the advent of second generation current conveyors (CCII), differential voltage current conveyor (DVCC), current controlled current conveyor (CCCII), and dual-X current conveyor (DXCCII) signalled the era of voltage-mode and current-mode signal processing. Since then, there has been a significant amount of technical literature available on the subject. Obviously, it is not possible to attempt a thorough review of all the related works. However, a survey of some of the recently published first-order voltage mode all-pass filters (APF) is presented in this section. A variety of circuits are available based on the above-mentioned conveyors [1–22]. The filter in [1–8] is composed of more than one active element while the method proposed in [9–22] employs only a single active element and passive components. The filters in [16, 17] employ four passive components; the filter in [19] employs two to three passive components while the filters designed in [10–13, 15, 20, 21] employ three passive components. Out of these, the filters presented in [11, 20, 21] do not exhibit a low output impedance and hence fall in the category of noncascadable filters while those in [10, 12, 13, 15] have a low output impedance and are classified as cascadable filters. The filters in [1, 3, 4, 18] are resistorless circuits based on one or more active elements. A distinct advantage of the filter presented in [18] is that it employs a single active and a passive element with low output impedance.However, none of the above-mentioned filters support tuning as a feature except the filter in [1].The DXCCII presented in [15], even though contains a buffered output, requires an additional current source to obtain a low output impedence terminal, while, in this work, no additional current source is required. The DD-DXCCII is utilized to design a tunable voltage mode cascadable first-order filter.The single active element all-pass filter presented in this paper exhibits the following features:(a)
single active element DD-DXCCII,(b)
single passive element,(c)
resistorless,(d)
low output impedance,(e)
tunable,(f)
no matching condition.A detailed comparison of some of the reported single active element voltage mode filters with the proposed filter is shown in Table 1. From this table, it is clear that none of the reported filters exhibit all the above-mentioned features.Table 1
Comparison of single active element based proposed and existing first-order circuits.
Ref no.
Active element
No. of passive components
Resistorless
High input impedance
Low output impedance
Supply voltages
Matching condition required
Tunable
Highest operating frequency
[9]
CCII
5
No
Yes
No
—
Yes
No
~10 KHz
[10]
FDCCII
3
No
Yes
Yes
±3.3 V
Yes
No
1.59 MHz
[11]
CCII
3
No
Yes
No
—
Yes
No
—
[12]
UVC
3
No
Yes
Yes
±2.5 V
Yes
Yes
1.17 MHz
[13]
CBTA/CCCDBA
3
No
No
Yes
±2.5 V
No
No
119 KHz
[14]
DDCC
2
No
No
No
±2.5 V
No
No
1.59 MHz
[15]
DXCCII
2/3
No
Yes
Yes
±2.5 V
No
No
25 MHz
[16]
CCIII
4
No
No
No
Yes
No
1 KHz
[17]
DXCCII
4
No
Yes
No
±1.25 V
Yes
No
1.59 MHz
[18]
VD-DIBA
1
Yes
Yes
Yes
—
No
No
318 KHz
[19]
ICCII
2
No
No
No
±2.5 V
Yes
No
370 KHz
[20]
CCII
3
No
Yes
No
±2.5 V
Yes
No
1 MHz
[21]
CCII
3
No
No
No
—
Yes
No
159 KHz
[22]
FDCCII
2
No
Yes
Yes
±3 V
No
No
3.11 MHz
Proposed
DDDXCCII
1
Yes
No
Yes
±1.25 V
No
Yes
4–6 MHzThe rest of the paper is organized as follows. Section2 presents a brief overview of the DD-DXCCII, with buffered output followed by the design and analysis of a new voltage-mode, first-order, all-pass filter section based on a single DD-DXCCII. In Section 3, nonideal and parasitic analysis of the proposed circuit is performed. The feature of easy cascadibility is highlighted in Section 4 while Section 5 presents the results of computer simulations of the proposed circuits using the PSPICE program. Some conclusive remarks appear in Section 6.


## 2. Proposed First-Order All-Pass Filter

The differential difference dual-X current conveyor with buffered output has been proposed as an eight-terminal device characterized by the following port relations:(1)[Iy1Iy2Iy3VxpVxnIzpiIzniVwn]=[0000000000000000001-11000-1+1-1000000100000010000001][Vy1Vy2Vy3IxpIxnVzn].
Figure 1 shows the schematic symbol of a DD-DXCCII with buffered output. The CMOS implementation of DD-DXCCII with buffered output at Zn is shown in Figure 2.Figure 1
Schematic symbol of DD-DXCCII.Figure 2
CMOS implementation of DD-DXCCII.The input side has three terminals (calledY1, Y2, and Y3) and there are two X-terminals (Xp and Xn). At the output side, there are three terminals Zp, Zn, and Wn. For the Zp terminal, the direction and magnitude of the conveyed current are the same as those of the current flowing in the Xp-terminal whereas for the Zn terminal, the current is the same as in the Xn-terminal. The voltage that appears at terminal Wn is equal to the voltage at Zn.The proposed tunable voltage-mode first-order all-pass filter section is shown in Figure3. As can be seen, the circuit has minimal complexity and employs a single DD-DXCCII, a single capacitor, and an NMOS transistor biased in the triode region.Figure 3
Proposed tunable first-order all-pass filter.The transfer function of an all-pass filter can be given as(2)TAP=VoutVin=s-2/RMCs+2/RMC,
where RM is the resistance of the MOSFET transistor (M) in Figure 3 and is given by
(3)RM=[μnCox(WL)(VC-VT)]-1,
where μn, Cox, VT, W, and L are the surface mobility, oxide capacitance, threshold voltage, channel width, and length of MOS. From (2) the pole frequency ω0 can be expressed as
(4)ω0=2RMC.
From (4) it is clear that the pole frequency of the all-pass filter can be tuned by varying the resistance (RM) of the triode MOS resistor (M). The phase angle of the all-pass filter can be expressed as
(5)∠ϕ=π-2tan-1⁡(ωCRM2).


## 3. Nonideal Study

### 3.1. Effect of Nonideal Transfer Gain

The port relations defining the DD-DXCCII, as given in (1), correspond to an ideal device in which the current and voltage conveying processes are deemed perfect. For a more realistic understanding of the operation of the circuit of Figure 3, the nonidealities associated with the DD-DXCCII need to be taken into consideration. The nonideal port relationship can be expressed as
(6)Vxp=βp1Vy1-βp2Vy2+βp3Vy3,Vxn=βn1Vy1-βn2Vy2+βn3Vy3,Izp=αpIxp,Izn=αnIxn,Vwn=γnVzn,
where βpi (βni) is the voltage transfer gain from the Yi port to Xp (Xn) port, where i = 1 to 3, αp (αn) is the current transfer gain from the Xp port to Zp port (Xn port to Zn port) and γn is the voltage transfer gain from Zn port to Wn port (ideally, these transfer gains are unity in magnitude).Using (6) the ideal transfer functions of the AP filter section, given in (2), yield the following nonideal transfer function:
(7)TAP,nonideal=VoutVin=s-(2αpβ1/RMC)s+(2αpβ3/RMC).
From (7) the nonideal pole frequency can be expressed as
(8)ω0,nonideal=2αpβ3RMC.
Equation (8) shows that, due to nonideal voltage and current transfer gain, the pole frequency does get affected. The sensitivity analysis shows that the pole frequency due to the nonidealities is unity in magnitude.


### 3.2. Effect of Parasitics

The parasitics associated with the actual DD-DXCCII are the same as those of the DXCCII [23]. In Figure 3, Y1 and Zp port parasitics are in parallel; that is, Ry1//Rzp//Cy1//Czp, Y3, and Zn port resistances and capacitances are also in parallel, that is, Ry3//Rzn//Cy3//Czn. Also, the Xp and Xn parasitics, that is, Rxp and Rxn, merge with the resistance of triode MOSFET. The proposed circuit is reanalyzed by taking into account the above parasitics (assuming RM≫(Rxp+Rxn)). The nonideal transfer gain due to parasitics then becomes
(9)TAP,parasitic=VoutVin=(C+C′C)(s-2/RM(C+C′)s+2/RMC),
where C′=Cy1//Czp and since C≫C′, the transfer function reduces to
(10)TAP,parasitic=VoutVin=(s-2/RMCs+2/RMC).
From (10) it is clear that the pole frequency is unaffected in the presence of parasitics.


## 3.1. Effect of Nonideal Transfer Gain

The port relations defining the DD-DXCCII, as given in (1), correspond to an ideal device in which the current and voltage conveying processes are deemed perfect. For a more realistic understanding of the operation of the circuit of Figure 3, the nonidealities associated with the DD-DXCCII need to be taken into consideration. The nonideal port relationship can be expressed as
(6)Vxp=βp1Vy1-βp2Vy2+βp3Vy3,Vxn=βn1Vy1-βn2Vy2+βn3Vy3,Izp=αpIxp,Izn=αnIxn,Vwn=γnVzn,
where βpi (βni) is the voltage transfer gain from the Yi port to Xp (Xn) port, where i = 1 to 3, αp (αn) is the current transfer gain from the Xp port to Zp port (Xn port to Zn port) and γn is the voltage transfer gain from Zn port to Wn port (ideally, these transfer gains are unity in magnitude).Using (6) the ideal transfer functions of the AP filter section, given in (2), yield the following nonideal transfer function:
(7)TAP,nonideal=VoutVin=s-(2αpβ1/RMC)s+(2αpβ3/RMC).
From (7) the nonideal pole frequency can be expressed as
(8)ω0,nonideal=2αpβ3RMC.
Equation (8) shows that, due to nonideal voltage and current transfer gain, the pole frequency does get affected. The sensitivity analysis shows that the pole frequency due to the nonidealities is unity in magnitude.


## 3.2. Effect of Parasitics

The parasitics associated with the actual DD-DXCCII are the same as those of the DXCCII [23]. In Figure 3, Y1 and Zp port parasitics are in parallel; that is, Ry1//Rzp//Cy1//Czp, Y3, and Zn port resistances and capacitances are also in parallel, that is, Ry3//Rzn//Cy3//Czn. Also, the Xp and Xn parasitics, that is, Rxp and Rxn, merge with the resistance of triode MOSFET. The proposed circuit is reanalyzed by taking into account the above parasitics (assuming RM≫(Rxp+Rxn)). The nonideal transfer gain due to parasitics then becomes
(9)TAP,parasitic=VoutVin=(C+C′C)(s-2/RM(C+C′)s+2/RMC),
where C′=Cy1//Czp and since C≫C′, the transfer function reduces to
(10)TAP,parasitic=VoutVin=(s-2/RMCs+2/RMC).
From (10) it is clear that the pole frequency is unaffected in the presence of parasitics.


## 4. Higher Order All-Pass Filter

It is well known that higher order filters exhibit a larger rate of phase change at constant magnitude when compared to a first-order filter. They can also be used as a group delay equalizer in video and communication applications. These features are the motivating factor behind realizing a higher order filter in this work. The proposednth order APF filter is presented in Figure 4 which is obtained by cascading n-stages of the first-order filter described in Figure 3. The proposed filter employs n-stages of DD-DXCCII and n-capacitors and MOS resistors operating in the triode region.Figure 4
Proposed tunablenth order all-pass filter.Analysis of the above circuit yields the following transfer function:(11)TAP,nthorder=VoutVin=(s-2/RM1C1s+2/RM1C1)=×(s-2/RM2C2s+2/RM2C2)⋯(s-2/RMnCns+2/RMnCn).
From (11) the pole frequency can be expressed as
(12)ω0,nthorder=(2n(RM1·RM2⋯RMn)·(CM1·CM2⋯CMn))1/n.


## 5. Design and Verification

The performance of the first-order all-pass shown in Figure3 was verified using PSPICE program. Supply voltages were kept at ±1.25 V. The proposed filter was designed with C=10pF and gate control voltages are VC=0.8V, 1.0V, and 1.2V. The gain and phase plot is shown in Figure 5 which shows the variation in pole frequency at different control words. As can be seen, the pole frequency is varied from 4 MHz, 5 MHz, and 6 MHz at VC=0.8V, 1.0V, and 1.2V, respectively. The time domain response of the proposed all-pass filter as shown in Figure 6 is obtained by applying a sine wave of 80 mV peak-to-peak amplitude at 6 MHz. The output is 88.9° phases shifted, which corresponds well with the theoretical value of 90°. The total harmonics distortion was found to be 1% at pole frequency of 6 MHz. The Fourier spectrum of input and output waveform is also shown in Figure 7.Figure 5
Frequency response showing gain and phase of APS of Figure3.Figure 6
Time domain response of APS at 6 MHz.Figure 7
Fourier spectrum of input and output at 6 MHz.The circuit proposed in Figure4 is verified for a third-order filter; that is, n=3. The filter was designed at C=10pF at different gate control voltages of the MOS transistor; that is, VC=0.8V, 1.0V, and 1.2V. Simulated gain and phase response at different pole frequencies is shown in Figure 8. The pole frequencies are found to be 4 MHz, 5 MHz, and 6 MHz at a phase of −90°. The variation in pole frequency is obtained by varying the control word. The total harmonics distortion (THD) variation of first- and third-order filter is shown in Figure 9, which shows that the THD variation is around 3% up to 300 mV of the variation in the input signal amplitude.Figure 8
Frequency response showing gain and phase of 3rd order APS of Figure4.Figure 9
THD variation of 1st and 3rd order filter.


## 6. Conclusion

In this paper a new active element, that is, DD-DXCCII with buffered output, is presented. By employing DD-DXCCII a new voltage mode tunable resistorless all-pass filter using single passive element is realized. The proposed filter does not require any matching condition. The filter has low output impedance which is elaborated by designing a third-order filter. Nonidealities of the active element along with parasitics are also considered, so as to evaluate the proposed filter. The filter reported in [23, 24] is a current mode all-pass filter while the filter presented in this work is a voltage mode all-pass filter.



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*Source: 219453-2014-01-22.xml*