# MCML D-Latch Using Triple-Tail Cells: Analysis and Design

Authors: Kirti Gupta; Neeta Pandey; Maneesha Gupta
Journal: Active and Passive Electronic Components
 (2013)

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## Abstract

A new low-voltage MOS current mode logic (MCML) topology for D-latch is proposed. The new topology employs a triple-tail cell to lower the supply voltage requirement in comparison to traditional MCML D-latch. The design of the proposed MCML D-latch is carried out through analytical modeling of its static parameters. The delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage MCML D-latch is analyzed for the two design cases, namely, high-speed and power-efficient, and the performance is compared with the traditional MCML D-latch for each design case. The theoretical propositions are validated through extensive SPICE simulations using TSMC 0.18µm CMOS technology parameters.


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## Body

## 1. Introduction

The advances in semiconductor technology have led to the integration of high performance digital and analog circuits on the same silicon substrate. The traditional CMOS logic style does not provide an analog friendly environment due to the large switching noise [1–3]. Many alternate logic styles have been suggested in [3–6] and the reference mentioned therein. MOS current mode logic (MCML) style is the most promising one due to the lower switching noise in comparison to traditional CMOS logic style [6–9]. Also, it exhibits better power delay than the traditional CMOS logic style at high frequencies [6–15]. Therefore, MCML style is appropriate for designing high performance digital circuits wherein a D-latch is widely used as a building block in different applications such as prescalars, frequency dividers, and sequential logic circuits [16–20].The D-latch topology given in [16–20] is referred to as traditional D-latch and is based on the series-gating approach (i.e., stacked source-coupled transistor pairs) [9] which puts a limit on the minimum power supply. The power supply may, however, be lowered by reducing the number of stacked transistor pair levels with triple-tail cell concept [21–23]. In this paper, a new low-voltage MCML D-latch is proposed. The static parameters for the proposed D-latch are analytically modeled and applied to develop a design approach. From the knowledge of the transistor sizes, the delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage multiplexer is analyzed for high-speed and power-efficient design cases. A comparison in performance of the proposed D-latch with the traditional one is carried out for all the cases.The paper first briefs the operation of the traditional MCML D-latch in Section2. Thereafter, a new low-voltage MCML topology for the D-latch is proposed, and analytical formulations for different static parameters and delay are put forward in Section 3. The analysis of the proposed D-latch for the different design cases is presented, and its performance is compared with the traditional one in Section 4. Extensive SPICE simulations are carried out to validate the proposed theory. Section 5 concludes the paper.


## 2. Traditional MCML D-Latch

A traditional MCML D-latch with differential inputsD and CLK is shown in Figure 1 [24]. It consists of two levels of source-coupled transistor pairs to implement the logic function and a constant current source MTR1 to generate bias current ISS. The differential input CLK drives the lower level transistor pair MTR2-MTR3 that alternatively activates the upper level transistor pairs MTR4-MTR5 and MTR6-MTR7. When differential input CLK is high, MTR3 is OFF and the bias current ISS flows through MTR2 and is steered either to MTR4 or MTR5 according to the differential input D to ensure that the D-latch operates in the transparent state. Conversely, when the differential input CLK is low, the bias current ISS flows through MTR3 and is steered to one of the two transistors, that is, either MTR6 or MTR7 according to the previous output value such that the output does not respond to the changes in the input; thus, D-latch remains in the hold state. The bias current ISS is converted to the differential output voltage (VQ-VQ-) through the PMOS transistors MTR8 and MTR9 [24]. The load capacitance CL includes the effect of fanout and the interconnect capacitances.Figure 1
Traditional MCML D-latch.The minimum supply voltage,VDD_MIN_TR, for the traditional D-latch is defined as the lowest voltage at which all the transistors in the two levels and the current source operate in the saturation region [25] and is computed as
(1)VDD_MIN_TR=3VBIAS-3VT_TR1+VT_TR,
where VT_TR is the threshold voltage of the transistors MTR4,5,6,7, VT_TR1 is the threshold voltage of MTR1, and VBIAS is the biasing voltage of MTR1.


## 3. Proposed Low-Voltage MCML D-Latch

The proposed low-voltage D-latch with differential inputsD and CLK is shown in Figure 2. It consists of two triple-tail cells (MLV3, MLV4, MLV7) and (MLV5, MLV6, MLV8) biased by separate current sources of ISS/2 value. The transistors MLV7 and MLV8 are driven by the differential CLK input and are connected between the supply terminal and the common source terminal of transistor pairs MLV3-MLV4 and MLV5-MLV6, respectively. A high differential CLK voltage turns ON the transistor MLV8, and deactivates the transistor pair MLV5-MLV6. At the same time, the transistor MLV7 turns OFF so that the transistor pair MLV3-MLV4 generates the output according to the differential input D. Thus, the D-latch works in the transparent state. Similarly, the transistor pair MLV5-MLV6 gets activated for low differential CLK voltage and preserves the previous output. Therefore the D-latch operates in the hold state for low value of the differential CLK input.Figure 2
Proposed low-voltage D-latch.The minimum supply voltage,VDD_MIN_LV, for the proposed D-latch is computed by the method outlined in [25] as
(2)VDD_MIN_LV=2VBIAS-2VT_LV1+VT_LV,
where VT_LV is the threshold voltage of transistor MLV3,4,5,6, VT_LV1 is the threshold voltage of MLV1, and VBIASis the biasing voltage of MLV1.


### 3.1. Static Model

The static model is derived by modeling the load transistorsMLV9, MLV10 by an equivalent linear resistance, RP[26]. Using the standard BSIM3v3 model, the linear resistance, RP is computed as
(3)RP=Rint1-((RDSW10-6)/WP)/Rint,
where RDSW is the empirical model parameter, WP the channel width of the load transistor, and the parameter Rint is the intrinsic resistance of the PMOS transistor in the linear region and is given as
(4)Rint=[μeff,pCoxWPLP(VDD-|VT,p|)]-1,
where Coxis the oxide capacitance per unit area. The parameters μeff,p,VT,p,WP, and LPare the effective hole mobility, the threshold voltage, and the effective channel length of the load transistor, respectively.It may be noted that if equal aspect ratio of all transistors in the triple-tail cells is considered, then the transistorsMLV7 and MLV8 will not be able to completely switch OFF the transistor pair MLV3-MLV4 and MLV5-MLV6. Hence, for proper operation, the aspect ratio of transistors MLV7, MLV8 is made greater than the other transistors’ aspect ratio by a factor N. As an example if the value of differential input D is chosen such that the transistors MLV3, MLV5  are ON while the transistors MLV4, MLV6  are OFF, then a high differential CLK voltage turns ON the transistor MLV8. But since the transistors MLV5  and MLV8  have the same gate-source voltages, the currents flowing through MLV5  (iD,5) and MLV8 (iD,8) can be written as(5a)iD,5=ISS211+N,(5b)iD,8=ISS2N1+N.The current through MLV5 can be minimized by increasing factor N. This input condition produces minimum output voltage VOL as
(6)VOL=VQ-VQ-=RP[(iD,4+iD,6)-(iD,3+iD,5)]=-RPISS2(1+11+N),
where iD,3,iD,4,iD,5, and iD,6 are the currents through transistors MLV3, MLV4, MLV5, and MLV6, respectively. The differential output voltages for various input combinations are enlisted in Table 1. It can be observed from Table 1 that there are two values of maximum output voltage (VOH) and minimum output voltage (VOL) for different input and output combinations. Consequently, the voltage swing, VSWING1, when the input and output are the same can be expressed as(7a)VSWING1=VOH1-VOL1=RPISS(1+11+N),
where VOH1,VOL1 are maximum output voltage and minimum output voltage, respectively, for the same input/output. The voltage swing, VSWING2, when the input and output are different can be expressed as
(7b)VSWING2=VOH2-VOL2=RPISS(N1+N),where VOH2,VOL2 are maximum output voltage and minimum output voltage, respectively, for different input/output.Table 1
Differential output voltages of the proposed D-latch for various input combinations.
Differential inputs
Present state
Currents through the transistors
Next state differential output (VQ-VQ¯)
CLK
D
Q
M
LV3
M
LV4
M
LV5
M
LV6
M
LV7
M
LV8
Level
R
P
[
(
i
D
,
4
+
i
D
,
6
)
-
(
i
D
,
3
+
i
D
,
5
)
]
L
L
L
I
3
0
I
1
0
I
2
0
V
OL1
-
R
P
(
I
SS
/
2
)
(
1
+
1
/
(
1
+
N
)
)
L
L
H
I
3
0
0
I
1
I
2
0
V
OH2
R
P
(
I
SS
/
2
)
(
N
/
(
1
+
N
)
)
L
H
L
0
I
3
I
1
0
I
2
0
V
OL2
-
R
P
(
I
SS
/
2
)
(
N
/
(
1
+
N
)
)
L
H
H
0
I
3
0
I
1
I
2
0
V
OH1
R
P
(
I
SS
/
2
)
(
1
+
N
/
(
1
+
N
)
)
H
L
L
I
1
0
I
3
0
0
I
2
V
OL1
-
R
P
(
I
SS
/
2
)
(
1
+
N
/
(
1
+
N
)
)
H
L
H
I
1
0
0
I
3
0
I
2
V
OL2
-
R
P
(
I
SS
/
2
)
(
N
/
(
1
+
N
)
)
H
H
L
0
I
1
I
3
0
0
I
2
V
OH2
R
P
(
I
SS
/
2
)
(
N
/
(
1
+
N
)
)
H
H
H
0
I
1
0
I
3
0
I
2
V
OH1
R
P
(
I
SS
/
2
)
(
1
+
N
/
(
1
+
N
)
)
L
/
H = low/high differential input voltage, I1=ISS/2, I2=(ISS/2)(N/(1+N)), and I3=(ISS/2)(1/(1+N)).AsVSWING2<VSWING1, VSWING2has been considered as the worst case voltage swing:
(8)VSWING=RPISS(N1+N).
The small-signal voltage gain (Av) and noise margin (NM) for the proposed D-latch are computed by the method outlined in [26] as
(9)Av=gm,nRP=1+NNVSWING22μeff,nCOXWNLN1ISS(10)NM=VSWING2[1-2Av],
where μeff,n, gm,n, WN, and LN are the effective electron mobility, the transconductance, the effective channel width, and length of transistors MLV3,4,5,6, respectively.


### 3.2. Transistor Sizing

In this section, an approach to size the transistors of the proposed low-voltage D-latch on the basis of static model is developed.For a specified value of NM, factorN, and Av (≥1.4 for MCML [8]), the voltage swing of the proposed D-latch is calculated using (10) as
(11)VSWING=2NM1-(2/Av).
It may be noted that VSWING should be lower than the maximum value of 2VT so as to ensure that transistors MLV3,4,5,6 operate in saturation region. The voltage swing obtained from (11) requires sizing of the load transistor with equivalent resistance RP(=((1+N)/N)(VSWING/ISS)). To this end, the equivalent resistance, RP_MIN, for the minimum sized PMOS transistor is first determined, and then the bias current IHIGH for the required voltage swing is determined as
(12)IHIGH=VSWINGRP_MIN.
If the bias current is higher than IHIGH, then RPshould be less than RP_MIN, and this is achieved by setting LP to its minimum value, that is, LMIN and WP which is calculated by solving (3) and (4) as
(13)WP=N1+NISSVSWING(LMIN)×({1-RDSW10-6LMIN[μeff,pCox(VDD-|VT,p|)]}μeff,pCox(VDD-|VT,p|)ffff×{1-RDSW10-6LMINddddddd×[μeff,pCox(VDD-|VT,p|)]1-RDSW10-6LMIN})-1.
Similarly, if the bias current is lower than IHIGH, then RP should be greater than RP_MIN, and this is achieved by setting WP to its minimum value, that is, WMIN and LP which is calculated by solving (3) and (4) as
(14)LP=WMINμeff,pCox(VDD-|VT,p|)×(1+NNVSWINGISS-RDSW10-6WMIN).
The small-signal voltage gain (Av) (9) has been used to size transistors MLV3,4,5,6. Assuming minimum channel length for the said transistors, the width is computed as
(15)WN=2μeff,nCox(N1+N)2(AvVSWING)2ISSLMIN.
Sometimes (15) results in a value of WN smaller than the minimum channel width. This happens when the bias current is lower than the current of the minimum sized NMOS transistor, ILOW, given as
(16)ILOW=12(1+NN)2WMINLMINμeff,nCox(VSWINGAv)2from(9)
Therefore, in such cases, WN is also set to WMIN. For proper switching, the width of transistors MLV7,8 is made N times the width of transistors MLV3,4,5,6.The accuracy of the static model for the proposed D-latch is validated through SPICE simulations by using TSMC 0.18μm CMOS process parameters and with a power supply of 1.1 V. The proposed D-latch was designed and simulated for wide range of operating conditions: voltage swing of 300 mV and 400 mV, small-signal voltage gain of 2 and 4, N=5, and the bias current ranging from 10 μA to 100 μA. The designs were simulated, and the error in simulated and theoretical values for voltage swing, small-signal voltage gain, and noise margin using (8), (9), and (10), respectively, are calculated and are plotted in Figure 3. It may be noted that maximum error in voltage swing, small-signal voltage gain, and noise margin are 10%, 8%, and 14%, respectively.Errors in the static parameters (a) voltage swing, (b) small-signal voltage gain, and (c) noise margin.
(a)
(b)
(c)The impact of parameter variation on proposed low-voltage and traditional MCML D-latch performance is studied at different design corners. The findings for various operating conditions are given in Table2. It is found that the voltage swing, small-signal voltage gain, and noise margin of the proposed low-voltage D-latch varies by a factor of 1.8, 1.4, and 2.1, respectively, between the best and the worst cases. For the traditional MCML D-latch, the voltage swing, small-signal voltage gain, and noise margin vary by a factor of 1.7, 1.2, and 1.7, respectively, between the best and the worst cases. Thus, the proposed low-voltage D-latch shows slightly higher variations than those of the traditional MCML D-latch for different design corners which can be attributed to the smaller aspect ratio of transistors in the proposed low-voltage D-latch [8].Table 2
Effect of process variation on static parameters of the proposed and the traditional D-latch.
Parameter
NMOS
T
F
S
F
S
PMOS
T
F
S
S
F
V
SWING (mV)
Proposed
427
590
327
447
417
Traditional
416
508
300
509
457
A
v
Proposed
4.3
5.34
3.9
4.14
4.9
Traditional
4.34
4.42
4
4.46
5
NM (mV)
Proposed
143
216
104
147
148
Traditional
139
172
97
173
163
Different design corners are denoted by T: typical, F: fast, and S: slow.
Simulation condition:Av=4, VSWING=0.4 V, CL=100 fF, and ISS=100 µA.


### 3.3. Delay Model

In this section, a delay model of the proposed D-latch is formulated in terms of bias current and the voltage swing. For a low-to-high transition on CLK input that causes output to switch by activating (deactivating) the transistor pairMLV3-MLV4 (MLV5-MLV6), the circuit reduces to a simple MCML inverter. The equivalent linear half circuit is shown in Figure 4 where Cgdi,Cdbi represent the gate-drain capacitance and the drain-bulk junction capacitance of the ith transistor. For NMOS transistors operating in saturation region, Cgd is equal to the overlap capacitance CgdoWn between the gate and the drain [26]. For the PMOS transistor operating in linear region, Cgd is evaluated as the sum of the overlap capacitance and the intrinsic contribution associated with its channel charge [26]. The junction capacitance Cdb for the transistors is computed as explained in [27]. The input capacitance Cinput represents the input capacitance of the source-coupled pair (MLV5-MLV6) [9].Figure 4
Linear half circuit (with low-to-high transition on CLK).The delay of the proposed D-latch can be expressed as(17)tPD=0.69RP(Cdb3+Cgd3+Cgd9+Cdb9+Cdb5ffffffff+Cgd5+CL+Cinput)
with Cdb3=Cdb5, Cgd3=Cgd5 and, RP=((1+N)/N)(VSWING/ISS); (17) can be rewritten as
(18)tPD=0.691+NNVSWINGISS(2Cdb3+2Cgd3(0.691+NNVSWINGISS+Cgd9+Cdb9+CL+Cinput).
The capacitances may be expressed in terms of the bias current and the voltage swing as
(19)Cxy=axyISS(VSWING)2+bxyVSWINGISS+cxy,
where Cxy is the capacitance between the terminals x and y and axy, bxy, and cxy are the associated coefficients. Using (14) and (15), various capacitances in (18) for ISS ranging from ILOW to IHIGH may be expressed as
(20)Cgd3=CgdoW3=2Av2Cgdo(N1+N)2LMINμeff,nCOXISS(VSWING)2,
where Cgdo is the drain-gate overlap capacitance per unit transistor width. Consider the following:
(21)Cdb3=W3(KjnCjnLdn+2KjswnCjswn)+2KjswnCjswnLdn=2Av2LMINμeff,nCOX(N1+N)2(KjnCjnLdn+2KjswnCjswn)×ISS(VSWING)2+2KjswnCjswnLdn,
where Cjn, Cjswn are the zero-bias junction capacitance per unit area and zero-bias sidewall capacitance per unit parameter, respectively. The coefficients Kjn, Kjswn are the voltage equivalence factor for the junction and the sidewall capacitances [27]. Parameter Ldn is extrapolated from design rules [9]. Consider the following:
(22)Cinput=23CoxLMINW5=43μeff,n(N1+N)2(AvVSWING)2ISSLMIN2,(23a)Cgd9=CgdoWMIN+34Abulk,maxWMINLPCox(23b)=CgdoWMIN+34Abulk,maxWMINCox×{[1+NNVSWINGISS-RDSW10-6WMIN]μeff,pCoxWMIN(VDD-|VT,p|)fff×[1+NNVSWINGISS-RDSW10-6WMIN]},where Abulk,max is a parameter defined in BSIM3v3 model [24]. Consider the following:
(24)Cdb9=WMIN(KjpCjpLdp+2KjswpCjswp)+2KjswpCjswpLdp,
where Cjp, Cjswp are the zero-bias junction capacitance per unit area and zero-bias sidewall capacitance per unit parameter respectively. The coefficients Kjp, Kjswp are the voltage equivalence factor for the junction and the sidewall capacitances of the PMOS transistor, respectively [27]. Parameter Ldp is extrapolated from design rules [9]. The coefficients axy,bxy, and cxyof all the capacitances in (18) are summarized in Table 3. Using (20)–(24), (18) can be written as
(25)tPD=0.691+NNVSWING×(aVSWING2+bVSWINGISS2+c+CLISS),
where(26a)a=2adb3+2agd3+ainput(26b)b=bgd9(26c)c=2cdb3+cgd9+cdb9.The delay model can also be used for ISS value outside the range [ILOW, IHIGH]. This is because for ISS>IHIGH, the capacitance coefficients of PMOS transistor in (25) differ as explained in Section 3.2. But since for high values of ISS, the capacitive contribution of PMOS transistor is negligible, therefore (25) can predict the delay. Similarly, for ISS<ILOW, the capacitance coefficients of NMOS transistor in (25) differ. But since for low values of ISS, the delay majorly depends on the capacitances of PMOS transistor, so expression (25) can estimate the delay of the proposed D-latch.Table 3
Coefficients of the capacitances for the proposed D-latch.
NMOS coefficients
a
db3
(
2
A
v
2
L
MIN
/
µ
eff
,
n
C
ox
)
(
N
/
(
1
+
N
)
)
2
(
K
j
n
C
j
n
L
d
n
+
2
K
j
sw
n
C
j
sw
n
)
a
gd3
2
A
v
2
C
gdo
(
N
/
(
1
+
N
)
)
2
(
L
MIN
/
µ
eff
,
n
C
ox
)
a
input
(
4
A
v
2
/
3
µ
eff
,
n
)
(
N
/
(
1
+
N
)
)
2
L
MIN
2
c
db3
2
K
j
sw
n
C
j
sw
n
L
d
n
b
db3, bgd3, cgd3
0
PMOS coefficients
b
gd9
(
3
/
4
)
(
(
1
+
N
)
/
N
)
A
bulk,max
µ
eff
,
p
C
ox
2
W
MIN
2
(
V
DD
-
|
V
T
,
p
|
)
c
gd9
C
gdo
W
MIN
-
(
3
/
4
)
A
bulk,max
µ
eff
,
p
C
ox
2
W
MIN
(
V
DD
-
|
V
T
,
p
|
)
R
DSW
10
-
6
c
db9
K
j
p
C
j
p
L
d
p
W
MIN
+
2
K
j
sw
p
C
j
sw
p
(
L
d
p
+
W
MIN
)
a
gd9, adb9, bdb9
0
The symbols have their usual meaning.The accuracy of the delay model for the proposed D-latch is validated through SPICE simulations by using TSMC 0.18μm CMOS process parameters and with a power supply of 1.1 V. The proposed D-latch was designed for wide range of operating conditions: voltage swing of 300 mV and 400 mV, small-signal voltage gain of 2 and 4, the bias current ranging from 10 μA to 100 μA, N=5, and load capacitance of 0 fF, 10 fF, 100 fF, and 1 pF. It is found that there is a close agreement between the simulated and the predicted delay for all the operating conditions. The simulated and the predicted delay in particular for NM = 130 mV and Av=4 and with different load capacitances are plotted in Figure 5.Simulated and predicted delay of proposed D-latch versusISS with NM = 130 mV, Av=4, and different load capacitances (a) CL=0 fF, (b) CL=10 fF, (c) CL=100 fF, and (d) CL=1 pF.
(a)
(b)
(c)
(d)The impact of parameter variation on proposed low-voltage and traditional MCML D-latches delay is studied at different design corners. The findings for various operating conditions are given in Table4. It is found that the propagation delay of the proposed low-voltage D-latch varies by a factor of 1.8 between the best and the worst cases. For the traditional MCML D-latch, the delay varies by a factor of 1.7 between the best and the worst cases. Thus, the proposed low-voltage D-latch shows slightly higher variation than the traditional MCML D-latch in delay for different design corners which can be attributed to the smaller aspect ratio of transistors in the proposed low-voltage D-latch [8].Table 4
Effect of process variation on the delay of the proposed and the traditional D-latch.
Parameter
NMOS
T
F
S
F
S
PMOS
T
F
S
S
F
t
PD (ps)
Proposed
467
380
580
410
430
Traditional
589
565
984
587
590
Simulation condition:Av=4, VSWING=0.4 V, CL=100 fF, and ISS=100 µA.


## 3.1. Static Model

The static model is derived by modeling the load transistorsMLV9, MLV10 by an equivalent linear resistance, RP[26]. Using the standard BSIM3v3 model, the linear resistance, RP is computed as
(3)RP=Rint1-((RDSW10-6)/WP)/Rint,
where RDSW is the empirical model parameter, WP the channel width of the load transistor, and the parameter Rint is the intrinsic resistance of the PMOS transistor in the linear region and is given as
(4)Rint=[μeff,pCoxWPLP(VDD-|VT,p|)]-1,
where Coxis the oxide capacitance per unit area. The parameters μeff,p,VT,p,WP, and LPare the effective hole mobility, the threshold voltage, and the effective channel length of the load transistor, respectively.It may be noted that if equal aspect ratio of all transistors in the triple-tail cells is considered, then the transistorsMLV7 and MLV8 will not be able to completely switch OFF the transistor pair MLV3-MLV4 and MLV5-MLV6. Hence, for proper operation, the aspect ratio of transistors MLV7, MLV8 is made greater than the other transistors’ aspect ratio by a factor N. As an example if the value of differential input D is chosen such that the transistors MLV3, MLV5  are ON while the transistors MLV4, MLV6  are OFF, then a high differential CLK voltage turns ON the transistor MLV8. But since the transistors MLV5  and MLV8  have the same gate-source voltages, the currents flowing through MLV5  (iD,5) and MLV8 (iD,8) can be written as(5a)iD,5=ISS211+N,(5b)iD,8=ISS2N1+N.The current through MLV5 can be minimized by increasing factor N. This input condition produces minimum output voltage VOL as
(6)VOL=VQ-VQ-=RP[(iD,4+iD,6)-(iD,3+iD,5)]=-RPISS2(1+11+N),
where iD,3,iD,4,iD,5, and iD,6 are the currents through transistors MLV3, MLV4, MLV5, and MLV6, respectively. The differential output voltages for various input combinations are enlisted in Table 1. It can be observed from Table 1 that there are two values of maximum output voltage (VOH) and minimum output voltage (VOL) for different input and output combinations. Consequently, the voltage swing, VSWING1, when the input and output are the same can be expressed as(7a)VSWING1=VOH1-VOL1=RPISS(1+11+N),
where VOH1,VOL1 are maximum output voltage and minimum output voltage, respectively, for the same input/output. The voltage swing, VSWING2, when the input and output are different can be expressed as
(7b)VSWING2=VOH2-VOL2=RPISS(N1+N),where VOH2,VOL2 are maximum output voltage and minimum output voltage, respectively, for different input/output.Table 1
Differential output voltages of the proposed D-latch for various input combinations.
Differential inputs
Present state
Currents through the transistors
Next state differential output (VQ-VQ¯)
CLK
D
Q
M
LV3
M
LV4
M
LV5
M
LV6
M
LV7
M
LV8
Level
R
P
[
(
i
D
,
4
+
i
D
,
6
)
-
(
i
D
,
3
+
i
D
,
5
)
]
L
L
L
I
3
0
I
1
0
I
2
0
V
OL1
-
R
P
(
I
SS
/
2
)
(
1
+
1
/
(
1
+
N
)
)
L
L
H
I
3
0
0
I
1
I
2
0
V
OH2
R
P
(
I
SS
/
2
)
(
N
/
(
1
+
N
)
)
L
H
L
0
I
3
I
1
0
I
2
0
V
OL2
-
R
P
(
I
SS
/
2
)
(
N
/
(
1
+
N
)
)
L
H
H
0
I
3
0
I
1
I
2
0
V
OH1
R
P
(
I
SS
/
2
)
(
1
+
N
/
(
1
+
N
)
)
H
L
L
I
1
0
I
3
0
0
I
2
V
OL1
-
R
P
(
I
SS
/
2
)
(
1
+
N
/
(
1
+
N
)
)
H
L
H
I
1
0
0
I
3
0
I
2
V
OL2
-
R
P
(
I
SS
/
2
)
(
N
/
(
1
+
N
)
)
H
H
L
0
I
1
I
3
0
0
I
2
V
OH2
R
P
(
I
SS
/
2
)
(
N
/
(
1
+
N
)
)
H
H
H
0
I
1
0
I
3
0
I
2
V
OH1
R
P
(
I
SS
/
2
)
(
1
+
N
/
(
1
+
N
)
)
L
/
H = low/high differential input voltage, I1=ISS/2, I2=(ISS/2)(N/(1+N)), and I3=(ISS/2)(1/(1+N)).AsVSWING2<VSWING1, VSWING2has been considered as the worst case voltage swing:
(8)VSWING=RPISS(N1+N).
The small-signal voltage gain (Av) and noise margin (NM) for the proposed D-latch are computed by the method outlined in [26] as
(9)Av=gm,nRP=1+NNVSWING22μeff,nCOXWNLN1ISS(10)NM=VSWING2[1-2Av],
where μeff,n, gm,n, WN, and LN are the effective electron mobility, the transconductance, the effective channel width, and length of transistors MLV3,4,5,6, respectively.


## 3.2. Transistor Sizing

In this section, an approach to size the transistors of the proposed low-voltage D-latch on the basis of static model is developed.For a specified value of NM, factorN, and Av (≥1.4 for MCML [8]), the voltage swing of the proposed D-latch is calculated using (10) as
(11)VSWING=2NM1-(2/Av).
It may be noted that VSWING should be lower than the maximum value of 2VT so as to ensure that transistors MLV3,4,5,6 operate in saturation region. The voltage swing obtained from (11) requires sizing of the load transistor with equivalent resistance RP(=((1+N)/N)(VSWING/ISS)). To this end, the equivalent resistance, RP_MIN, for the minimum sized PMOS transistor is first determined, and then the bias current IHIGH for the required voltage swing is determined as
(12)IHIGH=VSWINGRP_MIN.
If the bias current is higher than IHIGH, then RPshould be less than RP_MIN, and this is achieved by setting LP to its minimum value, that is, LMIN and WP which is calculated by solving (3) and (4) as
(13)WP=N1+NISSVSWING(LMIN)×({1-RDSW10-6LMIN[μeff,pCox(VDD-|VT,p|)]}μeff,pCox(VDD-|VT,p|)ffff×{1-RDSW10-6LMINddddddd×[μeff,pCox(VDD-|VT,p|)]1-RDSW10-6LMIN})-1.
Similarly, if the bias current is lower than IHIGH, then RP should be greater than RP_MIN, and this is achieved by setting WP to its minimum value, that is, WMIN and LP which is calculated by solving (3) and (4) as
(14)LP=WMINμeff,pCox(VDD-|VT,p|)×(1+NNVSWINGISS-RDSW10-6WMIN).
The small-signal voltage gain (Av) (9) has been used to size transistors MLV3,4,5,6. Assuming minimum channel length for the said transistors, the width is computed as
(15)WN=2μeff,nCox(N1+N)2(AvVSWING)2ISSLMIN.
Sometimes (15) results in a value of WN smaller than the minimum channel width. This happens when the bias current is lower than the current of the minimum sized NMOS transistor, ILOW, given as
(16)ILOW=12(1+NN)2WMINLMINμeff,nCox(VSWINGAv)2from(9)
Therefore, in such cases, WN is also set to WMIN. For proper switching, the width of transistors MLV7,8 is made N times the width of transistors MLV3,4,5,6.The accuracy of the static model for the proposed D-latch is validated through SPICE simulations by using TSMC 0.18μm CMOS process parameters and with a power supply of 1.1 V. The proposed D-latch was designed and simulated for wide range of operating conditions: voltage swing of 300 mV and 400 mV, small-signal voltage gain of 2 and 4, N=5, and the bias current ranging from 10 μA to 100 μA. The designs were simulated, and the error in simulated and theoretical values for voltage swing, small-signal voltage gain, and noise margin using (8), (9), and (10), respectively, are calculated and are plotted in Figure 3. It may be noted that maximum error in voltage swing, small-signal voltage gain, and noise margin are 10%, 8%, and 14%, respectively.Errors in the static parameters (a) voltage swing, (b) small-signal voltage gain, and (c) noise margin.
(a)
(b)
(c)The impact of parameter variation on proposed low-voltage and traditional MCML D-latch performance is studied at different design corners. The findings for various operating conditions are given in Table2. It is found that the voltage swing, small-signal voltage gain, and noise margin of the proposed low-voltage D-latch varies by a factor of 1.8, 1.4, and 2.1, respectively, between the best and the worst cases. For the traditional MCML D-latch, the voltage swing, small-signal voltage gain, and noise margin vary by a factor of 1.7, 1.2, and 1.7, respectively, between the best and the worst cases. Thus, the proposed low-voltage D-latch shows slightly higher variations than those of the traditional MCML D-latch for different design corners which can be attributed to the smaller aspect ratio of transistors in the proposed low-voltage D-latch [8].Table 2
Effect of process variation on static parameters of the proposed and the traditional D-latch.
Parameter
NMOS
T
F
S
F
S
PMOS
T
F
S
S
F
V
SWING (mV)
Proposed
427
590
327
447
417
Traditional
416
508
300
509
457
A
v
Proposed
4.3
5.34
3.9
4.14
4.9
Traditional
4.34
4.42
4
4.46
5
NM (mV)
Proposed
143
216
104
147
148
Traditional
139
172
97
173
163
Different design corners are denoted by T: typical, F: fast, and S: slow.
Simulation condition:Av=4, VSWING=0.4 V, CL=100 fF, and ISS=100 µA.


## 3.3. Delay Model

In this section, a delay model of the proposed D-latch is formulated in terms of bias current and the voltage swing. For a low-to-high transition on CLK input that causes output to switch by activating (deactivating) the transistor pairMLV3-MLV4 (MLV5-MLV6), the circuit reduces to a simple MCML inverter. The equivalent linear half circuit is shown in Figure 4 where Cgdi,Cdbi represent the gate-drain capacitance and the drain-bulk junction capacitance of the ith transistor. For NMOS transistors operating in saturation region, Cgd is equal to the overlap capacitance CgdoWn between the gate and the drain [26]. For the PMOS transistor operating in linear region, Cgd is evaluated as the sum of the overlap capacitance and the intrinsic contribution associated with its channel charge [26]. The junction capacitance Cdb for the transistors is computed as explained in [27]. The input capacitance Cinput represents the input capacitance of the source-coupled pair (MLV5-MLV6) [9].Figure 4
Linear half circuit (with low-to-high transition on CLK).The delay of the proposed D-latch can be expressed as(17)tPD=0.69RP(Cdb3+Cgd3+Cgd9+Cdb9+Cdb5ffffffff+Cgd5+CL+Cinput)
with Cdb3=Cdb5, Cgd3=Cgd5 and, RP=((1+N)/N)(VSWING/ISS); (17) can be rewritten as
(18)tPD=0.691+NNVSWINGISS(2Cdb3+2Cgd3(0.691+NNVSWINGISS+Cgd9+Cdb9+CL+Cinput).
The capacitances may be expressed in terms of the bias current and the voltage swing as
(19)Cxy=axyISS(VSWING)2+bxyVSWINGISS+cxy,
where Cxy is the capacitance between the terminals x and y and axy, bxy, and cxy are the associated coefficients. Using (14) and (15), various capacitances in (18) for ISS ranging from ILOW to IHIGH may be expressed as
(20)Cgd3=CgdoW3=2Av2Cgdo(N1+N)2LMINμeff,nCOXISS(VSWING)2,
where Cgdo is the drain-gate overlap capacitance per unit transistor width. Consider the following:
(21)Cdb3=W3(KjnCjnLdn+2KjswnCjswn)+2KjswnCjswnLdn=2Av2LMINμeff,nCOX(N1+N)2(KjnCjnLdn+2KjswnCjswn)×ISS(VSWING)2+2KjswnCjswnLdn,
where Cjn, Cjswn are the zero-bias junction capacitance per unit area and zero-bias sidewall capacitance per unit parameter, respectively. The coefficients Kjn, Kjswn are the voltage equivalence factor for the junction and the sidewall capacitances [27]. Parameter Ldn is extrapolated from design rules [9]. Consider the following:
(22)Cinput=23CoxLMINW5=43μeff,n(N1+N)2(AvVSWING)2ISSLMIN2,(23a)Cgd9=CgdoWMIN+34Abulk,maxWMINLPCox(23b)=CgdoWMIN+34Abulk,maxWMINCox×{[1+NNVSWINGISS-RDSW10-6WMIN]μeff,pCoxWMIN(VDD-|VT,p|)fff×[1+NNVSWINGISS-RDSW10-6WMIN]},where Abulk,max is a parameter defined in BSIM3v3 model [24]. Consider the following:
(24)Cdb9=WMIN(KjpCjpLdp+2KjswpCjswp)+2KjswpCjswpLdp,
where Cjp, Cjswp are the zero-bias junction capacitance per unit area and zero-bias sidewall capacitance per unit parameter respectively. The coefficients Kjp, Kjswp are the voltage equivalence factor for the junction and the sidewall capacitances of the PMOS transistor, respectively [27]. Parameter Ldp is extrapolated from design rules [9]. The coefficients axy,bxy, and cxyof all the capacitances in (18) are summarized in Table 3. Using (20)–(24), (18) can be written as
(25)tPD=0.691+NNVSWING×(aVSWING2+bVSWINGISS2+c+CLISS),
where(26a)a=2adb3+2agd3+ainput(26b)b=bgd9(26c)c=2cdb3+cgd9+cdb9.The delay model can also be used for ISS value outside the range [ILOW, IHIGH]. This is because for ISS>IHIGH, the capacitance coefficients of PMOS transistor in (25) differ as explained in Section 3.2. But since for high values of ISS, the capacitive contribution of PMOS transistor is negligible, therefore (25) can predict the delay. Similarly, for ISS<ILOW, the capacitance coefficients of NMOS transistor in (25) differ. But since for low values of ISS, the delay majorly depends on the capacitances of PMOS transistor, so expression (25) can estimate the delay of the proposed D-latch.Table 3
Coefficients of the capacitances for the proposed D-latch.
NMOS coefficients
a
db3
(
2
A
v
2
L
MIN
/
µ
eff
,
n
C
ox
)
(
N
/
(
1
+
N
)
)
2
(
K
j
n
C
j
n
L
d
n
+
2
K
j
sw
n
C
j
sw
n
)
a
gd3
2
A
v
2
C
gdo
(
N
/
(
1
+
N
)
)
2
(
L
MIN
/
µ
eff
,
n
C
ox
)
a
input
(
4
A
v
2
/
3
µ
eff
,
n
)
(
N
/
(
1
+
N
)
)
2
L
MIN
2
c
db3
2
K
j
sw
n
C
j
sw
n
L
d
n
b
db3, bgd3, cgd3
0
PMOS coefficients
b
gd9
(
3
/
4
)
(
(
1
+
N
)
/
N
)
A
bulk,max
µ
eff
,
p
C
ox
2
W
MIN
2
(
V
DD
-
|
V
T
,
p
|
)
c
gd9
C
gdo
W
MIN
-
(
3
/
4
)
A
bulk,max
µ
eff
,
p
C
ox
2
W
MIN
(
V
DD
-
|
V
T
,
p
|
)
R
DSW
10
-
6
c
db9
K
j
p
C
j
p
L
d
p
W
MIN
+
2
K
j
sw
p
C
j
sw
p
(
L
d
p
+
W
MIN
)
a
gd9, adb9, bdb9
0
The symbols have their usual meaning.The accuracy of the delay model for the proposed D-latch is validated through SPICE simulations by using TSMC 0.18μm CMOS process parameters and with a power supply of 1.1 V. The proposed D-latch was designed for wide range of operating conditions: voltage swing of 300 mV and 400 mV, small-signal voltage gain of 2 and 4, the bias current ranging from 10 μA to 100 μA, N=5, and load capacitance of 0 fF, 10 fF, 100 fF, and 1 pF. It is found that there is a close agreement between the simulated and the predicted delay for all the operating conditions. The simulated and the predicted delay in particular for NM = 130 mV and Av=4 and with different load capacitances are plotted in Figure 5.Simulated and predicted delay of proposed D-latch versusISS with NM = 130 mV, Av=4, and different load capacitances (a) CL=0 fF, (b) CL=10 fF, (c) CL=100 fF, and (d) CL=1 pF.
(a)
(b)
(c)
(d)The impact of parameter variation on proposed low-voltage and traditional MCML D-latches delay is studied at different design corners. The findings for various operating conditions are given in Table4. It is found that the propagation delay of the proposed low-voltage D-latch varies by a factor of 1.8 between the best and the worst cases. For the traditional MCML D-latch, the delay varies by a factor of 1.7 between the best and the worst cases. Thus, the proposed low-voltage D-latch shows slightly higher variation than the traditional MCML D-latch in delay for different design corners which can be attributed to the smaller aspect ratio of transistors in the proposed low-voltage D-latch [8].Table 4
Effect of process variation on the delay of the proposed and the traditional D-latch.
Parameter
NMOS
T
F
S
F
S
PMOS
T
F
S
S
F
t
PD (ps)
Proposed
467
380
580
410
430
Traditional
589
565
984
587
590
Simulation condition:Av=4, VSWING=0.4 V, CL=100 fF, and ISS=100 µA.


## 4. Design Cases

In the previous section, the proposed D-latch has been modeled, and different parameters are expressed as a function of bias current and voltage swing. In practice, the voltage swing is set on the basis of the specified noise margin while the bias current is chosen according to power-delay considerations. Therefore, the proposed low-voltage D-latch for high-speed and power-efficient design cases is discussed.


### 4.1. High-Speed Design

A high-speed design requires bias current that results in minimum delay. The delay (25) decreases with the increasing ISS and tends to an asymptotic minimum value of 0.69((1+N)/N)(a/VSWING) for ISS→ ∞. A substantial improvement in delay with increasing bias current is achieved if condition
(27)aVSWING2≥bVSWINGISS2+c+CLISS
is satisfied. However, high value of bias current results in large transistor sizes. Therefore, the bias current should be set to such a value after which the improvement in speed is not significant. If equality sign in (27) is considered, then the delay is close to its minimum value, and the use of high bias current is avoided. Therefore, this assumption leads to a bias current (ISS_HS) and delay (tPD_MIN) as
(28)ISS_HS=c+CL2aVSWING2(1+1+4ab(c+CL)21VSWING)(29)tPD_MIN=2×0.691+NNaVSWING.
The proposed high-speed D-latch, designed with a power supply of 1.1 V, noise margin of 130 mV, small-signal gain of 4, N=5, and load capacitance of 100 fF, gives ISS_HS as 254 μA. A delay of 265 ps and 255 ps is obtained from (29) and simulations, respectively. On the contrary, a traditional high-speed D-latch designed using the method outlined in [24] and with power supply of 1.4 V for the same specifications results in a delay of 598 ps. This indicates that the proposed D-latch can achieve a much higher speed than the traditional one.


### 4.2. Power-Efficient Design

A power-efficient design requires a bias current that results in minimum power-delay product (PDP). The power is calculated as the product ofVDD and ISS. So, the PDP of the proposed D-latch may be expressed as
(30)PDP=0.69VDDVSWING1+NN×(aVSWING2ISS+bVSWINGISS+c+CL).
Therefore, the current ISS_PDP for minimum PDP may be given as
(31)ISS_PDP=ba(VSWING)3/2.
Accordingly, the minimum PDP results in
(32)PDP=0.69VDDVSWING1+NN(2abVSWING+c+CL).
The proposed power-efficient D-latch, designed with a power supply of 1.1 V, noise margin of 130 mV, small signal gain of 4, N=5, and load capacitance of 100 fF, gives ISS_PDP as 5.3 μA. A PDP value of 38.5 fJ has been obtained for the proposed D-latch. On the other hand, a traditional power-efficient D-latch designed using the method outlined in [24] and with power supply of 1.4 V for the same specifications results in a PDP value of 24 fJ. The result signifies that the proposed D-latch results in higher PDP values than the traditional one.


## 4.1. High-Speed Design

A high-speed design requires bias current that results in minimum delay. The delay (25) decreases with the increasing ISS and tends to an asymptotic minimum value of 0.69((1+N)/N)(a/VSWING) for ISS→ ∞. A substantial improvement in delay with increasing bias current is achieved if condition
(27)aVSWING2≥bVSWINGISS2+c+CLISS
is satisfied. However, high value of bias current results in large transistor sizes. Therefore, the bias current should be set to such a value after which the improvement in speed is not significant. If equality sign in (27) is considered, then the delay is close to its minimum value, and the use of high bias current is avoided. Therefore, this assumption leads to a bias current (ISS_HS) and delay (tPD_MIN) as
(28)ISS_HS=c+CL2aVSWING2(1+1+4ab(c+CL)21VSWING)(29)tPD_MIN=2×0.691+NNaVSWING.
The proposed high-speed D-latch, designed with a power supply of 1.1 V, noise margin of 130 mV, small-signal gain of 4, N=5, and load capacitance of 100 fF, gives ISS_HS as 254 μA. A delay of 265 ps and 255 ps is obtained from (29) and simulations, respectively. On the contrary, a traditional high-speed D-latch designed using the method outlined in [24] and with power supply of 1.4 V for the same specifications results in a delay of 598 ps. This indicates that the proposed D-latch can achieve a much higher speed than the traditional one.


## 4.2. Power-Efficient Design

A power-efficient design requires a bias current that results in minimum power-delay product (PDP). The power is calculated as the product ofVDD and ISS. So, the PDP of the proposed D-latch may be expressed as
(30)PDP=0.69VDDVSWING1+NN×(aVSWING2ISS+bVSWINGISS+c+CL).
Therefore, the current ISS_PDP for minimum PDP may be given as
(31)ISS_PDP=ba(VSWING)3/2.
Accordingly, the minimum PDP results in
(32)PDP=0.69VDDVSWING1+NN(2abVSWING+c+CL).
The proposed power-efficient D-latch, designed with a power supply of 1.1 V, noise margin of 130 mV, small signal gain of 4, N=5, and load capacitance of 100 fF, gives ISS_PDP as 5.3 μA. A PDP value of 38.5 fJ has been obtained for the proposed D-latch. On the other hand, a traditional power-efficient D-latch designed using the method outlined in [24] and with power supply of 1.4 V for the same specifications results in a PDP value of 24 fJ. The result signifies that the proposed D-latch results in higher PDP values than the traditional one.


## 5. Conclusions

A new low-voltage MCML D-latch based on the triple-tail cell concept is proposed. Its static parameters are analytically modeled and are used to develop a design approach for the proposed low-voltage MCML D-latch. The delay is formulated as a function of the bias current and the voltage swing and is traded off with power consumption for high-speed and power-efficient design cases. It is found that the proposed low-voltage D-latch is better than those of the traditional MCML D-latch for the high-speed design case.



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*Source: 217674-2013-11-04.xml*