# Design of New Nonisolated High Gain Converter for Higher Power Density

Authors: Ramachandran Rajesh; Natarajan Prabaharan
Journal: International Transactions on Electrical Energy Systems
 (2023)

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## Abstract

A high gain nonisolated DC-DC converter using a single power semiconductor switch is proposed in this article. The operation of the proposed converter is explained under continuous conduction mode (CCM), discontinuous conduction mode (DCM), and boundary conduction mode (BCM). The mathematical expressions for steady-state voltage gain, voltage stress, and current stress of diodes and switch are provided. Also, the design of inductors and capacitors in the CCM mode is explained with appropriate mathematical equations. The proposed topology is tested with a 200 W prototype at 50 kHz and a 60% duty cycle. The dynamic behavior of the proposed converter is examined by changing the duty cycle value and also load values. The proposed converter is verified with experimental results to prove the effectiveness of its operation. The proposed converter provides higher steady-state voltage gain as compared with recently developed topologies. The efficiency and power density of the proposed converter is 90% and 1.16 kW/L, respectively.


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## Body

## 1. Introduction

The increase in carbon emission and depletion of natural resources due to nonrenewable power generation affects the environment largely. This downside makes a gaining reputation in incorporating the renewable energy sources (RES). The development of RES like photovoltaic (PV) and wind are evolving around the globe in recent years. As per the International Energy Agency report [1], RES will be the largest source of electricity generation globally in 2025. The increase in PV installation capacity motivates the researchers to focus more on the DC-DC power conversion topologies for effective utilization of RES power [2]. The development of DC-DC power conversion topologies mainly depends on few significant parameters such as high efficiency, high conversion ratio, transformerless configuration, control techniques, low size, and less cost.The DC-DC converter can be classified broadly into two types such as isolated and nonisolated topologies [3]. The isolated topologies utilize a high-frequency transformer that acts as galvanic isolation between the source and the output as well as it increases the voltage gain of the converter by adjusting its turns ratio [4]. But it has certain drawbacks such as the higher volume and cost and saturation of the transformer. Considering RES application, the DC-DC converter plays vital role to provide good efficiency, high voltage gain, and low cost. Therefore, the development of new nonisolated topology for RES application is considered to be the right choice. But the nonisolated DC-DC converter topology should provide high voltage gain at low duty cycle which is the key challenge for designing a new topology. Though several changes have been incorporated on the traditional nonisolated converters to improve the voltage gain [5], but still there is the necessity to develop a new converter with high voltage gain at a low duty cycle with reduced stress.A voltage lift technique based on the high step-up DC-DC converter has developed in [6] for providing high voltage gain, but it utilizes two switches that may lead to increase in power loss of the converter. In [7], the buck-boost converter based on the ZETA converter has been designed with the single power semiconductor switch for automobile electronics. It has focused on both step-up and step-down conversion. The hybrid converter has been developed [8] by combining the cuk and boost converter that provides low output ripple and high voltage gain. It supports the hybridizing two input power sources such as photovoltaic cells, fuel cells, and battery. But the power loss is high due to multiple switches thereby reducing the efficiency [8]. The quadratic boost converter topology has been developed [9] such that it provides high voltage gain as compared with a conventional boost converter. But the topology has utilized two switches for achieving high voltage gain thereby increasing the overall loss of the converter and reducing the efficiency [9]. Many transformerless hybrid converter topologies have been developed with the help of voltage multiplier cells, switched capacitor, and switched inductor combinations for providing high voltage gain [10]. An improved hybrid topology has been developed [11] by combining the switched inductor and switched capacitor cells. The topology provides reasonable voltage gain at less duty cycle, but it utilizes three switches [11]. Voltage multiplier cells (VMC) are one of the best methods to increase the converter’s voltage gain. The development of high step-up converters with different multiplier cells continuously evolves yearly to improve their power density, efficiency, and fast dynamic response for different advantages and applications. Therefore, in this article, a new voltage multiplier cell is proposed with two inductors, two diodes, and four capacitors to provide the maximum voltage gain and reduced voltage stress across the main switch.The advantages of the proposed converter are given below:(i)
The proposed converter utilizes single switch with less voltage stress (0.59 times of output voltage) which produces higher voltage gain (G = 10.75) at 60% duty cycle(ii)
The power density and efficiency of the proposed converter are 1.16 kW/L and 90%, respectively(iii)
The dynamic behavior of proposed converter is examined under varying duty cycles and load conditionsFurthermore, the operation of the proposed converter is examined through the laboratory-based experimental prototype with 200 W.


## 2. Operation of the Proposed High Gain DC-DC Converter

The proposed high gain DC-DC converter topology is developed by combining the modified quadratic boost converter (MQDBC) with the unique voltage multiplier cell (VMC). The proposed high gain DC-DC converter topology is shown in Figure1, which consists of single switch S1, five inductors L1,L2,L3,L4andL5, seven capacitors C1,C2,C3,C4,C5,C6,andCo, six diodes D1,D2,D3,D4,D5andD6, and load R0. It has two modes of operation such as mode-I and mode-II in CCM. The topology consists of multiple components, but it operates at less duty cycle to provide higher voltage gain with reduced voltage and current stress which is the significant aspect of the proposed topology.Figure 1
Proposed high gain DC-DC converter.


### 2.1. Continuous Conduction Mode

#### 2.1.1. Mode-I

The operation of mode-I is explained when the switch is closed. The current path is shown in Figure2, where the energy from the DC input charges the inductor L1, and the capacitor C2 charges the inductor L2. The capacitor C4 charges the inductor L4 and C5 charges inductor L5. The combined charge of the capacitors C4 and C5 supports for charging the capacitors C3, C6, and C7. The capacitor C1 supports to charge the capacitor C3 and inductor L3. The capacitor C0 discharges the stored charge to the load:(1)VL1=Vi;VL2=VC2;VL3=VC1−VC3VL4=VC4−VC3−VC7;VL5=VC4+VC5−VC6−VC3−VC7.Figure 2
Equivalent circuit of proposed in mode-I.


#### 2.1.2. Mode II

The operation of mode-II is explained with two stages of operation when the switch is opened. The current path of the first stage of operation is shown in Figure3. Here, the energy stored in inductor L1 and the energy from DC source charges the capacitor C1 through D3. The stored energy in the inductor L2 & L3 and the capacitors C2 & C3 discharge through D3 and D4 to the capacitor C4. It should be noted that the capacitor C2 makes the D1 to be in reverse biased condition due to VC2>VC1. The inductor L4 charges the capacitor C5 through D5. The stored energy in the capacitor C7, C6, and inductor L5 discharges through D6 to charge the capacitor C0 and supply the energy to the load.Figure 3
Equivalent circuit of proposed converter in mode II (first stage).In the second stage of operation,VC2<VC1 makes the diode D1 in forward-biased condition. Therefore, the energy from the DC source charges the capacitor C2 through D1. The changes in current flow of the capacitor C3, C4, and inductor L3 occurs, which is predicted as shown in Figure 4:(2)VL1=Vi−VC2=Vi−VC1VL2=VC2+VC3−VC4VL3=−VC3;VL4=−VC5VL5=−VC6V0=Vi−VL1+VC7+VC6+VC3.Figure 4
Equivalent circuit of the proposed converter in mode II (second stage).The analytical waveform of the proposed converter under CCM is illustrated in Figure5. Applying the volt-sec balance principle on the inductors L1toL5, the following expressions can be obtained:(3)VC1=VC2=Vi1−D;VC3=VC5=VC6=DVi1−DVC4=1+D−D21−D2Vi;VC7=2D−D21−D2Vi,(4)Vi−VL1+VC7+VC6+VC3=V0.Figure 5
Analytical waveform of the proposed converter under CCM operation for one switching cycle.The proposed converter steady-state voltage gain (M) is derived by solving the equations (3) in (4) as(5)M=V0Vi=1+3D−3D21−D2.


### 2.2. Discontinuous Conduction Mode

The operation of the proposed converter in DCM is divided into three instants. At the first instantt0<t<t1, the switch S1 is closed. It is similar to the mode-I operation in CCM. At the second instant t1<t<t2, the switch S1 is opened and the inductor starts to decay. It is also similar to mode-II operation in CCM. At the third instant t2<t<t3, the switch S1 is still opened and the inductor currents decays to zero. The equivalent circuit of DCM mode for this instant is shown in Figure 6. It is noted that all the diodes are in reverse biased condition, and the stored energy in capacitor C6 is discharged to the load R0.Figure 6
Equivalent circuit of the proposed converter in DCM.Applying the volt-sec balance principle across the inductorsL1, L2, L3, L4, and L5 under DCM operation, the voltage gain and duty cycle can be obtained as follows:(6)GDCM=V0Vi=1+5DDm2+D2Dm22,(7)Dm2=D1.5.From the analytical waveform of the DCM operation, as shown in Figure7(a), the average current of diode D6 is derived, and it is expressed as given below:(8)iD6_avg=12Dm2ViDLeqfs.Figure 7
(a) Analytical waveform under DCM operation. (b) Voltage gain of CCM and DCM versus duty cycle. (c)Kb vs duty cycle.
(a)(b)(c)The duty cycle of “Dm2” is calculated as follows:(9)Dm2=KLGDCMD.The voltage transfer gainGDCM can be obtained by equating (7) and (9)as(10)GDCM=D21.5KL,where KL is the normalized inductor time constant, which is given as(11)KL=LeqfsR.Figure7(b) shows the plot between voltage gain versus duty cycle under CCM and DCM operation.


### 2.3. Boundary Conduction Mode

When the proposed converter is operated at the boundary of CCM and DCM, then the voltage gain of CCM and DCM is equal. Therefore, the normalized boundary inductor time constant “KB” is found by equating (5) and (10) as(12)Kb=D21−D21+3D−3D2.From Figure7(c), it is evident that if the “Kb” is larger than “KL,” then the converter operates in DCM else in CCM.


### 2.4. Design Considerations

The accurate design of proposed converter components is necessary to obtain the desired outcome. The voltage ripple and current ripple equations can be determined by applying amp-sec balance and volt-sec balance on the proposed converter capacitors and inductors, respectively:(13)iL5=2i01−D;iC5=2i0;iC6=i02D−11−DiL4=2i01−D+1−D2−i02D−121−DiL2=iL4+2D−1iC51−D;iC4=2i0D−iL4+iL2iL3=i0D−1+iC42D−1;iC2=iL2D1−DiC7=2i0−iL51−DD+iL4;iL1=iL3D1−D+iC7+iC2.Here,fs is the switching frequency of the switch S1:(14)ΔiL1=ViDL1fs;ΔiL2=ViD1−DL2fs;ΔiL3=ViDL3fsΔiL4=ViDL4fs;ΔiL5=ViD21−DL5fs.The capacitor ripple voltage are as follows:(15)ΔVC1=iC11−DC1fsΔVC2=iL1−iC1−iL5+iC6−iL21−DC2fsΔVC3=iC1+iL4+iC6DC3fs;ΔVC4=iL21−DC4fsΔVC5=iL41−DC5fs;ΔVC6=iC6DC6fsΔVC7=iL4+iC6DC7fs;ΔVC0=iL5+iC61−DC0fs.


### 2.5. Voltage and Current Stress Analysis

From the mode-I, the voltage stress of the diodesD1,3,4,5,6 and current stress of the switch S1 and diode D2 can be determined as(16)VD1=VD3=VD5=Vi1−DVD4=Vi1−D2;VD6=V0−Vi1+D−D21−D2,iD2=iL1+iC7D;iS1=iL1+iC7+iL2D.From the mode-II, the voltage stress of diodeD2, switch S1, and current stress of the diodes D1,3,4,5,6 can be calculated as(17)VD2=DVi1−D2;VS1=Vi1−D2,iD1=iC2+iL21−D;iD3=iC1+iL31−DiD4=iL21−D;iD5=iC5+iL51−DiD6=iC6+iL51−D.


## 2.1. Continuous Conduction Mode

### 2.1.1. Mode-I

The operation of mode-I is explained when the switch is closed. The current path is shown in Figure2, where the energy from the DC input charges the inductor L1, and the capacitor C2 charges the inductor L2. The capacitor C4 charges the inductor L4 and C5 charges inductor L5. The combined charge of the capacitors C4 and C5 supports for charging the capacitors C3, C6, and C7. The capacitor C1 supports to charge the capacitor C3 and inductor L3. The capacitor C0 discharges the stored charge to the load:(1)VL1=Vi;VL2=VC2;VL3=VC1−VC3VL4=VC4−VC3−VC7;VL5=VC4+VC5−VC6−VC3−VC7.Figure 2
Equivalent circuit of proposed in mode-I.


### 2.1.2. Mode II

The operation of mode-II is explained with two stages of operation when the switch is opened. The current path of the first stage of operation is shown in Figure3. Here, the energy stored in inductor L1 and the energy from DC source charges the capacitor C1 through D3. The stored energy in the inductor L2 & L3 and the capacitors C2 & C3 discharge through D3 and D4 to the capacitor C4. It should be noted that the capacitor C2 makes the D1 to be in reverse biased condition due to VC2>VC1. The inductor L4 charges the capacitor C5 through D5. The stored energy in the capacitor C7, C6, and inductor L5 discharges through D6 to charge the capacitor C0 and supply the energy to the load.Figure 3
Equivalent circuit of proposed converter in mode II (first stage).In the second stage of operation,VC2<VC1 makes the diode D1 in forward-biased condition. Therefore, the energy from the DC source charges the capacitor C2 through D1. The changes in current flow of the capacitor C3, C4, and inductor L3 occurs, which is predicted as shown in Figure 4:(2)VL1=Vi−VC2=Vi−VC1VL2=VC2+VC3−VC4VL3=−VC3;VL4=−VC5VL5=−VC6V0=Vi−VL1+VC7+VC6+VC3.Figure 4
Equivalent circuit of the proposed converter in mode II (second stage).The analytical waveform of the proposed converter under CCM is illustrated in Figure5. Applying the volt-sec balance principle on the inductors L1toL5, the following expressions can be obtained:(3)VC1=VC2=Vi1−D;VC3=VC5=VC6=DVi1−DVC4=1+D−D21−D2Vi;VC7=2D−D21−D2Vi,(4)Vi−VL1+VC7+VC6+VC3=V0.Figure 5
Analytical waveform of the proposed converter under CCM operation for one switching cycle.The proposed converter steady-state voltage gain (M) is derived by solving the equations (3) in (4) as(5)M=V0Vi=1+3D−3D21−D2.


## 2.1.1. Mode-I

The operation of mode-I is explained when the switch is closed. The current path is shown in Figure2, where the energy from the DC input charges the inductor L1, and the capacitor C2 charges the inductor L2. The capacitor C4 charges the inductor L4 and C5 charges inductor L5. The combined charge of the capacitors C4 and C5 supports for charging the capacitors C3, C6, and C7. The capacitor C1 supports to charge the capacitor C3 and inductor L3. The capacitor C0 discharges the stored charge to the load:(1)VL1=Vi;VL2=VC2;VL3=VC1−VC3VL4=VC4−VC3−VC7;VL5=VC4+VC5−VC6−VC3−VC7.Figure 2
Equivalent circuit of proposed in mode-I.


## 2.1.2. Mode II

The operation of mode-II is explained with two stages of operation when the switch is opened. The current path of the first stage of operation is shown in Figure3. Here, the energy stored in inductor L1 and the energy from DC source charges the capacitor C1 through D3. The stored energy in the inductor L2 & L3 and the capacitors C2 & C3 discharge through D3 and D4 to the capacitor C4. It should be noted that the capacitor C2 makes the D1 to be in reverse biased condition due to VC2>VC1. The inductor L4 charges the capacitor C5 through D5. The stored energy in the capacitor C7, C6, and inductor L5 discharges through D6 to charge the capacitor C0 and supply the energy to the load.Figure 3
Equivalent circuit of proposed converter in mode II (first stage).In the second stage of operation,VC2<VC1 makes the diode D1 in forward-biased condition. Therefore, the energy from the DC source charges the capacitor C2 through D1. The changes in current flow of the capacitor C3, C4, and inductor L3 occurs, which is predicted as shown in Figure 4:(2)VL1=Vi−VC2=Vi−VC1VL2=VC2+VC3−VC4VL3=−VC3;VL4=−VC5VL5=−VC6V0=Vi−VL1+VC7+VC6+VC3.Figure 4
Equivalent circuit of the proposed converter in mode II (second stage).The analytical waveform of the proposed converter under CCM is illustrated in Figure5. Applying the volt-sec balance principle on the inductors L1toL5, the following expressions can be obtained:(3)VC1=VC2=Vi1−D;VC3=VC5=VC6=DVi1−DVC4=1+D−D21−D2Vi;VC7=2D−D21−D2Vi,(4)Vi−VL1+VC7+VC6+VC3=V0.Figure 5
Analytical waveform of the proposed converter under CCM operation for one switching cycle.The proposed converter steady-state voltage gain (M) is derived by solving the equations (3) in (4) as(5)M=V0Vi=1+3D−3D21−D2.


## 2.2. Discontinuous Conduction Mode

The operation of the proposed converter in DCM is divided into three instants. At the first instantt0<t<t1, the switch S1 is closed. It is similar to the mode-I operation in CCM. At the second instant t1<t<t2, the switch S1 is opened and the inductor starts to decay. It is also similar to mode-II operation in CCM. At the third instant t2<t<t3, the switch S1 is still opened and the inductor currents decays to zero. The equivalent circuit of DCM mode for this instant is shown in Figure 6. It is noted that all the diodes are in reverse biased condition, and the stored energy in capacitor C6 is discharged to the load R0.Figure 6
Equivalent circuit of the proposed converter in DCM.Applying the volt-sec balance principle across the inductorsL1, L2, L3, L4, and L5 under DCM operation, the voltage gain and duty cycle can be obtained as follows:(6)GDCM=V0Vi=1+5DDm2+D2Dm22,(7)Dm2=D1.5.From the analytical waveform of the DCM operation, as shown in Figure7(a), the average current of diode D6 is derived, and it is expressed as given below:(8)iD6_avg=12Dm2ViDLeqfs.Figure 7
(a) Analytical waveform under DCM operation. (b) Voltage gain of CCM and DCM versus duty cycle. (c)Kb vs duty cycle.
(a)(b)(c)The duty cycle of “Dm2” is calculated as follows:(9)Dm2=KLGDCMD.The voltage transfer gainGDCM can be obtained by equating (7) and (9)as(10)GDCM=D21.5KL,where KL is the normalized inductor time constant, which is given as(11)KL=LeqfsR.Figure7(b) shows the plot between voltage gain versus duty cycle under CCM and DCM operation.


## 2.3. Boundary Conduction Mode

When the proposed converter is operated at the boundary of CCM and DCM, then the voltage gain of CCM and DCM is equal. Therefore, the normalized boundary inductor time constant “KB” is found by equating (5) and (10) as(12)Kb=D21−D21+3D−3D2.From Figure7(c), it is evident that if the “Kb” is larger than “KL,” then the converter operates in DCM else in CCM.


## 2.4. Design Considerations

The accurate design of proposed converter components is necessary to obtain the desired outcome. The voltage ripple and current ripple equations can be determined by applying amp-sec balance and volt-sec balance on the proposed converter capacitors and inductors, respectively:(13)iL5=2i01−D;iC5=2i0;iC6=i02D−11−DiL4=2i01−D+1−D2−i02D−121−DiL2=iL4+2D−1iC51−D;iC4=2i0D−iL4+iL2iL3=i0D−1+iC42D−1;iC2=iL2D1−DiC7=2i0−iL51−DD+iL4;iL1=iL3D1−D+iC7+iC2.Here,fs is the switching frequency of the switch S1:(14)ΔiL1=ViDL1fs;ΔiL2=ViD1−DL2fs;ΔiL3=ViDL3fsΔiL4=ViDL4fs;ΔiL5=ViD21−DL5fs.The capacitor ripple voltage are as follows:(15)ΔVC1=iC11−DC1fsΔVC2=iL1−iC1−iL5+iC6−iL21−DC2fsΔVC3=iC1+iL4+iC6DC3fs;ΔVC4=iL21−DC4fsΔVC5=iL41−DC5fs;ΔVC6=iC6DC6fsΔVC7=iL4+iC6DC7fs;ΔVC0=iL5+iC61−DC0fs.


## 2.5. Voltage and Current Stress Analysis

From the mode-I, the voltage stress of the diodesD1,3,4,5,6 and current stress of the switch S1 and diode D2 can be determined as(16)VD1=VD3=VD5=Vi1−DVD4=Vi1−D2;VD6=V0−Vi1+D−D21−D2,iD2=iL1+iC7D;iS1=iL1+iC7+iL2D.From the mode-II, the voltage stress of diodeD2, switch S1, and current stress of the diodes D1,3,4,5,6 can be calculated as(17)VD2=DVi1−D2;VS1=Vi1−D2,iD1=iC2+iL21−D;iD3=iC1+iL31−DiD4=iL21−D;iD5=iC5+iL51−DiD6=iC6+iL51−D.


## 3. Comparison with Recently Developed Quadratic Topologies

This section presents the comparison of proposed high gain DC converter with recently developed nonisolated topologies. Figure8(a) illustrates the comparison of voltage gain with various duty cycles. It is worth mentioning that the proposed converter provides higher voltage gain when compared to the topologies developed in [12–23]. Figure 8(b) clearly depicts the total semiconductor switch utilization and operating duty cycle of the proposed converter with other recently developed topologies. From Figure 8(b), it is clearly understood that the proposed converter utilizes a single semiconductor switch as compared with the topologies developed in [12–18, 22, 23]. Increase of semiconductor switch may increase the size of the converter and decrease the power density of the converter. The converters developed in [13–16, 18, 22, 23] were operated at higher duty cycle to obtain reasonable voltage gain which shall increase the conduction loss of the converter. The ratio of voltage gain (M) to Total Component Count (TCC) is measured to find the component utilization factor of the converter. The proposed converter is operated at a duty cycle of 60% which provides a voltage gain of 10.75. Figure 8(c) shows the comparison of M/TCC ratio of the proposed converter with recently developed topologies at duty cycle of 60%. It is noted that the proposed converter developed converter in [17, 22] has a same ratio (0.55), but those topologies utilizes more than a single semiconductor switch. Also, the component utilization factor is performed for a higher duty cycle of 0.8 for all converters, as shown in Figure 8(d). It is noted that the proposed converter has a higher M/TCC ratio as compared with other developed converters in [13, 15–23].Figure 8
Comparison of the proposed converter with recently developed converters found in [12–23]. (a) Voltage gain vs duty cycle. (b) TSS vs duty cycle. (c) Voltage gain/TCC for D = 0.6. (d) Voltage gain/TCC for D = 0.8.
(a)(b)(c)(d)


## 4. Experimental Results

In order to validate the functionality of the proposed converter in CCM operation, a laboratory-based 200 W prototype is developed. The proposed converter is operated at 50 kHz for an input voltage of 20 V with 60% duty ratio. The parameter of the proposed converter are listed in Table1.Table 1
Specifications of the proposed converter.
ComponentValuesDimensionInductorsL1 = 1.2 mH, L2 = 3 mH, L3 = L4 = 1 mH, L5 = 1.4 mH1.5 inch (L) × 1.15 inch (B) × 1.08 inch (H)CapacitorsC1 =C2 = 12 μF(ESY156M063AC3), C4 =C7 =10 μF (ESK106M160AH1), C3 =C5 =33 μF (ESY336M050AG1), C6 = 6.8 μF (ESY685M050AC2) and C0 = 5.6 μF (ESK685M250AG3)0.43 inch (L) × 0.19 inch (D), 0.47 inch (L) × 0.39 inch (D), 0.28 inch (L) × 0.31 inch (D), 0.28 inch (L) × 0.19 inch (D), 0.43 inch (L) × 0.31 inch (D)DiodesD1 = D3 = D5 = D6 = MUR1610CTG, D2 = MUR1615CTG0.42 inch (L) × 0.19 inch (B) × 1.18 inch (H)D4 = STTH2002)0.41 inch (L) × 0.18 inch (B) × 1.17 inch (H)MOSFETIXFH120N30X30.62 inch (L) × 0.19 inch (B) × 1.65 inch (H)L-length, B-breadth, H-height, D-diameter.The maximum height of the prototype is 1.65 inch, and the total area is 6.35 inch2. Therefore, the power density of the proposed converter is 1.16 kW/L. Figure 9(a) shows the input and output voltage waveform of the proposed converter where the output waveform is maximized in Figure 9(a) to show the magnitude of ripple voltage. It is 1.7% of the output voltage which is similar to the designed value. The obtained experimental result of output voltage is found to be 204 V which is 5% lower than the theoretical value. Figure 9(b) shows the input and output current waveform. The maximum value of input Iin and output current I0 obtained from the experimental result are 11 A and 0.88 A, respectively. The experimental results confirm that the output current is found to be continuous at 60% duty cycle. Therefore, the proposed topology is more suitable for renewable energy applications. Figure 9(c) represents the voltage and current stress of the switch. The maximum voltage across the switch during OFF-state is 121 V. During the ON-state, the maximum current flowing through the switch is 16.9 A. Figures 9(d)–9(f) show the voltage across the diodes. It is observed that the average voltage of diode D4 blocks the maximum voltage as compared with other diodes.Figure 9
(a) Input and output voltage, (b) input and output current, (c) voltage and current stress on switch, voltage across diodes, (d)D1 and D2, (e)D3 and D4, (f)D5 and D6, (g) voltage across capacitors C1 and C2, (h)C3 and C4, (i)C5 and C6, (j)C7 and C0, (k) output voltage and output current for the varying load, and (l) output voltage for the varying duty cycle.
(a)(b)(c)(d)(e)(f)(g)(h)(i)(j)(k)(l)The reverse peak voltage of the diodes isVRD1,3,5_peak=44V, VRD2_peak=79V, VRD4_peak=121V, and VRD6_peak=46V. The maximum voltage across the capacitor is shown in Figures 9(g)–9(j). The maximum value of the individual capacitor voltage is VC1=48V, VC2=49V, VC3=29.1V, VC4=151.4V, VC5=27V, VC6=26.9V, VC7=102.2V, and VC0=204V. These values are closely matched with the designed values. The dynamic behavior of the proposed converter is examined by changing the duty ratio and load values. Figure 9(k) shows the output voltage and output current for change in load. The values of the resistive load is adjusted (i.e., R=308Ω,R=230Ω,andR=230Ω) at 60% duty cycle. It is observed that the output voltage is maintained constant, and the output current varies with the load. Figure 9(l) shows the variation in output voltage for the various duty cycles. The proposed converter is tested by varying the duty cycle (i.e., D = 0.4, 0.5, and 0.6) for a constant load of R=185Ω.The power loss and efficiency of the proposed converter are analyzed to show the effectiveness of the proposed converter. The expression for the total power loss is(18)PLoss=Pind+Pcap+Pswitch+Pdiode,where Pind and Pcap are the total power loss of the inductors and capacitors, respectively. Pswitch and Pdiode are the total power loss of switch and diodes, respectively. The conduction loss and switching loss are considered for calculating the Pswitch.The power loss expression for individual components are given below:(19)Pind=∑n=15rLn.iLn2;Pcap=∑n=17rCn.iCn2Pdiode=∑n=1n≠26rFDn.1−DiDn2+VFDn.1−DiDn+rFD2.DiD22+VFD2.DiD2Pcond.loss=rDSDiS12Pswitching.loss=f.Cs.Vi1−D22,where rDS is the ON-state resistance of the MOSFET; rL and rC are the equivalent series resistance of inductor and capacitor, respectively; and rFD and VFD are the forward resistance and threshold voltages of the diode, respectively. Figures 10(a) and 10(b) show the cumulative loss of the proposed converter components and breakdown loss of the individual components in the proposed converter, respectively. The loss analysis for individual components will help to evaluate the efficiency of the converter. This proposed converter delivers an efficiency of 90% for an input voltage of 20 V with a 60% duty cycle for a switching frequency of 50 kHz. From the loss breakdown analysis, it is confirmed that the loss of diode D2 and conduction loss of the switch is higher than the other components.Figure 10
(a) Cumulative losses. (b) Loss breakdown analysis.
(a)(b)


## 5. Conclusion

A high gain DC-DC converter has been proposed and examined under CCM, DCM, and BCM in this article. The steady-state voltage gain has been derived along with the voltage stress and current stress of the components. The mathematical expression for designing the inductors and capacitors has been provided. The proposed topology has been tested with 200 W in the laboratory-based prototype, and the results have been obtained effectively. The proposed topology has tested with dynamic condition by changing the duty cycle and load value to check the feasibility of the topology. The efficiency and power density of the proposed converter is 90% and 1.16 kW/L, respectively. The proposed converter utilizes a single switch for achieving higher voltage gain so that it could be useful for RES applications.



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*Source: 2011926-2023-02-09.xml*