# A Novel Inverter Topology for Single-Phase Transformerless PV System

Authors: Haiyan Cao
Journal: Active and Passive Electronic Components
 (2016)

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## Abstract

Transformerless photovoltaic (PV) power system is very promising due to its low cost, small size, and high efficiency. One of its most important issues is how to prevent the common mode leakage current. In order to solve the problem, a new inverter is proposed in this paper. The system common mode model is established, and the four operation modes of the inverter are analyzed. It reveals that the common mode voltage can be kept constant, and consequently the leakage current can be suppressed. Finally, the experimental tests are conducted. The experimental results verify the effectiveness of the proposed solution.


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## Body

## 1. Introduction

The transformerless PV inverter has the prominent advantages of the small size, low cost, and high efficiency [1]. And more and more commercial transformerless PV inverters have been developed in recent years. However, there is no galvanic isolation between the input and output sides of the transformerless inverter, so it is prone to common mode leakage current problems [2]. The common mode leakage current not only affects the electromagnetic compatibility of the inverter [3], but also leads to the potential human safety problems [4].In order to solve this problem, Sunways Company developed HERIC inverter [5]. SMA Company developed H5 inverter [6]. Xiao and Xie presented a leakage current analytical model [7] and then developed the new optimized H5 [8], and split-inductor neutral point clamped inverters [9]. Cavalcanti et al. developed the space vector modulation techniques for three-phase two-level [10] and three-level [11] inverters. Guo et al. developed the carrier modulation techniques for three-phase inverters [12]. Yang et al. [13], Zhang et al. [14], and San et al. [15] developed the improved H6 inverter. And there is an increasing attention to develop the new inverter for transformerless PV applications.The main contribution of this paper is to develop a new single-phase transformerless PV inverter. Compared with HERIC in [5], only one auxiliary switch and gating driver are needed in the proposal. While in HERIC, two auxiliary switches are needed. Also, two auxiliary gating drivers should be designed for two auxiliary switches. Therefore, the proposal is more cost-effective and reliable, due to less auxiliary switches and gating drivers are used. On the other hand, three semiconductors conduct current during modes 2 and 4. While in Heric, two semiconductors conducts current during modes 2 and 4. Therefore, the main difference is that one additional diode loss. With the development of the commercially available Sic diode, the diode loss will be very small. So this difference due to one additional diode loss would be small. Finally, the theoretical analysis and experimental results validate the proposed solution.


## 2. Proposed Topology

Figure1 illustrates the schematic diagram of the proposed single-phase inverter. It consists of five switches and four diodes. C
P
V is the parasitic capacitance between PV array and ground. The capacitance value depends on many conditions such as the PV panel frame structure, weather conditions, and humidity, and it is generally up to 50–150 nF/kW. V
g is the grid voltage, and V
d is the dc bus voltage. L
a and L
b are filter inductors, respectively.Figure 1
Schematic diagram of proposed inverter.The common mode voltage and differential mode voltage are defined as(1)
U
C
M
=
U
A
N
+
U
B
N
2
,
U
D
M
=
U
A
N
-
U
B
N
.From (1), the following voltage equations can be obtained:(2)
U
A
N
=
U
C
M
+
U
D
M
2
,
U
B
N
=
U
C
M
-
U
D
M
2
.Figure2 shows the system common mode model. It can be observed that the differential mode voltage has the effect on the system common mode current if L
b
≠
L
a. Therefore, the filter inductance of L
a should be designed the same value as that of L
b; that is, L
a
=
L
b. So the differential mode voltage will not contribute the common mode current, as shown in Figure 2 [15]. Note that the common mode current is mainly due to the high frequency switching components. Therefore, the effect of grid voltage on the common mode voltage is neglected, because its frequency is much lower than the switching frequency [2].Figure 2
System common mode model.On the other hand, from Figure2, it can be observed that the common mode leakage current will be eliminated on condition that the common mode voltage U
C
M can be kept constant all the time. The reason is that the common mode leakage current, which passes through C
P
V, depends on C
P
V
d
U
C
P
V
/
d
t. When the common mode voltage U
C
M is constant, the voltage across C
P
V is constant as well. That is d
U
C
P
V
/
d
t
=
0. Therefore, the common mode leakage current can be eliminated if the common mode voltage U
C
M is constant. In order to achieve this goal, the following will present the operation principle.The proposed inverter operates in four modes, as shown in Figure3 and Table 1.Table 1
Four operation modes and common mode voltage.
S
1
S
2
S
3
S
4
S
5
U
A
N
U
B
N
U
C
M
Mode 1
1
0
0
1
0
V
d
0
V
d
/
2
Mode 2
0
0
0
0
1
V
d
/
2
V
d
/
2
V
d
/
2
Mode 3
0
1
1
0
0
0
V
d
V
d
/
2
Mode 4
0
0
0
0
1
V
d
/
2
V
d
/
2
V
d
/
2Figure 3
Switching state of the proposed inverter.In Mode 1, the switchesS
1 and S
4 turn on, and other switches turn off. The differential mode voltage U
A
B is equal to the dc bus voltage of V
d, while the common mode voltage can be expressed as(3)
U
C
M
=
1
2
U
A
N
+
U
B
N
=
1
2
V
d
+
0
=
V
d
2
.In Mode 2, only the switchS
5 turns on, and other switches turn off. The current flows through S
5 and diodes. In this case, the differential mode voltage U
A
B is 0, while the common mode voltage remains unchanged as(4)
U
C
M
=
1
2
U
A
N
+
U
B
N
=
1
2
V
d
2
+
V
d
2
=
V
d
2
.In Mode 3, the switchesS
2 and S
3 turn on, and other switches turn off. The differential mode voltage U
A
B is -
V
d, while the common mode voltage can be expressed as(5)
U
C
M
=
1
2
U
A
N
+
U
B
N
=
1
2
0
+
V
d
=
V
d
2
.In Mode 4, only the switchS
5 turns on, and other switches turn off. The current flows through S
5 and diodes. In this case, the differential mode voltage U
A
B is 0, while the common mode voltage remains unchanged as(6)
U
C
M
=
1
2
U
A
N
+
U
B
N
=
1
2
V
d
2
+
V
d
2
=
V
d
2
.From the above theoretical analysis, it can be observed that the common mode voltage remains constant during the whole operation cycle. Consequently, the common mode leakage current can be significantly suppressed, according to theoretical analysis of Figure2.The system design in terms of passive and active components is presented as follows. The rated system power is 1.5 kW, dc bus voltageV
d is 400 V, grid voltage V
g is 220 Vac, grid frequency is 50 Hz, and inverter switching frequency is 10 kHz.First of all, the active components such as the switches are designed in terms of the operating voltage, on-state current. The rated voltage and current stresses of switches (S
1, S
2, S
3, S
4, S
5) and diodes are 400 V and 10 A, respectively. Therefore, the IRG4IBC30S IGBT from International Rectifier is selected for five switches (S
1, S
2, S
3, S
4, S
5). Its collector-to-emitter breakdown voltage is 600 V, and the continuous collector currents are 23.5 A and 13 A, respectively, in case of T
C
=
25°C and T
C
=
100°C. The diode is FR20J02GN-ND from GeneSiC Semiconductor.Another design consideration is the filter inductor. Its inductance can be calculated according to the commonly used design criterion, in which the maximum current ripple magnitude is less than 10% of the rated current. The filter inductor current ripple can be calculated from Figure4 as follows.Figure 4
Operation modes of the proposed.
(a)
Mode 1
(b)
Mode 2
(c)
Mode 3
(d)
Mode 4In mode 1, the inductor current increases:(7)
V
d
-
V
g
=
V
d
-
V
m
sin
⁡
ω
t
=
L
a
+
L
b
Δ
I
1
T
1
,where V
m and ω is the amplitude and angular frequency of the grid voltage and T
1 is the time interval of mode 1.In mode 2, the inductor current decreases:(8)
-
V
m
sin
⁡
ω
t
=
L
a
+
L
b
Δ
I
2
T
2
,where T
2 is the time interval of mode 2, T
1
+
T
2
=
T
s, and T
s is the switching cycle.In steady state,Δ
I
1
=
Δ
I
2. So (
V
d
-
V
m
sin
⁡
ω
t
)
T
1
=
(
V
m
sin
⁡
ω
t
)
T
2. Considering T
1
=
T
s
-
T
2, we can obtain(9)
T
2
=
V
d
-
V
m
sin
⁡
ω
t
V
d
T
s
.Substituting (9) into (8), the inductor current ripple can be calculated as follows:(10)
Δ
I
2
=
-
V
m
sin
⁡
ω
t
L
a
+
L
b
T
2
=
V
m
sin
⁡
ω
t
L
a
+
L
b
V
d
-
V
m
sin
⁡
ω
t
V
d
T
s
.The current ripple reaches its maximum value whenV
m
sin
⁡
ω
t
=
V
d
/
2. In this case, the maximum current ripple is(11)
Δ
I
m
a
x
=
V
d
4
L
a
+
L
b
T
s
.In this paper,V
d is 400 V, T
s is 100 us, the rated current is 10 A, and the maximum current ripple should be less than 1 A; therefore, the filter inductor should be designed as follows:(12)
L
a
+
L
b
=
V
d
4
Δ
I
m
a
x
T
s
≥
0.01
H
.


## 3. Simulation and Experimental Results

In order to further verify the effectiveness of the proposed inverter, the performance test is conducted in MATLAB/Simulink. The components and parameters are listed as follows: system rated power is 1.5 kW, dc bus voltageV
d is 400 V, grid voltage V
g is 220 Vac, grid frequency is 50 Hz, switching frequency is 10 kHz, filter inductor is L
a
=
L
b
=
5 mH, and parasitic capacitor is C
P
V = 150 nF. The leakage current is obtained by measuring the current through the parasitic capacitor [10].Figure5 shows the operation of the proposed converter. The simulation results of the operation mode 1 and mode 2 are shown in Figure 5(a). In agreement with the theoretical analysis in Figure 4(a), when the switches S
1 and S
4 turn on, the collector-to-emitter voltage V
s
1 of S
1 is approximately zero, and its current I
s
1 increases with a slope of V
d
-
V
m
sin
⁡
ω
t
/
L
a
+
L
b. The simulation result waveforms of S
4 are the same as those of S
1 in mode 1 and thus not duplicated here for simplicity.Figure 5
Simulation results showing the operation of the converter.
(a)
Operation mode 1 and mode 2
(b)
Operation mode 3 and mode 4In mode 2, only the switchS
5 turns on, the collector-to-emitter voltage V
s
5 of S
5 changes from 400 V (in mode 1) to zero (in mode 2), and its current I
s
5 decreases with a slope of -
V
m
sin
⁡
ω
t
/
L
a
+
L
b.The last figure in Figure5(a) shows the filter inductor current, it can be observed that the inductor current I
g charges (in mode 1) and discharges (in mode 2) during a switching cycle, and the current ripple is less than 1 A, which is in good agreement with the design consideration in Section 2.The simulation results of the operation mode 3 and mode 4 are shown in Figure5(b). In agreement with the theoretical analysis in Figure 4(c), when the switches S
2 and S
3 turn on, the collector-to-emitter voltage V
s
2 of S
2 is approximately zero, and its current I
s
2 increases in mode 3. In mode 4, only the switch S
5 turns on, the collector-to-emitter voltage V
s
5 of S
5 changes from 400 V (in mode 3) to zero (in mode 4), and its current I
s
5 decreases. The last figure in Figure 5(a) shows the filter inductor current, it can be observed that the inductor current I
g charges and discharges during a switching cycle, and the current ripple is less than 1 A, which is in good agreement with the design consideration in Section 2.Figure6 shows the simulation results of output waveforms in the time and frequency domains. It can be observed that the output grid current is sinusoidal, and its total harmonic distortion (THD) is well below 5%, as specified in IEEE Std. 929-2000.Figure 6
Simulation results of output waveforms in the time and frequency domains.The simulation results of the common mode voltage and leakage current are shown in Figure7. It can be observed that the common mode voltage is constant, which is in agreement with the theoretical analysis in Section 2. On the other hand, the parasitic capacitor voltage does not include any high frequency common mode voltage, and therefore the leakage current is significantly reduced, as shown in Figure 7(c). Its peak value is below 300 mA, and the RMS value is below 30 mA, which meets the international standard VDE 0126-1-1.Figure 7
Simulation results of common mode voltage and leakage current.
(a)
Common mode voltage
(b)
Parasitic capacitor voltage
(c)
Common mode leakage current and spectrumAs shown in Figure8, with the proposed topology, it can be observed that the parasitic capacitor voltage has only the fundamental frequency component, without any high frequency components. Therefore, the leakage current can be effectively reduced below 300 mA, which complies with the international standard VDE 0126-1-1.Figure 8
Experimental results of parasitic capacitor voltage and leakage current.


## 4. Conclusion

This paper has presented the theoretical analysis and experimental verification of a new inverter for transformerless PV systems. The proposed inverter has the following interesting features. It can keep the system common mode voltage constant during the entire operation cycle. Consequently, the common mode leakage current can be significantly reduced well below 300 mA, which meets the international standard VDE 0126-1-1. Therefore, it is attractive and a promising alternative topology for transformerless PV system applications.



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*Source: 1962438-2016-01-13.xml*