# Design of Hybrid Posicast Control for Super-Lift Luo Converter

Authors: K. Ramash Kumar; J. Jayaudhaya; V. Tamilselvan; S. Balakumar
Journal: Mathematical Problems in Engineering
 (2022)

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## Abstract

This article investigates a new Hybrid Posicast Controller (HPC) for Fundamental Positive Output Super-Lift Luo Converter (FPOSLLC) in Continuous Conduction Mode (CCM). It is a feedforward controller that decreases the flippantly damped plant overshoot in the step result. However, because of fluctuations in the natural frequency, the traditional controller technique is sensitive. In this article, a novel HPC is built to alleviate the FPOSLLC’s undesired sensitivity and load voltage control. HPC has a feedback loop and a posicast structure. The main design function of posicast is its independent computational time delay. By creating a MATLAB/Simulink model, the FPOSLLC implementation with HPC may be verified under various operating conditions. In comparison to standard PID control, the results of the new HPC have produced little noise in the control signal.


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## Body

## 1. Introduction

Luo Converters (LCs) are a type of DC-DC converter that converts a constant DC source voltage to a variable DC load voltage. LCs are more well known in a variety of applications, including renewable energy sources, DC microgrids, electric vehicle battery charging, medical instruments, and FACTS devices, among others. The LCs are nonlinear lightly damped dynamic systems with load limitations, storage components, and an operating duty cycle that explain their performance. As a result, LC controller design is more complicated and puzzling [1]. As a result, the Fundamental Positive Output Super-Lift Luo Converter (FPOSLLC) is chosen for controller design in this article. A FPOSLLC is a type of LC topology. In [2, 3], a control with posicast fundamental is thoroughly explained. It is a feedforward controller for flippantly damped plants that eliminates the oscillatory response. However, the fundamental problem with this control strategy is its sensitivity to plant ambiguity. If the plant’s sensitivity is eliminated, the posicast with feedback loop technique is more worthwhile. Support for posicast in a feedback loop solves this problem [4]. The verification of nonlinear controllers for LC has been extensively documented [5]. The developed controller, on the other hand, produced zero overshoot and required only 0.014 s to settle through the transient state for the same converter. The operation of an FPOSLLC in CCM with a Fuzzy Logic Controller (FLC) and a Sliding Mode Controller (SMC) is described in detail [6]. Despite this, in the transient operating state, this FPOSLLC with controller has produced a settling time of 0.006 s.A study of competent LCs in an open loop for a DC microgrid has been published [7]. However, it is clear that the load voltage of this model caused large overshoots and required a long time to settle. FPOSLLC with classical Proportional Integral (PI) controller is discussed [8]. During the transient stage, the PI control for the same model exhibited huge overshoots in line/load changes and needed a long settling time of 0.038 s. The results of a wide-ranging examination of numerous factors for FPOSLLC are well described [9]. The converter was run in open-loop mode in this article. The design of an LC with a stepping-down converter for EV is described in depth [10]. FPOSLLC performance under multitudinous control has been studied [11]. According to this report, the designed controller resulted in massive overshoots and a protracted settling time. Modified LCs are considered in terms of modelling and adaptive control [12]. The main issue with this control for LCs, however, is that it has resulted in noise in the control signals and enormous ripple factors [13]. There is a lot of information about the LC with power factor correction and output voltage regulation. However, the intended system has produced a THD of 3.15 percent, a long settling period, greater in-rush source current, and massive overshoots in the startup zone. The usage of a PV-fed LC for wiper motors has been documented [14]. Nonetheless, the LC has resulted in massive overshoots in the startup region. Various researchers have examined how traditional PID control for many power converters may necessitate unnecessary configuration to achieve good transient and steady-state performance. Extra switching noise and two stages of gains have resulted from these adjustments. A real-time digital PID implementation for a DC-DC power converter is also more complicated. The features of design of posicast controller for DC-DC power converter has excellent transient/steady-state response, proficient damping of resonant characteristics, easy computation of controller parameters, simple implementation in digital mode, frequency responses of posicast element innately minimized high frequency noise, and elimination of additional controller gain over PID control. Modelling of modified ultra-lift LC is addressed [15]. The use of modelling and SMC for LCs has been well documented [16]. However, according to this paper, the planned model was run at a variable frequency, which resulted in a significant quantity of noise in the control signal. FLC with fused LC-based renewable energy system is recorded [17]. From this article, converter with designed controller has generated more steady-state error along with overshoots. Voltage mode control for positive output elementary LC has been presented [18]. However, the developed control for same converter has resulted in more peak overshoots of 3 V and took long settling time. Novel high gain DC-DC step converter for PV system is well addressed in [19]. However, the simulated output voltage of the designed converter has produced more startup peak overshoots of 20 V. The phase shifting soft switching-based resonant bidirectional DC-DC converter with current limiting has been discussed [20]. The structure of converter has more number of components and also generates the current/voltage stresses of the devices. The design of effective controller for KY boost converter has been discussed [21]. From this article, output voltage of the same model with control has produced long settling time during the start-up transient and steady state regions.According to the aforementioned literature review, FPOSLLC with a new Hybrid Posicast Controller (HPC) is yet to be disclosed. As a result, this research introduces a novel HPC in CCM for FPOSLLC. The FPOSLLC’s controller values are designed with the use of small-signal averaged modelling. The HPC with FPOSLLC is validated using a MATLAB/Simulink model under various operating conditions.The following are the key contributions of this article:(i)
First, the mathematical modelling of FPOSLLC is obtained, and then the HPC/PID control for FPOSLLC is designed.(ii)
Second, simulation assessments for FPOSLLC over traditional PID control are performed using specially built HPC.(iii)
Finally, PID control is used to discuss the time-domain parameters of the proposed controller.The organization of this article is as follows. Introduction, literature survey, and motivation of the proposed system are discussed in Section1. The working and modelling of FPOSLLC are discussed in Section 2. Section 3 presents the detailed design procedure of a new HPC and PID control for FPOSLLC. Results and discussions of designed model with controllers are tested at different working states in Section 4. Section 5 draws the conclusions.


## 2. FPOSLLC Working and Modelling

### 2.1. Working of FPOSLLC

A FPOSLLC in CCM is represented in Figure1(a) [1]. It involves Vin (C1, Co, L parasitic resistances (rc1, rc, rL)), S (Da, Db), Vo, and R. Operation of this circuit is alienated into two states of working. In mode 1 (see Figure 1(a)), the switch S is turned on, and then, Da is conduct/the Db is a reverse bias, the L and the C1 are energized to Vin. Co stored energy released to R. iL rises with Vin. During mode 2 operation (Figure 1(c)), S is open, and iL falls with voltage (2Vin−Vo) to offer the energy to Co and R via Db. So, the ripple of iL can be expressed as(1)ΔiL=VinLδT=Vo−2VinLδT,(2)Vo=2−δ1−δVin.Figure 1
FPOSLLC circuit. (a) Topology. (b) Mode 1 working. (c) Mode 2 working.
(a)(b)(c)


### 2.2. Modelling of FPOSLLC

The FPOSLLC consists of three storage components. Therefore, assign three state variables such asiL = x1, Vc1 = x2, and Vo = x3, respectively. Then, state-space differential equations of the FPOSLLC in mode 1 can be engraved as [16].(3)LdiLdt=Vin,C1dVc1dt=−iL−Vc1Ri+VinRi,CodVodt=−VoR.SwitchON,State-space differential equations of the FPOSLLC in mode 2 can be inscribed as [16](4)LdiLdt=Vin+Vc1−Vo,C1dVc1dt=−iL,CodVodt=iL−VoR.SwitchOFF,The state-space average modelling of the FPOSLLC can be attained with support of the equations (1) and (2), and it is written as(5)iL˙Vc1˙Vo˙=01L−1−δL1C1−δRiC101−δCo0−1RCoiLVc1Vo+1−δLδRiC10Vin,Y=001iLVc1Vo,(6)A=Aonδ+Aoff1−δ,B=Bonδ+Boff1−δ,C=Conδ+Coff1−δ,A=01L−1−δL1C1−δRiC101−δCo0−1RCo,B=1−δLδRiC10,C=001,D=000,where A, B, C, and D are FPOSLLC state-space averaged matrices and δ is duty cycle.The transfer function (small signal) model of FPOSLLC and eliminatingRi in (4), (5), (6), and (7) is expressed as (7)vo∧δ∧=CSI−A−1Aon−AoffX+Bon−BoffVin+Con−CoffXGs=vo∧δ∧=Vin−sL2−δ/1−δ2+Rs2LRCo+sL+R1−δ2.


### 2.3. Design Calculation of FPOSLLC Circuit Components

The FPOSLLC parameters are developed with the pursuing specifications as chronicled in Table1.Table 1
Parameters of FPOSLLC.
ParameterSymbolValueSource voltage step inputVin12 VLoad voltageVo36 VFilter coilL100μHFilter capacitorC1 & Co30μFOperating frequencyfs100 kHzLoad resistanceR50 ΩOvershootλ0.8Natural period (damped)Td2.44 msDuty cycleδ0.5The design calculation of the FPOSLLC is as follows [5].(i)
Take theδ for FPOSLLC operated in CCM, which is computed using(8)VoVin=2−δ1−δ−1,δ=0.667.(ii)
DetermineIo by using(9)Io=VOR=3650=0.72A.(iii)
EvaluatePo by using(10)Po=VOIOPo=−36∗−0.72Po=25.92W.(iv)
Take the efficiency of the FPOSLLC as 91.8% for this study. Next, compute Pin using the efficiency value and(11)η=91.79%,Pin=Po/η,Pin=25.920.9179,Pin=28.238W.(v)
Estimate Iin via(12)Iin=PinVin=28.23812,Iin=2.353A.(vi)
SelectΔiL=0.6A by using the specified nominal switching frequency set in Table 1, to be applied in equation (13), and calculate the essential value of the inductor.(13)L=VinfΔiL1δ,L=12100e3∗0.6∗0.667,L=100μH.(vii)
AssumeΔVo=0.12V by using fs in Table 1, to be applied in equation (14), and evaluate Co and C1.(14)Co=1−δVofΔVoR,Co=1−0.667∗−36100e3∗−0.16∗50,Co=C1=30μF.Substitute the FPOSLLC specification in (7) to attain the model in Figure 2(a).Figure 2
(a) MATLAB/Simulink model of the FPOSLLC and (b) simulated open-loop response of the FPOSLLC.
(a)(b)


### 2.4. Open-Loop Study of the FPOSLLC

The MATLAB/Simulink model block diagram and its simulated result of the FPOSLLC in open-loop mode are displayed in Figures2(a) and 2(b) with Vin = 12 V and Vo = 36 V. It is clearly found that the FPOSLLC in open-loop mode has created massive overshoots and took a long time to settle. In order to solve this problem, a new posicast control is designed for FPOSLLC in CCM.


## 2.1. Working of FPOSLLC

A FPOSLLC in CCM is represented in Figure1(a) [1]. It involves Vin (C1, Co, L parasitic resistances (rc1, rc, rL)), S (Da, Db), Vo, and R. Operation of this circuit is alienated into two states of working. In mode 1 (see Figure 1(a)), the switch S is turned on, and then, Da is conduct/the Db is a reverse bias, the L and the C1 are energized to Vin. Co stored energy released to R. iL rises with Vin. During mode 2 operation (Figure 1(c)), S is open, and iL falls with voltage (2Vin−Vo) to offer the energy to Co and R via Db. So, the ripple of iL can be expressed as(1)ΔiL=VinLδT=Vo−2VinLδT,(2)Vo=2−δ1−δVin.Figure 1
FPOSLLC circuit. (a) Topology. (b) Mode 1 working. (c) Mode 2 working.
(a)(b)(c)


## 2.2. Modelling of FPOSLLC

The FPOSLLC consists of three storage components. Therefore, assign three state variables such asiL = x1, Vc1 = x2, and Vo = x3, respectively. Then, state-space differential equations of the FPOSLLC in mode 1 can be engraved as [16].(3)LdiLdt=Vin,C1dVc1dt=−iL−Vc1Ri+VinRi,CodVodt=−VoR.SwitchON,State-space differential equations of the FPOSLLC in mode 2 can be inscribed as [16](4)LdiLdt=Vin+Vc1−Vo,C1dVc1dt=−iL,CodVodt=iL−VoR.SwitchOFF,The state-space average modelling of the FPOSLLC can be attained with support of the equations (1) and (2), and it is written as(5)iL˙Vc1˙Vo˙=01L−1−δL1C1−δRiC101−δCo0−1RCoiLVc1Vo+1−δLδRiC10Vin,Y=001iLVc1Vo,(6)A=Aonδ+Aoff1−δ,B=Bonδ+Boff1−δ,C=Conδ+Coff1−δ,A=01L−1−δL1C1−δRiC101−δCo0−1RCo,B=1−δLδRiC10,C=001,D=000,where A, B, C, and D are FPOSLLC state-space averaged matrices and δ is duty cycle.The transfer function (small signal) model of FPOSLLC and eliminatingRi in (4), (5), (6), and (7) is expressed as (7)vo∧δ∧=CSI−A−1Aon−AoffX+Bon−BoffVin+Con−CoffXGs=vo∧δ∧=Vin−sL2−δ/1−δ2+Rs2LRCo+sL+R1−δ2.


## 2.3. Design Calculation of FPOSLLC Circuit Components

The FPOSLLC parameters are developed with the pursuing specifications as chronicled in Table1.Table 1
Parameters of FPOSLLC.
ParameterSymbolValueSource voltage step inputVin12 VLoad voltageVo36 VFilter coilL100μHFilter capacitorC1 & Co30μFOperating frequencyfs100 kHzLoad resistanceR50 ΩOvershootλ0.8Natural period (damped)Td2.44 msDuty cycleδ0.5The design calculation of the FPOSLLC is as follows [5].(i)
Take theδ for FPOSLLC operated in CCM, which is computed using(8)VoVin=2−δ1−δ−1,δ=0.667.(ii)
DetermineIo by using(9)Io=VOR=3650=0.72A.(iii)
EvaluatePo by using(10)Po=VOIOPo=−36∗−0.72Po=25.92W.(iv)
Take the efficiency of the FPOSLLC as 91.8% for this study. Next, compute Pin using the efficiency value and(11)η=91.79%,Pin=Po/η,Pin=25.920.9179,Pin=28.238W.(v)
Estimate Iin via(12)Iin=PinVin=28.23812,Iin=2.353A.(vi)
SelectΔiL=0.6A by using the specified nominal switching frequency set in Table 1, to be applied in equation (13), and calculate the essential value of the inductor.(13)L=VinfΔiL1δ,L=12100e3∗0.6∗0.667,L=100μH.(vii)
AssumeΔVo=0.12V by using fs in Table 1, to be applied in equation (14), and evaluate Co and C1.(14)Co=1−δVofΔVoR,Co=1−0.667∗−36100e3∗−0.16∗50,Co=C1=30μF.Substitute the FPOSLLC specification in (7) to attain the model in Figure 2(a).Figure 2
(a) MATLAB/Simulink model of the FPOSLLC and (b) simulated open-loop response of the FPOSLLC.
(a)(b)


## 2.4. Open-Loop Study of the FPOSLLC

The MATLAB/Simulink model block diagram and its simulated result of the FPOSLLC in open-loop mode are displayed in Figures2(a) and 2(b) with Vin = 12 V and Vo = 36 V. It is clearly found that the FPOSLLC in open-loop mode has created massive overshoots and took a long time to settle. In order to solve this problem, a new posicast control is designed for FPOSLLC in CCM.


## 3. Design Controllers

### 3.1. Principle of Posicast

The step result of lightly damped model is revealed in Figure3. It is categorized by λ and Td [2, 3]. Figure 4 indicates the structure of a classical half-cycle posicast. It is intended based on λ and Td. Precise information of the step result constraints produces control whose smallest zero frequency revokes the leading plant pair. It is known as half-cycle since the surrounded time delay is Td/2. Therefore, HPC arrangement is explained in Figure 5.Figure 3
Step result of a flippantly damped FPOSLLC.Figure 4
The classical half-cycle posicast.Figure 5
FPOSLLC with HPC.The posicast function is prearranged via the following equation [2, 21]:(15)Ps=λ1+λe−sTd/2−1.P(s) are λ and Td. It fundamentally reforms the set values into two portions; primarily, control minus the scale quantity from the set value (R), in order to the peak of a lightly damped result matches to the set final value of FPOSLLC result. The peak time of the step response is Td/2. Next, in this time delay, the complete value of the step reference is smeared to G(s), ensuring that Vo remains constant at set value. Alternative clarification is that the set value, which was previously removed from the input, now cancels any undesirable overshoots since it is delayed by Td/2.


### 3.2. Modelling of Hybrid Posicast Controller

The main components of HPC are as follows: P(s) is the scaling factor parameterized byλ and the time delay element parameterized by Td. There are two design steps for HPC. First, P(s) is developed for the averaged model of the FPOSLLC. Then, C(s) is framed to compensate joined model of (1 + P(s)) G(s). The classical frequency-domain approach is provided. A pure integrator type compensator is matched for the FPOSLLC to stabilize steady-state disturbances.(16)Cs=Ks.The gainK is selected to reduce the settling time as much as feasible, but not to the point where the overshoot is excessive. A new HPC model (17) is attained by joining the compensator C(s) and the P (s) [3, 21].(17)Cs1+Ps=Ks1+λ1+λe−sTd/2−1.


### 3.3. Design of a New HPC

Small-signal model transfer function of the FPOSLLC is(18)Gs=vo∧λ∧=12600e−6s+50150000e−12s2+100e−6s+12.5.Undamped natural frequency is(19)ωn=1LC,(20)Td=2πωn1−ζ2,(21)λ=e−πζ/1−ζ2.The values of the new HPC parameters are computed using equations (18)–(21). Then, Td = 0.00219 s and λ = 0.8. The K gain is designed to be as bulky as conceivable to reduce settling time of settling while avoiding unjustified overshoot, and it is fixed to be 7 in this work [2–4, 21].Now, the model of HPC is(22)Cs1+Ps=7s1+0.444e−0.001s−1.Figure8 shows the frequency analysis of HPC in an open-loop model, C(s) (1 + P(s)) G(s). The gain margin is approximately infinity, while the phase margin is around 89.8°.


### 3.4. PID Controller

For the output voltage regulation of FPOSLLC, standard controllers based on the PID control are frequently utilized. The PID controller approach may effectively control the low-order dynamics of power modulators. Traditional PID controller is problematic to surpass in this case because the integrator raises the converter type number, reducing the fixed state error. Controller has two zeros allowing for booming physiognomies to be dampened and the transient result to be enhanced. The PID controller is a simple structure for understanding in comparison with other control methodologies. For new HPC comparison, the PID compensator was designed for the FPOSLLC. In this article, the Ziegler–Nichols tuning method [21–23] is used to evaluate the PID control parameters for transfer function model FPOSLLC, which are obtained from the previous sections. Then, transfer function of PID control is expressed as (23) and its frequency response of open-loop model is illustrated in Figure 7.(23)GCs=0.23+400s+0.985s.When comparing the suggested posicast-based control to traditional PID control, several interesting results emerge. When compared to the PID-compensated system, the posicast-compensated magnitude response is dramatically attenuated at higher frequencies for the same gain margin. As a result, the posicast-compensated system suppresses high-frequency noise far more effectively than the PID method. From Figures6 and 7, new HPC removes frequency noise superior than the PID control.Figure 6
Frequency response analysis of HPC.Figure 7
Frequency result of PID control.


## 3.1. Principle of Posicast

The step result of lightly damped model is revealed in Figure3. It is categorized by λ and Td [2, 3]. Figure 4 indicates the structure of a classical half-cycle posicast. It is intended based on λ and Td. Precise information of the step result constraints produces control whose smallest zero frequency revokes the leading plant pair. It is known as half-cycle since the surrounded time delay is Td/2. Therefore, HPC arrangement is explained in Figure 5.Figure 3
Step result of a flippantly damped FPOSLLC.Figure 4
The classical half-cycle posicast.Figure 5
FPOSLLC with HPC.The posicast function is prearranged via the following equation [2, 21]:(15)Ps=λ1+λe−sTd/2−1.P(s) are λ and Td. It fundamentally reforms the set values into two portions; primarily, control minus the scale quantity from the set value (R), in order to the peak of a lightly damped result matches to the set final value of FPOSLLC result. The peak time of the step response is Td/2. Next, in this time delay, the complete value of the step reference is smeared to G(s), ensuring that Vo remains constant at set value. Alternative clarification is that the set value, which was previously removed from the input, now cancels any undesirable overshoots since it is delayed by Td/2.


## 3.2. Modelling of Hybrid Posicast Controller

The main components of HPC are as follows: P(s) is the scaling factor parameterized byλ and the time delay element parameterized by Td. There are two design steps for HPC. First, P(s) is developed for the averaged model of the FPOSLLC. Then, C(s) is framed to compensate joined model of (1 + P(s)) G(s). The classical frequency-domain approach is provided. A pure integrator type compensator is matched for the FPOSLLC to stabilize steady-state disturbances.(16)Cs=Ks.The gainK is selected to reduce the settling time as much as feasible, but not to the point where the overshoot is excessive. A new HPC model (17) is attained by joining the compensator C(s) and the P (s) [3, 21].(17)Cs1+Ps=Ks1+λ1+λe−sTd/2−1.


## 3.3. Design of a New HPC

Small-signal model transfer function of the FPOSLLC is(18)Gs=vo∧λ∧=12600e−6s+50150000e−12s2+100e−6s+12.5.Undamped natural frequency is(19)ωn=1LC,(20)Td=2πωn1−ζ2,(21)λ=e−πζ/1−ζ2.The values of the new HPC parameters are computed using equations (18)–(21). Then, Td = 0.00219 s and λ = 0.8. The K gain is designed to be as bulky as conceivable to reduce settling time of settling while avoiding unjustified overshoot, and it is fixed to be 7 in this work [2–4, 21].Now, the model of HPC is(22)Cs1+Ps=7s1+0.444e−0.001s−1.Figure8 shows the frequency analysis of HPC in an open-loop model, C(s) (1 + P(s)) G(s). The gain margin is approximately infinity, while the phase margin is around 89.8°.


## 3.4. PID Controller

For the output voltage regulation of FPOSLLC, standard controllers based on the PID control are frequently utilized. The PID controller approach may effectively control the low-order dynamics of power modulators. Traditional PID controller is problematic to surpass in this case because the integrator raises the converter type number, reducing the fixed state error. Controller has two zeros allowing for booming physiognomies to be dampened and the transient result to be enhanced. The PID controller is a simple structure for understanding in comparison with other control methodologies. For new HPC comparison, the PID compensator was designed for the FPOSLLC. In this article, the Ziegler–Nichols tuning method [21–23] is used to evaluate the PID control parameters for transfer function model FPOSLLC, which are obtained from the previous sections. Then, transfer function of PID control is expressed as (23) and its frequency response of open-loop model is illustrated in Figure 7.(23)GCs=0.23+400s+0.985s.When comparing the suggested posicast-based control to traditional PID control, several interesting results emerge. When compared to the PID-compensated system, the posicast-compensated magnitude response is dramatically attenuated at higher frequencies for the same gain margin. As a result, the posicast-compensated system suppresses high-frequency noise far more effectively than the PID method. From Figures6 and 7, new HPC removes frequency noise superior than the PID control.Figure 6
Frequency response analysis of HPC.Figure 7
Frequency result of PID control.


## 4. Simulation Results and Discussion

This part discusses the simulation results of FPOSLLC using HPC and PID controllers. The enactment of converter with controllers is verified at different working circumstances. Figure8 portrays the Simulink model of FPOSLLC with HPC.Figure 8
Simulink model of HPC for FPOSLLC.


### 4.1. Line Variations

Figures9 and 10 show the simulated characteristics in the startup for Vo and duty cycle of FPOSLLC with HPC for various Vin such as 09 V, 12 V, and 15 V, respectively. It is evident that Vo of the FPOSLLC with HPC has insignificant overshoots and quick settling times of 0.02 s, 0.015 s, and 0.011 s in transient region at different Vin.Figure 9
SimulatedVo response of FPOSLLC with HPC for various Vin.Figure 10
Simulated response of duty cycle of FPOSLLC with HPC for variousVin.


### 4.2. Load Variations

Figures11 and 12 indicate simulated results in startup for Vo and output current of FPOSLLC with designed controller for various R such as 40 Ω, 50 Ω, and 60 Ω, respectively. It is clearly found that Vo of the same converter has generated trifling overshoot and took time of settling 0.014 s, 0.012 s, and 0.011 s intended for R = 40 Ω, R = 50 Ω, and R = 60 Ω in startup with proficient HPC.Figure 11
SimulatedVo results of FPOSLLC with HPC for various R.Figure 12
Simulated responses of output currentIo of FPOSLLC with HPC for different R.


### 4.3. Various Controller Parameters

Figures13 and 14 show the simulated Vo results of FPOSLLC with designed controller for various values of Td and compensator gain K. From these figures, it is found that the output voltage of FPOSLLC with control has null overshoots and small steady-state error for different values of Td and K.Figure 13
Simulated response ofVo of FPOSLLC with HPC for dissimilar Td.Figure 14
Simulated results ofVo of FPOSLLC with HPC for various K.Results ofVo, duty cycle and quantity of noise of FPOSLLC with HPC are shown in Figure 15. It is observed that the settling time of converter with HPC is 0.03 s.Figure 15
Simulated results ofVo, duty cycle, and quantity of noise of FPOSLLC with controller for constant Vin and controller parameters.


### 4.4. Comparative Analysis of Different Controllers

Figure16 shows simulated results of FPOSLLC with HPC and PID controller. It could be observed that Vo of FPOSLLC with HPC has a null overshoot, rapid settling time, and excellent noise suppression over the PID controllers. In summary, the HPC performs better than PID.Figure 16
Results ofVo FPOSLLC with HPC and PID control for Vin = 12 V and R = 50 Ω.


### 4.5. Simulation Results of Steady-State Region

Table2 shows the numerically simulated Vo of FPOSLLC with HPC and PID controller for changing Vin from 3 V to 15 V. From this table, it is evident that the output voltage of FPOSLLC with designed HPC has small deviation in steady-state conditions at input voltage changes from 3 V to 15 V, whereas PID for same converter has more deviations at different Vin.Table 2
Output voltage variations with HPC forK = 7, Td = 0.00219 s, λ = 0.8, R = 50 Ω, and voref = 36 V.
Vin (V)HPCPID controllerVo (V)Deviation (V)Vo (V)Deviation (V)335.9820.01334.9121.088435.9900.01234.9801.002535.9920.00634.9911.009635.9930.00734.9921.008735.9950.00534.9951.005835.9940.00434.9941.006935.9970.00334.9961.0041035.9990.00135.9970.0031136036.2110.2111236036.2210.2211336.010.0136.320.311436.0150.01536.350.351536.0180.01836.380.38Figures17 and 18 show the simulated measured/reference output voltage of FPOSLLC with HPC. From these figures, it is clearly observed that the measured Vo follows the reference Vo without overshoot and rapid settling time. Time-domain specifications of FPOSLLC with controllers are recorded in Table 3. From this table, it is evident that the designed controller has proficient performance in comparison with traditional PID control at line and load variations.Figure 17
Simulated output voltage responses of FPOSLLC with HPC for referenceVo from 36 V to 46 V at time of 0.05 s.Figure 18
Simulated output voltage responses of FPOSLLC with HPC for reference output step change from 36 V to 26 V at time of 0.05 s.Table 3
Simulated numerical time-domain specification analysis of FPOSLLC using controllers.
Startup regionLine variationsLoad variationsMpTs(s)Vin = 12 V to 15 VVin = 15 V to 12 VR = 50 Ω to 60 ΩR = 50 Ω to 10 ΩMpTs(s)MpTs(s)MpTs(s)MpTs(s)HPCNil0.012 V0.012 V0.010.5 V0.010.5 V0.01PID4 V0.0056 V0.026 V0.041 V0.021 V0.02


## 4.1. Line Variations

Figures9 and 10 show the simulated characteristics in the startup for Vo and duty cycle of FPOSLLC with HPC for various Vin such as 09 V, 12 V, and 15 V, respectively. It is evident that Vo of the FPOSLLC with HPC has insignificant overshoots and quick settling times of 0.02 s, 0.015 s, and 0.011 s in transient region at different Vin.Figure 9
SimulatedVo response of FPOSLLC with HPC for various Vin.Figure 10
Simulated response of duty cycle of FPOSLLC with HPC for variousVin.


## 4.2. Load Variations

Figures11 and 12 indicate simulated results in startup for Vo and output current of FPOSLLC with designed controller for various R such as 40 Ω, 50 Ω, and 60 Ω, respectively. It is clearly found that Vo of the same converter has generated trifling overshoot and took time of settling 0.014 s, 0.012 s, and 0.011 s intended for R = 40 Ω, R = 50 Ω, and R = 60 Ω in startup with proficient HPC.Figure 11
SimulatedVo results of FPOSLLC with HPC for various R.Figure 12
Simulated responses of output currentIo of FPOSLLC with HPC for different R.


## 4.3. Various Controller Parameters

Figures13 and 14 show the simulated Vo results of FPOSLLC with designed controller for various values of Td and compensator gain K. From these figures, it is found that the output voltage of FPOSLLC with control has null overshoots and small steady-state error for different values of Td and K.Figure 13
Simulated response ofVo of FPOSLLC with HPC for dissimilar Td.Figure 14
Simulated results ofVo of FPOSLLC with HPC for various K.Results ofVo, duty cycle and quantity of noise of FPOSLLC with HPC are shown in Figure 15. It is observed that the settling time of converter with HPC is 0.03 s.Figure 15
Simulated results ofVo, duty cycle, and quantity of noise of FPOSLLC with controller for constant Vin and controller parameters.


## 4.4. Comparative Analysis of Different Controllers

Figure16 shows simulated results of FPOSLLC with HPC and PID controller. It could be observed that Vo of FPOSLLC with HPC has a null overshoot, rapid settling time, and excellent noise suppression over the PID controllers. In summary, the HPC performs better than PID.Figure 16
Results ofVo FPOSLLC with HPC and PID control for Vin = 12 V and R = 50 Ω.


## 4.5. Simulation Results of Steady-State Region

Table2 shows the numerically simulated Vo of FPOSLLC with HPC and PID controller for changing Vin from 3 V to 15 V. From this table, it is evident that the output voltage of FPOSLLC with designed HPC has small deviation in steady-state conditions at input voltage changes from 3 V to 15 V, whereas PID for same converter has more deviations at different Vin.Table 2
Output voltage variations with HPC forK = 7, Td = 0.00219 s, λ = 0.8, R = 50 Ω, and voref = 36 V.
Vin (V)HPCPID controllerVo (V)Deviation (V)Vo (V)Deviation (V)335.9820.01334.9121.088435.9900.01234.9801.002535.9920.00634.9911.009635.9930.00734.9921.008735.9950.00534.9951.005835.9940.00434.9941.006935.9970.00334.9961.0041035.9990.00135.9970.0031136036.2110.2111236036.2210.2211336.010.0136.320.311436.0150.01536.350.351536.0180.01836.380.38Figures17 and 18 show the simulated measured/reference output voltage of FPOSLLC with HPC. From these figures, it is clearly observed that the measured Vo follows the reference Vo without overshoot and rapid settling time. Time-domain specifications of FPOSLLC with controllers are recorded in Table 3. From this table, it is evident that the designed controller has proficient performance in comparison with traditional PID control at line and load variations.Figure 17
Simulated output voltage responses of FPOSLLC with HPC for referenceVo from 36 V to 46 V at time of 0.05 s.Figure 18
Simulated output voltage responses of FPOSLLC with HPC for reference output step change from 36 V to 26 V at time of 0.05 s.Table 3
Simulated numerical time-domain specification analysis of FPOSLLC using controllers.
Startup regionLine variationsLoad variationsMpTs(s)Vin = 12 V to 15 VVin = 15 V to 12 VR = 50 Ω to 60 ΩR = 50 Ω to 10 ΩMpTs(s)MpTs(s)MpTs(s)MpTs(s)HPCNil0.012 V0.012 V0.010.5 V0.010.5 V0.01PID4 V0.0056 V0.026 V0.041 V0.021 V0.02


## 5. Conclusions

A new HPC for output voltage regulation of FPOSLLC in CCM has been built with help of the Simulink software model. For the analytical and ideal techniques of FPOSLLC, the elements of posicast are explicitly computed. Better damping abilities, proficient output voltage regulation in line/load variations, minimized overshoots, quick settling time, reduced high frequency noise, easy digital implementation, and minimizing sensitivity of traditional approach are the main benefits of the newly designed HPC over PID control. Because of the integral compensator and single gain of the new HPC, the FPOSLLC’s steady-state response has improved. In contrast to PID control, the new HPC simply wants to modify the gain K, and the compensated plant has improved the gain/phase margins, while the short open-loop bandwidth verifies the conquest of higher frequency noise. Time-domain analysis of HPC for FPOSLLC has proficient performance over the PID control. Finally, for FPOSLLC in CCM, the newly developed HPC has excellent output voltage regulation at different input voltage and load resistance variations. It can be used to power LED drivers, medical instruments, solar systems, and mobile phones. In the future, the hardware model of FPOSLLC with HPC, as well as the design of super-twisting sliding mode control, will be implemented.



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*Source: 1760861-2022-03-30.xml*