# Stacked Input-Output High Step-Up Buck-Boost DC-DC Converter with Coupled Inductor and Voltage Multiplier

Authors: Tiago Miguel Klein Faistel; Ademir Toebe; António Manuel Santos Spencer Andrade; Ronaldo Antonio Guisso; Mauricio Mendes da Silva
Journal: International Transactions on Electrical Energy Systems
 (2022)

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## Abstract

This paper presents three high voltage gain DC-DC converters based on stacked input and output connection of nonisolated buck-boost converters with coupled inductor and voltage multiplier cells. Besides that, an empirical approach for the coupled inductor winding is proposed to show how to reduce the leakage inductance. In this way, the proposed converter achieves high voltage gain, low voltage, and current stress across the components without using an auxiliary clamp circuit, and they present a low component count. Besides that, this paper presents the evaluation of MPPT, modeling, and control of the converters. To validate the theoretical evaluations, three prototypes were built and evaluated experimentally, considering input power of 200 W, input voltage of 37.4 V, output voltage of 400 V, and switching frequency of 50 kHz. Finally, it should be noted that the maximum efficiency achieved is 97.53% at nominal input power.


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## Body

## 1. Introduction

Renewable energy systems, such as photovoltaic (PV), have become attractive all over the world. The performance of solar panels depends on different factors such as solar irradiance, temperature, and shadow. So to extract the maximum power from the PV, a maximum power point tracking (MPPT) algorithm is necessary. Besides that, the voltage level provided by a single PV panel is usually lower than 50 V. So, to provide energy to a DC microgrid or AC inverter connected to the grid, a high step-up stage is needed [1–10]. This type of configuration allows improving energy efficiency in partially shaded conditions since only one solar panel is used [11].High voltage gain DC-DC converters have been gaining popularity in recent years. The boost converter is the standard step-up converter found in the literature and is frequently preferred in solar photovoltaic systems and fuel-based energy systems [12]. Ideally, this converter can achieve high voltage gains. However, it presents high voltage stress in the semiconductors; that is, the voltage in the switch and the diode is equal to the output voltage. This means that components with intrinsic resistance tend to be used when a high voltage gain is needed. Furthermore, current efforts also increase for these cases. This set of factors makes the conduction losses in the converter components high. Consequently, the boost converter does not perform well for high voltage gain applications [13–19].Thus, in the literature, there are many step-up techniques applied in the boost converter, with the objective of increasing the static gain and decreasing the stresses across the components. One of the simplest techniques is the association of the coupled inductor to the boost converter. This approach allows increasing the voltage gain of the converter as the turns ratioN of the coupled inductor increases. However, for high N, the leakage inductance Lk of the coupled inductor tends to increase. So the stored energy of Lk increases, and consequently, this energy is dissipated on the semiconductor at turn ON or turn OFF. In this way, one approach is to use some technique to decrease the Lk to avoid voltage spikes on the semiconductors. Otherwise, auxiliary clamping circuits must be used, which increase the volume and cost of the converter [20, 21]. Besides, a natural clamp circuit can be used in the converter, which helps to improve the voltage gain of the converter and clamp the switch as shown in [22].Other voltage-raising techniques are associated with the boost converter found in the literature, as follows: switched inductor [23–25], switched capacitor [26–28], voltage multiplier [29–31], impedance source [32–35], converter cascade, etc. These techniques allow increasing the gain of the converter, reducing stress on the components, and allowing a good performance to be achieved. However, a large number of components are required to achieve these goals. By using a large number of components, these converters can have a high cost, high volume, and low power density.Another approach is stacking the input and output of the converter. The most common solution is the buck-boost converter [36]. This approach allows for different configurations, as can be seen in [37–39]. These converters are able to achieve a high voltage gain from cell stacking. But this requires a lot of cells, and consequently, a high number of components are needed, which increases the volume and cost.In order to find a simple solution with the fewest possible components, this paper aims to propose a stacked input and output connection of nonisolated buck-boost converters with coupled inductor and voltage multiplier cells. Along with this, an empirical approach for the coupled inductor winding is proposed. This technique allows low leakage inductance values to be achieved. Thus, the proposed converter does not need any kind of auxiliary circuit to clamp the voltage on the semiconductors. To demonstrate these characteristics, this paper is organized as follows. Initially, the operating steps, voltage gain, voltage and current stress, evaluation of the leakage inductance effect, and coupled inductor design methodology are discussed in Section2. In Section 3, theoretical evaluations are validated through experimental results.


## 2. Proposed Converters

The usually and simple solution of stacked input and output connection of nonisolated converters is the buck-boost converter, shown in Figure1(a). In continuous conduction mode (CCM), this converter presents the same voltage gain of standard boost converter given by (1). To achieve high voltage gain, high duty cycle D is necessary. However, due to the parasitic resistances of the components, the nonideal buck-boost converter (Figure 1(b)) cannot perform well when high D is needed. To show these features, (2) shows the voltage gain of the nonideal stacked input and output buck-boost converter. Figure 1(c) shows a comparison of the ideal and nonideal buck-boost converter. As mentioned before, it is clear that the converter cannot achieve high voltage gain.(1)M=VoVi=11−D,(2)M=VoVi=1+D−vf1−D+rL1−2D+2D2+rSD2/1−DR+rD+rC/R,where rL is the wire resistances of the inductor, rS is the RDSon resistances of the switch, rD is the resistances of the diode, vf is the forward voltage of the diode, and rC is the equivalent series resistance (ESR) of the capacitor.Figure 1
Stacked boost-buck converter. (a) Ideal circuit. (b) Nonideal circuit. (c) Voltage gain versus duty cycle (r=rL=rS=rD=rc=150mΩ, R=800Ω,vf=0.5V).
(a)(b)(c)Thus, to increase the voltage gain of the converter without increasing the number of components, a simple solution is shown in Figure2(a), where a coupled inductor is integrated into the stacked input and output buck-boost converter. To simplify, the converter presented in Figure 2(a) is called SBCI. To increase the voltage gain of SBCI, another well-known technique can be associated; i.e., the voltage multiplier cell can be integrated into the SBCI. In this way, two converters one and two voltage multipliers can be generated as shown in 2(b) (SBCIVM1) and (c) (SBCIVM2), respectively. To demonstrate the improvements of these converters, in the following section, the main theoretical evaluations are made.Figure 2
Proposed converters. (a) SBCI. (b) SBCIVM1. (c) SBCIVM2.
(a)(b)(c)To demonstrate the explanation of the converters’ operation, the following assumptions are made: all power devices are ideal; the leakage inductance of the coupled inductor is calledLk; the turns ratio is given by N=N2/N1; the components that are in gray are OFF.


### 2.1. Operation Stage of SBCI

The proposed converter presents two stages of operation in continuous conduction mode (CCM) and three stages of operation in discontinuous conduction mode (DCM). In CCM, the stages of operation and key waveforms are shown in Figures3(a)-3(b) and 4(a), respectively. For DCM, the circuit for each stage is shown in Figures 3(a)–3(c), and its key waveforms are given in Figure 4(b).Figure 3
Operation stage of SBCI. (a) Stage 1. (b) Stage 2. (c) Stage 3.
(a)(b)(c)Figure 4
Key waveforms of SBCI. (a) CCM. (b) DCM.
(a)(b)Stage 1 (to−t1, Figure 3(a)). This stage begins when the switch S is turned ON. The inductors Lm and Lk are magnetized, and their current is equal, as given by (3). In relation to the semiconductors, their currents are given by (4) and (5).(3)iLmt=iLkt=ViLm+Lkt+ILmto,(4)iSt=iLmt,(5)iD1t=0.Stage 2 t1−t2(t1−t2, Figure 3(b)). This stage begins when the switch S is turned OFF. The inductors Lm and Lk are demagnetized, and their currents are given by (6) and (7), respectively. The currents of the semiconductors are given by (8) and (9).(6)iLmt=−Lm+NLmVC1Lm+NLm+Lkt+ILmt1,(7)iLkt=−LkVC1Lm+NLm+Lkt+ILkt1,(8)iSt=0,(9)iD1t=iLkt.This stage ends when the switch is turned ON and a new switching period begins when the switch is turned ON for CCM. In DCM, this stage ends at timet2.Stage 3 t2−t3(t2−t3, Figure 3(c)). This stage is only for DCM and begins when the current of the inductors (Lm and Lk) is zero. All semiconductors are blocked at this stage. The load R is supplied by the output capacitor Ci and the input source Vi.


### 2.2. Operation Stage of SBCIVM1

The proposed converter presents two stages of operation in continuous conduction mode (CCM) and three stages of operation in discontinuous conduction mode (DCM). In CCM, the stages of operation and key waveforms are shown in Figures5(a)-5(b) and 6(a), respectively. For DCM, the circuit for each stage is shown in Figures 5(a)–5(c), and its key waveforms are given in Figure 6(b).Figure 5
Operation stage of SBCIVM1. (a) Stage 1. (b) Stage 2. (c) Stage 3.
(a)(b)(c)Figure 6
Key waveforms of SBCIVM1. (a) CCM. (b) DCM.
(a)(b)Stage 1 to−t1(to−t1, Figure 5(a)). At the beginning of this stage, the switch S is turned ON. The inductors Lm and Lk are magnetized, and their currents are given by (10) and (11), respectively. The current of the switch S is given by (12), and the diodes D1 by (13) and D2 by (14).(10)iLmt=VC2NLmt+ILmto,(11)iLkt=Vi+VC2/NLkt+ILkto,(12)iSt=iLkt,(13)iD1t=0,(14)iD2t=iLkt−iLmtN.Stage 2 t1−t2(t1−t2, Figure 5(b)). This stage begins when the switch S is turned OFF. The inductors Lm and Lk are demagnetized, and their currents are given by (15) and (16), respectively. In relation to the semiconductors, their currents are given by (17), (18), and (19).(15)iLmt=−Lm+NLmVC1−VC2Lm+NLm+Lkt+ILmt1,(16)iLkt=−LkVC1−VC2Lm+NLm+Lkt+ILkt1,(17)iSt=0,(18)iD1t=iLkt,(19)iD2t=0.This stage ends when the switch is turned ON and a new switching period begins when the switch is turned ON for CCM. In DCM, this stage ends at timet2.Stage 3 (t2−t3, Figure 5(c)). This stage is only for DCM and begins when the current of the inductors (Lm and Lk) is zero. All semiconductors are blocked at this stage. The load R is supplied by the output capacitor Ci and the input source Vi.


### 2.3. Operation Stage of SBCIVM2

The proposed converter presents two stages of operation in continuous conduction mode (CCM) and three stages of operation in discontinuous conduction mode (DCM). In CCM, the stages of operation and key waveforms are shown in Figures7(a)-7(b) and 8(a), respectively. For DCM, the circuit for each stage is shown in Figures 7(a)–7(c), and its key waveforms are given in Figure 8(b).Figure 7
Operation stage of SBCIVM2. (a) Stage 1. (b) Stage 2. (c) Stage 3.
(a)(b)(c)Figure 8
Key waveforms of SBCIVM2. (a) CCM. (b) DCM.
(a)(b)Stage 1 (to−t1, Figure 7(a)). At the beginning of this stage, the switch S is turned ON. The inductors Lm and Lk are magnetized, and their currents are given by (20) and (21), respectively. The current of the switch S is given by (22), and the diodes D1 by (23) and D2=D3 by (24).(20)iLmt=VC2NLmt+ILmto,(21)iLkt=Vi+VC2/NLkt+ILkto,(22)iSt=iLkt,(23)iD1t=0,(24)iD2t=iD3t=iLkt−iLmt2N.Stage 2 (t1−t2, Figure 7(b)). This stage begins when the switch S is turned OFF. The inductors Lm and Lk are demagnetized, and their currents are given by (25)and(26), respectively. In relation to the semiconductors, their currents are given by (27), (28), and (29).(25)iLmt=−Lm+NLmVC1−VC2Lm+NLm+Lkt+ILmt1,(26)iLkt=−LkVC1−VC2Lm+NLm+Lkt+ILkt1,(27)iSt=0,(28)iD1t=iLkt,(29)iD2t=iD3t=0.This stage ends when the switch is turned ON and a new switching period begins when the switch is turned ON for CCM. In DCM, this stage ends at timet2.Stage 3 (t2−t3, Figure 7(c)). This stage is only for DCM and begins when the current of the inductors (Lm and Lk) is zero. All semiconductors are blocked at this stage. The load R is supplied by the output capacitor Ci and the input source Vi.


### 2.4. Derivation of Voltage Gain

To find the voltage gain of the converters, they are considered ideal. So, the volts–second balance principle is applied to the inductors, as shown as follows:(30)∫tot2vL1dt=0.For SBCI, applying the volt-sec concept across the inductorLm, the voltage across the capacitor is found as(31)VC1=ND+D1−DVi.Knowing the input-output is in a stacked connection, the voltage gain of SBCI is given by(32)MSBCI=VoVi=ND+11−D.Following the same approach, the voltage gain of SBCIVM1 and SBCIVM2 is given by(33)MSBCIVM1=VoVi=N+11−D,(34)MSBCIVM2=VoVi=2N+1−ND1−D.Figure9 shows the behavior of voltage gain versus duty cycle. The SBCIVM2 achieves higher voltage gain for the entire duty cycle range compared to the other converters. So, this converter is the most attractive in relation to the voltage gain.Figure 9
M versus D, for different N.


### 2.5. Semiconductors’ Voltage Stress

From the operation steps and knowing the voltage gain of the converters, the voltage stress can be found. All converters achieve the same voltage stress across the switch, as given by(35)VS=Vi1−D.In relation to the diodeD1, (36), (37), and (38) show the voltage stress across this diode for SBCI, SBCIVM1, and SBCIVM2, respectively.(36)VD1=2NVi1−D,(37)VD1=2N+1Vi1−D,(38)VD1=2N+1Vi1−D.For the diodeD2 and D3 of SBCIVM1 and SBCIVM, their voltage stress is equal:(39)VD2=VD3=NVi1−D.


### 2.6. Semiconductors' Current Stress

From the operation steps and following the methodology presented in [40], the RMS and average currents (avg) are found.All converters present the same current stress across the switchS given by(40)ISrms=I1D+NDN+1.The average current of diodeD1 for SBCI, SBCIVM1, and SBCVM2 is given by (41), (42), and (43), respectively.(41)ID1avg=I11−DND+1,(42)ID1avg=I11−DN+1,(43)ID1avg=I11−D2N+1−ND.Finally, the current stress of the diodesD2 and D3 of SBCIVM1 and SBCVM2 is given by (44) and (45), respectively.(44)ID2avg=I11−DN+1,(45)ID2avg=ID2med=I11−D2N+1.


### 2.7. Overvoltage Analysis Caused byLk

As can be seen in Figures4, 6, and 8, at the moment when the switch S is turned OFF, the current of Lk has a high current variation; consequently, an overvoltage may occur in this component, which is reflected in the switch. This voltage can be simplified as(46)ΔVLk=LkΔiLkΔt.ConsideringΔiLk as a constant, it has been evaluated (46), as can be seen in Figure 10(a). As Lk increases, the voltage ΔvLk increases. Consequently, the overvoltage at the switch rises, which can compromise the converter’s performance.Figure 10
Voltage of (a)ΔVLk. (b) Switch S.
(a)(b)This fact is evaluated through simulations as can be seen in Figure10(b). So, the overvoltage effect caused by the Lk makes it necessary to use MOSFETs with higher VDS, VDS; Consequently, higher RDSon has to be used, which increases losses driving. On the other hand, an auxiliary clamped circuit can be used, which requires more components; thus, the complexity, volume, and cost can increase. Thus, a simple solution is to work on the coupled inductor winding with the objective of decreasing Lk, consequently, decreasing the overvoltage on the switch S.


### 2.8. Design of the Coupled Inductor

In the traditional method for winding the coupled inductor, initially, the primary wireN1 is wound on the toroidal core and then the secondary wire N2. For this technique, it is estimated that Lk is approximately 5% of the Lm value. An empirical approach proposed in this paper to coil the coupled inductor is shown in Figure 11. For the fabrication of the coupled inductor windings, the same length of wires connected in parallel is used. These conductors are intertwined, forming a single winding to be wound on the toroidal core. Through the proposed technique, six conductors (wires) are selected to compose the primary side (yellow), and the same amount to compose the secondary side (purple). The windings that form them are separated into three pairs, which are connected in series (red and green connection), forming a single secondary winding three times the length of the primary winding. This allows for better magnetic coupling, thus reducing Lk.Figure 11
Coupled inductor winding proposal.Knowing the approach to wind the coupled inductor, the next step is to calculate the magnetizing inductanceLm, given by(47)Lm=ViDfsΔiLm.From this, the core of the coupled inductor must be selected. For this, the core area product (AeAw) required by the application is calculated, and this calculation is related to the AeAw value of the available cores [41,42]. The core area product is given by(48)AeAw=IefIpkLmkwBmaxJmax,where Ief is the RMS current, I−pk is the current peak, Bmax is the peak value of the magnetic field density (0.3 T), Jmax is the current density, and kw is the window utilization factor.The next step is to calculate the number of turns, which is given by(49)N1=IpkLmAeBmax.The air gap is calculated by(50)lairgap=AeμoN12Lm,where μo=4π10−7.The diameter of the winding wire is given by(51)Δ=7.5fs.From this, the coupled inductor can be designed. All main parameters are given in Table1.Table 1
Converter specifications and parameters.
SymbolNameValuePiInput power200 WViInput voltage37.4 VVoOutput voltage400 VMVoltage gain10.69fsSwitching frequency50 kHzNTurns ratio22 : 66 (NEE-65/33/52 core)DDuty cycle for SBCI0.7079DDuty cycle for SBCIVM10.6260DDuty cycle for SBCIVM20.4802SSwitchIPB044N15N5DallDiodosSTTH20R04FP and STTH20L03CTLmMagnetized inductor160μHLkLeakage inductor0.42μHCallCapacitors27μF


### 2.9. Modeling and Control

The dynamic analysis addressed in this section follows the methodology presented in [40,43], and the equivalent circuit is shown in Figure 12, considering the converter operating in CCM. This same approach is applied to the three converters.Figure 12
Validation of the input voltage small signal modelVCins. (a) Stage 1. (b) Stage 2.
(a)(b)For the first stage, switchS1 is ON (Figure 12(a)), and the following differential equations describe the behavior of the converter:(52)LmdiLmtdt=vC2tN,(53)CindvCintdt=−1RvC1t+iint−iLmt−vCintR+NvC2t−NvCintRc2,(54)C1dvC1tdt=−1RvC1t−vCintR,(55)C2dvC2tdt=−1Rc2vC2t+NvCintRc2,where N is the turns ratio of the coupled inductor, R is the load resistance, and Rc2 is the ESR of the capacitor C2.For the second stage, switchS1 is OFF (Figure 12(b)); the following differential equations describe the behavior of the converter:(56)LmdiLmtdt=−1N+1vC1t+vC2tN+1,(57)CindvCintdt=−1RvC1t+iint−vCintR,(58)C1dvC1tdt=−1RvC1t+iLmtN+1−vCintR,(59)C2dvC2tdt=−iLmtN+1.Applying the Laplace transform results in(60)Y˜s=CsI−A−1λ+Υd˜s,where the matrices λ and Υ are defined by(61)λ=A1−A2X+B1−B2U,(62)Υ=C1−C2X+E1−E2U.By solving these equations, the transfer function (FT) of the input capacitor voltagevCin by D is obtained. Applying the prototype values presented in Table 1, the FT is obtained, and the final result is provided by(63)Gvs=v˜Cinsd˜s=N4s3+N3s2+N2s+N1s4+D4s3+D3s2+D2s+D1,whereN4=−3,874⋅103,N3=−6,222⋅1008,N2=−2,104⋅1012,N1=−6,444⋅1014,D4=1,040⋅106,D3=1,451⋅108,D2=6,957⋅1010,andD1=3,220⋅1012.For model validation, as shown in Figure13, at time instants of 0.45 and 0.6 seconds, two disturbances being the positive (+0.5 A) and the negative of (−0.5 A), respectively, were applied to the input current iins of the photovoltaic panel (PV). Two duty cycle steps ds were also applied at the time instants of 0.75 seconds +1% and 0.85 seconds −1%. All disturbances aim to verify the effect caused on the input capacitor voltage vCins of the converter. Table 1 shows the parameters of the components used in the prototype. As shown in Figure 13, the model of vCins faithfully follows the behavior of the circuit.Figure 13
Validation of the input voltage small signal modelVCins.In this paper, the converter input is considered a PV panel. Thus, to ensure the tracking of the maximum power point (MPPT), the control strategy presented in Figure14(a) was used, which is composed of the measurement of the current ipv and of the voltage vpv of the panel, the MPPT algorithm, thus generating the input voltage reference v˜i,refs, the gain of the sensors Hvs, the controller Cvis, and the plant Gvs. The MPPT algorithm implemented in the PV panel is the Perturb and Observe (P&O), already consolidated in the literature. The algorithm provides the input voltage reference v˜i,refs which is compared to the input voltage v˜is measured in the converter, generating an error that passes through the PI controller C˜vis which gives the duty cycle d˜s, which adjusts the tension v˜is through the FT from vCins by dsGvs. The PI controller was designed using Matlab’s Sisotool tool, and the goat diagram is given through(64)Cvi,dz=−3.23201846×10−4z+3.15398154×10−4z−1.Figure 14
Input voltage controller design.
(a)(b)The open-loop and compensated open-loopBode diagram is shown in Figure 14(b). The open-loop system has a phase margin (MF) of 152° and a cutoff frequency of 3.26 kHz. With the use of the PI controller, the compensated system has an MF of 69° with a cutoff frequency of 11 Hz. This controller design achieved the expected result, obtaining satisfactory experimental results.


## 2.1. Operation Stage of SBCI

The proposed converter presents two stages of operation in continuous conduction mode (CCM) and three stages of operation in discontinuous conduction mode (DCM). In CCM, the stages of operation and key waveforms are shown in Figures3(a)-3(b) and 4(a), respectively. For DCM, the circuit for each stage is shown in Figures 3(a)–3(c), and its key waveforms are given in Figure 4(b).Figure 3
Operation stage of SBCI. (a) Stage 1. (b) Stage 2. (c) Stage 3.
(a)(b)(c)Figure 4
Key waveforms of SBCI. (a) CCM. (b) DCM.
(a)(b)Stage 1 (to−t1, Figure 3(a)). This stage begins when the switch S is turned ON. The inductors Lm and Lk are magnetized, and their current is equal, as given by (3). In relation to the semiconductors, their currents are given by (4) and (5).(3)iLmt=iLkt=ViLm+Lkt+ILmto,(4)iSt=iLmt,(5)iD1t=0.Stage 2 t1−t2(t1−t2, Figure 3(b)). This stage begins when the switch S is turned OFF. The inductors Lm and Lk are demagnetized, and their currents are given by (6) and (7), respectively. The currents of the semiconductors are given by (8) and (9).(6)iLmt=−Lm+NLmVC1Lm+NLm+Lkt+ILmt1,(7)iLkt=−LkVC1Lm+NLm+Lkt+ILkt1,(8)iSt=0,(9)iD1t=iLkt.This stage ends when the switch is turned ON and a new switching period begins when the switch is turned ON for CCM. In DCM, this stage ends at timet2.Stage 3 t2−t3(t2−t3, Figure 3(c)). This stage is only for DCM and begins when the current of the inductors (Lm and Lk) is zero. All semiconductors are blocked at this stage. The load R is supplied by the output capacitor Ci and the input source Vi.


## 2.2. Operation Stage of SBCIVM1

The proposed converter presents two stages of operation in continuous conduction mode (CCM) and three stages of operation in discontinuous conduction mode (DCM). In CCM, the stages of operation and key waveforms are shown in Figures5(a)-5(b) and 6(a), respectively. For DCM, the circuit for each stage is shown in Figures 5(a)–5(c), and its key waveforms are given in Figure 6(b).Figure 5
Operation stage of SBCIVM1. (a) Stage 1. (b) Stage 2. (c) Stage 3.
(a)(b)(c)Figure 6
Key waveforms of SBCIVM1. (a) CCM. (b) DCM.
(a)(b)Stage 1 to−t1(to−t1, Figure 5(a)). At the beginning of this stage, the switch S is turned ON. The inductors Lm and Lk are magnetized, and their currents are given by (10) and (11), respectively. The current of the switch S is given by (12), and the diodes D1 by (13) and D2 by (14).(10)iLmt=VC2NLmt+ILmto,(11)iLkt=Vi+VC2/NLkt+ILkto,(12)iSt=iLkt,(13)iD1t=0,(14)iD2t=iLkt−iLmtN.Stage 2 t1−t2(t1−t2, Figure 5(b)). This stage begins when the switch S is turned OFF. The inductors Lm and Lk are demagnetized, and their currents are given by (15) and (16), respectively. In relation to the semiconductors, their currents are given by (17), (18), and (19).(15)iLmt=−Lm+NLmVC1−VC2Lm+NLm+Lkt+ILmt1,(16)iLkt=−LkVC1−VC2Lm+NLm+Lkt+ILkt1,(17)iSt=0,(18)iD1t=iLkt,(19)iD2t=0.This stage ends when the switch is turned ON and a new switching period begins when the switch is turned ON for CCM. In DCM, this stage ends at timet2.Stage 3 (t2−t3, Figure 5(c)). This stage is only for DCM and begins when the current of the inductors (Lm and Lk) is zero. All semiconductors are blocked at this stage. The load R is supplied by the output capacitor Ci and the input source Vi.


## 2.3. Operation Stage of SBCIVM2

The proposed converter presents two stages of operation in continuous conduction mode (CCM) and three stages of operation in discontinuous conduction mode (DCM). In CCM, the stages of operation and key waveforms are shown in Figures7(a)-7(b) and 8(a), respectively. For DCM, the circuit for each stage is shown in Figures 7(a)–7(c), and its key waveforms are given in Figure 8(b).Figure 7
Operation stage of SBCIVM2. (a) Stage 1. (b) Stage 2. (c) Stage 3.
(a)(b)(c)Figure 8
Key waveforms of SBCIVM2. (a) CCM. (b) DCM.
(a)(b)Stage 1 (to−t1, Figure 7(a)). At the beginning of this stage, the switch S is turned ON. The inductors Lm and Lk are magnetized, and their currents are given by (20) and (21), respectively. The current of the switch S is given by (22), and the diodes D1 by (23) and D2=D3 by (24).(20)iLmt=VC2NLmt+ILmto,(21)iLkt=Vi+VC2/NLkt+ILkto,(22)iSt=iLkt,(23)iD1t=0,(24)iD2t=iD3t=iLkt−iLmt2N.Stage 2 (t1−t2, Figure 7(b)). This stage begins when the switch S is turned OFF. The inductors Lm and Lk are demagnetized, and their currents are given by (25)and(26), respectively. In relation to the semiconductors, their currents are given by (27), (28), and (29).(25)iLmt=−Lm+NLmVC1−VC2Lm+NLm+Lkt+ILmt1,(26)iLkt=−LkVC1−VC2Lm+NLm+Lkt+ILkt1,(27)iSt=0,(28)iD1t=iLkt,(29)iD2t=iD3t=0.This stage ends when the switch is turned ON and a new switching period begins when the switch is turned ON for CCM. In DCM, this stage ends at timet2.Stage 3 (t2−t3, Figure 7(c)). This stage is only for DCM and begins when the current of the inductors (Lm and Lk) is zero. All semiconductors are blocked at this stage. The load R is supplied by the output capacitor Ci and the input source Vi.


## 2.4. Derivation of Voltage Gain

To find the voltage gain of the converters, they are considered ideal. So, the volts–second balance principle is applied to the inductors, as shown as follows:(30)∫tot2vL1dt=0.For SBCI, applying the volt-sec concept across the inductorLm, the voltage across the capacitor is found as(31)VC1=ND+D1−DVi.Knowing the input-output is in a stacked connection, the voltage gain of SBCI is given by(32)MSBCI=VoVi=ND+11−D.Following the same approach, the voltage gain of SBCIVM1 and SBCIVM2 is given by(33)MSBCIVM1=VoVi=N+11−D,(34)MSBCIVM2=VoVi=2N+1−ND1−D.Figure9 shows the behavior of voltage gain versus duty cycle. The SBCIVM2 achieves higher voltage gain for the entire duty cycle range compared to the other converters. So, this converter is the most attractive in relation to the voltage gain.Figure 9
M versus D, for different N.


## 2.5. Semiconductors’ Voltage Stress

From the operation steps and knowing the voltage gain of the converters, the voltage stress can be found. All converters achieve the same voltage stress across the switch, as given by(35)VS=Vi1−D.In relation to the diodeD1, (36), (37), and (38) show the voltage stress across this diode for SBCI, SBCIVM1, and SBCIVM2, respectively.(36)VD1=2NVi1−D,(37)VD1=2N+1Vi1−D,(38)VD1=2N+1Vi1−D.For the diodeD2 and D3 of SBCIVM1 and SBCIVM, their voltage stress is equal:(39)VD2=VD3=NVi1−D.


## 2.6. Semiconductors' Current Stress

From the operation steps and following the methodology presented in [40], the RMS and average currents (avg) are found.All converters present the same current stress across the switchS given by(40)ISrms=I1D+NDN+1.The average current of diodeD1 for SBCI, SBCIVM1, and SBCVM2 is given by (41), (42), and (43), respectively.(41)ID1avg=I11−DND+1,(42)ID1avg=I11−DN+1,(43)ID1avg=I11−D2N+1−ND.Finally, the current stress of the diodesD2 and D3 of SBCIVM1 and SBCVM2 is given by (44) and (45), respectively.(44)ID2avg=I11−DN+1,(45)ID2avg=ID2med=I11−D2N+1.


## 2.7. Overvoltage Analysis Caused byLk

As can be seen in Figures4, 6, and 8, at the moment when the switch S is turned OFF, the current of Lk has a high current variation; consequently, an overvoltage may occur in this component, which is reflected in the switch. This voltage can be simplified as(46)ΔVLk=LkΔiLkΔt.ConsideringΔiLk as a constant, it has been evaluated (46), as can be seen in Figure 10(a). As Lk increases, the voltage ΔvLk increases. Consequently, the overvoltage at the switch rises, which can compromise the converter’s performance.Figure 10
Voltage of (a)ΔVLk. (b) Switch S.
(a)(b)This fact is evaluated through simulations as can be seen in Figure10(b). So, the overvoltage effect caused by the Lk makes it necessary to use MOSFETs with higher VDS, VDS; Consequently, higher RDSon has to be used, which increases losses driving. On the other hand, an auxiliary clamped circuit can be used, which requires more components; thus, the complexity, volume, and cost can increase. Thus, a simple solution is to work on the coupled inductor winding with the objective of decreasing Lk, consequently, decreasing the overvoltage on the switch S.


## 2.8. Design of the Coupled Inductor

In the traditional method for winding the coupled inductor, initially, the primary wireN1 is wound on the toroidal core and then the secondary wire N2. For this technique, it is estimated that Lk is approximately 5% of the Lm value. An empirical approach proposed in this paper to coil the coupled inductor is shown in Figure 11. For the fabrication of the coupled inductor windings, the same length of wires connected in parallel is used. These conductors are intertwined, forming a single winding to be wound on the toroidal core. Through the proposed technique, six conductors (wires) are selected to compose the primary side (yellow), and the same amount to compose the secondary side (purple). The windings that form them are separated into three pairs, which are connected in series (red and green connection), forming a single secondary winding three times the length of the primary winding. This allows for better magnetic coupling, thus reducing Lk.Figure 11
Coupled inductor winding proposal.Knowing the approach to wind the coupled inductor, the next step is to calculate the magnetizing inductanceLm, given by(47)Lm=ViDfsΔiLm.From this, the core of the coupled inductor must be selected. For this, the core area product (AeAw) required by the application is calculated, and this calculation is related to the AeAw value of the available cores [41,42]. The core area product is given by(48)AeAw=IefIpkLmkwBmaxJmax,where Ief is the RMS current, I−pk is the current peak, Bmax is the peak value of the magnetic field density (0.3 T), Jmax is the current density, and kw is the window utilization factor.The next step is to calculate the number of turns, which is given by(49)N1=IpkLmAeBmax.The air gap is calculated by(50)lairgap=AeμoN12Lm,where μo=4π10−7.The diameter of the winding wire is given by(51)Δ=7.5fs.From this, the coupled inductor can be designed. All main parameters are given in Table1.Table 1
Converter specifications and parameters.
SymbolNameValuePiInput power200 WViInput voltage37.4 VVoOutput voltage400 VMVoltage gain10.69fsSwitching frequency50 kHzNTurns ratio22 : 66 (NEE-65/33/52 core)DDuty cycle for SBCI0.7079DDuty cycle for SBCIVM10.6260DDuty cycle for SBCIVM20.4802SSwitchIPB044N15N5DallDiodosSTTH20R04FP and STTH20L03CTLmMagnetized inductor160μHLkLeakage inductor0.42μHCallCapacitors27μF


## 2.9. Modeling and Control

The dynamic analysis addressed in this section follows the methodology presented in [40,43], and the equivalent circuit is shown in Figure 12, considering the converter operating in CCM. This same approach is applied to the three converters.Figure 12
Validation of the input voltage small signal modelVCins. (a) Stage 1. (b) Stage 2.
(a)(b)For the first stage, switchS1 is ON (Figure 12(a)), and the following differential equations describe the behavior of the converter:(52)LmdiLmtdt=vC2tN,(53)CindvCintdt=−1RvC1t+iint−iLmt−vCintR+NvC2t−NvCintRc2,(54)C1dvC1tdt=−1RvC1t−vCintR,(55)C2dvC2tdt=−1Rc2vC2t+NvCintRc2,where N is the turns ratio of the coupled inductor, R is the load resistance, and Rc2 is the ESR of the capacitor C2.For the second stage, switchS1 is OFF (Figure 12(b)); the following differential equations describe the behavior of the converter:(56)LmdiLmtdt=−1N+1vC1t+vC2tN+1,(57)CindvCintdt=−1RvC1t+iint−vCintR,(58)C1dvC1tdt=−1RvC1t+iLmtN+1−vCintR,(59)C2dvC2tdt=−iLmtN+1.Applying the Laplace transform results in(60)Y˜s=CsI−A−1λ+Υd˜s,where the matrices λ and Υ are defined by(61)λ=A1−A2X+B1−B2U,(62)Υ=C1−C2X+E1−E2U.By solving these equations, the transfer function (FT) of the input capacitor voltagevCin by D is obtained. Applying the prototype values presented in Table 1, the FT is obtained, and the final result is provided by(63)Gvs=v˜Cinsd˜s=N4s3+N3s2+N2s+N1s4+D4s3+D3s2+D2s+D1,whereN4=−3,874⋅103,N3=−6,222⋅1008,N2=−2,104⋅1012,N1=−6,444⋅1014,D4=1,040⋅106,D3=1,451⋅108,D2=6,957⋅1010,andD1=3,220⋅1012.For model validation, as shown in Figure13, at time instants of 0.45 and 0.6 seconds, two disturbances being the positive (+0.5 A) and the negative of (−0.5 A), respectively, were applied to the input current iins of the photovoltaic panel (PV). Two duty cycle steps ds were also applied at the time instants of 0.75 seconds +1% and 0.85 seconds −1%. All disturbances aim to verify the effect caused on the input capacitor voltage vCins of the converter. Table 1 shows the parameters of the components used in the prototype. As shown in Figure 13, the model of vCins faithfully follows the behavior of the circuit.Figure 13
Validation of the input voltage small signal modelVCins.In this paper, the converter input is considered a PV panel. Thus, to ensure the tracking of the maximum power point (MPPT), the control strategy presented in Figure14(a) was used, which is composed of the measurement of the current ipv and of the voltage vpv of the panel, the MPPT algorithm, thus generating the input voltage reference v˜i,refs, the gain of the sensors Hvs, the controller Cvis, and the plant Gvs. The MPPT algorithm implemented in the PV panel is the Perturb and Observe (P&O), already consolidated in the literature. The algorithm provides the input voltage reference v˜i,refs which is compared to the input voltage v˜is measured in the converter, generating an error that passes through the PI controller C˜vis which gives the duty cycle d˜s, which adjusts the tension v˜is through the FT from vCins by dsGvs. The PI controller was designed using Matlab’s Sisotool tool, and the goat diagram is given through(64)Cvi,dz=−3.23201846×10−4z+3.15398154×10−4z−1.Figure 14
Input voltage controller design.
(a)(b)The open-loop and compensated open-loopBode diagram is shown in Figure 14(b). The open-loop system has a phase margin (MF) of 152° and a cutoff frequency of 3.26 kHz. With the use of the PI controller, the compensated system has an MF of 69° with a cutoff frequency of 11 Hz. This controller design achieved the expected result, obtaining satisfactory experimental results.


## 3. Performance Comparison

In order to highlight the merits of the proposed converter, Table2 shows a comparison of similar converters. The factors evaluated are voltage gain, the maximum voltage stress on the switch and diode, and the number of components. From this, it is evident that the proposed converters are attractive, in which the SBCIVM2 presents higher voltage gain and lower voltage stress on semiconductors while the SBCI has the lower component count. Thus, it is evident that these proposed converters are good candidates for high voltage gain applications.Table 2
Performance comparison.
ConverterGainMMaximum voltageMaximum voltageSwitchesDiodesInductorCapacitorCommonStress on switchVs/ViStress on diodeVDo/ViCountCountCountCountGroundedSBCIND+1/1−D1/1−D2N/1−D1111YesSBCIVM1N+1/1−D1/1−D2N+1/1−D1212YesSBCIVM22N+1−ND/1−D1/1−D2N+1/1−D1313Yes[36]2/1−D2/1−D2/1−D2222Yes[37]D/1−D112223Yes[38]D/1−D112223Yes[44]1+T+DT/1−D1/1−D1+T/1−D1313No


## 4. Experimental Results

To validate the theoretical evaluations made in the paper, three prototypes of the converters were built according to the specifications in Table2. As can be seen in Table 1, the coupled inductor winding approach allowed achieving a significantly low leakage inductance value. Besides that, the TMS320F28335 Digital Signal Processor was implemented to provide the PWM signal, and a Yokogawa WT1800 power meter and a Tektronix Encore MD03000 oscilloscope were used to measure the efficiency and the experimental waveforms of the proposed converters.Figure15 shows the switch voltage vgs, the input voltage vi, the capacitor voltage C1vC1, and the voltage of output vo. Using a duty cycle D=0.7079, the SBCI achieves the output voltage vo=400V, as calculated, in Figure 15(a). For the SBCIVM1 and SBCIVM2, a duty cycle D=0.6260 and D=0.4802, respectively, was used to achieve the output voltage vo=400V, in Figures 15(b) and 16(c). For all cases, the desired voltage gain was reached, thus validating the theoretical evaluations.Figure 15
Experimental results of voltage gain (10μ s/div). (a) SBCI. (b) SBCIVM1. (c) SBCIVM2.
(a)(b)(c)Regarding the semiconductor voltage stress, Figure16 presents the experimental results. For SBCI, in Figure 16(a), the switch presents the maximum voltage VS1=128V approximately while the maximum voltage of diode D1 is VD1=750V. The voltage value on diode D1 was much higher than expected due to parasitic elements in the converter. For SBCIVM1, in Figure 16(b), the maximum voltage at the semiconductors is VS1=100V, VS1=100V, VD1=600V, VD1=600V, and VD2=300V. As can be seen, this converter does not have voltage spike problems. Therefore, all the maximum voltages reached are in agreement with the theoretical evaluations. For SBCIVM2, in Figure 16(c), the maximum voltage at the semiconductors is VS1=72V, VS1=72V, VD1=575V, VD1=575V, and VD2=VD3=218V. The SBCIVM2 also does not present voltage spike problems, so all voltages reached are in accordance with theoretical evaluations.Figure 16
Experimental results of voltage stress across the semiconductors (10μ s/div). (a) SBCI. (b) SBCIVM1. (c) SBCIVM2.
(a)(b)(c)It should be noted that, as desired, the switches of the converters do not present any overvoltage. Thus, the advantages of the proposed coupled inductor winding technique are evident.The power source Agilent E4360 A programmable was chosen to emulate the PV module CS5A-200 manufactured by Canadian Solar and described in standard test conditions (1000 W/m2 and cell temperature of 25°C): Pmppt= 200 W, Vmppt= 37.4 V, Imppt= 5.35 A, Voc= 45.3 V, and Isc= 5.71 A.The MPPT algorithm used is the Perturb and Observe (P&O) technique, and this algorithm presents the simplicity of operation and efficiency greater than 99%. In this work, the tracking time adopted is 0.5 s to update the algorithm and the experimental results present good performance. No type of optimization was done.Thus, Figure17 shows the MPPT experimental results, where the converters are exposed to different steps of the irradiance, and the P&O algorithm and the control strategy accomplished the MPPT. Thus, it is evident that the proposed converters are good candidates for applications using solar panels.Figure 17
MPPT and controle experimental results (10 s/div). (a) SBCI. (b) SBCIVM1. (c) SBCIVM2.
(a)(b)(c)Figure18 presents the efficiency results of the proposed converters for different values of input power. It is evident that the SBCIVM2 presents higher efficiency in the entire input power range, reaching a peak of 97.53% at nominal power. Also, it can be highlighted that the SBCIVM1 achieves good efficiency.Figure 18
Experimental efficiency results.SBCI has a lower efficiency than all other converters over the entire input power range. In relation to SBCIVM1 and SBCIVM2, they present attractive efficiency. ForPi higher than 100 W, SBCIVM1 has an efficiency higher than 95% while SBCIVM2 achieves higher efficiency than 96% over the entire input power range.Finally, to demonstrate the effect of parasitic elements on the proposed converters, the experimental voltage gain results were obtained. Figure19 presents the experimental result compared to the ideal voltage gain of each converter. As can be seen, the effect of parasitic elements is significant when D is higher than 0.8; that is, the experimental voltage gain is considerably lower compared to the ideal voltage gain.Figure 19
Voltage gain experimental results.


## 5. Conclusion

This paper presented three topologies of high voltage gain converters based on a simple solution of stacked input and output connection of nonisolated converters and the buck-boost converter. Besides that, from a new coupled inductor winding approach, low leakage inductance values were achieved. This allowed no auxiliary circuits to be used in the converters. Thus, the proposed converters achieved good performance with a reduced number of components compared to other high voltage gain topologies proposed in the literature.The first proposed converter uses only one coupled inductor to increase the voltage gain while the second and third proposed converters, in addition to the coupled inductor, have one or two voltage multiplier cells, respectively. This approach allows the voltage gain of the converters to increase. From this, the converters were theoretically and experimentally evaluated in open loop and closed loop and performed the MPPT. All converters perform well.Finally, it is noteworthy that the SBCIVM2 presented better characteristics in relation to voltage gain, voltage and current effort, and better performance. On the other hand, this converter has a greater number of components. But overall, the SBCIVM2 is an attractive converter for high voltage gain applications.



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*Source: 1788472-2022-06-27.xml*