# Novel Modified High Step-Up DC/DC Converters with Reduced Switch Voltage Stress

Authors: Lingling Liu; Donghui Li
Journal: International Transactions on Electrical Energy Systems
 (2022)

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## Abstract

This paper presents the improved switched inductor unit and new step-up DC/DC converters with reduced switch voltage stress and high voltage gain. The proposed switching-inductor unit is composed of 1 switch, 2 diodes, and 2 inductors, which can realize the step-up function. Through comparison, the better topology is selected from the proposed converters, which is named the double-switch high step-up (DS-HS) converter. The CCM operating principles and voltage gain of the DS-HS converter are analyzed. Then, the influences of nonideal components, efficiency analysis, small signal modeling and control, and design criteria of components are discussed. The comparison of the converters is given, and the loss of the DS-HS converter is lower through theoretical derivation, which shows that the DS-HS converter has the advantages of high voltage gain, low voltage stress, and high efficiency. Finally, in order to verify the effectiveness of the DS-HS converter, simulation and experimental results are given, and the efficiency of the DS-HS converter can reach 96.15%.


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## Body

## 1. Introduction

In recent years, the world’s attention to the adhibition of renewable energy for power generation has greatly increased. Photovoltaic cells and fuel cells are sources of renewable energy power generation and have received sufficient attention. Because of the low output voltage of these renewable energy sources, it is not enough to be used in many applications [1]. Therefore, it is necessary to need an efficient and high boost DC/DC converter to achieve step-up. High-boost DC/DC converters can be applied to photovoltaic and fuel cell energy conversion systems, DC microgrids, automobiles, uninterruptible power supplies, high-intensity light ballasts, LEDs, and hybrid vehicles [2, 3]. Since the output DC voltage of solar photovoltaic power generation and fuel cell power generation is low, generally less than 50 V, the low DC voltage needs to be boosted to the 380 V DC bus voltage of input of the grid-connected full-bridge inverter. Therefore, the nonisolated high-gain DC converter is an important link to ensure the normal operation of the entire photovoltaic power generation system and fuel cell power generation system and has a very important impact on the entire system.For the classic boost converter [4], theoretically, it can achieve high voltage gain only as the duty cycle approaches 1. Recently, a number of DC/DC converters on account of several enhancement techniques have been proposed in [5]. Isolated step-up DC/DC converters can easily achieve high boost through transformers, such as H-bridge, push-pull, and others. However, due to the need for high-frequency transformers and supplementary circuits to handle leakage inductance energy [6, 7], these converters are bulky, large, and expensive. In addition, due to transformer leakage inductance, the voltage stresses of active switches on these converters are high. Therefore, additional energy regeneration technology and voltage clamping technology are needed to recover the leakage energy and reduce the voltage stress of the active switches [8, 9]. The boost DC/DC converters based on coupled inductors can achieve high step-up; however, additional voltage clamping techniques and input filters are needed to reduce ripple and leakage inductance energy recovery solutions, which lead to higher costs. In addition, authors in [10–12] also introduce additional losses related to the clamping circuit. However, these topologies are complicated, and the gain factor depends on the coupling coefficient of the coupled inductor. The LLC resonant converter uses the principle of soft switching to realize zero-voltage (zero-current) switching of the switching device, which greatly reduces the switching loss of the converter and further improves the switching frequency of the converter [13–15]. The LLC resonant converter has the advantages of parasitic parameter compatibility and good soft switching performance, but it also has a certain complexity, and its energy transfer is realized by using a complex resonant circuit. The cascaded and secondary boost converters can be other ways to the problem, but high-voltage devices are still required, and the switch voltage stress is equal to the output voltage. The cascade of two or more DC/DC converter topologies brings about complex circuits and increased costs. Because the voltage gain is highly nonlinear, two or more switches are required to be synchronized [9, 16–18], and the control is complicated.In order to solve the problems of the aforementioned converters, switched inductors (SIs), mixed switched inductors and capacitors, interleaved front-end structures, and multiplier-based converters are possible approaches recently [19–23]. However, multiple power levels are applied in many cases, and the voltage stress of the active switch is too high or even equal to the output voltage. In addition, using many multipliers will increase the measure and cost of the system. For the sake of reducing the voltage and current stress on the switch and obtaining a higher boost voltage gain, the DC-DC converters are proposed in [24, 25], when the duty cycle is not high. However, the converters in [23, 24] require a lot of reactive components and achieve high boost through the cascade. The geometric structure method is proposed in [26], which is a method to develop the DC conversion topology by constructing the geometric structure. However, the constructed geometric structure is only for a certain part of the topology, not for the whole topology, so it still cannot be unified in the character analysis, and the analysis process is too cumbersome.In this paper, the improved switching-inductor unit and new high step-up DC-DC converters with reduced switch voltage stress and high voltage gain are proposed. Then, the better topology is selected from the proposed converters by comparison, named the double-switch high step-up (DS-HS) converter, in Section2. Section 3 analyzes the CCM operating principles and voltage gain of the DS-HS converter so as to verify the accuracy of the DS-HS converter in Section 2. The impact of nonideal components on the output voltage and efficiency is analyzed in Section 4. A comparison with existing converters is shown in Section 5. Section 6 provides the design criteria for components. Small-signal models and control schemes are listed in Section 7. Sections 8 and 9 deal with the simulation and experimental results of the DS-HS converter. At last, Section 10 draws conclusions.


## 2. Proposed Switching-Inductor Unit and Step-Up Converters

Section2 proposes the improved switching-inductor unit and new high step-up DC/DC converters with reduced switch voltage stress and high voltage gain, and the better boost converter is selected from the proposed converters.


### 2.1. Proposed Switching-Inductor Unit

Based on the switching-inductor unit in [16], a modified switching-inductor unit is proposed. The switching-inductor units and operating conditions are shown in Figure 1. Figure 1(a) is the existing switching-inductor unit, consisting of 3 diodes and 2 inductors. By replacing a diode in Figure 1(a) with a switch and changing the position of the switch, it helps to share the voltage stress on this branch of the switches, when combining the step-up DC converters. The improved switching-inductor unit of Figure 1(b) originated from Figure 1(a) is proposed, consisting of 2 diodes, 1 switch, and 2 inductors. Figures 1(c) and 1(d) are the operating conditions of the improved switching-inductor unit. The inductors are charged in Figure 1(c), when the switch is in the conductive state. The inductors are discharged in Figure 1(d), when the switch is turned off. Simultaneously, the current flows in the direction of the arrow in Figures 1(c) and 1(d).Figure 1
Switching-inductor units and operating conditions. (a) Switching-inductor [16]. (b) Improved switching-inductor. (c) The operating condition when the switch is turned on. (d) The operating condition when the switch is turned off.
(a)(b)(c)(d)


### 2.2. Proposed High Step-Up Converters

Combining the proposed switching-inductor unit with the existing converters [27], four new step-up DC/DC converters with reduced switch voltage stress and high voltage gain are proposed in Figure 2. On the branch of the switches, two switches S1 and S2 can share the voltage stress with each other, as shown in Figure 2 marked with a red box, so the voltage stress of the switch can be much lower, compared with the DC/DC converter with only one switch in the branch. The characteristics of four proposed DC/DC converters are shown in Table 1, including voltage gain, voltage stress of switch, maximum of diode voltage, and the number of components. From Table 1, we can see that the converters of Figures 2(a)–2(d) have the same number of components. Compared with Figures 2(b) and 2(d), the converters in Figures 2(a) and 2(c) have higher voltage gain and lower voltage stress of the switches and diodes. The input current of the converters in Figures 2(a) and 2(d) is not pulsating but that of the DC/DC converters in Figures 2(b) and 2(c) is the opposite. By filtering the circuit with lower voltage stress and higher voltage gain, the converters in Figures 2(a) and 2(c) can be filtered out. In addition, the input current of the DC converter in Figure 2(a) is not pulsating, so its input current has less disturbance to the input power. All in all, by comparison, the proposed converter in Figure 2(a) is better, and the detailed analysis in the following section is carried out on the converter in Figure 2(a).Figure 2
Proposed new DC converters. (a) Converter I. (b) Converter II. (c) Converter III. (d) Converter IV.
(a)(b)(c)(d)Table 1
Characteristics of the proposed converters.
Figure2(a)Figure2(b)Figure2(c)Figure2(d)Voltage gain (G)21+D/1−D−1+3D/1−D21+D/1−D−1+3D/1−DSwitch voltage (US1 and US2)G+2Uo/4GG+3Uo/4GG+2Uo/4GG+3Uo/4GG−2Uo/4GG−1Uo/4GG−2Uo/4GG−1Uo/4GMaximum of diode voltageUo/21+D/1+3DUoUo/21+D/1+3DUoC/I/D/S/T2/2/6/1/112/2/6/1/112/2/6/1/112/2/6/1/11Pulsating input current(yes/no)NoYesYesNo


## 2.1. Proposed Switching-Inductor Unit

Based on the switching-inductor unit in [16], a modified switching-inductor unit is proposed. The switching-inductor units and operating conditions are shown in Figure 1. Figure 1(a) is the existing switching-inductor unit, consisting of 3 diodes and 2 inductors. By replacing a diode in Figure 1(a) with a switch and changing the position of the switch, it helps to share the voltage stress on this branch of the switches, when combining the step-up DC converters. The improved switching-inductor unit of Figure 1(b) originated from Figure 1(a) is proposed, consisting of 2 diodes, 1 switch, and 2 inductors. Figures 1(c) and 1(d) are the operating conditions of the improved switching-inductor unit. The inductors are charged in Figure 1(c), when the switch is in the conductive state. The inductors are discharged in Figure 1(d), when the switch is turned off. Simultaneously, the current flows in the direction of the arrow in Figures 1(c) and 1(d).Figure 1
Switching-inductor units and operating conditions. (a) Switching-inductor [16]. (b) Improved switching-inductor. (c) The operating condition when the switch is turned on. (d) The operating condition when the switch is turned off.
(a)(b)(c)(d)


## 2.2. Proposed High Step-Up Converters

Combining the proposed switching-inductor unit with the existing converters [27], four new step-up DC/DC converters with reduced switch voltage stress and high voltage gain are proposed in Figure 2. On the branch of the switches, two switches S1 and S2 can share the voltage stress with each other, as shown in Figure 2 marked with a red box, so the voltage stress of the switch can be much lower, compared with the DC/DC converter with only one switch in the branch. The characteristics of four proposed DC/DC converters are shown in Table 1, including voltage gain, voltage stress of switch, maximum of diode voltage, and the number of components. From Table 1, we can see that the converters of Figures 2(a)–2(d) have the same number of components. Compared with Figures 2(b) and 2(d), the converters in Figures 2(a) and 2(c) have higher voltage gain and lower voltage stress of the switches and diodes. The input current of the converters in Figures 2(a) and 2(d) is not pulsating but that of the DC/DC converters in Figures 2(b) and 2(c) is the opposite. By filtering the circuit with lower voltage stress and higher voltage gain, the converters in Figures 2(a) and 2(c) can be filtered out. In addition, the input current of the DC converter in Figure 2(a) is not pulsating, so its input current has less disturbance to the input power. All in all, by comparison, the proposed converter in Figure 2(a) is better, and the detailed analysis in the following section is carried out on the converter in Figure 2(a).Figure 2
Proposed new DC converters. (a) Converter I. (b) Converter II. (c) Converter III. (d) Converter IV.
(a)(b)(c)(d)Table 1
Characteristics of the proposed converters.
Figure2(a)Figure2(b)Figure2(c)Figure2(d)Voltage gain (G)21+D/1−D−1+3D/1−D21+D/1−D−1+3D/1−DSwitch voltage (US1 and US2)G+2Uo/4GG+3Uo/4GG+2Uo/4GG+3Uo/4GG−2Uo/4GG−1Uo/4GG−2Uo/4GG−1Uo/4GMaximum of diode voltageUo/21+D/1+3DUoUo/21+D/1+3DUoC/I/D/S/T2/2/6/1/112/2/6/1/112/2/6/1/112/2/6/1/11Pulsating input current(yes/no)NoYesYesNo


## 3. Operating Principle of the Proposed Converter

This section discusses the operating principles and voltage gain of the better converter in Figure2(a), named the double-switch high step-up (DS-HS) converter. The continuous-conduction mode (CCM) for the DS-HS converter is shown in Figure 3, where D is the duty ratio, and TS is a whole cycle. DTS represents the time that the switch is turned on, which is recorded as Ton, and (1-D) TS represents the time that the switch is turned off, which is recorded as Toff.Figure 3
Switching condition and typical waveforms of CCM.The operating principle of the DS-HS converter in CCM is shown in Figure4. The components connected by solid lines represent operation, but the components connected by dotted lines represent nonoperation in the circuit. Let us assume that the inductance of L1 is equal to L2, and the capacitance of C1 is equal to C2. The operation condition of the circuit during t0 − t1 can be shown in Figure 4(a). The inductors L1 and L2 are charged by the DC power supply, and in the meantime, the capacitors C1 and C2 charge the load. The operation condition of the circuit during t1 − t2 is shown in Figure 4(b). The DC power supply, L1, and L2 release energy to C1 and C2.Figure 4
Operating principles of the DS-HS converter in CCM. (a) WhenS1 is Ton. (b) When S1 is Toff.
(a)(b)In Figure4(a), the inductors L1 and L2 are charged during Ton, and their voltages are as follows:(1)UL1=UL2=Ui,C1 and C2 are discharged during the Ton period, and they are as follows:(2)UC1=UC2=Uo2.In Figure4(b), the voltages at L1 and L2 are expressed during Toff as follows:(3)UL1=UL2=UC1−Ui2=UC2−Ui2.On the basis of voltage-second balances ofL1 and L2, the expression is as follows:(4)∫t0t1Uidt=∫t0t1UC1−Ui2dt=∫t0t1UC2−Ui2dt.According to Figure3 and equation (4), the voltages at C1 and C2 are as follows:(5)UC1=UC2=1+D1−DVi.Combining the equations (2) and (5), the output voltage Uo is obtained as follows:(6)Uo=21+D1−DVi.According to equation (6), the voltage gain of the DS-HS converter in CCM can be expressed as follows:(7)G=21+D1−D.


## 4. Effect of Nonidealities on Output Voltage

The nonidealities of the DS-HS converter are considered in Figure5 to discuss the nonideal effects of components on voltage gain. The equivalent series resistance (ESR) of the inductors L1 and L2 is the resistance rL. The ON-state resistance of switches S1 and S2 is represented by the resistance rS. The threshold voltage and the forward resistance of diodes D1, D2, D3, D4, and D5 are indicated by the voltage UFD and resistance rD, respectively. The ESR of C1 and C2 is rC, and the ESR of Co is shown by rCo.Figure 5
Nonideal equivalent circuit of the DS-HS converter.


### 4.1. Nonideal Effect of InductorsL1 and L2 on Output Voltage

Considering the effect of ESR of the inductorsL1 and L2, other parasitic parameters are neglected, i.e., rS = 0, rD = 0, rCo = 0, rC = 0, and UFD = 0.Considering the case mentioned above, during theTon period, the voltages across inductors L1 and L2 are expressed as follows:(8)UL1≈Ui−iL1rL,UL2≈Ui−iL2rL.DuringToff, the voltages at L1 and L2 can be expressed as follows:(9)UL1+UL2≈UC1+iL1rL+iL2rL−Ui.According to (8), add the voltages across inductors, and the following formula is obtained:(10)UL1+UL2≈2Ui−iL1rL−iL2rL.On the basis of voltage-second balances onL1 and L2, the following formula is obtained:(11)2Ui−iL1rL−iL2rLD=UC1+iL1rL+iL2rL−Ui1−D.The ratio of the voltages ofC1 and C2 to the input voltage Ui is as follows:(12)UC1Vi|rL=VC2Vi|rL=1+D−iL1rL+iL2rL/Vi1−D.BecauseL1 = L2, the currents through the inductors L1 and L2 are equal, i.e., iL = iL1 = iL2. Assume that the voltage drop across ESR of the inductor is Ud − L, i.e., Ud − L = iL1rL = iL2rL. Thus, (12) can be re-expressed as follows:(13)UC1Vi|rL=UC2Vi|rL=1+D−2Ud−L/Vi1−D.The relationship between the output voltageUo and the voltages of C1 and C2 is as follows:(14)Uo=2UC1=2UC2.Combining the formulas (13) and (14), the voltage gain of the DS-HS converter can be deduced as follows:(15)UoUi|rL=21+D−4Ud−L/Ui1−D.Considering the different values ofUd − L/Ui and duty cycle D, equation (15) is shown in Figure 6(a), which indicates the effect of the inductor’s ESR on the voltage gain. It can be observed that the voltage gain will decrease for higher values of Ud − L. This fact indicates that the ESR (rL) of the inductor should be as small as possible.Figure 6
Nonideal effect on the duty cycle and voltage gain. (a) Inductors, (b) diodes, (c) switches, and (d) capacitors.
(a)(b)(c)(d)


### 4.2. Effect of DiodesD1, D2, D3, D4, and D5 on Output Voltage

Considering the effect of diodesD1, D2, D3, D4, and D5, other parasitic parameters are neglected, i.e., rL = 0, rC = 0, rCo = 0, and rS = 0. Assume that the voltage drops due to forward resistance, and the threshold voltage of the diodes are Ud − D1, Ud − D2, Ud − D3, Ud − D4, and Ud − D5, and the expressions are as follows:(16)Ud−D1=UFD+iD1rD,Ud−D2=UFD+iD2rD,Ud−D3=UFD+iD3rD,Ud−D4=UFD+iD4rD,Ud−D5=UFD+iD5rD.Considering the case mentioned above, duringTon, the voltages across inductors L1 and L2 are expressed as follows:(17)UL1≈Ui−Ud−D1,UL2≈Ui.DuringToff, the voltages at L1 and L2 are as follows:(18)UL1+UL2≈UC1+Ud−D2+Ud−D4−Ui=UC2+Ud−D2+Ud−D5−Ui.According to (17), add voltages across inductors, and the following formula is obtained:(19)UL1+UL2≈2Ui−Ud−D1.On the basis of voltage-second balances onL1 and L2, the following formula is obtained:(20)2Ui−Ud−D1D=UC1+Ud−D2+Ud−D4−Ui1−D=UC2+Ud−D2+Ud−D5−Ui1−D.The ratios of the voltages ofC1 and C2 to the input voltage Ui are obtained as follows:(21)UC1Ui|rD=1+D−DUd−D1/Ui−1−DUd−D2+Ud−D4/Ui1−D,(22)UC2Ui|rD=1+D−DUd−D1/Ui−1−DUd−D2+Ud−D5/Ui1−D.Combining the formulas (14), (21), and (22), the relationship between output and input voltages on the DS-HS converter can be deduced as follows:(23)UoUi|rD=UC1Ui|rD+UC2Ui|rD−Ud−D3Ui=21+D−2DUd−D1Ui−1−D2Ud−D2+Ud−D3Ui−1−DUd−D4+Ud−D5Vi11−D.Assuming that the voltage drops of all the diodes are equal, then we get the following formula:(24)Ud−D=Ud−D1=Ud−D2=Ud−D3=Ud−D4=Ud−D5.Thus, (23) can be re-expressed as follows:(25)UoUi|rD=21+D−5−3DUd−D/Ui1−D.Considering the different values ofUd − D/Ui and D, equation (25) is revealed in Figure 6(b), which indicates the effect of the diodes on the voltage gain. It can be observed that for higher values of Ud − D/Ui, the voltage gain will decrease. It indicates that the smaller the forward resistance and threshold voltage of the diodes, the better.


### 4.3. Effect of SwitchesS1 and S2 on Output Voltage

Since only the effect of switchesS1 and S2 is analyzed here, other parasitic parameters are neglected, i.e., rL = 0, rC = 0, rCo = 0, rD = 0, and UFD = 0.DuringTon, the voltages across inductors L1 and L2 are as follows:(26)UL1≈Ui−iS1rS−iS2rS,UL2≈Ui−iS1rS.DuringToff, the voltages at L1 and L2 are expressed as follows:(27)UL1+UL2≈UC1−Ui=UC2−Ui.According to (26), add voltages across L1 and L2, and the formula is obtained as follows:(28)UL1+UL2≈2Ui−2iS1rS−iS2rS.On the basis of voltage-second balances onL1 and L2, the following formula is obtained:(29)2Ui−2iS1rS−iS2rSD=UC1−Ui1−D=UC2−Ui1−D.The ratios of the voltages ofC1 and C2 to the input voltage Ui are as follows:(30)UC1Ui|rS=UC2Ui|rS=1+D−D2iS1rS+iS2rS/Ui1−D.Combining the formulas (14) and (30), the voltage gain of the DS-HS converter can be obtained as follows:(31)UoUi|rS=UC1Ui|rS+UC2Ui|rS−iS1rS+iS2rSUi=21+D−2D2iS1rS+iS2rS/Ui−1−DiS1rS+iS2rS/Ui1−D=21+D−1+3DiS1rS/Ui−1+DiS2rS/Ui1−D.Assume that the voltage drops on the switchesS1 and S2 are as follows:(32)Ud−S1=iS1rS,Ud−S2=iS2rS.Thus, (31) can be re-expressed as follows:(33)UoUi|rS=21+D−1+3DUd−S1/Ui−1+DUd−S2/Ui1−D.Assume thatUd−S=Ud−S1=Ud−S2. Thus, (33) is rewritten as follows:(34)UoUi|rS=21+D−21+2DUd−S/Ui1−D.By considering the different values ofUd − S/Ui and D, (34) is shown in Figure 6(c), and it also shows the relationship between the on-resistance of the switches and the voltage gain. It is observed that the higher the values of Ud − S, the lower the voltage gain. This fact indicates that the ON-state resistance of the switches should be as small as possible.


### 4.4. Effect of the CapacitorsC1, C2, and Co on Output Voltage

Considering the effect of ESR of capacitors C1, C2, andCo, other parasitic parameters are neglected, i.e., rL = 0, rD = 0, UFD = 0, and rS = 0.Considering the case mentioned above, duringTon, the voltages across the inductors L1 and L2 are expressed as follows:(35)UL1≈Ui,UL2≈Ui.Simultaneously,C1 and C2 are discharged to Co, and the output voltage is as follows:(36)Uoon=UC1+UC2−iC1onrC−iC2onrC=UCo+iCoonrCo.DuringToff, the voltages at L1 and L2 are expressed as follows:(37)UL1+UL2≈UC1+iC1offrC−Ui=UC2+iC2offrC−Ui.The capacitorCo is discharged through load Ro during t1 − t2, and the output voltage is as follows:(38)Uooff=UCo−iCooffrCo.According to (35), add voltages across inductors, and the following formula is obtained:(39)UL1+UL2≈2Ui.On the basis of voltage-second balances onL1 and L2, the following formula is obtained:(40)2UiD=UC1+iC1offrC−Ui1−D=UC2+iC2offrC−Ui1−D.The ratios of the voltage ofC1 and C2 to the input voltage Vi are shown as follows:(41)UC1Ui|rC=1+D−iC1offrC1−D/Ui1−D,(42)UC2Ui|rC=1+D−iC2offrC1−D/Ui1−D.Since the capacitor voltage cannot be changed suddenly, the voltages acrossC1, C2, and Co remain unchanged during the whole cycle. Therefore, the average value of the output voltage Uo in a whole period is as follows:(43)Uo=DUoon+1−DUooff=UCo.According to formulas (36), (38), (41), and (42), it can be obtained as follows:(44)UoUi|rC,rCo=UCoUi=UC1+UC2−iC1onrC−iC2onrC−iCoonrCoUi=21+D−iC1offrC1−D/Ui−iC2offrC1−D/Ui−iC1onrC1−D/Ui−iC2onrC1−D/Ui−iCoonrCo1−D/Ui1−D=21+D−iC1off+iC1onrC1−D/Ui−iC2off+iC2onrC1−D/Ui−iCoonrCo1−D/Ui1−D.The currents through the capacitorsC1 and C2 are as follows:(45)iCon=iC1on=iC2on,iCoff=iC1off=iC2off.Hence, the voltage gain is as follows:(46)UoUi|rC,rCo=21+D−iCoonrCo1−D/Ui−2iCoff+iConrC1−D/Ui1−D.Let us suppose the voltage drops due to ESR ofC1, C2, and Co are Ud − C and Ud − Co, then we get the following formula:(47)Ud−C=iCoff+iConrC,Ud−Co=iCoonrCo.Thus, (46) can be re-expressed as follows:(48)UoUi|rC,rCo=21+D−2Ud−C1−D/Ui−Ud−Co1−D/Ui1−D.Further, let us assume thatUd−C=Ud−Co. Thus, (48) is rewritten as follows:(49)UoUi|rC=21+D−3Ud−C1−D/Ui1−D.By considering the different values ofUd − C/Ui and D, equation (49) is shown in Figure 6(d), and it shows the effect of the ESR of the capacitors on voltage gain. It can be observed that for higher values of Ud − C/Ui, the voltage gain will decrease. This fact indicates that the ESR of the capacitor should be as small as possible.


### 4.5. Combined Effect of Nonidealities on Voltage Gain

By considering the nonideal effect of inductorsL1 and L2, diodes D1, D2, D3, D4, and D5, switches S1 and S2, and capacitors C1, C2, and Co, respectively, the voltage gain is expressed as follows:(50)UoUi≈21+D−4Ud−L/Ui−5−3DUd−D/Ui−21+2DUd−S/Ui−3Ud−C1−D/Ui1−D.


### 4.6. Efficiency Analysis

The proportional relationship between the inductor current and the output current is as follows:(51)IL=IL1=IL2=21−DIo=21−DUoRo.Considering thatPSW − S1 and PSW − S2 are the power losses on account of switching of S1 and S2, respectively, the total loss PSW during switching is as follows:(52)PSW=∑i=1,2PSW−Si=12TSIS1US1tr−S1+tf−S1+IS2US2tr−S2+tf−S2,where the rising and falling time of switches S1 and S2 are tr − S1, tf − S1 and tr − S2, tf − S2; IS1, US1 and IS2, US2 are the average current and voltage on S1 and S2.The core loss of the inductors is considered, so it can be shown as follows:(53)PFe=2KM′fmBacn,where Bacn is the operating magnetic position swing of the inductor core, M´ is the quality of the inductor core, and K, m, and n are the coefficients determined by the core material. The parameters can be found in the datasheet.The total power of the input and output are received as follows:(54)Pi=Ui2ILD+IL1−D+PSW+PFe,=2Ui1−DUoRo1+D+PSW+PFe,Po=Uo2Ro.According to (50)–(54), the efficiency of the DS-HS converter is obtained as follows:(55)η≈21+D−4Ud−L/Ui−5−3DUd−D/Ui−21+2DUd−S/Ui−3Ud−C1−D/Ui21+D+PSWRo1−D/UoUi+PFeRo1−D/UoUi.


## 4.1. Nonideal Effect of InductorsL1 and L2 on Output Voltage

Considering the effect of ESR of the inductorsL1 and L2, other parasitic parameters are neglected, i.e., rS = 0, rD = 0, rCo = 0, rC = 0, and UFD = 0.Considering the case mentioned above, during theTon period, the voltages across inductors L1 and L2 are expressed as follows:(8)UL1≈Ui−iL1rL,UL2≈Ui−iL2rL.DuringToff, the voltages at L1 and L2 can be expressed as follows:(9)UL1+UL2≈UC1+iL1rL+iL2rL−Ui.According to (8), add the voltages across inductors, and the following formula is obtained:(10)UL1+UL2≈2Ui−iL1rL−iL2rL.On the basis of voltage-second balances onL1 and L2, the following formula is obtained:(11)2Ui−iL1rL−iL2rLD=UC1+iL1rL+iL2rL−Ui1−D.The ratio of the voltages ofC1 and C2 to the input voltage Ui is as follows:(12)UC1Vi|rL=VC2Vi|rL=1+D−iL1rL+iL2rL/Vi1−D.BecauseL1 = L2, the currents through the inductors L1 and L2 are equal, i.e., iL = iL1 = iL2. Assume that the voltage drop across ESR of the inductor is Ud − L, i.e., Ud − L = iL1rL = iL2rL. Thus, (12) can be re-expressed as follows:(13)UC1Vi|rL=UC2Vi|rL=1+D−2Ud−L/Vi1−D.The relationship between the output voltageUo and the voltages of C1 and C2 is as follows:(14)Uo=2UC1=2UC2.Combining the formulas (13) and (14), the voltage gain of the DS-HS converter can be deduced as follows:(15)UoUi|rL=21+D−4Ud−L/Ui1−D.Considering the different values ofUd − L/Ui and duty cycle D, equation (15) is shown in Figure 6(a), which indicates the effect of the inductor’s ESR on the voltage gain. It can be observed that the voltage gain will decrease for higher values of Ud − L. This fact indicates that the ESR (rL) of the inductor should be as small as possible.Figure 6
Nonideal effect on the duty cycle and voltage gain. (a) Inductors, (b) diodes, (c) switches, and (d) capacitors.
(a)(b)(c)(d)


## 4.2. Effect of DiodesD1, D2, D3, D4, and D5 on Output Voltage

Considering the effect of diodesD1, D2, D3, D4, and D5, other parasitic parameters are neglected, i.e., rL = 0, rC = 0, rCo = 0, and rS = 0. Assume that the voltage drops due to forward resistance, and the threshold voltage of the diodes are Ud − D1, Ud − D2, Ud − D3, Ud − D4, and Ud − D5, and the expressions are as follows:(16)Ud−D1=UFD+iD1rD,Ud−D2=UFD+iD2rD,Ud−D3=UFD+iD3rD,Ud−D4=UFD+iD4rD,Ud−D5=UFD+iD5rD.Considering the case mentioned above, duringTon, the voltages across inductors L1 and L2 are expressed as follows:(17)UL1≈Ui−Ud−D1,UL2≈Ui.DuringToff, the voltages at L1 and L2 are as follows:(18)UL1+UL2≈UC1+Ud−D2+Ud−D4−Ui=UC2+Ud−D2+Ud−D5−Ui.According to (17), add voltages across inductors, and the following formula is obtained:(19)UL1+UL2≈2Ui−Ud−D1.On the basis of voltage-second balances onL1 and L2, the following formula is obtained:(20)2Ui−Ud−D1D=UC1+Ud−D2+Ud−D4−Ui1−D=UC2+Ud−D2+Ud−D5−Ui1−D.The ratios of the voltages ofC1 and C2 to the input voltage Ui are obtained as follows:(21)UC1Ui|rD=1+D−DUd−D1/Ui−1−DUd−D2+Ud−D4/Ui1−D,(22)UC2Ui|rD=1+D−DUd−D1/Ui−1−DUd−D2+Ud−D5/Ui1−D.Combining the formulas (14), (21), and (22), the relationship between output and input voltages on the DS-HS converter can be deduced as follows:(23)UoUi|rD=UC1Ui|rD+UC2Ui|rD−Ud−D3Ui=21+D−2DUd−D1Ui−1−D2Ud−D2+Ud−D3Ui−1−DUd−D4+Ud−D5Vi11−D.Assuming that the voltage drops of all the diodes are equal, then we get the following formula:(24)Ud−D=Ud−D1=Ud−D2=Ud−D3=Ud−D4=Ud−D5.Thus, (23) can be re-expressed as follows:(25)UoUi|rD=21+D−5−3DUd−D/Ui1−D.Considering the different values ofUd − D/Ui and D, equation (25) is revealed in Figure 6(b), which indicates the effect of the diodes on the voltage gain. It can be observed that for higher values of Ud − D/Ui, the voltage gain will decrease. It indicates that the smaller the forward resistance and threshold voltage of the diodes, the better.


## 4.3. Effect of SwitchesS1 and S2 on Output Voltage

Since only the effect of switchesS1 and S2 is analyzed here, other parasitic parameters are neglected, i.e., rL = 0, rC = 0, rCo = 0, rD = 0, and UFD = 0.DuringTon, the voltages across inductors L1 and L2 are as follows:(26)UL1≈Ui−iS1rS−iS2rS,UL2≈Ui−iS1rS.DuringToff, the voltages at L1 and L2 are expressed as follows:(27)UL1+UL2≈UC1−Ui=UC2−Ui.According to (26), add voltages across L1 and L2, and the formula is obtained as follows:(28)UL1+UL2≈2Ui−2iS1rS−iS2rS.On the basis of voltage-second balances onL1 and L2, the following formula is obtained:(29)2Ui−2iS1rS−iS2rSD=UC1−Ui1−D=UC2−Ui1−D.The ratios of the voltages ofC1 and C2 to the input voltage Ui are as follows:(30)UC1Ui|rS=UC2Ui|rS=1+D−D2iS1rS+iS2rS/Ui1−D.Combining the formulas (14) and (30), the voltage gain of the DS-HS converter can be obtained as follows:(31)UoUi|rS=UC1Ui|rS+UC2Ui|rS−iS1rS+iS2rSUi=21+D−2D2iS1rS+iS2rS/Ui−1−DiS1rS+iS2rS/Ui1−D=21+D−1+3DiS1rS/Ui−1+DiS2rS/Ui1−D.Assume that the voltage drops on the switchesS1 and S2 are as follows:(32)Ud−S1=iS1rS,Ud−S2=iS2rS.Thus, (31) can be re-expressed as follows:(33)UoUi|rS=21+D−1+3DUd−S1/Ui−1+DUd−S2/Ui1−D.Assume thatUd−S=Ud−S1=Ud−S2. Thus, (33) is rewritten as follows:(34)UoUi|rS=21+D−21+2DUd−S/Ui1−D.By considering the different values ofUd − S/Ui and D, (34) is shown in Figure 6(c), and it also shows the relationship between the on-resistance of the switches and the voltage gain. It is observed that the higher the values of Ud − S, the lower the voltage gain. This fact indicates that the ON-state resistance of the switches should be as small as possible.


## 4.4. Effect of the CapacitorsC1, C2, and Co on Output Voltage

Considering the effect of ESR of capacitors C1, C2, andCo, other parasitic parameters are neglected, i.e., rL = 0, rD = 0, UFD = 0, and rS = 0.Considering the case mentioned above, duringTon, the voltages across the inductors L1 and L2 are expressed as follows:(35)UL1≈Ui,UL2≈Ui.Simultaneously,C1 and C2 are discharged to Co, and the output voltage is as follows:(36)Uoon=UC1+UC2−iC1onrC−iC2onrC=UCo+iCoonrCo.DuringToff, the voltages at L1 and L2 are expressed as follows:(37)UL1+UL2≈UC1+iC1offrC−Ui=UC2+iC2offrC−Ui.The capacitorCo is discharged through load Ro during t1 − t2, and the output voltage is as follows:(38)Uooff=UCo−iCooffrCo.According to (35), add voltages across inductors, and the following formula is obtained:(39)UL1+UL2≈2Ui.On the basis of voltage-second balances onL1 and L2, the following formula is obtained:(40)2UiD=UC1+iC1offrC−Ui1−D=UC2+iC2offrC−Ui1−D.The ratios of the voltage ofC1 and C2 to the input voltage Vi are shown as follows:(41)UC1Ui|rC=1+D−iC1offrC1−D/Ui1−D,(42)UC2Ui|rC=1+D−iC2offrC1−D/Ui1−D.Since the capacitor voltage cannot be changed suddenly, the voltages acrossC1, C2, and Co remain unchanged during the whole cycle. Therefore, the average value of the output voltage Uo in a whole period is as follows:(43)Uo=DUoon+1−DUooff=UCo.According to formulas (36), (38), (41), and (42), it can be obtained as follows:(44)UoUi|rC,rCo=UCoUi=UC1+UC2−iC1onrC−iC2onrC−iCoonrCoUi=21+D−iC1offrC1−D/Ui−iC2offrC1−D/Ui−iC1onrC1−D/Ui−iC2onrC1−D/Ui−iCoonrCo1−D/Ui1−D=21+D−iC1off+iC1onrC1−D/Ui−iC2off+iC2onrC1−D/Ui−iCoonrCo1−D/Ui1−D.The currents through the capacitorsC1 and C2 are as follows:(45)iCon=iC1on=iC2on,iCoff=iC1off=iC2off.Hence, the voltage gain is as follows:(46)UoUi|rC,rCo=21+D−iCoonrCo1−D/Ui−2iCoff+iConrC1−D/Ui1−D.Let us suppose the voltage drops due to ESR ofC1, C2, and Co are Ud − C and Ud − Co, then we get the following formula:(47)Ud−C=iCoff+iConrC,Ud−Co=iCoonrCo.Thus, (46) can be re-expressed as follows:(48)UoUi|rC,rCo=21+D−2Ud−C1−D/Ui−Ud−Co1−D/Ui1−D.Further, let us assume thatUd−C=Ud−Co. Thus, (48) is rewritten as follows:(49)UoUi|rC=21+D−3Ud−C1−D/Ui1−D.By considering the different values ofUd − C/Ui and D, equation (49) is shown in Figure 6(d), and it shows the effect of the ESR of the capacitors on voltage gain. It can be observed that for higher values of Ud − C/Ui, the voltage gain will decrease. This fact indicates that the ESR of the capacitor should be as small as possible.


## 4.5. Combined Effect of Nonidealities on Voltage Gain

By considering the nonideal effect of inductorsL1 and L2, diodes D1, D2, D3, D4, and D5, switches S1 and S2, and capacitors C1, C2, and Co, respectively, the voltage gain is expressed as follows:(50)UoUi≈21+D−4Ud−L/Ui−5−3DUd−D/Ui−21+2DUd−S/Ui−3Ud−C1−D/Ui1−D.


## 4.6. Efficiency Analysis

The proportional relationship between the inductor current and the output current is as follows:(51)IL=IL1=IL2=21−DIo=21−DUoRo.Considering thatPSW − S1 and PSW − S2 are the power losses on account of switching of S1 and S2, respectively, the total loss PSW during switching is as follows:(52)PSW=∑i=1,2PSW−Si=12TSIS1US1tr−S1+tf−S1+IS2US2tr−S2+tf−S2,where the rising and falling time of switches S1 and S2 are tr − S1, tf − S1 and tr − S2, tf − S2; IS1, US1 and IS2, US2 are the average current and voltage on S1 and S2.The core loss of the inductors is considered, so it can be shown as follows:(53)PFe=2KM′fmBacn,where Bacn is the operating magnetic position swing of the inductor core, M´ is the quality of the inductor core, and K, m, and n are the coefficients determined by the core material. The parameters can be found in the datasheet.The total power of the input and output are received as follows:(54)Pi=Ui2ILD+IL1−D+PSW+PFe,=2Ui1−DUoRo1+D+PSW+PFe,Po=Uo2Ro.According to (50)–(54), the efficiency of the DS-HS converter is obtained as follows:(55)η≈21+D−4Ud−L/Ui−5−3DUd−D/Ui−21+2DUd−S/Ui−3Ud−C1−D/Ui21+D+PSWRo1−D/UoUi+PFeRo1−D/UoUi.


## 5. Comparison of Converters

Many converters have recently been proposed to realize high voltage gain. The DS-HS converter is compared with the classical and recently proposed converters in this part. The detailed comparison is shown in Table2, including voltage gain, number of components, the position of the switch, the voltage and current stresses of switches and diodes, the average value and effective value of inductor current, and efficiency. It is obvious that the total number of components of the DS-HS converter is the same as the converter in [20]. The efficiency of the converter depends on several factors, including voltage and current ratings and their types.Table 2
The comparison of converters.
Boost [4]The converter in [13]The converter in [16]The converter in [17]Proposed converterC/I/D/S/T1/1/1/1/41/2/4/1/81/2/1/2/63/2/6/1/123/2/5/2/12Voltage gain1/1−D1+D/1−D1+D/1−D21+D/1−D21+D/1−DSwitch voltageUoUoG+1Uo/2GUo/2US1=G+2Uo/4GUS2=G−2Uo/4GDiode voltageUoUD1,3=G−1Uo/2GG+1Uo/GUD1,3=G−2Uo/4GVD1=G−2Uo/4GUD2=Uo/GUD2=Uo/GVD2=Uo/GUDo=UoUD4−6=Uo/2VD3−5=Uo/2The average value of inductor currentGIoG+1/2IoG+1/2IoG+2/2IoG+2/2IoRMS of inductor currentGIo2+1/12UiD/Lfs2G+1/2Io2+1/12UiD/Lfs2G+1/2Io2+1/12UiD/Lfs2G+2/2Io2+1/12UiD/Lfs2G+2/2Io2+1/12UiD/Lfs2Switch currentGIoG+1IoG+1/2IoG2+G−2/G−2IoIS1=G2+G−2/G−2IoIS2=G2+2G/2G−2IoDiode currentGIoID1−3,Do=G+1/2IoG+1/2IoID1−3=G+2/2IoID1−2=G+2/2IoID4−5=G+2/4IoID4−5=G+2/4IoID6=G+2/G−2IoID3=G+2/G−2IoCommon groundYesYesNoNoNoHigh/low side gate driverLowLowHigh/lowLowHigh/lowPower efficiency100 W40 W40W100 W100W88%90.2%92.7%94.31%96.15%The comparison of the voltage gain for converters is revealed in Figure7(a). From Figure 7(a), it can be seen that the DS-HS converter and the converter in [20] have higher voltage gain, compared with the converters in [4, 16, 19]. The average values of inductor currents for the converters are described in Figure 7(b), which reflect the relationship between the voltage gain G and the ratio of average inductor current to output current IL/Io. From Figure 7(b), it is evident that IL/Io of the DS-HS converter and the converter in [20] is slightly higher than that of the converters in [16, 19] but much lower than the boost converter in [4]. The figures of normalized current stress on switches and diodes are incarnated in Figures 8(a) and 8(b). The comparison chart of total current stress on switches and diodes for converter topologies is shown in Figure 8(c), and the comparison chart of total current stress per component is revealed in Figure 8(d). The comparison between the total current stress of the converters is as follows:(56)3G+12Io︸19<2GIo︸Boost4<3G+1Io︸16<3G+2Io+2G+2G−2Io︸20<3G+2Io+3G+2G−2Io︸Proposed.Figure 7
Comparison. (a) Voltage gain G versus duty cycle D. (b) The ratio of inductor currentIL to output current Io versus duty cycle D. Note: A represents boost converter [4], B represents SIBC [16], C represents converter [19], D represents converter [20], and E represents the proposed DS-HS converter.
(a)(b)Figure 8
Comparison of current. (a) Switch currents, (b) diode currents, (c) ΣISD/Io versus voltage gain G, and (d) ΣISD/NIo versus voltage gain G. Note: X(Z) means the switch or diode of converter X, ΣX(Z) are total current of switches or diodes for converter X, and ΣISD are total current stress of switches and diodes.
(a)(b)(c)(d)The relationship between the total current stress averaged to each element is shown as follows:(57)G+12Io︸19<3G+1Io5︸16<GIo︸Boost43G+2Io+2G+2/G−2Io7︸20<3G+2Io+3G+2/G−2Io7︸Proposed.Generally speaking, the cost of components increases parabolically with component ratings. A high rating means high cost and high on-resistance. The relationship of total voltage stresses for converters is as follows:(58)2GUi︸Boost4<2G+1Ui︸19<9G+24Ui︸Proposed<5G2Ui︸20<3GUi︸16.The total voltage stress of each component is received as follows:(59)9G+228Ui︸Proposed<5G14Ui︸20<2G+1Ui3︸19<3GUi5︸16<GUi︸Boost4.The figures of normalized voltage stress on switches and diodes are reflected in Figures9(a) and 9(b), respectively. The comparison chart of total current stress for converters is shown in Figure 9(c), and the comparison chart of total current stress per component is also shown in Figure 9(c). According to (59), on average for each component, the proposed DS-HS converter has lower voltage stress than the converters in [4, 16, 19, 20].Figure 9
Comparison of voltage. (a) Switch voltages, (b) diode voltages, and (c) ΣUSD/Ui and ΣUSD/NUi versus voltage gain G. Note: X(Z) means the switch or diode of converter X, ΣX(Z) are total voltage of switches or diodes for converter X, and ΣVSD are total voltage stress of switches and diodes.
(a)(b)(c)Half of the total output voltage for the proposed DS-HS converter is shared by two switches. Then, low voltage rating switches can be used to design DS-HS converters. In general, as the rating of any device increases, its on-resistance increases. It can be seen that the DS-HS converter requires lower rating components. The efficiency of the classical boost converter [4] and suggested converters in [16, 19, 20] are 88%, 90.2%, 92.7%, and 94.31%, respectively, and that of the DS-HS converter is 96.15%. Therefore, the proposed DS-HS converter has higher efficiency compared with converters in [4, 16, 19, 20].By comparing with the converter in [20], the DS-HS converter has the same number of components, and the difference in components is just one more switch and one less diode. Therefore, the difference in loss is derived in detail as shown in the following figure.The total switching losses of the converter in [20] and the proposed DS-HS converter are shown as follows:(60)PSD20=ES+ED1+ED2+ED3+ED4+ED5+ED6fs,PSDDS−HS=ES1+ES2+ED1+ED2+ED3+ED4+ED5fs,where E represents the energy loss during the switching process, and its subscript represents the components. The difference value between the switching loss of the DS-HS converter and the converter in [20] is shown as follows:(61)PSDDS−HS−PSD20=Eon,S1+Eoff,S1+Eon,S2+Eoff,S2fs−Eon,S+Eoff,S+Eon,D3+Eoff,D3fs,where Eon and Eoff represent the switching energy loss of turn-on and turn-off. Through solving (61), the following formula is obtained:(62)PSDDS−HS−PSDD=US1IS1+US2IS2−USIStr+tffs−ED3fs,where tr and tf represent rise time and fall time. According to the formula (62), the final difference value between the switching losses is as follows:(63)PSDDS−HS−PSDD=−G−24GDUoILtr+tffs−ED3fs<0,G≥2.The solution of (63) is always negative, when the voltage gain G is greater than 2.Therefore, it can be concluded that the switching loss of the DS-HS converter is less than the converter in [20]. According to the above analysis, the DS-HS converter provides a feasible method to achieve high voltage gain, reduce voltage stress, and improve efficiency.


## 6. Design Criteria of Component Parameters

The parameter design criteria for inductors and capacitors are given as follows.When the DS-HS converter operates at the boundary (BCM) between the CCM and DCM modes, the relationship between the average inductor current and the minimum load currentIoG is as follows:(64)IL1=IL2=2DIoG1−D.For a given application, if the maximum allowable value for the inductor current ripple is ∆ILmax, then we get the following formula:(65)ΔILmax=KiIL1=KiIL2.For the relationship of ΔIL1 ≤ ΔIL1max and ΔIL2 ≤ ΔIL2max, the minimum inductance of L1 and L2 is as follows:(66)L1min=L2min=D1−DUi2fsKiIoG,where fs=1/Ts, and Ki is the proportional coefficient.In order to ensure that the DS-HS converter works in CCM, the following inequality needs to be satisfied:(67)IL1≥12ΔiL1,IL2≥12ΔiL2,ΔIL1 and ΔIL2 in the formula are the inductor current ripples, and ΔiL1=Ui/L1DTs,ΔiL2=Ui/L2DTs.Substituting formula (64) into (67), the following formula is obtained:(68)L1fsRo=L2fsRo≥D1−D281+D.The normalized inductor time constantτ is as follows:(69)τ=L1fsRo=L2fsRo.By combining equations (68) and (69), the boundary functions of the DS-HS converter working in CCM and DCM can be obtained as follows:(70)τ≥D1−D281+D.The boundary conditions of the HS-LC converter are shown in Figure10. From Figure 10, it can be seen that when τ is below the solid line, the circuit works in DCM, and when τ is above the solid line, the circuit works in CCM.Figure 10
Boundary condition of the HS-LC converter.Simplifying formula (68), the relationship of Ro can be obtained as follows:(71)Ro≤8L1fs1+DD1−D2=8L1fs1+DD1−D2.According to formula (71), it can be known that the value of the load Ro also determines whether the circuit works in CCM or DCM.The minimum capacitance formula is as follows:(72)C1min=C2min=DUoΔUC1maxRofs=DUoΔUC2maxRofs,ΔVC1 and ΔVC2 are the voltage ripples of the capacitors, and ΔVC1max and ΔVC2max are the maximum allowable values of ΔVC1 and ΔVC2, respectively.The minimum value of the output capacitor is as follows:(73)Comin=1−DUoΔUComaxRofs,where ΔVComax is the maximum allowable value of ΔVCo, and ΔVCo is the voltage ripple of the output capacitor.


## 7. Small Signal Modeling and Control Scheme

Figure11 shows the voltage loop control scheme of the DS-HS converter. The most important part of closed-loop control is the design of the compensation network, and the design of the compensation network requires a small signal model as shown in the following figure.Figure 11
Voltage loop control scheme of the DS-HS converter.Assuming that the inductance and capacitance are large enough, the small-signal model can be obtained using the state-space averaging method.Ui(t), Uo(t), and d(t) are input variable, output variable, and control variable, respectively. iL1(t), iL2(t), UC1(t), UC2(t), and UCo(t) are state variables. The equivalent series resistance of capacitors C1 and C2 is r. When switches S1 and S2 are turned on, the state space average model can be obtained as follows:(74)diL1tdtdiL2tdtdUC1tdtdUC2tdtdUCotdt=00000000000012rC112rC1−12rC10012rC212rC2−12rC200−12rCo−12rCo12rCo+1RoCoiL1tiL2tUC1tUC2tUCot+1L11L2000Uit,Uot=00001iL1tiL2tUC1tUC2tUCotT.WhenS1 and S2 are turned off, the state space average model can be written as follows:(75)diL1tdtdiL2tdtdUC1tdtdUC2tdtdUCotdt=−r4L10−12L100−r4L20−12L200−12C10000−12C2000000001RoCoiL1tiL2tUC1tUC2tUCot+12L112L2000Uit,Uot=00001iL1tiL2tUC1tUC2tUCotT.Combining (74) and (75), the average model of the DS-HS converter can be obtained as follows:(76)diL1tdtdiL2tdtdUC1tdtdUC2tdtdUCotdt=r1−dt4L10−1−dt2L100r1−dt4L20−1−dt2L200−1−dt2C10dt2rC1dt2rC1−dt2rC1−1−dt2C20dt2rC2dt2rC2−dt2rC200−12rCo−12rCo12rCo+1RoCoiL1tiL2tUC1tUC2tUCot+1+dt2L11+dt2L2000Uit,Uot=00001iL1tiL2tUC1tUC2tUCotΤ.State variables, input variables, output variables, and control variables can be described as follows:(77)iL1t=IL1+i^L1t,iL2t=IL2+i^L2t,UC1t=UC1+U^C1t,UC2t=UC2+U^C2t,UCot=UCo,+U^Cot,Uot=Uo+U^ot,Uit=Ui+U^it,dt=D+d^t,where IL1, IL2, UC1, UC2, UCo, Ui, and D are the steady-state components; i^L1t, i^L2t, U^C1t, U^C2t, U^Cot, U^it, d^t, and U^ot are the small-signal disturbance variables.Combining equations (76) and (77), the small-signal model of the converter can be written as follows:(78)di^L1tdi^L2tdU^C1tdU^C2tdU^Cot=−r1−D4L10−1−D2L100−r1−D4L20−1−D2L200−1−D2C10D2rC1D2rC1−D2rC1−1−D2C20D2rC2D2rC2−D2rC200−D2rCo−D2rCoD2rCo+1RoCoi^L1ti^L2tU^C1tU^C2tU^Cot+12L112L2000Uid^t+DL1+1−D2L1DL2+1−D2L2000U^it+r4L1012L100r4L2012L20012C1012rC112rC1−12rC112C2012rC212rC2−12rC200−12rCo−12rCo12rCoIL1IL2UC1UC2UCod^t,U^ot=00001i^L1ti^L2tU^C1tU^C2tU^CotT.


## 8. Simulation Results

In order to verify the correctness of the DS-HS converter, a simulation is carried out. The design index and component parameters are shown in Table3, with an output power of 100 W, an input voltage of 25 V–45 V, and an output voltage of 380 V.Table 3
The design index and component parameters.
ComponentsParameterOutput powerPo100 WOutput voltageVo380 VInput voltageVi25 Vfs(frequency)80 kHzL1, L2(inductors)320μHC1, C2(capacitors)6.8μFS1, S2(MOSFET)IRFP260 ND2(diodes)V50100PD1(diodes)MBR40200PTD3, D4, and D5(diodes)SBR20A300CTCo(out capacitor)680μF/450VWhen the input voltage is 25 V and the output voltage is 380 V, the simulation waveforms are shown in Figure12. The drive signal of the switches S1 and S2, output voltage, and the voltage stress of the diode D5 are shown in Figure 12(a). The voltage stresses of the diodes D1–D4 are shown in Figure 12(b). From Figures 12(a) and 12(b), it is obvious that the output voltage is 380 V, and the voltage stresses of the diodes D3, D4, and D5 are half of the output voltage, 190 V. The voltage stress of D1 is about 82.5 V, and the voltage stress of D2 is equal to the input voltage, which is about 25 V. The voltage stresses of S1 and S2 and the sum of the voltage stresses of S1 and S2 are shown in Figure 12(c). The current stress of the inductor current is shown in Figure 12(d), and the average currents of L1 and L2 are 2.26 A.Figure 12
Simulation results whenVi = 25 V. (a) UPWM, Uo, and UD5, (b) UD4, UD3, UD2, and UD1, (c) US2, US1, and US2 + US1, and (d) currents of L1 and L2.
(a)(b)(c)(d)When the input voltage is 45 V and the output voltage is 380 V, the simulation waveforms are shown in Figure13. The drive signal of the switches S1 and S2, output voltage, and the voltage stress of the diode D5 are shown in Figure 13(a). The voltage stresses of the diodes D1–D4 are shown in Figure 13(b), then the voltage stresses of S1 and S2 and the sum of the voltage stresses of S1 and S2 are shown in Figure 13(c). The current stress of the inductor current is shown in Figure 13(d), and the average currents of L1 and L2 are 1.37 A.Figure 13
Simulation results whenVi = 45 V. (a) UPWM, Uo, and UD5, (b) UD4, UD3, UD2, and UD1, (c) US2, US1, and US2 + US1, and (d) currents of L1 and L2.
(a)(b)(c)(d)


## 9. Experimental Results

For the sake of verifying the correctness of the above analysis for the DS-HS converter, the experimental prototype of the DS-HS converter is built, shown in Figure14(a), composed of a power supply, DSP, oscilloscope, and DS-HS converter. The enlarged figure of the DS-HS converter is shown in Figure 14(b), which consists of inductors, capacitors, switches and diodes, and so on.Figure 14
The DS-HS converter. (a) The experimental prototype and (b) the enlarged figure.
(a)(b)When the input voltage of the DS-HS converter is 25 V and the output voltage is 380 V, the experimental results are shown in Figure15. The drive signal of the switches S1 and S2 for the DS-HS converter is shown in Figure 15(a). The output voltage and the voltage stress of diode D5 are shown in Figure 15(b), and the voltage stresses of the diodes D3 and D4 are shown in Figure 15(c). From Figures 15(b) and 15(c), it is obvious that the output voltage is 380 V, and the voltage stresses of the diodes D3, D4, and D5 are half of the output voltage, 190 V. The voltage stresses of the diodes D1 and D2 are revealed in Figure 15(d). The voltage stress of D1 is about 82.5 V, and the voltage stress of D2 is equal to the input voltage, which is about 25 V. The voltage stresses of S1 and S2 are shown in Figure 15(e), and the sum of the voltage stresses of S1 and S2 is shown in Figure 15(f), which is half of the output voltage, 190 V. The current stress of the inductor current is shown in Figure 15(g), and the average currents of L1 and L2 are 2.3 A and 2.3 A.Figure 15
Experimental results whenUi = 25 V. (a) Drive signal of S1, S2, (b) Uo and UD5, (c) UD4 and UD3, (d) UD1 and UD2, (e) US2 and US1, (f) US2 + US1, and (g) currents of L1 and L2.
(a)(b)(c)(d)(e)(f)(g)When the input voltage of the DS-HS converter is 45 V and the output voltage is 380 V, the experimental results are shown in Figure16. The driving signal of switches S1 and S2 is shown in Figure 16(a), and the output voltage and the voltage of D5 are shown in Figure 16(b). The voltage stresses of D3, D4, D1, and D2 are shown in Figures 16(c) and 16(d). The voltage stresses of S1 and S2 are shown in Figure 16(e), and the sum of the voltage stresses of S1 and S2 is shown in Figure 16(f), which is half of the output voltage, 190 V. The current of inductors L1 and L2 is shown in Figure 16(g), and the average currents of L1 and L2 are about 1.33 A and 1.33 A.Figure 16
Experimental results whenUi = 45 V. (a) Drive signal of S1, S2, (b) Uo and UD5, (c) UD4 and UD3, (d) UD1 and UD2, (e) US2 and US1, (f) US2 + US1, and (g) currents of L1 and L2.
(a)(b)(c)(d)(e)(f)(g)As shown in Figure17(a), when the input voltage of the DS-HS converter changes from 25 V to 45 V, the output voltage remains around 380 V, and the DS-HS converter can achieve a gain range from 8.4 to 15.2. As shown in Figure 17(b), when the input voltage of the HS-LC converter drops from 45 V to 25 V, the output voltage remains around 380 V, and the DS-HS converter can achieve a gain range from 15.2 to 8.4.Figure 17
The waveforms ofUo, when Ui changes. (a) Ui changes from 25 V to 45 V, (b) Ui changes from 45 V to 25 V.
(a)(b)The efficiency of the DS-HS converter is shown in Figure18, when Ui = 25 V. It can be seen from Figure 18 that the efficiency of the DS-HS converter increases as the power increases, and the efficiency can reach up to 96.15%. In addition, the DS-HS converter also has some limitations. The input and output do not share the same ground, which will cause an electromagnetic interference problem. Because the DS-HS converter does not use soft switching, voltage and current spikes will be generated which results in power loss when the switch is switched.Figure 18
The efficiency of the DS-HS converter, whenUi = 25 V.


## 10. Conclusion

The improved switching-inductor unit and new step-up DC-DC converters with reduced switch voltage stress are proposed. Through filtering of characteristics, the DS-HS converter is selected from the proposed converters. The voltage gain of the DS-HS converter in CCM, the nonideal effects of components, and the efficiency analysis are analyzed. The design criteria for components and small signal modeling and control are given. By the comparison of the existing converters, it can be shown that the DS-HS converter has lower voltage stress, higher voltage gain, and higher efficiency. The actual circuit of the DS-HS converter is built to verify the correctness of the theory. The simulation and experimental results of the DS-HS converter are presented, and the efficiency can reach 96.15%.



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*Source: 1870727-2022-09-27.xml*