# Design and Characterization of the Next Generation Nanowire Amplifiers

Authors: Sotoudeh Hamedi-Hagh; Ahmet Bindal
Journal: VLSI Design
 (2008)

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## Abstract

Vertical nanowire surrounding gate field effect transistors (SGFETs) provide full gate control over the channel to eliminate short-channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10 nm channel length and a 2 nm channel radius. The amplifier dissipates 5μW power and provides 5 THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5 V, and a distortion better than 3% from a 1.8 V power supply and a 20 aF capacitive load. The 2nd- and 3rd-order harmonic distortions of the amplifier are −40 dBm and −52 dBm, respectively, and the 3rd-order intermodulation is −24 dBm for a two-tone input signal with 10 mV amplitude and 10 GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high-speed analog and VLSI technologies.


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## Body

## 1. Introduction

The speed of silicon integrated circuits is reaching
beyond 100 GHz to enable wireless communications with wideband channels [1].
Even though the current VLSI technology has approached to its scaling limits
necessitating a replacement technology, silicon-based devices are still favored
to realize large-scale circuits and systems because of their low cost.Downscaling of the bulk metal oxide semiconductor
field effect transistors (MOSFETs) to nanometer dimensions has increased the leakage current and short-channel
effects. Therefore, alternative silicon compatible transistor devices such as silicon
on insulator (SOI) MOSFETs, FinFETs, and nanotube FETs have been investigated
for improved performance [2].Vertical surrounding gate field effect transistors (SGFETs)
have full gate control around channel and have minimized short-channel effects [3].
The elimination of bulk in these transistors reduces latchup and substrate
noise. The layout views of a vertical nanowire SGFET and a planar bulk MOSFET
are shown in Figure 1
for comparison. Both transistors have identical channel widths of 13 nm and
channel lengths of 10 nm and are designed with similar layout design rules. The
area of the vertical transistor is (40 nm × 40 nm) 1600 nm2, and the area
of the planar transistor is also 1600 nm2 (76 nm × 21 nm) with body
contact.Layout views of (a) vertical nanowire
SGFET and (b) planar bulk MOSFET.
(a)(b)


## 2. High-Frequency Modeling

The three-dimensional view and the corresponding parasitic components of the
vertical nanowire SGFET are shown in
Figure2. Only, the dominant parasitics are considered to simplify the circuit model.Figure 2
The 3D view of nanowire transistor.The intrinsic transistorM is modeled using
a BSIM-SOI compatible model to ensure that all the input and output transfer
characteristics of the circuit and device simulators match each other. The
parasitic capacitance between the source contacts and the metal gate is denoted
as Cgs2 in the figure. The parasitic capacitance, Cgs1, between
the metal gate and the concentric source makes contact, and the junction well is the
largest dominant capacitor of the SGFET device. The gate and drain capacitors
(Cgd1 and Cgd2) and the drain and source capacitors (Cds1 and Cds2) can be lumped into Cgd and Cds,
respectively. Compared to planar bulk transistors, Cgd is very small
and there is no junction to bulk capacitance, therefore, Cds is quite
linear. The well resistance, Rs, can be quite large and is the major
drawback of the vertical SGFETs compared with planar transistors. The magnitude
of this resistance can be reduced drastically by placing a concentric (ring
shape) source contact in parallel with the well, as shown in the figure.The simplified parasitic components
associated with NMOS and PMOS SGFETs are shown in Figures3(a) and 3(b). For
accurate circuit level simulations, the intrinsic SGFETs (Mn and Mp)
are modeled using BSIM-SOI.Simplified parasitic components
of (a) NMOS and (b) PMOS SGFETs.
(a)(b)For simplified hand calculations and
finding the AC parameters of the amplifiers, designed using SGFETs, the
linearized small-signal model shown in Figure4 can be used. Using this model
at low frequencies, the DC voltage gain and output resistance of various
amplifier stages can be calculated. The model shown in Figure 4 is valid for transistors
biased in the active operating region, and transistor models in triode or
cutoff regions can be easily constructed from this model by minor modifications.Figure 4
Linearized
small-signal model of SGFET.


## 3. Differential-Pair Amplifier

The full gate control and the low leakage current of
SGFETs make them suitable for many digital applications [4].
Operational amplifiers are one of the most important building blocks of analog
integrated circuits, and differential-pair amplifiers are the input building
blocks of any opamp, as shown in Figure 5.
Therefore, the performance of a differential-pair amplifier, designed using
SGFETs, needs to be measured before designing an opamp and will be investigated
in this work. We design the input transistors of the differential pair
amplifier using PMOS transistors to enable realizing the Miller stage using
NMOS transistors and achieving higher gains.Figure 5
Schematic of a differential pair amplifier.The low-frequency small signal model of the
differential pair amplifier designed using SGFETs is shown in Figure6.Figure 6
The low-frequency small signal model
of the differential pair amplifier.The layout of the differential pair
amplifier realized using 3 metallization layers is presented in Figure7. All
interconnect parasitics are extracted and added to the amplifier netlist for
postlayout simulations.Figure 7
Layout of the differential pair amplifier.The resistorR3 is given by (1)R3=Rs3+(rds3∣1gm3). The voltage gain of the differential pair
amplifier is given by
(2)VoutVin=gm2rds2+rds2(gm2+Gs2)/rds5Gs21−U1/U2. where U1 denotes gm2rds2[rds1(gm1+Gs1)+Gs1(Rs3+rds3/(1+gm3rds3))] and U2 denotes gm1rds1Gs1Gs4rds4(Rs3+rds3/(1+gm3rds3)).ForGs≫gm≫gds,
the voltage gain is approximately given by (3)VoutVin≈gm2rds2.ForGs≫gm≫gds,
the output resistance is approximately given by
(4)Rout≈[rds2(1+gm2gm1)]∣rds4.The main transistors of the input
differential pair amplifier are realized by parallel combination of two p-type
SGFETs to ensure a large transconductance. The width of the metal interconnects
is selected to be
14 nm to reduce their resistivity, and four parallel vias are used to connect
metal-2 and metal-3 layers to minimize the signal loss. Each via with 4 nm× 4 nm dimension and
36 nm height has a resistance of 400 Ω. Overlap capacitance between metal-1 and
metal-2 routing interconnects is 0.2 aF for 14 nm × 14 nm dimension and 36 nm height. The layout area
of the differential pair amplifier is x=136 nm and y=190 nm.


## 4. Postlayout Characteristics

The transient and frequency responses of
the SGFET differential pair amplifier are shown in Figure8. The amplifier
provides a gain of 16 with the first pole located at 100 GHz and the second pole
located at 100 THz. To attain high accuracy in the transfer functions of various
analog circuits such as switch capacitor filters and amplifiers, it might be
necessary to cascade multiple stages in nested Miller architectures and achieve
a voltage gain higher than 1000.Frequency and transient responses of the differential pair
amplifier.
(a)(b)(c)(d)The spectrum of the output waveform of the amplifier
is given in Figure9. It has very good linearity characteristics, and the total
harmonic distortions of the amplifier are only 3% for ±233 mV output swing. Such
a high linearity is due to the source resistance, Rs, acting as the degeneration resistance
and minimizing the harmonic distortions of input differential pair transistors.Figure 9
Spectrum of the output transient waveform.The postlayout characteristics of the opamp
are listed in Table1. The good performance of the SGFET amplifier indicates
that these transistors are good choices for future integration of high-speed
and low-power analog and mixed signal circuits.Table 1
Postlayout characteristics of the differential pair amplifier.
Supply voltage1.8 VMaximum output linear signal swing0.5 VInput DC voltage level0.6 VVoltage gain (at 1 GHz)16Phase margin>90°Unity voltage gain cutoff frequency5.1 THzThird-order intermodulation distortion (10 mV two-tone signals with 1 GHz spacing)−24 dBmSecond-order harmonic distortion−40 dBmThird-order harmonic distortion−52 dBmTotal harmonic distortion3%Load capacitor20 aFPower dissipation5μWArea136 nm× 190 nm


## 5. Conclusions

The design and characteristics of a
differential pair amplifier designed using
nanowire SGFETs and having channel
length of 10 nm and channel radius of 2 nm were presented. The amplifier
dissipates 5μW power and provides 5 THz bandwidth with a voltage gain of 16 and
a distortion better than 3%. All these parameters indicate that vertical
nanowire SGFETs are promising candidates for realizing next generation high-speed
analog integrated circuits.



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*Source: 190315-2009-02-03.xml*