# Device Performance of Double-Gate Schottky-Barrier Graphene Nanoribbon Field-Effect Transistors with Physical Scaling

Authors: Mu Wen Chuan; Muhammad Amirul Irfan Misnon; Nurul Ezaila Alias; Michael Loong Peng Tan
Journal: Journal of Nanotechnology
 (2023)

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## Abstract

Moore’s law is approaching its limit due to various challenges, especially the size limit of the transistors. The International Roadmap for Devices and Systems (IRDS), the successor of International Technology Roadmap for Semiconductors (ITRS), has included 2D materials as an alternative approach for the More-than-Moore nanoelectronic applications. Among the 2D materials, graphene nanoribbons (GNRs) have been widely used as the alternative channel materials of field-effect transistors (FETs). In this paper, the impacts of physical scaling on the device performance of double-gate Schottky-barrier GNR FETs (DG-SB-GNRFETs) are investigated by using NanoTCAD ViDES simulation tool based on the tight-binding Hamiltonian and self-consistent solutions of 3D Poisson and Schrödinger equations with open boundary conditions within the nonequilibrium Green’s function formalism. The extracted device performance parameters include the subthreshold swing and on-to-off current ratio. The results suggest that the performances of DG-SB-GNRFETs are strongly dependent on their physical parameters, especially the widths of the GNRs.


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## Body

## 1. Introduction

Over the last few decades, the continuous scaling of transistors, as described by Moore’s law, has resulted in astonishing innovations, especially in the semiconductor industry. According to Moore’s law, the number of transistors in an integrated circuit would be doubled every 2 years [1]. However, the scaling of silicon (Si) complementary metal-oxide-semiconductor (CMOS) technology is expected to face its fundamental limit as it enters the sub-10 nm scaling regime [2, 3]. To leverage these shortcomings, various innovations involving field-effect transistors (FETs), such as the tunnelling FETs (TFETs) [4], nanowire FETs (NWFETs) [5], multibridge-channel FETs (MBCFETs) [6], and two-dimensional (2D) FETs, have been actively developed and studied. Interestingly, 2D material-based FETs have been listed as the potential candidates for further transistor miniaturisation in the International Roadmap for Devices and Systems (IRDS) [7]. Among the potential 2D material candidates, graphene has attracted outstanding research interests among researchers since its introduction by Novoselov et al. [8].Graphene possesses unique electronic and mechanical properties, but its gapless properties inhibit its application in FETs for switching applications (which typically require a band gap value between 0.1 eV and 3.0 eV [9]). Nevertheless, the band gap of graphene can be engineered by simply limiting its width, inducing the lateral confinement within its finite width and producing graphene nanoribbons (GNRs) [10, 11]. Theoretical works show that Armchair GNRs (AGNRs) have energy gap values which are inversely proportional to their widths. These widths can be classified into three families: the 3p group (with semiconducting properties), the 3p + 1 group (with semiconducting properties), and the 3p + 2 group (with metallic properties) [12]. The bandgap of the channel materials of FETs are crucial in the design of nanoelectronic devices [13].Graphene is a 2D monolayer of carbon atoms constructed in the form of 2D honeycomb lattice. As a potential candidate for More-than-Moore CMOS technology, graphene offers several advantages such as high mobility for electron transport, high carrier velocity for fast switching, monolayer thin body for optimum scaling, and excellent thermal conductivity [14]. The band gap tuning of gapless graphene can be achieved by tailoring it into GNRs, enabling its application as digital switching devices, namely the GNRFETs [15, 16]. Careful selection of physical parameters of GNRFETs must be performed because the device performances of GNRFETs are strongly dependent on their widths. Previous studies showed that the carefully designed GNRFETs can have comparable current-voltage (I–V) characteristics as compared to silicon-based FETs [17]. In addition to the band gaps of the channel materials, the metal contacts in FETs are also important. Upon connection with metal contacts, Schottky-barrier (SB) is formed at the intersections between the GNR channel material and the contact metals [18]. Therefore, studying merely the electron transport properties within the GNR-based FET channels is insufficient to predict the overall performance of the GNR FETs.In this paper, the simulation of double-gate SB-GNRFETs (DG-SB-GNRFETs) is performed using NanoTCAD ViDES simulation tool [15, 16, 19]. Figure 1 shows the schematic structure of the SB-GNR-FET used in this work. Subsequently, the effects of physical scaling to the device performance of DG-SB-GNRFETs are also investigated. The remaining sections of this paper are organised as follows: Section 2 shows the theoretical equations employed in the NanoTCAD ViDES simulation tool [15, 16]. Section 3 compiles the results and discussions of this work. Conclusion of this study is drawn in Section 4.Figure 1
Schematic structure of the SB-GNR-FET used in the simulation [19].


## 2. Simulation Procedures

The performance of GNRFETs can be evaluated by using different carrier transport models such as simplified semiclassical transport model or quantum transport model. However, simplified semiclassical transport model does not treat quantum tunnelling effect and electrostatic short channel effect, making it difficult to explore the behaviour of GNRFETs due to physical scaling [20]. The quantum-based transport simulation approach is more efficient and accurate than that of other method. The NanoTCAD ViDES simulation tool performs the calculations based on the tight-binding Hamiltonian and self-consistent solutions of 3-D Poisson and Schrödinger equations with open boundary conditions within the nonequilibrium Green’s function formalism [15, 16]. Non-equilibrium Green’s function formalism (NEGF) formalism provides the atomistic description of the channel material, producing relatively accurate results in investigating the performance of GNRFETs in the sub-10 nm channel length regime [21]. Green’s function [15, 16] can be expressed as follows:(1)GE=EI−H−∑s−∑D−1,where E is the energy, I the identity matrix, H is the Hamiltonian of GNR, and ∑s and ∑D are the self-energies of the source and drain. In this simulation tool, the transport is assumed to be completely ballistic and the type of graphene nanoribbon is armchair. This model assumes that the chemical potential of reservoirs is aligned at the equilibrium with Fermi energy level of the GNR channel. Given that there are no fully confined state, the electrons and holes concentration equations [15, 16] are expressed as follows:(2)nr⟶=2∫Et+∞dEψsE,r⟶2fE−EFS+ψDE,r⟶2fE−EFD,(3)pr⟶=2∫−∞EtdEψsE,r⟶21−fE−EFS+ψDE,r⟶21−fE−EFD,where r⟶ represents the coordinate of the carbon atoms, f is the Fermi–Dirac occupation factor, and ψS2 and ψD2 are the probability of the states injected by the source and drain, respectively. EFS and EFD are the Fermi energy levels at the source and drain, respectively. Following that, the output current of DG-SB-GNRFETs [15, 16] are then simulated by using the following formula:(4)I=2qh∫−∞+∞dETEfE−EFS−fE−EFD,where TE is the transmission coefficient, q is the electron charge, and h is Plank’s constant. In addition, the widths of the AGNRs with NA dimers of carbon atoms are calculated by using the following formula:(5)W=NA−132ac−c,where ac−c=0.142nm is the carbon-carbon bond length. To better illustrate the model in this work, Figure 2 shows the 3D structure of the SB-GNR-FET.Figure 2
3D structure of the SB-GNR-FET [19].


## 3. Results and Discussion

In this work, the DG-SB-GNRFETs are simulated with the scaling physical parameter, including the channel length (LC), the gate oxide thickness (tOX), and width of GNRs (W). For all the simulations in this work, the temperature and dielectric constant are fixed to T=300K (ambient temperature) and εr=3.9, respectively. Table 1 shows the values that are used in the simulation of DG-SB-GNRFETs, whereas the physical parameters are shown in Figure 1.Table 1
Physical device structure of DG-SB-GNRFETs.
Physical parametersSimulation 1Simulation 2Simulation 3Channel length,LC (nm)7, 10, 141010Oxide thickness,tOX (nm)1.01.01.0, 2.0, 3.0Dimers of carbon atoms,NA99, 12, 159GNR width,W (nm)0.980.98, 1.35, 1.720.98Lateral space,S (nm)1.01.01.0For simulation 1, the channel length (LC) of DG-SB-GNRFETs is manipulated while fixing other physical parameters. For simulation 2 and simulation 3, the manipulated variables are the width of GNR channels (W) and gate oxide thickness (tOX), respectively. All simulation results are analysed by extracting the on-to-off current (ION/IOFF) ratio and subthreshold swing (SS) from I–V characteristics as shown in [22]. The ION/IOFF ratio is one of the important parameter performances of this device that is related to the short channel effect and leakage current, whereas SS is an important measure of the performance for switching operation in FET devices. Figure 3 shows the I–V characteristics of DG-SB-GNRFETs with the width of W=0.98nm (NA=9), with their channel length scaled, at low (VD=0.1V) and high (VD=0.3V) drain voltages. Based on the I–V characteristics obtained, it is clearly shown that the IOFF for VD=0.3V is generally higher than that for VD=0.1V.Figure 3
I–V characteristics of SB-GNR-FETs with different channel lengths: (a)LC=7nm, (b) LC=10nm, and (c) LC=14nm, simulated at low and high drain voltages.
(a)(b)(c)In Figure3, the I–V characteristics do not show significant difference for different channel length. Theoretically, scaling down the channel length of transistor will be resulting the short channel effect on the transistor and therefore leading to current leakage. However, the ION/IOFF ratio and SS do not show significant changes when the channel lengths of SB-GNR-FETs are scaled down from 14nm to 7nm, where only slight decimal points differences can be observed. This condition is observed due to the ballistic transport [23] assumption employed in the NanoTCAD ViDES simulation tool. Table 2 summarises the results of device performance of the SB-GNR-FETs with respect to channel length scaling. The device metrics summary clearly shows that the performances of SB-GNR-FETs are severely degraded at high drain biasing voltage. This observation has also been observed in the previous study on SB-GNR-FETs [15]. Therefore, the subsequent simulations are carried out at low drain voltage, that is Vd=0.10V.Table 2
Device performance of SB-GNR-FETs with channel length scaling.
Device metricsVd=0.10VVd=0.30VLC=7nmLC=10nmLC=14nmLC=7nmLC=10nmLC=14nmOn-current,ION (A)7.47×10−67.52×10−67.53×10−61.52×10−51.56×10−51.61×10−5Off-current,IOFF (A)6.11×10−106.11×10−106.11×10−102.55×10−62.61×10−62.67×10−6ION/IOFF ratio1.22×1041.23×1041.23×1045.96×1005.98×1006.03×100SS (mV/dec)73.272.072.53127.9125.8125.7Figure4 shows the I–V characteristics of SB-GNR-FETs with GNR width scaling. From the I–V characteristics in Figure 4, SB-GNR-FET with W=1.72nm has higher off-current compared to the SB-GNR-FET with W=0.98nm. This shows that the scaling of GNR width significantly affects the ION/IOFF ratio due to the altered band gap values. In other words, increasing the GNR width reduces the band gap, and hence, increasing the tendency of band-to-band tunnelling and smaller Schottky-barrier height. Moreover, the SS of SB-GNR-FETs is also degraded significantly when the width is increased to W=1.35nm and W=1.72nm, while the SB-GNR-FET with W=0.98nm possesses SS value of 72mV/dec, which is close to the ideal room temperature limit (SS = 60mV/dec). Table 3 shows the summarised device metrics of SB-GNR-FETs with GNR width scaling.Figure 4
I–V characteristics of SB-GNR-FETs with GNR width scaling, simulated atVd=0.1V.Table 3
Device performance of SB-GNR-FETs with GNR width scaling.
Device metricsWidth of GNRW=0.98nmW=1.35nmW=1.72nmOn-current,ION (A)7.52×10−67.82×10−69.47×10−6Off-current,IOFF (A)6.11×10−104.25×10−91.37×10−8ION/IOFF ratio1.23×1041.84×1036.92×102SS (mV/dec)72.0114.1123.2Figure5 shows the I–V characteristics of SB-GNR-FETs with three gate oxide thickness at 1 nm, 2 nm, and 3 nm. Table 4 lists the summarised device metrics of SB-GNR-FETs with gate oxide thickness scaling. Based on the gate oxide thickness scaling in Figure 5, it is shown that the oxide thicknesses of the SB-GNR-FETs have minimal impacts on their I–V characteristics. Although the SS and ION/IOFF ratio are slightly degraded due to thicker gate oxide, the performances of the SB-GNR-FETs are still decent. This observation is most probably due to the excellent gate electrostatic control offered by the DG structure [24]. In summary, the results in this work imply that the widths of the GNR channels are the most significant physical parameter influencing the device performance of SB-GNR-FETs. In the future, this study can be extended by incorporating other band gap engineering techniques such as doping and defects [25].Figure 5
I–V characteristics of SB-GNR-FETs with gate oxide thickness scaling, simulated atVd=0.1V.Table 4
Device performance of SB-GNR-FETs with gate oxide thickness scaling.
Device metricsGate oxide thicknesstOX=1.0nmtOX=2.0nmtOX=3.0nmOn-current,ION (A)7.52×10−66.79×10−66.06×10−6Off-current,IOFF (A)6.11×10−106.11×10−106.11×10−10ION/IOFF ratio1.23×1041.11×1040.99×104SS (mV/dec)72.076.480.6


## 4. Conclusion

In conclusion, the performances of SB-GNR-FETs with physical scaling are studied by using NanoTCAD ViDES tool. The performances of these devices are investigated by comparing the device metrics including the on-to-off current ratio and subthreshold swing. The results also show that DG structure can provide excellent gate control for GNR-based FETs. In addition, among the three physical scaling parameters investigated in this work, the widths of GNR channels are identified as the most vital design parameter that strongly affects the device performances of SB-GNR-FETs. The on-to-off current decreases and subthreshold swing increases when the width of SB-GNR-FET increases, causing its device performance to degrade. In summary, the physical parameters of SB-GNR-FETs must be carefully designed to achieve optimum performances for nanoelectronic applications.



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