# Area Efficient Implementation of MTI Processing Module on a Reconfigurable Platform

Authors: Munaza Yousuf; Arshad Aziz; Riaz Mahmud
Journal: Chinese Journal of Engineering
 (2014)

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## Abstract

This paper presents an area efficient Field Programmable Gate Array (FPGA) based digital design of a processing module for MTI radar. Signal contaminated with noise and clutter is modelled to test the efficacy of the design algorithms. For flexibility of design and to achieve optimized results, we have combined the high-level utility of MATLAB with the flexibility and optimization on FPGA for this implementation. Two- and three-pulse cancellers are chosen for design due to its simplicity in both concept and implementation. The results obtained are efficient in terms of enhanced  throughput per Slice (TPA) of 1.146, that is, occupying fewer area resources on hardware while achieving optimized speed. The outcomes show that this design of MTI radar processor has many advantages, such as high processing precision, strong processing ability, real time, and low cost. All these advantages greatly contribute to the design requirements and make it appropriate for the application of high-speed signal processing.


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## Body

## 1. Introduction

In radar systems, it is often desirable to be able to differentiate between moving targets and those that are stationary. This information can greatly serve operators when the surveillance targets of interest, such as vehicles or aircraft, are located in environments with a high density of traffic, clutter, stationary, and slow moving targets. Fortunately, through the use of digital signal processing, it is possible to extract this information from the system in real time using a Moving Target Indicator (MTI) filter [1]. Modern radar systems have evolving requirements, both in how the systems are designed and how the end user uses the data. This results in design change in electronic systems affecting both the military and commercial design communities, that is, the need for smaller, energy-efficient systems with high processing-power requirements. This makes low power consumption key drivers in most designs of high speed systems. More digital logic also allows designers to make early decisions on actionable intelligence and to meta-tag sensor data earlier for more efficient analysis. These and other emerging techniques will allow for the creation of better radar systems, but each requires additional signal-processing resources. One of these resources is the emerging class of high-performance FPGAs.Moving Target Indicator (MTI) radars are developed and used extensively to detect and follow specific moving targets and eliminate clutters. Processing system in the radar is massive and complex, since it is required to perform at high processing speed. Improvement in FPGAs component density and performance capability has resulted in more signal-processing functions being incorporated and migrated to the front end of the radar system containing the exciter/receiver [2]. In past systems, conventional digital signal processors were used to perform many of these algorithms. However, Field-Programmable Gate Arrays (FPGA) deliver an order of magnitude higher performance than traditional DSPs. Several DSP functions are needed for radar signal processing in the receiver. Each function should be closely examined to determine whether the application will show substantial speed and performance improvements through implementation in an FPGA. These functions can be efficiently implemented using an FPGA embedded processor, even for highly complex and adaptive operations. Our target will be to combine the capabilities of hardware and software to implement the original MTI receiver to generate a true bit accurate model and validate it using Simulink. The contribution factor of this paper is the design strategy that invests more time in thorough simulation based verification of design concepts to save time rather than on postsynthesis issues. This focus has helped us simplify the design to more optimal levels on reconfigurable hardware, that is, FPGA. This enables us to minimize the hardware delivery time by translating the concept into a fully functional, implementation ready design optimized for target embedded platform as per requirement.The rest of the paper is arranged as follows. In Section2 a detailed literature review has been given that discusses the contribution factor of this work as compared to previous implementations. Section 3 describes the basic characteristics of MTI processing. Section 4 covers design architecture on FPGA. This also includes the integration of software and hardware platforms to achieve optimized results. Section 5 includes results of design implementation. Section 6 pertains to the conclusions that are arrived at, after combining the software and hardware computations.


## 2. A Literature Review

High-speed, real time, and accuracy have always been the significant requirements of radar signal processing in its application area. Using FPGA cannot only meet these needs, but also improve reliability of system and strengthen universality of unit, cut cycle, and cost of the system development, and so forth. This paper has completed the design of an MTI radar module in which a FPGA is the core, primarily elucidating the principles of radar applications, filtering amplification of radar signal processing,A/D sampling, algorithm and FPGA realization. The literature survey does not reveal any application that discusses a completely FPGA based implementation of an MTI processor. However, some implementations present FPGA’s work alongside DSPs that is a semiparallel architecture to perform MTI processing, implemented by Ali et al. [3]. An architecture utilizing a DSP-FPGA combination for clutter processing has been proposed by Xu et al. [4], which involves the FPGA writing the successive returns into an SRAM chip and DSP performing the computations. Different FPGA implementations for FIR filters have been proposed in [5, 6]; both of these implementations focus primarily on area reduction while trying to achieve reasonable speeds. Stapleton et al. [7] have examined the possibilities of enhancing radar signal processing algorithms using FPGAs. Li and Wang [8] have given radar signal processor design on FPGA that focuses on filtering amplification, A/D sampling algorithm, and realization of FFT. Reference [9] has proposed a timeshared approach requiring about 1.2% slices of an XC2V6000 for implementation of a dynamically reconfigurable Pulse Doppler radar in a mixed system comprising a DSP and FPGA to perform linear frequency modulation. Reference [10] has given implementation of an IIR filter based moving target indication (MTI) processor but there is a downside to IIR filters in that they do not guarantee a linear phase response. Moreover, stability issues have to be looked after. Bin Khalid et al. [11] have proposed an FPGA based real-time signal processor for Pulse-Doppler radar. Hence it is observed that the radar processors have been implemented either entirely on hardware or entirely on software. The results of this research work done contribute to integrate the individual capabilities of both hardware and software to achieve optimized results. The conclusions show that this design is advantageous in terms of speed and efficient device utilization.


## 3. MTI Processing

Doppler processing can be divided into two major classes: Pulse Doppler processing and Moving Target Indication (MTI). When only target detection is of concern, the MTI filter is usually adequate. MTI filters even a first or second order FIR high-pass filter such as 2- or 3-pulse MTI cancellers can be used to filter out the stationary clutter. Figure1 shows a typical MTI Pulse canceller. Higher order filter types are used as they only provide modest performance improvements over the pulse cancellers [12]. The synchronous detection in Figure 2 shows the complex envelope during the coherent local oscillator demodulation stage in the receiver. Quadrature demodulation avoids loss of signal due to blind phase effects of a single demodulator as well as resolving the phase function of the complex envelope. Once the synchronous detection of the complex envelope is complete, it is processed in two stages: high-pass FIR filters with sampling at the pulse repetition rate and a matched correlator for return code (target) detection with video A/D sampling at the bit duration interval.Figure 1
MTI pulse canceller.Figure 2
Synchronous detection of Doppler-shifted pulse return.The resulting complex signal will be filtered in both the in-phase and quadrature-phase components as defined in:(1)IpI(n)=cos(2πfd·ntpri)IpQ(n)=sin(2πfd·ntpri)OpI(n)=sin(2πfd·ntpri)OpQ(n)=cos(2πfd·ntpri).A steadily moving target moving atVd will Doppler shift by ωd the carrier frequency ωc, thereby altering the complex envelope of the radar waveform. This is defined in (2), where c is the speed of light. The Doppler frequency is simply the time derivative of the complex envelope’s phase function, thus emphasizing constant receiver phase offset. This Doppler shift is found by sampling the quadrature phase angle at the pulse repetition frequency. It is this angle θ, defined in (2) and illustrated in Figure 3 that is measured using consecutive IQ samples at the pulse repetition interval:
(2)fd=2FtcVcosθ.Figure 3
Quadrature Doppler phase angle measurement.The set of relations as defined in [1] best describe the phenomena. The reference signal and the target echo signal are mixed in the mixer stage of the receiver. Only the difference frequency voltage component from the mixer is of interest:
(3)vd=Vdsin[ωdt-ω0R0c].
The fundamental MTI filter component is the high-pass FIR feed-forward pulse canceller. These filters are guaranteed to be stable, that is, all zeroes and no poles in the transfer function. They are easy to implement in direct form using a tapped delay line. A two-pulse canceller as shown in Figure 1 is used if the clutter component (assuming DC only) remains constant in a given range bin and can be eliminated by subtracting the output from two successive pulses. The transfer function of two-pulse canceller is equal to 1-1/z and is equivalent to FIR digital filter with magnitude response sin(ω/2). In practice, the clutter has a power spectrum that covers frequencies above DC. The two-pulse canceller will attenuate low frequency components but may not totally reject clutter. A three-pulse canceller with its transform function equivalent to FIR filter is given in (7). This decreases further the components near DC [13]. Figure 4 shows the unity gain frequency response of the filter:
(4)h(t)=δ(t)-2δ(t·T)+δ(t·2T).
Signal-to-Clutter Ratio (SCR) instead of Signal-to-Noise Ratio (SNR) determines the RADAR’s capability to detect targets in a high clutter background. Normally, clutter signal level is much higher than the receiver noise level because clutter echoes are random and have thermal noise-like characteristics. Grazing angle, surface roughness, and the RADAR wavelengths mainly affect the amount of clutter in the RADAR operation [14]. Differentiating target returns from clutter echoes is based on the target RCS and the estimated clutter RCS. Clutter RCS can be defined as the equivalent radar cross section endorsed to reflections from a clutter area, Ac. The average clutter is given by
(5)σc=σ0Ac,
where σ0 (dB/m2) is the clutter scattering coefficient.Figure 4
MTI high-pass filter response versus normalized frequency.The clutter areaAc and SCR are defined as
(6)Ac=(Rθ3dBcτ2secΨg),(7)SCR=2σtcosΨgσ0θ3dBRcτ.
Clutter-to-Noise (CNR) is defined as
(8)CNR=PtG2λ2σc(4π)3R4KT0BFL,
where Pt is the peak transmitted power, G is the antenna gain, λ is the wavelength, K is Boltzmann’s constant, T0 is the effective noise temperature, B is the radar operating bandwidth, F is the receiver noise figure, and L is the total radar losses.For Gaussian clutter, the clutter and noise can be combined and RADAR measurement can be derived from the signal-to-clutter + noise ratio as given by(9)SIR=1(1/SNR+1/SCR).MATLAB simulations considering clutter have been carried out and the results are shown in the Figure5. The simulation parameters are written below
(10)σt=0dBsm,σ0=-30dBsm,AntennaSidelobeLevel=-30dBsm,AntennaandTargetHeight=10m.
The optimal goal is to concentrate on clutter rejection; hence, the desired SNR as shown in the top of the graph is quite high. It is also clear that the SCR is well below the SNR level.Figure 5
Variation of SCR, SNR, and CNR with distance (km).


## 4. Design Implementation

The workflow demonstrated by Figure6 starts by reading the target information from an array stored in the workspace which in this case is the speed of the target. A MATLAB-based mathematical model of the system has been developed and investigated. Part of the data, received as a result from these investigations, has been used for the simulation of the circuit [15] and synthesized in FPGA to verify if the system meets the real-time constraints. The analysis of the results shows their complete coincidence with those received from the mathematical simulation. The gateways are used to do conversion from floating point data type to fixed point data type and vice versa.Figure 6
Flow chart of design algorithm.The main advantage of proposed structure, that is, the hybrid of software and FPGA hardware, is the capacity whereupon we can easily change the operating factors of any block of the system. If it is required in some applications to increase the precision of the overall system, then the increase in number of bits can be realized in each block hence giving us the flexibility to adjust the parameters of the system and therefore better solutions. The parameters of the design have been chosen carefully so that the radar system is operating in theL band of the electromagnetic spectrum. Table 1 shows process parameter assessed and refined according to design approach.Table 1
Process parameters.
Parameter
Value
Operating band
L (1.0-2.0 GHz)
Operating frequency range (MHz)
1215–1400
Nominal operating frequency f0
1250 MHz
Range resolution (m)
150
Receiver bandwidth (MHz)
1
Pulse widthτ (µs)
1
Unambiguous  range (nm)
100
PRF (Hz)
800
PRF Mode
Single
PRI (msec)
1.25
Noise figure (dB)
10
Antenna gain (dB)
35
Unambiguous range (nm)
100
Pd
0.9
Pfa
1
e
-
6The core of this design relies on the fact that MTI systems contain coherent pulse train signals. The output of the phase detector for moving target varies in amplitude from pulse to pulse as the phase changes between the transmitted and received signals. However there is no change in phase for fixed objects. By making use of this approach signal processing technique like delay line cancellers are used to implement MTI systems. A stationary target at the range of 60 km has been placed to simulate the effect of clutter rejection filter. Also, additive white Gaussian noise (AWGN) has been added to account for receiver noise introduced in actual systems. The simulated radar parameters yield an unambiguous range of approximately 100 Nm and detection of targets with maximum radial velocity of no less than 310 m/s. The computational block for the radar signal processor is implemented on Xilinx FPGA Spartan-III E Xc3s500e using Verilog HDL (Hardware Descriptive Language). Fixed point implementation has been done. Each memory location was 16 bit wide; lower 8 bits to store the imaginary part and upper 8 bits to store the real part. The block diagram of radar system implemented on FPGA is shown in Figure7. The user defined precision has been set for the addition blocks with output type as signed 2’s complement 16 bit number with 14 binary points. The implementation field is set by selecting fabric as core parameter. The solver used for simulation is fixed step discrete solver and simulation step size is 1.25e-007 for this design.Figure 7
Block diagram of hardware implementation.The received echo is fed to the phase detector forI/Q channel processing. The I/Q demodulation stage is most commonly digitally implemented as either a Hilbert transform or an in-phase and quadrature mixing operation. The mixing operations are simply digital multiplications by sine and cosine [16]. These are further illustrated by pseudocodes in the following listings.(A)  Pseudocode
(11)
loop
i
=
0
to
P
-
1
,
loop
j
=
0
to
2
*
N
-
1
,
input
re
[
i
]
[
j
]
=
input
[
i
]
[
j
]
*
sin
(
2
*
pi
*
f
IF
*
J
f
ADC
)
,
ADC
where P is the number of pulses per burst and N is the number of range bins per pulse. fIF and fADC are sampling frequency of intermediate frequency (IF) and ADC respectively.(B)  Pseudocode for Two-Pulse Canceller
(12)
loop
i
=
0
to
N
-
1
,
loop
j
=
0
to
P
-
1
,
mti
[
i
]
[
j
]
=
n
[
j
]
[
i
]
-
temp
,
temp
=
n
[
j
]
[
i
]
.The processing requirements for the two-pulse canceller are thusN×P×2 memory reads, subtractions, and memory writes, while the 3-pulse canceller requires an additional N×P×2 multiplications and additions [16].(C)  Pseudocode for Three-Pulse Canceller
(13)
loop
i
=
0
to
N
-
1
,
loop
j
=
0
to
P
-
1
,
mti
[
i
]
[
j
]
=
n
[
j
]
[
i
]
-
2
*
temp
1
+
temp
2
,
temp
2
=
temp
temp
1
=
n
[
j
]
[
i
]
,
where n corresponds to the present pulse.Our design module 1 implements MTI filter using three-pulse canceller realizations as shown in Figure8. The three-pulse canceller is a popular and simple MTI filter. It is an all-zero FIR filter with filter coefficients 1, −2, and 1. Design module 2 implements MTI filtering using single delay line canceller also known as two-pulse canceller as shown in Figure 9. The system throughput is one sample per clock cycle. According to minimum period of 9.787 ns, the maximum frequency is 144.8 MHz.Figure 8
Design 1 (3-pulse canceller).Figure 9
Design 2 (2-pulse canceller).


## 5. Results

We have successfully implemented our design module on FPGA. The design takes the target information and approximated Doppler speeds within acceptable threshold. On implementation of designs, in Design module 1 the clock rate achieved is higher while Design module 2 turns out to be an efficient approach in terms of achieving effective area utilization on FPGA. Also the results obtained are resourceful in terms of enhanced throughput per slice, that is, occupying fewer area resources on hardware while, achieving optimized speed, TPA of 1.146 for our design module 2 is much better than other implementations [3], which is considered as a significant achievement. Bin Khalid et al.’s [11] implementation on Xilinx Virtex-II Pro (ML300) took less than 90 μs hence resulting in slower performance of overall system. These premises give us a subjective idea of the performance since there are not similar architectures reported. Table 2 gives a comparative analysis of the device utilizations and clock details of our designs with other works [3, 9, 11]. Results indicate that our design gives more area optimization. The filtered signal by the proposed architecture is shown in Figure 10 with clutter being suppressed.Table 2
Implementation results.
Implementation
Device
Clock rate(MHz)
FPGA area(slices)
Throughput/slice(TPA)
Our design 1
Xc3s500e
144.8
1336
0.108
Our design 2
Xc3s500e
122.639
107
1.146
Other work [3]
Virtex-4 SX35
183.55
1075
0.170
Other work [3]
Virtex-4 SX35
177.70
1382
0.128
Other work [11]
Virtex-II Pro (ML-300)
0.11
1468
—
Other work [9]
XC2V6000
102.17
811
—
Bold values emphasize superiority of results.Figure 10
MTI filter output.


## 6. Conclusions

Our research emphasizes on designing digitized MTI processing modules that have been efficiently tested and verified on FPGA. This research contribution has integrated the capabilities of both hardware and software to achieve optimized results both in terms of device utilization and maximum achievable frequency. In the future, this work can be optimized further by carrying out all the phases of design on Verilog HDL. The Verilog HDL code can be optimized to achieve the desired results in lesser time and fewer storage elements. Also, the newer FPGA families being introduced in the market offer better performance and more storage elements to enhance performance and yield better results.



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