# A New Digital to Analog Converter Based on Low-Offset Bandgap Reference

Authors: Jinpeng Qiu; Tong Liu; Xubin Chen; Yongheng Shang; Jiongjiong Mo; Zhiyu Wang; Hua Chen; Jiarui Liu; Jingjing Lv; Faxin Yu
Journal: Journal of Electrical and Computer Engineering
 (2017)

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## Abstract

This paper presents a new 12-bit digital to analog converter (DAC) circuit based on a low-offset bandgap reference (BGR) circuit with two cascade transistor structure and two self-contained feedback low-offset operational amplifiers to reduce the effects of offset operational amplifier voltage effect on the reference voltage, PMOS current-mirror mismatch, and its channel modulation. A Start-Up circuit with self-bias current architecture and multipoint voltage monitoring is employed to keep the BGR circuit working properly. Finally, a dual-resistor ladder DAC-Core circuit is used to generate an accuracy DAC output signal to the buffer operational amplifier. The proposed circuit was fabricated in CSMC 0.5μm 5 V 1P4M process. The measured differential nonlinearity (DNL) of the output voltages is less than 0.45 LSB and integral nonlinearity (INL) less than 1.5 LSB at room temperature, consuming only 3.5 mW from a 5 V supply voltage. The DNL and INL at −55°C and 125°C are presented as well together with the discussion of possibility of improving the DNL and INL accuracy in future design.


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## Body

## 1. Introduction

Along with the development of the semiconductor technology, phased array radar system has become more and more attractive in the area of space communication. However, due to the source limitation in space environment, it constrains that the design of the transmit/receive (TR) module has to have many control ability to switch between transmit and receive mode. This has motivated the design of high performance control chip with respect to accuracy, linearity, and stability under harsh space environment [1–4].The duty of the control chip is to deliver different bias voltage to corresponding chip by following instructions from command computer. Therefore, its performance is highly relay on the design of its digital to analogous converter (DAC). There are many types of DAC structures that have been proposed in the literature [5–12]. Resistor based DAC architecture is one of the most attractive due to its simplicity structure, high stability, high monotonic, and low power consumption [12] and is a good choice for space application. However, for resistor type of DAC architecture, the DAC’s number of bits is proportional to the number of resistor used in the circuit. The higher number of resistors further leads to larger of chip area. It also faces the increasing of instability due to the effectiveness of processing technology on the larger number of resistors. In order to solve such problems, the researchers have developed many types of architecture such as subranging [5], dual-ladder resistor [6], resistor-floating-resistor-string [7], embedded operational amplifier [8], and multibits calibration [9]. Nonetheless, all those methods are able to improve some the DAC circuit in different ways; there are still more space that can be improved, especially in the application of space environment. This has motivated the introduction of low-offset bandgap reference (BGR) structure [10, 11]. The good side is that the BGR circuit is able to provide a reference voltage to the DAC circuit for improving the stability of DAC circuit for a normal application, but for the harsh environmental application such as space application, the BGR circuit needs to be improved further to cope with the application.In this work, we have introduced a new development of a 12-bit high precision, low power consumption, and high stability DAC circuit based on an improved low-offset BGR and dual-resistor ladder circuit. Three main blocks have been optimized to achieve the design constrains.


## 2. DAC Overall Circuit Design

The proposed circuit design mainly includes three parts: BGR block, Start-Up Block, and DAC-Core Block as illustrated in Figure1. The input signal of the proposed DAC includes a pair of latch up signal “CE” and “CS”; it decides which input DAC instruction is stored into the “Latch Up” register. The “DAC IN<12:1>” is a 12-bit input instruction from an upper-computer which will be transferred to a set of bias voltages “Vout” and act on the following chipset in a TR module. “VDD” and “VSS” correspond to “+5 V” and “0 V” and are the power supply of the DAC. The reference voltage from BGR circuit is Vref = 2.5 V. The end stage operational amplifier is a two-stage PMOS class-AB output buffer with a 0.2 V to 4.8 V output voltages.Figure 1
Block diagram of the proposed DAC circuit.


## 3. The BGR Circuit Design

The aim of the BGR circuit is to provide a stable reference voltage “Vref” to the “DAC-Core” circuit without the effects from variation of power supply and environment condition such as temperature and radiation. There are two ways that have been employed in this paper to improve the stability of “Vref.” One is the use of two-cascade transistor structure; the second is the use of two low-offset operational amplifier with self-contained feedback circuit. They are detailed as follows.First, let us start with analysis of the traditional BGR circuit illustrated in Figure2 [12]; the output voltage “Vref” can be written as(1)Vref=Vbe-Q2+1+R2R1Vtln⁡n-VOS,where “Vbe-Q2” is base-emitter voltage for Q2 (≈ 0.7 V), “Vt” is the electron thermal voltage (≈ 0.026 V), “VOS” is the input offset voltage for operational amplifier, “n” is the ratio between number of Q2 and number of Q1. From (1), we know that the most troublesome part is “VOS.” If we can reduce the effect of “VOS,” then we have found a way of stabilize the overall DAC circuit. This is done by using a low-offset BGR circuit which is shown in Figure 3. This architecture employs two-cascade transistors to minimize the contribution of “VOS” on “Vref.”Figure 2
The traditional BGR circuit.Figure 3
Improved low-offset BGR circuit.From Figure3, the output voltage of the improved low-offset BGR circuit is written as(2)Vref=2Vbe-Q3Q4+1+R2R12Vtln⁡n-VOS,where “Vbe-Q3Q4” is the base-emitter voltage for transistor “Q3” and “Q4”. Comparing (1) and (2), the effectiveness of “VOS” to the “Vref” is reduced by increasing the value of “2Vbe-Q3Q4” and “2Vtln⁡n.” However, the value of “VOS” is untouched from (2), which still causes problems. Therefore, in order to reduce the effect of “VOS” further, two low-offset operational amplifiers (see Figure 4) with self-contained feedback circuit are employed in here to reduce the effects of PMOS current-mirror mismatch and its channel modulation without the decrease of supply power redundancy. It further leads to the reducing of “VOS” value of the overall BGR circuit.Figure 4
Low-offset operational amplifier circuit.


## 4. Start-Up Circuit Design

The Start-Up circuit has a self-bias and multipoint monitor structure which provides a self-bias current to the BGR circuit. As demonstrated in Figure5, when the power of the DAC is switched on, points A and B will have a high voltage level; “Vref1” and “Vref2” are at low voltage level. The current at BGR circuit is “0.” The MOSFET M7–M10 are “off.” M5 and M6 are “on.” Current is injected into BGR circuit and the voltage level starts to drop at points A and B at the same time. Following this process, M1 and M2 are switched on which indicates the BGR circuit is fully functioning. M7 and M8 mirror the BGR circuit current “ib.” At this point, M5 and M6 are switched off, and the Start-Up circuit changes to low power consumption state. The voltages at “Vref1”, “Vref2,” and point A are monitored during the DAC working state. Once the voltage at those three points is affected by the environment condition, they will wake up the Start-Up circuit to keep the BGR circuit working properly.Figure 5
Start-Up circuit with self-bias current source.


## 5. DAC-Core Circuit Design

The design of the DAC-Core circuit is based on resistor structure to achieve high output monotonic and stability with simply layout and low power dissipation. A two stage dual-ladder resistor string circuit structure is used in here to trade off between the accuracy and chip size.R1 and R2 are the voltage splitter at the first and second stage. There are two switches S1 and S2. They have been controlled by DAC IN<12:7> for S1 and DAC IN<6:1> for S2.The main problem of such design is that whenS1 is in action, the fluctuation of its switch on resistance (Ron) will result in the voltage value change for the second stage resistors. This leads to the lower of the DAC output accuracy. In order to solve this problem, we have adjusted the size of the 65 switches to achieve a full match, low variation of switch on resistance. This is done as follows. First, when the switches in the first stage are switched on in pair, the connection point voltage can be written as “Vr” and “Vp” (see Figure 7); then the effective resistance between those two points is written as(3)RParallel=R1∥2Ron⁡+63R2=R163R2+2Ron⁡R1+63R2+2Ron⁡.Before switching,(4)V1=RparVref63R1+Rpar×63R2+Ron⁡63R2+2Ron⁡+Vr.After switching,(5)V2=R1+Rpar×Ron⁡/63R2+2Ron⁡63R1+RparVref+Vr.The DAC output variation before and after the switching can be written as(6)Vstep1=V2-V1=R1-63R2Rpar/63R2+2Ron⁡63R1+RparVref.Voltage step size in the second stage before switching is illustrated as(7)Vstep2=RparR2/63R2+2Ron⁡63R1+RparVref.In order to achieve a high accuracy output of the DAC, Vstep1 has to be equal to Vstep2, which means that(8)Ron⁡=R2-R12.Due to the fact that MOSFET is working at the linear region under switching on condition, then Ron⁡ can be rewritten as(9)Ron⁡=1μnCoxW/LVGS-VTH.Then the width and length ration of the switches in the first stage have to satisfy the following relation:(10)WL=1Ron⁡μnCoxW/LVGS-VTH.Therefore, by tuning the width and length ration of the switches in the first stage, the switching resistance effect on the DAC accuracy is reduced.


## 6. Test Results and Discussion

The proposed DAC circuit is fabricated by using CSMC 0.5μm 5 V 1P4M process. Its photography is shown in Figure 8.At the first instance, the 12-bit digital commands from “000000000000” to “111111111111” are tested at three temperature points, −55°C, 25°C, and 125°C, by using a PXI test system and a probe station. The variation of the output DAC is illustrated in Figure9. It is almost unchanged under the temperature test which indicates that the proposed DAC is every stable at this point. However, this cannot prove that the designed DAC are good enough definitely. Therefore, in order to evaluate the DAC performance more deeply, the NDL and INL results are illustrated as follows.In Figure10, the DNL verse input command is shown. The overall DNL is less than 0.45 LSB. There are no periodic properties (there is no sudden changes for every 64 commands within total 4096 commands) that have been observed; this indicates that the proposed DAC the step-size accuracy is kept well by the circuit shown in Figure 6.Figure 6
Dual ladder resistor string circuit.Figure 7
The schematic diagram of switching.
(a) (b)Figure 8
Photography of the proposed DAC chip.Figure 9
DAC output with different input code.Figure 10
DNL at 25°C.The DNL under −55°C is illustrated in Figure11. As shown, the DNL is getting worse with a maximum increase of 0.5 LSB. This is mainly due to the fact that the MOSFET has contributed to the power divider circuit in Figure 6. For MOSFET under low temperature condition, the resistance value for each MOSFET highly depends on its bias voltage which varies rapidly. Those variations have effects on the DAC’s DNL significantly. In case of high temperature at 125°C, the MOSFET has been less affected by the temperature; therefore, it results in a better DNL variation compared with the low temperature. This conclusion is illustrated in Figure 12. As illustrated, the DNL variation is less than 0.15 LSB with respect DNL value at 25°C.Figure 11
DNL at −55°C.Figure 12
DNL at 125°C.The variations of DNL at low temperature are very harmful characteristics for DAC design; they could cause a code jumping when DNL is greater than 1. However, they can be reduced by adding more resistor ladders to reduce the effects of the MOSFET switching resistance. The downside is the increasing of chip size. Therefore, tradeoff between the output accuracy and chip size has been considered during DAC design.The INL versa input commands are shown in Figure13. The INL value is less than 1.5 LSB. The shape of the INL curve is not monotonous; it has a “sine wave”-like shape, which indicates the INL has no accumulative error for the full command swap.Figure 13
INL at 25°C.In Figures14 and 15, the INL at −55°C and 125°C are shown. The shapes of the INL are preserved, but the INL value has increased up to 2.5 LSB at 125°C. This is because, during the wafer processing, the concentration for producing the resistor has a huge effect on the quality of the resistors, and the resistors are sensitive to the high temperature as well compared with the low temperature. This results in that the INL has been getting worse along with the increase of temperature. Another source of uncertainty is that the switch on resistance of the MOSFET is highly affected by the temperature which leads to a poor INL performance. Those can be explained by using a resistors mismatch model illustrated in Figure 16.Figure 14
INL at −55°C.Figure 15
INL at 125°C.Figure 16
The model of resistors mismatch.As shown in Figure16, during the wafer process, there will be a resistance gradient which results in a resistance change. This can be demonstrated by introducing ΔR to represent the resistance changes with respect to wafer process (in here, the resistance is modeled as a linear incasing of resistance form the bottom of the resistance ladder to the top). Therefore, the resistance mismatch has created the change of Vout under different temperature and leads to the INL and DNL change under temperature.In case of DNL, it is highly affected by the voltage step sizeVstep as(11)DNLk=Vstepk-VstepidealVstepideal.Then the error can be written as follows where Vp-Vr is related to the Bandgap reference voltage Vref and ΔR1:(12)Vstep,error=Vp-VrΔR263R2+2Ron⁡.Let k1 and k2 represent the temperature coefficient of R1R2 and Ron, respectively. The equation of Vstep,error can be approximated as(13)Vstep,error=Vp-Vrβ63+2Ron1+k2ΔT/R21+k1ΔT,where β represents the resistance mismatch ratio, β=ΔR2/R2, and ΔT represents the change of temperature from room temperature. Then, the step error is ultimately affected by Vref, resistance, and its temperature coefficient. Combined with the design in this paper, we can draw the following conclusion: when the temperature becomes high, Vstep,error becomes larger and the DNL performance decreases.In case of INL, it is the error between the theoretical voltage and actual voltage which can be expressed as(14)INLk=Vk-VidealkLSB=∑n=0kDNLn.As illustrated in Figure 16, when the temperature changes, all the node voltage in the first ladder will change, while the effect of divider resistance will decrease and the absolute value will deviate from the theoretical value, resulting in INL performance decline. On the other hand, as can be seen from the definition of INL, it can be regarded as the accumulation of DNL, so the mechanism of temperature influence on DNL is also applicable to the analysis of INL. The same conclusion can be realized that INL performance is decreased under high temperature.This can be improved by increasing the resistors value at the second ladder and reducing the resistors value at the first ladder at the same time. This method will reduce the effects of the switching on resistance from the MOSFET. However, we have to be alarmed that the power consumption will increase along with the increasing of the resistor value at the second ladder.


## 7. Conclusion

In conclusion, a new 12-bit digital to analog converter (DAC) circuit based on a low-offset BGR circuit was presented. In order to improve the stability of the BGR circuit, two cascade transistor structures and two self-contained feedback low-offset operational amplifiers are employed to reduce the effects of offset operational amplifier voltage effect on the reference voltage, PMOS current-mirror mismatch, and its channel modulation. A Start-Up circuit with self-bias current architecture and multipoint voltage monitoring was also used to keep the BGR circuit working properly. The DAC-Core circuit with a dual-resistor ladder structure is employed to produce an accuracy output signal. The INL and DNL results of the proposed circuit using CSMC 0.5μm 5 V 1P4M process at −55°C, 25°C, and 125°C are presented. The measured DNL of the output voltages is less than 0.45 LSB and INL is less than 1.5 LSB at room temperature, consuming only 3.5 mW from a 5 V supply voltage. The discussion of improving the INL and DNL in the future design is detailed as well to provide a vision of high accuracy, low power consumption, and high stability DAC design.



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*Source: 1658695-2017-01-02.xml*