# Potential and Quantum Threshold Voltage Modeling of Gate-All-Around Nanowire MOSFETs

Authors: M. Karthigai Pandian; N. B. Balamurugan; A. Pricilla
Journal: Active and Passive Electronic Components
 (2013)

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## Abstract

An improved physics-based compact model for a symmetrically biased gate-all-around (GAA) silicon nanowire transistor is proposed. Short channel effects and quantum mechanical effects caused by the ultrathin silicon devices are considered in modelling the threshold voltage. Device geometrics play a very important role in multigate devices, and hence their impact on the threshold voltage is also analyzed by varying the height and width of silicon channel. The inversion charge and electrical potential distribution along the channel are expressed in their closed forms. The proposed model shows excellent accuracy with TCAD simulations of the device in the weak inversion regime.


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## Body

## 1. Introduction

Semiconductor nanowires are attractive components for future nanoelectronics since they can exhibit a wide range of device function and at the same time serve as bridging wires that connect larger scale metallization. The nanoscale FETs based on silicon nanowires have notable attention for their potential applications in electronics industry. In a continuous effort to increase current drive and better control over SCEs, silicon-on-insulator (SOI) MOS transistors have evolved from classical, planar, and single-gate devices into 3D devices with a multigate structure (double-, triple-, or gate-all-around devices). These multigate nanowire FETs that prevent the electric field lines from originating at the drain from terminating under the channel region are now widely recognized as one of the most auspicious solutions, for meeting the roadmap requirements in the decananometer scale. Multigate device structures of nanowire transistors pave the way for better electrostatic control, and as a result, intrinsic channels get higher mobility and current [1].CMOS devices can be scaled down up to a channel length of 10 nm when the number of gates in the device is increased. In such transistors the short channel effects are controlled by the device geometry, and hence an undoped or lightly doped ultrathin body is used to sustain the channel. Various device structures such as double gate fully depleted SOI, trigate, and all around gate structures have been extensively investigated to restrict SCEs within a limit while achieving the primary advantages of scaling, that is, higher performance, lower power, and ever increasing integration density [2]. The scaling theory and the analytical SCEs model for nanowire transistors based on the concept of natural length are successful to a certain extent. To address the issue of 2D effects in the gate insulator, a more generalized concept of scale length has been proposed recently [3, 4].Modeling of quantum confinement and transport in a nanowire transistor has been addressed in the literature [5–7]. The undoped cylindrical body GAA field effect transistor, that has a great control over the corner effects and channel, is considered to be promising candidate for sub-45 nm regime [8, 9]. An analytical threshold voltage model for GAA nanoscale MOSFETs (Figure 1) considering the hot carrier induced interface charges has been proposed by Ghoggali et al., in 2008 [10]. Quantum confinement and its effect on threshold voltage variations in short channel GAA devices have been studied in 2009 [11]. A compact analytical threshold voltage model proposed by Te-Kuang deals with the interface trapped charges in a nanowire channel [12]. A physically based classical model for body potential of a cylindrical GAA nanowire transistor has been proposed by Ray and Mahapatra in 2008 [13], and a quasianalytical model for predicting the potential of a nanowire FET has been proposed by De Michielis et al., in 2010 [14].Figure 1
Schematic diagram of a gate-all-around SiNW MOSFET.In this paper quantum threshold voltage modeling of a lightly doped gate-all-around silicon nanowire transistor is proposed. In modeling the threshold voltage, the quantum effects are also taken into account, as the quantization of electron energy in ultrathin devices can never be ignored. One important consequence of the quantum mechanical carrier distribution, in accordance with the device behavior, occurs when the device geometrics and the silicon thickness are varied, so a reliable compact model for the nanowire transistors must also take into account quantum effects resulting out of these variations. The proposed physically based closed form quantum threshold voltage model holds good for ultrathin and ultrashort channel gate all around devices and does not discuss any unphysical fitting parameter. The compact threshold voltage model is obtained by solving the 3D Poisson equation and 2D Schrodinger equations in the weak inversion region. These equations are then consistently solved to obtain the potential distribution and inversion charge density.


## 2. Threshold Voltage Modeling

Here, we consider a lightly doped nanowire MOSFET in the weak inversion region, where both fixed and mobile charge densities in the channel are negligible. We have assumed a flat potential on the plane perpendicular to the source-drain direction. Poisson-Schrödinger equations should be solved consistently to obtain the potential and inversion charge density. But, in the weak inversion regime, we have approximated the Poisson equation as Laplace equation with the inversion charge density neglected, and thus the two equations are decoupled. The midgap metals are used for gate, intended to suppress the silicon gate poly depletion induced parasitic capacitances [15]. The 3D Poisson equation is solved to obtain the threshold voltage in the weak inversion region, including the parabolic band approximation. The potential distribution in insulator and silicon regions can be expressed as
(1)δ2ψ(x,y,z)δx2+δ2ψ(x,y,z)δy2+δ2ψ(x,y,z)δz2=0.The potentialψ in terms of x (width), y (height), and z (length) is to be determined. The boundary conditions defined by the physics of the device are given by
(2)ψ(x,-H2-TOX,z)=Vg,ψ(-W2-TOX,y,z)=Vg′,δψδx|x=0=0,δψδy|y=0=0,ψ(x,y,0)=ψbi,ψ(x,y,L)=ψbi+Vds.
For a gate-all-around device, we have to find the insulator potential on all sides of the channel under consideration. So the height and width of the channel are also taken into account. The insulator potential is now expressed as
(3)ψ(x,y,z)=Vg-ψbi-ΦmsTOX(x-W2)+ψbiforW2<x<W2+TOX,0<y<H2,ψ(x,y,z)=Vg-ψbi-ΦmsTOX(y-H2)+ψbifor0<x<W2,H2<y<H2+TOX,
where Vg is the gate voltage, ψbi is the built-in potential, L is the channel length, and Vds is the drain to source voltage which is negligible for low Vds. Φms is the work function difference. By applying the superposition principle, the electrostatic potential can be now written as
(4)ψ(x,y,z)=UL(x,y,z)+UR(x,y,z)+Vg(x,y).
Here Vg(x,y) is the 1D solution of the Poisson equation that satisfies the gate boundary conditions. UL satisfies the source boundary condition, but it is bound to have a null value on the gate and drain boundaries. Similarly UR satisfies the drain boundary condition, and it is bound to have a null value on the gate and source boundaries. On further evaluation, the term Vg+UL is found to satisfy the potential equation when UR is on null value, and in an exact repetition, the term Vg+UR satisfies the potential equation when UL is on null value. From (1),
(5)ψxx+ψyy+ψzz=0.
By solving the above equation using LDE method, we obtain the value of ψ. Then the limits are applied on the equation using the boundary conditions. Now the potentials UL is given by
(6)UL1=∑n∑mC×KAnmsin(Λn(x-W2-TOX))×cos(Mmy)sinh(∑nm(L-z))forW2<x<W2+TOX,0<y<H2,(7)UL2=∑n∑mC×KBnmcos(Λnx)×sin(Mm(y-H2-TOX))×sinh(∑nm(L-z))for0<x<W2,H2<y<H2+TOX,(8)UL3=∑n∑mC×KCnmcos(Λnx)cos(Mmy)×sinh(∑nm(L-z))for0<x<W2,0<y<H2.Similarly the values of potentialUR are also derived as follows:
(9)UR1=∑n∑mC×KPnmsin(Λn(x-W2-TOX))×cos(Mmy)×sinh(∑nmz)forW2<x<W2+TOX,0<y<H2,UR2=∑n∑mC×KQnmcos(Λnx)×sin(Mm(y-H2-TOX))sinh(∑nmz)for0<x<W2,H2<y<H2+TOX,UR3=∑n∑mC×KRnmcos(Λnx)cos(Mmy)×sinh(∑nmz)for0<x<W2,0<y<H2,
where c=1/∑nmL and KAnm, KBnm, KCnm, KPnm, Kqnm, and KRnm are constants. From (6) and (8), UL and (∂UL)/∂x are found to be continuous in the x direction (x=W/2). The first derivative function (∂UL1)/∂x itself has εOX/εsi times discontinuities at the silicon insulator interfaces. Thus, applying continuity in both equations, we proceed to equate (6) and (8) as follows:
(10)-KAnmsin(ΛnTOX)=KCnmcos(ΛnW2).
Differentiating (6) with respect to x,
(11)∂UL1∂x=∑n∑mC×KAnm(Λn)cos(Λn(x-W2-TOX))×cos(Mmy)sinh(∑nm(L-z)).
Differentiating (8) with respect to x,
(12)∂UL3∂x=∑n∑mC×Kcnm(Λn)(-sin(Λnx))×cos(Mmy)×sinh(∑nm(L-z)).
Equating (11) and (12),
(13)KAnmεOXcos(ΛnTOX)=-KCnmεsisin(Λn2).
Dividing (10) by (13),
(14)εsitan(ΛnTOX)-εOXcot(ΛnW2)=0.
Likewise, from (7) and (8), UL and (∂UL/∂y) are found to be continuous in the y direction (y=H/2). The function (∂UL2/∂y) itself has discontinuities at the silicon insulator interfaces which are proportional to the dielectric constant εOX/εsi. Thus, applying continuity in both equations and equating (7) and (8), we get
(15)-KBnmsin(MmTOX)=KCnmcos(MmH2).
Differentiating (7) with respect to y,
(16)∂UL2∂y=∑n∑mC×KBnmcos(Λnx)(Mm)×cos(Mm(y-H2-TOX))×sinh(∑nm(L-z)).
Differentiating (8) with respect to y,
(17)∂UL3∂y=∑n∑mC×KCnmcos(Λnx)(Mm)×(-sin(Mmy))sinh(∑nm(L-z)).
Equating (16) and (17),
(18)KBnmεOXcos(MmTOX)=-KCnmεsisin(MmH2).
Dividing (15) by (18),
(19)εsitan(MmTOX)-εOXcot(MmH2)=0.
This natural length is an easy guide for choosing device parameters and has simple physical meaning that a small natural length corresponds to superb short channel effect immunity [4]. The value of Λn and Mm depends on device parameters. The potential UL can be modified as
(20)ULnm1=αnm×C×sin(Λn(x-W2-TOX))×cos(Mmy)×sinh(∑nm(L-z))forW2<x<W2+TOX,0<y<H2,ULnm2=βnm×C×cos(Λnx)×sin(Mm(y-H2-TOX))sinh(∑nm(L-z))for0<x<W2,H2<y<H2+TOX,ULnm3=γnm×C×cos(Λnx)cos(Mmy)×sinh∑nm(L-z)for0<x<W2,0<y<H2.
Similarly, the potential UR can be modified as
(21)URnm1=αnm×C×sin(Λn(x-W2-TOX))×cos(Mmy)×sinh(∑nmz)forW2<x<W2+TOX,0<y<H2,URnm2=βnm×C×cos(Λnx)×sin(Mm(y-H2-TOX))×sinh(∑nmz)for0<x<W2,H2<y<H2+TOX,URnm3=γnm×cos(Λnx)cos(Mmy)×sinh(∑nmz)for0<x<W2,0<y<H2.
Now the gnm can be obtained from the potential equations (20) by using different multipliers in different regions:
(22)gnm1=εOXsin(Λn(x-W/2-TOX))cos(Mmy)2εsisin(ΛnTOX)cos(Mm(H/2))forW2<x<W2+TOX,0<y<H2,gnm2=εOXcos(Λnx)sin(Mm(y-H/2-TOX))2εsicos(Λn(W/2))sin(MmTOX)for0<x<W2,H2<y<H2+TOX,gnm3=-cos(Λnx)cos(Mmy)cos(Λn(W/2))cos(Mm(H/2))for0<x<W2,0<y<W2.
Subsequently the constants αnm, βnm, and γnm are evaluated suitably:
(23)αnm=cos(ΛnW2)sin(MmTOX),βnm=cos(MmH2)sin(ΛnTOX),γnm=sin(MmTOX)sin(ΛnTOX).
From (20), the potential ULnm can be rewritten as
(24)ULnm1=-cos(ΛnW2)sin(MmTOX)×sin(ΛnTOX)cos(MmH2),ULnm2=-cos(MmH2)sin(ΛnTOX)×cos(ΛnW2)sin(MmTOX),ULnm3=-sin(MmTOX)sin(ΛnTOX)×cos(ΛnW2)cos(MmH2).
By multiplying with the corresponding orthogonal conjugate functions and integrating, coefficients of UL can be obtained. The coefficients of UR are also obtained in a similar method:
(25)inm=(∫0H+TOX∫0W+TOX(ψ(x,y,0))-V(x,y)gnm(x,y)dxdy∫0H+TOX∫0W+TOX(ψ(x,y,0))×(∫0H+TOX∫0W+TOXULnm(x,y,0)gnm(x,y)dxdy)-1,jnm=(∫0H+TOX∫0W+TOX(ψ(x,y,L))-V(x,y)gnm(x,y)dxdy∫0H+TOX∫0W+TOX(ψ(x,y,L))×(∫0H+TOX∫0W+TOXULnm(x,y,L)gnm(x,y)dxdy)-1.
The above integrals (25) are evaluated to obtain explicit expressions for inm and jnm as follows:
(26)inm=(Vg-ψbi)ωnm,jnm=(Vg-ψbi-Vds)ωnm,ωnm=Ωnmξnm,
where
(27)Ωnm=εOXΛntan((ΛnW)/2)+εOXMmtan(MmH/2)2εsiTOXΛn2Mm2-2ΛnMmtan(ΛnW2)tan(MmH2),ξnm=sin(ΛnTOX)16cos(ΛnW/2)(W+sin(ΛnW)Λn)r1+sin(MmTOX)16cos(MmH/2)(H+sin(MmH)Mm)r2.
And the values of r1 and r2 are given by
(28)r1=εOXTOXcos(MmH/2)εsisin(MmTOX)+Hsin(MmTOX)2cos(MmH/2),r2=εOXTOXcos(ΛnW/2)εsisin(ΛnTOX)+Wsin(ΛnTOX)2cos(ΛnW/2).
The potential equation is now rewritten as
(29)ψ(x,y,z)=Vg+(Vg-ψbi)×∑n∑mρnmsinh(∑nm(L-z))+(Vg-ψbi-Vds)∑n∑msinh(∑nmz),
where
(30)ρnm(x,y)=-ωnmγnmcos(Λnx)cos(Mmy)sinh(∑nmL).
Once the potential distribution at every point of the cross-section of the channel is known, we calculate the inversion charge density by using surface integral over the surface area of the channel. When the integrated charge at virtual source becomes equal to critical charge, the gate voltage of a lightly doped body device is nearly equal to the threshold voltage of the device. Hence the inversion charge can be expressed as
(31)Q=∫-H/2H/2∫-W/2W/2qnie(ψ/UT)dxdy,
where q is the elementary charge, UT is thermal voltage, and ni is the intrinsic carrier concentration.The charge equation can now be approximated as(32)Q≈WHqnie((ψ((3W/14),(3H/14),zc))/UT).
Here, zc is the virtual source position, which is half of the channel length for low Vds. Using the inversion charge we can obtain the classical threshold model as expressed in the following:
(33)VTC=(UTlnQWHqni+2Vbiρ11(3W14,3H14)×sinh(∑11L2))×(1+2ρ11(3W14,3H14)sinh(∑11L2))-1.


## 3. Quantum Threshold Voltage Modeling

As MOSFET devices are further scaled into the deep nanometer regime, it has become necessary to include quantum mechanical effects while modeling their device behavior. In this paper, we approximate the actual potential well as the square well potential since it is difficult to solve the Schrödinger equation to obtain the potential expressed in (29). The square well potential of a gate-all-around nanowire transistor is shown in Figure 2. The quantum charge of the device is expressed as
(34)Q=∑ix∑iyq∫Eixiy∞N1Df(E)dE,
where N1D is the 1D density-of-states and f(E) is the Fermi-Dirac distribution function. E is the energy of the electron wave. The terms ix and iy are positive natural numbers.Figure 2
Band diagram perpendicular to the gate-square well potential of a GAA silicon nanowire transistor.In silicon, six energy valleys are found to be present in its band structure (two lower energy valleys, two middle energy valleys, and two higher energy valleys). If the thin film of device has equal height and width, the two lower energy valleys and two middle energy valleys are combined together  to produce four lower energy valleys, and the other two higher energy valleys remain in their own state. Thus, the charge is given by(35)Q=q∑ix∑iy(mz2πℏ2)∫Eixiy∞(E-Eixiy)-1/21+e((E-EF)/kT)dE,
where mz is the mass of the valley which is perpendicular to the direction of quantization. The Fermi energy level is much lower than the conduction band energy in weak inversion region. Hence the charge equation can be approximated as
(36)Q=q(mz2πℏ2)∑ix∑iy∫Eixiy∞e((EF-E)/kT)(E-Eixiy)1/2dE.
Using the Schrödinger equation, the value of EixEiy is determined by the following formulation [5]:
(37)Eixiy=Eco+ℏ2π22[1mx(ixIx)2+1my(iyIy)2],
where the conduction band energy is given as
(38)Eco=Eg2-qψ(0,0,zc).
Using (36) and (37), the integrated charge can be obtained as
(39)Q=q(2kTmtℏ2)∑ix∑iyexp(-Eco+E1(ix,iy)kT)+q(2kTmtℏ2)∑ix∑iyexp(-Eco+E2(ix,iy)kT)+q(2kTmtℏ2)∑ix∑iyexp(-Eco+E3(ix,iy)kT),
where
(40)E1(ix,iy)=ℏ2π22[1m1(ixW)2+1mt(iyH)2],E2(ix,iy)=ℏ2π22[1mt(ixW)2+1m1(iyH)2],E3(ix,iy)=ℏ2π22[1mt(ixW)2+1mt(iyH)2].
Here the mt and m1 are the transverse and longitudinal effective masses of the energy valleys of silicon. The lengths ix and iy carry distinct values contingent on the direction of quantization. Finally, the quantum threshold voltage model becomes
(41)VTQ=(Eg2q+(kTq)In(QTτ)+2ψbiρ11(0,0)sinh((∑11L)2))×(1+2ρ11(0,0)sinh((∑11L)2))-1,
where
(42)τ=q(2kTmtℏ2)exp(-E1(1,1)kT)+q(2kTmtℏ2)exp(-E2(1,1)kT)+q(2kTmtℏ2)exp(-E3(1,1)kT).
The impacts on the threshold voltage due to quantum effects are acquired by using the following equation:
(43)VTC=VTQ+ΔVT.
Here, ΔVT is the difference between the quantum threshold voltage and the classical threshold voltage.


## 4. Results and Discussion

Figure3 shows the electrostatic potential of the proposed gate all around transistor, and it is found to be constant value at 0.3 V. Continuously varying the n and m terms in (4) has no impact on the potential as it remains constant along the insulator boundaries. This is totally in contrast to the results obtained in [15] where the potential is found to be linearly varying in the insulator boundaries. The constant potential has to be deduced as the resultant of the gate voltage applied symmetrically across the four sides of the transistor. The TCAD simulation of the device shows that the electrostatic potential is constant at 0.296 V. The simulation results are found to in acceptance with the TCAD results.Figure 3
Constant electrostatic potential obtained from the analytical solution of a gate-all-around silicon nanowire transistor is 0.3 V for different channel length with a height ofH=9 nm and channel width of W=9 nm. TCAD simulation shows that the potential is constant at 0.296 V.Figure4 represents the variation of total quantum integrated charge with the gate voltage. Equation (39) is used to obtain the integrated charge with only one energy level and one series term. It clearly shows that the decrease in the film thickness leads to the increase in the quantum threshold voltage which is actually due to the increase in energy quantization of the transistor. With the height and length of the device being constant, the width of the device is varied, and henceforth the variation of charge in accordance with the gate voltage is illustrated in Figure 4.Figure 4
Variation of quantum integrated charge at virtual source with gate voltage for different film widths where the height and length areH=9 nm, L=20 nm.The variation of quantum threshold voltage with width and height of the film at a channel length of 20 nm is shown in Figure5. The short channel effects tend to decrease along with the energy quantisation, and this can be further explained as a result of increase in the effective band gap of silicon due to quantum effects. The effect of confinement, expressed as the difference in the threshold voltage and its variation with the channel length L, is illustrated in Figure 6. The most important thing about this gate all around nanowire transistor is that any change in one of the dimensions can be nullified by proper tuning of other dimensions as the transistor is symmetric about its height and width.Figure 5
Variation of quantum threshold voltage with film height and width for channel length (L=20 nm).Figure 6
Variation of threshold voltage with film width for different height atL=20 nm.Figure7 shows the variation of the classical threshold voltage and quantum threshold voltage with the film height at a constant width of 9 nm. The value of the classical threshold voltage ranges from 0.27 V to 0.29 V for the corresponding changes in the film height. Similarly the quantum threshold voltage ranges from 0.3 V to 0.31 V. It shows that the device has a highly improved control over the threshold voltage. The TCAD results justify the simulation results.Figure 7
Variation of quantum and classical threshold voltage with film height. HereL=20 nm and W=9 nm.


## 5. Conclusion

In this paper, a quantum threshold voltage model for a GAA silicon nanowire transistor is proposed by solving the 3D Poisson and Schrodinger equations. Analytical expressions for potential and the inversion charge are expressed in their closed forms. The results show that the integrated charge and the threshold voltage calculated in accordance with the quantum effects of this proposed model are highly improved. The future considerations include deriving the I-V characteristics of the gate all around nanowire transistors and studying the impact of scaling on various device parameters. Finally, to conclude, this model provides an analytical and useful way for the threshold voltage evaluations in gate all around nanowire devices with a unified formalism employed in both classical and quantum mechanical approaches.



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