# Fully Programmable Gaussian Function Generator Using Floating Gate MOS Transistor

Authors: Richa Srivastava; Maneesha Gupta; Urvashi Singh
Journal: ISRN Electronics
 (2012)

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## Abstract

Floating gate MOS (FGMOS) based fully programmable Gaussian function generator is presented. The circuit combines the tunable property of FGMOS transistor, exponential characteristics of MOS transistor in weak inversion, and its square law characteristic in strong inversion region to implement the function. Two-quadrant current mode squarer is the core subcircuit of Gaussian function generator that helps to implement full Gaussian function for positive as well as negative input current. FGMOS implementation of the circuit reduces the current mismatching error and increases the tunability of the circuit. The performance of circuit is verified at 1.8 V in TSMC 0.18μm CMOS, BSIM3, and Level 49 technology by using Cadence Spectre simulator.


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## Body

## 1. Introduction

Gaussian function is one of the most widely used functions in many domains such as neural network, neural algorithm, and on-chip diffusion profile. Diffusion is one of the important steps in the chip fabrication. The diffusion profile of impurity atoms is dependent on the initial and boundary conditions. When a constant amount of dopant is deposited on the surface, the doping profile is approximated by Gaussian function [1]. Another application of Gaussian function is observed in multidimensional problems like pattern matching and data classifications [2]. These cases are calculated using probability density functions and these functions can be modeled by normal distributions [3].Madrinas et al. proposed a CMOS analog integrated circuit to implement Gaussian function [4]. They have successfully designed a five-transistor circuit in which current mirror is in weak inversion region and voltage variable resistors are replaced by two MOS transistors. But the conventional circuit has limitations of mismatching of MOS transistors and it can implement only half of the Gaussian function. The circuit proposed in [5] overcomes the limitations of the circuit proposed in [4] by using FGMOS transistors.Recently the work published in [6] implements the Gaussian functions using fourth-order approximation. The accuracy and complexity of this circuit depends upon order of approximation of the Gaussian function. So, there is always a tradeoff between circuit complexity and its accuracy.This paper presents very simple FGMOS based fully programmable Gaussian function generator that uses a single two-quadrant current mode squarer/divider to generate fully programmable Gaussian function.FGMOS has many attractive features for example it reduces the complexity of circuits and can simplify the signal processing chain of a design. It can shift the signal levels and incorporate tunable mechanisms. It can even work normally below the operational limits of supply voltage levels for a particular technology and thus consume less power than the minimum power required for a MOS circuit of same technology without affecting the performance of the device [7].The paper is organized as follows. Basics of FGMOS transistor is given in Section2. A fully programmable Gaussian function generator is introduced and analyzed in Section 3. Next section details the simulation results. Finally on the basis of simulation results, conclusions are drawn in the last section.


## 2. Basics of FGMOS Transistor

FGMOS is a multiple-input floating gate transistor whose threshold voltage can be controlled and tuned by the values of capacitors and bias voltage applied.The symbolic representation of two-input FGMOS transistor and its equivalent circuit are shown in Figure1. The input signal (V1) and bias voltage (Vb) are applied at gates G1 and G2 of FGMOS transistor, respectively.(a) Symbol of two-input floating gate and (b) its equivalent circuit [7].
(a)
(b)The voltage on floating gateVFG is given as [7–10]
(1)VFG=(QFG+CFGDVD+CFGSVss+CFGBVB+C1V1+C2Vb)CT,
where C1 and C2 are the capacitances associated with G1 and G2, CT=C1+C2+CFGS+CFGD+CFGB, is the total floating gate (FG) capacitance. CFGD, CFGS, and CFGB are the overlap capacitances of floating gate with drain, source, and bulk respectively, VD is the drain voltage, Vss is the source voltage, VB is the bulk voltage, and QFG is the residual charge.Since the floating gate of FGMOS does not have any connection to ground, so to avoid dc convergence error during simulation the model suggested by Yin et al. [11] has been used. The model is based on connecting resistors in parallel with the input capacitors as shown in Figure 2, where, Ri=1/kCi=1000GΩ.Figure 2
Simulation model for FGMOS [11].The drain current(ID) of the FGMOS transistor operating in ohmic region (source grounded) is given by [7]
(2)ID=β[{(C1CTV1+C2CTV2+CFGDCTVD)-VT}-VD2]VD,
where β is the transconductance parameter, C1 and C2 are the capacitances associated with G1 and G2, respectively, CT is the total floatinggate (FG) capacitance, and VT stands for the threshold voltage. Above equation can be simplified as
(3)ID=β(C1CT)[(V1-VT,eff)VD-CT2C1VD2],
where effective threshold voltage (VT,eff) is given by
(4)VT,eff=VT+C2C1(VT-Vb).
From (3), it is obvious that the reduction in VT,eff can be done by selecting Vb>VT and C2>C1.Hence,VT,eff is controllable and it is depending on the values of C1 and C2. The proposed Gaussian circuit utilizes this property of FGMOS transistor.


## 3. Proposed Gaussian Function Generator

Ifx is the input variable and y is the output, then the Gaussian function is defined by
(5)y=Ae-x2/2σ2,
where A, σ are the adjustable constants which define the amplitude and width of Gaussian function. In the proposed work the Gaussian function is constructed by first squaring the input variable x that is current by using the square law characteristic of MOS, secondly exponential characteristic of MOS in weak inversion is used to complete the transfer function as given in (5).Current mode squarer/divider used for full Gaussian function generation is shown in Figure3 [12]. The operation of the circuit will be based on square law characteristics if all the MOS transistors are biased in strong inversion region. The transistors M1 through M3 form the squarer part of the circuit. The drain currents ID1 and ID2 of M1 and M2 can be, respectively, given as [12]
(6)ID1=(4IB-Iin)16IB2for|Iin|≤4Ib,(7)ID2=(4IB-Iin)16IB2for|Iin|≤4Ib.Figure 3
Two-quadrant current mode squarer/divider [12].The total currentIout is given by
(8)Iout=Iin28IB+2IB.
From above equation, it can be seen that the output current consists of the squared input current Iin and dc current 2IB Thus if the dc current 2IB is compensated, a perfect squarer/divider circuit is obtained which can be used to realize many current mode analog processing circuits.The operating principle of conventional Gaussian circuit, proposed by Madrinas et al. is described in [4]. The MOSFETs M3 and M4 of the conventional circuit, shown in Figure 4, are working in linear region and behave as variable resistors.Figure 4
Conventional Gaussian circuit [4].In the proposed circuit, shown in Figure5, the MOS transistors M3 and M4 working in linear region are replaced by FGMOS transistors to increase tuning ability of the circuit and reduce mismatching error between transistor pair M3-M4. PMOS transistor M5 of the conventional (Figure 4) circuit is replaced by current squarer/divider to implement fully programmable Gaussian function.Figure 5
The proposed FGMOS based Gaussian circuit.Figure5 is the circuit implementation of FGMOS based Gaussian circuit.In the circuitVC and VB are the gate and bias voltages, respectively. The FGMOS transistors Mc and Md are working in their linear region. On neglecting CFGD, the drain current can be expressed by (if source is grounded)
(9)ID=β·VD[VF-VT-VD2],
where
(10)VF=C1CTVC+C2CTVB.
The control voltage VF controls the output conductances of Mc and Md, whose value is approximately given by
(11)gdsc,d≅βc,d(VF-VTc,d).
The condition for the linear operation is
(12)(VF-VT)≫VDc,d.
The effect of VF on output current and the Gaussian function is given by [4]
(13)I0=IRe-Iout/vTgdsd,
where IR is dc bias current of current mirror, vT is volt-thermal equivalent, and Iout is the output current of squarer/divider. On comparing (13) and (5) it can be seen that the width of Gaussian function can be controlled by varying the floating gate voltage VF. Since, VF depends upon both VC and VB, the width becomes more programmable. The performance of the Gaussian circuit depends upon the symmetry of the current mirror used. If there is mismatch between MOS Ma-Mb, their source voltages will be different and output current IO will not be equal to reference current IR, that is,
(14)ΔVS=IRgdsc-IOgdsd.
The difference source voltage can be zero if gdsc=gdsd. In the proposed circuit the tuning capability of FGMOS transistor helps to make gds3 and gds4 to be equal. Full implementation of the proposed circuit is shown in Figure 6.Figure 6
Proposed FGMOS based Gaussian circuit (complete).


## 4. Simulation Results

The designed circuits are simulated using Cadence Spectre simulator in TSMC 0.18 um CMOS technology using 1.8 V power supply.Simulation result for squarer/divider is shown in Figure7. The bias current (IB) for squarer/divider is 10μA and the input current (Iin) varies from −40μA to 40μA.Figure 7
Output current of squarer/divider.Figure8 shows the variation of output current (IO) with respect to input (Iin) and control voltage VC varying from 0.9 V to 1 V. It can be noticed from output waveforms (Figure 8) that width of the Gaussian function can be controlled by varying the control voltage VC. Figure 9 shows the power dissipated by the circuit at different values of input current Iin. It can be seen that the circuit has power dissipation of 0.1 mW at the input current of 10 μA. Table 1 summarizes the aspect ratio of the MOS used in the proposed circuit. Table 2 shows the output current relative error defined as
(15)Er=(IO-IR)IR×100%
for different values of control voltage VC. It can be seen that percentage error is zero for VC=0.95 V.Table 1
Aspect ratio of transistors of Figure6.
Transistor
W
(μm)
L
(μm)
M1–M3, M4, M6
0.54
0.18
M5
3.6
0.18
M7–M10
1.44
0.18
Ma–Md
0.4
0.18Table 2
Output current relative error for different values ofVC at IR = 1 μA.
I
R (μA)
1
V
C (V)
0.85
0.9
0.95
1
E
r (%)
−3
−1
0
2Figure 8
Variation of output current with respect toIin at different value of control voltage VC.Figure 9
Variation of output power with respect to input current.Table3 gives the performance parameters of the proposed circuit. It can be seen that circuit has the total noise of 1.6441e−14 V2/Hz at the frequency of 100 kHz. The complexity of the circuit is also low as compared to other circuits implementing full Gaussian function.Table 3
Performance parameters of  the proposed circuit.
Parameters
Simulated results
Supply voltage (V)
1.8
Input current (Iin) range (μA)
−100 to 100
Power dissipated (mW) (atIin= 10 μA)
0.1
Total noise (V2/Hz)
1.6441
e
-
14
No. of transistor
14


## 5. Conclusion

In this paper FGMOS based fully programmable Gaussian circuit has been proposed which utilizes the advantages of FGMOS transistor for better tuning ability and low mismatching error between the MOS pair. The proposed circuit uses two-quadrant square/divider to implement full Gaussian function. Complexity and power dissipation of the circuit are very low. Thus the newly developed Gaussian circuit is the best choice for highly accurate and low power applications of Gaussian function.



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*Source: 148492-2012-11-20.xml*